VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 19607

Last change on this file since 19607 was 19607, checked in by vboxsync, 16 years ago

ACPI: increased maximum nr of supported VCPUs to 16; we should reconsider the way we build the table
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1/* $Id: DevACPI.cpp 19607 2009-05-12 11:31:14Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_ACPI
26#include <VBox/pdmdev.h>
27#include <VBox/pgm.h>
28#include <VBox/log.h>
29#include <VBox/param.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35#endif /* IN_RING3 */
36
37#include "../Builtins.h"
38
39#ifdef LOG_ENABLED
40# define DEBUG_ACPI
41#endif
42
43/* the compiled DSL */
44#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
45# include <vboxaml.hex>
46#endif /* !IN_RING3 */
47
48
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53#define DEBUG_HEX 0x3000
54#define DEBUG_CHR 0x3001
55
56#define PM_TMR_FREQ 3579545
57#define PM1a_EVT_BLK 0x00004000
58#define PM1b_EVT_BLK 0x00000000 /**< not supported */
59#define PM1a_CTL_BLK 0x00004004
60#define PM1b_CTL_BLK 0x00000000 /**< not supported */
61#define PM2_CTL_BLK 0x00000000 /**< not supported */
62#define PM_TMR_BLK 0x00004008
63#define GPE0_BLK 0x00004020
64#define GPE1_BLK 0x00000000 /**< not supported */
65#define BAT_INDEX 0x00004040
66#define BAT_DATA 0x00004044
67#define SYSI_INDEX 0x00004048
68#define SYSI_DATA 0x0000404c
69#define ACPI_RESET_BLK 0x00004050
70
71/* PM1x status register bits */
72#define TMR_STS RT_BIT(0)
73#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
74#define BM_STS RT_BIT(4)
75#define GBL_STS RT_BIT(5)
76#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
77#define PWRBTN_STS RT_BIT(8)
78#define SLPBTN_STS RT_BIT(9)
79#define RTC_STS RT_BIT(10)
80#define IGN_STS RT_BIT(11)
81#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
82#define WAK_STS RT_BIT(15)
83#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
84
85/* PM1x enable register bits */
86#define TMR_EN RT_BIT(0)
87#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
88#define GBL_EN RT_BIT(5)
89#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
90#define PWRBTN_EN RT_BIT(8)
91#define SLPBTN_EN RT_BIT(9)
92#define RTC_EN RT_BIT(10)
93#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
94#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
95#define IGN_EN 0
96
97/* PM1x control register bits */
98#define SCI_EN RT_BIT(0)
99#define BM_RLD RT_BIT(1)
100#define GBL_RLS RT_BIT(2)
101#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
102#define IGN_CNT RT_BIT(9)
103#define SLP_TYPx_SHIFT 10
104#define SLP_TYPx_MASK 7
105#define SLP_EN RT_BIT(13)
106#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
107#define RSR_CNT (RSR1_CNT | RSR2_CNT)
108
109#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
110
111enum
112{
113 BAT_STATUS_STATE = 0x00, /**< BST battery state */
114 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
115 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
116 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
117 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
118 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
119 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
120 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
121 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
122 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
123 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
124 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
125 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
126 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
127 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
128 BAT_INDEX_LAST
129};
130
131enum
132{
133 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
134 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
135 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
136 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
137 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
138 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
139 SYSTEM_INFO_INDEX_CPU1_STATUS = 6,
140 SYSTEM_INFO_INDEX_CPU2_STATUS = 7,
141 SYSTEM_INFO_INDEX_CPU3_STATUS = 8,
142 SYSTEM_INFO_INDEX_CPU4_STATUS = 9,
143 SYSTEM_INFO_INDEX_CPU5_STATUS = 10,
144 SYSTEM_INFO_INDEX_CPU6_STATUS = 11,
145 SYSTEM_INFO_INDEX_CPU7_STATUS = 12,
146 SYSTEM_INFO_INDEX_CPU8_STATUS = 13,
147 SYSTEM_INFO_INDEX_CPU9_STATUS = 14,
148 SYSTEM_INFO_INDEX_CPUA_STATUS = 15,
149 SYSTEM_INFO_INDEX_CPUB_STATUS = 16,
150 SYSTEM_INFO_INDEX_CPUC_STATUS = 17,
151 SYSTEM_INFO_INDEX_CPUD_STATUS = 18,
152 SYSTEM_INFO_INDEX_CPUE_STATUS = 19,
153 SYSTEM_INFO_INDEX_CPUF_STATUS = 20,
154 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 21,
155 SYSTEM_INFO_INDEX_RTC_STATUS = 22,
156 SYSTEM_INFO_INDEX_END = 23,
157 SYSTEM_INFO_INDEX_INVALID = 0x80,
158 SYSTEM_INFO_INDEX_VALID = 0x200
159};
160
161#define AC_OFFLINE 0
162#define AC_ONLINE 1
163
164#define BAT_TECH_PRIMARY 1
165#define BAT_TECH_SECONDARY 2
166
167#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
168#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
169#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
170#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
171#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
172
173
174/*******************************************************************************
175* Structures and Typedefs *
176*******************************************************************************/
177/**
178 * The ACPI device state.
179 */
180typedef struct ACPIState
181{
182 PCIDevice dev;
183 uint16_t pm1a_en;
184 uint16_t pm1a_sts;
185 uint16_t pm1a_ctl;
186 /** Number of logical CPUs in guest */
187 uint16_t cCpus;
188 int64_t pm_timer_initial;
189 PTMTIMERR3 tsR3;
190 PTMTIMERR0 tsR0;
191 PTMTIMERRC tsRC;
192
193 uint32_t gpe0_en;
194 uint32_t gpe0_sts;
195
196 unsigned int uBatteryIndex;
197 uint32_t au8BatteryInfo[13];
198
199 unsigned int uSystemInfoIndex;
200 uint64_t u64RamSize;
201 /** The number of bytes above 4GB. */
202 uint64_t cbRamHigh;
203 /** The number of bytes below 4GB. */
204 uint32_t cbRamLow;
205
206 /** Current ACPI S* state. We support S0 and S5 */
207 uint32_t uSleepState;
208 uint8_t au8RSDPPage[0x1000];
209 /** This is a workaround for incorrect index field handling by Intels ACPICA.
210 * The system info _INI method writes to offset 0x200. We either observe a
211 * write request to index 0x80 (in that case we don't change the index) or a
212 * write request to offset 0x200 (in that case we divide the index value by
213 * 4. Note that the _STA method is sometimes called prior to the _INI method
214 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
215 * acpiBatIndexWrite() for handling this. */
216 uint8_t u8IndexShift;
217 /** provide an I/O-APIC */
218 uint8_t u8UseIOApic;
219 /** provide a floppy controller */
220 bool fUseFdc;
221 /** If High Precision Event Timer device should be supported */
222 bool fUseHpet;
223 /** If System Management Controller device should be supported */
224 bool fUseSmc;
225 /** the guest handled the last power button event */
226 bool fPowerButtonHandled;
227 /** If ACPI CPU device should be shown */
228 bool fShowCpu;
229 /** If Real Time Clock ACPI object to be shown */
230 bool fShowRtc;
231 /** Aligning IBase. */
232 bool afAlignment[5];
233
234 /** ACPI port base interface. */
235 PDMIBASE IBase;
236 /** ACPI port interface. */
237 PDMIACPIPORT IACPIPort;
238 /** Pointer to the device instance. */
239 PPDMDEVINSR3 pDevIns;
240 /** Pointer to the driver base interface */
241 R3PTRTYPE(PPDMIBASE) pDrvBase;
242 /** Pointer to the driver connector interface */
243 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
244} ACPIState;
245
246#pragma pack(1)
247
248/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
249struct ACPIGENADDR
250{
251 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
252 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
253 uint8_t u8RegisterBitOffset; /**< bit offset of register */
254 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
255 uint64_t u64Address; /**< 64-bit address of register */
256};
257AssertCompileSize(ACPIGENADDR, 12);
258
259/** Root System Description Pointer */
260struct ACPITBLRSDP
261{
262 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
263 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
264 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
265 uint8_t u8Revision; /**< revision number, currently 2 */
266#define ACPI_REVISION 2 /**< ACPI 3.0 */
267 uint32_t u32RSDT; /**< phys addr of RSDT */
268 uint32_t u32Length; /**< bytes of this table */
269 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
270 uint8_t u8ExtChecksum; /**< checksum of entire table */
271 uint8_t u8Reserved[3]; /**< reserved */
272};
273AssertCompileSize(ACPITBLRSDP, 36);
274
275/** System Description Table Header */
276struct ACPITBLHEADER
277{
278 uint8_t au8Signature[4]; /**< table identifier */
279 uint32_t u32Length; /**< length of the table including header */
280 uint8_t u8Revision; /**< revision number */
281 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
282 uint8_t au8OemId[6]; /**< OEM-supplied string */
283 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
284 uint32_t u32OemRevision; /**< OEM-supplied revision number */
285 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
286 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
287};
288AssertCompileSize(ACPITBLHEADER, 36);
289
290/** Root System Description Table */
291struct ACPITBLRSDT
292{
293 ACPITBLHEADER header;
294 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
295};
296AssertCompileSize(ACPITBLRSDT, 40);
297
298/** Extended System Description Table */
299struct ACPITBLXSDT
300{
301 ACPITBLHEADER header;
302 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
303};
304AssertCompileSize(ACPITBLXSDT, 44);
305
306/** Fixed ACPI Description Table */
307struct ACPITBLFADT
308{
309 ACPITBLHEADER header;
310 uint32_t u32FACS; /**< phys. address of FACS */
311 uint32_t u32DSDT; /**< phys. address of DSDT */
312 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
313#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
314#define INT_MODEL_MULTIPLE_APIC 2
315 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
316 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
317#define SCI_INT 9
318 uint32_t u32SMICmd; /**< system port address of SMI command port */
319#define SMI_CMD 0x0000442e
320 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
321#define ACPI_ENABLE 0xa1
322 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
323#define ACPI_DISABLE 0xa0
324 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
325 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
326 state control responsibility */
327 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
328 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
329 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
330 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
331 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
332 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
333 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
334 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
335 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
336 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
337 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
338 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
339 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
340#define GPE0_BLK_LEN 2
341 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
342#define GPE1_BLK_LEN 0
343 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
344#define GPE1_BASE 0
345 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
346 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
347#define P_LVL2_LAT 101 /**< C2 state not supported */
348 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
349#define P_LVL3_LAT 1001 /**< C3 state not supported */
350 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
351 lines from any processors memory caches */
352#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
353 uint16_t u16FlushStride; /**< cache line width */
354#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
355 uint8_t u8DutyOffset;
356 uint8_t u8DutyWidth;
357 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
358 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
359 uint8_t u8Century; /**< RTC CMOS RAM index of century */
360 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
361#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
362 (COM too?) */
363#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
364#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
365 uint8_t u8Must0_0; /**< must be 0 */
366 uint32_t u32Flags; /**< fixed feature flags */
367#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
368#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
369#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
370#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
371#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
372#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
373#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
374#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
375#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
376#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
377#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
378#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
379#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
380#define FADT_FL_CPU_SW_SLP RT_BIT(13)
381#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
382#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
383#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
384#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
385#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
386#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
387 ACPIGENADDR ResetReg; /**< ext addr of reset register */
388 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
389#define ACPI_RESET_REG_VAL 0x10
390 uint8_t au8Must0_1[3]; /**< must be 0 */
391 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
392 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
393 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
394 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
395 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
396 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
397 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
398 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
399 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
400 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
401};
402AssertCompileSize(ACPITBLFADT, 244);
403
404/** Firmware ACPI Control Structure */
405struct ACPITBLFACS
406{
407 uint8_t au8Signature[4]; /**< 'FACS' */
408 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
409 uint32_t u32HWSignature; /**< systems HW signature at last boot */
410 uint32_t u32FWVector; /**< address of waking vector */
411 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
412 uint32_t u32Flags; /**< FACS flags */
413 uint64_t u64X_FWVector; /**< 64-bit waking vector */
414 uint8_t u8Version; /**< version of this table */
415 uint8_t au8Reserved[31]; /**< zero */
416};
417AssertCompileSize(ACPITBLFACS, 64);
418
419/** Processor Local APIC Structure */
420struct ACPITBLLAPIC
421{
422 uint8_t u8Type; /**< 0 = LAPIC */
423 uint8_t u8Length; /**< 8 */
424 uint8_t u8ProcId; /**< processor ID */
425 uint8_t u8ApicId; /**< local APIC ID */
426 uint32_t u32Flags; /**< Flags */
427#define LAPIC_ENABLED 0x1
428};
429AssertCompileSize(ACPITBLLAPIC, 8);
430
431/** I/O APIC Structure */
432struct ACPITBLIOAPIC
433{
434 uint8_t u8Type; /**< 1 == I/O APIC */
435 uint8_t u8Length; /**< 12 */
436 uint8_t u8IOApicId; /**< I/O APIC ID */
437 uint8_t u8Reserved; /**< 0 */
438 uint32_t u32Address; /**< phys address to access I/O APIC */
439 uint32_t u32GSIB; /**< global system interrupt number to start */
440};
441AssertCompileSize(ACPITBLIOAPIC, 12);
442
443# ifdef IN_RING3 /**@todo r=bird: Move this down to where it's used. */
444
445# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
446
447/**
448 * Multiple APIC Description Table.
449 *
450 * This structure looks somewhat convoluted due layout of MADT table in MP case.
451 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
452 * use regular C structure and proxy to raw memory instead.
453 */
454class AcpiTableMADT
455{
456 /**
457 * All actual data stored in dynamically allocated memory pointed by this field.
458 */
459 uint8_t *m_pbData;
460 /**
461 * Number of CPU entries in this MADT.
462 */
463 uint32_t m_cCpus;
464
465public:
466 /**
467 * Address of ACPI header
468 */
469 inline ACPITBLHEADER *header_addr(void) const
470 {
471 return (ACPITBLHEADER *)m_pbData;
472 }
473
474 /**
475 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
476 * although address is the same for all of them.
477 */
478 inline uint32_t *u32LAPIC_addr(void) const
479 {
480 return (uint32_t *)(header_addr() + 1);
481 }
482
483 /**
484 * Address of APIC flags
485 */
486 inline uint32_t *u32Flags_addr(void) const
487 {
488 return (uint32_t *)(u32LAPIC_addr() + 1);
489 }
490
491 /**
492 * Address of per-CPU LAPIC descriptions
493 */
494 inline ACPITBLLAPIC *LApics_addr(void) const
495 {
496 return (ACPITBLLAPIC *)(u32Flags_addr() + 1);
497 }
498
499 /**
500 * Address of IO APIC description
501 */
502 inline ACPITBLIOAPIC *IOApic_addr(void) const
503 {
504 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
505 }
506
507 /**
508 * Size of MADT.
509 * Note that this function assumes IOApic to be the last field in structure.
510 */
511 inline uint32_t size(void) const
512 {
513 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
514 }
515
516 /**
517 * Raw data of MADT.
518 */
519 inline const uint8_t *data(void) const
520 {
521 return m_pbData;
522 }
523
524 /**
525 * Size of MADT for given ACPI config, useful to compute layout.
526 */
527 static uint32_t sizeFor(ACPIState *s)
528 {
529 return AcpiTableMADT(s->cCpus).size();
530 }
531
532 /*
533 * Constructor, only works in Ring 3, doesn't look like a big deal.
534 */
535 AcpiTableMADT(uint32_t cCpus)
536 {
537 m_cCpus = cCpus;
538 uint32_t cb = size();
539 m_pbData = (uint8_t *)RTMemAllocZ(cb);
540 }
541
542 ~AcpiTableMADT()
543 {
544 RTMemFree(m_pbData);
545 }
546};
547# endif /* IN_RING3 */
548
549#pragma pack()
550
551
552#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
553/*******************************************************************************
554* Internal Functions *
555*******************************************************************************/
556__BEGIN_DECLS
557PDMBOTHCBDECL(int) acpiPMTmrRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
558#ifdef IN_RING3
559PDMBOTHCBDECL(int) acpiPm1aEnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
560PDMBOTHCBDECL(int) acpiPM1aEnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
561PDMBOTHCBDECL(int) acpiPm1aStsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
562PDMBOTHCBDECL(int) acpiPM1aStsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
563PDMBOTHCBDECL(int) acpiPm1aCtlRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
564PDMBOTHCBDECL(int) acpiPM1aCtlWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
565PDMBOTHCBDECL(int) acpiSmiWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
566PDMBOTHCBDECL(int) acpiBatIndexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
567PDMBOTHCBDECL(int) acpiBatDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
568PDMBOTHCBDECL(int) acpiSysInfoDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
569PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
570PDMBOTHCBDECL(int) acpiGpe0EnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
571PDMBOTHCBDECL(int) acpiGpe0EnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
572PDMBOTHCBDECL(int) acpiGpe0StsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
573PDMBOTHCBDECL(int) acpiGpe0StsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
574PDMBOTHCBDECL(int) acpiResetWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
575# ifdef DEBUG_ACPI
576PDMBOTHCBDECL(int) acpiDhexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
577PDMBOTHCBDECL(int) acpiDchrWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
578# endif
579#endif /* IN_RING3 */
580__END_DECLS
581
582
583#ifdef IN_RING3
584
585/* Simple acpiChecksum: all the bytes must add up to 0. */
586static uint8_t acpiChecksum(const uint8_t * const data, size_t len)
587{
588 uint8_t sum = 0;
589 for (size_t i = 0; i < len; ++i)
590 sum += data[i];
591 return -sum;
592}
593
594static void acpiPrepareHeader(ACPITBLHEADER *header, const char au8Signature[4],
595 uint32_t u32Length, uint8_t u8Revision)
596{
597 memcpy(header->au8Signature, au8Signature, 4);
598 header->u32Length = RT_H2LE_U32(u32Length);
599 header->u8Revision = u8Revision;
600 memcpy(header->au8OemId, "VBOX ", 6);
601 memcpy(header->au8OemTabId, "VBOX", 4);
602 memcpy(header->au8OemTabId+4, au8Signature, 4);
603 header->u32OemRevision = RT_H2LE_U32(1);
604 memcpy(header->au8CreatorId, "ASL ", 4);
605 header->u32CreatorRev = RT_H2LE_U32(0x61);
606}
607
608static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
609 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
610 uint8_t u8AccessSize, uint64_t u64Address)
611{
612 g->u8AddressSpaceId = u8AddressSpaceId;
613 g->u8RegisterBitWidth = u8RegisterBitWidth;
614 g->u8RegisterBitOffset = u8RegisterBitOffset;
615 g->u8AccessSize = u8AccessSize;
616 g->u64Address = RT_H2LE_U64(u64Address);
617}
618
619static void acpiPhyscpy(ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
620{
621 PDMDevHlpPhysWrite(s->pDevIns, dst, src, size);
622}
623
624/** Differentiated System Description Table (DSDT) */
625static void acpiSetupDSDT(ACPIState *s, RTGCPHYS32 addr)
626{
627 acpiPhyscpy(s, addr, AmlCode, sizeof(AmlCode));
628}
629
630/** Firmware ACPI Control Structure (FACS) */
631static void acpiSetupFACS(ACPIState *s, RTGCPHYS32 addr)
632{
633 ACPITBLFACS facs;
634
635 memset(&facs, 0, sizeof(facs));
636 memcpy(facs.au8Signature, "FACS", 4);
637 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
638 facs.u32HWSignature = RT_H2LE_U32(0);
639 facs.u32FWVector = RT_H2LE_U32(0);
640 facs.u32GlobalLock = RT_H2LE_U32(0);
641 facs.u32Flags = RT_H2LE_U32(0);
642 facs.u64X_FWVector = RT_H2LE_U64(0);
643 facs.u8Version = 1;
644
645 acpiPhyscpy(s, addr, (const uint8_t *)&facs, sizeof(facs));
646}
647
648/** Fixed ACPI Description Table (FADT aka FACP) */
649static void acpiSetupFADT(ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
650{
651 ACPITBLFADT fadt;
652
653 memset(&fadt, 0, sizeof(fadt));
654 acpiPrepareHeader(&fadt.header, "FACP", sizeof(fadt), 4);
655 fadt.u32FACS = RT_H2LE_U32(facs_addr);
656 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
657 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
658 fadt.u8PreferredPMProfile = 0; /* unspecified */
659 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
660 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
661 fadt.u8AcpiEnable = ACPI_ENABLE;
662 fadt.u8AcpiDisable = ACPI_DISABLE;
663 fadt.u8S4BIOSReq = 0;
664 fadt.u8PStateCnt = 0;
665 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
666 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
667 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
668 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
669 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
670 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
671 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
672 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
673 fadt.u8PM1EVTLEN = 4;
674 fadt.u8PM1CTLLEN = 2;
675 fadt.u8PM2CTLLEN = 0;
676 fadt.u8PMTMLEN = 4;
677 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
678 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
679 fadt.u8GPE1BASE = GPE1_BASE;
680 fadt.u8CSTCNT = 0;
681 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
682 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
683 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
684 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
685 fadt.u8DutyOffset = 0;
686 fadt.u8DutyWidth = 0;
687 fadt.u8DayAlarm = 0;
688 fadt.u8MonAlarm = 0;
689 fadt.u8Century = 0;
690 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
691 /** @note WBINVD is required for ACPI versions newer than 1.0 */
692 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
693 | FADT_FL_FIX_RTC
694 | FADT_FL_TMR_VAL_EXT);
695 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
696 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
697 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
698 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
699 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
700 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
701 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
702 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
703 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
704 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
705 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
706 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
707 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, sizeof(fadt));
708 acpiPhyscpy(s, addr, &fadt, sizeof(fadt));
709}
710
711/**
712 * Root System Description Table.
713 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
714 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
715 */
716static int acpiSetupRSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
717{
718 ACPITBLRSDT *rsdt;
719 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
720
721 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
722 if (!rsdt)
723 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
724
725 acpiPrepareHeader(&rsdt->header, "RSDT", (uint32_t)size, 1);
726 for (unsigned int i = 0; i < nb_entries; ++i)
727 {
728 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
729 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
730 }
731 rsdt->header.u8Checksum = acpiChecksum((uint8_t*)rsdt, size);
732 acpiPhyscpy(s, addr, rsdt, size);
733 RTMemFree(rsdt);
734 return VINF_SUCCESS;
735}
736
737/** Extended System Description Table. */
738static int acpiSetupXSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
739{
740 ACPITBLXSDT *xsdt;
741 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
742
743 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
744 if (!xsdt)
745 return VERR_NO_TMP_MEMORY;
746
747 acpiPrepareHeader(&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
748 for (unsigned int i = 0; i < nb_entries; ++i)
749 {
750 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
751 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
752 }
753 xsdt->header.u8Checksum = acpiChecksum((uint8_t*)xsdt, size);
754 acpiPhyscpy(s, addr, xsdt, size);
755 RTMemFree(xsdt);
756 return VINF_SUCCESS;
757}
758
759/** Root System Description Pointer (RSDP) */
760static void acpiSetupRSDP(ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
761{
762 memset(rsdp, 0, sizeof(*rsdp));
763
764 /* ACPI 1.0 part (RSDT */
765 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
766 memcpy(rsdp->au8OemId, "VBOX ", 6);
767 rsdp->u8Revision = ACPI_REVISION;
768 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
769 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
770
771 /* ACPI 2.0 part (XSDT) */
772 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
773 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
774 rsdp->u8ExtChecksum = acpiChecksum((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
775}
776
777/**
778 * Multiple APIC Description Table.
779 *
780 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both
781 *
782 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
783 */
784static void acpiSetupMADT(ACPIState *s, RTGCPHYS32 addr)
785{
786 uint16_t cpus = s->cCpus;
787 AcpiTableMADT madt(cpus);
788
789 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
790
791 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
792 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
793
794 ACPITBLLAPIC* lapic = madt.LApics_addr();
795 for (uint16_t i = 0; i < cpus; i++)
796 {
797 lapic->u8Type = 0;
798 lapic->u8Length = sizeof(ACPITBLLAPIC);
799 lapic->u8ProcId = i;
800 lapic->u8ApicId = i;
801 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
802 lapic++;
803 }
804
805 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
806
807 ioapic->u8Type = 1;
808 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
809 ioapic->u8IOApicId = cpus;
810 ioapic->u8Reserved = 0;
811 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
812 ioapic->u32GSIB = RT_H2LE_U32(0);
813
814 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
815 acpiPhyscpy(s, addr, madt.data(), madt.size());
816}
817
818/* SCI IRQ */
819DECLINLINE(void) acpiSetIrq(ACPIState *s, int level)
820{
821 if (s->pm1a_ctl & SCI_EN)
822 PDMDevHlpPCISetIrq(s->pDevIns, -1, level);
823}
824
825DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
826{
827 return en & ~(RSR_EN | IGN_EN);
828}
829
830DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
831{
832 return sts & ~(RSR_STS | IGN_STS);
833}
834
835DECLINLINE(int) pm1a_level(ACPIState *s)
836{
837 return (pm1a_pure_en(s->pm1a_en) & pm1a_pure_sts(s->pm1a_sts)) != 0;
838}
839
840DECLINLINE(int) gpe0_level(ACPIState *s)
841{
842 return (s->gpe0_en & s->gpe0_sts) != 0;
843}
844
845static void update_pm1a(ACPIState *s, uint32_t sts, uint32_t en)
846{
847 int old_level, new_level;
848
849 if (gpe0_level(s))
850 return;
851
852 old_level = pm1a_level(s);
853 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
854
855 s->pm1a_en = en;
856 s->pm1a_sts = sts;
857
858 if (new_level != old_level)
859 acpiSetIrq(s, new_level);
860}
861
862static void update_gpe0(ACPIState *s, uint32_t sts, uint32_t en)
863{
864 int old_level, new_level;
865
866 if (pm1a_level(s))
867 return;
868
869 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
870 new_level = (en & sts) != 0;
871
872 s->gpe0_en = en;
873 s->gpe0_sts = sts;
874
875 if (new_level != old_level)
876 acpiSetIrq(s, new_level);
877}
878
879static int acpiPowerDown(ACPIState *s)
880{
881 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
882 if (RT_FAILURE(rc))
883 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
884 return rc;
885}
886
887/** Converts a ACPI port interface pointer to an ACPI state pointer. */
888#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
889
890/**
891 * Send an ACPI power off event.
892 *
893 * @returns VBox status code
894 * @param pInterface Pointer to the interface structure containing the called function pointer.
895 */
896static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
897{
898 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
899 s->fPowerButtonHandled = false;
900 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
901 return VINF_SUCCESS;
902}
903
904/**
905 * Check if the ACPI power button event was handled.
906 *
907 * @returns VBox status code
908 * @param pInterface Pointer to the interface structure containing the called function pointer.
909 * @param pfHandled Return true if the power button event was handled by the guest.
910 */
911static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
912{
913 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
914 *pfHandled = s->fPowerButtonHandled;
915 return VINF_SUCCESS;
916}
917
918/**
919 * Check if the Guest entered into G0 (working) or G1 (sleeping).
920 *
921 * @returns VBox status code
922 * @param pInterface Pointer to the interface structure containing the called function pointer.
923 * @param pfEntered Return true if the guest entered the ACPI mode.
924 */
925static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
926{
927 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
928 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
929 return VINF_SUCCESS;
930}
931
932/**
933 * Send an ACPI sleep button event.
934 *
935 * @returns VBox status code
936 * @param pInterface Pointer to the interface structure containing the called function pointer.
937 */
938static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
939{
940 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
941 update_pm1a(s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
942 return VINF_SUCCESS;
943}
944
945/* PM1a_EVT_BLK enable */
946static uint32_t acpiPm1aEnReadw(ACPIState *s, uint32_t addr)
947{
948 uint16_t val = s->pm1a_en;
949 Log(("acpi: acpiPm1aEnReadw -> %#x\n", val));
950 return val;
951}
952
953static void acpiPM1aEnWritew(ACPIState *s, uint32_t addr, uint32_t val)
954{
955 Log(("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
956 val &= ~(RSR_EN | IGN_EN);
957 update_pm1a(s, s->pm1a_sts, val);
958}
959
960/* PM1a_EVT_BLK status */
961static uint32_t acpiPm1aStsReadw(ACPIState *s, uint32_t addr)
962{
963 uint16_t val = s->pm1a_sts;
964 Log(("acpi: acpiPm1aStsReadw -> %#x\n", val));
965 return val;
966}
967
968static void acpiPM1aStsWritew(ACPIState *s, uint32_t addr, uint32_t val)
969{
970 Log(("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
971 if (val & PWRBTN_STS)
972 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
973 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
974 update_pm1a(s, val, s->pm1a_en);
975}
976
977/* PM1a_CTL_BLK */
978static uint32_t acpiPm1aCtlReadw(ACPIState *s, uint32_t addr)
979{
980 uint16_t val = s->pm1a_ctl;
981 Log(("acpi: acpiPm1aCtlReadw -> %#x\n", val));
982 return val;
983}
984
985static int acpiPM1aCtlWritew(ACPIState *s, uint32_t addr, uint32_t val)
986{
987 uint32_t uSleepState;
988
989 Log(("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
990 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
991
992 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
993 if (uSleepState != s->uSleepState)
994 {
995 s->uSleepState = uSleepState;
996 switch (uSleepState)
997 {
998 case 0x00: /* S0 */
999 break;
1000 case 0x05: /* S5 */
1001 LogRel(("Entering S5 (power down)\n"));
1002 return acpiPowerDown(s);
1003 default:
1004 AssertMsgFailed(("Unknown sleep state %#x\n", uSleepState));
1005 break;
1006 }
1007 }
1008 return VINF_SUCCESS;
1009}
1010
1011/* GPE0_BLK */
1012static uint32_t acpiGpe0EnReadb(ACPIState *s, uint32_t addr)
1013{
1014 uint8_t val = s->gpe0_en;
1015 Log(("acpi: acpiGpe0EnReadl -> %#x\n", val));
1016 return val;
1017}
1018
1019static void acpiGpe0EnWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1020{
1021 Log(("acpi: acpiGpe0EnWritel <- %#x\n", val));
1022 update_gpe0(s, s->gpe0_sts, val);
1023}
1024
1025static uint32_t acpiGpe0StsReadb(ACPIState *s, uint32_t addr)
1026{
1027 uint8_t val = s->gpe0_sts;
1028 Log(("acpi: acpiGpe0StsReadl -> %#x\n", val));
1029 return val;
1030}
1031
1032static void acpiGpe0StsWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1033{
1034 val = s->gpe0_sts & ~val;
1035 update_gpe0(s, val, s->gpe0_en);
1036 Log(("acpi: acpiGpe0StsWritel <- %#x\n", val));
1037}
1038
1039static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1040{
1041 int rc = VINF_SUCCESS;
1042
1043 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1044 if (val == ACPI_RESET_REG_VAL)
1045 {
1046# ifndef IN_RING3
1047 rc = VINF_IOM_HC_IOPORT_WRITE;
1048# else /* IN_RING3 */
1049 rc = PDMDevHlpVMReset(s->pDevIns);
1050# endif /* !IN_RING3 */
1051 }
1052 return rc;
1053}
1054
1055/* SMI */
1056static void acpiSmiWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1057{
1058 Log(("acpi: acpiSmiWriteU8 %#x\n", val));
1059 if (val == ACPI_ENABLE)
1060 s->pm1a_ctl |= SCI_EN;
1061 else if (val == ACPI_DISABLE)
1062 s->pm1a_ctl &= ~SCI_EN;
1063 else
1064 Log(("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1065}
1066
1067static uint32_t find_rsdp_space(void)
1068{
1069 return 0xe0000;
1070}
1071
1072static void acpiPMTimerReset(ACPIState *s)
1073{
1074 uint64_t interval, freq;
1075
1076 freq = TMTimerGetFreq(s->CTX_SUFF(ts));
1077 interval = ASMMultU64ByU32DivByU32(0xffffffff, freq, PM_TMR_FREQ);
1078 Log(("interval = %RU64\n", interval));
1079 TMTimerSet(s->CTX_SUFF(ts), TMTimerGet(s->CTX_SUFF(ts)) + interval);
1080}
1081
1082static DECLCALLBACK(void) acpiTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1083{
1084 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1085
1086 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1087 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1088 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1089
1090 update_pm1a(s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1091 acpiPMTimerReset(s);
1092}
1093
1094/**
1095 * _BST method.
1096 */
1097static void acpiFetchBatteryStatus(ACPIState *s)
1098{
1099 uint32_t *p = s->au8BatteryInfo;
1100 bool fPresent; /* battery present? */
1101 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1102 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1103 uint32_t hostPresentRate; /* 0..1000 */
1104 int rc;
1105
1106 if (!s->pDrv)
1107 return;
1108 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1109 &hostBatteryState, &hostPresentRate);
1110 AssertRC(rc);
1111
1112 /* default values */
1113 p[BAT_STATUS_STATE] = hostBatteryState;
1114 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1115 : hostPresentRate * 50; /* mW */
1116 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1117 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1118
1119 /* did we get a valid battery state? */
1120 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1121 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1122 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1123 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1124}
1125
1126/**
1127 * _BIF method.
1128 */
1129static void acpiFetchBatteryInfo(ACPIState *s)
1130{
1131 uint32_t *p = s->au8BatteryInfo;
1132
1133 p[BAT_INFO_UNITS] = 0; /* mWh */
1134 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1135 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1136 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1137 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1138 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1139 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1140 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1141 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1142}
1143
1144/**
1145 * _STA method.
1146 */
1147static uint32_t acpiGetBatteryDeviceStatus(ACPIState *s)
1148{
1149 bool fPresent; /* battery present? */
1150 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1151 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1152 uint32_t hostPresentRate; /* 0..1000 */
1153 int rc;
1154
1155 if (!s->pDrv)
1156 return 0;
1157 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1158 &hostBatteryState, &hostPresentRate);
1159 AssertRC(rc);
1160
1161 return fPresent
1162 ? STA_DEVICE_PRESENT_MASK /* present */
1163 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1164 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1165 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1166 | STA_BATTERY_PRESENT_MASK /* battery is present */
1167 : 0; /* device not present */
1168}
1169
1170static uint32_t acpiGetPowerSource(ACPIState *s)
1171{
1172 PDMACPIPOWERSOURCE ps;
1173
1174 /* query the current power source from the host driver */
1175 if (!s->pDrv)
1176 return AC_ONLINE;
1177 int rc = s->pDrv->pfnQueryPowerSource(s->pDrv, &ps);
1178 AssertRC(rc);
1179 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1180}
1181
1182PDMBOTHCBDECL(int) acpiBatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1183{
1184 ACPIState *s = (ACPIState *)pvUser;
1185
1186 switch (cb)
1187 {
1188 case 4:
1189 u32 >>= s->u8IndexShift;
1190 /* see comment at the declaration of u8IndexShift */
1191 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1192 {
1193 s->u8IndexShift = 2;
1194 u32 >>= 2;
1195 }
1196 Assert(u32 < BAT_INDEX_LAST);
1197 s->uBatteryIndex = u32;
1198 break;
1199 default:
1200 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1201 break;
1202 }
1203 return VINF_SUCCESS;
1204}
1205
1206PDMBOTHCBDECL(int) acpiBatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1207{
1208 ACPIState *s = (ACPIState *)pvUser;
1209
1210 switch (cb)
1211 {
1212 case 4:
1213 switch (s->uBatteryIndex)
1214 {
1215 case BAT_STATUS_STATE:
1216 acpiFetchBatteryStatus(s);
1217 case BAT_STATUS_PRESENT_RATE:
1218 case BAT_STATUS_REMAINING_CAPACITY:
1219 case BAT_STATUS_PRESENT_VOLTAGE:
1220 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1221 break;
1222
1223 case BAT_INFO_UNITS:
1224 acpiFetchBatteryInfo(s);
1225 case BAT_INFO_DESIGN_CAPACITY:
1226 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1227 case BAT_INFO_TECHNOLOGY:
1228 case BAT_INFO_DESIGN_VOLTAGE:
1229 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1230 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1231 case BAT_INFO_CAPACITY_GRANULARITY_1:
1232 case BAT_INFO_CAPACITY_GRANULARITY_2:
1233 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1234 break;
1235
1236 case BAT_DEVICE_STATUS:
1237 *pu32 = acpiGetBatteryDeviceStatus(s);
1238 break;
1239
1240 case BAT_POWER_SOURCE:
1241 *pu32 = acpiGetPowerSource(s);
1242 break;
1243
1244 default:
1245 AssertMsgFailed(("Invalid battery index %d\n", s->uBatteryIndex));
1246 break;
1247 }
1248 break;
1249 default:
1250 return VERR_IOM_IOPORT_UNUSED;
1251 }
1252 return VINF_SUCCESS;
1253}
1254
1255PDMBOTHCBDECL(int) acpiSysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1256{
1257 ACPIState *s = (ACPIState *)pvUser;
1258
1259 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1260 switch (cb)
1261 {
1262 case 4:
1263 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1264 s->uSystemInfoIndex = u32;
1265 else
1266 {
1267 /* see comment at the declaration of u8IndexShift */
1268 if (s->u8IndexShift == 0)
1269 {
1270 if (((u32 >> 2) < SYSTEM_INFO_INDEX_END) && ((u32 & 0x3)) == 0)
1271 {
1272 s->u8IndexShift = 2;
1273 }
1274 }
1275
1276 u32 >>= s->u8IndexShift;
1277 Assert(u32 < SYSTEM_INFO_INDEX_END);
1278 s->uSystemInfoIndex = u32;
1279 }
1280 break;
1281
1282 default:
1283 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1284 break;
1285 }
1286 return VINF_SUCCESS;
1287}
1288
1289PDMBOTHCBDECL(int) acpiSysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1290{
1291 ACPIState *s = (ACPIState *)pvUser;
1292
1293 switch (cb)
1294 {
1295 case 4:
1296 switch (s->uSystemInfoIndex)
1297 {
1298 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1299 *pu32 = s->cbRamLow;
1300 break;
1301
1302 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1303 *pu32 = s->cbRamHigh >> 16; /* 64KB units */
1304 Assert(((uint64_t)*pu32 << 16) == s->cbRamHigh);
1305 break;
1306
1307 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1308 *pu32 = s->u8UseIOApic;
1309 break;
1310
1311 case SYSTEM_INFO_INDEX_HPET_STATUS:
1312 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1313 | STA_DEVICE_ENABLED_MASK
1314 | STA_DEVICE_SHOW_IN_UI_MASK
1315 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1316 : 0;
1317 break;
1318
1319 case SYSTEM_INFO_INDEX_SMC_STATUS:
1320 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1321 | STA_DEVICE_ENABLED_MASK
1322 /* no need to show this device in the UI */
1323 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1324 : 0;
1325 break;
1326
1327 case SYSTEM_INFO_INDEX_FDC_STATUS:
1328 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1329 | STA_DEVICE_ENABLED_MASK
1330 | STA_DEVICE_SHOW_IN_UI_MASK
1331 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1332 : 0;
1333 break;
1334
1335 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1336 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1337 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1338 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1339 case SYSTEM_INFO_INDEX_CPU4_STATUS:
1340 case SYSTEM_INFO_INDEX_CPU5_STATUS:
1341 case SYSTEM_INFO_INDEX_CPU6_STATUS:
1342 case SYSTEM_INFO_INDEX_CPU7_STATUS:
1343 case SYSTEM_INFO_INDEX_CPU8_STATUS:
1344 case SYSTEM_INFO_INDEX_CPU9_STATUS:
1345 case SYSTEM_INFO_INDEX_CPUA_STATUS:
1346 case SYSTEM_INFO_INDEX_CPUB_STATUS:
1347 case SYSTEM_INFO_INDEX_CPUC_STATUS:
1348 case SYSTEM_INFO_INDEX_CPUD_STATUS:
1349 case SYSTEM_INFO_INDEX_CPUE_STATUS:
1350 case SYSTEM_INFO_INDEX_CPUF_STATUS:
1351 *pu32 = s->fShowCpu
1352 && s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < s->cCpus
1353 ? STA_DEVICE_PRESENT_MASK
1354 | STA_DEVICE_ENABLED_MASK
1355 | STA_DEVICE_SHOW_IN_UI_MASK
1356 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK
1357 : 0;
1358 break;
1359
1360 case SYSTEM_INFO_INDEX_RTC_STATUS:
1361 *pu32 = s->fShowRtc ? ( STA_DEVICE_PRESENT_MASK
1362 | STA_DEVICE_ENABLED_MASK
1363 | STA_DEVICE_SHOW_IN_UI_MASK
1364 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1365 : 0;
1366 break;
1367
1368 /* Solaris 9 tries to read from this index */
1369 case SYSTEM_INFO_INDEX_INVALID:
1370 *pu32 = 0;
1371 break;
1372
1373 default:
1374 AssertMsgFailed(("Invalid system info index %d\n", s->uSystemInfoIndex));
1375 break;
1376 }
1377 break;
1378
1379 default:
1380 return VERR_IOM_IOPORT_UNUSED;
1381 }
1382
1383 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1384 return VINF_SUCCESS;
1385}
1386
1387PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1388{
1389 ACPIState *s = (ACPIState *)pvUser;
1390
1391 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1392
1393 if (cb == 4 && u32 == 0xbadc0de)
1394 {
1395 switch (s->uSystemInfoIndex)
1396 {
1397 case SYSTEM_INFO_INDEX_INVALID:
1398 s->u8IndexShift = 0;
1399 break;
1400
1401 case SYSTEM_INFO_INDEX_VALID:
1402 s->u8IndexShift = 2;
1403 break;
1404
1405 default:
1406 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1407 Port, cb, u32, s->uSystemInfoIndex));
1408 break;
1409 }
1410 }
1411 else
1412 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1413 return VINF_SUCCESS;
1414}
1415
1416/** @todo Don't call functions, but do the job in the read/write handlers
1417 * here! */
1418
1419/* IO Helpers */
1420PDMBOTHCBDECL(int) acpiPm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1421{
1422 switch (cb)
1423 {
1424 case 2:
1425 *pu32 = acpiPm1aEnReadw((ACPIState*)pvUser, Port);
1426 break;
1427 default:
1428 return VERR_IOM_IOPORT_UNUSED;
1429 }
1430 return VINF_SUCCESS;
1431}
1432
1433PDMBOTHCBDECL(int) acpiPm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1434{
1435 switch (cb)
1436 {
1437 case 2:
1438 *pu32 = acpiPm1aStsReadw((ACPIState*)pvUser, Port);
1439 break;
1440 default:
1441 return VERR_IOM_IOPORT_UNUSED;
1442 }
1443 return VINF_SUCCESS;
1444}
1445
1446PDMBOTHCBDECL(int) acpiPm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1447{
1448 switch (cb)
1449 {
1450 case 2:
1451 *pu32 = acpiPm1aCtlReadw((ACPIState*)pvUser, Port);
1452 break;
1453 default:
1454 return VERR_IOM_IOPORT_UNUSED;
1455 }
1456 return VINF_SUCCESS;
1457}
1458
1459PDMBOTHCBDECL(int) acpiPM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1460{
1461 switch (cb)
1462 {
1463 case 2:
1464 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32);
1465 break;
1466 default:
1467 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1468 break;
1469 }
1470 return VINF_SUCCESS;
1471}
1472
1473PDMBOTHCBDECL(int) acpiPM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1474{
1475 switch (cb)
1476 {
1477 case 2:
1478 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32);
1479 break;
1480 default:
1481 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1482 break;
1483 }
1484 return VINF_SUCCESS;
1485}
1486
1487PDMBOTHCBDECL(int) acpiPM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1488{
1489 switch (cb)
1490 {
1491 case 2:
1492 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32);
1493 default:
1494 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1495 break;
1496 }
1497 return VINF_SUCCESS;
1498}
1499
1500#endif /* IN_RING3 */
1501
1502/**
1503 * PMTMR readable from host/guest.
1504 */
1505PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1506{
1507 if (cb == 4)
1508 {
1509 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1510 int64_t now = TMTimerGet(s->CTX_SUFF(ts));
1511 int64_t elapsed = now - s->pm_timer_initial;
1512
1513 *pu32 = ASMMultU64ByU32DivByU32(elapsed, PM_TMR_FREQ, TMTimerGetFreq(s->CTX_SUFF(ts)));
1514 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1515 return VINF_SUCCESS;
1516 }
1517 return VERR_IOM_IOPORT_UNUSED;
1518}
1519
1520#ifdef IN_RING3
1521
1522PDMBOTHCBDECL(int) acpiGpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1523{
1524 switch (cb)
1525 {
1526 case 1:
1527 *pu32 = acpiGpe0StsReadb((ACPIState*)pvUser, Port);
1528 break;
1529 default:
1530 return VERR_IOM_IOPORT_UNUSED;
1531 }
1532 return VINF_SUCCESS;
1533}
1534
1535PDMBOTHCBDECL(int) acpiGpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1536{
1537 switch (cb)
1538 {
1539 case 1:
1540 *pu32 = acpiGpe0EnReadb((ACPIState*)pvUser, Port);
1541 break;
1542 default:
1543 return VERR_IOM_IOPORT_UNUSED;
1544 }
1545 return VINF_SUCCESS;
1546}
1547
1548PDMBOTHCBDECL(int) acpiGpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1549{
1550 switch (cb)
1551 {
1552 case 1:
1553 acpiGpe0StsWriteb((ACPIState*)pvUser, Port, u32);
1554 break;
1555 default:
1556 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1557 break;
1558 }
1559 return VINF_SUCCESS;
1560}
1561
1562PDMBOTHCBDECL(int) acpiGpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1563{
1564 switch (cb)
1565 {
1566 case 1:
1567 acpiGpe0EnWriteb((ACPIState*)pvUser, Port, u32);
1568 break;
1569 default:
1570 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1571 break;
1572 }
1573 return VINF_SUCCESS;
1574}
1575
1576PDMBOTHCBDECL(int) acpiSmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1577{
1578 switch (cb)
1579 {
1580 case 1:
1581 acpiSmiWriteU8((ACPIState*)pvUser, Port, u32);
1582 break;
1583 default:
1584 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1585 break;
1586 }
1587 return VINF_SUCCESS;
1588}
1589
1590PDMBOTHCBDECL(int) acpiResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1591{
1592 switch (cb)
1593 {
1594 case 1:
1595 return acpiResetWriteU8((ACPIState*)pvUser, Port, u32);
1596 default:
1597 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1598 break;
1599 }
1600 return VINF_SUCCESS;
1601}
1602
1603#ifdef DEBUG_ACPI
1604
1605PDMBOTHCBDECL(int) acpiDhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1606{
1607 switch (cb)
1608 {
1609 case 1:
1610 Log(("%#x\n", u32 & 0xff));
1611 break;
1612 case 2:
1613 Log(("%#6x\n", u32 & 0xffff));
1614 case 4:
1615 Log(("%#10x\n", u32));
1616 break;
1617 default:
1618 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1619 break;
1620 }
1621 return VINF_SUCCESS;
1622}
1623
1624PDMBOTHCBDECL(int) acpiDchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1625{
1626 switch (cb)
1627 {
1628 case 1:
1629 Log(("%c", u32 & 0xff));
1630 break;
1631 default:
1632 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1633 break;
1634 }
1635 return VINF_SUCCESS;
1636}
1637
1638#endif /* DEBUG_ACPI */
1639
1640
1641/**
1642 * Saved state structure description.
1643 */
1644static const SSMFIELD g_AcpiSavedStateFields[] =
1645{
1646 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1647 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1648 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1649 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1650 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1651 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1652 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1653 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1654 SSMFIELD_ENTRY(ACPIState, u64RamSize), /** @todo not necessary to save this. */
1655 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1656 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1657 SSMFIELD_ENTRY(ACPIState, uSleepState),
1658 SSMFIELD_ENTRY_TERM()
1659};
1660
1661static DECLCALLBACK(int) acpi_save_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1662{
1663 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1664 return SSMR3PutStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1665}
1666
1667static DECLCALLBACK(int) acpi_load_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1668 uint32_t u32Version)
1669{
1670 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1671 int rc;
1672
1673 if (u32Version != 4)
1674 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1675
1676 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1677 if (RT_SUCCESS(rc))
1678 {
1679 acpiFetchBatteryStatus(s);
1680 acpiFetchBatteryInfo(s);
1681 acpiPMTimerReset(s);
1682 }
1683 return rc;
1684}
1685
1686/**
1687 * Queries an interface to the driver.
1688 *
1689 * @returns Pointer to interface.
1690 * @returns NULL if the interface was not supported by the driver.
1691 * @param pInterface Pointer to this interface structure.
1692 * @param enmInterface The requested interface identification.
1693 * @thread Any thread.
1694 */
1695static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1696{
1697 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1698 switch (enmInterface)
1699 {
1700 case PDMINTERFACE_BASE:
1701 return &pThis->IBase;
1702 case PDMINTERFACE_ACPI_PORT:
1703 return &pThis->IACPIPort;
1704 default:
1705 return NULL;
1706 }
1707}
1708
1709/**
1710 * Create the ACPI tables.
1711 */
1712static int acpiPlantTables(ACPIState *s)
1713{
1714 int rc;
1715 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1716 uint32_t addend = 0;
1717 RTGCPHYS32 rsdt_addrs[4];
1718 uint32_t cAddr;
1719 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1720 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1721
1722 cAddr = 1; /* FADT */
1723 if (s->u8UseIOApic)
1724 cAddr++; /* MADT */
1725
1726 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1727 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1728
1729 rc = CFGMR3QueryU64(s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1730 if (RT_FAILURE(rc))
1731 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1732 N_("Configuration error: Querying "
1733 "\"RamSize\" as integer failed"));
1734
1735 uint32_t cbRamHole;
1736 rc = CFGMR3QueryU32Def(s->pDevIns->pCfgHandle, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1737 if (RT_FAILURE(rc))
1738 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1739 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
1740
1741 /*
1742 * Calc the sizes for the high and low regions.
1743 */
1744 const uint64_t offRamHole = _4G - cbRamHole;
1745 s->cbRamHigh = offRamHole < s->u64RamSize ? s->u64RamSize - offRamHole : 0;
1746 uint64_t cbRamLow = offRamHole < s->u64RamSize ? offRamHole : s->u64RamSize;
1747 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
1748 {
1749 /* Note: This is also enforced by DevPcBios.cpp. */
1750 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
1751 cbRamLow = UINT32_C(0xffe00000);
1752 }
1753 s->cbRamLow = (uint32_t)cbRamLow;
1754
1755 rsdt_addr = 0;
1756 xsdt_addr = RT_ALIGN_32(rsdt_addr + rsdt_tbl_len, 16);
1757 fadt_addr = RT_ALIGN_32(xsdt_addr + xsdt_tbl_len, 16);
1758 facs_addr = RT_ALIGN_32(fadt_addr + sizeof(ACPITBLFADT), 16);
1759 if (s->u8UseIOApic)
1760 {
1761 apic_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1762 /**
1763 * @todo nike: maybe some refactoring needed to compute tables layout,
1764 * but as this code is executed only once it doesn't make sense to optimize much
1765 */
1766 dsdt_addr = RT_ALIGN_32(apic_addr + AcpiTableMADT::sizeFor(s), 16);
1767 }
1768 else
1769 {
1770 dsdt_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1771 }
1772
1773 last_addr = RT_ALIGN_32(dsdt_addr + sizeof(AmlCode), 16);
1774 if (last_addr > 0x10000)
1775 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1776 N_("Error: ACPI tables > 64KB"));
1777
1778 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1779 addend = s->cbRamLow - 0x10000;
1780 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1781 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1782 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1783 acpiSetupRSDP((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1784 acpiSetupDSDT(s, dsdt_addr + addend);
1785 acpiSetupFACS(s, facs_addr + addend);
1786 acpiSetupFADT(s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1787
1788 rsdt_addrs[0] = fadt_addr + addend;
1789 if (s->u8UseIOApic)
1790 {
1791 acpiSetupMADT(s, apic_addr + addend);
1792 rsdt_addrs[1] = apic_addr + addend;
1793 }
1794
1795 rc = acpiSetupRSDT(s, rsdt_addr + addend, cAddr, rsdt_addrs);
1796 if (RT_FAILURE(rc))
1797 return rc;
1798 return acpiSetupXSDT(s, xsdt_addr + addend, cAddr, rsdt_addrs);
1799}
1800
1801/**
1802 * Construct a device instance for a VM.
1803 *
1804 * @returns VBox status.
1805 * @param pDevIns The device instance data.
1806 * If the registration structure is needed, pDevIns->pDevReg points to it.
1807 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1808 * The device number is also found in pDevIns->iInstance, but since it's
1809 * likely to be freqently used PDM passes it as parameter.
1810 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1811 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1812 * iInstance it's expected to be used a bit in this function.
1813 */
1814static DECLCALLBACK(int) acpiConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1815{
1816 int rc;
1817 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1818 uint32_t rsdp_addr;
1819 PCIDevice *dev;
1820 bool fGCEnabled;
1821 bool fR0Enabled;
1822
1823 /* Validate and read the configuration. */
1824 if (!CFGMR3AreValuesValid(pCfgHandle,
1825 "RamSize\0"
1826 "RamHoleSize\0"
1827 "IOAPIC\0"
1828 "NumCPUs\0"
1829 "GCEnabled\0"
1830 "R0Enabled\0"
1831 "HpetEnabled\0"
1832 "SmcEnabled\0"
1833 "FdcEnabled\0"
1834 "ShowRtc\0"
1835 "ShowCpu\0"
1836 ))
1837 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1838 N_("Configuration error: Invalid config key for ACPI device"));
1839
1840 s->pDevIns = pDevIns;
1841
1842 /* query whether we are supposed to present an IOAPIC */
1843 rc = CFGMR3QueryU8Def(pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
1844 if (RT_FAILURE(rc))
1845 return PDMDEV_SET_ERROR(pDevIns, rc,
1846 N_("Configuration error: Failed to read \"IOAPIC\""));
1847
1848 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
1849 if (RT_FAILURE(rc))
1850 return PDMDEV_SET_ERROR(pDevIns, rc,
1851 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
1852
1853 /* query whether we are supposed to present an FDC controller */
1854 rc = CFGMR3QueryBoolDef(pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
1855 if (RT_FAILURE(rc))
1856 return PDMDEV_SET_ERROR(pDevIns, rc,
1857 N_("Configuration error: Failed to read \"FdcEnabled\""));
1858
1859 /* query whether we are supposed to present HPET */
1860 rc = CFGMR3QueryBoolDef(pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
1861 if (RT_FAILURE(rc))
1862 return PDMDEV_SET_ERROR(pDevIns, rc,
1863 N_("Configuration error: Failed to read \"HpetEnabled\""));
1864 /* query whether we are supposed to present SMC */
1865 rc = CFGMR3QueryBoolDef(pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
1866 if (RT_FAILURE(rc))
1867 return PDMDEV_SET_ERROR(pDevIns, rc,
1868 N_("Configuration error: Failed to read \"SmcEnabled\""));
1869
1870 /* query whether we are supposed to present RTC object */
1871 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowRtc", &s->fShowRtc, false);
1872 if (RT_FAILURE(rc))
1873 return PDMDEV_SET_ERROR(pDevIns, rc,
1874 N_("Configuration error: Failed to read \"ShowRtc\""));
1875
1876 /* query whether we are supposed to present CPU objects */
1877 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowCpu", &s->fShowCpu, false);
1878 if (RT_FAILURE(rc))
1879 return PDMDEV_SET_ERROR(pDevIns, rc,
1880 N_("Configuration error: Failed to read \"ShowCpu\""));
1881
1882 /* Always show the CPU leafs when we have multiple VCPUs. */
1883 if (s->cCpus > 1)
1884 s->fShowCpu = true;
1885
1886 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1887 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1888 fGCEnabled = true;
1889 else if (RT_FAILURE(rc))
1890 return PDMDEV_SET_ERROR(pDevIns, rc,
1891 N_("Configuration error: Failed to read \"GCEnabled\""));
1892
1893 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1894 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1895 fR0Enabled = true;
1896 else if (RT_FAILURE(rc))
1897 return PDMDEV_SET_ERROR(pDevIns, rc,
1898 N_("configuration error: failed to read R0Enabled as boolean"));
1899
1900 /* */
1901 rsdp_addr = find_rsdp_space();
1902 if (!rsdp_addr)
1903 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1904 N_("Can not find space for RSDP. ACPI is disabled"));
1905
1906 rc = acpiPlantTables(s);
1907 if (RT_FAILURE(rc))
1908 return rc;
1909
1910 rc = PDMDevHlpROMRegister(pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage,
1911 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
1912 if (RT_FAILURE(rc))
1913 return rc;
1914
1915#define R(addr, cnt, writer, reader, description) \
1916 do { \
1917 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, s, writer, reader, \
1918 NULL, NULL, description); \
1919 if (RT_FAILURE(rc)) \
1920 return rc; \
1921 } while (0)
1922#define L (GPE0_BLK_LEN / 2)
1923
1924 R(PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1925 R(PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1926 R(PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1927 R(PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1928 R(SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1929#ifdef DEBUG_ACPI
1930 R(DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1931 R(DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1932#endif
1933 R(BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1934 R(BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1935 R(SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1936 R(SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1937 R(GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1938 R(GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1939 R(ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1940#undef L
1941#undef R
1942
1943 /* register GC stuff */
1944 if (fGCEnabled)
1945 {
1946 rc = PDMDevHlpIOPortRegisterGC(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1947 NULL, NULL, "ACPI PM Timer");
1948 AssertRCReturn(rc, rc);
1949 }
1950
1951 /* register R0 stuff */
1952 if (fR0Enabled)
1953 {
1954 rc = PDMDevHlpIOPortRegisterR0(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1955 NULL, NULL, "ACPI PM Timer");
1956 AssertRCReturn(rc, rc);
1957 }
1958
1959 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1960 if (RT_FAILURE(rc))
1961 {
1962 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1963 return rc;
1964 }
1965
1966 s->tsR0 = TMTimerR0Ptr(s->tsR3);
1967 s->tsRC = TMTimerRCPtr(s->tsR3);
1968 s->pm_timer_initial = TMTimerGet(s->tsR3);
1969 acpiPMTimerReset(s);
1970
1971 dev = &s->dev;
1972 PCIDevSetVendorId(dev, 0x8086); /* Intel */
1973 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
1974
1975 dev->config[0x04] = 0x01; /* command */
1976 dev->config[0x05] = 0x00;
1977
1978 dev->config[0x06] = 0x80; /* status */
1979 dev->config[0x07] = 0x02;
1980 dev->config[0x08] = 0x08;
1981 dev->config[0x09] = 0x00;
1982
1983 dev->config[0x0a] = 0x80;
1984 dev->config[0x0b] = 0x06;
1985
1986 dev->config[0x0e] = 0x80;
1987 dev->config[0x0f] = 0x00;
1988
1989#if 0 /* The ACPI controller usually has no subsystem ID. */
1990 dev->config[0x2c] = 0x86;
1991 dev->config[0x2d] = 0x80;
1992 dev->config[0x2e] = 0x00;
1993 dev->config[0x2f] = 0x00;
1994#endif
1995 dev->config[0x3c] = SCI_INT;
1996
1997 rc = PDMDevHlpPCIRegister(pDevIns, dev);
1998 if (RT_FAILURE(rc))
1999 return rc;
2000
2001 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
2002 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
2003 if (RT_FAILURE(rc))
2004 return rc;
2005
2006 /*
2007 * Interfaces
2008 */
2009 /* IBase */
2010 s->IBase.pfnQueryInterface = acpiQueryInterface;
2011 /* IACPIPort */
2012 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
2013 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
2014 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
2015 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
2016
2017 /*
2018 * Get the corresponding connector interface
2019 */
2020 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
2021 if (RT_SUCCESS(rc))
2022 {
2023 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface(s->pDrvBase, PDMINTERFACE_ACPI_CONNECTOR);
2024 if (!s->pDrv)
2025 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
2026 N_("LUN #0 doesn't have an ACPI connector interface"));
2027 }
2028 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2029 {
2030 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2031 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2032 rc = VINF_SUCCESS;
2033 }
2034 else
2035 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
2036
2037 return rc;
2038}
2039
2040/**
2041 * Relocates the GC pointer members.
2042 */
2043static DECLCALLBACK(void) acpiRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2044{
2045 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2046 s->tsRC = TMTimerRCPtr(s->CTX_SUFF(ts));
2047}
2048
2049static DECLCALLBACK(void) acpiReset(PPDMDEVINS pDevIns)
2050{
2051 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2052
2053 s->pm1a_en = 0;
2054 s->pm1a_sts = 0;
2055 s->pm1a_ctl = 0;
2056 s->pm_timer_initial = TMTimerGet(s->CTX_SUFF(ts));
2057 acpiPMTimerReset(s);
2058 s->uBatteryIndex = 0;
2059 s->uSystemInfoIndex = 0;
2060 s->gpe0_en = 0;
2061 s->gpe0_sts = 0;
2062 s->uSleepState = 0;
2063
2064 acpiPlantTables(s);
2065}
2066
2067/**
2068 * The device registration structure.
2069 */
2070const PDMDEVREG g_DeviceACPI =
2071{
2072 /* u32Version */
2073 PDM_DEVREG_VERSION,
2074 /* szDeviceName */
2075 "acpi",
2076 /* szRCMod */
2077 "VBoxDDGC.gc",
2078 /* szR0Mod */
2079 "VBoxDDR0.r0",
2080 /* pszDescription */
2081 "Advanced Configuration and Power Interface",
2082 /* fFlags */
2083 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2084 /* fClass */
2085 PDM_DEVREG_CLASS_ACPI,
2086 /* cMaxInstances */
2087 ~0,
2088 /* cbInstance */
2089 sizeof(ACPIState),
2090 /* pfnConstruct */
2091 acpiConstruct,
2092 /* pfnDestruct */
2093 NULL,
2094 /* pfnRelocate */
2095 acpiRelocate,
2096 /* pfnIOCtl */
2097 NULL,
2098 /* pfnPowerOn */
2099 NULL,
2100 /* pfnReset */
2101 acpiReset,
2102 /* pfnSuspend */
2103 NULL,
2104 /* pfnResume */
2105 NULL,
2106 /* pfnAttach */
2107 NULL,
2108 /* pfnDetach */
2109 NULL,
2110 /* pfnQueryInterface. */
2111 NULL,
2112 /* pfnInitComplete */
2113 NULL,
2114 /* pfnPowerOff */
2115 NULL,
2116 /* pfnSoftReset */
2117 NULL,
2118 /* u32VersionEnd */
2119 PDM_DEVREG_VERSION
2120};
2121
2122#endif /* IN_RING3 */
2123#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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