VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 20592

Last change on this file since 20592 was 20592, checked in by vboxsync, 16 years ago

ACPI: cleanup, restored removed AML patching
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1/* $Id: DevACPI.cpp 20592 2009-06-15 14:32:18Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_ACPI
26#include <VBox/pdmdev.h>
27#include <VBox/pgm.h>
28#include <VBox/log.h>
29#include <VBox/param.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35#endif /* IN_RING3 */
36
37#include "../Builtins.h"
38
39#ifdef LOG_ENABLED
40# define DEBUG_ACPI
41#endif
42
43#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
44int acpiPrepareDsdt(PPDMDEVINS pDevIns, void* *ppPtr, size_t *puDsdtLen);
45int acpiCleanupDsdt(PPDMDEVINS pDevIns, void* pPtr);
46#endif /* !IN_RING3 */
47
48
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53#define DEBUG_HEX 0x3000
54#define DEBUG_CHR 0x3001
55
56#define PM_TMR_FREQ 3579545
57#define PM1a_EVT_BLK 0x00004000
58#define PM1b_EVT_BLK 0x00000000 /**< not supported */
59#define PM1a_CTL_BLK 0x00004004
60#define PM1b_CTL_BLK 0x00000000 /**< not supported */
61#define PM2_CTL_BLK 0x00000000 /**< not supported */
62#define PM_TMR_BLK 0x00004008
63#define GPE0_BLK 0x00004020
64#define GPE1_BLK 0x00000000 /**< not supported */
65#define BAT_INDEX 0x00004040
66#define BAT_DATA 0x00004044
67#define SYSI_INDEX 0x00004048
68#define SYSI_DATA 0x0000404c
69#define ACPI_RESET_BLK 0x00004050
70
71/* PM1x status register bits */
72#define TMR_STS RT_BIT(0)
73#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
74#define BM_STS RT_BIT(4)
75#define GBL_STS RT_BIT(5)
76#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
77#define PWRBTN_STS RT_BIT(8)
78#define SLPBTN_STS RT_BIT(9)
79#define RTC_STS RT_BIT(10)
80#define IGN_STS RT_BIT(11)
81#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
82#define WAK_STS RT_BIT(15)
83#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
84
85/* PM1x enable register bits */
86#define TMR_EN RT_BIT(0)
87#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
88#define GBL_EN RT_BIT(5)
89#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
90#define PWRBTN_EN RT_BIT(8)
91#define SLPBTN_EN RT_BIT(9)
92#define RTC_EN RT_BIT(10)
93#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
94#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
95#define IGN_EN 0
96
97/* PM1x control register bits */
98#define SCI_EN RT_BIT(0)
99#define BM_RLD RT_BIT(1)
100#define GBL_RLS RT_BIT(2)
101#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
102#define IGN_CNT RT_BIT(9)
103#define SLP_TYPx_SHIFT 10
104#define SLP_TYPx_MASK 7
105#define SLP_EN RT_BIT(13)
106#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
107#define RSR_CNT (RSR1_CNT | RSR2_CNT)
108
109#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
110
111enum
112{
113 BAT_STATUS_STATE = 0x00, /**< BST battery state */
114 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
115 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
116 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
117 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
118 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
119 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
120 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
121 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
122 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
123 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
124 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
125 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
126 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
127 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
128 BAT_INDEX_LAST
129};
130
131enum
132{
133 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
134 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
135 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
136 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
137 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
138 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
139 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 6,
140 SYSTEM_INFO_INDEX_RTC_STATUS = 7,
141 SYSTEM_INFO_INDEX_END = 8,
142 SYSTEM_INFO_INDEX_INVALID = 0x80,
143 SYSTEM_INFO_INDEX_VALID = 0x200
144};
145
146#define AC_OFFLINE 0
147#define AC_ONLINE 1
148
149#define BAT_TECH_PRIMARY 1
150#define BAT_TECH_SECONDARY 2
151
152#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
153#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
154#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
155#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
156#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
157
158
159/*******************************************************************************
160* Structures and Typedefs *
161*******************************************************************************/
162/**
163 * The ACPI device state.
164 */
165typedef struct ACPIState
166{
167 PCIDevice dev;
168 uint16_t pm1a_en;
169 uint16_t pm1a_sts;
170 uint16_t pm1a_ctl;
171 /** Number of logical CPUs in guest */
172 uint16_t cCpus;
173 int64_t pm_timer_initial;
174 PTMTIMERR3 tsR3;
175 PTMTIMERR0 tsR0;
176 PTMTIMERRC tsRC;
177
178 uint32_t gpe0_en;
179 uint32_t gpe0_sts;
180
181 unsigned int uBatteryIndex;
182 uint32_t au8BatteryInfo[13];
183
184 unsigned int uSystemInfoIndex;
185 uint64_t u64RamSize;
186 /** The number of bytes above 4GB. */
187 uint64_t cbRamHigh;
188 /** The number of bytes below 4GB. */
189 uint32_t cbRamLow;
190
191 /** Current ACPI S* state. We support S0 and S5 */
192 uint32_t uSleepState;
193 uint8_t au8RSDPPage[0x1000];
194 /** This is a workaround for incorrect index field handling by Intels ACPICA.
195 * The system info _INI method writes to offset 0x200. We either observe a
196 * write request to index 0x80 (in that case we don't change the index) or a
197 * write request to offset 0x200 (in that case we divide the index value by
198 * 4. Note that the _STA method is sometimes called prior to the _INI method
199 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
200 * acpiBatIndexWrite() for handling this. */
201 uint8_t u8IndexShift;
202 /** provide an I/O-APIC */
203 uint8_t u8UseIOApic;
204 /** provide a floppy controller */
205 bool fUseFdc;
206 /** If High Precision Event Timer device should be supported */
207 bool fUseHpet;
208 /** If System Management Controller device should be supported */
209 bool fUseSmc;
210 /** the guest handled the last power button event */
211 bool fPowerButtonHandled;
212 /** If ACPI CPU device should be shown */
213 bool fShowCpu;
214 /** If Real Time Clock ACPI object to be shown */
215 bool fShowRtc;
216 /** Aligning IBase. */
217 bool afAlignment[5];
218
219 /** ACPI port base interface. */
220 PDMIBASE IBase;
221 /** ACPI port interface. */
222 PDMIACPIPORT IACPIPort;
223 /** Pointer to the device instance. */
224 PPDMDEVINSR3 pDevIns;
225 /** Pointer to the driver base interface */
226 R3PTRTYPE(PPDMIBASE) pDrvBase;
227 /** Pointer to the driver connector interface */
228 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
229} ACPIState;
230
231#pragma pack(1)
232
233/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
234struct ACPIGENADDR
235{
236 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
237 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
238 uint8_t u8RegisterBitOffset; /**< bit offset of register */
239 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
240 uint64_t u64Address; /**< 64-bit address of register */
241};
242AssertCompileSize(ACPIGENADDR, 12);
243
244/** Root System Description Pointer */
245struct ACPITBLRSDP
246{
247 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
248 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
249 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
250 uint8_t u8Revision; /**< revision number, currently 2 */
251#define ACPI_REVISION 2 /**< ACPI 3.0 */
252 uint32_t u32RSDT; /**< phys addr of RSDT */
253 uint32_t u32Length; /**< bytes of this table */
254 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
255 uint8_t u8ExtChecksum; /**< checksum of entire table */
256 uint8_t u8Reserved[3]; /**< reserved */
257};
258AssertCompileSize(ACPITBLRSDP, 36);
259
260/** System Description Table Header */
261struct ACPITBLHEADER
262{
263 uint8_t au8Signature[4]; /**< table identifier */
264 uint32_t u32Length; /**< length of the table including header */
265 uint8_t u8Revision; /**< revision number */
266 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
267 uint8_t au8OemId[6]; /**< OEM-supplied string */
268 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
269 uint32_t u32OemRevision; /**< OEM-supplied revision number */
270 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
271 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
272};
273AssertCompileSize(ACPITBLHEADER, 36);
274
275/** Root System Description Table */
276struct ACPITBLRSDT
277{
278 ACPITBLHEADER header;
279 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
280};
281AssertCompileSize(ACPITBLRSDT, 40);
282
283/** Extended System Description Table */
284struct ACPITBLXSDT
285{
286 ACPITBLHEADER header;
287 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
288};
289AssertCompileSize(ACPITBLXSDT, 44);
290
291/** Fixed ACPI Description Table */
292struct ACPITBLFADT
293{
294 ACPITBLHEADER header;
295 uint32_t u32FACS; /**< phys. address of FACS */
296 uint32_t u32DSDT; /**< phys. address of DSDT */
297 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
298#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
299#define INT_MODEL_MULTIPLE_APIC 2
300 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
301 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
302#define SCI_INT 9
303 uint32_t u32SMICmd; /**< system port address of SMI command port */
304#define SMI_CMD 0x0000442e
305 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
306#define ACPI_ENABLE 0xa1
307 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
308#define ACPI_DISABLE 0xa0
309 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
310 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
311 state control responsibility */
312 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
313 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
314 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
315 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
316 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
317 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
318 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
319 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
320 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
321 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
322 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
323 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
324 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
325#define GPE0_BLK_LEN 2
326 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
327#define GPE1_BLK_LEN 0
328 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
329#define GPE1_BASE 0
330 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
331 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
332#define P_LVL2_LAT 101 /**< C2 state not supported */
333 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
334#define P_LVL3_LAT 1001 /**< C3 state not supported */
335 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
336 lines from any processors memory caches */
337#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
338 uint16_t u16FlushStride; /**< cache line width */
339#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
340 uint8_t u8DutyOffset;
341 uint8_t u8DutyWidth;
342 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
343 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
344 uint8_t u8Century; /**< RTC CMOS RAM index of century */
345 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
346#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
347 (COM too?) */
348#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
349#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
350 uint8_t u8Must0_0; /**< must be 0 */
351 uint32_t u32Flags; /**< fixed feature flags */
352#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
353#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
354#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
355#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
356#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
357#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
358#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
359#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
360#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
361#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
362#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
363#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
364#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
365#define FADT_FL_CPU_SW_SLP RT_BIT(13)
366#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
367#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
368#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
369#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
370#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
371#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
372 ACPIGENADDR ResetReg; /**< ext addr of reset register */
373 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
374#define ACPI_RESET_REG_VAL 0x10
375 uint8_t au8Must0_1[3]; /**< must be 0 */
376 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
377 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
378 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
379 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
380 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
381 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
382 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
383 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
384 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
385 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
386};
387AssertCompileSize(ACPITBLFADT, 244);
388
389/** Firmware ACPI Control Structure */
390struct ACPITBLFACS
391{
392 uint8_t au8Signature[4]; /**< 'FACS' */
393 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
394 uint32_t u32HWSignature; /**< systems HW signature at last boot */
395 uint32_t u32FWVector; /**< address of waking vector */
396 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
397 uint32_t u32Flags; /**< FACS flags */
398 uint64_t u64X_FWVector; /**< 64-bit waking vector */
399 uint8_t u8Version; /**< version of this table */
400 uint8_t au8Reserved[31]; /**< zero */
401};
402AssertCompileSize(ACPITBLFACS, 64);
403
404/** Processor Local APIC Structure */
405struct ACPITBLLAPIC
406{
407 uint8_t u8Type; /**< 0 = LAPIC */
408 uint8_t u8Length; /**< 8 */
409 uint8_t u8ProcId; /**< processor ID */
410 uint8_t u8ApicId; /**< local APIC ID */
411 uint32_t u32Flags; /**< Flags */
412#define LAPIC_ENABLED 0x1
413};
414AssertCompileSize(ACPITBLLAPIC, 8);
415
416/** I/O APIC Structure */
417struct ACPITBLIOAPIC
418{
419 uint8_t u8Type; /**< 1 == I/O APIC */
420 uint8_t u8Length; /**< 12 */
421 uint8_t u8IOApicId; /**< I/O APIC ID */
422 uint8_t u8Reserved; /**< 0 */
423 uint32_t u32Address; /**< phys address to access I/O APIC */
424 uint32_t u32GSIB; /**< global system interrupt number to start */
425};
426AssertCompileSize(ACPITBLIOAPIC, 12);
427
428# ifdef IN_RING3 /**@todo r=bird: Move this down to where it's used. */
429
430# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
431
432/**
433 * Multiple APIC Description Table.
434 *
435 * This structure looks somewhat convoluted due layout of MADT table in MP case.
436 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
437 * use regular C structure and proxy to raw memory instead.
438 */
439class AcpiTableMADT
440{
441 /**
442 * All actual data stored in dynamically allocated memory pointed by this field.
443 */
444 uint8_t *m_pbData;
445 /**
446 * Number of CPU entries in this MADT.
447 */
448 uint32_t m_cCpus;
449
450public:
451 /**
452 * Address of ACPI header
453 */
454 inline ACPITBLHEADER *header_addr(void) const
455 {
456 return (ACPITBLHEADER *)m_pbData;
457 }
458
459 /**
460 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
461 * although address is the same for all of them.
462 */
463 inline uint32_t *u32LAPIC_addr(void) const
464 {
465 return (uint32_t *)(header_addr() + 1);
466 }
467
468 /**
469 * Address of APIC flags
470 */
471 inline uint32_t *u32Flags_addr(void) const
472 {
473 return (uint32_t *)(u32LAPIC_addr() + 1);
474 }
475
476 /**
477 * Address of per-CPU LAPIC descriptions
478 */
479 inline ACPITBLLAPIC *LApics_addr(void) const
480 {
481 return (ACPITBLLAPIC *)(u32Flags_addr() + 1);
482 }
483
484 /**
485 * Address of IO APIC description
486 */
487 inline ACPITBLIOAPIC *IOApic_addr(void) const
488 {
489 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
490 }
491
492 /**
493 * Size of MADT.
494 * Note that this function assumes IOApic to be the last field in structure.
495 */
496 inline uint32_t size(void) const
497 {
498 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
499 }
500
501 /**
502 * Raw data of MADT.
503 */
504 inline const uint8_t *data(void) const
505 {
506 return m_pbData;
507 }
508
509 /**
510 * Size of MADT for given ACPI config, useful to compute layout.
511 */
512 static uint32_t sizeFor(ACPIState *s)
513 {
514 return AcpiTableMADT(s->cCpus).size();
515 }
516
517 /*
518 * Constructor, only works in Ring 3, doesn't look like a big deal.
519 */
520 AcpiTableMADT(uint32_t cCpus)
521 {
522 m_cCpus = cCpus;
523 uint32_t cb = size();
524 m_pbData = (uint8_t *)RTMemAllocZ(cb);
525 }
526
527 ~AcpiTableMADT()
528 {
529 RTMemFree(m_pbData);
530 }
531};
532# endif /* IN_RING3 */
533
534#pragma pack()
535
536
537#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
538/*******************************************************************************
539* Internal Functions *
540*******************************************************************************/
541RT_C_DECLS_BEGIN
542PDMBOTHCBDECL(int) acpiPMTmrRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
543#ifdef IN_RING3
544PDMBOTHCBDECL(int) acpiPm1aEnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
545PDMBOTHCBDECL(int) acpiPM1aEnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
546PDMBOTHCBDECL(int) acpiPm1aStsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
547PDMBOTHCBDECL(int) acpiPM1aStsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
548PDMBOTHCBDECL(int) acpiPm1aCtlRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
549PDMBOTHCBDECL(int) acpiPM1aCtlWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
550PDMBOTHCBDECL(int) acpiSmiWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
551PDMBOTHCBDECL(int) acpiBatIndexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
552PDMBOTHCBDECL(int) acpiBatDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
553PDMBOTHCBDECL(int) acpiSysInfoDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
554PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
555PDMBOTHCBDECL(int) acpiGpe0EnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
556PDMBOTHCBDECL(int) acpiGpe0EnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
557PDMBOTHCBDECL(int) acpiGpe0StsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
558PDMBOTHCBDECL(int) acpiGpe0StsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
559PDMBOTHCBDECL(int) acpiResetWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
560# ifdef DEBUG_ACPI
561PDMBOTHCBDECL(int) acpiDhexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
562PDMBOTHCBDECL(int) acpiDchrWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
563# endif
564#endif /* IN_RING3 */
565RT_C_DECLS_END
566
567
568#ifdef IN_RING3
569
570/* Simple acpiChecksum: all the bytes must add up to 0. */
571static uint8_t acpiChecksum(const uint8_t * const data, size_t len)
572{
573 uint8_t sum = 0;
574 for (size_t i = 0; i < len; ++i)
575 sum += data[i];
576 return -sum;
577}
578
579static void acpiPrepareHeader(ACPITBLHEADER *header, const char au8Signature[4],
580 uint32_t u32Length, uint8_t u8Revision)
581{
582 memcpy(header->au8Signature, au8Signature, 4);
583 header->u32Length = RT_H2LE_U32(u32Length);
584 header->u8Revision = u8Revision;
585 memcpy(header->au8OemId, "VBOX ", 6);
586 memcpy(header->au8OemTabId, "VBOX", 4);
587 memcpy(header->au8OemTabId+4, au8Signature, 4);
588 header->u32OemRevision = RT_H2LE_U32(1);
589 memcpy(header->au8CreatorId, "ASL ", 4);
590 header->u32CreatorRev = RT_H2LE_U32(0x61);
591}
592
593static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
594 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
595 uint8_t u8AccessSize, uint64_t u64Address)
596{
597 g->u8AddressSpaceId = u8AddressSpaceId;
598 g->u8RegisterBitWidth = u8RegisterBitWidth;
599 g->u8RegisterBitOffset = u8RegisterBitOffset;
600 g->u8AccessSize = u8AccessSize;
601 g->u64Address = RT_H2LE_U64(u64Address);
602}
603
604static void acpiPhyscpy(ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
605{
606 PDMDevHlpPhysWrite(s->pDevIns, dst, src, size);
607}
608
609/** Differentiated System Description Table (DSDT) */
610
611static void acpiSetupDSDT(ACPIState *s, RTGCPHYS32 addr,
612 void* pPtr, size_t uDsdtLen)
613{
614 acpiPhyscpy(s, addr, pPtr, uDsdtLen);
615}
616
617/** Firmware ACPI Control Structure (FACS) */
618static void acpiSetupFACS(ACPIState *s, RTGCPHYS32 addr)
619{
620 ACPITBLFACS facs;
621
622 memset(&facs, 0, sizeof(facs));
623 memcpy(facs.au8Signature, "FACS", 4);
624 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
625 facs.u32HWSignature = RT_H2LE_U32(0);
626 facs.u32FWVector = RT_H2LE_U32(0);
627 facs.u32GlobalLock = RT_H2LE_U32(0);
628 facs.u32Flags = RT_H2LE_U32(0);
629 facs.u64X_FWVector = RT_H2LE_U64(0);
630 facs.u8Version = 1;
631
632 acpiPhyscpy(s, addr, (const uint8_t *)&facs, sizeof(facs));
633}
634
635/** Fixed ACPI Description Table (FADT aka FACP) */
636static void acpiSetupFADT(ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
637{
638 ACPITBLFADT fadt;
639
640 memset(&fadt, 0, sizeof(fadt));
641 acpiPrepareHeader(&fadt.header, "FACP", sizeof(fadt), 4);
642 fadt.u32FACS = RT_H2LE_U32(facs_addr);
643 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
644 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
645 fadt.u8PreferredPMProfile = 0; /* unspecified */
646 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
647 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
648 fadt.u8AcpiEnable = ACPI_ENABLE;
649 fadt.u8AcpiDisable = ACPI_DISABLE;
650 fadt.u8S4BIOSReq = 0;
651 fadt.u8PStateCnt = 0;
652 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
653 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
654 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
655 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
656 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
657 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
658 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
659 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
660 fadt.u8PM1EVTLEN = 4;
661 fadt.u8PM1CTLLEN = 2;
662 fadt.u8PM2CTLLEN = 0;
663 fadt.u8PMTMLEN = 4;
664 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
665 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
666 fadt.u8GPE1BASE = GPE1_BASE;
667 fadt.u8CSTCNT = 0;
668 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
669 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
670 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
671 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
672 fadt.u8DutyOffset = 0;
673 fadt.u8DutyWidth = 0;
674 fadt.u8DayAlarm = 0;
675 fadt.u8MonAlarm = 0;
676 fadt.u8Century = 0;
677 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
678 /** @note WBINVD is required for ACPI versions newer than 1.0 */
679 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
680 | FADT_FL_FIX_RTC
681 | FADT_FL_TMR_VAL_EXT);
682 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
683 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
684 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
685 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
686 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
687 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
688 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
689 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
690 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
691 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
692 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
693 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
694 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, sizeof(fadt));
695 acpiPhyscpy(s, addr, &fadt, sizeof(fadt));
696}
697
698/**
699 * Root System Description Table.
700 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
701 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
702 */
703static int acpiSetupRSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
704{
705 ACPITBLRSDT *rsdt;
706 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
707
708 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
709 if (!rsdt)
710 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
711
712 acpiPrepareHeader(&rsdt->header, "RSDT", (uint32_t)size, 1);
713 for (unsigned int i = 0; i < nb_entries; ++i)
714 {
715 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
716 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
717 }
718 rsdt->header.u8Checksum = acpiChecksum((uint8_t*)rsdt, size);
719 acpiPhyscpy(s, addr, rsdt, size);
720 RTMemFree(rsdt);
721 return VINF_SUCCESS;
722}
723
724/** Extended System Description Table. */
725static int acpiSetupXSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
726{
727 ACPITBLXSDT *xsdt;
728 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
729
730 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
731 if (!xsdt)
732 return VERR_NO_TMP_MEMORY;
733
734 acpiPrepareHeader(&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
735 for (unsigned int i = 0; i < nb_entries; ++i)
736 {
737 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
738 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
739 }
740 xsdt->header.u8Checksum = acpiChecksum((uint8_t*)xsdt, size);
741 acpiPhyscpy(s, addr, xsdt, size);
742 RTMemFree(xsdt);
743 return VINF_SUCCESS;
744}
745
746/** Root System Description Pointer (RSDP) */
747static void acpiSetupRSDP(ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
748{
749 memset(rsdp, 0, sizeof(*rsdp));
750
751 /* ACPI 1.0 part (RSDT */
752 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
753 memcpy(rsdp->au8OemId, "VBOX ", 6);
754 rsdp->u8Revision = ACPI_REVISION;
755 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
756 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
757
758 /* ACPI 2.0 part (XSDT) */
759 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
760 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
761 rsdp->u8ExtChecksum = acpiChecksum((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
762}
763
764/**
765 * Multiple APIC Description Table.
766 *
767 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both
768 *
769 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
770 */
771static void acpiSetupMADT(ACPIState *s, RTGCPHYS32 addr)
772{
773 uint16_t cpus = s->cCpus;
774 AcpiTableMADT madt(cpus);
775
776 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
777
778 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
779 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
780
781 ACPITBLLAPIC* lapic = madt.LApics_addr();
782 for (uint16_t i = 0; i < cpus; i++)
783 {
784 lapic->u8Type = 0;
785 lapic->u8Length = sizeof(ACPITBLLAPIC);
786 lapic->u8ProcId = i;
787 lapic->u8ApicId = i;
788 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
789 lapic++;
790 }
791
792 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
793
794 ioapic->u8Type = 1;
795 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
796 ioapic->u8IOApicId = cpus;
797 ioapic->u8Reserved = 0;
798 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
799 ioapic->u32GSIB = RT_H2LE_U32(0);
800
801 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
802 acpiPhyscpy(s, addr, madt.data(), madt.size());
803}
804
805/* SCI IRQ */
806DECLINLINE(void) acpiSetIrq(ACPIState *s, int level)
807{
808 if (s->pm1a_ctl & SCI_EN)
809 PDMDevHlpPCISetIrq(s->pDevIns, -1, level);
810}
811
812DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
813{
814 return en & ~(RSR_EN | IGN_EN);
815}
816
817DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
818{
819 return sts & ~(RSR_STS | IGN_STS);
820}
821
822DECLINLINE(int) pm1a_level(ACPIState *s)
823{
824 return (pm1a_pure_en(s->pm1a_en) & pm1a_pure_sts(s->pm1a_sts)) != 0;
825}
826
827DECLINLINE(int) gpe0_level(ACPIState *s)
828{
829 return (s->gpe0_en & s->gpe0_sts) != 0;
830}
831
832static void update_pm1a(ACPIState *s, uint32_t sts, uint32_t en)
833{
834 int old_level, new_level;
835
836 if (gpe0_level(s))
837 return;
838
839 old_level = pm1a_level(s);
840 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
841
842 s->pm1a_en = en;
843 s->pm1a_sts = sts;
844
845 if (new_level != old_level)
846 acpiSetIrq(s, new_level);
847}
848
849static void update_gpe0(ACPIState *s, uint32_t sts, uint32_t en)
850{
851 int old_level, new_level;
852
853 if (pm1a_level(s))
854 return;
855
856 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
857 new_level = (en & sts) != 0;
858
859 s->gpe0_en = en;
860 s->gpe0_sts = sts;
861
862 if (new_level != old_level)
863 acpiSetIrq(s, new_level);
864}
865
866static int acpiPowerDown(ACPIState *s)
867{
868 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
869 if (RT_FAILURE(rc))
870 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
871 return rc;
872}
873
874/** Converts a ACPI port interface pointer to an ACPI state pointer. */
875#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
876
877/**
878 * Send an ACPI power off event.
879 *
880 * @returns VBox status code
881 * @param pInterface Pointer to the interface structure containing the called function pointer.
882 */
883static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
884{
885 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
886 s->fPowerButtonHandled = false;
887 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
888 return VINF_SUCCESS;
889}
890
891/**
892 * Check if the ACPI power button event was handled.
893 *
894 * @returns VBox status code
895 * @param pInterface Pointer to the interface structure containing the called function pointer.
896 * @param pfHandled Return true if the power button event was handled by the guest.
897 */
898static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
899{
900 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
901 *pfHandled = s->fPowerButtonHandled;
902 return VINF_SUCCESS;
903}
904
905/**
906 * Check if the Guest entered into G0 (working) or G1 (sleeping).
907 *
908 * @returns VBox status code
909 * @param pInterface Pointer to the interface structure containing the called function pointer.
910 * @param pfEntered Return true if the guest entered the ACPI mode.
911 */
912static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
913{
914 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
915 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
916 return VINF_SUCCESS;
917}
918
919/**
920 * Send an ACPI sleep button event.
921 *
922 * @returns VBox status code
923 * @param pInterface Pointer to the interface structure containing the called function pointer.
924 */
925static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
926{
927 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
928 update_pm1a(s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
929 return VINF_SUCCESS;
930}
931
932/* PM1a_EVT_BLK enable */
933static uint32_t acpiPm1aEnReadw(ACPIState *s, uint32_t addr)
934{
935 uint16_t val = s->pm1a_en;
936 Log(("acpi: acpiPm1aEnReadw -> %#x\n", val));
937 return val;
938}
939
940static void acpiPM1aEnWritew(ACPIState *s, uint32_t addr, uint32_t val)
941{
942 Log(("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
943 val &= ~(RSR_EN | IGN_EN);
944 update_pm1a(s, s->pm1a_sts, val);
945}
946
947/* PM1a_EVT_BLK status */
948static uint32_t acpiPm1aStsReadw(ACPIState *s, uint32_t addr)
949{
950 uint16_t val = s->pm1a_sts;
951 Log(("acpi: acpiPm1aStsReadw -> %#x\n", val));
952 return val;
953}
954
955static void acpiPM1aStsWritew(ACPIState *s, uint32_t addr, uint32_t val)
956{
957 Log(("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
958 if (val & PWRBTN_STS)
959 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
960 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
961 update_pm1a(s, val, s->pm1a_en);
962}
963
964/* PM1a_CTL_BLK */
965static uint32_t acpiPm1aCtlReadw(ACPIState *s, uint32_t addr)
966{
967 uint16_t val = s->pm1a_ctl;
968 Log(("acpi: acpiPm1aCtlReadw -> %#x\n", val));
969 return val;
970}
971
972static int acpiPM1aCtlWritew(ACPIState *s, uint32_t addr, uint32_t val)
973{
974 uint32_t uSleepState;
975
976 Log(("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
977 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
978
979 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
980 if (uSleepState != s->uSleepState)
981 {
982 s->uSleepState = uSleepState;
983 switch (uSleepState)
984 {
985 case 0x00: /* S0 */
986 break;
987 case 0x05: /* S5 */
988 LogRel(("Entering S5 (power down)\n"));
989 return acpiPowerDown(s);
990 default:
991 AssertMsgFailed(("Unknown sleep state %#x\n", uSleepState));
992 break;
993 }
994 }
995 return VINF_SUCCESS;
996}
997
998/* GPE0_BLK */
999static uint32_t acpiGpe0EnReadb(ACPIState *s, uint32_t addr)
1000{
1001 uint8_t val = s->gpe0_en;
1002 Log(("acpi: acpiGpe0EnReadl -> %#x\n", val));
1003 return val;
1004}
1005
1006static void acpiGpe0EnWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1007{
1008 Log(("acpi: acpiGpe0EnWritel <- %#x\n", val));
1009 update_gpe0(s, s->gpe0_sts, val);
1010}
1011
1012static uint32_t acpiGpe0StsReadb(ACPIState *s, uint32_t addr)
1013{
1014 uint8_t val = s->gpe0_sts;
1015 Log(("acpi: acpiGpe0StsReadl -> %#x\n", val));
1016 return val;
1017}
1018
1019static void acpiGpe0StsWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1020{
1021 val = s->gpe0_sts & ~val;
1022 update_gpe0(s, val, s->gpe0_en);
1023 Log(("acpi: acpiGpe0StsWritel <- %#x\n", val));
1024}
1025
1026static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1027{
1028 int rc = VINF_SUCCESS;
1029
1030 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1031 if (val == ACPI_RESET_REG_VAL)
1032 {
1033# ifndef IN_RING3
1034 rc = VINF_IOM_HC_IOPORT_WRITE;
1035# else /* IN_RING3 */
1036 rc = PDMDevHlpVMReset(s->pDevIns);
1037# endif /* !IN_RING3 */
1038 }
1039 return rc;
1040}
1041
1042/* SMI */
1043static void acpiSmiWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1044{
1045 Log(("acpi: acpiSmiWriteU8 %#x\n", val));
1046 if (val == ACPI_ENABLE)
1047 s->pm1a_ctl |= SCI_EN;
1048 else if (val == ACPI_DISABLE)
1049 s->pm1a_ctl &= ~SCI_EN;
1050 else
1051 Log(("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1052}
1053
1054static uint32_t find_rsdp_space(void)
1055{
1056 return 0xe0000;
1057}
1058
1059static void acpiPMTimerReset(ACPIState *s)
1060{
1061 uint64_t interval, freq;
1062
1063 freq = TMTimerGetFreq(s->CTX_SUFF(ts));
1064 interval = ASMMultU64ByU32DivByU32(0xffffffff, freq, PM_TMR_FREQ);
1065 Log(("interval = %RU64\n", interval));
1066 TMTimerSet(s->CTX_SUFF(ts), TMTimerGet(s->CTX_SUFF(ts)) + interval);
1067}
1068
1069static DECLCALLBACK(void) acpiTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1070{
1071 ACPIState *s = (ACPIState *)pvUser;
1072
1073 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1074 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1075 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1076
1077 update_pm1a(s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1078 acpiPMTimerReset(s);
1079}
1080
1081/**
1082 * _BST method.
1083 */
1084static void acpiFetchBatteryStatus(ACPIState *s)
1085{
1086 uint32_t *p = s->au8BatteryInfo;
1087 bool fPresent; /* battery present? */
1088 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1089 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1090 uint32_t hostPresentRate; /* 0..1000 */
1091 int rc;
1092
1093 if (!s->pDrv)
1094 return;
1095 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1096 &hostBatteryState, &hostPresentRate);
1097 AssertRC(rc);
1098
1099 /* default values */
1100 p[BAT_STATUS_STATE] = hostBatteryState;
1101 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1102 : hostPresentRate * 50; /* mW */
1103 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1104 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1105
1106 /* did we get a valid battery state? */
1107 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1108 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1109 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1110 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1111}
1112
1113/**
1114 * _BIF method.
1115 */
1116static void acpiFetchBatteryInfo(ACPIState *s)
1117{
1118 uint32_t *p = s->au8BatteryInfo;
1119
1120 p[BAT_INFO_UNITS] = 0; /* mWh */
1121 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1122 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1123 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1124 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1125 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1126 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1127 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1128 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1129}
1130
1131/**
1132 * _STA method.
1133 */
1134static uint32_t acpiGetBatteryDeviceStatus(ACPIState *s)
1135{
1136 bool fPresent; /* battery present? */
1137 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1138 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1139 uint32_t hostPresentRate; /* 0..1000 */
1140 int rc;
1141
1142 if (!s->pDrv)
1143 return 0;
1144 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1145 &hostBatteryState, &hostPresentRate);
1146 AssertRC(rc);
1147
1148 return fPresent
1149 ? STA_DEVICE_PRESENT_MASK /* present */
1150 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1151 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1152 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1153 | STA_BATTERY_PRESENT_MASK /* battery is present */
1154 : 0; /* device not present */
1155}
1156
1157static uint32_t acpiGetPowerSource(ACPIState *s)
1158{
1159 PDMACPIPOWERSOURCE ps;
1160
1161 /* query the current power source from the host driver */
1162 if (!s->pDrv)
1163 return AC_ONLINE;
1164 int rc = s->pDrv->pfnQueryPowerSource(s->pDrv, &ps);
1165 AssertRC(rc);
1166 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1167}
1168
1169PDMBOTHCBDECL(int) acpiBatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1170{
1171 ACPIState *s = (ACPIState *)pvUser;
1172
1173 switch (cb)
1174 {
1175 case 4:
1176 u32 >>= s->u8IndexShift;
1177 /* see comment at the declaration of u8IndexShift */
1178 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1179 {
1180 s->u8IndexShift = 2;
1181 u32 >>= 2;
1182 }
1183 Assert(u32 < BAT_INDEX_LAST);
1184 s->uBatteryIndex = u32;
1185 break;
1186 default:
1187 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1188 break;
1189 }
1190 return VINF_SUCCESS;
1191}
1192
1193PDMBOTHCBDECL(int) acpiBatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1194{
1195 ACPIState *s = (ACPIState *)pvUser;
1196
1197 switch (cb)
1198 {
1199 case 4:
1200 switch (s->uBatteryIndex)
1201 {
1202 case BAT_STATUS_STATE:
1203 acpiFetchBatteryStatus(s);
1204 case BAT_STATUS_PRESENT_RATE:
1205 case BAT_STATUS_REMAINING_CAPACITY:
1206 case BAT_STATUS_PRESENT_VOLTAGE:
1207 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1208 break;
1209
1210 case BAT_INFO_UNITS:
1211 acpiFetchBatteryInfo(s);
1212 case BAT_INFO_DESIGN_CAPACITY:
1213 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1214 case BAT_INFO_TECHNOLOGY:
1215 case BAT_INFO_DESIGN_VOLTAGE:
1216 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1217 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1218 case BAT_INFO_CAPACITY_GRANULARITY_1:
1219 case BAT_INFO_CAPACITY_GRANULARITY_2:
1220 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1221 break;
1222
1223 case BAT_DEVICE_STATUS:
1224 *pu32 = acpiGetBatteryDeviceStatus(s);
1225 break;
1226
1227 case BAT_POWER_SOURCE:
1228 *pu32 = acpiGetPowerSource(s);
1229 break;
1230
1231 default:
1232 AssertMsgFailed(("Invalid battery index %d\n", s->uBatteryIndex));
1233 break;
1234 }
1235 break;
1236 default:
1237 return VERR_IOM_IOPORT_UNUSED;
1238 }
1239 return VINF_SUCCESS;
1240}
1241
1242PDMBOTHCBDECL(int) acpiSysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1243{
1244 ACPIState *s = (ACPIState *)pvUser;
1245
1246 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1247 switch (cb)
1248 {
1249 case 4:
1250 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1251 s->uSystemInfoIndex = u32;
1252 else
1253 {
1254 /* see comment at the declaration of u8IndexShift */
1255 if (s->u8IndexShift == 0)
1256 {
1257 if (((u32 >> 2) < SYSTEM_INFO_INDEX_END) && ((u32 & 0x3)) == 0)
1258 {
1259 s->u8IndexShift = 2;
1260 }
1261 }
1262
1263 u32 >>= s->u8IndexShift;
1264 Assert(u32 < SYSTEM_INFO_INDEX_END);
1265 s->uSystemInfoIndex = u32;
1266 }
1267 break;
1268
1269 default:
1270 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1271 break;
1272 }
1273 return VINF_SUCCESS;
1274}
1275
1276PDMBOTHCBDECL(int) acpiSysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1277{
1278 ACPIState *s = (ACPIState *)pvUser;
1279
1280 switch (cb)
1281 {
1282 case 4:
1283 switch (s->uSystemInfoIndex)
1284 {
1285 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1286 *pu32 = s->cbRamLow;
1287 break;
1288
1289 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1290 *pu32 = s->cbRamHigh >> 16; /* 64KB units */
1291 Assert(((uint64_t)*pu32 << 16) == s->cbRamHigh);
1292 break;
1293
1294 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1295 *pu32 = s->u8UseIOApic;
1296 break;
1297
1298 case SYSTEM_INFO_INDEX_HPET_STATUS:
1299 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1300 | STA_DEVICE_ENABLED_MASK
1301 | STA_DEVICE_SHOW_IN_UI_MASK
1302 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1303 : 0;
1304 break;
1305
1306 case SYSTEM_INFO_INDEX_SMC_STATUS:
1307 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1308 | STA_DEVICE_ENABLED_MASK
1309 /* no need to show this device in the UI */
1310 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1311 : 0;
1312 break;
1313
1314 case SYSTEM_INFO_INDEX_FDC_STATUS:
1315 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1316 | STA_DEVICE_ENABLED_MASK
1317 | STA_DEVICE_SHOW_IN_UI_MASK
1318 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1319 : 0;
1320 break;
1321
1322 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1323 *pu32 = s->fShowCpu
1324 ? STA_DEVICE_PRESENT_MASK
1325 | STA_DEVICE_ENABLED_MASK
1326 | STA_DEVICE_SHOW_IN_UI_MASK
1327 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK
1328 : 0;
1329 break;
1330
1331 case SYSTEM_INFO_INDEX_RTC_STATUS:
1332 *pu32 = s->fShowRtc ? ( STA_DEVICE_PRESENT_MASK
1333 | STA_DEVICE_ENABLED_MASK
1334 | STA_DEVICE_SHOW_IN_UI_MASK
1335 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1336 : 0;
1337 break;
1338
1339 /* Solaris 9 tries to read from this index */
1340 case SYSTEM_INFO_INDEX_INVALID:
1341 *pu32 = 0;
1342 break;
1343
1344 default:
1345 AssertMsgFailed(("Invalid system info index %d\n", s->uSystemInfoIndex));
1346 break;
1347 }
1348 break;
1349
1350 default:
1351 return VERR_IOM_IOPORT_UNUSED;
1352 }
1353
1354 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1355 return VINF_SUCCESS;
1356}
1357
1358PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1359{
1360 ACPIState *s = (ACPIState *)pvUser;
1361
1362 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1363
1364 if (cb == 4 && u32 == 0xbadc0de)
1365 {
1366 switch (s->uSystemInfoIndex)
1367 {
1368 case SYSTEM_INFO_INDEX_INVALID:
1369 s->u8IndexShift = 0;
1370 break;
1371
1372 case SYSTEM_INFO_INDEX_VALID:
1373 s->u8IndexShift = 2;
1374 break;
1375
1376 default:
1377 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1378 Port, cb, u32, s->uSystemInfoIndex));
1379 break;
1380 }
1381 }
1382 else
1383 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1384 return VINF_SUCCESS;
1385}
1386
1387/** @todo Don't call functions, but do the job in the read/write handlers
1388 * here! */
1389
1390/* IO Helpers */
1391PDMBOTHCBDECL(int) acpiPm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1392{
1393 switch (cb)
1394 {
1395 case 2:
1396 *pu32 = acpiPm1aEnReadw((ACPIState*)pvUser, Port);
1397 break;
1398 default:
1399 return VERR_IOM_IOPORT_UNUSED;
1400 }
1401 return VINF_SUCCESS;
1402}
1403
1404PDMBOTHCBDECL(int) acpiPm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1405{
1406 switch (cb)
1407 {
1408 case 2:
1409 *pu32 = acpiPm1aStsReadw((ACPIState*)pvUser, Port);
1410 break;
1411 default:
1412 return VERR_IOM_IOPORT_UNUSED;
1413 }
1414 return VINF_SUCCESS;
1415}
1416
1417PDMBOTHCBDECL(int) acpiPm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1418{
1419 switch (cb)
1420 {
1421 case 2:
1422 *pu32 = acpiPm1aCtlReadw((ACPIState*)pvUser, Port);
1423 break;
1424 default:
1425 return VERR_IOM_IOPORT_UNUSED;
1426 }
1427 return VINF_SUCCESS;
1428}
1429
1430PDMBOTHCBDECL(int) acpiPM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1431{
1432 switch (cb)
1433 {
1434 case 2:
1435 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32);
1436 break;
1437 default:
1438 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1439 break;
1440 }
1441 return VINF_SUCCESS;
1442}
1443
1444PDMBOTHCBDECL(int) acpiPM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1445{
1446 switch (cb)
1447 {
1448 case 2:
1449 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32);
1450 break;
1451 default:
1452 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1453 break;
1454 }
1455 return VINF_SUCCESS;
1456}
1457
1458PDMBOTHCBDECL(int) acpiPM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1459{
1460 switch (cb)
1461 {
1462 case 2:
1463 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32);
1464 default:
1465 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1466 break;
1467 }
1468 return VINF_SUCCESS;
1469}
1470
1471#endif /* IN_RING3 */
1472
1473/**
1474 * PMTMR readable from host/guest.
1475 */
1476PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1477{
1478 if (cb == 4)
1479 {
1480 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1481 int64_t now = TMTimerGet(s->CTX_SUFF(ts));
1482 int64_t elapsed = now - s->pm_timer_initial;
1483
1484 *pu32 = ASMMultU64ByU32DivByU32(elapsed, PM_TMR_FREQ, TMTimerGetFreq(s->CTX_SUFF(ts)));
1485 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1486 return VINF_SUCCESS;
1487 }
1488 return VERR_IOM_IOPORT_UNUSED;
1489}
1490
1491#ifdef IN_RING3
1492
1493PDMBOTHCBDECL(int) acpiGpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1494{
1495 switch (cb)
1496 {
1497 case 1:
1498 *pu32 = acpiGpe0StsReadb((ACPIState*)pvUser, Port);
1499 break;
1500 default:
1501 return VERR_IOM_IOPORT_UNUSED;
1502 }
1503 return VINF_SUCCESS;
1504}
1505
1506PDMBOTHCBDECL(int) acpiGpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1507{
1508 switch (cb)
1509 {
1510 case 1:
1511 *pu32 = acpiGpe0EnReadb((ACPIState*)pvUser, Port);
1512 break;
1513 default:
1514 return VERR_IOM_IOPORT_UNUSED;
1515 }
1516 return VINF_SUCCESS;
1517}
1518
1519PDMBOTHCBDECL(int) acpiGpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1520{
1521 switch (cb)
1522 {
1523 case 1:
1524 acpiGpe0StsWriteb((ACPIState*)pvUser, Port, u32);
1525 break;
1526 default:
1527 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1528 break;
1529 }
1530 return VINF_SUCCESS;
1531}
1532
1533PDMBOTHCBDECL(int) acpiGpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1534{
1535 switch (cb)
1536 {
1537 case 1:
1538 acpiGpe0EnWriteb((ACPIState*)pvUser, Port, u32);
1539 break;
1540 default:
1541 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1542 break;
1543 }
1544 return VINF_SUCCESS;
1545}
1546
1547PDMBOTHCBDECL(int) acpiSmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1548{
1549 switch (cb)
1550 {
1551 case 1:
1552 acpiSmiWriteU8((ACPIState*)pvUser, Port, u32);
1553 break;
1554 default:
1555 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1556 break;
1557 }
1558 return VINF_SUCCESS;
1559}
1560
1561PDMBOTHCBDECL(int) acpiResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1562{
1563 switch (cb)
1564 {
1565 case 1:
1566 return acpiResetWriteU8((ACPIState*)pvUser, Port, u32);
1567 default:
1568 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1569 break;
1570 }
1571 return VINF_SUCCESS;
1572}
1573
1574#ifdef DEBUG_ACPI
1575
1576PDMBOTHCBDECL(int) acpiDhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1577{
1578 switch (cb)
1579 {
1580 case 1:
1581 Log(("%#x\n", u32 & 0xff));
1582 break;
1583 case 2:
1584 Log(("%#6x\n", u32 & 0xffff));
1585 case 4:
1586 Log(("%#10x\n", u32));
1587 break;
1588 default:
1589 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1590 break;
1591 }
1592 return VINF_SUCCESS;
1593}
1594
1595PDMBOTHCBDECL(int) acpiDchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1596{
1597 switch (cb)
1598 {
1599 case 1:
1600 Log(("%c", u32 & 0xff));
1601 break;
1602 default:
1603 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1604 break;
1605 }
1606 return VINF_SUCCESS;
1607}
1608
1609#endif /* DEBUG_ACPI */
1610
1611
1612/**
1613 * Saved state structure description.
1614 */
1615static const SSMFIELD g_AcpiSavedStateFields[] =
1616{
1617 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1618 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1619 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1620 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1621 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1622 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1623 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1624 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1625 SSMFIELD_ENTRY(ACPIState, u64RamSize), /** @todo not necessary to save this. */
1626 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1627 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1628 SSMFIELD_ENTRY(ACPIState, uSleepState),
1629 SSMFIELD_ENTRY_TERM()
1630};
1631
1632static DECLCALLBACK(int) acpi_save_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1633{
1634 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1635 return SSMR3PutStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1636}
1637
1638static DECLCALLBACK(int) acpi_load_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1639 uint32_t u32Version)
1640{
1641 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1642 int rc;
1643
1644 if (u32Version != 4)
1645 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1646
1647 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1648 if (RT_SUCCESS(rc))
1649 {
1650 acpiFetchBatteryStatus(s);
1651 acpiFetchBatteryInfo(s);
1652 acpiPMTimerReset(s);
1653 }
1654 return rc;
1655}
1656
1657/**
1658 * Queries an interface to the driver.
1659 *
1660 * @returns Pointer to interface.
1661 * @returns NULL if the interface was not supported by the driver.
1662 * @param pInterface Pointer to this interface structure.
1663 * @param enmInterface The requested interface identification.
1664 * @thread Any thread.
1665 */
1666static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1667{
1668 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1669 switch (enmInterface)
1670 {
1671 case PDMINTERFACE_BASE:
1672 return &pThis->IBase;
1673 case PDMINTERFACE_ACPI_PORT:
1674 return &pThis->IACPIPort;
1675 default:
1676 return NULL;
1677 }
1678}
1679
1680/**
1681 * Create the ACPI tables.
1682 */
1683static int acpiPlantTables(ACPIState *s)
1684{
1685 int rc;
1686 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1687 uint32_t addend = 0;
1688 RTGCPHYS32 rsdt_addrs[4];
1689 uint32_t cAddr;
1690 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1691 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1692
1693 cAddr = 1; /* FADT */
1694 if (s->u8UseIOApic)
1695 cAddr++; /* MADT */
1696
1697 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1698 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1699
1700 rc = CFGMR3QueryU64(s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1701 if (RT_FAILURE(rc))
1702 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1703 N_("Configuration error: Querying "
1704 "\"RamSize\" as integer failed"));
1705
1706 uint32_t cbRamHole;
1707 rc = CFGMR3QueryU32Def(s->pDevIns->pCfgHandle, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1708 if (RT_FAILURE(rc))
1709 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1710 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
1711
1712 /*
1713 * Calc the sizes for the high and low regions.
1714 */
1715 const uint64_t offRamHole = _4G - cbRamHole;
1716 s->cbRamHigh = offRamHole < s->u64RamSize ? s->u64RamSize - offRamHole : 0;
1717 uint64_t cbRamLow = offRamHole < s->u64RamSize ? offRamHole : s->u64RamSize;
1718 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
1719 {
1720 /* Note: This is also enforced by DevPcBios.cpp. */
1721 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
1722 cbRamLow = UINT32_C(0xffe00000);
1723 }
1724 s->cbRamLow = (uint32_t)cbRamLow;
1725
1726 rsdt_addr = 0;
1727 xsdt_addr = RT_ALIGN_32(rsdt_addr + rsdt_tbl_len, 16);
1728 fadt_addr = RT_ALIGN_32(xsdt_addr + xsdt_tbl_len, 16);
1729 facs_addr = RT_ALIGN_32(fadt_addr + sizeof(ACPITBLFADT), 16);
1730 if (s->u8UseIOApic)
1731 {
1732 apic_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1733 /**
1734 * @todo nike: maybe some refactoring needed to compute tables layout,
1735 * but as this code is executed only once it doesn't make sense to optimize much
1736 */
1737 dsdt_addr = RT_ALIGN_32(apic_addr + AcpiTableMADT::sizeFor(s), 16);
1738 }
1739 else
1740 {
1741 dsdt_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1742 }
1743
1744 void* pDsdtCode = NULL;
1745 size_t uDsdtSize = 0;
1746 rc = acpiPrepareDsdt(s->pDevIns, &pDsdtCode, &uDsdtSize);
1747 if (RT_FAILURE(rc))
1748 return rc;
1749
1750 last_addr = RT_ALIGN_32(dsdt_addr + uDsdtSize, 16);
1751 if (last_addr > 0x10000)
1752 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1753 N_("Error: ACPI tables > 64KB"));
1754
1755 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1756 addend = s->cbRamLow - 0x10000;
1757 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1758 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1759 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1760 acpiSetupRSDP((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1761 acpiSetupDSDT(s, dsdt_addr + addend, pDsdtCode, uDsdtSize);
1762 acpiCleanupDsdt(s->pDevIns, pDsdtCode);
1763 acpiSetupFACS(s, facs_addr + addend);
1764 acpiSetupFADT(s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1765
1766 rsdt_addrs[0] = fadt_addr + addend;
1767 if (s->u8UseIOApic)
1768 {
1769 acpiSetupMADT(s, apic_addr + addend);
1770 rsdt_addrs[1] = apic_addr + addend;
1771 }
1772
1773 rc = acpiSetupRSDT(s, rsdt_addr + addend, cAddr, rsdt_addrs);
1774 if (RT_FAILURE(rc))
1775 return rc;
1776 return acpiSetupXSDT(s, xsdt_addr + addend, cAddr, rsdt_addrs);
1777}
1778
1779/**
1780 * Construct a device instance for a VM.
1781 *
1782 * @returns VBox status.
1783 * @param pDevIns The device instance data.
1784 * If the registration structure is needed, pDevIns->pDevReg points to it.
1785 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1786 * The device number is also found in pDevIns->iInstance, but since it's
1787 * likely to be freqently used PDM passes it as parameter.
1788 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1789 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1790 * iInstance it's expected to be used a bit in this function.
1791 */
1792static DECLCALLBACK(int) acpiConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1793{
1794 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1795 PCIDevice *dev = &s->dev;
1796
1797 /* Validate and read the configuration. */
1798 if (!CFGMR3AreValuesValid(pCfgHandle,
1799 "RamSize\0"
1800 "RamHoleSize\0"
1801 "IOAPIC\0"
1802 "NumCPUs\0"
1803 "GCEnabled\0"
1804 "R0Enabled\0"
1805 "HpetEnabled\0"
1806 "SmcEnabled\0"
1807 "FdcEnabled\0"
1808 "ShowRtc\0"
1809 "ShowCpu\0"
1810 ))
1811 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1812 N_("Configuration error: Invalid config key for ACPI device"));
1813
1814 s->pDevIns = pDevIns;
1815
1816 /* query whether we are supposed to present an IOAPIC */
1817 int rc = CFGMR3QueryU8Def(pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
1818 if (RT_FAILURE(rc))
1819 return PDMDEV_SET_ERROR(pDevIns, rc,
1820 N_("Configuration error: Failed to read \"IOAPIC\""));
1821
1822 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
1823 if (RT_FAILURE(rc))
1824 return PDMDEV_SET_ERROR(pDevIns, rc,
1825 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
1826
1827 /* query whether we are supposed to present an FDC controller */
1828 rc = CFGMR3QueryBoolDef(pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
1829 if (RT_FAILURE(rc))
1830 return PDMDEV_SET_ERROR(pDevIns, rc,
1831 N_("Configuration error: Failed to read \"FdcEnabled\""));
1832
1833 /* query whether we are supposed to present HPET */
1834 rc = CFGMR3QueryBoolDef(pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
1835 if (RT_FAILURE(rc))
1836 return PDMDEV_SET_ERROR(pDevIns, rc,
1837 N_("Configuration error: Failed to read \"HpetEnabled\""));
1838 /* query whether we are supposed to present SMC */
1839 rc = CFGMR3QueryBoolDef(pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
1840 if (RT_FAILURE(rc))
1841 return PDMDEV_SET_ERROR(pDevIns, rc,
1842 N_("Configuration error: Failed to read \"SmcEnabled\""));
1843
1844 /* query whether we are supposed to present RTC object */
1845 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowRtc", &s->fShowRtc, false);
1846 if (RT_FAILURE(rc))
1847 return PDMDEV_SET_ERROR(pDevIns, rc,
1848 N_("Configuration error: Failed to read \"ShowRtc\""));
1849
1850 /* query whether we are supposed to present CPU objects */
1851 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowCpu", &s->fShowCpu, false);
1852 if (RT_FAILURE(rc))
1853 return PDMDEV_SET_ERROR(pDevIns, rc,
1854 N_("Configuration error: Failed to read \"ShowCpu\""));
1855
1856 /* Always show the CPU leafs when we have multiple VCPUs or when the IO-APIC is enabled.
1857 * The Windows SMP kernel needs a CPU leaf or else its idle loop will burn cpu cycles; the
1858 * intelppm driver refuses to register an idle state handler.
1859 */
1860 if ( s->cCpus > 1
1861 || s->u8UseIOApic)
1862 s->fShowCpu = true;
1863
1864 bool fGCEnabled;
1865 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1866 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1867 fGCEnabled = true;
1868 else if (RT_FAILURE(rc))
1869 return PDMDEV_SET_ERROR(pDevIns, rc,
1870 N_("Configuration error: Failed to read \"GCEnabled\""));
1871
1872 bool fR0Enabled;
1873 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1874 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1875 fR0Enabled = true;
1876 else if (RT_FAILURE(rc))
1877 return PDMDEV_SET_ERROR(pDevIns, rc,
1878 N_("configuration error: failed to read R0Enabled as boolean"));
1879
1880 /* */
1881 uint32_t rsdp_addr = find_rsdp_space();
1882 if (!rsdp_addr)
1883 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1884 N_("Can not find space for RSDP. ACPI is disabled"));
1885
1886 rc = acpiPlantTables(s);
1887 if (RT_FAILURE(rc))
1888 return rc;
1889
1890 rc = PDMDevHlpROMRegister(pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage,
1891 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
1892 if (RT_FAILURE(rc))
1893 return rc;
1894
1895#define R(addr, cnt, writer, reader, description) \
1896 do { \
1897 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, s, writer, reader, \
1898 NULL, NULL, description); \
1899 if (RT_FAILURE(rc)) \
1900 return rc; \
1901 } while (0)
1902#define L (GPE0_BLK_LEN / 2)
1903
1904 R(PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1905 R(PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1906 R(PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1907 R(PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1908 R(SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1909#ifdef DEBUG_ACPI
1910 R(DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1911 R(DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1912#endif
1913 R(BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1914 R(BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1915 R(SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1916 R(SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1917 R(GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1918 R(GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1919 R(ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1920#undef L
1921#undef R
1922
1923 /* register GC stuff */
1924 if (fGCEnabled)
1925 {
1926 rc = PDMDevHlpIOPortRegisterGC(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1927 NULL, NULL, "ACPI PM Timer");
1928 AssertRCReturn(rc, rc);
1929 }
1930
1931 /* register R0 stuff */
1932 if (fR0Enabled)
1933 {
1934 rc = PDMDevHlpIOPortRegisterR0(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1935 NULL, NULL, "ACPI PM Timer");
1936 AssertRCReturn(rc, rc);
1937 }
1938
1939 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, dev,
1940 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "ACPI Timer", &s->tsR3);
1941 if (RT_FAILURE(rc))
1942 {
1943 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1944 return rc;
1945 }
1946
1947 s->tsR0 = TMTimerR0Ptr(s->tsR3);
1948 s->tsRC = TMTimerRCPtr(s->tsR3);
1949 s->pm_timer_initial = TMTimerGet(s->tsR3);
1950 acpiPMTimerReset(s);
1951
1952 PCIDevSetVendorId(dev, 0x8086); /* Intel */
1953 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
1954
1955 dev->config[0x04] = 0x01; /* command */
1956 dev->config[0x05] = 0x00;
1957
1958 dev->config[0x06] = 0x80; /* status */
1959 dev->config[0x07] = 0x02;
1960 dev->config[0x08] = 0x08;
1961 dev->config[0x09] = 0x00;
1962
1963 dev->config[0x0a] = 0x80;
1964 dev->config[0x0b] = 0x06;
1965
1966 dev->config[0x0e] = 0x80;
1967 dev->config[0x0f] = 0x00;
1968
1969#if 0 /* The ACPI controller usually has no subsystem ID. */
1970 dev->config[0x2c] = 0x86;
1971 dev->config[0x2d] = 0x80;
1972 dev->config[0x2e] = 0x00;
1973 dev->config[0x2f] = 0x00;
1974#endif
1975 dev->config[0x3c] = SCI_INT;
1976
1977 rc = PDMDevHlpPCIRegister(pDevIns, dev);
1978 if (RT_FAILURE(rc))
1979 return rc;
1980
1981 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1982 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1983 if (RT_FAILURE(rc))
1984 return rc;
1985
1986 /*
1987 * Interfaces
1988 */
1989 /* IBase */
1990 s->IBase.pfnQueryInterface = acpiQueryInterface;
1991 /* IACPIPort */
1992 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1993 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1994 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1995 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
1996
1997 /*
1998 * Get the corresponding connector interface
1999 */
2000 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
2001 if (RT_SUCCESS(rc))
2002 {
2003 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface(s->pDrvBase, PDMINTERFACE_ACPI_CONNECTOR);
2004 if (!s->pDrv)
2005 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
2006 N_("LUN #0 doesn't have an ACPI connector interface"));
2007 }
2008 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2009 {
2010 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2011 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2012 rc = VINF_SUCCESS;
2013 }
2014 else
2015 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
2016
2017 return rc;
2018}
2019
2020/**
2021 * Relocates the GC pointer members.
2022 */
2023static DECLCALLBACK(void) acpiRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2024{
2025 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2026 s->tsRC = TMTimerRCPtr(s->CTX_SUFF(ts));
2027}
2028
2029static DECLCALLBACK(void) acpiReset(PPDMDEVINS pDevIns)
2030{
2031 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2032
2033 s->pm1a_en = 0;
2034 s->pm1a_sts = 0;
2035 s->pm1a_ctl = 0;
2036 s->pm_timer_initial = TMTimerGet(s->CTX_SUFF(ts));
2037 acpiPMTimerReset(s);
2038 s->uBatteryIndex = 0;
2039 s->uSystemInfoIndex = 0;
2040 s->gpe0_en = 0;
2041 s->gpe0_sts = 0;
2042 s->uSleepState = 0;
2043
2044 acpiPlantTables(s);
2045}
2046
2047/**
2048 * The device registration structure.
2049 */
2050const PDMDEVREG g_DeviceACPI =
2051{
2052 /* u32Version */
2053 PDM_DEVREG_VERSION,
2054 /* szDeviceName */
2055 "acpi",
2056 /* szRCMod */
2057 "VBoxDDGC.gc",
2058 /* szR0Mod */
2059 "VBoxDDR0.r0",
2060 /* pszDescription */
2061 "Advanced Configuration and Power Interface",
2062 /* fFlags */
2063 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2064 /* fClass */
2065 PDM_DEVREG_CLASS_ACPI,
2066 /* cMaxInstances */
2067 ~0,
2068 /* cbInstance */
2069 sizeof(ACPIState),
2070 /* pfnConstruct */
2071 acpiConstruct,
2072 /* pfnDestruct */
2073 NULL,
2074 /* pfnRelocate */
2075 acpiRelocate,
2076 /* pfnIOCtl */
2077 NULL,
2078 /* pfnPowerOn */
2079 NULL,
2080 /* pfnReset */
2081 acpiReset,
2082 /* pfnSuspend */
2083 NULL,
2084 /* pfnResume */
2085 NULL,
2086 /* pfnAttach */
2087 NULL,
2088 /* pfnDetach */
2089 NULL,
2090 /* pfnQueryInterface. */
2091 NULL,
2092 /* pfnInitComplete */
2093 NULL,
2094 /* pfnPowerOff */
2095 NULL,
2096 /* pfnSoftReset */
2097 NULL,
2098 /* u32VersionEnd */
2099 PDM_DEVREG_VERSION
2100};
2101
2102#endif /* IN_RING3 */
2103#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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