VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 21855

Last change on this file since 21855 was 21855, checked in by vboxsync, 15 years ago

ACPI PM device: a bit more of refactoring and logging
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1/* $Id: DevACPI.cpp 21855 2009-07-28 16:43:30Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_ACPI
26#include <VBox/pdmdev.h>
27#include <VBox/pgm.h>
28#include <VBox/log.h>
29#include <VBox/param.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35#endif /* IN_RING3 */
36
37#include "../Builtins.h"
38
39#ifdef LOG_ENABLED
40# define DEBUG_ACPI
41#endif
42
43#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
44int acpiPrepareDsdt(PPDMDEVINS pDevIns, void* *ppPtr, size_t *puDsdtLen);
45int acpiCleanupDsdt(PPDMDEVINS pDevIns, void* pPtr);
46#endif /* !IN_RING3 */
47
48
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53#define DEBUG_HEX 0x3000
54#define DEBUG_CHR 0x3001
55
56#define PM_TMR_FREQ 3579545
57/* Default base for PM PIIX4 device */
58#define PM_PORT_BASE 0x4000
59/* Port offsets in PM device */
60enum
61{
62 PM1a_EVT_OFFSET = 0x00,
63 PM1b_EVT_OFFSET = -1, /**< not supported */
64 PM1a_CTL_OFFSET = 0x04,
65 PM1b_CTL_OFFSET = -1, /**< not supported */
66 PM2_CTL_OFFSET = -1, /**< not supported */
67 PM_TMR_OFFSET = 0x08,
68 GPE0_OFFSET = 0x20,
69 GPE1_OFFSET = -1 /**< not supported */
70};
71
72#define BAT_INDEX 0x00004040
73#define BAT_DATA 0x00004044
74#define SYSI_INDEX 0x00004048
75#define SYSI_DATA 0x0000404c
76#define ACPI_RESET_BLK 0x00004050
77
78/* PM1x status register bits */
79#define TMR_STS RT_BIT(0)
80#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
81#define BM_STS RT_BIT(4)
82#define GBL_STS RT_BIT(5)
83#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
84#define PWRBTN_STS RT_BIT(8)
85#define SLPBTN_STS RT_BIT(9)
86#define RTC_STS RT_BIT(10)
87#define IGN_STS RT_BIT(11)
88#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
89#define WAK_STS RT_BIT(15)
90#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
91
92/* PM1x enable register bits */
93#define TMR_EN RT_BIT(0)
94#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
95#define GBL_EN RT_BIT(5)
96#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
97#define PWRBTN_EN RT_BIT(8)
98#define SLPBTN_EN RT_BIT(9)
99#define RTC_EN RT_BIT(10)
100#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
101#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
102#define IGN_EN 0
103
104/* PM1x control register bits */
105#define SCI_EN RT_BIT(0)
106#define BM_RLD RT_BIT(1)
107#define GBL_RLS RT_BIT(2)
108#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
109#define IGN_CNT RT_BIT(9)
110#define SLP_TYPx_SHIFT 10
111#define SLP_TYPx_MASK 7
112#define SLP_EN RT_BIT(13)
113#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
114#define RSR_CNT (RSR1_CNT | RSR2_CNT)
115
116#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
117
118enum
119{
120 BAT_STATUS_STATE = 0x00, /**< BST battery state */
121 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
122 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
123 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
124 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
125 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
126 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
127 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
128 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
129 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
130 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
131 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
132 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
133 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
134 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
135 BAT_INDEX_LAST
136};
137
138enum
139{
140 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
141 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
142 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
143 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
144 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
145 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
146 SYSTEM_INFO_INDEX_CPU1_STATUS = 6,
147 SYSTEM_INFO_INDEX_CPU2_STATUS = 7,
148 SYSTEM_INFO_INDEX_CPU3_STATUS = 8,
149 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 9,
150 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
151 SYSTEM_INFO_INDEX_END = 11,
152 SYSTEM_INFO_INDEX_INVALID = 0x80,
153 SYSTEM_INFO_INDEX_VALID = 0x200
154};
155
156#define AC_OFFLINE 0
157#define AC_ONLINE 1
158
159#define BAT_TECH_PRIMARY 1
160#define BAT_TECH_SECONDARY 2
161
162#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
163#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
164#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
165#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
166#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
167
168
169/*******************************************************************************
170* Structures and Typedefs *
171*******************************************************************************/
172/**
173 * The ACPI device state.
174 */
175typedef struct ACPIState
176{
177 PCIDevice dev;
178 uint16_t pm1a_en;
179 uint16_t pm1a_sts;
180 uint16_t pm1a_ctl;
181 /** Number of logical CPUs in guest */
182 uint16_t cCpus;
183 int64_t pm_timer_initial;
184 PTMTIMERR3 tsR3;
185 PTMTIMERR0 tsR0;
186 PTMTIMERRC tsRC;
187
188 uint32_t gpe0_en;
189 uint32_t gpe0_sts;
190
191 unsigned int uBatteryIndex;
192 uint32_t au8BatteryInfo[13];
193
194 unsigned int uSystemInfoIndex;
195 uint64_t u64RamSize;
196 /** The number of bytes above 4GB. */
197 uint64_t cbRamHigh;
198 /** The number of bytes below 4GB. */
199 uint32_t cbRamLow;
200
201 /** Current ACPI S* state. We support S0 and S5 */
202 uint32_t uSleepState;
203 uint8_t au8RSDPPage[0x1000];
204 /** This is a workaround for incorrect index field handling by Intels ACPICA.
205 * The system info _INI method writes to offset 0x200. We either observe a
206 * write request to index 0x80 (in that case we don't change the index) or a
207 * write request to offset 0x200 (in that case we divide the index value by
208 * 4. Note that the _STA method is sometimes called prior to the _INI method
209 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
210 * acpiBatIndexWrite() for handling this. */
211 uint8_t u8IndexShift;
212 /** provide an I/O-APIC */
213 uint8_t u8UseIOApic;
214 /** provide a floppy controller */
215 bool fUseFdc;
216 /** If High Precision Event Timer device should be supported */
217 bool fUseHpet;
218 /** If System Management Controller device should be supported */
219 bool fUseSmc;
220 /** the guest handled the last power button event */
221 bool fPowerButtonHandled;
222 /** If ACPI CPU device should be shown */
223 bool fShowCpu;
224 /** If Real Time Clock ACPI object to be shown */
225 bool fShowRtc;
226 /** I/O port address of PM device. */
227 RTIOPORT uPmIoPortBase;
228 /** Flag whether the GC part of the device is enabled. */
229 bool fGCEnabled;
230 /** Flag whether the R0 part of the device is enabled. */
231 bool fR0Enabled;
232 /** Aligning IBase. */
233 bool afAlignment[4];
234
235 /** ACPI port base interface. */
236 PDMIBASE IBase;
237 /** ACPI port interface. */
238 PDMIACPIPORT IACPIPort;
239 /** Pointer to the device instance. */
240 PPDMDEVINSR3 pDevIns;
241 /** Pointer to the driver base interface */
242 R3PTRTYPE(PPDMIBASE) pDrvBase;
243 /** Pointer to the driver connector interface */
244 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
245
246 /* Pointer to default PCI config read function */
247 R3PTRTYPE(PFNPCICONFIGREAD) pfnAcpiPciConfigRead;
248 /* Pointer to default PCI config write function */
249 R3PTRTYPE(PFNPCICONFIGWRITE) pfnAcpiPciConfigWrite;
250} ACPIState;
251
252#pragma pack(1)
253
254/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
255struct ACPIGENADDR
256{
257 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
258 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
259 uint8_t u8RegisterBitOffset; /**< bit offset of register */
260 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
261 uint64_t u64Address; /**< 64-bit address of register */
262};
263AssertCompileSize(ACPIGENADDR, 12);
264
265/** Root System Description Pointer */
266struct ACPITBLRSDP
267{
268 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
269 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
270 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
271 uint8_t u8Revision; /**< revision number, currently 2 */
272#define ACPI_REVISION 2 /**< ACPI 3.0 */
273 uint32_t u32RSDT; /**< phys addr of RSDT */
274 uint32_t u32Length; /**< bytes of this table */
275 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
276 uint8_t u8ExtChecksum; /**< checksum of entire table */
277 uint8_t u8Reserved[3]; /**< reserved */
278};
279AssertCompileSize(ACPITBLRSDP, 36);
280
281/** System Description Table Header */
282struct ACPITBLHEADER
283{
284 uint8_t au8Signature[4]; /**< table identifier */
285 uint32_t u32Length; /**< length of the table including header */
286 uint8_t u8Revision; /**< revision number */
287 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
288 uint8_t au8OemId[6]; /**< OEM-supplied string */
289 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
290 uint32_t u32OemRevision; /**< OEM-supplied revision number */
291 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
292 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
293};
294AssertCompileSize(ACPITBLHEADER, 36);
295
296/** Root System Description Table */
297struct ACPITBLRSDT
298{
299 ACPITBLHEADER header;
300 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
301};
302AssertCompileSize(ACPITBLRSDT, 40);
303
304/** Extended System Description Table */
305struct ACPITBLXSDT
306{
307 ACPITBLHEADER header;
308 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
309};
310AssertCompileSize(ACPITBLXSDT, 44);
311
312/** Fixed ACPI Description Table */
313struct ACPITBLFADT
314{
315 ACPITBLHEADER header;
316 uint32_t u32FACS; /**< phys. address of FACS */
317 uint32_t u32DSDT; /**< phys. address of DSDT */
318 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
319#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
320#define INT_MODEL_MULTIPLE_APIC 2
321 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
322 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
323#define SCI_INT 9
324 uint32_t u32SMICmd; /**< system port address of SMI command port */
325#define SMI_CMD 0x0000442e
326 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
327#define ACPI_ENABLE 0xa1
328 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
329#define ACPI_DISABLE 0xa0
330 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
331 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
332 state control responsibility */
333 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
334 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
335 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
336 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
337 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
338 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
339 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
340 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
341 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
342 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
343 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
344 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
345 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
346#define GPE0_BLK_LEN 2
347 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
348#define GPE1_BLK_LEN 0
349 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
350#define GPE1_BASE 0
351 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
352 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
353#define P_LVL2_LAT 101 /**< C2 state not supported */
354 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
355#define P_LVL3_LAT 1001 /**< C3 state not supported */
356 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
357 lines from any processors memory caches */
358#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
359 uint16_t u16FlushStride; /**< cache line width */
360#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
361 uint8_t u8DutyOffset;
362 uint8_t u8DutyWidth;
363 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
364 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
365 uint8_t u8Century; /**< RTC CMOS RAM index of century */
366 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
367#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
368 (COM too?) */
369#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
370#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
371 uint8_t u8Must0_0; /**< must be 0 */
372 uint32_t u32Flags; /**< fixed feature flags */
373#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
374#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
375#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
376#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
377#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
378#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
379#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
380#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
381#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
382#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
383#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
384#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
385#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
386#define FADT_FL_CPU_SW_SLP RT_BIT(13)
387#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
388#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
389#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
390#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
391#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
392#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
393
394 /** Start of the ACPI 2.0 extension. */
395 ACPIGENADDR ResetReg; /**< ext addr of reset register */
396 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
397#define ACPI_RESET_REG_VAL 0x10
398 uint8_t au8Must0_1[3]; /**< must be 0 */
399 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
400 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
401 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
402 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
403 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
404 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
405 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
406 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
407 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
408 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
409};
410AssertCompileSize(ACPITBLFADT, 244);
411#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
412
413/** Firmware ACPI Control Structure */
414struct ACPITBLFACS
415{
416 uint8_t au8Signature[4]; /**< 'FACS' */
417 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
418 uint32_t u32HWSignature; /**< systems HW signature at last boot */
419 uint32_t u32FWVector; /**< address of waking vector */
420 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
421 uint32_t u32Flags; /**< FACS flags */
422 uint64_t u64X_FWVector; /**< 64-bit waking vector */
423 uint8_t u8Version; /**< version of this table */
424 uint8_t au8Reserved[31]; /**< zero */
425};
426AssertCompileSize(ACPITBLFACS, 64);
427
428/** Processor Local APIC Structure */
429struct ACPITBLLAPIC
430{
431 uint8_t u8Type; /**< 0 = LAPIC */
432 uint8_t u8Length; /**< 8 */
433 uint8_t u8ProcId; /**< processor ID */
434 uint8_t u8ApicId; /**< local APIC ID */
435 uint32_t u32Flags; /**< Flags */
436#define LAPIC_ENABLED 0x1
437};
438AssertCompileSize(ACPITBLLAPIC, 8);
439
440/** I/O APIC Structure */
441struct ACPITBLIOAPIC
442{
443 uint8_t u8Type; /**< 1 == I/O APIC */
444 uint8_t u8Length; /**< 12 */
445 uint8_t u8IOApicId; /**< I/O APIC ID */
446 uint8_t u8Reserved; /**< 0 */
447 uint32_t u32Address; /**< phys address to access I/O APIC */
448 uint32_t u32GSIB; /**< global system interrupt number to start */
449};
450AssertCompileSize(ACPITBLIOAPIC, 12);
451
452# ifdef IN_RING3 /** @todo r=bird: Move this down to where it's used. */
453
454# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
455
456/**
457 * Multiple APIC Description Table.
458 *
459 * This structure looks somewhat convoluted due layout of MADT table in MP case.
460 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
461 * use regular C structure and proxy to raw memory instead.
462 */
463class AcpiTableMADT
464{
465 /**
466 * All actual data stored in dynamically allocated memory pointed by this field.
467 */
468 uint8_t *m_pbData;
469 /**
470 * Number of CPU entries in this MADT.
471 */
472 uint32_t m_cCpus;
473
474public:
475 /**
476 * Address of ACPI header
477 */
478 inline ACPITBLHEADER *header_addr(void) const
479 {
480 return (ACPITBLHEADER *)m_pbData;
481 }
482
483 /**
484 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
485 * although address is the same for all of them.
486 */
487 inline uint32_t *u32LAPIC_addr(void) const
488 {
489 return (uint32_t *)(header_addr() + 1);
490 }
491
492 /**
493 * Address of APIC flags
494 */
495 inline uint32_t *u32Flags_addr(void) const
496 {
497 return (uint32_t *)(u32LAPIC_addr() + 1);
498 }
499
500 /**
501 * Address of per-CPU LAPIC descriptions
502 */
503 inline ACPITBLLAPIC *LApics_addr(void) const
504 {
505 return (ACPITBLLAPIC *)(u32Flags_addr() + 1);
506 }
507
508 /**
509 * Address of IO APIC description
510 */
511 inline ACPITBLIOAPIC *IOApic_addr(void) const
512 {
513 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
514 }
515
516 /**
517 * Size of MADT.
518 * Note that this function assumes IOApic to be the last field in structure.
519 */
520 inline uint32_t size(void) const
521 {
522 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
523 }
524
525 /**
526 * Raw data of MADT.
527 */
528 inline const uint8_t *data(void) const
529 {
530 return m_pbData;
531 }
532
533 /**
534 * Size of MADT for given ACPI config, useful to compute layout.
535 */
536 static uint32_t sizeFor(ACPIState *s)
537 {
538 return AcpiTableMADT(s->cCpus).size();
539 }
540
541 /*
542 * Constructor, only works in Ring 3, doesn't look like a big deal.
543 */
544 AcpiTableMADT(uint32_t cCpus)
545 {
546 m_cCpus = cCpus;
547 uint32_t cb = size();
548 m_pbData = (uint8_t *)RTMemAllocZ(cb);
549 }
550
551 ~AcpiTableMADT()
552 {
553 RTMemFree(m_pbData);
554 }
555};
556# endif /* IN_RING3 */
557
558#pragma pack()
559
560
561#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
562/*******************************************************************************
563* Internal Functions *
564*******************************************************************************/
565RT_C_DECLS_BEGIN
566PDMBOTHCBDECL(int) acpiPMTmrRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
567#ifdef IN_RING3
568PDMBOTHCBDECL(int) acpiPm1aEnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
569PDMBOTHCBDECL(int) acpiPM1aEnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
570PDMBOTHCBDECL(int) acpiPm1aStsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
571PDMBOTHCBDECL(int) acpiPM1aStsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
572PDMBOTHCBDECL(int) acpiPm1aCtlRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
573PDMBOTHCBDECL(int) acpiPM1aCtlWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
574PDMBOTHCBDECL(int) acpiSmiWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
575PDMBOTHCBDECL(int) acpiBatIndexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
576PDMBOTHCBDECL(int) acpiBatDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
577PDMBOTHCBDECL(int) acpiSysInfoDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
578PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
579PDMBOTHCBDECL(int) acpiGpe0EnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
580PDMBOTHCBDECL(int) acpiGpe0EnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
581PDMBOTHCBDECL(int) acpiGpe0StsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
582PDMBOTHCBDECL(int) acpiGpe0StsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
583PDMBOTHCBDECL(int) acpiResetWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
584# ifdef DEBUG_ACPI
585PDMBOTHCBDECL(int) acpiDhexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
586PDMBOTHCBDECL(int) acpiDchrWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
587# endif
588#endif /* IN_RING3 */
589RT_C_DECLS_END
590
591
592#ifdef IN_RING3
593
594static RTIOPORT acpiPmPort(ACPIState* pAcpi, int32_t offset)
595{
596 Assert(pAcpi->uPmIoPortBase != 0);
597
598 if (offset == -1)
599 return 0;
600
601 return RTIOPORT(pAcpi->uPmIoPortBase + offset);
602}
603
604/* Simple acpiChecksum: all the bytes must add up to 0. */
605static uint8_t acpiChecksum(const uint8_t * const data, size_t len)
606{
607 uint8_t sum = 0;
608 for (size_t i = 0; i < len; ++i)
609 sum += data[i];
610 return -sum;
611}
612
613static void acpiPrepareHeader(ACPITBLHEADER *header, const char au8Signature[4],
614 uint32_t u32Length, uint8_t u8Revision)
615{
616 memcpy(header->au8Signature, au8Signature, 4);
617 header->u32Length = RT_H2LE_U32(u32Length);
618 header->u8Revision = u8Revision;
619 memcpy(header->au8OemId, "VBOX ", 6);
620 memcpy(header->au8OemTabId, "VBOX", 4);
621 memcpy(header->au8OemTabId+4, au8Signature, 4);
622 header->u32OemRevision = RT_H2LE_U32(1);
623 memcpy(header->au8CreatorId, "ASL ", 4);
624 header->u32CreatorRev = RT_H2LE_U32(0x61);
625}
626
627static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
628 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
629 uint8_t u8AccessSize, uint64_t u64Address)
630{
631 g->u8AddressSpaceId = u8AddressSpaceId;
632 g->u8RegisterBitWidth = u8RegisterBitWidth;
633 g->u8RegisterBitOffset = u8RegisterBitOffset;
634 g->u8AccessSize = u8AccessSize;
635 g->u64Address = RT_H2LE_U64(u64Address);
636}
637
638static void acpiPhyscpy(ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
639{
640 PDMDevHlpPhysWrite(s->pDevIns, dst, src, size);
641}
642
643/** Differentiated System Description Table (DSDT) */
644
645static void acpiSetupDSDT(ACPIState *s, RTGCPHYS32 addr,
646 void* pPtr, size_t uDsdtLen)
647{
648 acpiPhyscpy(s, addr, pPtr, uDsdtLen);
649}
650
651/** Firmware ACPI Control Structure (FACS) */
652static void acpiSetupFACS(ACPIState *s, RTGCPHYS32 addr)
653{
654 ACPITBLFACS facs;
655
656 memset(&facs, 0, sizeof(facs));
657 memcpy(facs.au8Signature, "FACS", 4);
658 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
659 facs.u32HWSignature = RT_H2LE_U32(0);
660 facs.u32FWVector = RT_H2LE_U32(0);
661 facs.u32GlobalLock = RT_H2LE_U32(0);
662 facs.u32Flags = RT_H2LE_U32(0);
663 facs.u64X_FWVector = RT_H2LE_U64(0);
664 facs.u8Version = 1;
665
666 acpiPhyscpy(s, addr, (const uint8_t *)&facs, sizeof(facs));
667}
668
669/** Fixed ACPI Description Table (FADT aka FACP) */
670static void acpiSetupFADT(ACPIState *s, RTGCPHYS32 addr_acpi1, RTGCPHYS32 addr_acpi2, uint32_t facs_addr, uint32_t dsdt_addr)
671{
672 ACPITBLFADT fadt;
673
674 /* First the ACPI version 2+ version of the structure. */
675 memset(&fadt, 0, sizeof(fadt));
676 acpiPrepareHeader(&fadt.header, "FACP", sizeof(fadt), 4);
677 fadt.u32FACS = RT_H2LE_U32(facs_addr);
678 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
679 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
680 fadt.u8PreferredPMProfile = 0; /* unspecified */
681 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
682 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
683 fadt.u8AcpiEnable = ACPI_ENABLE;
684 fadt.u8AcpiDisable = ACPI_DISABLE;
685 fadt.u8S4BIOSReq = 0;
686 fadt.u8PStateCnt = 0;
687 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiPmPort(s, PM1a_EVT_OFFSET));
688 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiPmPort(s, PM1b_EVT_OFFSET));
689 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiPmPort(s, PM1a_CTL_OFFSET));
690 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiPmPort(s, PM1b_CTL_OFFSET));
691 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiPmPort(s, PM2_CTL_OFFSET));
692 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiPmPort(s, PM_TMR_OFFSET));
693 fadt.u32GPE0BLK = RT_H2LE_U32(acpiPmPort(s, GPE0_OFFSET));
694 fadt.u32GPE1BLK = RT_H2LE_U32(acpiPmPort(s, GPE1_OFFSET));
695 fadt.u8PM1EVTLEN = 4;
696 fadt.u8PM1CTLLEN = 2;
697 fadt.u8PM2CTLLEN = 0;
698 fadt.u8PMTMLEN = 4;
699 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
700 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
701 fadt.u8GPE1BASE = GPE1_BASE;
702 fadt.u8CSTCNT = 0;
703 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
704 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
705 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
706 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
707 fadt.u8DutyOffset = 0;
708 fadt.u8DutyWidth = 0;
709 fadt.u8DayAlarm = 0;
710 fadt.u8MonAlarm = 0;
711 fadt.u8Century = 0;
712 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
713 /** @note WBINVD is required for ACPI versions newer than 1.0 */
714 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
715 | FADT_FL_FIX_RTC
716 | FADT_FL_TMR_VAL_EXT);
717 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
718 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
719 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
720 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
721 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiPmPort(s, PM1a_EVT_OFFSET));
722 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiPmPort(s, PM1b_EVT_OFFSET));
723 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiPmPort(s, PM1a_CTL_OFFSET));
724 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiPmPort(s, PM1b_CTL_OFFSET));
725 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiPmPort(s, PM2_CTL_OFFSET));
726 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiPmPort(s, PM_TMR_OFFSET));
727 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiPmPort(s, GPE0_OFFSET));
728 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiPmPort(s, GPE1_OFFSET));
729 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, sizeof(fadt));
730 acpiPhyscpy(s, addr_acpi2, &fadt, sizeof(fadt));
731
732 /* Now the ACPI 1.0 version. */
733 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
734 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
735 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
736 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, ACPITBLFADT_VERSION1_SIZE);
737 acpiPhyscpy(s, addr_acpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
738}
739
740/**
741 * Root System Description Table.
742 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
743 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
744 */
745static int acpiSetupRSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
746{
747 ACPITBLRSDT *rsdt;
748 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
749
750 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
751 if (!rsdt)
752 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
753
754 acpiPrepareHeader(&rsdt->header, "RSDT", (uint32_t)size, 1);
755 for (unsigned int i = 0; i < nb_entries; ++i)
756 {
757 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
758 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
759 }
760 rsdt->header.u8Checksum = acpiChecksum((uint8_t*)rsdt, size);
761 acpiPhyscpy(s, addr, rsdt, size);
762 RTMemFree(rsdt);
763 return VINF_SUCCESS;
764}
765
766/** Extended System Description Table. */
767static int acpiSetupXSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
768{
769 ACPITBLXSDT *xsdt;
770 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
771
772 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
773 if (!xsdt)
774 return VERR_NO_TMP_MEMORY;
775
776 acpiPrepareHeader(&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
777 for (unsigned int i = 0; i < nb_entries; ++i)
778 {
779 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
780 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
781 }
782 xsdt->header.u8Checksum = acpiChecksum((uint8_t*)xsdt, size);
783 acpiPhyscpy(s, addr, xsdt, size);
784 RTMemFree(xsdt);
785 return VINF_SUCCESS;
786}
787
788/** Root System Description Pointer (RSDP) */
789static void acpiSetupRSDP(ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
790{
791 memset(rsdp, 0, sizeof(*rsdp));
792
793 /* ACPI 1.0 part (RSDT */
794 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
795 memcpy(rsdp->au8OemId, "VBOX ", 6);
796 rsdp->u8Revision = ACPI_REVISION;
797 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
798 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
799
800 /* ACPI 2.0 part (XSDT) */
801 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
802 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
803 rsdp->u8ExtChecksum = acpiChecksum((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
804}
805
806/**
807 * Multiple APIC Description Table.
808 *
809 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both
810 *
811 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
812 */
813static void acpiSetupMADT(ACPIState *s, RTGCPHYS32 addr)
814{
815 uint16_t cpus = s->cCpus;
816 AcpiTableMADT madt(cpus);
817
818 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
819
820 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
821 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
822
823 ACPITBLLAPIC* lapic = madt.LApics_addr();
824 for (uint16_t i = 0; i < cpus; i++)
825 {
826 lapic->u8Type = 0;
827 lapic->u8Length = sizeof(ACPITBLLAPIC);
828 lapic->u8ProcId = i;
829 lapic->u8ApicId = i;
830 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
831 lapic++;
832 }
833
834 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
835
836 ioapic->u8Type = 1;
837 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
838 /** @todo is this the right id? */
839 ioapic->u8IOApicId = cpus;
840 ioapic->u8Reserved = 0;
841 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
842 ioapic->u32GSIB = RT_H2LE_U32(0);
843
844 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
845 acpiPhyscpy(s, addr, madt.data(), madt.size());
846}
847
848/* SCI IRQ */
849DECLINLINE(void) acpiSetIrq(ACPIState *s, int level)
850{
851 if (s->pm1a_ctl & SCI_EN)
852 PDMDevHlpPCISetIrq(s->pDevIns, -1, level);
853}
854
855DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
856{
857 return en & ~(RSR_EN | IGN_EN);
858}
859
860DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
861{
862 return sts & ~(RSR_STS | IGN_STS);
863}
864
865DECLINLINE(int) pm1a_level(ACPIState *s)
866{
867 return (pm1a_pure_en(s->pm1a_en) & pm1a_pure_sts(s->pm1a_sts)) != 0;
868}
869
870DECLINLINE(int) gpe0_level(ACPIState *s)
871{
872 return (s->gpe0_en & s->gpe0_sts) != 0;
873}
874
875static void update_pm1a(ACPIState *s, uint32_t sts, uint32_t en)
876{
877 int old_level, new_level;
878
879 if (gpe0_level(s))
880 return;
881
882 old_level = pm1a_level(s);
883 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
884
885 s->pm1a_en = en;
886 s->pm1a_sts = sts;
887
888 if (new_level != old_level)
889 acpiSetIrq(s, new_level);
890}
891
892static void update_gpe0(ACPIState *s, uint32_t sts, uint32_t en)
893{
894 int old_level, new_level;
895
896 if (pm1a_level(s))
897 return;
898
899 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
900 new_level = (en & sts) != 0;
901
902 s->gpe0_en = en;
903 s->gpe0_sts = sts;
904
905 if (new_level != old_level)
906 acpiSetIrq(s, new_level);
907}
908
909static int acpiPowerDown(ACPIState *s)
910{
911 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
912 if (RT_FAILURE(rc))
913 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
914 return rc;
915}
916
917/** Converts a ACPI port interface pointer to an ACPI state pointer. */
918#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
919
920/**
921 * Send an ACPI power off event.
922 *
923 * @returns VBox status code
924 * @param pInterface Pointer to the interface structure containing the called function pointer.
925 */
926static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
927{
928 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
929 s->fPowerButtonHandled = false;
930 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
931 return VINF_SUCCESS;
932}
933
934/**
935 * Check if the ACPI power button event was handled.
936 *
937 * @returns VBox status code
938 * @param pInterface Pointer to the interface structure containing the called function pointer.
939 * @param pfHandled Return true if the power button event was handled by the guest.
940 */
941static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
942{
943 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
944 *pfHandled = s->fPowerButtonHandled;
945 return VINF_SUCCESS;
946}
947
948/**
949 * Check if the Guest entered into G0 (working) or G1 (sleeping).
950 *
951 * @returns VBox status code
952 * @param pInterface Pointer to the interface structure containing the called function pointer.
953 * @param pfEntered Return true if the guest entered the ACPI mode.
954 */
955static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
956{
957 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
958 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
959 return VINF_SUCCESS;
960}
961
962/**
963 * Send an ACPI sleep button event.
964 *
965 * @returns VBox status code
966 * @param pInterface Pointer to the interface structure containing the called function pointer.
967 */
968static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
969{
970 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
971 update_pm1a(s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
972 return VINF_SUCCESS;
973}
974
975/* PM1a_EVT_BLK enable */
976static uint32_t acpiPm1aEnReadw(ACPIState *s, uint32_t addr)
977{
978 uint16_t val = s->pm1a_en;
979 Log(("acpi: acpiPm1aEnReadw -> %#x\n", val));
980 return val;
981}
982
983static void acpiPM1aEnWritew(ACPIState *s, uint32_t addr, uint32_t val)
984{
985 Log(("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
986 val &= ~(RSR_EN | IGN_EN);
987 update_pm1a(s, s->pm1a_sts, val);
988}
989
990/* PM1a_EVT_BLK status */
991static uint32_t acpiPm1aStsReadw(ACPIState *s, uint32_t addr)
992{
993 uint16_t val = s->pm1a_sts;
994 Log(("acpi: acpiPm1aStsReadw -> %#x\n", val));
995 return val;
996}
997
998static void acpiPM1aStsWritew(ACPIState *s, uint32_t addr, uint32_t val)
999{
1000 Log(("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
1001 if (val & PWRBTN_STS)
1002 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1003 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
1004 update_pm1a(s, val, s->pm1a_en);
1005}
1006
1007/* PM1a_CTL_BLK */
1008static uint32_t acpiPm1aCtlReadw(ACPIState *s, uint32_t addr)
1009{
1010 uint16_t val = s->pm1a_ctl;
1011 Log(("acpi: acpiPm1aCtlReadw -> %#x\n", val));
1012 return val;
1013}
1014
1015static int acpiPM1aCtlWritew(ACPIState *s, uint32_t addr, uint32_t val)
1016{
1017 uint32_t uSleepState;
1018
1019 Log(("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
1020 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
1021
1022 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1023 if (uSleepState != s->uSleepState)
1024 {
1025 s->uSleepState = uSleepState;
1026 switch (uSleepState)
1027 {
1028 case 0x00: /* S0 */
1029 break;
1030 case 0x05: /* S5 */
1031 LogRel(("Entering S5 (power down)\n"));
1032 return acpiPowerDown(s);
1033 default:
1034 AssertMsgFailed(("Unknown sleep state %#x\n", uSleepState));
1035 break;
1036 }
1037 }
1038 return VINF_SUCCESS;
1039}
1040
1041/* GPE0_BLK */
1042static uint32_t acpiGpe0EnReadb(ACPIState *s, uint32_t addr)
1043{
1044 uint8_t val = s->gpe0_en;
1045 Log(("acpi: acpiGpe0EnReadl -> %#x\n", val));
1046 return val;
1047}
1048
1049static void acpiGpe0EnWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1050{
1051 Log(("acpi: acpiGpe0EnWritel <- %#x\n", val));
1052 update_gpe0(s, s->gpe0_sts, val);
1053}
1054
1055static uint32_t acpiGpe0StsReadb(ACPIState *s, uint32_t addr)
1056{
1057 uint8_t val = s->gpe0_sts;
1058 Log(("acpi: acpiGpe0StsReadl -> %#x\n", val));
1059 return val;
1060}
1061
1062static void acpiGpe0StsWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1063{
1064 val = s->gpe0_sts & ~val;
1065 update_gpe0(s, val, s->gpe0_en);
1066 Log(("acpi: acpiGpe0StsWritel <- %#x\n", val));
1067}
1068
1069static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1070{
1071 int rc = VINF_SUCCESS;
1072
1073 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1074 if (val == ACPI_RESET_REG_VAL)
1075 {
1076# ifndef IN_RING3
1077 rc = VINF_IOM_HC_IOPORT_WRITE;
1078# else /* IN_RING3 */
1079 rc = PDMDevHlpVMReset(s->pDevIns);
1080# endif /* !IN_RING3 */
1081 }
1082 return rc;
1083}
1084
1085/* SMI */
1086static void acpiSmiWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1087{
1088 Log(("acpi: acpiSmiWriteU8 %#x\n", val));
1089 if (val == ACPI_ENABLE)
1090 s->pm1a_ctl |= SCI_EN;
1091 else if (val == ACPI_DISABLE)
1092 s->pm1a_ctl &= ~SCI_EN;
1093 else
1094 Log(("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1095}
1096
1097static uint32_t find_rsdp_space(void)
1098{
1099 return 0xe0000;
1100}
1101
1102static int acpiPMTimerReset(ACPIState *s)
1103{
1104 uint64_t interval, freq;
1105
1106 freq = TMTimerGetFreq(s->CTX_SUFF(ts));
1107 interval = ASMMultU64ByU32DivByU32(0xffffffff, freq, PM_TMR_FREQ);
1108 Log(("interval = %RU64\n", interval));
1109 TMTimerSet(s->CTX_SUFF(ts), TMTimerGet(s->CTX_SUFF(ts)) + interval);
1110
1111 return VINF_SUCCESS;
1112}
1113
1114static DECLCALLBACK(void) acpiTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1115{
1116 ACPIState *s = (ACPIState *)pvUser;
1117
1118 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1119 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1120 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1121
1122 update_pm1a(s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1123 acpiPMTimerReset(s);
1124}
1125
1126/**
1127 * _BST method.
1128 */
1129static int acpiFetchBatteryStatus(ACPIState *s)
1130{
1131 uint32_t *p = s->au8BatteryInfo;
1132 bool fPresent; /* battery present? */
1133 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1134 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1135 uint32_t hostPresentRate; /* 0..1000 */
1136 int rc;
1137
1138 if (!s->pDrv)
1139 return VINF_SUCCESS;
1140 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1141 &hostBatteryState, &hostPresentRate);
1142 AssertRC(rc);
1143
1144 /* default values */
1145 p[BAT_STATUS_STATE] = hostBatteryState;
1146 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1147 : hostPresentRate * 50; /* mW */
1148 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1149 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1150
1151 /* did we get a valid battery state? */
1152 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1153 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1154 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1155 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1156
1157 return VINF_SUCCESS;
1158}
1159
1160/**
1161 * _BIF method.
1162 */
1163static int acpiFetchBatteryInfo(ACPIState *s)
1164{
1165 uint32_t *p = s->au8BatteryInfo;
1166
1167 p[BAT_INFO_UNITS] = 0; /* mWh */
1168 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1169 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1170 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1171 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1172 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1173 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1174 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1175 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1176
1177 return VINF_SUCCESS;
1178}
1179
1180/**
1181 * _STA method.
1182 */
1183static uint32_t acpiGetBatteryDeviceStatus(ACPIState *s)
1184{
1185 bool fPresent; /* battery present? */
1186 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1187 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1188 uint32_t hostPresentRate; /* 0..1000 */
1189 int rc;
1190
1191 if (!s->pDrv)
1192 return 0;
1193 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1194 &hostBatteryState, &hostPresentRate);
1195 AssertRC(rc);
1196
1197 return fPresent
1198 ? STA_DEVICE_PRESENT_MASK /* present */
1199 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1200 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1201 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1202 | STA_BATTERY_PRESENT_MASK /* battery is present */
1203 : 0; /* device not present */
1204}
1205
1206static uint32_t acpiGetPowerSource(ACPIState *s)
1207{
1208 PDMACPIPOWERSOURCE ps;
1209
1210 /* query the current power source from the host driver */
1211 if (!s->pDrv)
1212 return AC_ONLINE;
1213 int rc = s->pDrv->pfnQueryPowerSource(s->pDrv, &ps);
1214 AssertRC(rc);
1215 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1216}
1217
1218PDMBOTHCBDECL(int) acpiBatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1219{
1220 ACPIState *s = (ACPIState *)pvUser;
1221
1222 switch (cb)
1223 {
1224 case 4:
1225 u32 >>= s->u8IndexShift;
1226 /* see comment at the declaration of u8IndexShift */
1227 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1228 {
1229 s->u8IndexShift = 2;
1230 u32 >>= 2;
1231 }
1232 Assert(u32 < BAT_INDEX_LAST);
1233 s->uBatteryIndex = u32;
1234 break;
1235 default:
1236 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1237 break;
1238 }
1239 return VINF_SUCCESS;
1240}
1241
1242PDMBOTHCBDECL(int) acpiBatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1243{
1244 ACPIState *s = (ACPIState *)pvUser;
1245
1246 switch (cb)
1247 {
1248 case 4:
1249 switch (s->uBatteryIndex)
1250 {
1251 case BAT_STATUS_STATE:
1252 acpiFetchBatteryStatus(s);
1253 case BAT_STATUS_PRESENT_RATE:
1254 case BAT_STATUS_REMAINING_CAPACITY:
1255 case BAT_STATUS_PRESENT_VOLTAGE:
1256 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1257 break;
1258
1259 case BAT_INFO_UNITS:
1260 acpiFetchBatteryInfo(s);
1261 case BAT_INFO_DESIGN_CAPACITY:
1262 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1263 case BAT_INFO_TECHNOLOGY:
1264 case BAT_INFO_DESIGN_VOLTAGE:
1265 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1266 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1267 case BAT_INFO_CAPACITY_GRANULARITY_1:
1268 case BAT_INFO_CAPACITY_GRANULARITY_2:
1269 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1270 break;
1271
1272 case BAT_DEVICE_STATUS:
1273 *pu32 = acpiGetBatteryDeviceStatus(s);
1274 break;
1275
1276 case BAT_POWER_SOURCE:
1277 *pu32 = acpiGetPowerSource(s);
1278 break;
1279
1280 default:
1281 AssertMsgFailed(("Invalid battery index %d\n", s->uBatteryIndex));
1282 break;
1283 }
1284 break;
1285 default:
1286 return VERR_IOM_IOPORT_UNUSED;
1287 }
1288 return VINF_SUCCESS;
1289}
1290
1291PDMBOTHCBDECL(int) acpiSysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1292{
1293 ACPIState *s = (ACPIState *)pvUser;
1294
1295 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1296 switch (cb)
1297 {
1298 case 4:
1299 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1300 s->uSystemInfoIndex = u32;
1301 else
1302 {
1303 /* see comment at the declaration of u8IndexShift */
1304 if (s->u8IndexShift == 0)
1305 {
1306 if (((u32 >> 2) < SYSTEM_INFO_INDEX_END) && ((u32 & 0x3)) == 0)
1307 {
1308 s->u8IndexShift = 2;
1309 }
1310 }
1311
1312 u32 >>= s->u8IndexShift;
1313 Assert(u32 < SYSTEM_INFO_INDEX_END);
1314 s->uSystemInfoIndex = u32;
1315 }
1316 break;
1317
1318 default:
1319 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1320 break;
1321 }
1322 return VINF_SUCCESS;
1323}
1324
1325PDMBOTHCBDECL(int) acpiSysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1326{
1327 ACPIState *s = (ACPIState *)pvUser;
1328
1329 switch (cb)
1330 {
1331 case 4:
1332 switch (s->uSystemInfoIndex)
1333 {
1334 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1335 *pu32 = s->cbRamLow;
1336 break;
1337
1338 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1339 *pu32 = s->cbRamHigh >> 16; /* 64KB units */
1340 Assert(((uint64_t)*pu32 << 16) == s->cbRamHigh);
1341 break;
1342
1343 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1344 *pu32 = s->u8UseIOApic;
1345 break;
1346
1347 case SYSTEM_INFO_INDEX_HPET_STATUS:
1348 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1349 | STA_DEVICE_ENABLED_MASK
1350 | STA_DEVICE_SHOW_IN_UI_MASK
1351 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1352 : 0;
1353 break;
1354
1355 case SYSTEM_INFO_INDEX_SMC_STATUS:
1356 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1357 | STA_DEVICE_ENABLED_MASK
1358 /* no need to show this device in the UI */
1359 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1360 : 0;
1361 break;
1362
1363 case SYSTEM_INFO_INDEX_FDC_STATUS:
1364 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1365 | STA_DEVICE_ENABLED_MASK
1366 | STA_DEVICE_SHOW_IN_UI_MASK
1367 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1368 : 0;
1369 break;
1370
1371
1372 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1373 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1374 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1375 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1376 *pu32 = s->fShowCpu
1377 && s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < s->cCpus
1378 ?
1379 STA_DEVICE_PRESENT_MASK
1380 | STA_DEVICE_ENABLED_MASK
1381 | STA_DEVICE_SHOW_IN_UI_MASK
1382 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK
1383 : 0;
1384
1385 case SYSTEM_INFO_INDEX_RTC_STATUS:
1386 *pu32 = s->fShowRtc ? ( STA_DEVICE_PRESENT_MASK
1387 | STA_DEVICE_ENABLED_MASK
1388 | STA_DEVICE_SHOW_IN_UI_MASK
1389 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1390 : 0;
1391 break;
1392
1393 /* Solaris 9 tries to read from this index */
1394 case SYSTEM_INFO_INDEX_INVALID:
1395 *pu32 = 0;
1396 break;
1397
1398 default:
1399 AssertMsgFailed(("Invalid system info index %d\n", s->uSystemInfoIndex));
1400 break;
1401 }
1402 break;
1403
1404 default:
1405 return VERR_IOM_IOPORT_UNUSED;
1406 }
1407
1408 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1409 return VINF_SUCCESS;
1410}
1411
1412PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1413{
1414 ACPIState *s = (ACPIState *)pvUser;
1415
1416 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1417
1418 if (cb == 4 && u32 == 0xbadc0de)
1419 {
1420 switch (s->uSystemInfoIndex)
1421 {
1422 case SYSTEM_INFO_INDEX_INVALID:
1423 s->u8IndexShift = 0;
1424 break;
1425
1426 case SYSTEM_INFO_INDEX_VALID:
1427 s->u8IndexShift = 2;
1428 break;
1429
1430 default:
1431 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1432 Port, cb, u32, s->uSystemInfoIndex));
1433 break;
1434 }
1435 }
1436 else
1437 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1438 return VINF_SUCCESS;
1439}
1440
1441/** @todo Don't call functions, but do the job in the read/write handlers
1442 * here! */
1443
1444/* IO Helpers */
1445PDMBOTHCBDECL(int) acpiPm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1446{
1447 switch (cb)
1448 {
1449 case 2:
1450 *pu32 = acpiPm1aEnReadw((ACPIState*)pvUser, Port);
1451 break;
1452 default:
1453 return VERR_IOM_IOPORT_UNUSED;
1454 }
1455 return VINF_SUCCESS;
1456}
1457
1458PDMBOTHCBDECL(int) acpiPm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1459{
1460 switch (cb)
1461 {
1462 case 2:
1463 *pu32 = acpiPm1aStsReadw((ACPIState*)pvUser, Port);
1464 break;
1465 default:
1466 return VERR_IOM_IOPORT_UNUSED;
1467 }
1468 return VINF_SUCCESS;
1469}
1470
1471PDMBOTHCBDECL(int) acpiPm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1472{
1473 switch (cb)
1474 {
1475 case 2:
1476 *pu32 = acpiPm1aCtlReadw((ACPIState*)pvUser, Port);
1477 break;
1478 default:
1479 return VERR_IOM_IOPORT_UNUSED;
1480 }
1481 return VINF_SUCCESS;
1482}
1483
1484PDMBOTHCBDECL(int) acpiPM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1485{
1486 switch (cb)
1487 {
1488 case 2:
1489 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32);
1490 break;
1491 default:
1492 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1493 break;
1494 }
1495 return VINF_SUCCESS;
1496}
1497
1498PDMBOTHCBDECL(int) acpiPM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1499{
1500 switch (cb)
1501 {
1502 case 2:
1503 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32);
1504 break;
1505 default:
1506 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1507 break;
1508 }
1509 return VINF_SUCCESS;
1510}
1511
1512PDMBOTHCBDECL(int) acpiPM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1513{
1514 switch (cb)
1515 {
1516 case 2:
1517 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32);
1518 default:
1519 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1520 break;
1521 }
1522 return VINF_SUCCESS;
1523}
1524
1525#endif /* IN_RING3 */
1526
1527/**
1528 * PMTMR readable from host/guest.
1529 */
1530PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1531{
1532 if (cb == 4)
1533 {
1534 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1535 int64_t now = TMTimerGet(s->CTX_SUFF(ts));
1536 int64_t elapsed = now - s->pm_timer_initial;
1537
1538 *pu32 = ASMMultU64ByU32DivByU32(elapsed, PM_TMR_FREQ, TMTimerGetFreq(s->CTX_SUFF(ts)));
1539 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1540 return VINF_SUCCESS;
1541 }
1542 return VERR_IOM_IOPORT_UNUSED;
1543}
1544
1545#ifdef IN_RING3
1546
1547PDMBOTHCBDECL(int) acpiGpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1548{
1549 switch (cb)
1550 {
1551 case 1:
1552 *pu32 = acpiGpe0StsReadb((ACPIState*)pvUser, Port);
1553 break;
1554 default:
1555 return VERR_IOM_IOPORT_UNUSED;
1556 }
1557 return VINF_SUCCESS;
1558}
1559
1560PDMBOTHCBDECL(int) acpiGpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1561{
1562 switch (cb)
1563 {
1564 case 1:
1565 *pu32 = acpiGpe0EnReadb((ACPIState*)pvUser, Port);
1566 break;
1567 default:
1568 return VERR_IOM_IOPORT_UNUSED;
1569 }
1570 return VINF_SUCCESS;
1571}
1572
1573PDMBOTHCBDECL(int) acpiGpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1574{
1575 switch (cb)
1576 {
1577 case 1:
1578 acpiGpe0StsWriteb((ACPIState*)pvUser, Port, u32);
1579 break;
1580 default:
1581 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1582 break;
1583 }
1584 return VINF_SUCCESS;
1585}
1586
1587PDMBOTHCBDECL(int) acpiGpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1588{
1589 switch (cb)
1590 {
1591 case 1:
1592 acpiGpe0EnWriteb((ACPIState*)pvUser, Port, u32);
1593 break;
1594 default:
1595 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1596 break;
1597 }
1598 return VINF_SUCCESS;
1599}
1600
1601PDMBOTHCBDECL(int) acpiSmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1602{
1603 switch (cb)
1604 {
1605 case 1:
1606 acpiSmiWriteU8((ACPIState*)pvUser, Port, u32);
1607 break;
1608 default:
1609 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1610 break;
1611 }
1612 return VINF_SUCCESS;
1613}
1614
1615PDMBOTHCBDECL(int) acpiResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1616{
1617 switch (cb)
1618 {
1619 case 1:
1620 return acpiResetWriteU8((ACPIState*)pvUser, Port, u32);
1621 default:
1622 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1623 break;
1624 }
1625 return VINF_SUCCESS;
1626}
1627
1628#ifdef DEBUG_ACPI
1629
1630PDMBOTHCBDECL(int) acpiDhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1631{
1632 switch (cb)
1633 {
1634 case 1:
1635 Log(("%#x\n", u32 & 0xff));
1636 break;
1637 case 2:
1638 Log(("%#6x\n", u32 & 0xffff));
1639 case 4:
1640 Log(("%#10x\n", u32));
1641 break;
1642 default:
1643 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1644 break;
1645 }
1646 return VINF_SUCCESS;
1647}
1648
1649PDMBOTHCBDECL(int) acpiDchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1650{
1651 switch (cb)
1652 {
1653 case 1:
1654 Log(("%c", u32 & 0xff));
1655 break;
1656 default:
1657 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1658 break;
1659 }
1660 return VINF_SUCCESS;
1661}
1662
1663#endif /* DEBUG_ACPI */
1664
1665static int acpiRegisterPmHandlers(ACPIState* pThis)
1666{
1667 int rc = VINF_SUCCESS;
1668
1669#define R(offset, cnt, writer, reader, description) \
1670 do { \
1671 rc = PDMDevHlpIOPortRegister(pThis->pDevIns, acpiPmPort(pThis, offset), cnt, pThis, writer, reader, \
1672 NULL, NULL, description); \
1673 if (RT_FAILURE(rc)) \
1674 return rc; \
1675 } while (0)
1676#define L (GPE0_BLK_LEN / 2)
1677
1678 R(PM1a_EVT_OFFSET+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1679 R(PM1a_EVT_OFFSET, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1680 R(PM1a_CTL_OFFSET, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1681 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1682 R(GPE0_OFFSET + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1683 R(GPE0_OFFSET, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1684#undef L
1685#undef R
1686
1687 /* register GC stuff */
1688 if (pThis->fGCEnabled)
1689 {
1690 rc = PDMDevHlpIOPortRegisterGC(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),
1691 1, 0, NULL, "acpiPMTmrRead",
1692 NULL, NULL, "ACPI PM Timer");
1693 AssertRCReturn(rc, rc);
1694 }
1695
1696 /* register R0 stuff */
1697 if (pThis->fR0Enabled)
1698 {
1699 rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),
1700 1, 0, NULL, "acpiPMTmrRead",
1701 NULL, NULL, "ACPI PM Timer");
1702 AssertRCReturn(rc, rc);
1703 }
1704
1705 return rc;
1706}
1707
1708static int acpiUnregisterPmHandlers(ACPIState *pThis)
1709{
1710#define U(offset, cnt) \
1711 do { \
1712 int rc = PDMDevHlpIOPortDeregister(pThis->pDevIns, acpiPmPort(pThis, offset), cnt); \
1713 AssertRCReturn(rc, rc); \
1714 } while (0)
1715#define L (GPE0_BLK_LEN / 2)
1716
1717 U(PM1a_EVT_OFFSET+2, 1);
1718 U(PM1a_EVT_OFFSET, 1);
1719 U(PM1a_CTL_OFFSET, 1);
1720 U(PM_TMR_OFFSET, 1);
1721 U(GPE0_OFFSET + L, L);
1722 U(GPE0_OFFSET, L);
1723#undef L
1724#undef U
1725
1726 return VINF_SUCCESS;
1727}
1728
1729/**
1730 * Saved state structure description, version 4.
1731 */
1732static const SSMFIELD g_AcpiSavedStateFields4[] =
1733{
1734 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1735 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1736 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1737 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1738 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1739 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1740 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1741 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1742 SSMFIELD_ENTRY(ACPIState, u64RamSize),
1743 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1744 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1745 SSMFIELD_ENTRY(ACPIState, uSleepState),
1746 SSMFIELD_ENTRY_TERM()
1747};
1748
1749/**
1750 * Saved state structure description, version 5.
1751 */
1752static const SSMFIELD g_AcpiSavedStateFields5[] =
1753{
1754 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1755 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1756 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1757 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1758 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1759 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1760 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1761 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1762 SSMFIELD_ENTRY(ACPIState, uSleepState),
1763 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1764 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
1765 SSMFIELD_ENTRY_TERM()
1766};
1767
1768
1769static DECLCALLBACK(int) acpi_save_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1770{
1771 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1772 return SSMR3PutStruct(pSSMHandle, s, &g_AcpiSavedStateFields5[0]);
1773}
1774
1775static DECLCALLBACK(int) acpi_load_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1776 uint32_t u32Version)
1777{
1778 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1779 int rc;
1780
1781 /*
1782 * Unregister PM handlers, will register with actual base
1783 * after state successfully loaded.
1784 */
1785 rc = acpiUnregisterPmHandlers(s);
1786 if (RT_FAILURE(rc))
1787 return rc;
1788
1789 switch (u32Version)
1790 {
1791 case 4:
1792 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields4[0]);
1793 /** @todo Provide saner defaults for fields not found in saved state. */
1794 break;
1795 case 5:
1796 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields5[0]);
1797 break;
1798 default:
1799 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1800 }
1801 if (RT_SUCCESS(rc))
1802 {
1803 rc = acpiRegisterPmHandlers(s);
1804 if (RT_FAILURE(rc))
1805 return rc;
1806 rc = acpiFetchBatteryStatus(s);
1807 if (RT_FAILURE(rc))
1808 return rc;
1809 rc = acpiFetchBatteryInfo(s);
1810 if (RT_FAILURE(rc))
1811 return rc;
1812 rc = acpiPMTimerReset(s);
1813 if (RT_FAILURE(rc))
1814 return rc;
1815 }
1816 return rc;
1817}
1818
1819/**
1820 * Queries an interface to the driver.
1821 *
1822 * @returns Pointer to interface.
1823 * @returns NULL if the interface was not supported by the driver.
1824 * @param pInterface Pointer to this interface structure.
1825 * @param enmInterface The requested interface identification.
1826 * @thread Any thread.
1827 */
1828static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1829{
1830 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1831 switch (enmInterface)
1832 {
1833 case PDMINTERFACE_BASE:
1834 return &pThis->IBase;
1835 case PDMINTERFACE_ACPI_PORT:
1836 return &pThis->IACPIPort;
1837 default:
1838 return NULL;
1839 }
1840}
1841
1842/**
1843 * Create the ACPI tables.
1844 */
1845static int acpiPlantTables(ACPIState *s)
1846{
1847 int rc;
1848 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_acpi1_addr, fadt_acpi2_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1849 uint32_t addend = 0;
1850 RTGCPHYS32 rsdt_addrs[4];
1851 RTGCPHYS32 xsdt_addrs[4];
1852 uint32_t cAddr;
1853 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1854 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1855
1856 cAddr = 1; /* FADT */
1857 if (s->u8UseIOApic)
1858 cAddr++; /* MADT */
1859
1860 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1861 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1862
1863 rc = CFGMR3QueryU64(s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1864 if (RT_FAILURE(rc))
1865 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1866 N_("Configuration error: Querying "
1867 "\"RamSize\" as integer failed"));
1868
1869 uint32_t cbRamHole;
1870 rc = CFGMR3QueryU32Def(s->pDevIns->pCfgHandle, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1871 if (RT_FAILURE(rc))
1872 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1873 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
1874
1875 /*
1876 * Calc the sizes for the high and low regions.
1877 */
1878 const uint64_t offRamHole = _4G - cbRamHole;
1879 s->cbRamHigh = offRamHole < s->u64RamSize ? s->u64RamSize - offRamHole : 0;
1880 uint64_t cbRamLow = offRamHole < s->u64RamSize ? offRamHole : s->u64RamSize;
1881 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
1882 {
1883 /* Note: This is also enforced by DevPcBios.cpp. */
1884 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
1885 cbRamLow = UINT32_C(0xffe00000);
1886 }
1887 s->cbRamLow = (uint32_t)cbRamLow;
1888
1889 rsdt_addr = 0;
1890 xsdt_addr = RT_ALIGN_32(rsdt_addr + rsdt_tbl_len, 16);
1891 fadt_acpi1_addr = RT_ALIGN_32(xsdt_addr + xsdt_tbl_len, 16);
1892 fadt_acpi2_addr = RT_ALIGN_32(fadt_acpi1_addr + ACPITBLFADT_VERSION1_SIZE, 16);
1893 /** @todo ACPI 3.0 doc says it needs to be aligned on a 64 byte boundary. */
1894 facs_addr = RT_ALIGN_32(fadt_acpi2_addr + sizeof(ACPITBLFADT), 16);
1895 if (s->u8UseIOApic)
1896 {
1897 apic_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1898 /**
1899 * @todo nike: maybe some refactoring needed to compute tables layout,
1900 * but as this code is executed only once it doesn't make sense to optimize much
1901 */
1902 dsdt_addr = RT_ALIGN_32(apic_addr + AcpiTableMADT::sizeFor(s), 16);
1903 }
1904 else
1905 {
1906 dsdt_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1907 }
1908
1909 void* pDsdtCode = NULL;
1910 size_t uDsdtSize = 0;
1911 rc = acpiPrepareDsdt(s->pDevIns, &pDsdtCode, &uDsdtSize);
1912 if (RT_FAILURE(rc))
1913 return rc;
1914
1915 last_addr = RT_ALIGN_32(dsdt_addr + uDsdtSize, 16);
1916 if (last_addr > 0x10000)
1917 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1918 N_("Error: ACPI tables > 64KB"));
1919
1920 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1921 addend = s->cbRamLow - 0x10000;
1922 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1923 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", facs_addr + addend, fadt_acpi1_addr + addend, fadt_acpi2_addr + addend));
1924 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1925 acpiSetupRSDP((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1926 acpiSetupDSDT(s, dsdt_addr + addend, pDsdtCode, uDsdtSize);
1927 acpiCleanupDsdt(s->pDevIns, pDsdtCode);
1928 acpiSetupFACS(s, facs_addr + addend);
1929 acpiSetupFADT(s, fadt_acpi1_addr + addend, fadt_acpi2_addr + addend, facs_addr + addend, dsdt_addr + addend);
1930
1931 rsdt_addrs[0] = fadt_acpi1_addr + addend;
1932 xsdt_addrs[0] = fadt_acpi2_addr + addend;
1933 if (s->u8UseIOApic)
1934 {
1935 acpiSetupMADT(s, apic_addr + addend);
1936 rsdt_addrs[1] = apic_addr + addend;
1937 xsdt_addrs[1] = apic_addr + addend;
1938 }
1939
1940 rc = acpiSetupRSDT(s, rsdt_addr + addend, cAddr, rsdt_addrs);
1941 if (RT_FAILURE(rc))
1942 return rc;
1943 return acpiSetupXSDT(s, xsdt_addr + addend, cAddr, xsdt_addrs);
1944}
1945
1946static int acpiUpdatePmHandlers(ACPIState *pThis, RTIOPORT uNewBase)
1947{
1948 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, uNewBase));
1949 if (uNewBase != pThis->uPmIoPortBase)
1950 {
1951 int rc;
1952
1953 rc = acpiUnregisterPmHandlers(pThis);
1954 if (RT_FAILURE(rc))
1955 return rc;
1956
1957 pThis->uPmIoPortBase = uNewBase;
1958
1959 rc = acpiRegisterPmHandlers(pThis);
1960 if (RT_FAILURE(rc))
1961 return rc;
1962 }
1963
1964 return VINF_SUCCESS;
1965}
1966
1967static uint32_t acpiPciConfigRead(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb)
1968{
1969 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1970 ACPIState* pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1971
1972 Log2(("acpi: PCI config read: 0x%x (%d)\n", Address, cb));
1973
1974 return pThis->pfnAcpiPciConfigRead(pPciDev, Address, cb);
1975}
1976
1977static void acpiPciConfigWrite(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb)
1978{
1979 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1980 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1981
1982 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, Address, cb));
1983 pThis->pfnAcpiPciConfigWrite(pPciDev, Address, u32Value, cb);
1984
1985 /* PMREGMISC written */
1986 if (Address == 0x80)
1987 {
1988 /* Check Power Management IO Space Enable (PMIOSE) bit */
1989 if (pPciDev->config[0x80] & 0x1)
1990 {
1991 int rc;
1992
1993 RTIOPORT uNewBase =
1994 RTIOPORT(RT_LE2H_U32(*(uint32_t*)&pPciDev->config[0x40]));
1995 uNewBase &= 0xffc0;
1996
1997 rc = acpiUpdatePmHandlers(pThis, uNewBase);
1998 Assert(RT_SUCCESS(rc));
1999 }
2000 }
2001}
2002
2003/**
2004 * Construct a device instance for a VM.
2005 *
2006 * @returns VBox status.
2007 * @param pDevIns The device instance data.
2008 * If the registration structure is needed, pDevIns->pDevReg points to it.
2009 * @param iInstance Instance number. Use this to figure out which registers and such to use.
2010 * The device number is also found in pDevIns->iInstance, but since it's
2011 * likely to be freqently used PDM passes it as parameter.
2012 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
2013 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
2014 * iInstance it's expected to be used a bit in this function.
2015 */
2016static DECLCALLBACK(int) acpiConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2017{
2018 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2019 PCIDevice *dev = &s->dev;
2020
2021 /* Validate and read the configuration. */
2022 if (!CFGMR3AreValuesValid(pCfgHandle,
2023 "RamSize\0"
2024 "RamHoleSize\0"
2025 "IOAPIC\0"
2026 "NumCPUs\0"
2027 "GCEnabled\0"
2028 "R0Enabled\0"
2029 "HpetEnabled\0"
2030 "SmcEnabled\0"
2031 "FdcEnabled\0"
2032 "ShowRtc\0"
2033 "ShowCpu\0"
2034 ))
2035 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2036 N_("Configuration error: Invalid config key for ACPI device"));
2037
2038 s->pDevIns = pDevIns;
2039
2040 /* query whether we are supposed to present an IOAPIC */
2041 int rc = CFGMR3QueryU8Def(pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
2042 if (RT_FAILURE(rc))
2043 return PDMDEV_SET_ERROR(pDevIns, rc,
2044 N_("Configuration error: Failed to read \"IOAPIC\""));
2045
2046 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
2047 if (RT_FAILURE(rc))
2048 return PDMDEV_SET_ERROR(pDevIns, rc,
2049 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
2050
2051 /* query whether we are supposed to present an FDC controller */
2052 rc = CFGMR3QueryBoolDef(pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
2053 if (RT_FAILURE(rc))
2054 return PDMDEV_SET_ERROR(pDevIns, rc,
2055 N_("Configuration error: Failed to read \"FdcEnabled\""));
2056
2057 /* query whether we are supposed to present HPET */
2058 rc = CFGMR3QueryBoolDef(pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
2059 if (RT_FAILURE(rc))
2060 return PDMDEV_SET_ERROR(pDevIns, rc,
2061 N_("Configuration error: Failed to read \"HpetEnabled\""));
2062 /* query whether we are supposed to present SMC */
2063 rc = CFGMR3QueryBoolDef(pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
2064 if (RT_FAILURE(rc))
2065 return PDMDEV_SET_ERROR(pDevIns, rc,
2066 N_("Configuration error: Failed to read \"SmcEnabled\""));
2067
2068 /* query whether we are supposed to present RTC object */
2069 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowRtc", &s->fShowRtc, false);
2070 if (RT_FAILURE(rc))
2071 return PDMDEV_SET_ERROR(pDevIns, rc,
2072 N_("Configuration error: Failed to read \"ShowRtc\""));
2073
2074 /* query whether we are supposed to present CPU objects */
2075 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowCpu", &s->fShowCpu, false);
2076 if (RT_FAILURE(rc))
2077 return PDMDEV_SET_ERROR(pDevIns, rc,
2078 N_("Configuration error: Failed to read \"ShowCpu\""));
2079
2080 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &s->fGCEnabled);
2081 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2082 s->fGCEnabled = true;
2083 else if (RT_FAILURE(rc))
2084 return PDMDEV_SET_ERROR(pDevIns, rc,
2085 N_("Configuration error: Failed to read \"GCEnabled\""));
2086
2087 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &s->fR0Enabled);
2088 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2089 s->fR0Enabled = true;
2090 else if (RT_FAILURE(rc))
2091 return PDMDEV_SET_ERROR(pDevIns, rc,
2092 N_("configuration error: failed to read R0Enabled as boolean"));
2093
2094 /* Set default port base */
2095 s->uPmIoPortBase = PM_PORT_BASE;
2096
2097 /* */
2098 uint32_t rsdp_addr = find_rsdp_space();
2099 if (!rsdp_addr)
2100 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
2101 N_("Can not find space for RSDP. ACPI is disabled"));
2102
2103 rc = acpiPlantTables(s);
2104 if (RT_FAILURE(rc))
2105 return rc;
2106
2107 rc = PDMDevHlpROMRegister(pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage,
2108 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
2109 if (RT_FAILURE(rc))
2110 return rc;
2111
2112 rc = acpiRegisterPmHandlers(s);
2113 if (RT_FAILURE(rc))
2114 return rc;
2115
2116#define R(addr, cnt, writer, reader, description) \
2117 do { \
2118 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, s, writer, reader, \
2119 NULL, NULL, description); \
2120 if (RT_FAILURE(rc)) \
2121 return rc; \
2122 } while (0)
2123 R(SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
2124#ifdef DEBUG_ACPI
2125 R(DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
2126 R(DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
2127#endif
2128 R(BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
2129 R(BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
2130 R(SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
2131 R(SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
2132 R(ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
2133#undef R
2134
2135 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, dev,
2136 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "ACPI Timer", &s->tsR3);
2137 if (RT_FAILURE(rc))
2138 {
2139 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
2140 return rc;
2141 }
2142
2143 s->tsR0 = TMTimerR0Ptr(s->tsR3);
2144 s->tsRC = TMTimerRCPtr(s->tsR3);
2145 s->pm_timer_initial = TMTimerGet(s->tsR3);
2146 acpiPMTimerReset(s);
2147
2148 PCIDevSetVendorId(dev, 0x8086); /* Intel */
2149 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
2150
2151 /* See p. 50 of PIIX4 manual */
2152 dev->config[0x04] = 0x01; /* command */
2153 dev->config[0x05] = 0x00;
2154
2155 dev->config[0x06] = 0x80; /* status */
2156 dev->config[0x07] = 0x02;
2157
2158 dev->config[0x08] = 0x08; /* revision number */
2159
2160 dev->config[0x09] = 0x00; /* class code */
2161 dev->config[0x0a] = 0x80;
2162 dev->config[0x0b] = 0x06;
2163
2164 dev->config[0x0e] = 0x80; /* header type */
2165
2166 dev->config[0x0f] = 0x00; /* reserved */
2167
2168 dev->config[0x3c] = SCI_INT; /* interrupt line */
2169
2170#if 0
2171 dev->config[0x3d] = 0x01; /* interrupt pin */
2172#endif
2173
2174 dev->config[0x40] = 0x01; /* PM base address, this bit marks it as IO range, not PA */
2175
2176 rc = PDMDevHlpPCIRegister(pDevIns, dev);
2177 if (RT_FAILURE(rc))
2178 return rc;
2179
2180 PDMDevHlpPCISetConfigCallbacks(pDevIns, dev,
2181 acpiPciConfigRead, &s->pfnAcpiPciConfigRead,
2182 acpiPciConfigWrite, &s->pfnAcpiPciConfigWrite);
2183
2184 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 5, sizeof(*s),
2185 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
2186 if (RT_FAILURE(rc))
2187 return rc;
2188
2189 /*
2190 * Interfaces
2191 */
2192 /* IBase */
2193 s->IBase.pfnQueryInterface = acpiQueryInterface;
2194 /* IACPIPort */
2195 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
2196 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
2197 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
2198 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
2199
2200 /*
2201 * Get the corresponding connector interface
2202 */
2203 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
2204 if (RT_SUCCESS(rc))
2205 {
2206 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface(s->pDrvBase, PDMINTERFACE_ACPI_CONNECTOR);
2207 if (!s->pDrv)
2208 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
2209 N_("LUN #0 doesn't have an ACPI connector interface"));
2210 }
2211 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2212 {
2213 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2214 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2215 rc = VINF_SUCCESS;
2216 }
2217 else
2218 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
2219
2220 return rc;
2221}
2222
2223/**
2224 * Relocates the GC pointer members.
2225 */
2226static DECLCALLBACK(void) acpiRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2227{
2228 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2229 s->tsRC = TMTimerRCPtr(s->CTX_SUFF(ts));
2230}
2231
2232static DECLCALLBACK(void) acpiReset(PPDMDEVINS pDevIns)
2233{
2234 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2235
2236 s->pm1a_en = 0;
2237 s->pm1a_sts = 0;
2238 s->pm1a_ctl = 0;
2239 s->pm_timer_initial = TMTimerGet(s->CTX_SUFF(ts));
2240 acpiPMTimerReset(s);
2241 s->uBatteryIndex = 0;
2242 s->uSystemInfoIndex = 0;
2243 s->gpe0_en = 0;
2244 s->gpe0_sts = 0;
2245 s->uSleepState = 0;
2246
2247 /** @todo Should we really reset PM base? */
2248 acpiUpdatePmHandlers(s, PM_PORT_BASE);
2249
2250 acpiPlantTables(s);
2251}
2252
2253/**
2254 * The device registration structure.
2255 */
2256const PDMDEVREG g_DeviceACPI =
2257{
2258 /* u32Version */
2259 PDM_DEVREG_VERSION,
2260 /* szDeviceName */
2261 "acpi",
2262 /* szRCMod */
2263 "VBoxDDGC.gc",
2264 /* szR0Mod */
2265 "VBoxDDR0.r0",
2266 /* pszDescription */
2267 "Advanced Configuration and Power Interface",
2268 /* fFlags */
2269 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2270 /* fClass */
2271 PDM_DEVREG_CLASS_ACPI,
2272 /* cMaxInstances */
2273 ~0,
2274 /* cbInstance */
2275 sizeof(ACPIState),
2276 /* pfnConstruct */
2277 acpiConstruct,
2278 /* pfnDestruct */
2279 NULL,
2280 /* pfnRelocate */
2281 acpiRelocate,
2282 /* pfnIOCtl */
2283 NULL,
2284 /* pfnPowerOn */
2285 NULL,
2286 /* pfnReset */
2287 acpiReset,
2288 /* pfnSuspend */
2289 NULL,
2290 /* pfnResume */
2291 NULL,
2292 /* pfnAttach */
2293 NULL,
2294 /* pfnDetach */
2295 NULL,
2296 /* pfnQueryInterface. */
2297 NULL,
2298 /* pfnInitComplete */
2299 NULL,
2300 /* pfnPowerOff */
2301 NULL,
2302 /* pfnSoftReset */
2303 NULL,
2304 /* u32VersionEnd */
2305 PDM_DEVREG_VERSION
2306};
2307
2308#endif /* IN_RING3 */
2309#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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