VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 44582

Last change on this file since 44582 was 44514, checked in by vboxsync, 12 years ago

DevACPI cleanups.
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File size: 120.7 KB
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1/* $Id: DevACPI.cpp 44514 2013-02-01 14:26:03Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_ACPI
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/dbgftrace.h>
25#include <VBox/vmm/vmcpuset.h>
26#include <VBox/log.h>
27#include <VBox/param.h>
28#include <iprt/assert.h>
29#include <iprt/asm.h>
30#include <iprt/asm-math.h>
31#include <iprt/file.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35# include <iprt/uuid.h>
36#endif /* IN_RING3 */
37
38#include "VBoxDD.h"
39
40#ifdef LOG_ENABLED
41# define DEBUG_ACPI
42#endif
43
44
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49#ifdef IN_RING3
50/** Locks the device state, ring-3 only. */
51# define DEVACPI_LOCK_R3(a_pThis) \
52 do { \
53 int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
54 AssertRC(rcLock); \
55 } while (0)
56#endif
57/** Unlocks the device state (all contexts). */
58#define DEVACPI_UNLOCK(a_pThis) \
59 do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
60
61
62#define DEBUG_HEX 0x3000
63#define DEBUG_CHR 0x3001
64
65#define PM_TMR_FREQ 3579545
66/* Default base for PM PIIX4 device */
67#define PM_PORT_BASE 0x4000
68/* Port offsets in PM device */
69enum
70{
71 PM1a_EVT_OFFSET = 0x00,
72 PM1b_EVT_OFFSET = -1, /**< not supported */
73 PM1a_CTL_OFFSET = 0x04,
74 PM1b_CTL_OFFSET = -1, /**< not supported */
75 PM2_CTL_OFFSET = -1, /**< not supported */
76 PM_TMR_OFFSET = 0x08,
77 GPE0_OFFSET = 0x20,
78 GPE1_OFFSET = -1 /**< not supported */
79};
80
81#define BAT_INDEX 0x00004040
82#define BAT_DATA 0x00004044
83#define SYSI_INDEX 0x00004048
84#define SYSI_DATA 0x0000404c
85#define ACPI_RESET_BLK 0x00004050
86
87/* PM1x status register bits */
88#define TMR_STS RT_BIT(0)
89#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
90#define BM_STS RT_BIT(4)
91#define GBL_STS RT_BIT(5)
92#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
93#define PWRBTN_STS RT_BIT(8)
94#define SLPBTN_STS RT_BIT(9)
95#define RTC_STS RT_BIT(10)
96#define IGN_STS RT_BIT(11)
97#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
98#define WAK_STS RT_BIT(15)
99#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
100
101/* PM1x enable register bits */
102#define TMR_EN RT_BIT(0)
103#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
104#define GBL_EN RT_BIT(5)
105#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
106#define PWRBTN_EN RT_BIT(8)
107#define SLPBTN_EN RT_BIT(9)
108#define RTC_EN RT_BIT(10)
109#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
110#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
111#define IGN_EN 0
112
113/* PM1x control register bits */
114#define SCI_EN RT_BIT(0)
115#define BM_RLD RT_BIT(1)
116#define GBL_RLS RT_BIT(2)
117#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
118#define IGN_CNT RT_BIT(9)
119#define SLP_TYPx_SHIFT 10
120#define SLP_TYPx_MASK 7
121#define SLP_EN RT_BIT(13)
122#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
123#define RSR_CNT (RSR1_CNT | RSR2_CNT)
124
125#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
126
127enum
128{
129 BAT_STATUS_STATE = 0x00, /**< BST battery state */
130 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
131 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
132 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
133 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
134 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
135 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
136 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
137 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
138 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
139 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
140 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
141 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
142 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
143 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
144 BAT_INDEX_LAST
145};
146
147enum
148{
149 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
150 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
151};
152
153enum
154{
155 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
156 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
157 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
158 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
159 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
160 SYSTEM_INFO_INDEX_CPU0_STATUS = 5, /**< For compatibility with older saved states. */
161 SYSTEM_INFO_INDEX_CPU1_STATUS = 6, /**< For compatibility with older saved states. */
162 SYSTEM_INFO_INDEX_CPU2_STATUS = 7, /**< For compatibility with older saved states. */
163 SYSTEM_INFO_INDEX_CPU3_STATUS = 8, /**< For compatibility with older saved states. */
164 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 9,
165 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
166 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
167 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
168 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
169 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
170 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
171 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
172 SYSTEM_INFO_INDEX_POWER_STATES = 17,
173 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
174 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
175 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
176 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
177 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
178 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
179 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
180 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
181 SYSTEM_INFO_INDEX_END = 26,
182 SYSTEM_INFO_INDEX_INVALID = 0x80,
183 SYSTEM_INFO_INDEX_VALID = 0x200
184};
185
186#define AC_OFFLINE 0
187#define AC_ONLINE 1
188
189#define BAT_TECH_PRIMARY 1
190#define BAT_TECH_SECONDARY 2
191
192#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
193#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
194#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
195#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
196#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
197
198
199/*******************************************************************************
200* Structures and Typedefs *
201*******************************************************************************/
202/**
203 * The ACPI device state.
204 */
205typedef struct ACPIState
206{
207 PCIDevice dev;
208 /** Critical section protecting the ACPI state. */
209 PDMCRITSECT CritSect;
210
211 uint16_t pm1a_en;
212 uint16_t pm1a_sts;
213 uint16_t pm1a_ctl;
214 /** Number of logical CPUs in guest */
215 uint16_t cCpus;
216 uint64_t u64PmTimerInitial;
217 PTMTIMERR3 pPmTimerR3;
218 PTMTIMERR0 pPmTimerR0;
219 PTMTIMERRC pPmTimerRC;
220
221 uint32_t gpe0_en;
222 uint32_t gpe0_sts;
223
224 uint32_t uBatteryIndex;
225 uint32_t au8BatteryInfo[13];
226
227 uint32_t uSystemInfoIndex;
228 uint64_t u64RamSize;
229 /** The number of bytes above 4GB. */
230 uint64_t cbRamHigh;
231 /** The number of bytes below 4GB. */
232 uint32_t cbRamLow;
233
234 /** Current ACPI S* state. We support S0 and S5. */
235 uint32_t uSleepState;
236 uint8_t au8RSDPPage[0x1000];
237 /** This is a workaround for incorrect index field handling by Intels ACPICA.
238 * The system info _INI method writes to offset 0x200. We either observe a
239 * write request to index 0x80 (in that case we don't change the index) or a
240 * write request to offset 0x200 (in that case we divide the index value by
241 * 4. Note that the _STA method is sometimes called prior to the _INI method
242 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
243 * acpiR3BatIndexWrite() for handling this. */
244 uint8_t u8IndexShift;
245 /** provide an I/O-APIC */
246 uint8_t u8UseIOApic;
247 /** provide a floppy controller */
248 bool fUseFdc;
249 /** If High Precision Event Timer device should be supported */
250 bool fUseHpet;
251 /** If System Management Controller device should be supported */
252 bool fUseSmc;
253 /** the guest handled the last power button event */
254 bool fPowerButtonHandled;
255 /** If ACPI CPU device should be shown */
256 bool fShowCpu;
257 /** If Real Time Clock ACPI object to be shown */
258 bool fShowRtc;
259 /** I/O port address of PM device. */
260 RTIOPORT uPmIoPortBase;
261 /** Flag whether the GC part of the device is enabled. */
262 bool fGCEnabled;
263 /** Flag whether the R0 part of the device is enabled. */
264 bool fR0Enabled;
265 /** Array of flags of attached CPUs */
266 VMCPUSET CpuSetAttached;
267 /** Which CPU to check for the locked status. */
268 uint32_t idCpuLockCheck;
269 /** Mask of locked CPUs (used by the guest). */
270 VMCPUSET CpuSetLocked;
271 /** The CPU event type. */
272 uint32_t u32CpuEventType;
273 /** The CPU id affected. */
274 uint32_t u32CpuEvent;
275 /** Flag whether CPU hot plugging is enabled. */
276 bool fCpuHotPlug;
277 /** If MCFG ACPI table shown to the guest */
278 bool fUseMcfg;
279 /** Primary NIC PCI address. */
280 uint32_t u32NicPciAddress;
281 /** Primary audio card PCI address. */
282 uint32_t u32AudioPciAddress;
283 /** Flag whether S1 power state is enabled. */
284 bool fS1Enabled;
285 /** Flag whether S4 power state is enabled. */
286 bool fS4Enabled;
287 /** Flag whether S1 triggers a state save. */
288 bool fSuspendToSavedState;
289 /** Flag whether to set WAK_STS on resume (restore included). */
290 bool fSetWakeupOnResume;
291 /** PCI address of the IO controller device. */
292 uint32_t u32IocPciAddress;
293 /** PCI address of the host bus controller device. */
294 uint32_t u32HbcPciAddress;
295 /* Physical address of PCI config space MMIO region */
296 uint64_t u64PciConfigMMioAddress;
297 /* Length of PCI config space MMIO region */
298 uint64_t u64PciConfigMMioLength;
299 /** Serial 0 IRQ number */
300 uint8_t uSerial0Irq;
301 /** Serial 1 IRQ number */
302 uint8_t uSerial1Irq;
303 /** Serial 0 IO port base */
304 RTIOPORT uSerial0IoPortBase;
305 /** Serial 1 IO port base */
306 RTIOPORT uSerial1IoPortBase;
307 /** ACPI port base interface. */
308 PDMIBASE IBase;
309 /** ACPI port interface. */
310 PDMIACPIPORT IACPIPort;
311 /** Pointer to the device instance. */
312 PPDMDEVINSR3 pDevIns;
313 /** Pointer to the driver base interface. */
314 R3PTRTYPE(PPDMIBASE) pDrvBase;
315 /** Pointer to the driver connector interface. */
316 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
317
318 /** Pointer to default PCI config read function. */
319 R3PTRTYPE(PFNPCICONFIGREAD) pfnAcpiPciConfigRead;
320 /** Pointer to default PCI config write function. */
321 R3PTRTYPE(PFNPCICONFIGWRITE) pfnAcpiPciConfigWrite;
322
323 /** If custom table should be supported */
324 bool fUseCust;
325 /** ACPI OEM ID */
326 uint8_t au8OemId[6];
327 /** ACPI Crator ID */
328 uint8_t au8CreatorId[4];
329 /** ACPI Crator Rev */
330 uint32_t u32CreatorRev;
331 /** ACPI custom OEM Tab ID */
332 uint8_t au8OemTabId[8];
333 /** ACPI custom OEM Rev */
334 uint32_t u32OemRevision;
335 uint32_t Alignment0;
336
337 /** The custom table binary data. */
338 R3PTRTYPE(uint8_t *) pu8CustBin;
339 /** The size of the custom table binary. */
340 uint64_t cbCustBin;
341} ACPIState;
342
343#pragma pack(1)
344
345/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
346struct ACPIGENADDR
347{
348 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
349 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
350 uint8_t u8RegisterBitOffset; /**< bit offset of register */
351 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
352 uint64_t u64Address; /**< 64-bit address of register */
353};
354AssertCompileSize(ACPIGENADDR, 12);
355
356/** Root System Description Pointer */
357struct ACPITBLRSDP
358{
359 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
360 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
361 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
362 uint8_t u8Revision; /**< revision number, currently 2 */
363#define ACPI_REVISION 2 /**< ACPI 3.0 */
364 uint32_t u32RSDT; /**< phys addr of RSDT */
365 uint32_t u32Length; /**< bytes of this table */
366 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
367 uint8_t u8ExtChecksum; /**< checksum of entire table */
368 uint8_t u8Reserved[3]; /**< reserved */
369};
370AssertCompileSize(ACPITBLRSDP, 36);
371
372/** System Description Table Header */
373struct ACPITBLHEADER
374{
375 uint8_t au8Signature[4]; /**< table identifier */
376 uint32_t u32Length; /**< length of the table including header */
377 uint8_t u8Revision; /**< revision number */
378 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
379 uint8_t au8OemId[6]; /**< OEM-supplied string */
380 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
381 uint32_t u32OemRevision; /**< OEM-supplied revision number */
382 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
383 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
384};
385AssertCompileSize(ACPITBLHEADER, 36);
386
387/** Root System Description Table */
388struct ACPITBLRSDT
389{
390 ACPITBLHEADER header;
391 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
392};
393AssertCompileSize(ACPITBLRSDT, 40);
394
395/** Extended System Description Table */
396struct ACPITBLXSDT
397{
398 ACPITBLHEADER header;
399 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
400};
401AssertCompileSize(ACPITBLXSDT, 44);
402
403/** Fixed ACPI Description Table */
404struct ACPITBLFADT
405{
406 ACPITBLHEADER header;
407 uint32_t u32FACS; /**< phys. address of FACS */
408 uint32_t u32DSDT; /**< phys. address of DSDT */
409 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
410#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
411#define INT_MODEL_MULTIPLE_APIC 2
412 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
413 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
414#define SCI_INT 9
415 uint32_t u32SMICmd; /**< system port address of SMI command port */
416#define SMI_CMD 0x0000442e
417 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
418#define ACPI_ENABLE 0xa1
419 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
420#define ACPI_DISABLE 0xa0
421 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
422 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
423 state control responsibility */
424 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
425 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
426 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
427 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
428 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
429 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
430 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
431 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
432 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
433 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
434 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
435 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
436 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
437#define GPE0_BLK_LEN 2
438 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
439#define GPE1_BLK_LEN 0
440 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
441#define GPE1_BASE 0
442 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
443 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
444#define P_LVL2_LAT 101 /**< C2 state not supported */
445 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
446#define P_LVL3_LAT 1001 /**< C3 state not supported */
447 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
448 lines from any processors memory caches */
449#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
450 uint16_t u16FlushStride; /**< cache line width */
451#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
452 uint8_t u8DutyOffset;
453 uint8_t u8DutyWidth;
454 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
455 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
456 uint8_t u8Century; /**< RTC CMOS RAM index of century */
457 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
458#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
459 (COM too?) */
460#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
461#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
462 uint8_t u8Must0_0; /**< must be 0 */
463 uint32_t u32Flags; /**< fixed feature flags */
464#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
465#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
466#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
467#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
468#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
469#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
470#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
471#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
472#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
473#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
474#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
475#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
476#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
477#define FADT_FL_CPU_SW_SLP RT_BIT(13)
478#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
479#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
480#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
481#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
482#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
483#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
484
485 /** Start of the ACPI 2.0 extension. */
486 ACPIGENADDR ResetReg; /**< ext addr of reset register */
487 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
488#define ACPI_RESET_REG_VAL 0x10
489 uint8_t au8Must0_1[3]; /**< must be 0 */
490 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
491 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
492 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
493 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
494 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
495 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
496 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
497 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
498 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
499 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
500};
501AssertCompileSize(ACPITBLFADT, 244);
502#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
503
504/** Firmware ACPI Control Structure */
505struct ACPITBLFACS
506{
507 uint8_t au8Signature[4]; /**< 'FACS' */
508 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
509 uint32_t u32HWSignature; /**< systems HW signature at last boot */
510 uint32_t u32FWVector; /**< address of waking vector */
511 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
512 uint32_t u32Flags; /**< FACS flags */
513 uint64_t u64X_FWVector; /**< 64-bit waking vector */
514 uint8_t u8Version; /**< version of this table */
515 uint8_t au8Reserved[31]; /**< zero */
516};
517AssertCompileSize(ACPITBLFACS, 64);
518
519/** Processor Local APIC Structure */
520struct ACPITBLLAPIC
521{
522 uint8_t u8Type; /**< 0 = LAPIC */
523 uint8_t u8Length; /**< 8 */
524 uint8_t u8ProcId; /**< processor ID */
525 uint8_t u8ApicId; /**< local APIC ID */
526 uint32_t u32Flags; /**< Flags */
527#define LAPIC_ENABLED 0x1
528};
529AssertCompileSize(ACPITBLLAPIC, 8);
530
531/** I/O APIC Structure */
532struct ACPITBLIOAPIC
533{
534 uint8_t u8Type; /**< 1 == I/O APIC */
535 uint8_t u8Length; /**< 12 */
536 uint8_t u8IOApicId; /**< I/O APIC ID */
537 uint8_t u8Reserved; /**< 0 */
538 uint32_t u32Address; /**< phys address to access I/O APIC */
539 uint32_t u32GSIB; /**< global system interrupt number to start */
540};
541AssertCompileSize(ACPITBLIOAPIC, 12);
542
543/** Interrupt Source Override Structure */
544struct ACPITBLISO
545{
546 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
547 uint8_t u8Length; /**< 10 */
548 uint8_t u8Bus; /**< Bus */
549 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
550 uint32_t u32GSI; /**< Global System Interrupt */
551 uint16_t u16Flags; /**< MPS INTI flags Global */
552};
553AssertCompileSize(ACPITBLISO, 10);
554#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
555
556/** HPET Descriptor Structure */
557struct ACPITBLHPET
558{
559 ACPITBLHEADER aHeader;
560 uint32_t u32Id; /**< hardware ID of event timer block
561 [31:16] PCI vendor ID of first timer block
562 [15] legacy replacement IRQ routing capable
563 [14] reserved
564 [13] COUNT_SIZE_CAP counter size
565 [12:8] number of comparators in first timer block
566 [7:0] hardware rev ID */
567 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
568 uint8_t u32Number; /**< sequence number starting at 0 */
569 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
570 lost interrupts while the counter is programmed
571 to operate in periodic mode. Unit: clock tick. */
572 uint8_t u8Attributes; /**< page protection and OEM attribute. */
573};
574AssertCompileSize(ACPITBLHPET, 56);
575
576/** MCFG Descriptor Structure */
577typedef struct ACPITBLMCFG
578{
579 ACPITBLHEADER aHeader;
580 uint64_t u64Reserved;
581} ACPITBLMCFG;
582AssertCompileSize(ACPITBLMCFG, 44);
583
584/** Number of such entries can be computed from the whole table length in header */
585typedef struct ACPITBLMCFGENTRY
586{
587 uint64_t u64BaseAddress;
588 uint16_t u16PciSegmentGroup;
589 uint8_t u8StartBus;
590 uint8_t u8EndBus;
591 uint32_t u32Reserved;
592} ACPITBLMCFGENTRY;
593AssertCompileSize(ACPITBLMCFGENTRY, 16);
594
595#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
596
597/** Custom Description Table */
598struct ACPITBLCUST
599{
600 ACPITBLHEADER header;
601 uint8_t au8Data[476];
602};
603AssertCompileSize(ACPITBLCUST, 512);
604
605
606#pragma pack()
607
608
609#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
610/*******************************************************************************
611* Internal Functions *
612*******************************************************************************/
613RT_C_DECLS_BEGIN
614PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
615RT_C_DECLS_END
616#ifdef IN_RING3
617static int acpiR3PlantTables(ACPIState *pThis);
618#endif
619
620#ifdef IN_RING3
621
622/* SCI IRQ */
623DECLINLINE(void) acpiR3SetIrq(ACPIState *pThis, int level)
624{
625 if (pThis->pm1a_ctl & SCI_EN)
626 PDMDevHlpPCISetIrq(pThis->pDevIns, 0, level);
627}
628
629DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
630{
631 return en & ~(RSR_EN | IGN_EN);
632}
633
634DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
635{
636 return sts & ~(RSR_STS | IGN_STS);
637}
638
639DECLINLINE(int) pm1a_level(ACPIState *pThis)
640{
641 return (pm1a_pure_en(pThis->pm1a_en) & pm1a_pure_sts(pThis->pm1a_sts)) != 0;
642}
643
644DECLINLINE(bool) gpe0_level(ACPIState *pThis)
645{
646 return (pThis->gpe0_en & pThis->gpe0_sts) != 0;
647}
648
649/**
650 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
651 * acpiR3Port_PowerBuffonPress and acpiR3Port_SleepButtonPress to
652 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
653 *
654 * Caller must hold the state lock.
655 *
656 * @param pThis The ACPI instance.
657 * @param sts The new GPE0.STS value.
658 * @param en The new GPE0.EN value.
659 */
660static void apicR3UpdatePm1a(ACPIState *pThis, uint32_t sts, uint32_t en)
661{
662 Assert(PDMCritSectIsOwner(&pThis->CritSect));
663
664 if (gpe0_level(pThis))
665 return;
666
667 int const old_level = pm1a_level(pThis);
668 int const new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
669
670 Log(("apicR3UpdatePm1a() old=%x new=%x\n", old_level, new_level));
671
672 pThis->pm1a_en = en;
673 pThis->pm1a_sts = sts;
674
675 if (new_level != old_level)
676 acpiR3SetIrq(pThis, new_level);
677}
678
679/**
680 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
681 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
682 *
683 * Caller must hold the state lock.
684 *
685 * @param pThis The ACPI instance.
686 * @param sts The new GPE0.STS value.
687 * @param en The new GPE0.EN value.
688 */
689static void apicR3UpdateGpe0(ACPIState *pThis, uint32_t sts, uint32_t en)
690{
691 Assert(PDMCritSectIsOwner(&pThis->CritSect));
692
693 if (pm1a_level(pThis))
694 return;
695
696 int const old_level = (pThis->gpe0_en & pThis->gpe0_sts) != 0;
697 int const new_level = (en & sts) != 0;
698
699 pThis->gpe0_en = en;
700 pThis->gpe0_sts = sts;
701
702 if (new_level != old_level)
703 acpiR3SetIrq(pThis, new_level);
704}
705
706/**
707 * Used by acpiR3PM1aCtlWrite to power off the VM.
708 *
709 * @param pThis The ACPI instance.
710 * @returns Strict VBox status code.
711 */
712static int acpiR3DoPowerOff(ACPIState *pThis)
713{
714 int rc = PDMDevHlpVMPowerOff(pThis->pDevIns);
715 if (RT_FAILURE(rc))
716 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
717 return rc;
718}
719
720/**
721 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
722 *
723 * @param pThis The ACPI instance.
724 * @returns Strict VBox status code.
725 */
726static int acpiR3DoSleep(ACPIState *pThis)
727{
728 /* We must set WAK_STS on resume (includes restore) so the guest knows that
729 we've woken up and can continue executing code. The guest is probably
730 reading the PMSTS register in a loop to check this. */
731 int rc;
732 pThis->fSetWakeupOnResume = true;
733 if (pThis->fSuspendToSavedState)
734 {
735 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pThis->pDevIns);
736 if (rc != VERR_NOT_SUPPORTED)
737 AssertRC(rc);
738 else
739 {
740 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
741 rc = PDMDevHlpVMSuspend(pThis->pDevIns);
742 AssertRC(rc);
743 }
744 }
745 else
746 {
747 rc = PDMDevHlpVMSuspend(pThis->pDevIns);
748 AssertRC(rc);
749 }
750 return rc;
751}
752
753
754/**
755 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
756 */
757static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
758{
759 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
760 DEVACPI_LOCK_R3(pThis);
761
762 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
763 pThis->fPowerButtonHandled = false;
764 apicR3UpdatePm1a(pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
765
766 DEVACPI_UNLOCK(pThis);
767 return VINF_SUCCESS;
768}
769
770/**
771 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
772 */
773static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
774{
775 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
776 DEVACPI_LOCK_R3(pThis);
777
778 *pfHandled = pThis->fPowerButtonHandled;
779
780 DEVACPI_UNLOCK(pThis);
781 return VINF_SUCCESS;
782}
783
784/**
785 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
786 * Guest entered into G0 (working) or G1 (sleeping)}
787 */
788static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
789{
790 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
791 DEVACPI_LOCK_R3(pThis);
792
793 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
794
795 DEVACPI_UNLOCK(pThis);
796 return VINF_SUCCESS;
797}
798
799/**
800 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
801 */
802static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
803{
804 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
805 DEVACPI_LOCK_R3(pThis);
806
807 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
808
809 DEVACPI_UNLOCK(pThis);
810 return VINF_SUCCESS;
811}
812
813/**
814 * Send an ACPI sleep button event.
815 *
816 * @returns VBox status code
817 * @param pInterface Pointer to the interface structure containing the called function pointer.
818 */
819static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
820{
821 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
822 DEVACPI_LOCK_R3(pThis);
823
824 apicR3UpdatePm1a(pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
825
826 DEVACPI_UNLOCK(pThis);
827 return VINF_SUCCESS;
828}
829
830/**
831 * Used by acpiR3PmTimer to re-arm the PM timer.
832 *
833 * The caller is expected to either hold the clock lock or to have made sure
834 * the VM is resetting or loading state.
835 *
836 * @param pThis The ACPI instance.
837 * @param uNow The current time.
838 */
839static void acpiR3PmTimerReset(ACPIState *pThis, uint64_t uNow)
840{
841 uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer));
842 uint64_t uInterval = ASMMultU64ByU32DivByU32(0xffffffff, uTimerFreq, PM_TMR_FREQ);
843 TMTimerSet(pThis->pPmTimerR3, uNow + uInterval);
844 Log(("acpi: uInterval = %RU64\n", uInterval));
845}
846
847/**
848 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
849 */
850static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
851{
852 ACPIState *pThis = (ACPIState *)pvUser;
853 Assert(TMTimerIsLockOwner(pTimer));
854 NOREF(pDevIns);
855
856 DEVACPI_LOCK_R3(pThis);
857 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
858 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
859 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
860 apicR3UpdatePm1a(pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
861 DEVACPI_UNLOCK(pThis);
862
863 acpiR3PmTimerReset(pThis, TMTimerGet(pTimer));
864}
865
866/**
867 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
868 * acpiR3LoadState.
869 *
870 * @returns VINF_SUCCESS.
871 * @param pThis The ACPI instance.
872 */
873static int acpiR3FetchBatteryStatus(ACPIState *pThis)
874{
875 uint32_t *p = pThis->au8BatteryInfo;
876 bool fPresent; /* battery present? */
877 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
878 PDMACPIBATSTATE hostBatteryState; /* bitfield */
879 uint32_t hostPresentRate; /* 0..1000 */
880 int rc;
881
882 if (!pThis->pDrv)
883 return VINF_SUCCESS;
884 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
885 &hostBatteryState, &hostPresentRate);
886 AssertRC(rc);
887
888 /* default values */
889 p[BAT_STATUS_STATE] = hostBatteryState;
890 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
891 : hostPresentRate * 50; /* mW */
892 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
893 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
894
895 /* did we get a valid battery state? */
896 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
897 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
898 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
899 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
900
901 return VINF_SUCCESS;
902}
903
904/**
905 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
906 * acpiR3LoadState.
907 *
908 * @returns VINF_SUCCESS.
909 * @param pThis The ACPI instance.
910 */
911static int acpiR3FetchBatteryInfo(ACPIState *pThis)
912{
913 uint32_t *p = pThis->au8BatteryInfo;
914
915 p[BAT_INFO_UNITS] = 0; /* mWh */
916 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
917 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
918 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
919 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
920 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
921 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
922 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
923 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
924
925 return VINF_SUCCESS;
926}
927
928/**
929 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
930 *
931 * @returns status mask or 0.
932 * @param pThis The ACPI instance.
933 */
934static uint32_t acpiR3GetBatteryDeviceStatus(ACPIState *pThis)
935{
936 bool fPresent; /* battery present? */
937 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
938 PDMACPIBATSTATE hostBatteryState; /* bitfield */
939 uint32_t hostPresentRate; /* 0..1000 */
940 int rc;
941
942 if (!pThis->pDrv)
943 return 0;
944 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
945 &hostBatteryState, &hostPresentRate);
946 AssertRC(rc);
947
948 return fPresent
949 ? STA_DEVICE_PRESENT_MASK /* present */
950 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
951 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
952 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
953 | STA_BATTERY_PRESENT_MASK /* battery is present */
954 : 0; /* device not present */
955}
956
957/**
958 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
959 *
960 * @returns status.
961 * @param pThis The ACPI instance.
962 */
963static uint32_t acpiR3GetPowerSource(ACPIState *pThis)
964{
965 /* query the current power source from the host driver */
966 if (!pThis->pDrv)
967 return AC_ONLINE;
968
969 PDMACPIPOWERSOURCE ps;
970 int rc = pThis->pDrv->pfnQueryPowerSource(pThis->pDrv, &ps);
971 AssertRC(rc);
972 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
973}
974
975/**
976 * @callback_method_impl{FNIOMIOPORTOUT, Battery status index}
977 */
978PDMBOTHCBDECL(int) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
979{
980 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
981 if (cb != 4)
982 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
983
984 ACPIState *pThis = (ACPIState *)pvUser;
985 DEVACPI_LOCK_R3(pThis);
986
987 u32 >>= pThis->u8IndexShift;
988 /* see comment at the declaration of u8IndexShift */
989 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
990 {
991 pThis->u8IndexShift = 2;
992 u32 >>= 2;
993 }
994 Assert(u32 < BAT_INDEX_LAST);
995 pThis->uBatteryIndex = u32;
996
997 DEVACPI_UNLOCK(pThis);
998 return VINF_SUCCESS;
999}
1000
1001/**
1002 * @callback_method_impl{FNIOMIOPORTIN, Battery status data}
1003 */
1004PDMBOTHCBDECL(int) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1005{
1006 if (cb != 4)
1007 return VERR_IOM_IOPORT_UNUSED;
1008
1009 ACPIState *pThis = (ACPIState *)pvUser;
1010 DEVACPI_LOCK_R3(pThis);
1011
1012 int rc = VINF_SUCCESS;
1013 switch (pThis->uBatteryIndex)
1014 {
1015 case BAT_STATUS_STATE:
1016 acpiR3FetchBatteryStatus(pThis);
1017 /* fall thru */
1018 case BAT_STATUS_PRESENT_RATE:
1019 case BAT_STATUS_REMAINING_CAPACITY:
1020 case BAT_STATUS_PRESENT_VOLTAGE:
1021 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1022 break;
1023
1024 case BAT_INFO_UNITS:
1025 acpiR3FetchBatteryInfo(pThis);
1026 /* fall thru */
1027 case BAT_INFO_DESIGN_CAPACITY:
1028 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1029 case BAT_INFO_TECHNOLOGY:
1030 case BAT_INFO_DESIGN_VOLTAGE:
1031 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1032 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1033 case BAT_INFO_CAPACITY_GRANULARITY_1:
1034 case BAT_INFO_CAPACITY_GRANULARITY_2:
1035 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1036 break;
1037
1038 case BAT_DEVICE_STATUS:
1039 *pu32 = acpiR3GetBatteryDeviceStatus(pThis);
1040 break;
1041
1042 case BAT_POWER_SOURCE:
1043 *pu32 = acpiR3GetPowerSource(pThis);
1044 break;
1045
1046 default:
1047 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1048 *pu32 = UINT32_MAX;
1049 break;
1050 }
1051
1052 DEVACPI_UNLOCK(pThis);
1053 return rc;
1054}
1055
1056/**
1057 * @callback_method_impl{FNIOMIOPORTOUT, System info index}
1058 */
1059PDMBOTHCBDECL(int) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1060{
1061 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1062 if (cb != 4)
1063 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1064
1065 ACPIState *pThis = (ACPIState *)pvUser;
1066 DEVACPI_LOCK_R3(pThis);
1067
1068 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1069 pThis->uSystemInfoIndex = u32;
1070 else
1071 {
1072 /* see comment at the declaration of u8IndexShift */
1073 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1074 {
1075 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1076 pThis->u8IndexShift = 2;
1077 }
1078
1079 u32 >>= pThis->u8IndexShift;
1080 Assert(u32 < SYSTEM_INFO_INDEX_END);
1081 pThis->uSystemInfoIndex = u32;
1082 }
1083
1084 DEVACPI_UNLOCK(pThis);
1085 return VINF_SUCCESS;
1086}
1087
1088/**
1089 * @callback_method_impl{FNIOMIOPORTIN, System info data}
1090 */
1091PDMBOTHCBDECL(int) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1092{
1093 if (cb != 4)
1094 return VERR_IOM_IOPORT_UNUSED;
1095
1096 ACPIState *pThis = (ACPIState *)pvUser;
1097 DEVACPI_LOCK_R3(pThis);
1098
1099 int rc = VINF_SUCCESS;
1100 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1101 switch (uSystemInfoIndex)
1102 {
1103 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1104 *pu32 = pThis->cbRamLow;
1105 break;
1106
1107 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1108 *pu32 = pThis->cbRamHigh >> 16; /* 64KB units */
1109 Assert(((uint64_t)*pu32 << 16) == pThis->cbRamHigh);
1110 break;
1111
1112 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1113 *pu32 = pThis->u8UseIOApic;
1114 break;
1115
1116 case SYSTEM_INFO_INDEX_HPET_STATUS:
1117 *pu32 = pThis->fUseHpet
1118 ? ( STA_DEVICE_PRESENT_MASK
1119 | STA_DEVICE_ENABLED_MASK
1120 | STA_DEVICE_SHOW_IN_UI_MASK
1121 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1122 : 0;
1123 break;
1124
1125 case SYSTEM_INFO_INDEX_SMC_STATUS:
1126 *pu32 = pThis->fUseSmc
1127 ? ( STA_DEVICE_PRESENT_MASK
1128 | STA_DEVICE_ENABLED_MASK
1129 /* no need to show this device in the UI */
1130 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1131 : 0;
1132 break;
1133
1134 case SYSTEM_INFO_INDEX_FDC_STATUS:
1135 *pu32 = pThis->fUseFdc
1136 ? ( STA_DEVICE_PRESENT_MASK
1137 | STA_DEVICE_ENABLED_MASK
1138 | STA_DEVICE_SHOW_IN_UI_MASK
1139 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1140 : 0;
1141 break;
1142
1143 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1144 *pu32 = pThis->u32NicPciAddress;
1145 break;
1146
1147 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1148 *pu32 = pThis->u32AudioPciAddress;
1149 break;
1150
1151 case SYSTEM_INFO_INDEX_POWER_STATES:
1152 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1153 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1154 *pu32 |= RT_BIT(1);
1155 if (pThis->fS4Enabled)
1156 *pu32 |= RT_BIT(4);
1157 break;
1158
1159 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1160 *pu32 = pThis->u32IocPciAddress;
1161 break;
1162
1163 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1164 *pu32 = pThis->u32HbcPciAddress;
1165 break;
1166
1167 case SYSTEM_INFO_INDEX_PCI_BASE:
1168 /** @todo couldn't MCFG be in 64-bit range? */
1169 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1170 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1171 break;
1172
1173 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1174 /** @todo couldn't MCFG be in 64-bit range? */
1175 Assert(pThis->u64PciConfigMMioLength< 0xffffffff);
1176 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1177 break;
1178
1179 /* This is only for compatibility with older saved states that
1180 may include ACPI code that read these values. Legacy is
1181 a wonderful thing, isn't it? :-) */
1182 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1183 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1184 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1185 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1186 *pu32 = ( pThis->fShowCpu
1187 && pThis->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < pThis->cCpus
1188 && VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached,
1189 pThis->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS) )
1190 ? ( STA_DEVICE_PRESENT_MASK
1191 | STA_DEVICE_ENABLED_MASK
1192 | STA_DEVICE_SHOW_IN_UI_MASK
1193 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1194 : 0;
1195 break;
1196
1197 case SYSTEM_INFO_INDEX_RTC_STATUS:
1198 *pu32 = pThis->fShowRtc
1199 ? ( STA_DEVICE_PRESENT_MASK
1200 | STA_DEVICE_ENABLED_MASK
1201 | STA_DEVICE_SHOW_IN_UI_MASK
1202 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1203 : 0;
1204 break;
1205
1206 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1207 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1208 {
1209 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1210 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1211 }
1212 else
1213 {
1214 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1215 pThis->idCpuLockCheck);
1216 /* Always return locked status just to be safe */
1217 *pu32 = 1;
1218 }
1219 break;
1220
1221 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1222 *pu32 = pThis->u32CpuEventType;
1223 break;
1224
1225 case SYSTEM_INFO_INDEX_CPU_EVENT:
1226 *pu32 = pThis->u32CpuEvent;
1227 break;
1228
1229 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1230 *pu32 = pThis->uSerial0IoPortBase;
1231 break;
1232
1233 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1234 *pu32 = pThis->uSerial0Irq;
1235 break;
1236
1237 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1238 *pu32 = pThis->uSerial1IoPortBase;
1239 break;
1240
1241 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1242 *pu32 = pThis->uSerial1Irq;
1243 break;
1244
1245 case SYSTEM_INFO_INDEX_END:
1246 /** @todo why isn't this setting any output value? */
1247 break;
1248
1249 /* Solaris 9 tries to read from this index */
1250 case SYSTEM_INFO_INDEX_INVALID:
1251 *pu32 = 0;
1252 break;
1253
1254 default:
1255 *pu32 = UINT32_MAX;
1256 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1257 break;
1258 }
1259
1260 DEVACPI_UNLOCK(pThis);
1261 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%d) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, rc));
1262 return rc;
1263}
1264
1265/**
1266 * @callback_method_impl{FNIOMIOPORTOUT, System info data}
1267 */
1268PDMBOTHCBDECL(int) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1269{
1270 ACPIState *pThis = (ACPIState *)pvUser;
1271 if (cb != 4)
1272 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1273
1274 DEVACPI_LOCK_R3(pThis);
1275 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, pThis->uSystemInfoIndex));
1276
1277 int rc = VINF_SUCCESS;
1278 switch (pThis->uSystemInfoIndex)
1279 {
1280 case SYSTEM_INFO_INDEX_INVALID:
1281 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1282 pThis->u8IndexShift = 0;
1283 break;
1284
1285 case SYSTEM_INFO_INDEX_VALID:
1286 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1287 pThis->u8IndexShift = 2;
1288 break;
1289
1290 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1291 pThis->idCpuLockCheck = u32;
1292 break;
1293
1294 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1295 if (u32 < pThis->cCpus)
1296 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1297 else
1298 LogRel(("ACPI: CPU %u does not exist\n", u32));
1299 break;
1300
1301 default:
1302 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1303 break;
1304 }
1305
1306 DEVACPI_UNLOCK(pThis);
1307 return rc;
1308}
1309
1310/**
1311 * @callback_method_impl{FNIOMIOPORTIN, PM1a Enable}
1312 */
1313PDMBOTHCBDECL(int) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1314{
1315 NOREF(pDevIns); NOREF(Port);
1316 if (cb != 2)
1317 return VERR_IOM_IOPORT_UNUSED;
1318
1319 ACPIState *pThis = (ACPIState *)pvUser;
1320 DEVACPI_LOCK_R3(pThis);
1321
1322 *pu32 = pThis->pm1a_en;
1323
1324 DEVACPI_UNLOCK(pThis);
1325 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1326 return VINF_SUCCESS;
1327}
1328
1329/**
1330 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Enable}
1331 */
1332PDMBOTHCBDECL(int) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1333{
1334 if (cb != 2 && cb != 4)
1335 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1336
1337 ACPIState *pThis = (ACPIState *)pvUser;
1338 DEVACPI_LOCK_R3(pThis);
1339
1340 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1341 u32 &= ~(RSR_EN | IGN_EN);
1342 u32 &= 0xffff;
1343 apicR3UpdatePm1a(pThis, pThis->pm1a_sts, u32);
1344
1345 DEVACPI_UNLOCK(pThis);
1346 return VINF_SUCCESS;
1347}
1348
1349/**
1350 * @callback_method_impl{FNIOMIOPORTIN, PM1a Status}
1351 */
1352PDMBOTHCBDECL(int) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1353{
1354 if (cb != 2)
1355 {
1356 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1357 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1358 }
1359
1360 ACPIState *pThis = (ACPIState *)pvUser;
1361 DEVACPI_LOCK_R3(pThis);
1362
1363 *pu32 = pThis->pm1a_sts;
1364
1365 DEVACPI_UNLOCK(pThis);
1366 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1367 return VINF_SUCCESS;
1368}
1369
1370/**
1371 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Status}
1372 */
1373PDMBOTHCBDECL(int) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1374{
1375 if (cb != 2 && cb != 4)
1376 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1377
1378 ACPIState *pThis = (ACPIState *)pvUser;
1379 DEVACPI_LOCK_R3(pThis);
1380
1381 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1382 u32 &= 0xffff;
1383 if (u32 & PWRBTN_STS)
1384 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1385 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1386 apicR3UpdatePm1a(pThis, u32, pThis->pm1a_en);
1387
1388 DEVACPI_UNLOCK(pThis);
1389 return VINF_SUCCESS;
1390}
1391
1392/**
1393 * @callback_method_impl{FNIOMIOPORTIN, PM1a Control}
1394 */
1395PDMBOTHCBDECL(int) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1396{
1397 if (cb != 2)
1398 {
1399 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1400 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1401 }
1402
1403 ACPIState *pThis = (ACPIState *)pvUser;
1404 DEVACPI_LOCK_R3(pThis);
1405
1406 *pu32 = pThis->pm1a_ctl;
1407
1408 DEVACPI_UNLOCK(pThis);
1409 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1410 return VINF_SUCCESS;
1411}
1412
1413/**
1414 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Control}
1415 */
1416PDMBOTHCBDECL(int) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1417{
1418 if (cb != 2 && cb != 4)
1419 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1420
1421 ACPIState *pThis = (ACPIState *)pvUser;
1422 DEVACPI_LOCK_R3(pThis);
1423
1424 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1425 u32 &= 0xffff;
1426 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1427
1428 int rc = VINF_SUCCESS;
1429 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1430 if (uSleepState != pThis->uSleepState)
1431 {
1432 pThis->uSleepState = uSleepState;
1433 switch (uSleepState)
1434 {
1435 case 0x00: /* S0 */
1436 break;
1437
1438 case 0x01: /* S1 */
1439 if (pThis->fS1Enabled)
1440 {
1441 LogRel(("Entering S1 power state (powered-on suspend)\n"));
1442 rc = acpiR3DoSleep(pThis);
1443 break;
1444 }
1445 LogRel(("Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1446 /* fall thru */
1447
1448 case 0x04: /* S4 */
1449 if (pThis->fS4Enabled)
1450 {
1451 LogRel(("Entering S4 power state (suspend to disk)\n"));
1452 rc = acpiR3DoPowerOff(pThis);/* Same behavior as S5 */
1453 break;
1454 }
1455 LogRel(("Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1456 /* fall thru */
1457
1458 case 0x05: /* S5 */
1459 LogRel(("Entering S5 power state (power down)\n"));
1460 rc = acpiR3DoPowerOff(pThis);
1461 break;
1462
1463 default:
1464 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1465 break;
1466 }
1467 }
1468
1469 DEVACPI_UNLOCK(pThis);
1470 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", rc));
1471 return rc;
1472}
1473
1474#endif /* IN_RING3 */
1475
1476/**
1477 * @callback_method_impl{FNIOMIOPORTIN, PMTMR}
1478 *
1479 * @remarks Only I/O port currently implemented in all contexts.
1480 */
1481PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1482{
1483 if (cb != 4)
1484 return VERR_IOM_IOPORT_UNUSED;
1485
1486 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1487
1488 /*
1489 * We use the clock lock to serialize access to u64PmTimerInitial and to
1490 * make sure we get a reliable time from the clock.
1491 */
1492 int rc = TMTimerLock(pThis->CTX_SUFF(pPmTimer), VINF_IOM_R3_IOPORT_READ);
1493 if (rc == VINF_SUCCESS)
1494 {
1495 uint64_t const u64PmTimerInitial = pThis->u64PmTimerInitial;
1496 uint64_t u64Now = TMTimerGet(pThis->CTX_SUFF(pPmTimer));
1497 TMTimerUnlock(pThis->CTX_SUFF(pPmTimer));
1498
1499 /*
1500 * Calculate the return value.
1501 */
1502 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1503 uint64_t u64Elapsed = u64Now - u64PmTimerInitial;
1504 *pu32 = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer)));
1505 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1506 }
1507
1508 NOREF(pvUser); NOREF(Port);
1509 return rc;
1510}
1511
1512#ifdef IN_RING3
1513
1514/**
1515 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Status}
1516 */
1517PDMBOTHCBDECL(int) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1518{
1519 if (cb != 1)
1520 {
1521 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1522 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1523 }
1524
1525 ACPIState *pThis = (ACPIState *)pvUser;
1526 DEVACPI_LOCK_R3(pThis);
1527
1528 *pu32 = pThis->gpe0_sts & 0xff;
1529
1530 DEVACPI_UNLOCK(pThis);
1531 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1532 return VINF_SUCCESS;
1533}
1534
1535/**
1536 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Status}
1537 */
1538PDMBOTHCBDECL(int) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1539{
1540 if (cb != 1)
1541 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1542
1543 ACPIState *pThis = (ACPIState *)pvUser;
1544 DEVACPI_LOCK_R3(pThis);
1545
1546 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1547 u32 = pThis->gpe0_sts & ~u32;
1548 apicR3UpdateGpe0(pThis, u32, pThis->gpe0_en);
1549
1550 DEVACPI_UNLOCK(pThis);
1551 return VINF_SUCCESS;
1552}
1553
1554/**
1555 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Enable}
1556 */
1557PDMBOTHCBDECL(int) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1558{
1559 if (cb != 1)
1560 {
1561 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1562 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1563 }
1564
1565 ACPIState *pThis = (ACPIState *)pvUser;
1566 DEVACPI_LOCK_R3(pThis);
1567
1568 *pu32 = pThis->gpe0_en & 0xff;
1569
1570 DEVACPI_UNLOCK(pThis);
1571 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1572 return VINF_SUCCESS;
1573}
1574
1575/**
1576 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Enable}
1577 */
1578PDMBOTHCBDECL(int) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1579{
1580 if (cb != 1)
1581 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1582
1583 ACPIState *pThis = (ACPIState *)pvUser;
1584 DEVACPI_LOCK_R3(pThis);
1585
1586 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1587 apicR3UpdateGpe0(pThis, pThis->gpe0_sts, u32);
1588
1589 DEVACPI_UNLOCK(pThis);
1590 return VINF_SUCCESS;
1591}
1592
1593/**
1594 * @callback_method_impl{FNIOMIOPORTOUT, SMI_CMD}
1595 */
1596PDMBOTHCBDECL(int) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1597{
1598 Log(("acpiR3SmiWrite %#x\n", u32));
1599 if (cb != 1)
1600 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1601
1602 ACPIState *pThis = (ACPIState *)pvUser;
1603 DEVACPI_LOCK_R3(pThis);
1604
1605 if (u32 == ACPI_ENABLE)
1606 pThis->pm1a_ctl |= SCI_EN;
1607 else if (u32 == ACPI_DISABLE)
1608 pThis->pm1a_ctl &= ~SCI_EN;
1609 else
1610 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1611
1612 DEVACPI_UNLOCK(pThis);
1613 return VINF_SUCCESS;
1614}
1615
1616/**
1617 * @{FNIOMIOPORTOUT, ACPI_RESET_BLK}
1618 */
1619PDMBOTHCBDECL(int) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1620{
1621 Log(("acpiR3ResetWrite: %#x\n", u32));
1622 NOREF(pvUser);
1623 if (cb != 1)
1624 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1625
1626 /* No state locking required. */
1627 int rc = VINF_SUCCESS;
1628 if (u32 == ACPI_RESET_REG_VAL)
1629 {
1630 LogRel(("Reset initiated by ACPI\n"));
1631 rc = PDMDevHlpVMReset(pDevIns);
1632 }
1633 else
1634 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1635
1636 return rc;
1637}
1638
1639# ifdef DEBUG_ACPI
1640
1641/**
1642 * @callback_method_impl{FNIOMIOPORTOUT, Debug hex value logger}
1643 */
1644PDMBOTHCBDECL(int) acpiR3DhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1645{
1646 NOREF(pvUser);
1647 switch (cb)
1648 {
1649 case 1:
1650 Log(("%#x\n", u32 & 0xff));
1651 break;
1652 case 2:
1653 Log(("%#6x\n", u32 & 0xffff));
1654 case 4:
1655 Log(("%#10x\n", u32));
1656 break;
1657 default:
1658 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1659 }
1660 return VINF_SUCCESS;
1661}
1662
1663/**
1664 * @callback_method_impl{FNIOMIOPORTOUT, Debug char logger}
1665 */
1666PDMBOTHCBDECL(int) acpiR3DchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1667{
1668 NOREF(pvUser);
1669 switch (cb)
1670 {
1671 case 1:
1672 Log(("%c", u32 & 0xff));
1673 break;
1674 default:
1675 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1676 }
1677 return VINF_SUCCESS;
1678}
1679
1680# endif /* DEBUG_ACPI */
1681
1682/**
1683 * Used to calculate the value of a PM I/O port.
1684 *
1685 * @returns The actual I/O port value.
1686 * @param pThis The ACPI instance.
1687 * @param offset The offset into the I/O space, or -1 if invalid.
1688 */
1689static RTIOPORT acpiR3CalcPmPort(ACPIState *pThis, int32_t offset)
1690{
1691 Assert(pThis->uPmIoPortBase != 0);
1692
1693 if (offset == -1)
1694 return 0;
1695
1696 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
1697}
1698
1699/**
1700 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to register the PM1a, PM
1701 * timer and GPE0 I/O ports.
1702 *
1703 * @returns VBox status code.
1704 * @param pThis The ACPI instance.
1705 */
1706static int acpiR3RegisterPmHandlers(ACPIState *pThis)
1707{
1708 int rc = VINF_SUCCESS;
1709
1710#define R(offset, cnt, writer, reader, description) \
1711 do { \
1712 rc = PDMDevHlpIOPortRegister(pThis->pDevIns, acpiR3CalcPmPort(pThis, offset), cnt, pThis, writer, reader, \
1713 NULL, NULL, description); \
1714 if (RT_FAILURE(rc)) \
1715 return rc; \
1716 } while (0)
1717#define L (GPE0_BLK_LEN / 2)
1718
1719 R(PM1a_EVT_OFFSET+2, 1, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, "ACPI PM1a Enable");
1720 R(PM1a_EVT_OFFSET, 1, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, "ACPI PM1a Status");
1721 R(PM1a_CTL_OFFSET, 1, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, "ACPI PM1a Control");
1722 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1723 R(GPE0_OFFSET + L, L, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, "ACPI GPE0 Enable");
1724 R(GPE0_OFFSET, L, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, "ACPI GPE0 Status");
1725#undef L
1726#undef R
1727
1728 /* register RC stuff */
1729 if (pThis->fGCEnabled)
1730 {
1731 rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
1732 1, 0, NULL, "acpiPMTmrRead",
1733 NULL, NULL, "ACPI PM Timer");
1734 AssertRCReturn(rc, rc);
1735 }
1736
1737 /* register R0 stuff */
1738 if (pThis->fR0Enabled)
1739 {
1740 rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
1741 1, 0, NULL, "acpiPMTmrRead",
1742 NULL, NULL, "ACPI PM Timer");
1743 AssertRCReturn(rc, rc);
1744 }
1745
1746 return rc;
1747}
1748
1749/**
1750 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unregister the PM1a, PM
1751 * timer and GPE0 I/O ports.
1752 *
1753 * @returns VBox status code.
1754 * @param pThis The ACPI instance.
1755 */
1756static int acpiR3UnregisterPmHandlers(ACPIState *pThis)
1757{
1758#define U(offset, cnt) \
1759 do { \
1760 int rc = PDMDevHlpIOPortDeregister(pThis->pDevIns, acpiR3CalcPmPort(pThis, offset), cnt); \
1761 AssertRCReturn(rc, rc); \
1762 } while (0)
1763#define L (GPE0_BLK_LEN / 2)
1764
1765 U(PM1a_EVT_OFFSET+2, 1);
1766 U(PM1a_EVT_OFFSET, 1);
1767 U(PM1a_CTL_OFFSET, 1);
1768 U(PM_TMR_OFFSET, 1);
1769 U(GPE0_OFFSET + L, L);
1770 U(GPE0_OFFSET, L);
1771#undef L
1772#undef U
1773
1774 return VINF_SUCCESS;
1775}
1776
1777/**
1778 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
1779 * PM1a, PM timer and GPE0 ports.
1780 *
1781 * @returns VBox status code.
1782 *
1783 * @param pThis The ACPI instance.
1784 * @param NewIoPortBase The new base address of the I/O ports.
1785 */
1786static int acpiR3UpdatePmHandlers(ACPIState *pThis, RTIOPORT NewIoPortBase)
1787{
1788 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
1789 if (NewIoPortBase != pThis->uPmIoPortBase)
1790 {
1791 int rc = acpiR3UnregisterPmHandlers(pThis);
1792 if (RT_FAILURE(rc))
1793 return rc;
1794
1795 pThis->uPmIoPortBase = NewIoPortBase;
1796
1797 rc = acpiR3RegisterPmHandlers(pThis);
1798 if (RT_FAILURE(rc))
1799 return rc;
1800
1801 /* We have to update FADT table acccording to the new base */
1802 rc = acpiR3PlantTables(pThis);
1803 AssertRC(rc);
1804 if (RT_FAILURE(rc))
1805 return rc;
1806 }
1807
1808 return VINF_SUCCESS;
1809}
1810
1811
1812/**
1813 * Saved state structure description, version 4.
1814 */
1815static const SSMFIELD g_AcpiSavedStateFields4[] =
1816{
1817 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1818 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1819 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1820 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
1821 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1822 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1823 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1824 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1825 SSMFIELD_ENTRY(ACPIState, u64RamSize),
1826 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1827 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1828 SSMFIELD_ENTRY(ACPIState, uSleepState),
1829 SSMFIELD_ENTRY_TERM()
1830};
1831
1832/**
1833 * Saved state structure description, version 5.
1834 */
1835static const SSMFIELD g_AcpiSavedStateFields5[] =
1836{
1837 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1838 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1839 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1840 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
1841 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1842 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1843 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1844 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1845 SSMFIELD_ENTRY(ACPIState, uSleepState),
1846 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1847 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
1848 SSMFIELD_ENTRY_TERM()
1849};
1850
1851/**
1852 * Saved state structure description, version 6.
1853 */
1854static const SSMFIELD g_AcpiSavedStateFields6[] =
1855{
1856 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1857 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1858 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1859 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
1860 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1861 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1862 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1863 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1864 SSMFIELD_ENTRY(ACPIState, uSleepState),
1865 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1866 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
1867 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
1868 SSMFIELD_ENTRY_TERM()
1869};
1870
1871
1872/**
1873 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1874 */
1875static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1876{
1877 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1878 return SSMR3PutStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields6[0]);
1879}
1880
1881/**
1882 * @callback_method_impl{FNSSMDEVLOADEXEC}
1883 */
1884static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
1885{
1886 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1887 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1888
1889 /*
1890 * Unregister PM handlers, will register with actual base after state
1891 * successfully loaded.
1892 */
1893 int rc = acpiR3UnregisterPmHandlers(pThis);
1894 if (RT_FAILURE(rc))
1895 return rc;
1896
1897 switch (uVersion)
1898 {
1899 case 4:
1900 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields4[0]);
1901 break;
1902 case 5:
1903 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields5[0]);
1904 break;
1905 case 6:
1906 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields6[0]);
1907 break;
1908 default:
1909 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1910 break;
1911 }
1912 if (RT_SUCCESS(rc))
1913 {
1914 rc = acpiR3RegisterPmHandlers(pThis);
1915 if (RT_FAILURE(rc))
1916 return rc;
1917 rc = acpiR3FetchBatteryStatus(pThis);
1918 if (RT_FAILURE(rc))
1919 return rc;
1920 rc = acpiR3FetchBatteryInfo(pThis);
1921 if (RT_FAILURE(rc))
1922 return rc;
1923 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);
1924 acpiR3PmTimerReset(pThis, TMTimerGet(pThis->pPmTimerR3));
1925 TMTimerUnlock(pThis->pPmTimerR3);
1926 }
1927 return rc;
1928}
1929
1930/**
1931 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1932 */
1933static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
1934{
1935 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IBase);
1936 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1937 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThis->IACPIPort);
1938 return NULL;
1939}
1940
1941/**
1942 * Calculate the check sum for some ACPI data before planting it.
1943 *
1944 * All the bytes must add up to 0.
1945 *
1946 * @returns check sum.
1947 * @param pvSrc What to check sum.
1948 * @param cbData The amount of data to checksum.
1949 */
1950static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
1951{
1952 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
1953 uint8_t uSum = 0;
1954 for (size_t i = 0; i < cbData; ++i)
1955 uSum += pbSrc[i];
1956 return -uSum;
1957}
1958
1959/**
1960 * Prepare a ACPI table header.
1961 */
1962static void acpiR3PrepareHeader(ACPIState *pThis, ACPITBLHEADER *header,
1963 const char au8Signature[4],
1964 uint32_t u32Length, uint8_t u8Revision)
1965{
1966 memcpy(header->au8Signature, au8Signature, 4);
1967 header->u32Length = RT_H2LE_U32(u32Length);
1968 header->u8Revision = u8Revision;
1969 memcpy(header->au8OemId, pThis->au8OemId, 6);
1970 memcpy(header->au8OemTabId, "VBOX", 4);
1971 memcpy(header->au8OemTabId+4, au8Signature, 4);
1972 header->u32OemRevision = RT_H2LE_U32(1);
1973 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
1974 header->u32CreatorRev = pThis->u32CreatorRev;
1975}
1976
1977/**
1978 * Initialize a generic address structure (ACPIGENADDR).
1979 */
1980static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
1981 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
1982 uint8_t u8AccessSize, uint64_t u64Address)
1983{
1984 g->u8AddressSpaceId = u8AddressSpaceId;
1985 g->u8RegisterBitWidth = u8RegisterBitWidth;
1986 g->u8RegisterBitOffset = u8RegisterBitOffset;
1987 g->u8AccessSize = u8AccessSize;
1988 g->u64Address = RT_H2LE_U64(u64Address);
1989}
1990
1991/**
1992 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
1993 */
1994DECLINLINE(void) acpiR3PhysCopy(ACPIState *pThis, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
1995{
1996 PDMDevHlpPhysWrite(pThis->pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
1997}
1998
1999/**
2000 * Plant the Differentiated System Description Table (DSDT).
2001 */
2002static void acpiR3SetupDsdt(ACPIState *pThis, RTGCPHYS32 GCPhys32, void *pvPtr, size_t cbDsdt)
2003{
2004 acpiR3PhysCopy(pThis, GCPhys32, pvPtr, cbDsdt);
2005}
2006
2007/**
2008 * Plan the Secondary System Description Table (SSDT).
2009 */
2010static void acpiR3SetupSsdt(ACPIState *pThis, RTGCPHYS32 addr,
2011 void* pPtr, size_t uSsdtLen)
2012{
2013 acpiR3PhysCopy(pThis, addr, pPtr, uSsdtLen);
2014}
2015
2016/**
2017 * Plant the Firmware ACPI Control Structure (FACS).
2018 */
2019static void acpiR3SetupFacs(ACPIState *pThis, RTGCPHYS32 addr)
2020{
2021 ACPITBLFACS facs;
2022
2023 memset(&facs, 0, sizeof(facs));
2024 memcpy(facs.au8Signature, "FACS", 4);
2025 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2026 facs.u32HWSignature = RT_H2LE_U32(0);
2027 facs.u32FWVector = RT_H2LE_U32(0);
2028 facs.u32GlobalLock = RT_H2LE_U32(0);
2029 facs.u32Flags = RT_H2LE_U32(0);
2030 facs.u64X_FWVector = RT_H2LE_U64(0);
2031 facs.u8Version = 1;
2032
2033 acpiR3PhysCopy(pThis, addr, (const uint8_t *)&facs, sizeof(facs));
2034}
2035
2036/**
2037 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2038 */
2039static void acpiR3SetupFadt(ACPIState *pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2040 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2041{
2042 ACPITBLFADT fadt;
2043
2044 /* First the ACPI version 2+ version of the structure. */
2045 memset(&fadt, 0, sizeof(fadt));
2046 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2047 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2048 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2049 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2050 fadt.u8PreferredPMProfile = 0; /* unspecified */
2051 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2052 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2053 fadt.u8AcpiEnable = ACPI_ENABLE;
2054 fadt.u8AcpiDisable = ACPI_DISABLE;
2055 fadt.u8S4BIOSReq = 0;
2056 fadt.u8PStateCnt = 0;
2057 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2058 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2059 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2060 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2061 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2062 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2063 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2064 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2065 fadt.u8PM1EVTLEN = 4;
2066 fadt.u8PM1CTLLEN = 2;
2067 fadt.u8PM2CTLLEN = 0;
2068 fadt.u8PMTMLEN = 4;
2069 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2070 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2071 fadt.u8GPE1BASE = GPE1_BASE;
2072 fadt.u8CSTCNT = 0;
2073 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2074 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2075 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2076 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2077 fadt.u8DutyOffset = 0;
2078 fadt.u8DutyWidth = 0;
2079 fadt.u8DayAlarm = 0;
2080 fadt.u8MonAlarm = 0;
2081 fadt.u8Century = 0;
2082 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2083 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2084 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2085 | FADT_FL_FIX_RTC
2086 | FADT_FL_TMR_VAL_EXT
2087 | FADT_FL_RESET_REG_SUP);
2088
2089 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2090 if (pThis->fCpuHotPlug)
2091 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2092
2093 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2094 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2095 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2096 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2097 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2098 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2099 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2100 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2101 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2102 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2103 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2104 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2105 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2106 acpiR3PhysCopy(pThis, GCPhysAcpi2, &fadt, sizeof(fadt));
2107
2108 /* Now the ACPI 1.0 version. */
2109 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2110 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2111 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2112 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2113 acpiR3PhysCopy(pThis, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2114}
2115
2116/**
2117 * Plant the root System Description Table.
2118 *
2119 * The RSDT and XSDT tables are basically identical. The only difference is 32
2120 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2121 * ACPI 2.0 and up.
2122 */
2123static int acpiR3SetupRsdt(ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2124{
2125 ACPITBLRSDT *rsdt;
2126 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2127
2128 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2129 if (!rsdt)
2130 return PDMDEV_SET_ERROR(pThis->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2131
2132 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2133 for (unsigned int i = 0; i < nb_entries; ++i)
2134 {
2135 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2136 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2137 }
2138 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2139 acpiR3PhysCopy(pThis, addr, rsdt, size);
2140 RTMemFree(rsdt);
2141 return VINF_SUCCESS;
2142}
2143
2144/**
2145 * Plant the Extended System Description Table.
2146 */
2147static int acpiR3SetupXsdt(ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2148{
2149 ACPITBLXSDT *xsdt;
2150 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2151
2152 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
2153 if (!xsdt)
2154 return VERR_NO_TMP_MEMORY;
2155
2156 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
2157
2158 if (pThis->fUseCust)
2159 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2160
2161 for (unsigned int i = 0; i < nb_entries; ++i)
2162 {
2163 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2164 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2165 }
2166 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, size);
2167 acpiR3PhysCopy(pThis, addr, xsdt, size);
2168 RTMemFree(xsdt);
2169 return VINF_SUCCESS;
2170}
2171
2172/**
2173 * Plant the Root System Description Pointer (RSDP).
2174 */
2175static void acpiR3SetupRsdp(ACPIState *pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2176{
2177 memset(rsdp, 0, sizeof(*rsdp));
2178
2179 /* ACPI 1.0 part (RSDT) */
2180 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2181 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2182 rsdp->u8Revision = ACPI_REVISION;
2183 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2184 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2185
2186 /* ACPI 2.0 part (XSDT) */
2187 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2188 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2189 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2190}
2191
2192/**
2193 * Multiple APIC Description Table.
2194 *
2195 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2196 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2197 * use regular C structure and proxy to raw memory instead.
2198 */
2199class AcpiTableMadt
2200{
2201 /**
2202 * All actual data stored in dynamically allocated memory pointed by this field.
2203 */
2204 uint8_t *m_pbData;
2205 /**
2206 * Number of CPU entries in this MADT.
2207 */
2208 uint32_t m_cCpus;
2209
2210 /**
2211 * Number of interrupt overrides.
2212 */
2213 uint32_t m_cIsos;
2214
2215public:
2216 /**
2217 * Address of ACPI header
2218 */
2219 inline ACPITBLHEADER *header_addr(void) const
2220 {
2221 return (ACPITBLHEADER *)m_pbData;
2222 }
2223
2224 /**
2225 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2226 * although address is the same for all of them.
2227 */
2228 inline uint32_t *u32LAPIC_addr(void) const
2229 {
2230 return (uint32_t *)(header_addr() + 1);
2231 }
2232
2233 /**
2234 * Address of APIC flags
2235 */
2236 inline uint32_t *u32Flags_addr(void) const
2237 {
2238 return (uint32_t *)(u32LAPIC_addr() + 1);
2239 }
2240
2241 /**
2242 * Address of ISO description
2243 */
2244 inline ACPITBLISO *ISO_addr(void) const
2245 {
2246 return (ACPITBLISO *)(u32Flags_addr() + 1);
2247 }
2248
2249 /**
2250 * Address of per-CPU LAPIC descriptions
2251 */
2252 inline ACPITBLLAPIC *LApics_addr(void) const
2253 {
2254 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2255 }
2256
2257 /**
2258 * Address of IO APIC description
2259 */
2260 inline ACPITBLIOAPIC *IOApic_addr(void) const
2261 {
2262 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2263 }
2264
2265 /**
2266 * Size of MADT.
2267 * Note that this function assumes IOApic to be the last field in structure.
2268 */
2269 inline uint32_t size(void) const
2270 {
2271 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2272 }
2273
2274 /**
2275 * Raw data of MADT.
2276 */
2277 inline const uint8_t *data(void) const
2278 {
2279 return m_pbData;
2280 }
2281
2282 /**
2283 * Size of MADT for given ACPI config, useful to compute layout.
2284 */
2285 static uint32_t sizeFor(ACPIState *pThis, uint32_t cIsos)
2286 {
2287 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2288 }
2289
2290 /*
2291 * Constructor, only works in Ring 3, doesn't look like a big deal.
2292 */
2293 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2294 {
2295 m_cCpus = cCpus;
2296 m_cIsos = cIsos;
2297 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2298 uint32_t cb = size();
2299 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2300 }
2301
2302 ~AcpiTableMadt()
2303 {
2304 RTMemFree(m_pbData);
2305 }
2306};
2307
2308
2309/**
2310 * Plant the Multiple APIC Description Table (MADT).
2311 *
2312 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
2313 *
2314 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
2315 */
2316static void acpiR3SetupMadt(ACPIState *pThis, RTGCPHYS32 addr)
2317{
2318 uint16_t cpus = pThis->cCpus;
2319 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
2320
2321 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
2322
2323 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
2324 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
2325
2326 /* LAPICs records */
2327 ACPITBLLAPIC* lapic = madt.LApics_addr();
2328 for (uint16_t i = 0; i < cpus; i++)
2329 {
2330 lapic->u8Type = 0;
2331 lapic->u8Length = sizeof(ACPITBLLAPIC);
2332 lapic->u8ProcId = i;
2333 /** Must match numbering convention in MPTABLES */
2334 lapic->u8ApicId = i;
2335 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
2336 lapic++;
2337 }
2338
2339 /* IO-APIC record */
2340 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
2341 ioapic->u8Type = 1;
2342 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
2343 /** Must match MP tables ID */
2344 ioapic->u8IOApicId = cpus;
2345 ioapic->u8Reserved = 0;
2346 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
2347 ioapic->u32GSIB = RT_H2LE_U32(0);
2348
2349 /* Interrupt Source Overrides */
2350 /* Flags:
2351 bits[3:2]:
2352 00 conforms to the bus
2353 01 edge-triggered
2354 10 reserved
2355 11 level-triggered
2356 bits[1:0]
2357 00 conforms to the bus
2358 01 active-high
2359 10 reserved
2360 11 active-low */
2361 /* If changing, also update PDMIsaSetIrq() and MPS */
2362 ACPITBLISO* isos = madt.ISO_addr();
2363 /* Timer interrupt rule IRQ0 to GSI2 */
2364 isos[0].u8Type = 2;
2365 isos[0].u8Length = sizeof(ACPITBLISO);
2366 isos[0].u8Bus = 0; /* Must be 0 */
2367 isos[0].u8Source = 0; /* IRQ0 */
2368 isos[0].u32GSI = 2; /* connected to pin 2 */
2369 isos[0].u16Flags = 0; /* conform to the bus */
2370
2371 /* ACPI interrupt rule - IRQ9 to GSI9 */
2372 isos[1].u8Type = 2;
2373 isos[1].u8Length = sizeof(ACPITBLISO);
2374 isos[1].u8Bus = 0; /* Must be 0 */
2375 isos[1].u8Source = 9; /* IRQ9 */
2376 isos[1].u32GSI = 9; /* connected to pin 9 */
2377 isos[1].u16Flags = 0xd; /* active high, level triggered */
2378 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
2379
2380 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
2381 acpiR3PhysCopy(pThis, addr, madt.data(), madt.size());
2382}
2383
2384/**
2385 * Plant the High Performance Event Timer (HPET) descriptor.
2386 */
2387static void acpiR3SetupHpet(ACPIState *pThis, RTGCPHYS32 addr)
2388{
2389 ACPITBLHPET hpet;
2390
2391 memset(&hpet, 0, sizeof(hpet));
2392
2393 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
2394 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
2395 acpiR3WriteGenericAddr(&hpet.HpetAddr,
2396 0 /* Memory address space */,
2397 64 /* Register bit width */,
2398 0 /* Bit offset */,
2399 0, /* Register access size, is it correct? */
2400 0xfed00000 /* Address */);
2401
2402 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
2403 hpet.u32Number = 0;
2404 hpet.u32MinTick = 4096;
2405 hpet.u8Attributes = 0;
2406
2407 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
2408
2409 acpiR3PhysCopy(pThis, addr, (const uint8_t *)&hpet, sizeof(hpet));
2410}
2411
2412
2413/** Custom Description Table */
2414static void acpiR3SetupCust(ACPIState *pThis, RTGCPHYS32 addr)
2415{
2416 ACPITBLCUST cust;
2417
2418 /* First the ACPI version 1 version of the structure. */
2419 memset(&cust, 0, sizeof(cust));
2420 acpiR3PrepareHeader(pThis, &cust.header, "CUST", sizeof(cust), 1);
2421
2422 memcpy(cust.header.au8OemTabId, pThis->au8OemTabId, 8);
2423 cust.header.u32OemRevision = RT_H2LE_U32(pThis->u32OemRevision);
2424 cust.header.u8Checksum = acpiR3Checksum((uint8_t *)&cust, sizeof(cust));
2425
2426 acpiR3PhysCopy(pThis, addr, pThis->pu8CustBin, pThis->cbCustBin);
2427}
2428
2429/**
2430 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
2431 * descriptor.
2432 *
2433 * @param pThis The ACPI instance.
2434 * @param GCPhysDst Where to plant it.
2435 */
2436static void acpiR3SetupMcfg(ACPIState *pThis, RTGCPHYS32 GCPhysDst)
2437{
2438 struct
2439 {
2440 ACPITBLMCFG hdr;
2441 ACPITBLMCFGENTRY entry;
2442 } tbl;
2443 uint8_t u8StartBus = 0;
2444 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
2445
2446 RT_ZERO(tbl);
2447
2448 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
2449 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
2450 tbl.entry.u8StartBus = u8StartBus;
2451 tbl.entry.u8EndBus = u8EndBus;
2452 // u16PciSegmentGroup must match _SEG in ACPI table
2453
2454 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
2455
2456 acpiR3PhysCopy(pThis, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
2457}
2458
2459/**
2460 * Used by acpiR3PlantTables and acpiConstruct.
2461 *
2462 * @returns Guest memory address.
2463 */
2464static uint32_t apicR3FindRsdpSpace(void)
2465{
2466 return 0xe0000;
2467}
2468
2469/**
2470 * Create the ACPI tables in guest memory.
2471 */
2472static int acpiR3PlantTables(ACPIState *pThis)
2473{
2474 int rc;
2475 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
2476 RTGCPHYS32 GCPhysHpet = 0;
2477 RTGCPHYS32 GCPhysApic = 0;
2478 RTGCPHYS32 GCPhysSsdt = 0;
2479 RTGCPHYS32 GCPhysMcfg = 0;
2480 RTGCPHYS32 GCPhysCust = 0;
2481 uint32_t addend = 0;
2482 RTGCPHYS32 aGCPhysRsdt[8];
2483 RTGCPHYS32 aGCPhysXsdt[8];
2484 uint32_t cAddr;
2485 uint32_t iMadt = 0;
2486 uint32_t iHpet = 0;
2487 uint32_t iSsdt = 0;
2488 uint32_t iMcfg = 0;
2489 uint32_t iCust = 0;
2490 size_t cbRsdt = sizeof(ACPITBLHEADER);
2491 size_t cbXsdt = sizeof(ACPITBLHEADER);
2492
2493 cAddr = 1; /* FADT */
2494 if (pThis->u8UseIOApic)
2495 iMadt = cAddr++; /* MADT */
2496
2497 if (pThis->fUseHpet)
2498 iHpet = cAddr++; /* HPET */
2499
2500 if (pThis->fUseMcfg)
2501 iMcfg = cAddr++; /* MCFG */
2502
2503 if (pThis->fUseCust)
2504 iCust = cAddr++; /* CUST */
2505
2506 iSsdt = cAddr++; /* SSDT */
2507
2508 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
2509 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
2510
2511 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
2512 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
2513
2514 rc = CFGMR3QueryU64(pThis->pDevIns->pCfg, "RamSize", &pThis->u64RamSize);
2515 if (RT_FAILURE(rc))
2516 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
2517 N_("Configuration error: Querying \"RamSize\" as integer failed"));
2518
2519 uint32_t cbRamHole;
2520 rc = CFGMR3QueryU32Def(pThis->pDevIns->pCfg, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
2521 if (RT_FAILURE(rc))
2522 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
2523 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
2524
2525 /*
2526 * Calculate the sizes for the high and low regions.
2527 */
2528 const uint64_t offRamHole = _4G - cbRamHole;
2529 pThis->cbRamHigh = offRamHole < pThis->u64RamSize ? pThis->u64RamSize - offRamHole : 0;
2530 uint64_t cbRamLow = offRamHole < pThis->u64RamSize ? offRamHole : pThis->u64RamSize;
2531 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
2532 {
2533 /* Note: This is also enforced by DevPcBios.cpp. */
2534 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
2535 cbRamLow = UINT32_C(0xffe00000);
2536 }
2537 pThis->cbRamLow = (uint32_t)cbRamLow;
2538
2539 GCPhysCur = 0;
2540 GCPhysRsdt = GCPhysCur;
2541
2542 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
2543 GCPhysXsdt = GCPhysCur;
2544
2545 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
2546 GCPhysFadtAcpi1 = GCPhysCur;
2547
2548 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
2549 GCPhysFadtAcpi2 = GCPhysCur;
2550
2551 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
2552 GCPhysFacs = GCPhysCur;
2553
2554 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
2555 if (pThis->u8UseIOApic)
2556 {
2557 GCPhysApic = GCPhysCur;
2558 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
2559 }
2560 if (pThis->fUseHpet)
2561 {
2562 GCPhysHpet = GCPhysCur;
2563 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
2564 }
2565 if (pThis->fUseMcfg)
2566 {
2567 GCPhysMcfg = GCPhysCur;
2568 /* Assume one entry */
2569 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
2570 }
2571 if (pThis->fUseCust)
2572 {
2573 GCPhysCust = GCPhysCur;
2574 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThis->cbCustBin, 16);
2575 }
2576
2577 void *pvSsdtCode = NULL;
2578 size_t cbSsdt = 0;
2579 rc = acpiPrepareSsdt(pThis->pDevIns, &pvSsdtCode, &cbSsdt);
2580 if (RT_FAILURE(rc))
2581 return rc;
2582
2583 GCPhysSsdt = GCPhysCur;
2584 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
2585
2586 GCPhysDsdt = GCPhysCur;
2587
2588 void *pvDsdtCode = NULL;
2589 size_t cbDsdt = 0;
2590 rc = acpiPrepareDsdt(pThis->pDevIns, &pvDsdtCode, &cbDsdt);
2591 if (RT_FAILURE(rc))
2592 return rc;
2593
2594 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
2595
2596 if (GCPhysCur > 0x10000)
2597 return PDMDEV_SET_ERROR(pThis->pDevIns, VERR_TOO_MUCH_DATA,
2598 N_("Error: ACPI tables bigger than 64KB"));
2599
2600 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
2601 addend = pThis->cbRamLow - 0x10000;
2602 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
2603 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
2604 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
2605 if (pThis->u8UseIOApic)
2606 Log((" MADT 0x%08X", GCPhysApic + addend));
2607 if (pThis->fUseHpet)
2608 Log((" HPET 0x%08X", GCPhysHpet + addend));
2609 if (pThis->fUseMcfg)
2610 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
2611 if (pThis->fUseCust)
2612 Log((" CUST 0x%08X", GCPhysCust + addend));
2613 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
2614 Log(("\n"));
2615
2616 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
2617 acpiR3SetupDsdt(pThis, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
2618 acpiCleanupDsdt(pThis->pDevIns, pvDsdtCode);
2619 acpiR3SetupFacs(pThis, GCPhysFacs + addend);
2620 acpiR3SetupFadt(pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
2621
2622 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
2623 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
2624 if (pThis->u8UseIOApic)
2625 {
2626 acpiR3SetupMadt(pThis, GCPhysApic + addend);
2627 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
2628 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
2629 }
2630 if (pThis->fUseHpet)
2631 {
2632 acpiR3SetupHpet(pThis, GCPhysHpet + addend);
2633 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
2634 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
2635 }
2636 if (pThis->fUseMcfg)
2637 {
2638 acpiR3SetupMcfg(pThis, GCPhysMcfg + addend);
2639 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
2640 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
2641 }
2642 if (pThis->fUseCust)
2643 {
2644 acpiR3SetupCust(pThis, GCPhysCust + addend);
2645 aGCPhysRsdt[iCust] = GCPhysCust + addend;
2646 aGCPhysXsdt[iCust] = GCPhysCust + addend;
2647 }
2648
2649 acpiR3SetupSsdt(pThis, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
2650 acpiCleanupSsdt(pThis->pDevIns, pvSsdtCode);
2651 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
2652 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
2653
2654 rc = acpiR3SetupRsdt(pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
2655 if (RT_FAILURE(rc))
2656 return rc;
2657 return acpiR3SetupXsdt(pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
2658}
2659
2660/**
2661 * @callback_method_impl{FNPCICONFIGREAD}
2662 */
2663static DECLCALLBACK(uint32_t) acpiR3PciConfigRead(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb)
2664{
2665 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2666 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2667
2668 Log2(("acpi: PCI config read: 0x%x (%d)\n", Address, cb));
2669 return pThis->pfnAcpiPciConfigRead(pPciDev, Address, cb);
2670}
2671
2672/**
2673 * @callback_method_impl{FNPCICONFIGWRITE}
2674 */
2675static DECLCALLBACK(void) acpiR3PciConfigWrite(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb)
2676{
2677 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2678 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2679
2680 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, Address, cb));
2681 DEVACPI_LOCK_R3(pThis);
2682
2683 if (Address == VBOX_PCI_INTERRUPT_LINE)
2684 {
2685 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
2686 u32Value = SCI_INT;
2687 }
2688
2689 pThis->pfnAcpiPciConfigWrite(pPciDev, Address, u32Value, cb);
2690
2691 /* PMREGMISC written */
2692 if (Address == 0x80)
2693 {
2694 /* Check Power Management IO Space Enable (PMIOSE) bit */
2695 if (pPciDev->config[0x80] & 0x1)
2696 {
2697 RTIOPORT NewIoPortBase = (RTIOPORT)PCIDevGetDWord(pPciDev, 0x40);
2698 NewIoPortBase &= 0xffc0;
2699
2700 int rc = acpiR3UpdatePmHandlers(pThis, NewIoPortBase);
2701 AssertRC(rc);
2702 }
2703 }
2704
2705 DEVACPI_UNLOCK(pThis);
2706}
2707
2708/**
2709 * Attach a new CPU.
2710 *
2711 * @returns VBox status code.
2712 * @param pDevIns The device instance.
2713 * @param iLUN The logical unit which is being attached.
2714 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2715 *
2716 * @remarks This code path is not used during construction.
2717 */
2718static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
2719{
2720 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2721 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
2722
2723 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
2724 ("Hot-plug flag is not set\n"),
2725 VERR_NOT_SUPPORTED);
2726 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
2727
2728 /* Check if it was already attached */
2729 int rc = VINF_SUCCESS;
2730 DEVACPI_LOCK_R3(pThis);
2731 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
2732 {
2733 PPDMIBASE IBaseTmp;
2734 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThis->IBase, &IBaseTmp, "ACPI CPU");
2735 if (RT_SUCCESS(rc))
2736 {
2737 /* Enable the CPU */
2738 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
2739
2740 /*
2741 * Lock the CPU because we don't know if the guest will use it or not.
2742 * Prevents ejection while the CPU is still used
2743 */
2744 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
2745 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
2746 pThis->u32CpuEvent = iLUN;
2747
2748 /* Notify the guest */
2749 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
2750 }
2751 }
2752 DEVACPI_UNLOCK(pThis);
2753 return rc;
2754}
2755
2756/**
2757 * Detach notification.
2758 *
2759 * @param pDevIns The device instance.
2760 * @param iLUN The logical unit which is being detached.
2761 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2762 */
2763static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
2764{
2765 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2766
2767 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
2768
2769 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
2770 ("Hot-plug flag is not set\n"));
2771
2772 /* Check if it was already detached */
2773 DEVACPI_LOCK_R3(pThis);
2774 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
2775 {
2776 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
2777 {
2778 /* Disable the CPU */
2779 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
2780 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
2781 pThis->u32CpuEvent = iLUN;
2782
2783 /* Notify the guest */
2784 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
2785 }
2786 else
2787 AssertMsgFailed(("CPU is still locked by the guest\n"));
2788 }
2789 DEVACPI_UNLOCK(pThis);
2790}
2791
2792/**
2793 * @interface_method_impl{PDMDEVREG,pfnResume}
2794 */
2795static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
2796{
2797 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2798 if (pThis->fSetWakeupOnResume)
2799 {
2800 Log(("acpiResume: setting WAK_STS\n"));
2801 pThis->fSetWakeupOnResume = false;
2802 pThis->pm1a_sts |= WAK_STS;
2803 }
2804}
2805
2806/**
2807 * @interface_method_impl{PDMDEVREG,pfnReset}
2808 */
2809static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
2810{
2811 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2812
2813 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);
2814 pThis->pm1a_en = 0;
2815 pThis->pm1a_sts = 0;
2816 pThis->pm1a_ctl = 0;
2817 pThis->u64PmTimerInitial = TMTimerGet(pThis->pPmTimerR3);
2818 acpiR3PmTimerReset(pThis, pThis->u64PmTimerInitial);
2819 pThis->uBatteryIndex = 0;
2820 pThis->uSystemInfoIndex = 0;
2821 pThis->gpe0_en = 0;
2822 pThis->gpe0_sts = 0;
2823 pThis->uSleepState = 0;
2824 TMTimerUnlock(pThis->pPmTimerR3);
2825
2826 /** @todo Should we really reset PM base? */
2827 acpiR3UpdatePmHandlers(pThis, PM_PORT_BASE);
2828
2829 acpiR3PlantTables(pThis);
2830}
2831
2832/**
2833 * @interface_method_impl{PDMDEVREG,pfnRelocate}
2834 */
2835static DECLCALLBACK(void) acpiR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2836{
2837 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2838 pThis->pPmTimerRC = TMTimerRCPtr(pThis->pPmTimerR3);
2839 NOREF(offDelta);
2840}
2841
2842/**
2843 * @interface_methid_impl{PDMDEVREG,pfnDestruct}
2844 */
2845static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
2846{
2847 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2848 if (pThis->pu8CustBin)
2849 {
2850 MMR3HeapFree(pThis->pu8CustBin);
2851 pThis->pu8CustBin = NULL;
2852 }
2853 return VINF_SUCCESS;
2854}
2855
2856/**
2857 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2858 */
2859static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2860{
2861 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2862 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2863
2864 /*
2865 * Init data and set defaults.
2866 */
2867 /** @todo move more of the code up! */
2868
2869 pThis->pDevIns = pDevIns;
2870 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
2871 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
2872 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
2873 pThis->u32CpuEventType = 0;
2874 pThis->u32CpuEvent = UINT32_C(0xffffffff);
2875
2876 /* The first CPU can't be attached/detached */
2877 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
2878 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
2879
2880 /* IBase */
2881 pThis->IBase.pfnQueryInterface = acpiR3QueryInterface;
2882 /* IACPIPort */
2883 pThis->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
2884 pThis->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
2885 pThis->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
2886 pThis->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
2887 pThis->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
2888
2889 /*
2890 * Set the default critical section to NOP (related to the PM timer).
2891 */
2892 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2893 AssertRCReturn(rc, rc);
2894
2895 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
2896 AssertRCReturn(rc, rc);
2897
2898 /*
2899 * Validate and read the configuration.
2900 */
2901 if (!CFGMR3AreValuesValid(pCfg,
2902 "RamSize\0"
2903 "RamHoleSize\0"
2904 "IOAPIC\0"
2905 "NumCPUs\0"
2906 "GCEnabled\0"
2907 "R0Enabled\0"
2908 "HpetEnabled\0"
2909 "McfgEnabled\0"
2910 "McfgBase\0"
2911 "McfgLength\0"
2912 "SmcEnabled\0"
2913 "FdcEnabled\0"
2914 "ShowRtc\0"
2915 "ShowCpu\0"
2916 "NicPciAddress\0"
2917 "AudioPciAddress\0"
2918 "IocPciAddress\0"
2919 "HostBusPciAddress\0"
2920 "EnableSuspendToDisk\0"
2921 "PowerS1Enabled\0"
2922 "PowerS4Enabled\0"
2923 "CpuHotPlug\0"
2924 "AmlFilePath\0"
2925 "Serial0IoPortBase\0"
2926 "Serial1IoPortBase\0"
2927 "Serial0Irq\0"
2928 "Serial1Irq\0"
2929 "AcpiOemId\0"
2930 "AcpiCreatorId\0"
2931 "AcpiCreatorRev\0"
2932 "CustomTable\0"
2933 "SLICTable\0"
2934 ))
2935 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2936 N_("Configuration error: Invalid config key for ACPI device"));
2937
2938 /* query whether we are supposed to present an IOAPIC */
2939 rc = CFGMR3QueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
2940 if (RT_FAILURE(rc))
2941 return PDMDEV_SET_ERROR(pDevIns, rc,
2942 N_("Configuration error: Failed to read \"IOAPIC\""));
2943
2944 rc = CFGMR3QueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
2945 if (RT_FAILURE(rc))
2946 return PDMDEV_SET_ERROR(pDevIns, rc,
2947 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
2948
2949 /* query whether we are supposed to present an FDC controller */
2950 rc = CFGMR3QueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
2951 if (RT_FAILURE(rc))
2952 return PDMDEV_SET_ERROR(pDevIns, rc,
2953 N_("Configuration error: Failed to read \"FdcEnabled\""));
2954
2955 /* query whether we are supposed to present HPET */
2956 rc = CFGMR3QueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
2957 if (RT_FAILURE(rc))
2958 return PDMDEV_SET_ERROR(pDevIns, rc,
2959 N_("Configuration error: Failed to read \"HpetEnabled\""));
2960 /* query MCFG configuration */
2961 rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
2962 if (RT_FAILURE(rc))
2963 return PDMDEV_SET_ERROR(pDevIns, rc,
2964 N_("Configuration error: Failed to read \"McfgBase\""));
2965 rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
2966 if (RT_FAILURE(rc))
2967 return PDMDEV_SET_ERROR(pDevIns, rc,
2968 N_("Configuration error: Failed to read \"McfgLength\""));
2969 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
2970
2971 /* query whether we are supposed to present custom table */
2972 pThis->fUseCust = false;
2973
2974 /* query whether we are supposed to present SMC */
2975 rc = CFGMR3QueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
2976 if (RT_FAILURE(rc))
2977 return PDMDEV_SET_ERROR(pDevIns, rc,
2978 N_("Configuration error: Failed to read \"SmcEnabled\""));
2979
2980 /* query whether we are supposed to present RTC object */
2981 rc = CFGMR3QueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
2982 if (RT_FAILURE(rc))
2983 return PDMDEV_SET_ERROR(pDevIns, rc,
2984 N_("Configuration error: Failed to read \"ShowRtc\""));
2985
2986 /* query whether we are supposed to present CPU objects */
2987 rc = CFGMR3QueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
2988 if (RT_FAILURE(rc))
2989 return PDMDEV_SET_ERROR(pDevIns, rc,
2990 N_("Configuration error: Failed to read \"ShowCpu\""));
2991
2992 /* query primary NIC PCI address */
2993 rc = CFGMR3QueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
2994 if (RT_FAILURE(rc))
2995 return PDMDEV_SET_ERROR(pDevIns, rc,
2996 N_("Configuration error: Failed to read \"NicPciAddress\""));
2997
2998 /* query primary NIC PCI address */
2999 rc = CFGMR3QueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3000 if (RT_FAILURE(rc))
3001 return PDMDEV_SET_ERROR(pDevIns, rc,
3002 N_("Configuration error: Failed to read \"AudioPciAddress\""));
3003
3004 /* query IO controller (southbridge) PCI address */
3005 rc = CFGMR3QueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3006 if (RT_FAILURE(rc))
3007 return PDMDEV_SET_ERROR(pDevIns, rc,
3008 N_("Configuration error: Failed to read \"IocPciAddress\""));
3009
3010 /* query host bus controller PCI address */
3011 rc = CFGMR3QueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3012 if (RT_FAILURE(rc))
3013 return PDMDEV_SET_ERROR(pDevIns, rc,
3014 N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3015
3016 /* query whether S1 power state should be exposed */
3017 rc = CFGMR3QueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3018 if (RT_FAILURE(rc))
3019 return PDMDEV_SET_ERROR(pDevIns, rc,
3020 N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3021
3022 /* query whether S4 power state should be exposed */
3023 rc = CFGMR3QueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3024 if (RT_FAILURE(rc))
3025 return PDMDEV_SET_ERROR(pDevIns, rc,
3026 N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3027
3028 /* query whether S1 power state should save the VM state */
3029 rc = CFGMR3QueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3030 if (RT_FAILURE(rc))
3031 return PDMDEV_SET_ERROR(pDevIns, rc,
3032 N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3033
3034 /* query whether we are allow CPU hot plugging */
3035 rc = CFGMR3QueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3036 if (RT_FAILURE(rc))
3037 return PDMDEV_SET_ERROR(pDevIns, rc,
3038 N_("Configuration error: Failed to read \"CpuHotPlug\""));
3039
3040 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
3041 if (RT_FAILURE(rc))
3042 return PDMDEV_SET_ERROR(pDevIns, rc,
3043 N_("Configuration error: Failed to read \"GCEnabled\""));
3044
3045 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
3046 if (RT_FAILURE(rc))
3047 return PDMDEV_SET_ERROR(pDevIns, rc,
3048 N_("configuration error: failed to read \"R0Enabled\""));
3049
3050 /* query serial info */
3051 rc = CFGMR3QueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3052 if (RT_FAILURE(rc))
3053 return PDMDEV_SET_ERROR(pDevIns, rc,
3054 N_("Configuration error: Failed to read \"Serial0Irq\""));
3055
3056 rc = CFGMR3QueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3057 if (RT_FAILURE(rc))
3058 return PDMDEV_SET_ERROR(pDevIns, rc,
3059 N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3060
3061 /* Serial 1 is enabled, get config data */
3062 rc = CFGMR3QueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3063 if (RT_FAILURE(rc))
3064 return PDMDEV_SET_ERROR(pDevIns, rc,
3065 N_("Configuration error: Failed to read \"Serial1Irq\""));
3066
3067 rc = CFGMR3QueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3068 if (RT_FAILURE(rc))
3069 return PDMDEV_SET_ERROR(pDevIns, rc,
3070 N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3071
3072 /* Try to attach the other CPUs */
3073 for (unsigned i = 1; i < pThis->cCpus; i++)
3074 {
3075 if (pThis->fCpuHotPlug)
3076 {
3077 PPDMIBASE IBaseTmp;
3078 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3079
3080 if (RT_SUCCESS(rc))
3081 {
3082 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3083 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3084 Log(("acpi: Attached CPU %u\n", i));
3085 }
3086 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3087 Log(("acpi: CPU %u not attached yet\n", i));
3088 else
3089 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3090 }
3091 else
3092 {
3093 /* CPU is always attached if hot-plug is not enabled. */
3094 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3095 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3096 }
3097 }
3098
3099 char *pszOemId = NULL;
3100 rc = CFGMR3QueryStringAllocDef(pThis->pDevIns->pCfg, "AcpiOemId", &pszOemId, "VBOX ");
3101 if (RT_FAILURE(rc))
3102 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3103 N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3104 size_t cbOemId = strlen(pszOemId);
3105 if (cbOemId > 6)
3106 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3107 N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3108 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3109 memcpy(pThis->au8OemId, pszOemId, cbOemId);
3110 MMR3HeapFree(pszOemId);
3111
3112 char *pszCreatorId = NULL;
3113 rc = CFGMR3QueryStringAllocDef(pThis->pDevIns->pCfg, "AcpiCreatorId", &pszCreatorId, "ASL ");
3114 if (RT_FAILURE(rc))
3115 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3116 N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3117 size_t cbCreatorId = strlen(pszCreatorId);
3118 if (cbCreatorId > 4)
3119 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3120 N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3121 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3122 memcpy(pThis->au8CreatorId, pszCreatorId, cbCreatorId);
3123 MMR3HeapFree(pszCreatorId);
3124
3125 rc = CFGMR3QueryU32Def(pThis->pDevIns->pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3126 if (RT_FAILURE(rc))
3127 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3128 N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3129 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3130
3131 /*
3132 * Get the custom table binary file name.
3133 */
3134 char *pszCustBinFile;
3135 rc = CFGMR3QueryStringAlloc(pThis->pDevIns->pCfg, "CustomTable", &pszCustBinFile);
3136 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3137 rc = CFGMR3QueryStringAlloc(pThis->pDevIns->pCfg, "SLICTable", &pszCustBinFile);
3138 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3139 {
3140 pszCustBinFile = NULL;
3141 rc = VINF_SUCCESS;
3142 }
3143 else if (RT_FAILURE(rc))
3144 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3145 N_("Configuration error: Querying \"CustomTable\" as a string failed"));
3146 else if (!*pszCustBinFile)
3147 {
3148 MMR3HeapFree(pszCustBinFile);
3149 pszCustBinFile = NULL;
3150 }
3151
3152 /*
3153 * Determine the custom table binary size, open specified ROM file in the process.
3154 */
3155 if (pszCustBinFile)
3156 {
3157 RTFILE FileCUSTBin;
3158 rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3159 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3160 if (RT_SUCCESS(rc))
3161 {
3162 rc = RTFileGetSize(FileCUSTBin, &pThis->cbCustBin);
3163 if (RT_SUCCESS(rc))
3164 {
3165 /* The following checks should be in sync the AssertReleaseMsg's below. */
3166 if ( pThis->cbCustBin > 3072
3167 || pThis->cbCustBin < sizeof(ACPITBLHEADER))
3168 rc = VERR_TOO_MUCH_DATA;
3169
3170 /*
3171 * Allocate buffer for the custom table binary data.
3172 */
3173 pThis->pu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pThis->pDevIns, pThis->cbCustBin);
3174 if (pThis->pu8CustBin)
3175 {
3176 rc = RTFileRead(FileCUSTBin, pThis->pu8CustBin, pThis->cbCustBin, NULL);
3177 if (RT_FAILURE(rc))
3178 {
3179 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", pThis->cbCustBin, rc));
3180 MMR3HeapFree(pThis->pu8CustBin);
3181 pThis->pu8CustBin = NULL;
3182 }
3183 else
3184 {
3185 pThis->fUseCust = true;
3186 memcpy(&pThis->au8OemId[0], &pThis->pu8CustBin[10], 6);
3187 memcpy(&pThis->au8OemTabId[0], &pThis->pu8CustBin[16], 8);
3188 memcpy(&pThis->u32OemRevision, &pThis->pu8CustBin[24], 4);
3189 memcpy(&pThis->au8CreatorId[0], &pThis->pu8CustBin[28], 4);
3190 memcpy(&pThis->u32CreatorRev, &pThis->pu8CustBin[32], 4);
3191 LogRel(("Reading custom ACPI table from file '%s' (%d bytes)\n", pszCustBinFile, pThis->cbCustBin));
3192 }
3193 }
3194 else
3195 rc = VERR_NO_MEMORY;
3196
3197 RTFileClose(FileCUSTBin);
3198 }
3199 }
3200 MMR3HeapFree(pszCustBinFile);
3201 if (RT_FAILURE(rc))
3202 return PDMDEV_SET_ERROR(pDevIns, rc,
3203 N_("Error reading custom ACPI table"));
3204 }
3205
3206 /* Set default port base */
3207 pThis->uPmIoPortBase = PM_PORT_BASE;
3208
3209 /*
3210 * FDC and SMC try to use the same non-shareable interrupt (6),
3211 * enable only one device.
3212 */
3213 if (pThis->fUseSmc)
3214 pThis->fUseFdc = false;
3215
3216 /*
3217 * Plant ACPI tables.
3218 */
3219 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
3220 if (!GCPhysRsdp)
3221 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
3222 N_("Can not find space for RSDP. ACPI is disabled"));
3223
3224 rc = acpiR3PlantTables(pThis);
3225 if (RT_FAILURE(rc))
3226 return rc;
3227
3228 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
3229 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
3230 if (RT_FAILURE(rc))
3231 return rc;
3232
3233 /*
3234 * Register I/O ports.
3235 */
3236 rc = acpiR3RegisterPmHandlers(pThis);
3237 if (RT_FAILURE(rc))
3238 return rc;
3239
3240#define R(addr, cnt, writer, reader, description) \
3241 do { \
3242 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, pThis, writer, reader, \
3243 NULL, NULL, description); \
3244 if (RT_FAILURE(rc)) \
3245 return rc; \
3246 } while (0)
3247 R(SMI_CMD, 1, acpiR3SmiWrite, NULL, "ACPI SMI");
3248#ifdef DEBUG_ACPI
3249 R(DEBUG_HEX, 1, acpiR3DhexWrite, NULL, "ACPI Debug hex");
3250 R(DEBUG_CHR, 1, acpiR3DchrWrite, NULL, "ACPI Debug char");
3251#endif
3252 R(BAT_INDEX, 1, acpiR3BatIndexWrite, NULL, "ACPI Battery status index");
3253 R(BAT_DATA, 1, NULL, acpiR3BatDataRead, "ACPI Battery status data");
3254 R(SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL, "ACPI system info index");
3255 R(SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead, "ACPI system info data");
3256 R(ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL, "ACPI Reset");
3257#undef R
3258
3259 /*
3260 * Create the PM timer.
3261 */
3262 PTMTIMER pTimer;
3263 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, &pThis->dev,
3264 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pTimer);
3265 AssertRCReturn(rc, rc);
3266 pThis->pPmTimerR3 = pTimer;
3267 pThis->pPmTimerR0 = TMTimerR0Ptr(pTimer);
3268 pThis->pPmTimerRC = TMTimerRCPtr(pTimer);
3269
3270 rc = TMTimerLock(pTimer, VERR_IGNORED);
3271 AssertRCReturn(rc, rc);
3272 pThis->u64PmTimerInitial = TMTimerGet(pTimer);
3273 acpiR3PmTimerReset(pThis, pThis->u64PmTimerInitial);
3274 TMTimerUnlock(pTimer);
3275
3276 /*
3277 * Set up the PCI device.
3278 */
3279 PCIDevSetVendorId(&pThis->dev, 0x8086); /* Intel */
3280 PCIDevSetDeviceId(&pThis->dev, 0x7113); /* 82371AB */
3281
3282 /* See p. 50 of PIIX4 manual */
3283 PCIDevSetCommand(&pThis->dev, 0x01);
3284 PCIDevSetStatus(&pThis->dev, 0x0280);
3285
3286 PCIDevSetRevisionId(&pThis->dev, 0x08);
3287
3288 PCIDevSetClassProg(&pThis->dev, 0x00);
3289 PCIDevSetClassSub(&pThis->dev, 0x80);
3290 PCIDevSetClassBase(&pThis->dev, 0x06);
3291
3292 PCIDevSetHeaderType(&pThis->dev, 0x80);
3293
3294 PCIDevSetBIST(&pThis->dev, 0x00);
3295
3296 PCIDevSetInterruptLine(&pThis->dev, SCI_INT);
3297 PCIDevSetInterruptPin (&pThis->dev, 0x01);
3298
3299 pThis->dev.config[0x40] = 0x01; /* PM base address, this bit marks it as IO range, not PA */
3300
3301#if 0
3302 int smb_io_base = 0xb100;
3303 dev->config[0x90] = smb_io_base | 1; /* SMBus base address */
3304 dev->config[0x90] = smb_io_base >> 8;
3305#endif
3306
3307 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
3308 if (RT_FAILURE(rc))
3309 return rc;
3310
3311 PDMDevHlpPCISetConfigCallbacks(pDevIns, &pThis->dev,
3312 acpiR3PciConfigRead, &pThis->pfnAcpiPciConfigRead,
3313 acpiR3PciConfigWrite, &pThis->pfnAcpiPciConfigWrite);
3314
3315 /*
3316 * Register the saved state.
3317 */
3318 rc = PDMDevHlpSSMRegister(pDevIns, 6, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
3319 if (RT_FAILURE(rc))
3320 return rc;
3321
3322 /*
3323 * Get the corresponding connector interface
3324 */
3325 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "ACPI Driver Port");
3326 if (RT_SUCCESS(rc))
3327 {
3328 pThis->pDrv = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIACPICONNECTOR);
3329 if (!pThis->pDrv)
3330 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
3331 N_("LUN #0 doesn't have an ACPI connector interface"));
3332 }
3333 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3334 {
3335 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
3336 pDevIns->pReg->szName, pDevIns->iInstance));
3337 rc = VINF_SUCCESS;
3338 }
3339 else
3340 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
3341
3342 return rc;
3343}
3344
3345/**
3346 * The device registration structure.
3347 */
3348const PDMDEVREG g_DeviceACPI =
3349{
3350 /* u32Version */
3351 PDM_DEVREG_VERSION,
3352 /* szName */
3353 "acpi",
3354 /* szRCMod */
3355 "VBoxDDGC.gc",
3356 /* szR0Mod */
3357 "VBoxDDR0.r0",
3358 /* pszDescription */
3359 "Advanced Configuration and Power Interface",
3360 /* fFlags */
3361 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
3362 /* fClass */
3363 PDM_DEVREG_CLASS_ACPI,
3364 /* cMaxInstances */
3365 ~0U,
3366 /* cbInstance */
3367 sizeof(ACPIState),
3368 /* pfnConstruct */
3369 acpiR3Construct,
3370 /* pfnDestruct */
3371 acpiR3Destruct,
3372 /* pfnRelocate */
3373 acpiR3Relocate,
3374 /* pfnIOCtl */
3375 NULL,
3376 /* pfnPowerOn */
3377 NULL,
3378 /* pfnReset */
3379 acpiR3Reset,
3380 /* pfnSuspend */
3381 NULL,
3382 /* pfnResume */
3383 acpiR3Resume,
3384 /* pfnAttach */
3385 acpiR3Attach,
3386 /* pfnDetach */
3387 acpiR3Detach,
3388 /* pfnQueryInterface. */
3389 NULL,
3390 /* pfnInitComplete */
3391 NULL,
3392 /* pfnPowerOff */
3393 NULL,
3394 /* pfnSoftReset */
3395 NULL,
3396 /* u32VersionEnd */
3397 PDM_DEVREG_VERSION
3398};
3399
3400#endif /* IN_RING3 */
3401#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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