VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 545

Last change on this file since 545 was 491, checked in by vboxsync, 18 years ago

64-bit alignment.
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1/** @file
2 *
3 * VBox basic PC devices:
4 * Advanced Configuration and Power Interface (ACPI) device
5 */
6
7/*
8 * Copyright (C) 2006 InnoTek Systemberatung GmbH
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License as published by the Free Software Foundation,
14 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15 * distribution. VirtualBox OSE is distributed in the hope that it will
16 * be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * If you received this file as part of a commercial VirtualBox
19 * distribution, then only the terms of your commercial VirtualBox
20 * license agreement apply instead of the previous paragraph.
21 */
22
23#define LOG_GROUP LOG_GROUP_DEV_ACPI
24
25#include <VBox/pdm.h>
26#include <VBox/log.h>
27#include <iprt/assert.h>
28#ifdef IN_RING3
29#include <iprt/alloc.h>
30#endif /* IN_RING3 */
31
32#include "Builtins.h"
33#include "vl_vbox.h"
34
35#ifdef LOG_ENABLED
36#define DEBUG_ACPI
37#endif
38
39/* the compiled DSL */
40#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
41#include <vboxaml.hex>
42#endif /* !IN_RING3 */
43
44#define IO_READ_PROTO(name) \
45 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
46 RTIOPORT Port, uint32_t *pu32, unsigned cb)
47
48#define IO_WRITE_PROTO(name) \
49 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
50 RTIOPORT Port, uint32_t u32, unsigned cb)
51
52#define DEBUG_HEX 0x3000
53#define DEBUG_CHR 0x3001
54
55#define PM_TMR_FREQ 3579545
56#define PM1a_EVT_BLK 0x00004000
57#define PM1b_EVT_BLK 0x00000000 /**< not supported */
58#define PM1a_CTL_BLK 0x00004004
59#define PM1b_CTL_BLK 0x00000000 /**< not supported */
60#define PM2_CTL_BLK 0x00000000 /**< not supported */
61#define PM_TMR_BLK 0x00004008
62#define GPE0_BLK 0x00004020
63#define GPE1_BLK 0x00000000 /**< not supported */
64#define BAT_INDEX 0x00004040
65#define BAT_DATA 0x00004044
66#define SYSI_INDEX 0x00004048
67#define SYSI_DATA 0x0000404c
68#define ACPI_RESET_BLK 0x00004050
69
70/* PM1x status register bits */
71#define TMR_STS BIT(0)
72#define RSR1_STS (BIT(1) | BIT(2) | BIT(3))
73#define BM_STS BIT(4)
74#define GBL_STS BIT(5)
75#define RSR2_STS (BIT(6) | BIT(7))
76#define PWRBTN_STS BIT(8)
77#define SLPBTN_STS BIT(9)
78#define RTC_STS BIT(10)
79#define IGN_STS BIT(11)
80#define RSR3_STS (BIT(12) | BIT(13) | BIT(14))
81#define WAK_STS BIT(15)
82#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
83
84/* PM1x enable register bits */
85#define TMR_EN BIT(0)
86#define RSR1_EN (BIT(1) | BIT(2) | BIT(3) | BIT(4))
87#define GBL_EN BIT(5)
88#define RSR2_EN (BIT(6) | BIT(7))
89#define PWRBTN_EN BIT(8)
90#define SLPBTN_EN BIT(9)
91#define RTC_EN BIT(10)
92#define RSR3_EN (BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15))
93#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
94#define IGN_EN 0
95
96/* PM1x control register bits */
97#define SCI_EN BIT(0)
98#define BM_RLD BIT(1)
99#define GBL_RLS BIT(2)
100#define RSR1_CNT (BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8))
101#define IGN_CNT BIT(9)
102#define SLP_TYPx_SHIFT 10
103#define SLP_TYPx_MASK 7
104#define SLP_EN BIT(13)
105#define RSR2_CNT (BIT(14) | BIT(15))
106#define RSR_CNT (RSR1_CNT | RSR2_CNT)
107
108#define GPE0_BATTERY_INFO_CHANGED BIT (0)
109
110enum
111{
112 BAT_STATUS_STATE = 0x00, /**< BST battery state */
113 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
114 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
115 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
116 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
117 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
118 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
119 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
120 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
121 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
122 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
123 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
124 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
125 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
126 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
127 BAT_INDEX_LAST
128};
129
130enum
131{
132 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
133 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
134 SYSTEM_INFO_INDEX_LAST = 2,
135 SYSTEM_INFO_INDEX_INVALID = 0x80,
136 SYSTEM_INFO_INDEX_VALID = 0x200
137};
138
139#define AC_OFFLINE 0
140#define AC_ONLINE 1
141
142#define BAT_TECH_PRIMARY 1
143#define BAT_TECH_SECONDARY 2
144
145#define BAT_STATUS_DISCHARGING_MASK BIT (0)
146#define BAT_STATUS_CHARGING_MASK BIT (1)
147#define BAT_STATUS_CRITICAL_MASK BIT (2)
148
149#define STA_DEVICE_PRESENT_MASK BIT (0)
150#define STA_DEVICE_ENABLED_MASK BIT (1)
151#define STA_DEVICE_SHOW_IN_UI_MASK BIT (2)
152#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK BIT (3)
153#define STA_BATTERY_PRESENT_MASK BIT (4)
154
155struct ACPIState
156{
157 PCIDevice dev;
158 uint16_t pm1a_en;
159 uint16_t pm1a_sts;
160 uint16_t pm1a_ctl;
161 uint16_t Alignment0;
162 int64_t pm_timer_initial;
163 PTMTIMERHC tsHC;
164 PTMTIMERGC tsGC;
165
166 uint32_t gpe0_en;
167 uint32_t gpe0_sts;
168
169 unsigned int uBatteryIndex;
170 uint32_t au8BatteryInfo[13];
171
172 unsigned int uSystemInfoIndex;
173 uint64_t u64RamSize;
174
175 /** Current ACPI S* state. We support S0 and S5 */
176 uint32_t uSleepState;
177 uint8_t au8RSDPPage[0x1000];
178 uint8_t u8IndexShift;
179 uint8_t u8UseIOApic;
180
181 /** ACPI port base interface. */
182 PDMIBASE IBase;
183 /** ACPI port interface. */
184 PDMIACPIPORT IACPIPort;
185 /** Pointer to the device instance. */
186 PPDMDEVINSR3 pDevIns;
187 /** Pointer to the driver base interface */
188 R3PTRTYPE(PPDMIBASE) pDrvBase;
189 /** Pointer to the driver connector interface */
190 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
191};
192
193#pragma pack(1)
194
195/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
196struct ACPIGENADDR
197{
198 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
199 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
200 uint8_t u8RegisterBitOffset; /**< bit offset of register */
201 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
202 uint64_t u64Address; /**< 64-bit address of register */
203};
204AssertCompileSize(ACPIGENADDR, 12);
205
206/** Root System Description Pointer */
207struct ACPITBLRSDP
208{
209 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
210 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
211 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
212 uint8_t u8Revision; /**< revision number, currently 2 */
213#define ACPI_REVISION 2 /**< ACPI 3.0 */
214 uint32_t u32RSDT; /**< phys addr of RSDT */
215 uint32_t u32Length; /**< bytes of this table */
216 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
217 uint8_t u8ExtChecksum; /**< checksum of entire table */
218 uint8_t u8Reserved[3]; /**< reserved */
219};
220AssertCompileSize(ACPITBLRSDP, 36);
221
222/** System Description Table Header */
223struct ACPITBLHEADER
224{
225 uint8_t au8Signature[4]; /**< table identifier */
226 uint32_t u32Length; /**< length of the table including header */
227 uint8_t u8Revision; /**< revision number */
228 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
229 uint8_t au8OemId[6]; /**< OEM-supplied string */
230 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
231 uint32_t u32OemRevision; /**< OEM-supplied revision number */
232 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
233 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
234};
235AssertCompileSize(ACPITBLHEADER, 36);
236
237/** Root System Description Table */
238struct ACPITBLRSDT
239{
240 ACPITBLHEADER header;
241 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
242};
243AssertCompileSize(ACPITBLRSDT, 40);
244
245/** Extended System Description Table */
246struct ACPITBLXSDT
247{
248 ACPITBLHEADER header;
249 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
250};
251AssertCompileSize(ACPITBLXSDT, 44);
252
253/** Fixed ACPI Description Table */
254struct ACPITBLFADT
255{
256 ACPITBLHEADER header;
257 uint32_t u32FACS; /**< phys. address of FACS */
258 uint32_t u32DSDT; /**< phys. address of DSDT */
259 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
260#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
261#define INT_MODEL_MULTIPLE_APIC 2
262 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
263 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
264#define SCI_INT 9
265 uint32_t u32SMICmd; /**< system port address of SMI command port */
266#define SMI_CMD 0x0000442e
267 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
268#define ACPI_ENABLE 0xa1
269 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
270#define ACPI_DISABLE 0xa0
271 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
272 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
273 state control responsibility */
274 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
275 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
276 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
277 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
278 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
279 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
280 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
281 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
282 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
283 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
284 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
285 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
286 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
287#define GPE0_BLK_LEN 2
288 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
289#define GPE1_BLK_LEN 0
290 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
291#define GPE1_BASE 0
292 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
293 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
294#define P_LVL2_LAT 101 /**< C2 state not supported */
295 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
296#define P_LVL3_LAT 1001 /**< C3 state not supported */
297 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
298 lines from any processors memory caches */
299#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
300 uint16_t u16FlushStride; /**< cache line width */
301#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
302 uint8_t u8DutyOffset;
303 uint8_t u8DutyWidth;
304 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
305 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
306 uint8_t u8Century; /**< RTC CMOS RAM index of century */
307 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
308#define IAPC_BOOT_ARCH_LEGACY_DEV BIT(0) /**< legacy devices present such as LPT
309 (COM too?) */
310#define IAPC_BOOT_ARCH_8042 BIT(1) /**< legacy keyboard device present */
311#define IAPC_BOOT_ARCH_NO_VGA BIT(2) /**< VGA not present */
312 uint8_t u8Must0_0; /**< must be 0 */
313 uint32_t u32Flags; /**< fixed feature flags */
314#define FADT_FL_WBINVD BIT(0) /**< emulation of WBINVD available */
315#define FADT_FL_WBINVD_FLUSH BIT(1)
316#define FADT_FL_PROC_C1 BIT(2) /**< 1=C1 supported on all processors */
317#define FADT_FL_P_LVL2_UP BIT(3) /**< 1=C2 works on SMP and UNI systems */
318#define FADT_FL_PWR_BUTTON BIT(4) /**< 1=power button handled as ctrl method dev */
319#define FADT_FL_SLP_BUTTON BIT(5) /**< 1=sleep button handled as ctrl method dev */
320#define FADT_FL_FIX_RTC BIT(6) /**< 0=RTC wake status in fixed register */
321#define FADT_FL_RTC_S4 BIT(7) /**< 1=RTC can wake system from S4 */
322#define FADT_FL_TMR_VAL_EXT BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
323#define FADT_FL_DCK_CAP BIT(9) /**< 0=system cannot support docking */
324#define FADT_FL_RESET_REG_SUP BIT(10) /**< 1=system supports system resets */
325#define FADT_FL_SEALED_CASE BIT(11) /**< 1=case is sealed */
326#define FADT_FL_HEADLESS BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
327#define FADT_FL_CPU_SW_SLP BIT(13)
328#define FADT_FL_PCI_EXT_WAK BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
329#define FADT_FL_USE_PLATFORM_CLOCK BIT(15) /**< 1=system has ACPI PM timer */
330#define FADT_FL_S4_RTC_STS_VALID BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
331#define FADT_FL_REMOVE_POWER_ON_CAPABLE BIT(17) /**< 1=platform can remote power on */
332#define FADT_FL_FORCE_APIC_CLUSTER_MODEL BIT(18)
333#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE BIT(19)
334 ACPIGENADDR ResetReg; /**< ext addr of reset register */
335 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
336#define ACPI_RESET_REG_VAL 0x10
337 uint8_t au8Must0_1[3]; /**< must be 0 */
338 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
339 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
340 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
341 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
342 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
343 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
344 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
345 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
346 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
347 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
348};
349AssertCompileSize(ACPITBLFADT, 244);
350
351/** Firmware ACPI Control Structure */
352struct ACPITBLFACS
353{
354 uint8_t au8Signature[4]; /**< 'FACS' */
355 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
356 uint32_t u32HWSignature; /**< systems HW signature at last boot */
357 uint32_t u32FWVector; /**< address of waking vector */
358 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
359 uint32_t u32Flags; /**< FACS flags */
360 uint64_t u64X_FWVector; /**< 64-bit waking vector */
361 uint8_t u8Version; /**< version of this table */
362 uint8_t au8Reserved[31]; /**< zero */
363};
364AssertCompileSize(ACPITBLFACS, 64);
365
366/** Processor Local APIC Structure */
367struct ACPITBLLAPIC
368{
369 uint8_t u8Type; /**< 0 = LAPIC */
370 uint8_t u8Length; /**< 8 */
371 uint8_t u8ProcId; /**< processor ID */
372 uint8_t u8ApicId; /**< local APIC ID */
373 uint32_t u32Flags; /**< Flags */
374#define LAPIC_ENABLED 0x1
375};
376AssertCompileSize(ACPITBLLAPIC, 8);
377
378/** I/O APIC Structure */
379struct ACPITBLIOAPIC
380{
381 uint8_t u8Type; /**< 1 == I/O APIC */
382 uint8_t u8Length; /**< 12 */
383 uint8_t u8IOApicId; /**< I/O APIC ID */
384 uint8_t u8Reserved; /**< 0 */
385 uint32_t u32Address; /**< phys address to access I/O APIC */
386 uint32_t u32GSIB; /**< global system interrupt number to start */
387};
388AssertCompileSize(ACPITBLIOAPIC, 12);
389
390/** Multiple APIC Description Table */
391struct ACPITBLMADT
392{
393 ACPITBLHEADER header;
394 uint32_t u32LAPIC; /**< local APIC address */
395 uint32_t u32Flags; /**< Flags */
396#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
397 ACPITBLLAPIC LApic;
398 ACPITBLIOAPIC IOApic;
399};
400AssertCompileSize(ACPITBLMADT, 64);
401
402#pragma pack()
403
404
405#ifndef VBOX_DEVICE_STRUCT_TESTCASE
406__BEGIN_DECLS
407IO_READ_PROTO (acpiPMTmrRead);
408#ifdef IN_RING3
409IO_READ_PROTO (acpiPm1aEnRead);
410IO_WRITE_PROTO (acpiPM1aEnWrite);
411IO_READ_PROTO (acpiPm1aStsRead);
412IO_WRITE_PROTO (acpiPM1aStsWrite);
413IO_READ_PROTO (acpiPm1aCtlRead);
414IO_WRITE_PROTO (acpiPM1aCtlWrite);
415IO_WRITE_PROTO (acpiSmiWrite);
416IO_WRITE_PROTO (acpiBatIndexWrite);
417IO_READ_PROTO (acpiBatDataRead);
418IO_READ_PROTO (acpiSysInfoDataRead);
419IO_WRITE_PROTO (acpiSysInfoDataWrite);
420IO_READ_PROTO (acpiGpe0EnRead);
421IO_WRITE_PROTO (acpiGpe0EnWrite);
422IO_READ_PROTO (acpiGpe0StsRead);
423IO_WRITE_PROTO (acpiGpe0StsWrite);
424IO_WRITE_PROTO (acpiResetWrite);
425# ifdef DEBUG_ACPI
426IO_WRITE_PROTO (acpiDhexWrite);
427IO_WRITE_PROTO (acpiDchrWrite);
428# endif
429#endif
430__END_DECLS
431
432#ifdef IN_RING3
433
434/* Simple acpiChecksum: all the bytes must add up to 0. */
435static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
436{
437 uint8_t sum = 0;
438 for (size_t i = 0; i < len; ++i)
439 sum += data[i];
440 return -sum;
441}
442
443static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
444 uint32_t u32Length, uint8_t u8Revision)
445{
446 memcpy(header->au8Signature, au8Signature, 4);
447 header->u32Length = cpu_to_le32(u32Length);
448 header->u8Revision = u8Revision;
449 memcpy(header->au8OemId, "VBOX ", 6);
450 memcpy(header->au8OemTabId, "VBOX", 4);
451 memcpy(header->au8OemTabId+4, au8Signature, 4);
452 header->u32OemRevision = cpu_to_le32(1);
453 memcpy(header->au8CreatorId, "ASL ", 4);
454 header->u32CreatorRev = cpu_to_le32(0x61);
455}
456
457static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
458 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
459 uint8_t u8AccessSize, uint64_t u64Address)
460{
461 g->u8AddressSpaceId = u8AddressSpaceId;
462 g->u8RegisterBitWidth = u8RegisterBitWidth;
463 g->u8RegisterBitOffset = u8RegisterBitOffset;
464 g->u8AccessSize = u8AccessSize;
465 g->u64Address = cpu_to_le64(u64Address);
466}
467
468static void acpiPhyscpy (ACPIState *s, RTGCPHYS dst, const void * const src, size_t size)
469{
470 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
471}
472
473/* Differentiated System Description Table (DSDT) */
474static void acpiSetupDSDT (ACPIState *s, RTGCPHYS addr)
475{
476 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
477}
478
479/* Firmware ACPI Control Structure (FACS) */
480static void acpiSetupFACS (ACPIState *s, RTGCPHYS addr)
481{
482 ACPITBLFACS facs;
483
484 memset (&facs, 0, sizeof(facs));
485 memcpy (facs.au8Signature, "FACS", 4);
486 facs.u32Length = cpu_to_le32(sizeof(ACPITBLFACS));
487 facs.u32HWSignature = cpu_to_le32(0);
488 facs.u32FWVector = cpu_to_le32(0);
489 facs.u32GlobalLock = cpu_to_le32(0);
490 facs.u32Flags = cpu_to_le32(0);
491 facs.u64X_FWVector = cpu_to_le64(0);
492 facs.u8Version = 1;
493
494 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
495}
496
497/* Fixed ACPI Description Table (FADT aka FACP) */
498static void acpiSetupFADT (ACPIState *s, RTGCPHYS addr, uint32_t facs_addr, uint32_t dsdt_addr)
499{
500 ACPITBLFADT fadt;
501
502 memset (&fadt, 0, sizeof(fadt));
503 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
504 fadt.u32FACS = cpu_to_le32(facs_addr);
505 fadt.u32DSDT = cpu_to_le32(dsdt_addr);
506 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
507 fadt.u8PreferredPMProfile = 0; /* unspecified */
508 fadt.u16SCIInt = cpu_to_le16(SCI_INT);
509 fadt.u32SMICmd = cpu_to_le32(SMI_CMD);
510 fadt.u8AcpiEnable = ACPI_ENABLE;
511 fadt.u8AcpiDisable = ACPI_DISABLE;
512 fadt.u8S4BIOSReq = 0;
513 fadt.u8PStateCnt = 0;
514 fadt.u32PM1aEVTBLK = cpu_to_le32(PM1a_EVT_BLK);
515 fadt.u32PM1bEVTBLK = cpu_to_le32(PM1b_EVT_BLK);
516 fadt.u32PM1aCTLBLK = cpu_to_le32(PM1a_CTL_BLK);
517 fadt.u32PM1bCTLBLK = cpu_to_le32(PM1b_CTL_BLK);
518 fadt.u32PM2CTLBLK = cpu_to_le32(PM2_CTL_BLK);
519 fadt.u32PMTMRBLK = cpu_to_le32(PM_TMR_BLK);
520 fadt.u32GPE0BLK = cpu_to_le32(GPE0_BLK);
521 fadt.u32GPE1BLK = cpu_to_le32(GPE1_BLK);
522 fadt.u8PM1EVTLEN = 4;
523 fadt.u8PM1CTLLEN = 2;
524 fadt.u8PM2CTLLEN = 0;
525 fadt.u8PMTMLEN = 4;
526 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
527 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
528 fadt.u8GPE1BASE = GPE1_BASE;
529 fadt.u8CSTCNT = 0;
530 fadt.u16PLVL2LAT = cpu_to_le16(P_LVL2_LAT);
531 fadt.u16PLVL3LAT = cpu_to_le16(P_LVL3_LAT);
532 fadt.u16FlushSize = cpu_to_le16(FLUSH_SIZE);
533 fadt.u16FlushStride = cpu_to_le16(FLUSH_STRIDE);
534 fadt.u8DutyOffset = 0;
535 fadt.u8DutyWidth = 0;
536 fadt.u8DayAlarm = 0;
537 fadt.u8MonAlarm = 0;
538 fadt.u8Century = 0;
539 fadt.u16IAPCBOOTARCH = cpu_to_le16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
540 /** @note WBINVD is required for ACPI versions newer than 1.0 */
541 fadt.u32Flags = cpu_to_le32( FADT_FL_WBINVD | FADT_FL_SLP_BUTTON
542 | FADT_FL_FIX_RTC | FADT_FL_TMR_VAL_EXT);
543 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
544 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
545 fadt.u64XFACS = cpu_to_le64((uint64_t)facs_addr);
546 fadt.u64XDSDT = cpu_to_le64((uint64_t)dsdt_addr);
547 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
548 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
549 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
550 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
551 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
552 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
553 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
554 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
555 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
556 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
557}
558
559/*
560 * Root System Description Table.
561 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
562 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
563 */
564static int acpiSetupRSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
565{
566 ACPITBLRSDT *rsdt;
567 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
568
569 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
570 if (!rsdt)
571 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
572
573 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
574 for (unsigned int i = 0; i < nb_entries; ++i)
575 {
576 rsdt->u32Entry[i] = cpu_to_le32(addrs[i]);
577 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
578 }
579 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
580 acpiPhyscpy (s, addr, rsdt, size);
581 RTMemFree (rsdt);
582 return VINF_SUCCESS;
583}
584
585/* Extended System Description Table. */
586static int acpiSetupXSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
587{
588 ACPITBLXSDT *xsdt;
589 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
590
591 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
592 if (!xsdt)
593 return VERR_NO_TMP_MEMORY;
594
595 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
596 for (unsigned int i = 0; i < nb_entries; ++i)
597 {
598 xsdt->u64Entry[i] = cpu_to_le64((uint64_t)addrs[i]);
599 Log(("Setup XSDT: [%d] = %VX64\n", i, xsdt->u64Entry[i]));
600 }
601 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
602 acpiPhyscpy (s, addr, xsdt, size);
603 RTMemFree (xsdt);
604 return VINF_SUCCESS;
605}
606
607/* Root System Description Pointer (RSDP) */
608static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
609{
610 memset(rsdp, 0, sizeof(*rsdp));
611
612 /* ACPI 1.0 part (RSDT */
613 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
614 memcpy(rsdp->au8OemId, "VBox ", 6);
615 rsdp->u8Revision = ACPI_REVISION;
616 rsdp->u32RSDT = cpu_to_le32(rsdt_addr);
617 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
618
619 /* ACPI 2.0 part (XSDT) */
620 rsdp->u32Length = cpu_to_le32(sizeof(ACPITBLRSDP));
621 rsdp->u64XSDT = cpu_to_le64(xsdt_addr);
622 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
623}
624
625/* Multiple APIC Description Table. */
626/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
627/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
628static void acpiSetupMADT (ACPIState *s, RTGCPHYS addr)
629{
630 ACPITBLMADT madt;
631
632 /* Don't call this function if u8UseIOApic==false! */
633 Assert(s->u8UseIOApic);
634
635 memset(&madt, 0, sizeof(madt));
636 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
637
638 madt.u32LAPIC = cpu_to_le32(0xfee00000);
639 madt.u32Flags = cpu_to_le32(PCAT_COMPAT);
640
641 madt.LApic.u8Type = 0;
642 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
643 madt.LApic.u8ProcId = 0;
644 madt.LApic.u8ApicId = 0;
645 madt.LApic.u32Flags = cpu_to_le32(LAPIC_ENABLED);
646
647 madt.IOApic.u8Type = 1;
648 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
649 madt.IOApic.u8IOApicId = 0;
650 madt.IOApic.u8Reserved = 0;
651 madt.IOApic.u32Address = cpu_to_le32(0xfec00000);
652 madt.IOApic.u32GSIB = cpu_to_le32(0);
653
654 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
655 acpiPhyscpy (s, addr, &madt, sizeof(madt));
656}
657
658/* SCI IRQ */
659DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
660{
661 if (s->pm1a_ctl & SCI_EN)
662 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
663}
664
665DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
666{
667 return en & ~(RSR_EN | IGN_EN);
668}
669
670DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
671{
672 return sts & ~(RSR_STS | IGN_STS);
673}
674
675DECLINLINE(int) pm1a_level (ACPIState *s)
676{
677 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
678}
679
680DECLINLINE(int) gpe0_level (ACPIState *s)
681{
682 return (s->gpe0_en & s->gpe0_sts) != 0;
683}
684
685static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
686{
687 int old_level, new_level;
688
689 if (gpe0_level (s))
690 return;
691
692 old_level = pm1a_level (s);
693 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
694
695 s->pm1a_en = en;
696 s->pm1a_sts = sts;
697
698 if (new_level != old_level)
699 acpiSetIrq (s, new_level);
700}
701
702static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
703{
704 int old_level, new_level;
705
706 if (pm1a_level (s))
707 return;
708
709 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
710 new_level = (en & sts) != 0;
711
712 s->gpe0_en = en;
713 s->gpe0_sts = sts;
714
715 if (new_level != old_level)
716 acpiSetIrq (s, new_level);
717}
718
719static int acpiPowerDown (ACPIState *s)
720{
721 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
722 if (VBOX_FAILURE (rc))
723 AssertMsgFailed (("Could not power down the VM. rc = %Vrc\n", rc));
724 return rc;
725}
726
727/** Converts a ACPI port interface pointer to an ACPI state pointer. */
728#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
729
730/**
731 * Send an ACPI power off event.
732 *
733 * @returns VBox status code
734 * @param pInterface Pointer to the interface structure containing the called function pointer.
735 */
736static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
737{
738 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
739 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
740 return VINF_SUCCESS;
741}
742
743/* PM1a_EVT_BLK enable */
744static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
745{
746 uint16_t val = s->pm1a_en;
747 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
748 return val;
749}
750
751static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
752{
753 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
754 val &= ~(RSR_EN | IGN_EN);
755 update_pm1a (s, s->pm1a_sts, val);
756}
757
758/* PM1a_EVT_BLK status */
759static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
760{
761 uint16_t val = s->pm1a_sts;
762 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
763 return val;
764}
765
766static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
767{
768 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
769 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
770 update_pm1a (s, val, s->pm1a_en);
771}
772
773/* PM1a_CTL_BLK */
774static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
775{
776 uint16_t val = s->pm1a_ctl;
777 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
778 return val;
779}
780
781static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
782{
783 uint32_t uSleepState;
784
785 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
786 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
787
788 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
789 if (uSleepState != s->uSleepState)
790 {
791 s->uSleepState = uSleepState;
792 switch (uSleepState)
793 {
794 case 0x00: /* S0 */
795 break;
796 case 0x05: /* S5 */
797 LogRel (("Entering S5 (power down)\n"));
798 return acpiPowerDown (s);
799 default:
800 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
801 break;
802 }
803 }
804 return VINF_SUCCESS;
805}
806
807/* GPE0_BLK */
808static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
809{
810 uint8_t val = s->gpe0_en;
811 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
812 return val;
813}
814
815static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
816{
817 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
818 update_gpe0 (s, s->gpe0_sts, val);
819}
820
821static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
822{
823 uint8_t val = s->gpe0_sts;
824 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
825 return val;
826}
827
828static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
829{
830 val = s->gpe0_sts & ~val;
831 update_gpe0 (s, val, s->gpe0_en);
832 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
833}
834
835static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
836{
837 int rc = VINF_SUCCESS;
838
839 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
840 if (val == ACPI_RESET_REG_VAL)
841 {
842# ifndef IN_RING3
843 rc = VINF_IOM_HC_IOPORT_WRITE;
844# else /* IN_RING3 */
845 rc = PDMDevHlpVMReset(s->pDevIns);
846# endif /* !IN_RING3 */
847 }
848 return rc;
849}
850
851/* SMI */
852static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
853{
854 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
855 if (val == ACPI_ENABLE)
856 s->pm1a_ctl |= SCI_EN;
857 else if (val == ACPI_DISABLE)
858 s->pm1a_ctl &= ~SCI_EN;
859 else
860 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
861}
862
863static uint32_t find_rsdp_space (void)
864{
865 return 0xe0000;
866}
867
868static void acpiPMTimerReset (ACPIState *s)
869{
870 uint64_t interval, freq;
871
872 freq = TMTimerGetFreq (s->CTXSUFF(ts));
873 interval = muldiv64 (0xffffffff, freq, PM_TMR_FREQ);
874 Log (("interval = %RU64\n", interval));
875 TMTimerSet (s->CTXSUFF(ts), TMTimerGet (s->CTXSUFF(ts)) + interval);
876}
877
878static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
879{
880 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
881
882 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
883 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
884 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
885
886 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
887 acpiPMTimerReset (s);
888}
889
890/**
891 * _BST method.
892 */
893static void acpiFetchBatteryStatus (ACPIState *s)
894{
895 uint32_t *p = s->au8BatteryInfo;
896 bool fPresent; /* battery present? */
897 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
898 PDMACPIBATSTATE hostBatteryState; /* bitfield */
899 uint32_t hostPresentRate; /* 0..1000 */
900 int rc;
901
902 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
903 &hostBatteryState, &hostPresentRate);
904 AssertRC (rc);
905
906 /* default values */
907 p[BAT_STATUS_STATE] = hostBatteryState;
908 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
909 : hostPresentRate * 50; /* mW */
910 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
911 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
912
913 /* did we get a valid battery state? */
914 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
915 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
916 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
917 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
918}
919
920/**
921 * _BIF method.
922 */
923static void acpiFetchBatteryInfo (ACPIState *s)
924{
925 uint32_t *p = s->au8BatteryInfo;
926
927 p[BAT_INFO_UNITS] = 0; /* mWh */
928 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
929 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
930 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
931 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
932 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
933 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
934 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
935 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
936}
937
938/**
939 * _STA method.
940 */
941static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
942{
943 bool fPresent; /* battery present? */
944 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
945 PDMACPIBATSTATE hostBatteryState; /* bitfield */
946 uint32_t hostPresentRate; /* 0..1000 */
947 int rc;
948
949 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
950 &hostBatteryState, &hostPresentRate);
951 AssertRC (rc);
952
953 return fPresent
954 ? STA_DEVICE_PRESENT_MASK /* present */
955 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
956 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
957 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
958 | STA_BATTERY_PRESENT_MASK /* battery is present */
959 : 0; /* device not present */
960}
961
962static uint32_t acpiGetPowerSource (ACPIState *s)
963{
964 PDMACPIPOWERSOURCE ps;
965
966 /* query the current power source from the host driver */
967 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
968 AssertRC (rc);
969 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
970}
971
972IO_WRITE_PROTO (acpiBatIndexWrite)
973{
974 ACPIState *s = (ACPIState *)pvUser;
975
976 switch (cb)
977 {
978 case 4:
979 u32 >>= s->u8IndexShift;
980 Assert (u32 < BAT_INDEX_LAST);
981 s->uBatteryIndex = u32;
982 break;
983 default:
984 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
985 break;
986 }
987 return VINF_SUCCESS;
988}
989
990IO_READ_PROTO (acpiBatDataRead)
991{
992 ACPIState *s = (ACPIState *)pvUser;
993
994 switch (cb)
995 {
996 case 4:
997 switch (s->uBatteryIndex)
998 {
999 case BAT_STATUS_STATE:
1000 acpiFetchBatteryStatus(s);
1001 case BAT_STATUS_PRESENT_RATE:
1002 case BAT_STATUS_REMAINING_CAPACITY:
1003 case BAT_STATUS_PRESENT_VOLTAGE:
1004 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1005 break;
1006
1007 case BAT_INFO_UNITS:
1008 acpiFetchBatteryInfo(s);
1009 case BAT_INFO_DESIGN_CAPACITY:
1010 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1011 case BAT_INFO_TECHNOLOGY:
1012 case BAT_INFO_DESIGN_VOLTAGE:
1013 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1014 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1015 case BAT_INFO_CAPACITY_GRANULARITY_1:
1016 case BAT_INFO_CAPACITY_GRANULARITY_2:
1017 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1018 break;
1019
1020 case BAT_DEVICE_STATUS:
1021 *pu32 = acpiGetBatteryDeviceStatus(s);
1022 break;
1023
1024 case BAT_POWER_SOURCE:
1025 *pu32 = acpiGetPowerSource(s);
1026 break;
1027
1028 default:
1029 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1030 break;
1031 }
1032 break;
1033 default:
1034 return VERR_IOM_IOPORT_UNUSED;
1035 }
1036// LogRel(("Query %04x => %08x\n", s->uBatteryIndex, *pu32));
1037 return VINF_SUCCESS;
1038}
1039
1040IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1041{
1042 ACPIState *s = (ACPIState *)pvUser;
1043
1044 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1045 switch (cb) {
1046 case 4:
1047 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1048 s->uSystemInfoIndex = u32;
1049 else
1050 {
1051 u32 >>= s->u8IndexShift;
1052 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1053 s->uSystemInfoIndex = u32;
1054 }
1055 break;
1056
1057 default:
1058 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1059 break;
1060 }
1061 return VINF_SUCCESS;
1062}
1063
1064IO_READ_PROTO (acpiSysInfoDataRead)
1065{
1066 ACPIState *s = (ACPIState *)pvUser;
1067
1068 switch (cb)
1069 {
1070 case 4:
1071 switch (s->uSystemInfoIndex)
1072 {
1073 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1074 *pu32 = s->u64RamSize;
1075 break;
1076
1077 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1078 *pu32 = s->u8UseIOApic;
1079 break;
1080
1081 default:
1082 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1083 break;
1084 }
1085 break;
1086
1087 default:
1088 return VERR_IOM_IOPORT_UNUSED;
1089 }
1090
1091 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1092 return VINF_SUCCESS;
1093}
1094
1095IO_WRITE_PROTO (acpiSysInfoDataWrite)
1096{
1097 ACPIState *s = (ACPIState *)pvUser;
1098
1099 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1100
1101 if (cb == 4 && u32 == 0xbadc0de)
1102 {
1103 switch (s->uSystemInfoIndex)
1104 {
1105 case SYSTEM_INFO_INDEX_INVALID:
1106 s->u8IndexShift = 0;
1107 break;
1108
1109 case SYSTEM_INFO_INDEX_VALID:
1110 s->u8IndexShift = 2;
1111 break;
1112
1113 default:
1114 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1115 Port, cb, u32, s->uSystemInfoIndex));
1116 break;
1117 }
1118 }
1119 else
1120 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1121 return VINF_SUCCESS;
1122}
1123
1124/* IO Helpers */
1125IO_READ_PROTO (acpiPm1aEnRead)
1126{
1127 switch (cb)
1128 {
1129 case 2:
1130 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1131 break;
1132 default:
1133 return VERR_IOM_IOPORT_UNUSED;
1134 }
1135 return VINF_SUCCESS;
1136}
1137
1138IO_READ_PROTO (acpiPm1aStsRead)
1139{
1140 switch (cb)
1141 {
1142 case 2:
1143 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1144 break;
1145 default:
1146 return VERR_IOM_IOPORT_UNUSED;
1147 }
1148 return VINF_SUCCESS;
1149}
1150
1151IO_READ_PROTO (acpiPm1aCtlRead)
1152{
1153 switch (cb)
1154 {
1155 case 2:
1156 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1157 break;
1158 default:
1159 return VERR_IOM_IOPORT_UNUSED;
1160 }
1161 return VINF_SUCCESS;
1162}
1163
1164IO_WRITE_PROTO (acpiPM1aEnWrite)
1165{
1166 switch (cb)
1167 {
1168 case 2:
1169 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1170 break;
1171 default:
1172 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1173 break;
1174 }
1175 return VINF_SUCCESS;
1176}
1177
1178IO_WRITE_PROTO (acpiPM1aStsWrite)
1179{
1180 switch (cb)
1181 {
1182 case 2:
1183 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1184 break;
1185 default:
1186 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1187 break;
1188 }
1189 return VINF_SUCCESS;
1190}
1191
1192IO_WRITE_PROTO (acpiPM1aCtlWrite)
1193{
1194 switch (cb)
1195 {
1196 case 2:
1197 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1198 default:
1199 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1200 break;
1201 }
1202 return VINF_SUCCESS;
1203}
1204
1205#endif /* IN_RING3 */
1206
1207/**
1208 * PMTMR readable from host/guest.
1209 */
1210IO_READ_PROTO (acpiPMTmrRead)
1211{
1212 if (cb == 4)
1213 {
1214 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1215 int64_t now = TMTimerGet (s->CTXSUFF(ts));
1216 int64_t elapsed = now - s->pm_timer_initial;
1217
1218 *pu32 = muldiv64 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTXSUFF(ts)));
1219 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1220 return VINF_SUCCESS;
1221 }
1222 return VERR_IOM_IOPORT_UNUSED;
1223}
1224
1225#ifdef IN_RING3
1226
1227IO_READ_PROTO (acpiGpe0StsRead)
1228{
1229 switch (cb)
1230 {
1231 case 1:
1232 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1233 break;
1234 default:
1235 return VERR_IOM_IOPORT_UNUSED;
1236 }
1237 return VINF_SUCCESS;
1238}
1239
1240IO_READ_PROTO (acpiGpe0EnRead)
1241{
1242 switch (cb)
1243 {
1244 case 1:
1245 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1246 break;
1247 default:
1248 return VERR_IOM_IOPORT_UNUSED;
1249 }
1250 return VINF_SUCCESS;
1251}
1252
1253IO_WRITE_PROTO (acpiGpe0StsWrite)
1254{
1255 switch (cb)
1256 {
1257 case 1:
1258 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1259 break;
1260 default:
1261 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1262 break;
1263 }
1264 return VINF_SUCCESS;
1265}
1266
1267IO_WRITE_PROTO (acpiGpe0EnWrite)
1268{
1269 switch (cb)
1270 {
1271 case 1:
1272 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1273 break;
1274 default:
1275 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1276 break;
1277 }
1278 return VINF_SUCCESS;
1279}
1280
1281IO_WRITE_PROTO (acpiSmiWrite)
1282{
1283 switch (cb)
1284 {
1285 case 1:
1286 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1287 break;
1288 default:
1289 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1290 break;
1291 }
1292 return VINF_SUCCESS;
1293}
1294
1295IO_WRITE_PROTO (acpiResetWrite)
1296{
1297 switch (cb)
1298 {
1299 case 1:
1300 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1301 default:
1302 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1303 break;
1304 }
1305 return VINF_SUCCESS;
1306}
1307
1308#ifdef DEBUG_ACPI
1309
1310IO_WRITE_PROTO (acpiDhexWrite)
1311{
1312 switch (cb)
1313 {
1314 case 1:
1315 Log (("%#x\n", u32 & 0xff));
1316 break;
1317 case 2:
1318 Log (("%#6x\n", u32 & 0xffff));
1319 case 4:
1320 Log (("%#10x\n", u32));
1321 break;
1322 default:
1323 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1324 break;
1325 }
1326 return VINF_SUCCESS;
1327}
1328
1329IO_WRITE_PROTO (acpiDchrWrite)
1330{
1331 switch (cb)
1332 {
1333 case 1:
1334 Log (("%c", u32 & 0xff));
1335 break;
1336 default:
1337 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1338 break;
1339 }
1340 return VINF_SUCCESS;
1341}
1342
1343#endif /* DEBUG_ACPI */
1344
1345
1346/**
1347 * Saved state structure description.
1348 */
1349static const SSMFIELD g_AcpiSavedStateFields[] =
1350{
1351 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1352 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1353 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1354 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1355 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1356 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1357 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1358 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1359 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1360 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1361 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1362 SSMFIELD_ENTRY (ACPIState, uSleepState),
1363 SSMFIELD_ENTRY_TERM ()
1364};
1365
1366static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1367{
1368 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1369 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1370}
1371
1372static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1373 uint32_t u32Version)
1374{
1375 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1376 int rc;
1377
1378 if (u32Version != 4)
1379 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1380
1381 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1382 if (VBOX_SUCCESS (rc))
1383 {
1384 acpiFetchBatteryStatus (s);
1385 acpiFetchBatteryInfo (s);
1386 acpiPMTimerReset (s);
1387 }
1388 return rc;
1389}
1390
1391/**
1392 * Queries an interface to the driver.
1393 *
1394 * @returns Pointer to interface.
1395 * @returns NULL if the interface was not supported by the driver.
1396 * @param pInterface Pointer to this interface structure.
1397 * @param enmInterface The requested interface identification.
1398 * @thread Any thread.
1399 */
1400static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1401{
1402 ACPIState *pData = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1403 switch (enmInterface)
1404 {
1405 case PDMINTERFACE_BASE:
1406 return &pData->IBase;
1407 case PDMINTERFACE_ACPI_PORT:
1408 return &pData->IACPIPort;
1409 default:
1410 return NULL;
1411 }
1412}
1413
1414/**
1415 * Create the ACPI tables.
1416 */
1417static int acpiPlantTables (ACPIState *s)
1418{
1419 int rc;
1420 uint32_t rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1421 uint32_t addend = 0;
1422 uint32_t rsdt_addrs[4];
1423 uint32_t cAddr;
1424 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1425 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1426
1427 cAddr = 1; /* FADT */
1428 if (s->u8UseIOApic)
1429 cAddr++; /* MADT */
1430
1431 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1432 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1433
1434 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1435 if (VBOX_FAILURE (rc))
1436 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1437 N_("Configuration error: Querying "
1438 "\"RamSize\" as integer failed"));
1439
1440 if (s->u64RamSize > (0xffffffff - 0x10000))
1441 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1442 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1443 "value is 4095MB"));
1444
1445 rsdt_addr = 0;
1446 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1447 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1448 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1449 if (s->u8UseIOApic)
1450 {
1451 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1452 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1453 }
1454 else
1455 {
1456 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1457 }
1458
1459 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1460 if (last_addr > 0x10000)
1461 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1462 N_("Error: ACPI tables > 64KB!"));
1463
1464 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1465 addend = (uint32_t) s->u64RamSize - 0x10000;
1466 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1467 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1468 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1469 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1470 acpiSetupDSDT (s, dsdt_addr + addend);
1471 acpiSetupFACS (s, facs_addr + addend);
1472 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1473
1474 rsdt_addrs[0] = fadt_addr + addend;
1475 if (s->u8UseIOApic)
1476 {
1477 acpiSetupMADT (s, apic_addr + addend);
1478 rsdt_addrs[1] = apic_addr + addend;
1479 }
1480
1481 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1482 if (VBOX_FAILURE(rc))
1483 return rc;
1484 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1485}
1486
1487/**
1488 * Construct a device instance for a VM.
1489 *
1490 * @returns VBox status.
1491 * @param pDevIns The device instance data.
1492 * If the registration structure is needed, pDevIns->pDevReg points to it.
1493 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1494 * The device number is also found in pDevIns->iInstance, but since it's
1495 * likely to be freqently used PDM passes it as parameter.
1496 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1497 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1498 * iInstance it's expected to be used a bit in this function.
1499 */
1500static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1501{
1502 int rc;
1503 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1504 uint32_t rsdp_addr;
1505 PCIDevice *dev;
1506 bool fGCEnabled;
1507 bool fR0Enabled;
1508
1509 /* Validate and read the configuration. */
1510 if (!CFGMR3AreValuesValid (pCfgHandle, "RamSize\0IOAPIC\0GCEnabled\0R0Enabled\0"))
1511 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1512 N_("Configuration error: Invalid config key for ACPI device"));
1513
1514 s->pDevIns = pDevIns;
1515
1516 /* query whether we are supposed to present an IOAPIC */
1517 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1518 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1519 s->u8UseIOApic = 1;
1520 else if (VBOX_FAILURE (rc))
1521 return PDMDEV_SET_ERROR(pDevIns, rc,
1522 N_("Configuration error: Failed to read \"IOAPIC\"."));
1523
1524 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1525 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1526 fGCEnabled = true;
1527 else if (VBOX_FAILURE (rc))
1528 return PDMDEV_SET_ERROR(pDevIns, rc,
1529 N_("Configuration error: Failed to read \"GCEnabled\"."));
1530
1531 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1532 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1533 fR0Enabled = true;
1534 else if (VBOX_FAILURE(rc))
1535 return PDMDEV_SET_ERROR(pDevIns, rc,
1536 N_("configuration error: failed to read R0Enabled as boolean."));
1537
1538 /* */
1539 rsdp_addr = find_rsdp_space ();
1540 if (!rsdp_addr)
1541 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1542 N_("Can not find space for RSDP. ACPI is disabled."));
1543
1544 rc = acpiPlantTables (s);
1545 if (VBOX_FAILURE (rc))
1546 return rc;
1547
1548 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, "ACPI RSDP");
1549 if (VBOX_FAILURE (rc))
1550 return rc;
1551
1552#define R(addr, cnt, writer, reader, description) \
1553 do { \
1554 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1555 NULL, NULL, description); \
1556 if (VBOX_FAILURE (rc)) \
1557 return rc; \
1558 } while (0)
1559#define L (GPE0_BLK_LEN / 2)
1560
1561 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1562 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1563 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1564 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1565 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1566#ifdef DEBUG_ACPI
1567 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1568 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1569#endif
1570 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1571 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1572 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1573 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1574 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1575 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1576 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1577#undef L
1578#undef R
1579
1580 /* register GC stuff */
1581 if (fGCEnabled)
1582 {
1583 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1584 NULL, NULL, "ACPI PM Timer");
1585 AssertRCReturn(rc, rc);
1586 }
1587
1588 /* register R0 stuff */
1589 if (fR0Enabled)
1590 {
1591 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1592 NULL, NULL, "ACPI PM Timer");
1593 AssertRCReturn(rc, rc);
1594 }
1595
1596 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL, acpiTimer, "ACPI Timer", &s->tsHC);
1597 if (VBOX_FAILURE(rc))
1598 {
1599 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1600 return rc;
1601 }
1602
1603 s->tsGC = TMTimerGCPtr (s->tsHC);
1604 s->pm_timer_initial = TMTimerGet (s->tsHC);
1605 acpiPMTimerReset (s);
1606
1607 dev = &s->dev;
1608 dev->config[0x00] = 0x86;
1609 dev->config[0x01] = 0x80;
1610
1611 dev->config[0x02] = 0x13;
1612 dev->config[0x03] = 0x71;
1613
1614 dev->config[0x04] = 0x01;
1615 dev->config[0x05] = 0x00;
1616
1617 dev->config[0x06] = 0x80;
1618 dev->config[0x07] = 0x02;
1619 dev->config[0x08] = 0x08;
1620 dev->config[0x09] = 0x00;
1621
1622 dev->config[0x0a] = 0x80;
1623 dev->config[0x0b] = 0x06;
1624
1625 dev->config[0x0e] = 0x80;
1626 dev->config[0x0f] = 0x00;
1627
1628#if 0 /* The ACPI controller usually has no subsystem ID. */
1629 dev->config[0x2c] = 0x86;
1630 dev->config[0x2d] = 0x80;
1631 dev->config[0x2e] = 0x00;
1632 dev->config[0x2f] = 0x00;
1633#endif
1634 dev->config[0x3c] = SCI_INT;
1635
1636 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1637 if (VBOX_FAILURE (rc))
1638 return rc;
1639
1640 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1641 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1642 if (VBOX_FAILURE(rc))
1643 return rc;
1644
1645 /*
1646 * Interfaces
1647 */
1648 /* IBase */
1649 s->IBase.pfnQueryInterface = acpiQueryInterface;
1650 /* IACPIPort */
1651 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1652
1653 /*
1654 * Get the corresponding connector interface
1655 */
1656 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1657 if (VBOX_SUCCESS (rc))
1658 {
1659 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1660 PDMINTERFACE_ACPI_CONNECTOR);
1661 if (!s->pDrv)
1662 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1663 N_("LUN #0 doesn't have an ACPI connector interface!\n"));
1664 }
1665 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1666 {
1667 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1668 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1669 rc = VINF_SUCCESS;
1670 }
1671 else
1672 return PDMDEV_SET_ERROR(pDevIns, rc,
1673 N_("Failed to attach LUN #0!"));
1674
1675 return rc;
1676}
1677
1678/**
1679 * Relocates the GC pointer members.
1680 */
1681static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1682{
1683 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1684 s->tsGC = TMTimerGCPtr (s->tsHC);
1685}
1686
1687static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1688{
1689 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1690
1691 s->pm1a_en = 0;
1692 s->pm1a_sts = 0;
1693 s->pm1a_ctl = 0;
1694 s->pm_timer_initial = TMTimerGet (s->CTXSUFF(ts));
1695 acpiPMTimerReset(s);
1696 s->uBatteryIndex = 0;
1697 s->uSystemInfoIndex = 0;
1698 s->gpe0_en = 0;
1699 s->gpe0_sts = 0;
1700 s->uSleepState = 0;
1701
1702 acpiPlantTables(s);
1703}
1704
1705/**
1706 * The device registration structure.
1707 */
1708const PDMDEVREG g_DeviceACPI =
1709{
1710 /* u32Version */
1711 PDM_DEVREG_VERSION,
1712 /* szDeviceName */
1713 "acpi",
1714 /* szGCMod */
1715 "VBoxDDGC.gc",
1716 /* szR0Mod */
1717 "VBoxDDR0.r0",
1718 /* pszDescription */
1719 "Advanced Configuration and Power Interface",
1720 /* fFlags */
1721 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1722 /* fClass */
1723 PDM_DEVREG_CLASS_ACPI,
1724 /* cMaxInstances */
1725 ~0,
1726 /* cbInstance */
1727 sizeof(ACPIState),
1728 /* pfnConstruct */
1729 acpiConstruct,
1730 /* pfnDestruct */
1731 NULL,
1732 /* pfnRelocate */
1733 acpiRelocate,
1734 /* pfnIOCtl */
1735 NULL,
1736 /* pfnPowerOn */
1737 NULL,
1738 /* pfnReset */
1739 acpiReset,
1740 /* pfnSuspend */
1741 NULL,
1742 /* pfnResume */
1743 NULL,
1744 /* pfnAttach */
1745 NULL,
1746 /* pfnDetach */
1747 NULL,
1748 /* pfnQueryInterface. */
1749 NULL
1750};
1751
1752#endif /* IN_RING3 */
1753#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1754
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