VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 67456

Last change on this file since 67456 was 67456, checked in by vboxsync, 7 years ago

DevEFI/DevPciBiops: made McfgBase/McfgLength 64-bit as they already are in DevACPI and DevPciIch9. Also s/MCfgBase/McfgBase/ and s/MCfgSize/McfgSize/ in EFI/Firmware.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 146.7 KB
Line 
1/* $Id: DevACPI.cpp 67456 2017-06-19 08:40:53Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#include <iprt/file.h>
33#ifdef IN_RING3
34# include <iprt/alloc.h>
35# include <iprt/string.h>
36# include <iprt/uuid.h>
37#endif /* IN_RING3 */
38
39#include "VBoxDD.h"
40
41#ifdef LOG_ENABLED
42# define DEBUG_ACPI
43#endif
44
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50#ifdef IN_RING3
51/** Locks the device state, ring-3 only. */
52# define DEVACPI_LOCK_R3(a_pThis) \
53 do { \
54 int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
55 AssertRC(rcLock); \
56 } while (0)
57#endif
58/** Unlocks the device state (all contexts). */
59#define DEVACPI_UNLOCK(a_pThis) \
60 do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
61
62
63#define DEBUG_HEX 0x3000
64#define DEBUG_CHR 0x3001
65
66/** PM Base Address PCI config space offset */
67#define PMBA 0x40
68/** PM Miscellaneous Power Management PCI config space offset */
69#define PMREGMISC 0x80
70
71#define PM_TMR_FREQ 3579545
72/** Default base for PM PIIX4 device */
73#define PM_PORT_BASE 0x4000
74/* Port offsets in PM device */
75enum
76{
77 PM1a_EVT_OFFSET = 0x00,
78 PM1b_EVT_OFFSET = -1, /**< not supported */
79 PM1a_CTL_OFFSET = 0x04,
80 PM1b_CTL_OFFSET = -1, /**< not supported */
81 PM2_CTL_OFFSET = -1, /**< not supported */
82 PM_TMR_OFFSET = 0x08,
83 GPE0_OFFSET = 0x20,
84 GPE1_OFFSET = -1 /**< not supported */
85};
86
87/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
88#define PM_TMR_32BIT
89
90#define BAT_INDEX 0x00004040
91#define BAT_DATA 0x00004044
92#define SYSI_INDEX 0x00004048
93#define SYSI_DATA 0x0000404c
94#define ACPI_RESET_BLK 0x00004050
95
96/* PM1x status register bits */
97#define TMR_STS RT_BIT(0)
98#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
99#define BM_STS RT_BIT(4)
100#define GBL_STS RT_BIT(5)
101#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
102#define PWRBTN_STS RT_BIT(8)
103#define SLPBTN_STS RT_BIT(9)
104#define RTC_STS RT_BIT(10)
105#define IGN_STS RT_BIT(11)
106#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
107#define WAK_STS RT_BIT(15)
108#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
109
110/* PM1x enable register bits */
111#define TMR_EN RT_BIT(0)
112#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
113#define GBL_EN RT_BIT(5)
114#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
115#define PWRBTN_EN RT_BIT(8)
116#define SLPBTN_EN RT_BIT(9)
117#define RTC_EN RT_BIT(10)
118#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
119#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
120#define IGN_EN 0
121
122/* PM1x control register bits */
123#define SCI_EN RT_BIT(0)
124#define BM_RLD RT_BIT(1)
125#define GBL_RLS RT_BIT(2)
126#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
127#define IGN_CNT RT_BIT(9)
128#define SLP_TYPx_SHIFT 10
129#define SLP_TYPx_MASK 7
130#define SLP_EN RT_BIT(13)
131#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
132#define RSR_CNT (RSR1_CNT | RSR2_CNT)
133
134#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
135
136enum
137{
138 BAT_STATUS_STATE = 0x00, /**< BST battery state */
139 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
140 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
141 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
142 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
143 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
144 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
145 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
146 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
147 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
148 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
149 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
150 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
151 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
152 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
153 BAT_INDEX_LAST
154};
155
156enum
157{
158 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
159 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
160};
161
162enum
163{
164 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
165 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
166 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
167 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
168 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
169 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
170 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
171 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
172 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
173 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
174 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
175 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
176 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
177 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
178 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
179 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
180 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
181 SYSTEM_INFO_INDEX_POWER_STATES = 17,
182 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
183 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
184 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
185 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
186 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
187 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
188 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
189 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
190 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
191 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
192 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
193 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
194 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
195 SYSTEM_INFO_INDEX_END = 31,
196 SYSTEM_INFO_INDEX_INVALID = 0x80,
197 SYSTEM_INFO_INDEX_VALID = 0x200
198};
199
200#define AC_OFFLINE 0
201#define AC_ONLINE 1
202
203#define BAT_TECH_PRIMARY 1
204#define BAT_TECH_SECONDARY 2
205
206#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
207#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
208#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
209#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
210#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
211
212/** SMBus Base Address PCI config space offset */
213#define SMBBA 0x90
214/** SMBus Host Configuration PCI config space offset */
215#define SMBHSTCFG 0xd2
216/** SMBus Slave Command PCI config space offset */
217#define SMBSLVC 0xd3
218/** SMBus Slave Shadow Port 1 PCI config space offset */
219#define SMBSHDW1 0xd4
220/** SMBus Slave Shadow Port 2 PCI config space offset */
221#define SMBSHDW2 0xd5
222/** SMBus Revision Identification PCI config space offset */
223#define SMBREV 0xd6
224
225#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
226#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
227#define SMBHSTCFG_INTRSEL_SMI 0
228#define SMBHSTCFG_INTRSEL_IRQ9 4
229#define SMBHSTCFG_INTRSEL_SHIFT 1
230
231/** Default base for SMBus PIIX4 device */
232#define SMB_PORT_BASE 0x4100
233
234/** SMBus Host Status Register I/O offset */
235#define SMBHSTSTS_OFF 0x0000
236/** SMBus Slave Status Register I/O offset */
237#define SMBSLVSTS_OFF 0x0001
238/** SMBus Host Count Register I/O offset */
239#define SMBHSTCNT_OFF 0x0002
240/** SMBus Host Command Register I/O offset */
241#define SMBHSTCMD_OFF 0x0003
242/** SMBus Host Address Register I/O offset */
243#define SMBHSTADD_OFF 0x0004
244/** SMBus Host Data 0 Register I/O offset */
245#define SMBHSTDAT0_OFF 0x0005
246/** SMBus Host Data 1 Register I/O offset */
247#define SMBHSTDAT1_OFF 0x0006
248/** SMBus Block Data Register I/O offset */
249#define SMBBLKDAT_OFF 0x0007
250/** SMBus Slave Control Register I/O offset */
251#define SMBSLVCNT_OFF 0x0008
252/** SMBus Shadow Command Register I/O offset */
253#define SMBSHDWCMD_OFF 0x0009
254/** SMBus Slave Event Register I/O offset */
255#define SMBSLVEVT_OFF 0x000a
256/** SMBus Slave Data Register I/O offset */
257#define SMBSLVDAT_OFF 0x000c
258
259#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
260#define SMBHSTSTS_INTER RT_BIT(1)
261#define SMBHSTSTS_DEV_ERR RT_BIT(2)
262#define SMBHSTSTS_BUS_ERR RT_BIT(3)
263#define SMBHSTSTS_FAILED RT_BIT(4)
264#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
265
266#define SMBSLVSTS_WRITE_MASK 0x3c
267
268#define SMBHSTCNT_INTEREN RT_BIT(0)
269#define SMBHSTCNT_KILL RT_BIT(1)
270#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
271#define SMBHSTCNT_START RT_BIT(6)
272#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
273
274#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
275
276
277/*********************************************************************************************************************************
278* Structures and Typedefs *
279*********************************************************************************************************************************/
280/**
281 * The ACPI device state.
282 */
283typedef struct ACPIState
284{
285 PDMPCIDEV dev;
286 /** Critical section protecting the ACPI state. */
287 PDMCRITSECT CritSect;
288
289 uint16_t pm1a_en;
290 uint16_t pm1a_sts;
291 uint16_t pm1a_ctl;
292 /** Number of logical CPUs in guest */
293 uint16_t cCpus;
294 uint64_t u64PmTimerInitial;
295 PTMTIMERR3 pPmTimerR3;
296 PTMTIMERR0 pPmTimerR0;
297 PTMTIMERRC pPmTimerRC;
298
299 /* PM Timer last calculated value */
300 uint32_t uPmTimerVal;
301 uint32_t Alignment0;
302
303 uint32_t gpe0_en;
304 uint32_t gpe0_sts;
305
306 uint32_t uBatteryIndex;
307 uint32_t au8BatteryInfo[13];
308
309 uint32_t uSystemInfoIndex;
310 uint64_t u64RamSize;
311 /** Offset of the 64-bit prefetchable memory window. */
312 uint64_t u64PciPref64Min;
313 /** Limit of the 64-bit prefetchable memory window. */
314 uint64_t u64PciPref64Max;
315 /** The number of bytes below 4GB. */
316 uint32_t cbRamLow;
317
318 /** Current ACPI S* state. We support S0 and S5. */
319 uint32_t uSleepState;
320 uint8_t au8RSDPPage[0x1000];
321 /** This is a workaround for incorrect index field handling by Intels ACPICA.
322 * The system info _INI method writes to offset 0x200. We either observe a
323 * write request to index 0x80 (in that case we don't change the index) or a
324 * write request to offset 0x200 (in that case we divide the index value by
325 * 4. Note that the _STA method is sometimes called prior to the _INI method
326 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
327 * acpiR3BatIndexWrite() for handling this. */
328 uint8_t u8IndexShift;
329 /** provide an I/O-APIC */
330 uint8_t u8UseIOApic;
331 /** provide a floppy controller */
332 bool fUseFdc;
333 /** If High Precision Event Timer device should be supported */
334 bool fUseHpet;
335 /** If System Management Controller device should be supported */
336 bool fUseSmc;
337 /** the guest handled the last power button event */
338 bool fPowerButtonHandled;
339 /** If ACPI CPU device should be shown */
340 bool fShowCpu;
341 /** If Real Time Clock ACPI object to be shown */
342 bool fShowRtc;
343 /** I/O port address of PM device. */
344 RTIOPORT uPmIoPortBase;
345 /** I/O port address of SMBus device. */
346 RTIOPORT uSMBusIoPortBase;
347 /** Flag whether the GC part of the device is enabled. */
348 bool fGCEnabled;
349 /** Flag whether the R0 part of the device is enabled. */
350 bool fR0Enabled;
351 /** Array of flags of attached CPUs */
352 VMCPUSET CpuSetAttached;
353 /** Which CPU to check for the locked status. */
354 uint32_t idCpuLockCheck;
355 /** Mask of locked CPUs (used by the guest). */
356 VMCPUSET CpuSetLocked;
357 /** The CPU event type. */
358 uint32_t u32CpuEventType;
359 /** The CPU id affected. */
360 uint32_t u32CpuEvent;
361 /** Flag whether CPU hot plugging is enabled. */
362 bool fCpuHotPlug;
363 /** If MCFG ACPI table shown to the guest */
364 bool fUseMcfg;
365 /** if the 64-bit prefetchable memory window is shown to the guest */
366 bool fPciPref64Enabled;
367 /** Primary NIC PCI address. */
368 uint32_t u32NicPciAddress;
369 /** Primary audio card PCI address. */
370 uint32_t u32AudioPciAddress;
371 /** Flag whether S1 power state is enabled. */
372 bool fS1Enabled;
373 /** Flag whether S4 power state is enabled. */
374 bool fS4Enabled;
375 /** Flag whether S1 triggers a state save. */
376 bool fSuspendToSavedState;
377 /** Flag whether to set WAK_STS on resume (restore included). */
378 bool fSetWakeupOnResume;
379 /** PCI address of the IO controller device. */
380 uint32_t u32IocPciAddress;
381 /** PCI address of the host bus controller device. */
382 uint32_t u32HbcPciAddress;
383
384 uint32_t Alignment1;
385
386 /** Physical address of PCI config space MMIO region */
387 uint64_t u64PciConfigMMioAddress;
388 /** Length of PCI config space MMIO region */
389 uint64_t u64PciConfigMMioLength;
390 /** Serial 0 IRQ number */
391 uint8_t uSerial0Irq;
392 /** Serial 1 IRQ number */
393 uint8_t uSerial1Irq;
394 /** Serial 2 IRQ number */
395 uint8_t uSerial2Irq;
396 /** Serial 3 IRQ number */
397 uint8_t uSerial3Irq;
398 /** Serial 0 IO port base */
399 RTIOPORT uSerial0IoPortBase;
400 /** Serial 1 IO port base */
401 RTIOPORT uSerial1IoPortBase;
402 /** Serial 2 IO port base */
403 RTIOPORT uSerial2IoPortBase;
404 /** Serial 3 IO port base */
405 RTIOPORT uSerial3IoPortBase;
406
407 /** @name Parallel port config bits
408 * @{ */
409 /** Parallel 0 IRQ number */
410 uint8_t uParallel0Irq;
411 /** Parallel 1 IRQ number */
412 uint8_t uParallel1Irq;
413 /** Parallel 0 IO port base */
414 RTIOPORT uParallel0IoPortBase;
415 /** Parallel 1 IO port base */
416 RTIOPORT uParallel1IoPortBase;
417 /** @} */
418
419 uint32_t Alignment2;
420
421 /** ACPI port base interface. */
422 PDMIBASE IBase;
423 /** ACPI port interface. */
424 PDMIACPIPORT IACPIPort;
425 /** Pointer to the device instance. */
426 PPDMDEVINSR3 pDevInsR3;
427 PPDMDEVINSR0 pDevInsR0;
428 PPDMDEVINSRC pDevInsRC;
429
430 uint32_t Alignment3;
431 /** Pointer to the driver base interface. */
432 R3PTRTYPE(PPDMIBASE) pDrvBase;
433 /** Pointer to the driver connector interface. */
434 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
435
436 /** Pointer to default PCI config read function. */
437 R3PTRTYPE(PFNPCICONFIGREAD) pfnAcpiPciConfigRead;
438 /** Pointer to default PCI config write function. */
439 R3PTRTYPE(PFNPCICONFIGWRITE) pfnAcpiPciConfigWrite;
440
441 /** If custom table should be supported */
442 bool fUseCust;
443 /** ACPI OEM ID */
444 uint8_t au8OemId[6];
445 /** ACPI Crator ID */
446 uint8_t au8CreatorId[4];
447 /** ACPI Crator Rev */
448 uint32_t u32CreatorRev;
449 /** ACPI custom OEM Tab ID */
450 uint8_t au8OemTabId[8];
451 /** ACPI custom OEM Rev */
452 uint32_t u32OemRevision;
453 uint32_t Alignment4;
454
455 /** The custom table binary data. */
456 R3PTRTYPE(uint8_t *) pu8CustBin;
457 /** The size of the custom table binary. */
458 uint64_t cbCustBin;
459
460 /** SMBus Host Status Register */
461 uint8_t u8SMBusHstSts;
462 /** SMBus Slave Status Register */
463 uint8_t u8SMBusSlvSts;
464 /** SMBus Host Control Register */
465 uint8_t u8SMBusHstCnt;
466 /** SMBus Host Command Register */
467 uint8_t u8SMBusHstCmd;
468 /** SMBus Host Address Register */
469 uint8_t u8SMBusHstAdd;
470 /** SMBus Host Data 0 Register */
471 uint8_t u8SMBusHstDat0;
472 /** SMBus Host Data 1 Register */
473 uint8_t u8SMBusHstDat1;
474 /** SMBus Slave Control Register */
475 uint8_t u8SMBusSlvCnt;
476 /** SMBus Shadow Command Register */
477 uint8_t u8SMBusShdwCmd;
478 /** SMBus Slave Event Register */
479 uint16_t u16SMBusSlvEvt;
480 /** SMBus Slave Data Register */
481 uint16_t u16SMBusSlvDat;
482 /** SMBus Host Block Data Buffer */
483 uint8_t au8SMBusBlkDat[32];
484 /** SMBus Host Block Index */
485 uint8_t u8SMBusBlkIdx;
486} ACPIState;
487
488#pragma pack(1)
489
490/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
491struct ACPIGENADDR
492{
493 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
494 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
495 uint8_t u8RegisterBitOffset; /**< bit offset of register */
496 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
497 uint64_t u64Address; /**< 64-bit address of register */
498};
499AssertCompileSize(ACPIGENADDR, 12);
500
501/** Root System Description Pointer */
502struct ACPITBLRSDP
503{
504 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
505 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
506 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
507 uint8_t u8Revision; /**< revision number, currently 2 */
508#define ACPI_REVISION 2 /**< ACPI 3.0 */
509 uint32_t u32RSDT; /**< phys addr of RSDT */
510 uint32_t u32Length; /**< bytes of this table */
511 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
512 uint8_t u8ExtChecksum; /**< checksum of entire table */
513 uint8_t u8Reserved[3]; /**< reserved */
514};
515AssertCompileSize(ACPITBLRSDP, 36);
516
517/** System Description Table Header */
518struct ACPITBLHEADER
519{
520 uint8_t au8Signature[4]; /**< table identifier */
521 uint32_t u32Length; /**< length of the table including header */
522 uint8_t u8Revision; /**< revision number */
523 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
524 uint8_t au8OemId[6]; /**< OEM-supplied string */
525 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
526 uint32_t u32OemRevision; /**< OEM-supplied revision number */
527 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
528 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
529};
530AssertCompileSize(ACPITBLHEADER, 36);
531
532/** Root System Description Table */
533struct ACPITBLRSDT
534{
535 ACPITBLHEADER header;
536 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
537};
538AssertCompileSize(ACPITBLRSDT, 40);
539
540/** Extended System Description Table */
541struct ACPITBLXSDT
542{
543 ACPITBLHEADER header;
544 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
545};
546AssertCompileSize(ACPITBLXSDT, 44);
547
548/** Fixed ACPI Description Table */
549struct ACPITBLFADT
550{
551 ACPITBLHEADER header;
552 uint32_t u32FACS; /**< phys. address of FACS */
553 uint32_t u32DSDT; /**< phys. address of DSDT */
554 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
555#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
556#define INT_MODEL_MULTIPLE_APIC 2
557 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
558 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
559#define SCI_INT 9
560 uint32_t u32SMICmd; /**< system port address of SMI command port */
561#define SMI_CMD 0x0000442e
562 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
563#define ACPI_ENABLE 0xa1
564 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
565#define ACPI_DISABLE 0xa0
566 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
567 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
568 state control responsibility */
569 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
570 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
571 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
572 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
573 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
574 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
575 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
576 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
577 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
578 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
579 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
580 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
581 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
582#define GPE0_BLK_LEN 2
583 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
584#define GPE1_BLK_LEN 0
585 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
586#define GPE1_BASE 0
587 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
588 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
589#define P_LVL2_LAT 101 /**< C2 state not supported */
590 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
591#define P_LVL3_LAT 1001 /**< C3 state not supported */
592 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
593 lines from any processors memory caches */
594#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
595 uint16_t u16FlushStride; /**< cache line width */
596#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
597 uint8_t u8DutyOffset;
598 uint8_t u8DutyWidth;
599 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
600 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
601 uint8_t u8Century; /**< RTC CMOS RAM index of century */
602 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
603#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
604 (COM too?) */
605#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
606#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
607#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
608#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
609 uint8_t u8Must0_0; /**< must be 0 */
610 uint32_t u32Flags; /**< fixed feature flags */
611#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
612#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
613#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
614#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
615#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
616#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
617#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
618#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
619#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
620#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
621#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
622#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
623#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
624#define FADT_FL_CPU_SW_SLP RT_BIT(13)
625#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
626#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
627#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
628#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
629#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
630#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
631
632/* PM Timer mask and msb */
633#ifndef PM_TMR_32BIT
634#define TMR_VAL_MSB 0x800000
635#define TMR_VAL_MASK 0xffffff
636#undef FADT_FL_TMR_VAL_EXT
637#define FADT_FL_TMR_VAL_EXT 0
638#else
639#define TMR_VAL_MSB 0x80000000
640#define TMR_VAL_MASK 0xffffffff
641#endif
642
643 /** Start of the ACPI 2.0 extension. */
644 ACPIGENADDR ResetReg; /**< ext addr of reset register */
645 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
646#define ACPI_RESET_REG_VAL 0x10
647 uint8_t au8Must0_1[3]; /**< must be 0 */
648 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
649 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
650 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
651 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
652 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
653 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
654 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
655 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
656 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
657 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
658};
659AssertCompileSize(ACPITBLFADT, 244);
660#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
661
662/** Firmware ACPI Control Structure */
663struct ACPITBLFACS
664{
665 uint8_t au8Signature[4]; /**< 'FACS' */
666 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
667 uint32_t u32HWSignature; /**< systems HW signature at last boot */
668 uint32_t u32FWVector; /**< address of waking vector */
669 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
670 uint32_t u32Flags; /**< FACS flags */
671 uint64_t u64X_FWVector; /**< 64-bit waking vector */
672 uint8_t u8Version; /**< version of this table */
673 uint8_t au8Reserved[31]; /**< zero */
674};
675AssertCompileSize(ACPITBLFACS, 64);
676
677/** Processor Local APIC Structure */
678struct ACPITBLLAPIC
679{
680 uint8_t u8Type; /**< 0 = LAPIC */
681 uint8_t u8Length; /**< 8 */
682 uint8_t u8ProcId; /**< processor ID */
683 uint8_t u8ApicId; /**< local APIC ID */
684 uint32_t u32Flags; /**< Flags */
685#define LAPIC_ENABLED 0x1
686};
687AssertCompileSize(ACPITBLLAPIC, 8);
688
689/** I/O APIC Structure */
690struct ACPITBLIOAPIC
691{
692 uint8_t u8Type; /**< 1 == I/O APIC */
693 uint8_t u8Length; /**< 12 */
694 uint8_t u8IOApicId; /**< I/O APIC ID */
695 uint8_t u8Reserved; /**< 0 */
696 uint32_t u32Address; /**< phys address to access I/O APIC */
697 uint32_t u32GSIB; /**< global system interrupt number to start */
698};
699AssertCompileSize(ACPITBLIOAPIC, 12);
700
701/** Interrupt Source Override Structure */
702struct ACPITBLISO
703{
704 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
705 uint8_t u8Length; /**< 10 */
706 uint8_t u8Bus; /**< Bus */
707 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
708 uint32_t u32GSI; /**< Global System Interrupt */
709 uint16_t u16Flags; /**< MPS INTI flags Global */
710};
711AssertCompileSize(ACPITBLISO, 10);
712#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
713
714/** HPET Descriptor Structure */
715struct ACPITBLHPET
716{
717 ACPITBLHEADER aHeader;
718 uint32_t u32Id; /**< hardware ID of event timer block
719 [31:16] PCI vendor ID of first timer block
720 [15] legacy replacement IRQ routing capable
721 [14] reserved
722 [13] COUNT_SIZE_CAP counter size
723 [12:8] number of comparators in first timer block
724 [7:0] hardware rev ID */
725 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
726 uint8_t u32Number; /**< sequence number starting at 0 */
727 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
728 lost interrupts while the counter is programmed
729 to operate in periodic mode. Unit: clock tick. */
730 uint8_t u8Attributes; /**< page protection and OEM attribute. */
731};
732AssertCompileSize(ACPITBLHPET, 56);
733
734/** MCFG Descriptor Structure */
735typedef struct ACPITBLMCFG
736{
737 ACPITBLHEADER aHeader;
738 uint64_t u64Reserved;
739} ACPITBLMCFG;
740AssertCompileSize(ACPITBLMCFG, 44);
741
742/** Number of such entries can be computed from the whole table length in header */
743typedef struct ACPITBLMCFGENTRY
744{
745 uint64_t u64BaseAddress;
746 uint16_t u16PciSegmentGroup;
747 uint8_t u8StartBus;
748 uint8_t u8EndBus;
749 uint32_t u32Reserved;
750} ACPITBLMCFGENTRY;
751AssertCompileSize(ACPITBLMCFGENTRY, 16);
752
753#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
754
755/** Custom Description Table */
756struct ACPITBLCUST
757{
758 ACPITBLHEADER header;
759 uint8_t au8Data[476];
760};
761AssertCompileSize(ACPITBLCUST, 512);
762
763
764#pragma pack()
765
766
767#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
768
769
770/*********************************************************************************************************************************
771* Internal Functions *
772*********************************************************************************************************************************/
773RT_C_DECLS_BEGIN
774PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
775RT_C_DECLS_END
776#ifdef IN_RING3
777static int acpiR3PlantTables(ACPIState *pThis);
778#endif
779
780/* SCI, usually IRQ9 */
781DECLINLINE(void) acpiSetIrq(ACPIState *pThis, int level)
782{
783 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, level);
784}
785
786DECLINLINE(bool) pm1a_level(ACPIState *pThis)
787{
788 return (pThis->pm1a_ctl & SCI_EN)
789 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
790}
791
792DECLINLINE(bool) gpe0_level(ACPIState *pThis)
793{
794 return !!(pThis->gpe0_en & pThis->gpe0_sts);
795}
796
797DECLINLINE(bool) smbus_level(ACPIState *pThis)
798{
799 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
800 && (pThis->dev.abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
801 && (pThis->dev.abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
802 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
803}
804
805DECLINLINE(bool) acpiSCILevel(ACPIState *pThis)
806{
807 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pThis);
808}
809
810/**
811 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
812 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
813 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
814 * registers and trigger IRQs.
815 *
816 * Caller must hold the state lock.
817 *
818 * @param pThis The ACPI instance.
819 * @param sts The new PM1a.STS value.
820 * @param en The new PM1a.EN value.
821 */
822static void apicUpdatePm1a(ACPIState *pThis, uint32_t sts, uint32_t en)
823{
824 Assert(PDMCritSectIsOwner(&pThis->CritSect));
825
826 const bool old_level = acpiSCILevel(pThis);
827 pThis->pm1a_en = en;
828 pThis->pm1a_sts = sts;
829 const bool new_level = acpiSCILevel(pThis);
830
831 LogFunc(("old=%x new=%x\n", old_level, new_level));
832
833 if (new_level != old_level)
834 acpiSetIrq(pThis, new_level);
835}
836
837#ifdef IN_RING3
838
839/**
840 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
841 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
842 *
843 * Caller must hold the state lock.
844 *
845 * @param pThis The ACPI instance.
846 * @param sts The new GPE0.STS value.
847 * @param en The new GPE0.EN value.
848 */
849static void apicR3UpdateGpe0(ACPIState *pThis, uint32_t sts, uint32_t en)
850{
851 Assert(PDMCritSectIsOwner(&pThis->CritSect));
852
853 const bool old_level = acpiSCILevel(pThis);
854 pThis->gpe0_en = en;
855 pThis->gpe0_sts = sts;
856 const bool new_level = acpiSCILevel(pThis);
857
858 LogFunc(("old=%x new=%x\n", old_level, new_level));
859
860 if (new_level != old_level)
861 acpiSetIrq(pThis, new_level);
862}
863
864/**
865 * Used by acpiR3PM1aCtlWrite to power off the VM.
866 *
867 * @param pThis The ACPI instance.
868 * @returns Strict VBox status code.
869 */
870static int acpiR3DoPowerOff(ACPIState *pThis)
871{
872 int rc = PDMDevHlpVMPowerOff(pThis->pDevInsR3);
873 if (RT_FAILURE(rc))
874 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
875 return rc;
876}
877
878/**
879 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
880 *
881 * @param pThis The ACPI instance.
882 * @returns Strict VBox status code.
883 */
884static int acpiR3DoSleep(ACPIState *pThis)
885{
886 /* We must set WAK_STS on resume (includes restore) so the guest knows that
887 we've woken up and can continue executing code. The guest is probably
888 reading the PMSTS register in a loop to check this. */
889 int rc;
890 pThis->fSetWakeupOnResume = true;
891 if (pThis->fSuspendToSavedState)
892 {
893 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pThis->pDevInsR3);
894 if (rc != VERR_NOT_SUPPORTED)
895 AssertRC(rc);
896 else
897 {
898 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
899 rc = PDMDevHlpVMSuspend(pThis->pDevInsR3);
900 AssertRC(rc);
901 }
902 }
903 else
904 {
905 rc = PDMDevHlpVMSuspend(pThis->pDevInsR3);
906 AssertRC(rc);
907 }
908 return rc;
909}
910
911
912/**
913 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
914 */
915static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
916{
917 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
918 DEVACPI_LOCK_R3(pThis);
919
920 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
921 pThis->fPowerButtonHandled = false;
922 apicUpdatePm1a(pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
923
924 DEVACPI_UNLOCK(pThis);
925 return VINF_SUCCESS;
926}
927
928/**
929 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
930 */
931static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
932{
933 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
934 DEVACPI_LOCK_R3(pThis);
935
936 *pfHandled = pThis->fPowerButtonHandled;
937
938 DEVACPI_UNLOCK(pThis);
939 return VINF_SUCCESS;
940}
941
942/**
943 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
944 * Guest entered into G0 (working) or G1 (sleeping)}
945 */
946static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
947{
948 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
949 DEVACPI_LOCK_R3(pThis);
950
951 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
952
953 DEVACPI_UNLOCK(pThis);
954 return VINF_SUCCESS;
955}
956
957/**
958 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
959 */
960static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
961{
962 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
963 DEVACPI_LOCK_R3(pThis);
964
965 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
966
967 DEVACPI_UNLOCK(pThis);
968 return VINF_SUCCESS;
969}
970
971/**
972 * Send an ACPI sleep button event.
973 *
974 * @returns VBox status code
975 * @param pInterface Pointer to the interface structure containing the called function pointer.
976 */
977static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
978{
979 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
980 DEVACPI_LOCK_R3(pThis);
981
982 apicUpdatePm1a(pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
983
984 DEVACPI_UNLOCK(pThis);
985 return VINF_SUCCESS;
986}
987
988/**
989 * Send an ACPI monitor hot-plug event.
990 *
991 * @returns VBox status code
992 * @param pInterface Pointer to the interface structure containing the
993 * called function pointer.
994 */
995static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
996{
997 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
998 DEVACPI_LOCK_R3(pThis);
999
1000 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1001
1002 DEVACPI_UNLOCK(pThis);
1003 return VINF_SUCCESS;
1004}
1005
1006/**
1007 * Send an ACPI battery status change event.
1008 *
1009 * @returns VBox status code
1010 * @param pInterface Pointer to the interface structure containing the
1011 * called function pointer.
1012 */
1013static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1014{
1015 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
1016 DEVACPI_LOCK_R3(pThis);
1017
1018 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1019
1020 DEVACPI_UNLOCK(pThis);
1021 return VINF_SUCCESS;
1022}
1023
1024/**
1025 * Used by acpiR3PmTimer to re-arm the PM timer.
1026 *
1027 * The caller is expected to either hold the clock lock or to have made sure
1028 * the VM is resetting or loading state.
1029 *
1030 * @param pThis The ACPI instance.
1031 * @param uNow The current time.
1032 */
1033static void acpiR3PmTimerReset(ACPIState *pThis, uint64_t uNow)
1034{
1035 uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer));
1036 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1037 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1038 TMTimerSet(pThis->pPmTimerR3, uNow + uInterval + 1);
1039 Log(("acpi: uInterval = %RU64\n", uInterval));
1040}
1041
1042#endif
1043
1044/**
1045 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1046 *
1047 * The caller is expected to either hold the clock lock or to have made sure
1048 * the VM is resetting or loading state.
1049 *
1050 * @param pThis The ACPI instance
1051 * @param u64Now The current time
1052 */
1053
1054static void acpiPmTimerUpdate(ACPIState *pThis, uint64_t u64Now)
1055{
1056 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1057 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1058 Assert(TMTimerIsLockOwner(pThis->CTX_SUFF(pPmTimer)));
1059
1060 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer))) & TMR_VAL_MASK;
1061
1062 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1063 {
1064 apicUpdatePm1a(pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1065 }
1066}
1067
1068#ifdef IN_RING3
1069
1070/**
1071 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1072 */
1073static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1074{
1075 ACPIState *pThis = (ACPIState *)pvUser;
1076 Assert(TMTimerIsLockOwner(pTimer));
1077 NOREF(pDevIns);
1078
1079 DEVACPI_LOCK_R3(pThis);
1080 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1081 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1082 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1083 uint64_t u64Now = TMTimerGet(pTimer);
1084 acpiPmTimerUpdate(pThis, u64Now);
1085 DEVACPI_UNLOCK(pThis);
1086
1087 acpiR3PmTimerReset(pThis, u64Now);
1088}
1089
1090/**
1091 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1092 * acpiR3LoadState.
1093 *
1094 * @returns VINF_SUCCESS.
1095 * @param pThis The ACPI instance.
1096 */
1097static int acpiR3FetchBatteryStatus(ACPIState *pThis)
1098{
1099 uint32_t *p = pThis->au8BatteryInfo;
1100 bool fPresent; /* battery present? */
1101 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1102 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1103 uint32_t hostPresentRate; /* 0..1000 */
1104 int rc;
1105
1106 if (!pThis->pDrv)
1107 return VINF_SUCCESS;
1108 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
1109 &hostBatteryState, &hostPresentRate);
1110 AssertRC(rc);
1111
1112 /* default values */
1113 p[BAT_STATUS_STATE] = hostBatteryState;
1114 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1115 : hostPresentRate * 50; /* mW */
1116 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1117 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1118
1119 /* did we get a valid battery state? */
1120 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1121 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1122 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1123 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1124
1125 return VINF_SUCCESS;
1126}
1127
1128/**
1129 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1130 * acpiR3LoadState.
1131 *
1132 * @returns VINF_SUCCESS.
1133 * @param pThis The ACPI instance.
1134 */
1135static int acpiR3FetchBatteryInfo(ACPIState *pThis)
1136{
1137 uint32_t *p = pThis->au8BatteryInfo;
1138
1139 p[BAT_INFO_UNITS] = 0; /* mWh */
1140 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1141 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1142 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1143 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1144 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1145 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1146 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1147 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1148
1149 return VINF_SUCCESS;
1150}
1151
1152/**
1153 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1154 *
1155 * @returns status mask or 0.
1156 * @param pThis The ACPI instance.
1157 */
1158static uint32_t acpiR3GetBatteryDeviceStatus(ACPIState *pThis)
1159{
1160 bool fPresent; /* battery present? */
1161 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1162 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1163 uint32_t hostPresentRate; /* 0..1000 */
1164 int rc;
1165
1166 if (!pThis->pDrv)
1167 return 0;
1168 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
1169 &hostBatteryState, &hostPresentRate);
1170 AssertRC(rc);
1171
1172 return fPresent
1173 ? STA_DEVICE_PRESENT_MASK /* present */
1174 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1175 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1176 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1177 | STA_BATTERY_PRESENT_MASK /* battery is present */
1178 : 0; /* device not present */
1179}
1180
1181/**
1182 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1183 *
1184 * @returns status.
1185 * @param pThis The ACPI instance.
1186 */
1187static uint32_t acpiR3GetPowerSource(ACPIState *pThis)
1188{
1189 /* query the current power source from the host driver */
1190 if (!pThis->pDrv)
1191 return AC_ONLINE;
1192
1193 PDMACPIPOWERSOURCE ps;
1194 int rc = pThis->pDrv->pfnQueryPowerSource(pThis->pDrv, &ps);
1195 AssertRC(rc);
1196 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1197}
1198
1199/**
1200 * @callback_method_impl{FNIOMIOPORTOUT, Battery status index}
1201 */
1202PDMBOTHCBDECL(int) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1203{
1204 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1205 if (cb != 4)
1206 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1207
1208 ACPIState *pThis = (ACPIState *)pvUser;
1209 DEVACPI_LOCK_R3(pThis);
1210
1211 u32 >>= pThis->u8IndexShift;
1212 /* see comment at the declaration of u8IndexShift */
1213 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1214 {
1215 pThis->u8IndexShift = 2;
1216 u32 >>= 2;
1217 }
1218 Assert(u32 < BAT_INDEX_LAST);
1219 pThis->uBatteryIndex = u32;
1220
1221 DEVACPI_UNLOCK(pThis);
1222 return VINF_SUCCESS;
1223}
1224
1225/**
1226 * @callback_method_impl{FNIOMIOPORTIN, Battery status data}
1227 */
1228PDMBOTHCBDECL(int) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1229{
1230 if (cb != 4)
1231 return VERR_IOM_IOPORT_UNUSED;
1232
1233 ACPIState *pThis = (ACPIState *)pvUser;
1234 DEVACPI_LOCK_R3(pThis);
1235
1236 int rc = VINF_SUCCESS;
1237 switch (pThis->uBatteryIndex)
1238 {
1239 case BAT_STATUS_STATE:
1240 acpiR3FetchBatteryStatus(pThis);
1241 /* fall thru */
1242 case BAT_STATUS_PRESENT_RATE:
1243 case BAT_STATUS_REMAINING_CAPACITY:
1244 case BAT_STATUS_PRESENT_VOLTAGE:
1245 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1246 break;
1247
1248 case BAT_INFO_UNITS:
1249 acpiR3FetchBatteryInfo(pThis);
1250 /* fall thru */
1251 case BAT_INFO_DESIGN_CAPACITY:
1252 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1253 case BAT_INFO_TECHNOLOGY:
1254 case BAT_INFO_DESIGN_VOLTAGE:
1255 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1256 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1257 case BAT_INFO_CAPACITY_GRANULARITY_1:
1258 case BAT_INFO_CAPACITY_GRANULARITY_2:
1259 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1260 break;
1261
1262 case BAT_DEVICE_STATUS:
1263 *pu32 = acpiR3GetBatteryDeviceStatus(pThis);
1264 break;
1265
1266 case BAT_POWER_SOURCE:
1267 *pu32 = acpiR3GetPowerSource(pThis);
1268 break;
1269
1270 default:
1271 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1272 *pu32 = UINT32_MAX;
1273 break;
1274 }
1275
1276 DEVACPI_UNLOCK(pThis);
1277 return rc;
1278}
1279
1280/**
1281 * @callback_method_impl{FNIOMIOPORTOUT, System info index}
1282 */
1283PDMBOTHCBDECL(int) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1284{
1285 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1286 if (cb != 4)
1287 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1288
1289 ACPIState *pThis = (ACPIState *)pvUser;
1290 DEVACPI_LOCK_R3(pThis);
1291
1292 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1293 pThis->uSystemInfoIndex = u32;
1294 else
1295 {
1296 /* see comment at the declaration of u8IndexShift */
1297 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1298 {
1299 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1300 pThis->u8IndexShift = 2;
1301 }
1302
1303 u32 >>= pThis->u8IndexShift;
1304 Assert(u32 < SYSTEM_INFO_INDEX_END);
1305 pThis->uSystemInfoIndex = u32;
1306 }
1307
1308 DEVACPI_UNLOCK(pThis);
1309 return VINF_SUCCESS;
1310}
1311
1312/**
1313 * @callback_method_impl{FNIOMIOPORTIN, System info data}
1314 */
1315PDMBOTHCBDECL(int) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1316{
1317 if (cb != 4)
1318 return VERR_IOM_IOPORT_UNUSED;
1319
1320 ACPIState *pThis = (ACPIState *)pvUser;
1321 DEVACPI_LOCK_R3(pThis);
1322
1323 int rc = VINF_SUCCESS;
1324 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1325 switch (uSystemInfoIndex)
1326 {
1327 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1328 *pu32 = pThis->cbRamLow;
1329 break;
1330
1331 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1332 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1333 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1334 break;
1335
1336 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1337 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1338 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1339 break;
1340
1341 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1342 *pu32 = pThis->u8UseIOApic;
1343 break;
1344
1345 case SYSTEM_INFO_INDEX_HPET_STATUS:
1346 *pu32 = pThis->fUseHpet
1347 ? ( STA_DEVICE_PRESENT_MASK
1348 | STA_DEVICE_ENABLED_MASK
1349 | STA_DEVICE_SHOW_IN_UI_MASK
1350 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1351 : 0;
1352 break;
1353
1354 case SYSTEM_INFO_INDEX_SMC_STATUS:
1355 *pu32 = pThis->fUseSmc
1356 ? ( STA_DEVICE_PRESENT_MASK
1357 | STA_DEVICE_ENABLED_MASK
1358 /* no need to show this device in the UI */
1359 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1360 : 0;
1361 break;
1362
1363 case SYSTEM_INFO_INDEX_FDC_STATUS:
1364 *pu32 = pThis->fUseFdc
1365 ? ( STA_DEVICE_PRESENT_MASK
1366 | STA_DEVICE_ENABLED_MASK
1367 | STA_DEVICE_SHOW_IN_UI_MASK
1368 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1369 : 0;
1370 break;
1371
1372 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1373 *pu32 = pThis->u32NicPciAddress;
1374 break;
1375
1376 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1377 *pu32 = pThis->u32AudioPciAddress;
1378 break;
1379
1380 case SYSTEM_INFO_INDEX_POWER_STATES:
1381 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1382 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1383 *pu32 |= RT_BIT(1);
1384 if (pThis->fS4Enabled)
1385 *pu32 |= RT_BIT(4);
1386 break;
1387
1388 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1389 *pu32 = pThis->u32IocPciAddress;
1390 break;
1391
1392 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1393 *pu32 = pThis->u32HbcPciAddress;
1394 break;
1395
1396 case SYSTEM_INFO_INDEX_PCI_BASE:
1397 /** @todo couldn't MCFG be in 64-bit range? */
1398 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1399 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1400 break;
1401
1402 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1403 /** @todo couldn't MCFG be in 64-bit range? */
1404 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1405 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1406 break;
1407
1408 case SYSTEM_INFO_INDEX_RTC_STATUS:
1409 *pu32 = pThis->fShowRtc
1410 ? ( STA_DEVICE_PRESENT_MASK
1411 | STA_DEVICE_ENABLED_MASK
1412 | STA_DEVICE_SHOW_IN_UI_MASK
1413 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1414 : 0;
1415 break;
1416
1417 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1418 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1419 {
1420 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1421 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1422 }
1423 else
1424 {
1425 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1426 pThis->idCpuLockCheck);
1427 /* Always return locked status just to be safe */
1428 *pu32 = 1;
1429 }
1430 break;
1431
1432 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1433 *pu32 = pThis->u32CpuEventType;
1434 break;
1435
1436 case SYSTEM_INFO_INDEX_CPU_EVENT:
1437 *pu32 = pThis->u32CpuEvent;
1438 break;
1439
1440 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1441 *pu32 = pThis->uSerial0IoPortBase;
1442 break;
1443
1444 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1445 *pu32 = pThis->uSerial0Irq;
1446 break;
1447
1448 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1449 *pu32 = pThis->uSerial1IoPortBase;
1450 break;
1451
1452 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1453 *pu32 = pThis->uSerial1Irq;
1454 break;
1455
1456 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1457 *pu32 = pThis->uSerial2IoPortBase;
1458 break;
1459
1460 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1461 *pu32 = pThis->uSerial2Irq;
1462 break;
1463
1464 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1465 *pu32 = pThis->uSerial3IoPortBase;
1466 break;
1467
1468 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1469 *pu32 = pThis->uSerial3Irq;
1470 break;
1471
1472 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1473 *pu32 = pThis->uParallel0IoPortBase;
1474 break;
1475
1476 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1477 *pu32 = pThis->uParallel0Irq;
1478 break;
1479
1480 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1481 *pu32 = pThis->uParallel1IoPortBase;
1482 break;
1483
1484 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1485 *pu32 = pThis->uParallel1Irq;
1486 break;
1487
1488 case SYSTEM_INFO_INDEX_END:
1489 /** @todo why isn't this setting any output value? */
1490 break;
1491
1492 /* Solaris 9 tries to read from this index */
1493 case SYSTEM_INFO_INDEX_INVALID:
1494 *pu32 = 0;
1495 break;
1496
1497 default:
1498 *pu32 = UINT32_MAX;
1499 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1500 break;
1501 }
1502
1503 DEVACPI_UNLOCK(pThis);
1504 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%d) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, rc));
1505 return rc;
1506}
1507
1508/**
1509 * @callback_method_impl{FNIOMIOPORTOUT, System info data}
1510 */
1511PDMBOTHCBDECL(int) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1512{
1513 ACPIState *pThis = (ACPIState *)pvUser;
1514 if (cb != 4)
1515 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1516
1517 DEVACPI_LOCK_R3(pThis);
1518 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, pThis->uSystemInfoIndex));
1519
1520 int rc = VINF_SUCCESS;
1521 switch (pThis->uSystemInfoIndex)
1522 {
1523 case SYSTEM_INFO_INDEX_INVALID:
1524 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1525 pThis->u8IndexShift = 0;
1526 break;
1527
1528 case SYSTEM_INFO_INDEX_VALID:
1529 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1530 pThis->u8IndexShift = 2;
1531 break;
1532
1533 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1534 pThis->idCpuLockCheck = u32;
1535 break;
1536
1537 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1538 if (u32 < pThis->cCpus)
1539 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1540 else
1541 LogRel(("ACPI: CPU %u does not exist\n", u32));
1542 break;
1543
1544 default:
1545 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1546 break;
1547 }
1548
1549 DEVACPI_UNLOCK(pThis);
1550 return rc;
1551}
1552
1553/**
1554 * @callback_method_impl{FNIOMIOPORTIN, PM1a Enable}
1555 */
1556PDMBOTHCBDECL(int) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1557{
1558 NOREF(pDevIns); NOREF(Port);
1559 if (cb != 2)
1560 return VERR_IOM_IOPORT_UNUSED;
1561
1562 ACPIState *pThis = (ACPIState *)pvUser;
1563 DEVACPI_LOCK_R3(pThis);
1564
1565 *pu32 = pThis->pm1a_en;
1566
1567 DEVACPI_UNLOCK(pThis);
1568 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1569 return VINF_SUCCESS;
1570}
1571
1572/**
1573 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Enable}
1574 */
1575PDMBOTHCBDECL(int) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1576{
1577 if (cb != 2 && cb != 4)
1578 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1579
1580 ACPIState *pThis = (ACPIState *)pvUser;
1581 DEVACPI_LOCK_R3(pThis);
1582
1583 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1584 u32 &= ~(RSR_EN | IGN_EN);
1585 u32 &= 0xffff;
1586 apicUpdatePm1a(pThis, pThis->pm1a_sts, u32);
1587
1588 DEVACPI_UNLOCK(pThis);
1589 return VINF_SUCCESS;
1590}
1591
1592/**
1593 * @callback_method_impl{FNIOMIOPORTIN, PM1a Status}
1594 */
1595PDMBOTHCBDECL(int) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1596{
1597 if (cb != 2)
1598 {
1599 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1600 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1601 }
1602
1603 ACPIState *pThis = (ACPIState *)pvUser;
1604 DEVACPI_LOCK_R3(pThis);
1605
1606 *pu32 = pThis->pm1a_sts;
1607
1608 DEVACPI_UNLOCK(pThis);
1609 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1610 return VINF_SUCCESS;
1611}
1612
1613/**
1614 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Status}
1615 */
1616PDMBOTHCBDECL(int) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1617{
1618 if (cb != 2 && cb != 4)
1619 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1620
1621 ACPIState *pThis = (ACPIState *)pvUser;
1622 DEVACPI_LOCK_R3(pThis);
1623
1624 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1625 u32 &= 0xffff;
1626 if (u32 & PWRBTN_STS)
1627 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1628 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1629 apicUpdatePm1a(pThis, u32, pThis->pm1a_en);
1630
1631 DEVACPI_UNLOCK(pThis);
1632 return VINF_SUCCESS;
1633}
1634
1635/**
1636 * @callback_method_impl{FNIOMIOPORTIN, PM1a Control}
1637 */
1638PDMBOTHCBDECL(int) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1639{
1640 if (cb != 2)
1641 {
1642 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1643 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1644 }
1645
1646 ACPIState *pThis = (ACPIState *)pvUser;
1647 DEVACPI_LOCK_R3(pThis);
1648
1649 *pu32 = pThis->pm1a_ctl;
1650
1651 DEVACPI_UNLOCK(pThis);
1652 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1653 return VINF_SUCCESS;
1654}
1655
1656/**
1657 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Control}
1658 */
1659PDMBOTHCBDECL(int) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1660{
1661 if (cb != 2 && cb != 4)
1662 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1663
1664 ACPIState *pThis = (ACPIState *)pvUser;
1665 DEVACPI_LOCK_R3(pThis);
1666
1667 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1668 u32 &= 0xffff;
1669 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1670
1671 int rc = VINF_SUCCESS;
1672 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1673 if (uSleepState != pThis->uSleepState)
1674 {
1675 pThis->uSleepState = uSleepState;
1676 switch (uSleepState)
1677 {
1678 case 0x00: /* S0 */
1679 break;
1680
1681 case 0x01: /* S1 */
1682 if (pThis->fS1Enabled)
1683 {
1684 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1685 rc = acpiR3DoSleep(pThis);
1686 break;
1687 }
1688 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1689 /* fall thru */
1690
1691 case 0x04: /* S4 */
1692 if (pThis->fS4Enabled)
1693 {
1694 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1695 rc = acpiR3DoPowerOff(pThis);/* Same behavior as S5 */
1696 break;
1697 }
1698 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1699 /* fall thru */
1700
1701 case 0x05: /* S5 */
1702 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1703 rc = acpiR3DoPowerOff(pThis);
1704 break;
1705
1706 default:
1707 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1708 break;
1709 }
1710 }
1711
1712 DEVACPI_UNLOCK(pThis);
1713 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", rc));
1714 return rc;
1715}
1716
1717#endif /* IN_RING3 */
1718
1719/**
1720 * @callback_method_impl{FNIOMIOPORTIN, PMTMR}
1721 *
1722 * @remarks Only I/O port currently implemented in all contexts.
1723 */
1724PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1725{
1726 if (cb != 4)
1727 return VERR_IOM_IOPORT_UNUSED;
1728
1729 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1730
1731 /*
1732 * We use the clock lock to serialize access to u64PmTimerInitial and to
1733 * make sure we get a reliable time from the clock
1734 * as well as and to prevent uPmTimerVal from being updated during read.
1735 */
1736
1737 int rc = TMTimerLock(pThis->CTX_SUFF(pPmTimer), VINF_IOM_R3_IOPORT_READ);
1738 if (rc != VINF_SUCCESS)
1739 return rc;
1740
1741 rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1742 if (rc != VINF_SUCCESS)
1743 {
1744 TMTimerUnlock(pThis->CTX_SUFF(pPmTimer));
1745 return rc;
1746 }
1747
1748 uint64_t u64Now = TMTimerGet(pThis->CTX_SUFF(pPmTimer));
1749 acpiPmTimerUpdate(pThis, u64Now);
1750 *pu32 = pThis->uPmTimerVal;
1751
1752 DEVACPI_UNLOCK(pThis);
1753 TMTimerUnlock(pThis->CTX_SUFF(pPmTimer));
1754
1755 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1756 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1757
1758 NOREF(pvUser); NOREF(Port);
1759 return rc;
1760}
1761
1762#ifdef IN_RING3
1763
1764/**
1765 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Status}
1766 */
1767PDMBOTHCBDECL(int) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1768{
1769 if (cb != 1)
1770 {
1771 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1772 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1773 }
1774
1775 ACPIState *pThis = (ACPIState *)pvUser;
1776 DEVACPI_LOCK_R3(pThis);
1777
1778 *pu32 = pThis->gpe0_sts & 0xff;
1779
1780 DEVACPI_UNLOCK(pThis);
1781 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1782 return VINF_SUCCESS;
1783}
1784
1785/**
1786 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Status}
1787 */
1788PDMBOTHCBDECL(int) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1789{
1790 if (cb != 1)
1791 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1792
1793 ACPIState *pThis = (ACPIState *)pvUser;
1794 DEVACPI_LOCK_R3(pThis);
1795
1796 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1797 u32 = pThis->gpe0_sts & ~u32;
1798 apicR3UpdateGpe0(pThis, u32, pThis->gpe0_en);
1799
1800 DEVACPI_UNLOCK(pThis);
1801 return VINF_SUCCESS;
1802}
1803
1804/**
1805 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Enable}
1806 */
1807PDMBOTHCBDECL(int) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1808{
1809 if (cb != 1)
1810 {
1811 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1812 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1813 }
1814
1815 ACPIState *pThis = (ACPIState *)pvUser;
1816 DEVACPI_LOCK_R3(pThis);
1817
1818 *pu32 = pThis->gpe0_en & 0xff;
1819
1820 DEVACPI_UNLOCK(pThis);
1821 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1822 return VINF_SUCCESS;
1823}
1824
1825/**
1826 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Enable}
1827 */
1828PDMBOTHCBDECL(int) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1829{
1830 if (cb != 1)
1831 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1832
1833 ACPIState *pThis = (ACPIState *)pvUser;
1834 DEVACPI_LOCK_R3(pThis);
1835
1836 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1837 apicR3UpdateGpe0(pThis, pThis->gpe0_sts, u32);
1838
1839 DEVACPI_UNLOCK(pThis);
1840 return VINF_SUCCESS;
1841}
1842
1843/**
1844 * @callback_method_impl{FNIOMIOPORTOUT, SMI_CMD}
1845 */
1846PDMBOTHCBDECL(int) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1847{
1848 Log(("acpiR3SmiWrite %#x\n", u32));
1849 if (cb != 1)
1850 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1851
1852 ACPIState *pThis = (ACPIState *)pvUser;
1853 DEVACPI_LOCK_R3(pThis);
1854
1855 if (u32 == ACPI_ENABLE)
1856 pThis->pm1a_ctl |= SCI_EN;
1857 else if (u32 == ACPI_DISABLE)
1858 pThis->pm1a_ctl &= ~SCI_EN;
1859 else
1860 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1861
1862 DEVACPI_UNLOCK(pThis);
1863 return VINF_SUCCESS;
1864}
1865
1866/**
1867 * @{FNIOMIOPORTOUT, ACPI_RESET_BLK}
1868 */
1869PDMBOTHCBDECL(int) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1870{
1871 Log(("acpiR3ResetWrite: %#x\n", u32));
1872 NOREF(pvUser);
1873 if (cb != 1)
1874 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1875
1876 /* No state locking required. */
1877 int rc = VINF_SUCCESS;
1878 if (u32 == ACPI_RESET_REG_VAL)
1879 {
1880 LogRel(("ACPI: Reset initiated by ACPI\n"));
1881 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
1882 }
1883 else
1884 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1885
1886 return rc;
1887}
1888
1889# ifdef DEBUG_ACPI
1890
1891/**
1892 * @callback_method_impl{FNIOMIOPORTOUT, Debug hex value logger}
1893 */
1894PDMBOTHCBDECL(int) acpiR3DhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1895{
1896 NOREF(pvUser);
1897 switch (cb)
1898 {
1899 case 1:
1900 Log(("%#x\n", u32 & 0xff));
1901 break;
1902 case 2:
1903 Log(("%#6x\n", u32 & 0xffff));
1904 break;
1905 case 4:
1906 Log(("%#10x\n", u32));
1907 break;
1908 default:
1909 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1910 }
1911 return VINF_SUCCESS;
1912}
1913
1914/**
1915 * @callback_method_impl{FNIOMIOPORTOUT, Debug char logger}
1916 */
1917PDMBOTHCBDECL(int) acpiR3DchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1918{
1919 NOREF(pvUser);
1920 switch (cb)
1921 {
1922 case 1:
1923 Log(("%c", u32 & 0xff));
1924 break;
1925 default:
1926 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1927 }
1928 return VINF_SUCCESS;
1929}
1930
1931# endif /* DEBUG_ACPI */
1932
1933/**
1934 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
1935 *
1936 * @param pThis The ACPI instance.
1937 */
1938static void acpiR3PmPCIBIOSFake(ACPIState *pThis)
1939{
1940 pThis->dev.abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
1941 pThis->dev.abConfig[PMBA+1] = pThis->uPmIoPortBase >> 8;
1942 pThis->dev.abConfig[PMBA+2] = 0x00;
1943 pThis->dev.abConfig[PMBA+3] = 0x00;
1944}
1945
1946/**
1947 * Used to calculate the value of a PM I/O port.
1948 *
1949 * @returns The actual I/O port value.
1950 * @param pThis The ACPI instance.
1951 * @param offset The offset into the I/O space, or -1 if invalid.
1952 */
1953static RTIOPORT acpiR3CalcPmPort(ACPIState *pThis, int32_t offset)
1954{
1955 Assert(pThis->uPmIoPortBase != 0);
1956
1957 if (offset == -1)
1958 return 0;
1959
1960 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
1961}
1962
1963/**
1964 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to register the PM1a, PM
1965 * timer and GPE0 I/O ports.
1966 *
1967 * @returns VBox status code.
1968 * @param pThis The ACPI instance.
1969 */
1970static int acpiR3RegisterPmHandlers(ACPIState *pThis)
1971{
1972 if (pThis->uPmIoPortBase == 0)
1973 return VINF_SUCCESS;
1974
1975#define R(offset, cnt, writer, reader, description) \
1976 do { \
1977 int rc = PDMDevHlpIOPortRegister(pThis->pDevInsR3, acpiR3CalcPmPort(pThis, offset), cnt, pThis, writer, reader, \
1978 NULL, NULL, description); \
1979 if (RT_FAILURE(rc)) \
1980 return rc; \
1981 } while (0)
1982#define L (GPE0_BLK_LEN / 2)
1983
1984 R(PM1a_EVT_OFFSET+2, 1, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, "ACPI PM1a Enable");
1985 R(PM1a_EVT_OFFSET, 1, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, "ACPI PM1a Status");
1986 R(PM1a_CTL_OFFSET, 1, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, "ACPI PM1a Control");
1987 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1988 R(GPE0_OFFSET + L, L, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, "ACPI GPE0 Enable");
1989 R(GPE0_OFFSET, L, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, "ACPI GPE0 Status");
1990#undef L
1991#undef R
1992
1993 /* register RC stuff */
1994 if (pThis->fGCEnabled)
1995 {
1996 int rc = PDMDevHlpIOPortRegisterRC(pThis->pDevInsR3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
1997 1, 0, NULL, "acpiPMTmrRead",
1998 NULL, NULL, "ACPI PM Timer");
1999 AssertRCReturn(rc, rc);
2000 }
2001
2002 /* register R0 stuff */
2003 if (pThis->fR0Enabled)
2004 {
2005 int rc = PDMDevHlpIOPortRegisterR0(pThis->pDevInsR3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
2006 1, 0, NULL, "acpiPMTmrRead",
2007 NULL, NULL, "ACPI PM Timer");
2008 AssertRCReturn(rc, rc);
2009 }
2010
2011 return VINF_SUCCESS;
2012}
2013
2014/**
2015 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unregister the PM1a, PM
2016 * timer and GPE0 I/O ports.
2017 *
2018 * @returns VBox status code.
2019 * @param pThis The ACPI instance.
2020 */
2021static int acpiR3UnregisterPmHandlers(ACPIState *pThis)
2022{
2023 if (pThis->uPmIoPortBase == 0)
2024 return VINF_SUCCESS;
2025
2026#define U(offset, cnt) \
2027 do { \
2028 int rc = PDMDevHlpIOPortDeregister(pThis->pDevInsR3, acpiR3CalcPmPort(pThis, offset), cnt); \
2029 AssertRCReturn(rc, rc); \
2030 } while (0)
2031#define L (GPE0_BLK_LEN / 2)
2032
2033 U(PM1a_EVT_OFFSET+2, 1);
2034 U(PM1a_EVT_OFFSET, 1);
2035 U(PM1a_CTL_OFFSET, 1);
2036 U(PM_TMR_OFFSET, 1);
2037 U(GPE0_OFFSET + L, L);
2038 U(GPE0_OFFSET, L);
2039#undef L
2040#undef U
2041
2042 return VINF_SUCCESS;
2043}
2044
2045/**
2046 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2047 * PM1a, PM timer and GPE0 ports.
2048 *
2049 * @returns VBox status code.
2050 *
2051 * @param pThis The ACPI instance.
2052 * @param NewIoPortBase The new base address of the I/O ports.
2053 */
2054static int acpiR3UpdatePmHandlers(ACPIState *pThis, RTIOPORT NewIoPortBase)
2055{
2056 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2057 if (NewIoPortBase != pThis->uPmIoPortBase)
2058 {
2059 int rc = acpiR3UnregisterPmHandlers(pThis);
2060 if (RT_FAILURE(rc))
2061 return rc;
2062
2063 pThis->uPmIoPortBase = NewIoPortBase;
2064
2065 rc = acpiR3RegisterPmHandlers(pThis);
2066 if (RT_FAILURE(rc))
2067 return rc;
2068
2069 /* We have to update FADT table acccording to the new base */
2070 rc = acpiR3PlantTables(pThis);
2071 AssertRC(rc);
2072 if (RT_FAILURE(rc))
2073 return rc;
2074 }
2075
2076 return VINF_SUCCESS;
2077}
2078
2079/**
2080 * @callback_method_impl{FNIOMIOPORTOUT, SMBus}
2081 */
2082PDMBOTHCBDECL(int) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2083{
2084 ACPIState *pThis = (ACPIState *)pvUser;
2085 DEVACPI_LOCK_R3(pThis);
2086
2087 LogFunc(("Port=%#x u32=%#x cb=%u\n", Port, u32, cb));
2088 uint8_t off = Port & 0x000f;
2089 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2090 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2091 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
2092
2093 switch (off)
2094 {
2095 case SMBHSTSTS_OFF:
2096 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2097 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2098 break;
2099 case SMBSLVSTS_OFF:
2100 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2101 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2102 break;
2103 case SMBHSTCNT_OFF:
2104 {
2105 Assert(PDMCritSectIsOwner(&pThis->CritSect));
2106
2107 const bool old_level = acpiSCILevel(pThis);
2108 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2109 if (u32 & SMBHSTCNT_START)
2110 {
2111 /* Start, trigger error as this is a dummy implementation */
2112 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2113 }
2114 if (u32 & SMBHSTCNT_KILL)
2115 {
2116 /* Kill */
2117 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2118 }
2119 const bool new_level = acpiSCILevel(pThis);
2120
2121 LogFunc(("old=%x new=%x\n", old_level, new_level));
2122
2123 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2124 * needs to be implemented later if it ever becomes relevant. */
2125 if (new_level != old_level)
2126 acpiSetIrq(pThis, new_level);
2127 break;
2128 }
2129 case SMBHSTCMD_OFF:
2130 pThis->u8SMBusHstCmd = u32;
2131 break;
2132 case SMBHSTADD_OFF:
2133 pThis->u8SMBusHstAdd = u32;
2134 break;
2135 case SMBHSTDAT0_OFF:
2136 pThis->u8SMBusHstDat0 = u32;
2137 break;
2138 case SMBHSTDAT1_OFF:
2139 pThis->u8SMBusHstDat1 = u32;
2140 break;
2141 case SMBBLKDAT_OFF:
2142 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2143 pThis->u8SMBusBlkIdx++;
2144 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2145 break;
2146 case SMBSLVCNT_OFF:
2147 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2148 break;
2149 case SMBSHDWCMD_OFF:
2150 /* readonly register */
2151 break;
2152 case SMBSLVEVT_OFF:
2153 pThis->u16SMBusSlvEvt = u32;
2154 break;
2155 case SMBSLVDAT_OFF:
2156 /* readonly register */
2157 break;
2158 default:
2159 /* caught by the sanity check above */
2160 ;
2161 }
2162
2163 DEVACPI_UNLOCK(pThis);
2164 return VINF_SUCCESS;
2165}
2166
2167/**
2168 * @callback_method_impl{FNIOMIOPORTIN, SMBus}
2169 */
2170PDMBOTHCBDECL(int) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2171{
2172 RT_NOREF1(pDevIns);
2173 ACPIState *pThis = (ACPIState *)pvUser;
2174 DEVACPI_LOCK_R3(pThis);
2175
2176 int rc = VINF_SUCCESS;
2177 LogFunc(("Port=%#x cb=%u\n", Port, cb));
2178 uint8_t off = Port & 0x000f;
2179 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2180 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2181 return VERR_IOM_IOPORT_UNUSED;
2182
2183 switch (off)
2184 {
2185 case SMBHSTSTS_OFF:
2186 *pu32 = pThis->u8SMBusHstSts;
2187 break;
2188 case SMBSLVSTS_OFF:
2189 *pu32 = pThis->u8SMBusSlvSts;
2190 break;
2191 case SMBHSTCNT_OFF:
2192 pThis->u8SMBusBlkIdx = 0;
2193 *pu32 = pThis->u8SMBusHstCnt;
2194 break;
2195 case SMBHSTCMD_OFF:
2196 *pu32 = pThis->u8SMBusHstCmd;
2197 break;
2198 case SMBHSTADD_OFF:
2199 *pu32 = pThis->u8SMBusHstAdd;
2200 break;
2201 case SMBHSTDAT0_OFF:
2202 *pu32 = pThis->u8SMBusHstDat0;
2203 break;
2204 case SMBHSTDAT1_OFF:
2205 *pu32 = pThis->u8SMBusHstDat1;
2206 break;
2207 case SMBBLKDAT_OFF:
2208 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2209 pThis->u8SMBusBlkIdx++;
2210 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2211 break;
2212 case SMBSLVCNT_OFF:
2213 *pu32 = pThis->u8SMBusSlvCnt;
2214 break;
2215 case SMBSHDWCMD_OFF:
2216 *pu32 = pThis->u8SMBusShdwCmd;
2217 break;
2218 case SMBSLVEVT_OFF:
2219 *pu32 = pThis->u16SMBusSlvEvt;
2220 break;
2221 case SMBSLVDAT_OFF:
2222 *pu32 = pThis->u16SMBusSlvDat;
2223 break;
2224 default:
2225 /* caught by the sanity check above */
2226 rc = VERR_IOM_IOPORT_UNUSED;
2227 }
2228
2229 DEVACPI_UNLOCK(pThis);
2230 LogFunc(("Port=%#x u32=%#x cb=%u rc=%Rrc\n", Port, *pu32, cb, rc));
2231 return rc;
2232}
2233
2234/**
2235 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2236 *
2237 * @param pThis The ACPI instance.
2238 */
2239static void acpiR3SMBusPCIBIOSFake(ACPIState *pThis)
2240{
2241 pThis->dev.abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2242 pThis->dev.abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2243 pThis->dev.abConfig[SMBBA+2] = 0x00;
2244 pThis->dev.abConfig[SMBBA+3] = 0x00;
2245 pThis->dev.abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2246 pThis->dev.abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2247 pThis->dev.abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2248 pThis->dev.abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2249 pThis->dev.abConfig[SMBREV] = 0x00; /* SMBREV */
2250}
2251
2252/**
2253 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2254 *
2255 * @param pThis The ACPI instance.
2256 */
2257static void acpiR3SMBusResetDevice(ACPIState *pThis)
2258{
2259 pThis->u8SMBusHstSts = 0x00;
2260 pThis->u8SMBusSlvSts = 0x00;
2261 pThis->u8SMBusHstCnt = 0x00;
2262 pThis->u8SMBusHstCmd = 0x00;
2263 pThis->u8SMBusHstAdd = 0x00;
2264 pThis->u8SMBusHstDat0 = 0x00;
2265 pThis->u8SMBusHstDat1 = 0x00;
2266 pThis->u8SMBusSlvCnt = 0x00;
2267 pThis->u8SMBusShdwCmd = 0x00;
2268 pThis->u16SMBusSlvEvt = 0x0000;
2269 pThis->u16SMBusSlvDat = 0x0000;
2270 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2271 pThis->u8SMBusBlkIdx = 0;
2272}
2273
2274/**
2275 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to register the SMBus ports.
2276 *
2277 * @returns VBox status code.
2278 * @param pThis The ACPI instance.
2279 */
2280static int acpiR3RegisterSMBusHandlers(ACPIState *pThis)
2281{
2282 int rc = VINF_SUCCESS;
2283
2284 if (pThis->uSMBusIoPortBase == 0)
2285 return VINF_SUCCESS;
2286
2287 rc = PDMDevHlpIOPortRegister(pThis->pDevInsR3, pThis->uSMBusIoPortBase, 16, pThis, acpiR3SMBusWrite, acpiR3SMBusRead, NULL, NULL, "SMBus");
2288 if (RT_FAILURE(rc))
2289 return rc;
2290
2291 return VINF_SUCCESS;
2292}
2293
2294/**
2295 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unregister the SMBus ports.
2296 *
2297 * @returns VBox status code.
2298 * @param pThis The ACPI instance.
2299 */
2300static int acpiR3UnregisterSMBusHandlers(ACPIState *pThis)
2301{
2302 if (pThis->uSMBusIoPortBase == 0)
2303 return VINF_SUCCESS;
2304
2305 int rc = PDMDevHlpIOPortDeregister(pThis->pDevInsR3, pThis->uSMBusIoPortBase, 16);
2306 AssertRCReturn(rc, rc);
2307
2308 return VINF_SUCCESS;
2309}
2310
2311/**
2312 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2313 * SMBus ports.
2314 *
2315 * @returns VBox status code.
2316 *
2317 * @param pThis The ACPI instance.
2318 * @param NewIoPortBase The new base address of the I/O ports.
2319 */
2320static int acpiR3UpdateSMBusHandlers(ACPIState *pThis, RTIOPORT NewIoPortBase)
2321{
2322 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2323 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2324 {
2325 int rc = acpiR3UnregisterSMBusHandlers(pThis);
2326 if (RT_FAILURE(rc))
2327 return rc;
2328
2329 pThis->uSMBusIoPortBase = NewIoPortBase;
2330
2331 rc = acpiR3RegisterSMBusHandlers(pThis);
2332 if (RT_FAILURE(rc))
2333 return rc;
2334
2335#if 0 /* is there an FADT table entry for the SMBus base? */
2336 /* We have to update FADT table acccording to the new base */
2337 rc = acpiR3PlantTables(pThis);
2338 AssertRC(rc);
2339 if (RT_FAILURE(rc))
2340 return rc;
2341#endif
2342 }
2343
2344 return VINF_SUCCESS;
2345}
2346
2347
2348/**
2349 * Saved state structure description, version 4.
2350 */
2351static const SSMFIELD g_AcpiSavedStateFields4[] =
2352{
2353 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2354 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2355 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2356 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2357 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2358 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2359 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2360 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2361 SSMFIELD_ENTRY(ACPIState, u64RamSize),
2362 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2363 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
2364 SSMFIELD_ENTRY(ACPIState, uSleepState),
2365 SSMFIELD_ENTRY_TERM()
2366};
2367
2368/**
2369 * Saved state structure description, version 5.
2370 */
2371static const SSMFIELD g_AcpiSavedStateFields5[] =
2372{
2373 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2374 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2375 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2376 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2377 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2378 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2379 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2380 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2381 SSMFIELD_ENTRY(ACPIState, uSleepState),
2382 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2383 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2384 SSMFIELD_ENTRY_TERM()
2385};
2386
2387/**
2388 * Saved state structure description, version 6.
2389 */
2390static const SSMFIELD g_AcpiSavedStateFields6[] =
2391{
2392 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2393 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2394 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2395 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2396 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2397 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2398 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2399 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2400 SSMFIELD_ENTRY(ACPIState, uSleepState),
2401 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2402 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2403 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2404 SSMFIELD_ENTRY_TERM()
2405};
2406
2407/**
2408 * Saved state structure description, version 7.
2409 */
2410static const SSMFIELD g_AcpiSavedStateFields7[] =
2411{
2412 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2413 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2414 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2415 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2416 SSMFIELD_ENTRY(ACPIState, uPmTimerVal),
2417 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2418 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2419 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2420 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2421 SSMFIELD_ENTRY(ACPIState, uSleepState),
2422 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2423 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2424 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2425 SSMFIELD_ENTRY_TERM()
2426};
2427
2428/**
2429 * Saved state structure description, version 8.
2430 */
2431static const SSMFIELD g_AcpiSavedStateFields8[] =
2432{
2433 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2434 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2435 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2436 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2437 SSMFIELD_ENTRY(ACPIState, uPmTimerVal),
2438 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2439 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2440 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2441 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2442 SSMFIELD_ENTRY(ACPIState, uSleepState),
2443 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2444 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2445 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2446 SSMFIELD_ENTRY(ACPIState, uSMBusIoPortBase),
2447 SSMFIELD_ENTRY(ACPIState, u8SMBusHstSts),
2448 SSMFIELD_ENTRY(ACPIState, u8SMBusSlvSts),
2449 SSMFIELD_ENTRY(ACPIState, u8SMBusHstCnt),
2450 SSMFIELD_ENTRY(ACPIState, u8SMBusHstCmd),
2451 SSMFIELD_ENTRY(ACPIState, u8SMBusHstAdd),
2452 SSMFIELD_ENTRY(ACPIState, u8SMBusHstDat0),
2453 SSMFIELD_ENTRY(ACPIState, u8SMBusHstDat1),
2454 SSMFIELD_ENTRY(ACPIState, u8SMBusSlvCnt),
2455 SSMFIELD_ENTRY(ACPIState, u8SMBusShdwCmd),
2456 SSMFIELD_ENTRY(ACPIState, u16SMBusSlvEvt),
2457 SSMFIELD_ENTRY(ACPIState, u16SMBusSlvDat),
2458 SSMFIELD_ENTRY(ACPIState, au8SMBusBlkDat),
2459 SSMFIELD_ENTRY(ACPIState, u8SMBusBlkIdx),
2460 SSMFIELD_ENTRY_TERM()
2461};
2462
2463/**
2464 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2465 */
2466static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2467{
2468 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2469 return SSMR3PutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2470}
2471
2472/**
2473 * @callback_method_impl{FNSSMDEVLOADEXEC}
2474 */
2475static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2476{
2477 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2478 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2479
2480 /*
2481 * Unregister PM handlers, will register with actual base after state
2482 * successfully loaded.
2483 */
2484 int rc = acpiR3UnregisterPmHandlers(pThis);
2485 if (RT_FAILURE(rc))
2486 return rc;
2487
2488 /*
2489 * Unregister SMBus handlers, will register with actual base after state
2490 * successfully loaded.
2491 */
2492 rc = acpiR3UnregisterSMBusHandlers(pThis);
2493 if (RT_FAILURE(rc))
2494 return rc;
2495 acpiR3SMBusResetDevice(pThis);
2496
2497 switch (uVersion)
2498 {
2499 case 4:
2500 rc = SSMR3GetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2501 break;
2502 case 5:
2503 rc = SSMR3GetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2504 break;
2505 case 6:
2506 rc = SSMR3GetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2507 break;
2508 case 7:
2509 rc = SSMR3GetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2510 break;
2511 case 8:
2512 rc = SSMR3GetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2513 break;
2514 default:
2515 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2516 break;
2517 }
2518 if (RT_SUCCESS(rc))
2519 {
2520 rc = acpiR3RegisterPmHandlers(pThis);
2521 if (RT_FAILURE(rc))
2522 return rc;
2523 rc = acpiR3RegisterSMBusHandlers(pThis);
2524 if (RT_FAILURE(rc))
2525 return rc;
2526 rc = acpiR3FetchBatteryStatus(pThis);
2527 if (RT_FAILURE(rc))
2528 return rc;
2529 rc = acpiR3FetchBatteryInfo(pThis);
2530 if (RT_FAILURE(rc))
2531 return rc;
2532 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);
2533 DEVACPI_LOCK_R3(pThis);
2534 uint64_t u64Now = TMTimerGet(pThis->pPmTimerR3);
2535 /* The interrupt may be incorrectly re-generated
2536 * if the state is restored from versions < 7
2537 */
2538 acpiPmTimerUpdate(pThis, u64Now);
2539 acpiR3PmTimerReset(pThis, u64Now);
2540 DEVACPI_UNLOCK(pThis);
2541 TMTimerUnlock(pThis->pPmTimerR3);
2542 }
2543 return rc;
2544}
2545
2546/**
2547 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2548 */
2549static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2550{
2551 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IBase);
2552 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2553 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThis->IACPIPort);
2554 return NULL;
2555}
2556
2557/**
2558 * Calculate the check sum for some ACPI data before planting it.
2559 *
2560 * All the bytes must add up to 0.
2561 *
2562 * @returns check sum.
2563 * @param pvSrc What to check sum.
2564 * @param cbData The amount of data to checksum.
2565 */
2566static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2567{
2568 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2569 uint8_t uSum = 0;
2570 for (size_t i = 0; i < cbData; ++i)
2571 uSum += pbSrc[i];
2572 return -uSum;
2573}
2574
2575/**
2576 * Prepare a ACPI table header.
2577 */
2578static void acpiR3PrepareHeader(ACPIState *pThis, ACPITBLHEADER *header,
2579 const char au8Signature[4],
2580 uint32_t u32Length, uint8_t u8Revision)
2581{
2582 memcpy(header->au8Signature, au8Signature, 4);
2583 header->u32Length = RT_H2LE_U32(u32Length);
2584 header->u8Revision = u8Revision;
2585 memcpy(header->au8OemId, pThis->au8OemId, 6);
2586 memcpy(header->au8OemTabId, "VBOX", 4);
2587 memcpy(header->au8OemTabId+4, au8Signature, 4);
2588 header->u32OemRevision = RT_H2LE_U32(1);
2589 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2590 header->u32CreatorRev = pThis->u32CreatorRev;
2591}
2592
2593/**
2594 * Initialize a generic address structure (ACPIGENADDR).
2595 */
2596static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2597 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2598 uint8_t u8AccessSize, uint64_t u64Address)
2599{
2600 g->u8AddressSpaceId = u8AddressSpaceId;
2601 g->u8RegisterBitWidth = u8RegisterBitWidth;
2602 g->u8RegisterBitOffset = u8RegisterBitOffset;
2603 g->u8AccessSize = u8AccessSize;
2604 g->u64Address = RT_H2LE_U64(u64Address);
2605}
2606
2607/**
2608 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2609 */
2610DECLINLINE(void) acpiR3PhysCopy(ACPIState *pThis, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2611{
2612 PDMDevHlpPhysWrite(pThis->pDevInsR3, GCPhys32Dst, pvSrc, cbToCopy);
2613}
2614
2615/**
2616 * Plant the Differentiated System Description Table (DSDT).
2617 */
2618static void acpiR3SetupDsdt(ACPIState *pThis, RTGCPHYS32 GCPhys32, void *pvPtr, size_t cbDsdt)
2619{
2620 acpiR3PhysCopy(pThis, GCPhys32, pvPtr, cbDsdt);
2621}
2622
2623/**
2624 * Plan the Secondary System Description Table (SSDT).
2625 */
2626static void acpiR3SetupSsdt(ACPIState *pThis, RTGCPHYS32 addr,
2627 void* pPtr, size_t uSsdtLen)
2628{
2629 acpiR3PhysCopy(pThis, addr, pPtr, uSsdtLen);
2630}
2631
2632/**
2633 * Plant the Firmware ACPI Control Structure (FACS).
2634 */
2635static void acpiR3SetupFacs(ACPIState *pThis, RTGCPHYS32 addr)
2636{
2637 ACPITBLFACS facs;
2638
2639 memset(&facs, 0, sizeof(facs));
2640 memcpy(facs.au8Signature, "FACS", 4);
2641 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2642 facs.u32HWSignature = RT_H2LE_U32(0);
2643 facs.u32FWVector = RT_H2LE_U32(0);
2644 facs.u32GlobalLock = RT_H2LE_U32(0);
2645 facs.u32Flags = RT_H2LE_U32(0);
2646 facs.u64X_FWVector = RT_H2LE_U64(0);
2647 facs.u8Version = 1;
2648
2649 acpiR3PhysCopy(pThis, addr, (const uint8_t *)&facs, sizeof(facs));
2650}
2651
2652/**
2653 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2654 */
2655static void acpiR3SetupFadt(ACPIState *pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2656 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2657{
2658 ACPITBLFADT fadt;
2659
2660 /* First the ACPI version 2+ version of the structure. */
2661 memset(&fadt, 0, sizeof(fadt));
2662 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2663 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2664 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2665 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2666 fadt.u8PreferredPMProfile = 0; /* unspecified */
2667 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2668 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2669 fadt.u8AcpiEnable = ACPI_ENABLE;
2670 fadt.u8AcpiDisable = ACPI_DISABLE;
2671 fadt.u8S4BIOSReq = 0;
2672 fadt.u8PStateCnt = 0;
2673 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2674 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2675 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2676 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2677 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2678 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2679 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2680 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2681 fadt.u8PM1EVTLEN = 4;
2682 fadt.u8PM1CTLLEN = 2;
2683 fadt.u8PM2CTLLEN = 0;
2684 fadt.u8PMTMLEN = 4;
2685 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2686 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2687 fadt.u8GPE1BASE = GPE1_BASE;
2688 fadt.u8CSTCNT = 0;
2689 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2690 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2691 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2692 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2693 fadt.u8DutyOffset = 0;
2694 fadt.u8DutyWidth = 0;
2695 fadt.u8DayAlarm = 0;
2696 fadt.u8MonAlarm = 0;
2697 fadt.u8Century = 0;
2698 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2699 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2700 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2701 | FADT_FL_FIX_RTC
2702 | FADT_FL_TMR_VAL_EXT
2703 | FADT_FL_RESET_REG_SUP);
2704
2705 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2706 if (pThis->fCpuHotPlug)
2707 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2708
2709 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2710 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2711 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2712 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2713 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2714 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2715 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2716 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2717 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2718 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2719 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2720 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2721 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2722 acpiR3PhysCopy(pThis, GCPhysAcpi2, &fadt, sizeof(fadt));
2723
2724 /* Now the ACPI 1.0 version. */
2725 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2726 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2727 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2728 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2729 acpiR3PhysCopy(pThis, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2730}
2731
2732/**
2733 * Plant the root System Description Table.
2734 *
2735 * The RSDT and XSDT tables are basically identical. The only difference is 32
2736 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2737 * ACPI 2.0 and up.
2738 */
2739static int acpiR3SetupRsdt(ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2740{
2741 ACPITBLRSDT *rsdt;
2742 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2743
2744 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2745 if (!rsdt)
2746 return PDMDEV_SET_ERROR(pThis->pDevInsR3, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2747
2748 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2749 for (unsigned int i = 0; i < nb_entries; ++i)
2750 {
2751 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2752 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2753 }
2754 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2755 acpiR3PhysCopy(pThis, addr, rsdt, size);
2756 RTMemFree(rsdt);
2757 return VINF_SUCCESS;
2758}
2759
2760/**
2761 * Plant the Extended System Description Table.
2762 */
2763static int acpiR3SetupXsdt(ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2764{
2765 ACPITBLXSDT *xsdt;
2766 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2767
2768 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
2769 if (!xsdt)
2770 return VERR_NO_TMP_MEMORY;
2771
2772 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
2773
2774 if (pThis->fUseCust)
2775 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2776
2777 for (unsigned int i = 0; i < nb_entries; ++i)
2778 {
2779 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2780 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2781 }
2782 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, size);
2783 acpiR3PhysCopy(pThis, addr, xsdt, size);
2784 RTMemFree(xsdt);
2785 return VINF_SUCCESS;
2786}
2787
2788/**
2789 * Plant the Root System Description Pointer (RSDP).
2790 */
2791static void acpiR3SetupRsdp(ACPIState *pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2792{
2793 memset(rsdp, 0, sizeof(*rsdp));
2794
2795 /* ACPI 1.0 part (RSDT) */
2796 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2797 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2798 rsdp->u8Revision = ACPI_REVISION;
2799 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2800 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2801
2802 /* ACPI 2.0 part (XSDT) */
2803 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2804 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2805 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2806}
2807
2808/**
2809 * Multiple APIC Description Table.
2810 *
2811 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2812 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2813 * use regular C structure and proxy to raw memory instead.
2814 */
2815class AcpiTableMadt
2816{
2817 /**
2818 * All actual data stored in dynamically allocated memory pointed by this field.
2819 */
2820 uint8_t *m_pbData;
2821 /**
2822 * Number of CPU entries in this MADT.
2823 */
2824 uint32_t m_cCpus;
2825
2826 /**
2827 * Number of interrupt overrides.
2828 */
2829 uint32_t m_cIsos;
2830
2831public:
2832 /**
2833 * Address of ACPI header
2834 */
2835 inline ACPITBLHEADER *header_addr(void) const
2836 {
2837 return (ACPITBLHEADER *)m_pbData;
2838 }
2839
2840 /**
2841 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2842 * although address is the same for all of them.
2843 */
2844 inline uint32_t *u32LAPIC_addr(void) const
2845 {
2846 return (uint32_t *)(header_addr() + 1);
2847 }
2848
2849 /**
2850 * Address of APIC flags
2851 */
2852 inline uint32_t *u32Flags_addr(void) const
2853 {
2854 return (uint32_t *)(u32LAPIC_addr() + 1);
2855 }
2856
2857 /**
2858 * Address of ISO description
2859 */
2860 inline ACPITBLISO *ISO_addr(void) const
2861 {
2862 return (ACPITBLISO *)(u32Flags_addr() + 1);
2863 }
2864
2865 /**
2866 * Address of per-CPU LAPIC descriptions
2867 */
2868 inline ACPITBLLAPIC *LApics_addr(void) const
2869 {
2870 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2871 }
2872
2873 /**
2874 * Address of IO APIC description
2875 */
2876 inline ACPITBLIOAPIC *IOApic_addr(void) const
2877 {
2878 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2879 }
2880
2881 /**
2882 * Size of MADT.
2883 * Note that this function assumes IOApic to be the last field in structure.
2884 */
2885 inline uint32_t size(void) const
2886 {
2887 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2888 }
2889
2890 /**
2891 * Raw data of MADT.
2892 */
2893 inline const uint8_t *data(void) const
2894 {
2895 return m_pbData;
2896 }
2897
2898 /**
2899 * Size of MADT for given ACPI config, useful to compute layout.
2900 */
2901 static uint32_t sizeFor(ACPIState *pThis, uint32_t cIsos)
2902 {
2903 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2904 }
2905
2906 /*
2907 * Constructor, only works in Ring 3, doesn't look like a big deal.
2908 */
2909 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2910 {
2911 m_cCpus = cCpus;
2912 m_cIsos = cIsos;
2913 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2914 uint32_t cb = size();
2915 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2916 }
2917
2918 ~AcpiTableMadt()
2919 {
2920 RTMemFree(m_pbData);
2921 }
2922};
2923
2924
2925/**
2926 * Plant the Multiple APIC Description Table (MADT).
2927 *
2928 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
2929 *
2930 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
2931 */
2932static void acpiR3SetupMadt(ACPIState *pThis, RTGCPHYS32 addr)
2933{
2934 uint16_t cpus = pThis->cCpus;
2935 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
2936
2937 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
2938
2939 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
2940 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
2941
2942 /* LAPICs records */
2943 ACPITBLLAPIC* lapic = madt.LApics_addr();
2944 for (uint16_t i = 0; i < cpus; i++)
2945 {
2946 lapic->u8Type = 0;
2947 lapic->u8Length = sizeof(ACPITBLLAPIC);
2948 lapic->u8ProcId = i;
2949 /** Must match numbering convention in MPTABLES */
2950 lapic->u8ApicId = i;
2951 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
2952 lapic++;
2953 }
2954
2955 /* IO-APIC record */
2956 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
2957 ioapic->u8Type = 1;
2958 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
2959 /** Must match MP tables ID */
2960 ioapic->u8IOApicId = cpus;
2961 ioapic->u8Reserved = 0;
2962 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
2963 ioapic->u32GSIB = RT_H2LE_U32(0);
2964
2965 /* Interrupt Source Overrides */
2966 /* Flags:
2967 bits[3:2]:
2968 00 conforms to the bus
2969 01 edge-triggered
2970 10 reserved
2971 11 level-triggered
2972 bits[1:0]
2973 00 conforms to the bus
2974 01 active-high
2975 10 reserved
2976 11 active-low */
2977 /* If changing, also update PDMIsaSetIrq() and MPS */
2978 ACPITBLISO* isos = madt.ISO_addr();
2979 /* Timer interrupt rule IRQ0 to GSI2 */
2980 isos[0].u8Type = 2;
2981 isos[0].u8Length = sizeof(ACPITBLISO);
2982 isos[0].u8Bus = 0; /* Must be 0 */
2983 isos[0].u8Source = 0; /* IRQ0 */
2984 isos[0].u32GSI = 2; /* connected to pin 2 */
2985 isos[0].u16Flags = 0; /* conform to the bus */
2986
2987 /* ACPI interrupt rule - IRQ9 to GSI9 */
2988 isos[1].u8Type = 2;
2989 isos[1].u8Length = sizeof(ACPITBLISO);
2990 isos[1].u8Bus = 0; /* Must be 0 */
2991 isos[1].u8Source = 9; /* IRQ9 */
2992 isos[1].u32GSI = 9; /* connected to pin 9 */
2993 isos[1].u16Flags = 0xd; /* active high, level triggered */
2994 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
2995
2996 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
2997 acpiR3PhysCopy(pThis, addr, madt.data(), madt.size());
2998}
2999
3000/**
3001 * Plant the High Performance Event Timer (HPET) descriptor.
3002 */
3003static void acpiR3SetupHpet(ACPIState *pThis, RTGCPHYS32 addr)
3004{
3005 ACPITBLHPET hpet;
3006
3007 memset(&hpet, 0, sizeof(hpet));
3008
3009 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3010 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3011 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3012 0 /* Memory address space */,
3013 64 /* Register bit width */,
3014 0 /* Bit offset */,
3015 0, /* Register access size, is it correct? */
3016 0xfed00000 /* Address */);
3017
3018 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3019 hpet.u32Number = 0;
3020 hpet.u32MinTick = 4096;
3021 hpet.u8Attributes = 0;
3022
3023 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3024
3025 acpiR3PhysCopy(pThis, addr, (const uint8_t *)&hpet, sizeof(hpet));
3026}
3027
3028
3029/** Custom Description Table */
3030static void acpiR3SetupCust(ACPIState *pThis, RTGCPHYS32 addr)
3031{
3032 ACPITBLCUST cust;
3033
3034 /* First the ACPI version 1 version of the structure. */
3035 memset(&cust, 0, sizeof(cust));
3036 acpiR3PrepareHeader(pThis, &cust.header, "CUST", sizeof(cust), 1);
3037
3038 memcpy(cust.header.au8OemTabId, pThis->au8OemTabId, 8);
3039 cust.header.u32OemRevision = RT_H2LE_U32(pThis->u32OemRevision);
3040 cust.header.u8Checksum = acpiR3Checksum((uint8_t *)&cust, sizeof(cust));
3041
3042 acpiR3PhysCopy(pThis, addr, pThis->pu8CustBin, pThis->cbCustBin);
3043}
3044
3045/**
3046 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3047 * descriptor.
3048 *
3049 * @param pThis The ACPI instance.
3050 * @param GCPhysDst Where to plant it.
3051 */
3052static void acpiR3SetupMcfg(ACPIState *pThis, RTGCPHYS32 GCPhysDst)
3053{
3054 struct
3055 {
3056 ACPITBLMCFG hdr;
3057 ACPITBLMCFGENTRY entry;
3058 } tbl;
3059 uint8_t u8StartBus = 0;
3060 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3061
3062 RT_ZERO(tbl);
3063
3064 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3065 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3066 tbl.entry.u8StartBus = u8StartBus;
3067 tbl.entry.u8EndBus = u8EndBus;
3068 // u16PciSegmentGroup must match _SEG in ACPI table
3069
3070 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3071
3072 acpiR3PhysCopy(pThis, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3073}
3074
3075/**
3076 * Used by acpiR3PlantTables and acpiConstruct.
3077 *
3078 * @returns Guest memory address.
3079 */
3080static uint32_t apicR3FindRsdpSpace(void)
3081{
3082 return 0xe0000;
3083}
3084
3085/**
3086 * Create the ACPI tables in guest memory.
3087 */
3088static int acpiR3PlantTables(ACPIState *pThis)
3089{
3090 int rc;
3091 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3092 RTGCPHYS32 GCPhysHpet = 0;
3093 RTGCPHYS32 GCPhysApic = 0;
3094 RTGCPHYS32 GCPhysSsdt = 0;
3095 RTGCPHYS32 GCPhysMcfg = 0;
3096 RTGCPHYS32 GCPhysCust = 0;
3097 uint32_t addend = 0;
3098 RTGCPHYS32 aGCPhysRsdt[8];
3099 RTGCPHYS32 aGCPhysXsdt[8];
3100 uint32_t cAddr;
3101 uint32_t iMadt = 0;
3102 uint32_t iHpet = 0;
3103 uint32_t iSsdt = 0;
3104 uint32_t iMcfg = 0;
3105 uint32_t iCust = 0;
3106 size_t cbRsdt = sizeof(ACPITBLHEADER);
3107 size_t cbXsdt = sizeof(ACPITBLHEADER);
3108
3109 cAddr = 1; /* FADT */
3110 if (pThis->u8UseIOApic)
3111 iMadt = cAddr++; /* MADT */
3112
3113 if (pThis->fUseHpet)
3114 iHpet = cAddr++; /* HPET */
3115
3116 if (pThis->fUseMcfg)
3117 iMcfg = cAddr++; /* MCFG */
3118
3119 if (pThis->fUseCust)
3120 iCust = cAddr++; /* CUST */
3121
3122 iSsdt = cAddr++; /* SSDT */
3123
3124 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3125 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3126
3127 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3128 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3129
3130 /*
3131 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3132 * The latter starts never below 4G.
3133 */
3134 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
3135 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3136 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3137
3138 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3139 if (pThis->fPciPref64Enabled)
3140 {
3141 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3142 if (pThis->u64PciPref64Max > u64PciPref64Min)
3143 {
3144 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3145 pThis->u64PciPref64Min = u64PciPref64Min;
3146 LogRel(("ACPI: enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3147 u64PciPref64Min, pThis->u64PciPref64Max-1));
3148 }
3149 else
3150 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3151 u64PciPref64Min, pThis->u64PciPref64Max-1));
3152 }
3153 if (cbBelow4GB > UINT32_C(0xffe00000)) /* See MEM3. */
3154 {
3155 /* Note: This is also enforced by DevPcBios.cpp. */
3156 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbBelow4GB));
3157 cbBelow4GB = UINT32_C(0xffe00000);
3158 }
3159 pThis->cbRamLow = cbBelow4GB;
3160
3161 GCPhysCur = 0;
3162 GCPhysRsdt = GCPhysCur;
3163
3164 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3165 GCPhysXsdt = GCPhysCur;
3166
3167 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3168 GCPhysFadtAcpi1 = GCPhysCur;
3169
3170 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3171 GCPhysFadtAcpi2 = GCPhysCur;
3172
3173 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3174 GCPhysFacs = GCPhysCur;
3175
3176 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3177 if (pThis->u8UseIOApic)
3178 {
3179 GCPhysApic = GCPhysCur;
3180 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3181 }
3182 if (pThis->fUseHpet)
3183 {
3184 GCPhysHpet = GCPhysCur;
3185 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3186 }
3187 if (pThis->fUseMcfg)
3188 {
3189 GCPhysMcfg = GCPhysCur;
3190 /* Assume one entry */
3191 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3192 }
3193 if (pThis->fUseCust)
3194 {
3195 GCPhysCust = GCPhysCur;
3196 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThis->cbCustBin, 16);
3197 }
3198
3199 void *pvSsdtCode = NULL;
3200 size_t cbSsdt = 0;
3201 rc = acpiPrepareSsdt(pThis->pDevInsR3, &pvSsdtCode, &cbSsdt);
3202 if (RT_FAILURE(rc))
3203 return rc;
3204
3205 GCPhysSsdt = GCPhysCur;
3206 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3207
3208 GCPhysDsdt = GCPhysCur;
3209
3210 void *pvDsdtCode = NULL;
3211 size_t cbDsdt = 0;
3212 rc = acpiPrepareDsdt(pThis->pDevInsR3, &pvDsdtCode, &cbDsdt);
3213 if (RT_FAILURE(rc))
3214 return rc;
3215
3216 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3217
3218 if (GCPhysCur > 0x10000)
3219 return PDMDEV_SET_ERROR(pThis->pDevInsR3, VERR_TOO_MUCH_DATA,
3220 N_("Error: ACPI tables bigger than 64KB"));
3221
3222 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3223 addend = pThis->cbRamLow - 0x10000;
3224 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3225 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3226 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3227 if (pThis->u8UseIOApic)
3228 Log((" MADT 0x%08X", GCPhysApic + addend));
3229 if (pThis->fUseHpet)
3230 Log((" HPET 0x%08X", GCPhysHpet + addend));
3231 if (pThis->fUseMcfg)
3232 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3233 if (pThis->fUseCust)
3234 Log((" CUST 0x%08X", GCPhysCust + addend));
3235 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3236 Log(("\n"));
3237
3238 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3239 acpiR3SetupDsdt(pThis, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3240 acpiCleanupDsdt(pThis->pDevInsR3, pvDsdtCode);
3241 acpiR3SetupFacs(pThis, GCPhysFacs + addend);
3242 acpiR3SetupFadt(pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3243
3244 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3245 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3246 if (pThis->u8UseIOApic)
3247 {
3248 acpiR3SetupMadt(pThis, GCPhysApic + addend);
3249 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3250 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3251 }
3252 if (pThis->fUseHpet)
3253 {
3254 acpiR3SetupHpet(pThis, GCPhysHpet + addend);
3255 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3256 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3257 }
3258 if (pThis->fUseMcfg)
3259 {
3260 acpiR3SetupMcfg(pThis, GCPhysMcfg + addend);
3261 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3262 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3263 }
3264 if (pThis->fUseCust)
3265 {
3266 acpiR3SetupCust(pThis, GCPhysCust + addend);
3267 aGCPhysRsdt[iCust] = GCPhysCust + addend;
3268 aGCPhysXsdt[iCust] = GCPhysCust + addend;
3269 }
3270
3271 acpiR3SetupSsdt(pThis, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3272 acpiCleanupSsdt(pThis->pDevInsR3, pvSsdtCode);
3273 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3274 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3275
3276 rc = acpiR3SetupRsdt(pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3277 if (RT_FAILURE(rc))
3278 return rc;
3279 return acpiR3SetupXsdt(pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3280}
3281
3282/**
3283 * @callback_method_impl{FNPCICONFIGREAD}
3284 */
3285static DECLCALLBACK(uint32_t) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
3286{
3287 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3288
3289 Log2(("acpi: PCI config read: 0x%x (%d)\n", uAddress, cb));
3290 return pThis->pfnAcpiPciConfigRead(pDevIns, pPciDev, uAddress, cb);
3291}
3292
3293/**
3294 * @callback_method_impl{FNPCICONFIGWRITE}
3295 */
3296static DECLCALLBACK(void) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3297 uint32_t u32Value, unsigned cb)
3298{
3299 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3300
3301 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3302 DEVACPI_LOCK_R3(pThis);
3303
3304 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3305 {
3306 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3307 u32Value = SCI_INT;
3308 }
3309
3310 pThis->pfnAcpiPciConfigWrite(pDevIns, pPciDev, uAddress, u32Value, cb);
3311
3312 /* Assume that the base address is only changed when the corresponding
3313 * hardware functionality is disabled. The IO region is mapped when the
3314 * functionality is enabled by the guest. */
3315
3316 if (uAddress == PMREGMISC)
3317 {
3318 RTIOPORT NewIoPortBase = 0;
3319 /* Check Power Management IO Space Enable (PMIOSE) bit */
3320 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3321 {
3322 NewIoPortBase = (RTIOPORT)PCIDevGetDWord(pPciDev, PMBA);
3323 NewIoPortBase &= 0xffc0;
3324 }
3325
3326 int rc = acpiR3UpdatePmHandlers(pThis, NewIoPortBase);
3327 AssertRC(rc);
3328 }
3329
3330 if (uAddress == SMBHSTCFG)
3331 {
3332 RTIOPORT NewIoPortBase = 0;
3333 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3334 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3335 {
3336 NewIoPortBase = (RTIOPORT)PCIDevGetDWord(pPciDev, SMBBA);
3337 NewIoPortBase &= 0xfff0;
3338 }
3339
3340 int rc = acpiR3UpdateSMBusHandlers(pThis, NewIoPortBase);
3341 AssertRC(rc);
3342 }
3343
3344 DEVACPI_UNLOCK(pThis);
3345}
3346
3347/**
3348 * Attach a new CPU.
3349 *
3350 * @returns VBox status code.
3351 * @param pDevIns The device instance.
3352 * @param iLUN The logical unit which is being attached.
3353 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3354 *
3355 * @remarks This code path is not used during construction.
3356 */
3357static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3358{
3359 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3360 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3361
3362 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3363 ("Hot-plug flag is not set\n"),
3364 VERR_NOT_SUPPORTED);
3365 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3366
3367 /* Check if it was already attached */
3368 int rc = VINF_SUCCESS;
3369 DEVACPI_LOCK_R3(pThis);
3370 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3371 {
3372 PPDMIBASE IBaseTmp;
3373 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3374 if (RT_SUCCESS(rc))
3375 {
3376 /* Enable the CPU */
3377 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3378
3379 /*
3380 * Lock the CPU because we don't know if the guest will use it or not.
3381 * Prevents ejection while the CPU is still used
3382 */
3383 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3384 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3385 pThis->u32CpuEvent = iLUN;
3386
3387 /* Notify the guest */
3388 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3389 }
3390 }
3391 DEVACPI_UNLOCK(pThis);
3392 return rc;
3393}
3394
3395/**
3396 * Detach notification.
3397 *
3398 * @param pDevIns The device instance.
3399 * @param iLUN The logical unit which is being detached.
3400 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3401 */
3402static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3403{
3404 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3405
3406 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3407
3408 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3409 ("Hot-plug flag is not set\n"));
3410
3411 /* Check if it was already detached */
3412 DEVACPI_LOCK_R3(pThis);
3413 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3414 {
3415 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3416 {
3417 /* Disable the CPU */
3418 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3419 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3420 pThis->u32CpuEvent = iLUN;
3421
3422 /* Notify the guest */
3423 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3424 }
3425 else
3426 AssertMsgFailed(("CPU is still locked by the guest\n"));
3427 }
3428 DEVACPI_UNLOCK(pThis);
3429}
3430
3431/**
3432 * @interface_method_impl{PDMDEVREG,pfnResume}
3433 */
3434static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3435{
3436 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3437 if (pThis->fSetWakeupOnResume)
3438 {
3439 Log(("acpiResume: setting WAK_STS\n"));
3440 pThis->fSetWakeupOnResume = false;
3441 pThis->pm1a_sts |= WAK_STS;
3442 }
3443}
3444
3445/**
3446 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3447 */
3448static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3449{
3450 RT_NOREF1(enmCtx);
3451 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3452 acpiR3PlantTables(pThis);
3453}
3454
3455/**
3456 * @interface_method_impl{PDMDEVREG,pfnReset}
3457 */
3458static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3459{
3460 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3461
3462 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3463 acpiSetIrq(pThis, 0);
3464
3465 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);
3466 pThis->pm1a_en = 0;
3467 pThis->pm1a_sts = 0;
3468 pThis->pm1a_ctl = 0;
3469 pThis->u64PmTimerInitial = TMTimerGet(pThis->pPmTimerR3);
3470 pThis->uPmTimerVal = 0;
3471 acpiR3PmTimerReset(pThis, pThis->u64PmTimerInitial);
3472 pThis->uBatteryIndex = 0;
3473 pThis->uSystemInfoIndex = 0;
3474 pThis->gpe0_en = 0;
3475 pThis->gpe0_sts = 0;
3476 pThis->uSleepState = 0;
3477 TMTimerUnlock(pThis->pPmTimerR3);
3478
3479 /* Real device behavior is resetting only the PM controller state,
3480 * but we're additionally doing the job of the BIOS. */
3481 acpiR3UpdatePmHandlers(pThis, PM_PORT_BASE);
3482 acpiR3PmPCIBIOSFake(pThis);
3483
3484 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3485 * state. Real device behavior is only the SMBus controller state reset,
3486 * but we're additionally doing the job of the BIOS. */
3487 acpiR3UpdateSMBusHandlers(pThis, SMB_PORT_BASE);
3488 acpiR3SMBusPCIBIOSFake(pThis);
3489 acpiR3SMBusResetDevice(pThis);
3490}
3491
3492/**
3493 * @interface_method_impl{PDMDEVREG,pfnRelocate}
3494 */
3495static DECLCALLBACK(void) acpiR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3496{
3497 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3498 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3499 pThis->pPmTimerRC = TMTimerRCPtr(pThis->pPmTimerR3);
3500 NOREF(offDelta);
3501}
3502
3503/**
3504 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3505 */
3506static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3507{
3508 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3509 if (pThis->pu8CustBin)
3510 {
3511 PDMDevHlpMMHeapFree(pDevIns, pThis->pu8CustBin);
3512 pThis->pu8CustBin = NULL;
3513 }
3514 return VINF_SUCCESS;
3515}
3516
3517/**
3518 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3519 */
3520static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3521{
3522 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
3523 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3524
3525 /*
3526 * Init data and set defaults.
3527 */
3528 /** @todo move more of the code up! */
3529
3530 pThis->pDevInsR3 = pDevIns;
3531 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3532 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3533 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3534 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3535 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3536 pThis->u32CpuEventType = 0;
3537 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3538
3539 /* The first CPU can't be attached/detached */
3540 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3541 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3542
3543 /* IBase */
3544 pThis->IBase.pfnQueryInterface = acpiR3QueryInterface;
3545 /* IACPIPort */
3546 pThis->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3547 pThis->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3548 pThis->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3549 pThis->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3550 pThis->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3551 pThis->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3552 pThis->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3553
3554 /*
3555 * Set the default critical section to NOP (related to the PM timer).
3556 */
3557 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3558 AssertRCReturn(rc, rc);
3559
3560 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3561 AssertRCReturn(rc, rc);
3562
3563 /*
3564 * Validate and read the configuration.
3565 */
3566 if (!CFGMR3AreValuesValid(pCfg,
3567 "IOAPIC\0"
3568 "NumCPUs\0"
3569 "GCEnabled\0"
3570 "R0Enabled\0"
3571 "HpetEnabled\0"
3572 "McfgEnabled\0"
3573 "McfgBase\0"
3574 "McfgLength\0"
3575 "PciPref64Enabled\0"
3576 "PciPref64LimitGB\0"
3577 "SmcEnabled\0"
3578 "FdcEnabled\0"
3579 "ShowRtc\0"
3580 "ShowCpu\0"
3581 "NicPciAddress\0"
3582 "AudioPciAddress\0"
3583 "IocPciAddress\0"
3584 "HostBusPciAddress\0"
3585 "EnableSuspendToDisk\0"
3586 "PowerS1Enabled\0"
3587 "PowerS4Enabled\0"
3588 "CpuHotPlug\0"
3589 "AmlFilePath\0"
3590 "Serial0IoPortBase\0"
3591 "Serial1IoPortBase\0"
3592 "Serial2IoPortBase\0"
3593 "Serial3IoPortBase\0"
3594 "Serial0Irq\0"
3595 "Serial1Irq\0"
3596 "Serial2Irq\0"
3597 "Serial3Irq\0"
3598 "AcpiOemId\0"
3599 "AcpiCreatorId\0"
3600 "AcpiCreatorRev\0"
3601 "CustomTable\0"
3602 "SLICTable\0"
3603 "Parallel0IoPortBase\0"
3604 "Parallel1IoPortBase\0"
3605 "Parallel0Irq\0"
3606 "Parallel1Irq\0"
3607 ))
3608 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
3609 N_("Configuration error: Invalid config key for ACPI device"));
3610
3611 /* query whether we are supposed to present an IOAPIC */
3612 rc = CFGMR3QueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3613 if (RT_FAILURE(rc))
3614 return PDMDEV_SET_ERROR(pDevIns, rc,
3615 N_("Configuration error: Failed to read \"IOAPIC\""));
3616
3617 rc = CFGMR3QueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3618 if (RT_FAILURE(rc))
3619 return PDMDEV_SET_ERROR(pDevIns, rc,
3620 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3621
3622 /* query whether we are supposed to present an FDC controller */
3623 rc = CFGMR3QueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3624 if (RT_FAILURE(rc))
3625 return PDMDEV_SET_ERROR(pDevIns, rc,
3626 N_("Configuration error: Failed to read \"FdcEnabled\""));
3627
3628 /* query whether we are supposed to present HPET */
3629 rc = CFGMR3QueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
3630 if (RT_FAILURE(rc))
3631 return PDMDEV_SET_ERROR(pDevIns, rc,
3632 N_("Configuration error: Failed to read \"HpetEnabled\""));
3633 /* query MCFG configuration */
3634 rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
3635 if (RT_FAILURE(rc))
3636 return PDMDEV_SET_ERROR(pDevIns, rc,
3637 N_("Configuration error: Failed to read \"McfgBase\""));
3638 rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
3639 if (RT_FAILURE(rc))
3640 return PDMDEV_SET_ERROR(pDevIns, rc,
3641 N_("Configuration error: Failed to read \"McfgLength\""));
3642 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
3643
3644 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
3645 rc = CFGMR3QueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
3646 if (RT_FAILURE(rc))
3647 return PDMDEV_SET_ERROR(pDevIns, rc,
3648 N_("Configuration error: Failed to read \"PciPref64Enabled\""));
3649
3650 /* query the limit of the the 64-bit prefetchable memory window */
3651 uint64_t u64PciPref64MaxGB;
3652 rc = CFGMR3QueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
3653 if (RT_FAILURE(rc))
3654 return PDMDEV_SET_ERROR(pDevIns, rc,
3655 N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
3656 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
3657
3658 /* query whether we are supposed to present custom table */
3659 pThis->fUseCust = false;
3660
3661 /* query whether we are supposed to present SMC */
3662 rc = CFGMR3QueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
3663 if (RT_FAILURE(rc))
3664 return PDMDEV_SET_ERROR(pDevIns, rc,
3665 N_("Configuration error: Failed to read \"SmcEnabled\""));
3666
3667 /* query whether we are supposed to present RTC object */
3668 rc = CFGMR3QueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
3669 if (RT_FAILURE(rc))
3670 return PDMDEV_SET_ERROR(pDevIns, rc,
3671 N_("Configuration error: Failed to read \"ShowRtc\""));
3672
3673 /* query whether we are supposed to present CPU objects */
3674 rc = CFGMR3QueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
3675 if (RT_FAILURE(rc))
3676 return PDMDEV_SET_ERROR(pDevIns, rc,
3677 N_("Configuration error: Failed to read \"ShowCpu\""));
3678
3679 /* query primary NIC PCI address */
3680 rc = CFGMR3QueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
3681 if (RT_FAILURE(rc))
3682 return PDMDEV_SET_ERROR(pDevIns, rc,
3683 N_("Configuration error: Failed to read \"NicPciAddress\""));
3684
3685 /* query primary NIC PCI address */
3686 rc = CFGMR3QueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3687 if (RT_FAILURE(rc))
3688 return PDMDEV_SET_ERROR(pDevIns, rc,
3689 N_("Configuration error: Failed to read \"AudioPciAddress\""));
3690
3691 /* query IO controller (southbridge) PCI address */
3692 rc = CFGMR3QueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3693 if (RT_FAILURE(rc))
3694 return PDMDEV_SET_ERROR(pDevIns, rc,
3695 N_("Configuration error: Failed to read \"IocPciAddress\""));
3696
3697 /* query host bus controller PCI address */
3698 rc = CFGMR3QueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3699 if (RT_FAILURE(rc))
3700 return PDMDEV_SET_ERROR(pDevIns, rc,
3701 N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3702
3703 /* query whether S1 power state should be exposed */
3704 rc = CFGMR3QueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3705 if (RT_FAILURE(rc))
3706 return PDMDEV_SET_ERROR(pDevIns, rc,
3707 N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3708
3709 /* query whether S4 power state should be exposed */
3710 rc = CFGMR3QueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3711 if (RT_FAILURE(rc))
3712 return PDMDEV_SET_ERROR(pDevIns, rc,
3713 N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3714
3715 /* query whether S1 power state should save the VM state */
3716 rc = CFGMR3QueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3717 if (RT_FAILURE(rc))
3718 return PDMDEV_SET_ERROR(pDevIns, rc,
3719 N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3720
3721 /* query whether we are allow CPU hot plugging */
3722 rc = CFGMR3QueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3723 if (RT_FAILURE(rc))
3724 return PDMDEV_SET_ERROR(pDevIns, rc,
3725 N_("Configuration error: Failed to read \"CpuHotPlug\""));
3726
3727 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
3728 if (RT_FAILURE(rc))
3729 return PDMDEV_SET_ERROR(pDevIns, rc,
3730 N_("Configuration error: Failed to read \"GCEnabled\""));
3731
3732 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
3733 if (RT_FAILURE(rc))
3734 return PDMDEV_SET_ERROR(pDevIns, rc,
3735 N_("configuration error: failed to read \"R0Enabled\""));
3736
3737 /* query serial info */
3738 rc = CFGMR3QueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3739 if (RT_FAILURE(rc))
3740 return PDMDEV_SET_ERROR(pDevIns, rc,
3741 N_("Configuration error: Failed to read \"Serial0Irq\""));
3742
3743 rc = CFGMR3QueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3744 if (RT_FAILURE(rc))
3745 return PDMDEV_SET_ERROR(pDevIns, rc,
3746 N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3747
3748 /* Serial 1 is enabled, get config data */
3749 rc = CFGMR3QueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3750 if (RT_FAILURE(rc))
3751 return PDMDEV_SET_ERROR(pDevIns, rc,
3752 N_("Configuration error: Failed to read \"Serial1Irq\""));
3753
3754 rc = CFGMR3QueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3755 if (RT_FAILURE(rc))
3756 return PDMDEV_SET_ERROR(pDevIns, rc,
3757 N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3758
3759 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
3760 rc = CFGMR3QueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
3761 if (RT_FAILURE(rc))
3762 return PDMDEV_SET_ERROR(pDevIns, rc,
3763 N_("Configuration error: Failed to read \"Serial2Irq\""));
3764
3765 rc = CFGMR3QueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
3766 if (RT_FAILURE(rc))
3767 return PDMDEV_SET_ERROR(pDevIns, rc,
3768 N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
3769
3770 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
3771 rc = CFGMR3QueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
3772 if (RT_FAILURE(rc))
3773 return PDMDEV_SET_ERROR(pDevIns, rc,
3774 N_("Configuration error: Failed to read \"Serial3Irq\""));
3775
3776 rc = CFGMR3QueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
3777 if (RT_FAILURE(rc))
3778 return PDMDEV_SET_ERROR(pDevIns, rc,
3779 N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
3780 /*
3781 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
3782 * the corresponding parallel port is not enabled.
3783 */
3784 rc = CFGMR3QueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
3785 if (RT_FAILURE(rc))
3786 return PDMDEV_SET_ERROR(pDevIns, rc,
3787 N_("Configuration error: Failed to read \"Parallel0Irq\""));
3788
3789 rc = CFGMR3QueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
3790 if (RT_FAILURE(rc))
3791 return PDMDEV_SET_ERROR(pDevIns, rc,
3792 N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
3793
3794 rc = CFGMR3QueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
3795 if (RT_FAILURE(rc))
3796 return PDMDEV_SET_ERROR(pDevIns, rc,
3797 N_("Configuration error: Failed to read \"Parallel1Irq\""));
3798
3799 rc = CFGMR3QueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
3800 if (RT_FAILURE(rc))
3801 return PDMDEV_SET_ERROR(pDevIns, rc,
3802 N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
3803
3804 /* Try to attach the other CPUs */
3805 for (unsigned i = 1; i < pThis->cCpus; i++)
3806 {
3807 if (pThis->fCpuHotPlug)
3808 {
3809 PPDMIBASE IBaseTmp;
3810 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3811
3812 if (RT_SUCCESS(rc))
3813 {
3814 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3815 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3816 Log(("acpi: Attached CPU %u\n", i));
3817 }
3818 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3819 Log(("acpi: CPU %u not attached yet\n", i));
3820 else
3821 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3822 }
3823 else
3824 {
3825 /* CPU is always attached if hot-plug is not enabled. */
3826 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3827 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3828 }
3829 }
3830
3831 char *pszOemId = NULL;
3832 rc = CFGMR3QueryStringAllocDef(pCfg, "AcpiOemId", &pszOemId, "VBOX ");
3833 if (RT_FAILURE(rc))
3834 return PDMDEV_SET_ERROR(pDevIns, rc,
3835 N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3836 size_t cbOemId = strlen(pszOemId);
3837 if (cbOemId > 6)
3838 return PDMDEV_SET_ERROR(pDevIns, rc,
3839 N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3840 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3841 memcpy(pThis->au8OemId, pszOemId, cbOemId);
3842 MMR3HeapFree(pszOemId);
3843
3844 char *pszCreatorId = NULL;
3845 rc = CFGMR3QueryStringAllocDef(pCfg, "AcpiCreatorId", &pszCreatorId, "ASL ");
3846 if (RT_FAILURE(rc))
3847 return PDMDEV_SET_ERROR(pDevIns, rc,
3848 N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3849 size_t cbCreatorId = strlen(pszCreatorId);
3850 if (cbCreatorId > 4)
3851 return PDMDEV_SET_ERROR(pDevIns, rc,
3852 N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3853 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3854 memcpy(pThis->au8CreatorId, pszCreatorId, cbCreatorId);
3855 MMR3HeapFree(pszCreatorId);
3856
3857 rc = CFGMR3QueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3858 if (RT_FAILURE(rc))
3859 return PDMDEV_SET_ERROR(pDevIns, rc,
3860 N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3861 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3862
3863 /*
3864 * Get the custom table binary file name.
3865 */
3866 char *pszCustBinFile;
3867 rc = CFGMR3QueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile);
3868 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3869 rc = CFGMR3QueryStringAlloc(pCfg, "SLICTable", &pszCustBinFile);
3870 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3871 {
3872 pszCustBinFile = NULL;
3873 rc = VINF_SUCCESS;
3874 }
3875 else if (RT_FAILURE(rc))
3876 return PDMDEV_SET_ERROR(pDevIns, rc,
3877 N_("Configuration error: Querying \"CustomTable\" as a string failed"));
3878 else if (!*pszCustBinFile)
3879 {
3880 MMR3HeapFree(pszCustBinFile);
3881 pszCustBinFile = NULL;
3882 }
3883
3884 /*
3885 * Determine the custom table binary size, open specified ROM file in the process.
3886 */
3887 if (pszCustBinFile)
3888 {
3889 RTFILE FileCUSTBin;
3890 rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3891 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3892 if (RT_SUCCESS(rc))
3893 {
3894 rc = RTFileGetSize(FileCUSTBin, &pThis->cbCustBin);
3895 if (RT_SUCCESS(rc))
3896 {
3897 /* The following checks should be in sync the AssertReleaseMsg's below. */
3898 if ( pThis->cbCustBin > 3072
3899 || pThis->cbCustBin < sizeof(ACPITBLHEADER))
3900 rc = VERR_TOO_MUCH_DATA;
3901
3902 /*
3903 * Allocate buffer for the custom table binary data.
3904 */
3905 pThis->pu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, pThis->cbCustBin);
3906 if (pThis->pu8CustBin)
3907 {
3908 rc = RTFileRead(FileCUSTBin, pThis->pu8CustBin, pThis->cbCustBin, NULL);
3909 if (RT_FAILURE(rc))
3910 {
3911 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", pThis->cbCustBin, rc));
3912 PDMDevHlpMMHeapFree(pDevIns, pThis->pu8CustBin);
3913 pThis->pu8CustBin = NULL;
3914 }
3915 else
3916 {
3917 pThis->fUseCust = true;
3918 memcpy(&pThis->au8OemId[0], &pThis->pu8CustBin[10], 6);
3919 memcpy(&pThis->au8OemTabId[0], &pThis->pu8CustBin[16], 8);
3920 memcpy(&pThis->u32OemRevision, &pThis->pu8CustBin[24], 4);
3921 memcpy(&pThis->au8CreatorId[0], &pThis->pu8CustBin[28], 4);
3922 memcpy(&pThis->u32CreatorRev, &pThis->pu8CustBin[32], 4);
3923 LogRel(("ACPI: Reading custom ACPI table from file '%s' (%d bytes)\n", pszCustBinFile,
3924 pThis->cbCustBin));
3925 }
3926 }
3927 else
3928 rc = VERR_NO_MEMORY;
3929
3930 RTFileClose(FileCUSTBin);
3931 }
3932 }
3933 MMR3HeapFree(pszCustBinFile);
3934 if (RT_FAILURE(rc))
3935 return PDMDEV_SET_ERROR(pDevIns, rc,
3936 N_("Error reading custom ACPI table"));
3937 }
3938
3939 /* Set default PM port base */
3940 pThis->uPmIoPortBase = PM_PORT_BASE;
3941
3942 /* Set default SMBus port base */
3943 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
3944
3945 /*
3946 * FDC and SMC try to use the same non-shareable interrupt (6),
3947 * enable only one device.
3948 */
3949 if (pThis->fUseSmc)
3950 pThis->fUseFdc = false;
3951
3952 /*
3953 * Plant ACPI tables.
3954 */
3955 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
3956 * au8RSDPPage here. However, there should be no harm in doing it
3957 * twice, so the lazy bird is taking the quick way out for now. */
3958 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
3959 if (!GCPhysRsdp)
3960 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
3961 N_("Can not find space for RSDP. ACPI is disabled"));
3962
3963 rc = acpiR3PlantTables(pThis);
3964 if (RT_FAILURE(rc))
3965 return rc;
3966
3967 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
3968 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
3969 if (RT_FAILURE(rc))
3970 return rc;
3971
3972 /*
3973 * Register I/O ports.
3974 */
3975 rc = acpiR3RegisterPmHandlers(pThis);
3976 if (RT_FAILURE(rc))
3977 return rc;
3978
3979 rc = acpiR3RegisterSMBusHandlers(pThis);
3980 if (RT_FAILURE(rc))
3981 return rc;
3982
3983#define R(addr, cnt, writer, reader, description) \
3984 do { \
3985 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, pThis, writer, reader, \
3986 NULL, NULL, description); \
3987 if (RT_FAILURE(rc)) \
3988 return rc; \
3989 } while (0)
3990 R(SMI_CMD, 1, acpiR3SmiWrite, NULL, "ACPI SMI");
3991#ifdef DEBUG_ACPI
3992 R(DEBUG_HEX, 1, acpiR3DhexWrite, NULL, "ACPI Debug hex");
3993 R(DEBUG_CHR, 1, acpiR3DchrWrite, NULL, "ACPI Debug char");
3994#endif
3995 R(BAT_INDEX, 1, acpiR3BatIndexWrite, NULL, "ACPI Battery status index");
3996 R(BAT_DATA, 1, NULL, acpiR3BatDataRead, "ACPI Battery status data");
3997 R(SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL, "ACPI system info index");
3998 R(SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead, "ACPI system info data");
3999 R(ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL, "ACPI Reset");
4000#undef R
4001
4002 /*
4003 * Create the PM timer.
4004 */
4005 PTMTIMER pTimer;
4006 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, &pThis->dev,
4007 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pTimer);
4008 AssertRCReturn(rc, rc);
4009 pThis->pPmTimerR3 = pTimer;
4010 pThis->pPmTimerR0 = TMTimerR0Ptr(pTimer);
4011 pThis->pPmTimerRC = TMTimerRCPtr(pTimer);
4012
4013 rc = TMTimerLock(pTimer, VERR_IGNORED);
4014 AssertRCReturn(rc, rc);
4015 pThis->u64PmTimerInitial = TMTimerGet(pTimer);
4016 acpiR3PmTimerReset(pThis, pThis->u64PmTimerInitial);
4017 TMTimerUnlock(pTimer);
4018
4019 /*
4020 * Set up the PCI device.
4021 */
4022 PCIDevSetVendorId(&pThis->dev, 0x8086); /* Intel */
4023 PCIDevSetDeviceId(&pThis->dev, 0x7113); /* 82371AB */
4024
4025 /* See p. 50 of PIIX4 manual */
4026 PCIDevSetCommand(&pThis->dev, 0x01);
4027 PCIDevSetStatus(&pThis->dev, 0x0280);
4028
4029 PCIDevSetRevisionId(&pThis->dev, 0x08);
4030
4031 PCIDevSetClassProg(&pThis->dev, 0x00);
4032 PCIDevSetClassSub(&pThis->dev, 0x80);
4033 PCIDevSetClassBase(&pThis->dev, 0x06);
4034
4035 PCIDevSetHeaderType(&pThis->dev, 0x80);
4036
4037 PCIDevSetBIST(&pThis->dev, 0x00);
4038
4039 PCIDevSetInterruptLine(&pThis->dev, SCI_INT);
4040 PCIDevSetInterruptPin (&pThis->dev, 0x01);
4041
4042 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4043 acpiR3PmPCIBIOSFake(pThis);
4044
4045 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4046 acpiR3SMBusPCIBIOSFake(pThis);
4047 acpiR3SMBusResetDevice(pThis);
4048
4049 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
4050 if (RT_FAILURE(rc))
4051 return rc;
4052
4053 PDMDevHlpPCISetConfigCallbacks(pDevIns, &pThis->dev,
4054 acpiR3PciConfigRead, &pThis->pfnAcpiPciConfigRead,
4055 acpiR3PciConfigWrite, &pThis->pfnAcpiPciConfigWrite);
4056
4057 /*
4058 * Register the saved state.
4059 */
4060 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4061 if (RT_FAILURE(rc))
4062 return rc;
4063
4064 /*
4065 * Get the corresponding connector interface
4066 */
4067 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "ACPI Driver Port");
4068 if (RT_SUCCESS(rc))
4069 {
4070 pThis->pDrv = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIACPICONNECTOR);
4071 if (!pThis->pDrv)
4072 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
4073 N_("LUN #0 doesn't have an ACPI connector interface"));
4074 }
4075 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4076 {
4077 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
4078 pDevIns->pReg->szName, pDevIns->iInstance));
4079 rc = VINF_SUCCESS;
4080 }
4081 else
4082 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4083
4084 return rc;
4085}
4086
4087/**
4088 * The device registration structure.
4089 */
4090const PDMDEVREG g_DeviceACPI =
4091{
4092 /* u32Version */
4093 PDM_DEVREG_VERSION,
4094 /* szName */
4095 "acpi",
4096 /* szRCMod */
4097 "VBoxDDRC.rc",
4098 /* szR0Mod */
4099 "VBoxDDR0.r0",
4100 /* pszDescription */
4101 "Advanced Configuration and Power Interface",
4102 /* fFlags */
4103 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
4104 /* fClass */
4105 PDM_DEVREG_CLASS_ACPI,
4106 /* cMaxInstances */
4107 ~0U,
4108 /* cbInstance */
4109 sizeof(ACPIState),
4110 /* pfnConstruct */
4111 acpiR3Construct,
4112 /* pfnDestruct */
4113 acpiR3Destruct,
4114 /* pfnRelocate */
4115 acpiR3Relocate,
4116 /* pfnMemSetup */
4117 acpiR3MemSetup,
4118 /* pfnPowerOn */
4119 NULL,
4120 /* pfnReset */
4121 acpiR3Reset,
4122 /* pfnSuspend */
4123 NULL,
4124 /* pfnResume */
4125 acpiR3Resume,
4126 /* pfnAttach */
4127 acpiR3Attach,
4128 /* pfnDetach */
4129 acpiR3Detach,
4130 /* pfnQueryInterface. */
4131 NULL,
4132 /* pfnInitComplete */
4133 NULL,
4134 /* pfnPowerOff */
4135 NULL,
4136 /* pfnSoftReset */
4137 NULL,
4138 /* u32VersionEnd */
4139 PDM_DEVREG_VERSION
4140};
4141
4142#endif /* IN_RING3 */
4143#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette