VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 81996

Last change on this file since 81996 was 81996, checked in by vboxsync, 5 years ago

DevACPI: Converted the timer pointers to a handle and eliminated the pDevInsR* members. bugref:9218
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File size: 152.6 KB
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1/* $Id: DevACPI.cpp 81996 2019-11-19 14:41:07Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#include <iprt/file.h>
33#ifdef IN_RING3
34# include <iprt/alloc.h>
35# include <iprt/string.h>
36# include <iprt/uuid.h>
37#endif /* IN_RING3 */
38
39#include "VBoxDD.h"
40
41#ifdef LOG_ENABLED
42# define DEBUG_ACPI
43#endif
44
45
46/*********************************************************************************************************************************
47* Defined Constants And Macros *
48*********************************************************************************************************************************/
49#ifdef IN_RING3
50/** Locks the device state, ring-3 only. */
51# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
52 do { \
53 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
54 AssertRC(rcLock); \
55 } while (0)
56#endif
57/** Unlocks the device state (all contexts). */
58#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
59 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
60
61
62#define DEBUG_HEX 0x3000
63#define DEBUG_CHR 0x3001
64
65/** PM Base Address PCI config space offset */
66#define PMBA 0x40
67/** PM Miscellaneous Power Management PCI config space offset */
68#define PMREGMISC 0x80
69
70#define PM_TMR_FREQ 3579545
71/** Default base for PM PIIX4 device */
72#define PM_PORT_BASE 0x4000
73/* Port offsets in PM device */
74enum
75{
76 PM1a_EVT_OFFSET = 0x00,
77 PM1b_EVT_OFFSET = -1, /**< not supported */
78 PM1a_CTL_OFFSET = 0x04,
79 PM1b_CTL_OFFSET = -1, /**< not supported */
80 PM2_CTL_OFFSET = -1, /**< not supported */
81 PM_TMR_OFFSET = 0x08,
82 GPE0_OFFSET = 0x20,
83 GPE1_OFFSET = -1 /**< not supported */
84};
85
86/* Maximum supported number of custom ACPI tables */
87#define MAX_CUST_TABLES 4
88
89/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
90#define PM_TMR_32BIT
91
92#define BAT_INDEX 0x00004040
93#define BAT_DATA 0x00004044
94#define SYSI_INDEX 0x00004048
95#define SYSI_DATA 0x0000404c
96#define ACPI_RESET_BLK 0x00004050
97
98/* PM1x status register bits */
99#define TMR_STS RT_BIT(0)
100#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
101#define BM_STS RT_BIT(4)
102#define GBL_STS RT_BIT(5)
103#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
104#define PWRBTN_STS RT_BIT(8)
105#define SLPBTN_STS RT_BIT(9)
106#define RTC_STS RT_BIT(10)
107#define IGN_STS RT_BIT(11)
108#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
109#define WAK_STS RT_BIT(15)
110#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
111
112/* PM1x enable register bits */
113#define TMR_EN RT_BIT(0)
114#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
115#define GBL_EN RT_BIT(5)
116#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
117#define PWRBTN_EN RT_BIT(8)
118#define SLPBTN_EN RT_BIT(9)
119#define RTC_EN RT_BIT(10)
120#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
121#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
122#define IGN_EN 0
123
124/* PM1x control register bits */
125#define SCI_EN RT_BIT(0)
126#define BM_RLD RT_BIT(1)
127#define GBL_RLS RT_BIT(2)
128#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
129#define IGN_CNT RT_BIT(9)
130#define SLP_TYPx_SHIFT 10
131#define SLP_TYPx_MASK 7
132#define SLP_EN RT_BIT(13)
133#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
134#define RSR_CNT (RSR1_CNT | RSR2_CNT)
135
136#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
137
138enum
139{
140 BAT_STATUS_STATE = 0x00, /**< BST battery state */
141 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
142 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
143 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
144 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
145 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
146 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
147 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
148 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
149 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
150 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
151 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
152 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
153 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
154 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
155 BAT_INDEX_LAST
156};
157
158enum
159{
160 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
161 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
162};
163
164enum
165{
166 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
167 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
168 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
169 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
170 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
171 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
172 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
173 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
174 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
175 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
176 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
177 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
178 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
179 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
180 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
181 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
182 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
183 SYSTEM_INFO_INDEX_POWER_STATES = 17,
184 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
185 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
186 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
187 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
188 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
189 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
190 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
191 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
192 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
193 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
194 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
195 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
196 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
197 SYSTEM_INFO_INDEX_END = 31,
198 SYSTEM_INFO_INDEX_INVALID = 0x80,
199 SYSTEM_INFO_INDEX_VALID = 0x200
200};
201
202#define AC_OFFLINE 0
203#define AC_ONLINE 1
204
205#define BAT_TECH_PRIMARY 1
206#define BAT_TECH_SECONDARY 2
207
208#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
209#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
210#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
211#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
212#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
213
214/** SMBus Base Address PCI config space offset */
215#define SMBBA 0x90
216/** SMBus Host Configuration PCI config space offset */
217#define SMBHSTCFG 0xd2
218/** SMBus Slave Command PCI config space offset */
219#define SMBSLVC 0xd3
220/** SMBus Slave Shadow Port 1 PCI config space offset */
221#define SMBSHDW1 0xd4
222/** SMBus Slave Shadow Port 2 PCI config space offset */
223#define SMBSHDW2 0xd5
224/** SMBus Revision Identification PCI config space offset */
225#define SMBREV 0xd6
226
227#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
228#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
229#define SMBHSTCFG_INTRSEL_SMI 0
230#define SMBHSTCFG_INTRSEL_IRQ9 4
231#define SMBHSTCFG_INTRSEL_SHIFT 1
232
233/** Default base for SMBus PIIX4 device */
234#define SMB_PORT_BASE 0x4100
235
236/** SMBus Host Status Register I/O offset */
237#define SMBHSTSTS_OFF 0x0000
238/** SMBus Slave Status Register I/O offset */
239#define SMBSLVSTS_OFF 0x0001
240/** SMBus Host Count Register I/O offset */
241#define SMBHSTCNT_OFF 0x0002
242/** SMBus Host Command Register I/O offset */
243#define SMBHSTCMD_OFF 0x0003
244/** SMBus Host Address Register I/O offset */
245#define SMBHSTADD_OFF 0x0004
246/** SMBus Host Data 0 Register I/O offset */
247#define SMBHSTDAT0_OFF 0x0005
248/** SMBus Host Data 1 Register I/O offset */
249#define SMBHSTDAT1_OFF 0x0006
250/** SMBus Block Data Register I/O offset */
251#define SMBBLKDAT_OFF 0x0007
252/** SMBus Slave Control Register I/O offset */
253#define SMBSLVCNT_OFF 0x0008
254/** SMBus Shadow Command Register I/O offset */
255#define SMBSHDWCMD_OFF 0x0009
256/** SMBus Slave Event Register I/O offset */
257#define SMBSLVEVT_OFF 0x000a
258/** SMBus Slave Data Register I/O offset */
259#define SMBSLVDAT_OFF 0x000c
260
261#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
262#define SMBHSTSTS_INTER RT_BIT(1)
263#define SMBHSTSTS_DEV_ERR RT_BIT(2)
264#define SMBHSTSTS_BUS_ERR RT_BIT(3)
265#define SMBHSTSTS_FAILED RT_BIT(4)
266#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
267
268#define SMBSLVSTS_WRITE_MASK 0x3c
269
270#define SMBHSTCNT_INTEREN RT_BIT(0)
271#define SMBHSTCNT_KILL RT_BIT(1)
272#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
273#define SMBHSTCNT_START RT_BIT(6)
274#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
275
276#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
277
278
279/*********************************************************************************************************************************
280* Structures and Typedefs *
281*********************************************************************************************************************************/
282/**
283 * The ACPI device state.
284 */
285typedef struct ACPIState
286{
287 /** Critical section protecting the ACPI state. */
288 PDMCRITSECT CritSect;
289
290 uint16_t pm1a_en;
291 uint16_t pm1a_sts;
292 uint16_t pm1a_ctl;
293 /** Number of logical CPUs in guest */
294 uint16_t cCpus;
295
296 uint64_t u64PmTimerInitial;
297 /** The PM timer. */
298 TMTIMERHANDLE hPmTimer;
299 /* PM Timer last calculated value */
300 uint32_t uPmTimerVal;
301 uint32_t Alignment0;
302
303 uint32_t gpe0_en;
304 uint32_t gpe0_sts;
305
306 uint32_t uBatteryIndex;
307 uint32_t au8BatteryInfo[13];
308
309 uint32_t uSystemInfoIndex;
310 uint64_t u64RamSize;
311 /** Offset of the 64-bit prefetchable memory window. */
312 uint64_t u64PciPref64Min;
313 /** Limit of the 64-bit prefetchable memory window. */
314 uint64_t u64PciPref64Max;
315 /** The number of bytes below 4GB. */
316 uint32_t cbRamLow;
317
318 /** Current ACPI S* state. We support S0 and S5. */
319 uint32_t uSleepState;
320 uint8_t au8RSDPPage[0x1000];
321 /** This is a workaround for incorrect index field handling by Intels ACPICA.
322 * The system info _INI method writes to offset 0x200. We either observe a
323 * write request to index 0x80 (in that case we don't change the index) or a
324 * write request to offset 0x200 (in that case we divide the index value by
325 * 4. Note that the _STA method is sometimes called prior to the _INI method
326 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
327 * acpiR3BatIndexWrite() for handling this. */
328 uint8_t u8IndexShift;
329 /** provide an I/O-APIC */
330 uint8_t u8UseIOApic;
331 /** provide a floppy controller */
332 bool fUseFdc;
333 /** If High Precision Event Timer device should be supported */
334 bool fUseHpet;
335 /** If System Management Controller device should be supported */
336 bool fUseSmc;
337 /** the guest handled the last power button event */
338 bool fPowerButtonHandled;
339 /** If ACPI CPU device should be shown */
340 bool fShowCpu;
341 /** If Real Time Clock ACPI object to be shown */
342 bool fShowRtc;
343 /** I/O port address of PM device. */
344 RTIOPORT uPmIoPortBase;
345 /** I/O port address of SMBus device. */
346 RTIOPORT uSMBusIoPortBase;
347 /** Array of flags of attached CPUs */
348 VMCPUSET CpuSetAttached;
349 /** Which CPU to check for the locked status. */
350 uint32_t idCpuLockCheck;
351 /** Mask of locked CPUs (used by the guest). */
352 VMCPUSET CpuSetLocked;
353 /** The CPU event type. */
354 uint32_t u32CpuEventType;
355 /** The CPU id affected. */
356 uint32_t u32CpuEvent;
357 /** Flag whether CPU hot plugging is enabled. */
358 bool fCpuHotPlug;
359 /** If MCFG ACPI table shown to the guest */
360 bool fUseMcfg;
361 /** if the 64-bit prefetchable memory window is shown to the guest */
362 bool fPciPref64Enabled;
363 /** Primary NIC PCI address. */
364 uint32_t u32NicPciAddress;
365 /** Primary audio card PCI address. */
366 uint32_t u32AudioPciAddress;
367 /** Flag whether S1 power state is enabled. */
368 bool fS1Enabled;
369 /** Flag whether S4 power state is enabled. */
370 bool fS4Enabled;
371 /** Flag whether S1 triggers a state save. */
372 bool fSuspendToSavedState;
373 /** Flag whether to set WAK_STS on resume (restore included). */
374 bool fSetWakeupOnResume;
375 /** PCI address of the IO controller device. */
376 uint32_t u32IocPciAddress;
377 /** PCI address of the host bus controller device. */
378 uint32_t u32HbcPciAddress;
379
380 /** Physical address of PCI config space MMIO region */
381 uint64_t u64PciConfigMMioAddress;
382 /** Length of PCI config space MMIO region */
383 uint64_t u64PciConfigMMioLength;
384 /** Serial 0 IRQ number */
385 uint8_t uSerial0Irq;
386 /** Serial 1 IRQ number */
387 uint8_t uSerial1Irq;
388 /** Serial 2 IRQ number */
389 uint8_t uSerial2Irq;
390 /** Serial 3 IRQ number */
391 uint8_t uSerial3Irq;
392 /** Serial 0 IO port base */
393 RTIOPORT uSerial0IoPortBase;
394 /** Serial 1 IO port base */
395 RTIOPORT uSerial1IoPortBase;
396 /** Serial 2 IO port base */
397 RTIOPORT uSerial2IoPortBase;
398 /** Serial 3 IO port base */
399 RTIOPORT uSerial3IoPortBase;
400
401 /** @name Parallel port config bits
402 * @{ */
403 /** Parallel 0 IRQ number */
404 uint8_t uParallel0Irq;
405 /** Parallel 1 IRQ number */
406 uint8_t uParallel1Irq;
407 /** Parallel 0 IO port base */
408 RTIOPORT uParallel0IoPortBase;
409 /** Parallel 1 IO port base */
410 RTIOPORT uParallel1IoPortBase;
411 /** @} */
412
413 uint32_t Alignment2;
414
415 /** ACPI port base interface. */
416 PDMIBASE IBase;
417 /** ACPI port interface. */
418 PDMIACPIPORT IACPIPort;
419 /** Pointer to the device instance so we can get our bearings from
420 * interface functions. */
421 PPDMDEVINSR3 pDevIns;
422
423 /** Pointer to the driver base interface. */
424 R3PTRTYPE(PPDMIBASE) pDrvBase;
425 /** Pointer to the driver connector interface. */
426 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
427
428 /** Number of custom ACPI tables */
429 uint8_t cCustTbls;
430 /** ACPI OEM ID */
431 uint8_t au8OemId[6];
432 /** ACPI Crator ID */
433 uint8_t au8CreatorId[4];
434 /** ACPI Crator Rev */
435 uint32_t u32CreatorRev;
436 /** ACPI custom OEM Tab ID */
437 uint8_t au8OemTabId[8];
438 /** ACPI custom OEM Rev */
439 uint32_t u32OemRevision;
440 uint32_t Alignment4;
441
442 /** Custom ACPI tables binary data. */
443 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
444 /** The size of the custom table binary. */
445 uint64_t acbCustBin[MAX_CUST_TABLES];
446
447 /** SMBus Host Status Register */
448 uint8_t u8SMBusHstSts;
449 /** SMBus Slave Status Register */
450 uint8_t u8SMBusSlvSts;
451 /** SMBus Host Control Register */
452 uint8_t u8SMBusHstCnt;
453 /** SMBus Host Command Register */
454 uint8_t u8SMBusHstCmd;
455 /** SMBus Host Address Register */
456 uint8_t u8SMBusHstAdd;
457 /** SMBus Host Data 0 Register */
458 uint8_t u8SMBusHstDat0;
459 /** SMBus Host Data 1 Register */
460 uint8_t u8SMBusHstDat1;
461 /** SMBus Slave Control Register */
462 uint8_t u8SMBusSlvCnt;
463 /** SMBus Shadow Command Register */
464 uint8_t u8SMBusShdwCmd;
465 /** SMBus Slave Event Register */
466 uint16_t u16SMBusSlvEvt;
467 /** SMBus Slave Data Register */
468 uint16_t u16SMBusSlvDat;
469 /** SMBus Host Block Data Buffer */
470 uint8_t au8SMBusBlkDat[32];
471 /** SMBus Host Block Index */
472 uint8_t u8SMBusBlkIdx;
473
474 /** @todo DEBUGGING */
475 uint32_t uPmTimeOld;
476 uint32_t uPmTimeA;
477 uint32_t uPmTimeB;
478 uint32_t Alignment5;
479} ACPIState, ACPISTATE;
480/** Pointer to the shared ACPI device state. */
481typedef ACPISTATE *PACPISTATE;
482
483#pragma pack(1)
484
485/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
486struct ACPIGENADDR
487{
488 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
489 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
490 uint8_t u8RegisterBitOffset; /**< bit offset of register */
491 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
492 uint64_t u64Address; /**< 64-bit address of register */
493};
494AssertCompileSize(ACPIGENADDR, 12);
495
496/** Root System Description Pointer */
497struct ACPITBLRSDP
498{
499 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
500 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
501 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
502 uint8_t u8Revision; /**< revision number, currently 2 */
503#define ACPI_REVISION 2 /**< ACPI 3.0 */
504 uint32_t u32RSDT; /**< phys addr of RSDT */
505 uint32_t u32Length; /**< bytes of this table */
506 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
507 uint8_t u8ExtChecksum; /**< checksum of entire table */
508 uint8_t u8Reserved[3]; /**< reserved */
509};
510AssertCompileSize(ACPITBLRSDP, 36);
511
512/** System Description Table Header */
513struct ACPITBLHEADER
514{
515 uint8_t au8Signature[4]; /**< table identifier */
516 uint32_t u32Length; /**< length of the table including header */
517 uint8_t u8Revision; /**< revision number */
518 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
519 uint8_t au8OemId[6]; /**< OEM-supplied string */
520 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
521 uint32_t u32OemRevision; /**< OEM-supplied revision number */
522 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
523 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
524};
525AssertCompileSize(ACPITBLHEADER, 36);
526
527/** Root System Description Table */
528struct ACPITBLRSDT
529{
530 ACPITBLHEADER header;
531 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
532};
533AssertCompileSize(ACPITBLRSDT, 40);
534
535/** Extended System Description Table */
536struct ACPITBLXSDT
537{
538 ACPITBLHEADER header;
539 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
540};
541AssertCompileSize(ACPITBLXSDT, 44);
542
543/** Fixed ACPI Description Table */
544struct ACPITBLFADT
545{
546 ACPITBLHEADER header;
547 uint32_t u32FACS; /**< phys. address of FACS */
548 uint32_t u32DSDT; /**< phys. address of DSDT */
549 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
550#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
551#define INT_MODEL_MULTIPLE_APIC 2
552 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
553 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
554#define SCI_INT 9
555 uint32_t u32SMICmd; /**< system port address of SMI command port */
556#define SMI_CMD 0x0000442e
557 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
558#define ACPI_ENABLE 0xa1
559 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
560#define ACPI_DISABLE 0xa0
561 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
562 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
563 state control responsibility */
564 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
565 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
566 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
567 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
568 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
569 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
570 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
571 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
572 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
573 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
574 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
575 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
576 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
577#define GPE0_BLK_LEN 2
578 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
579#define GPE1_BLK_LEN 0
580 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
581#define GPE1_BASE 0
582 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
583 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
584#define P_LVL2_LAT 101 /**< C2 state not supported */
585 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
586#define P_LVL3_LAT 1001 /**< C3 state not supported */
587 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
588 lines from any processors memory caches */
589#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
590 uint16_t u16FlushStride; /**< cache line width */
591#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
592 uint8_t u8DutyOffset;
593 uint8_t u8DutyWidth;
594 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
595 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
596 uint8_t u8Century; /**< RTC CMOS RAM index of century */
597 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
598#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
599 (COM too?) */
600#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
601#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
602#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
603#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
604 uint8_t u8Must0_0; /**< must be 0 */
605 uint32_t u32Flags; /**< fixed feature flags */
606#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
607#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
608#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
609#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
610#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
611#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
612#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
613#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
614#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
615#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
616#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
617#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
618#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
619#define FADT_FL_CPU_SW_SLP RT_BIT(13)
620#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
621#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
622#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
623#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
624#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
625#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
626
627/* PM Timer mask and msb */
628#ifndef PM_TMR_32BIT
629#define TMR_VAL_MSB 0x800000
630#define TMR_VAL_MASK 0xffffff
631#undef FADT_FL_TMR_VAL_EXT
632#define FADT_FL_TMR_VAL_EXT 0
633#else
634#define TMR_VAL_MSB 0x80000000
635#define TMR_VAL_MASK 0xffffffff
636#endif
637
638 /** Start of the ACPI 2.0 extension. */
639 ACPIGENADDR ResetReg; /**< ext addr of reset register */
640 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
641#define ACPI_RESET_REG_VAL 0x10
642 uint8_t au8Must0_1[3]; /**< must be 0 */
643 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
644 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
645 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
646 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
647 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
648 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
649 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
650 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
651 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
652 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
653};
654AssertCompileSize(ACPITBLFADT, 244);
655#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
656
657/** Firmware ACPI Control Structure */
658struct ACPITBLFACS
659{
660 uint8_t au8Signature[4]; /**< 'FACS' */
661 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
662 uint32_t u32HWSignature; /**< systems HW signature at last boot */
663 uint32_t u32FWVector; /**< address of waking vector */
664 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
665 uint32_t u32Flags; /**< FACS flags */
666 uint64_t u64X_FWVector; /**< 64-bit waking vector */
667 uint8_t u8Version; /**< version of this table */
668 uint8_t au8Reserved[31]; /**< zero */
669};
670AssertCompileSize(ACPITBLFACS, 64);
671
672/** Processor Local APIC Structure */
673struct ACPITBLLAPIC
674{
675 uint8_t u8Type; /**< 0 = LAPIC */
676 uint8_t u8Length; /**< 8 */
677 uint8_t u8ProcId; /**< processor ID */
678 uint8_t u8ApicId; /**< local APIC ID */
679 uint32_t u32Flags; /**< Flags */
680#define LAPIC_ENABLED 0x1
681};
682AssertCompileSize(ACPITBLLAPIC, 8);
683
684/** I/O APIC Structure */
685struct ACPITBLIOAPIC
686{
687 uint8_t u8Type; /**< 1 == I/O APIC */
688 uint8_t u8Length; /**< 12 */
689 uint8_t u8IOApicId; /**< I/O APIC ID */
690 uint8_t u8Reserved; /**< 0 */
691 uint32_t u32Address; /**< phys address to access I/O APIC */
692 uint32_t u32GSIB; /**< global system interrupt number to start */
693};
694AssertCompileSize(ACPITBLIOAPIC, 12);
695
696/** Interrupt Source Override Structure */
697struct ACPITBLISO
698{
699 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
700 uint8_t u8Length; /**< 10 */
701 uint8_t u8Bus; /**< Bus */
702 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
703 uint32_t u32GSI; /**< Global System Interrupt */
704 uint16_t u16Flags; /**< MPS INTI flags Global */
705};
706AssertCompileSize(ACPITBLISO, 10);
707#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
708
709/** HPET Descriptor Structure */
710struct ACPITBLHPET
711{
712 ACPITBLHEADER aHeader;
713 uint32_t u32Id; /**< hardware ID of event timer block
714 [31:16] PCI vendor ID of first timer block
715 [15] legacy replacement IRQ routing capable
716 [14] reserved
717 [13] COUNT_SIZE_CAP counter size
718 [12:8] number of comparators in first timer block
719 [7:0] hardware rev ID */
720 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
721 uint8_t u32Number; /**< sequence number starting at 0 */
722 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
723 lost interrupts while the counter is programmed
724 to operate in periodic mode. Unit: clock tick. */
725 uint8_t u8Attributes; /**< page protection and OEM attribute. */
726};
727AssertCompileSize(ACPITBLHPET, 56);
728
729/** MCFG Descriptor Structure */
730typedef struct ACPITBLMCFG
731{
732 ACPITBLHEADER aHeader;
733 uint64_t u64Reserved;
734} ACPITBLMCFG;
735AssertCompileSize(ACPITBLMCFG, 44);
736
737/** Number of such entries can be computed from the whole table length in header */
738typedef struct ACPITBLMCFGENTRY
739{
740 uint64_t u64BaseAddress;
741 uint16_t u16PciSegmentGroup;
742 uint8_t u8StartBus;
743 uint8_t u8EndBus;
744 uint32_t u32Reserved;
745} ACPITBLMCFGENTRY;
746AssertCompileSize(ACPITBLMCFGENTRY, 16);
747
748#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
749
750/** Custom Description Table */
751struct ACPITBLCUST
752{
753 ACPITBLHEADER header;
754 uint8_t au8Data[476];
755};
756AssertCompileSize(ACPITBLCUST, 512);
757
758
759#pragma pack()
760
761
762#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
763
764
765/*********************************************************************************************************************************
766* Internal Functions *
767*********************************************************************************************************************************/
768RT_C_DECLS_BEGIN
769PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
770RT_C_DECLS_END
771#ifdef IN_RING3
772static int acpiR3PlantTables(PPDMDEVINS pDevIns, ACPIState *pThis);
773#endif
774
775/* SCI, usually IRQ9 */
776DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
777{
778 PDMDevHlpPCISetIrq(pDevIns, 0, level);
779}
780
781DECLINLINE(bool) pm1a_level(ACPIState *pThis)
782{
783 return (pThis->pm1a_ctl & SCI_EN)
784 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
785}
786
787DECLINLINE(bool) gpe0_level(ACPIState *pThis)
788{
789 return !!(pThis->gpe0_en & pThis->gpe0_sts);
790}
791
792DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, ACPIState *pThis)
793{
794 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
795 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
796 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
797 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
798 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
799}
800
801DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, ACPIState *pThis)
802{
803 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
804}
805
806/**
807 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
808 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
809 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
810 * registers and trigger IRQs.
811 *
812 * Caller must hold the state lock.
813 *
814 * @param pDevIns The PDM device instance.
815 * @param pThis The ACPI shared instance data.
816 * @param sts The new PM1a.STS value.
817 * @param en The new PM1a.EN value.
818 */
819static void acpiUpdatePm1a(PPDMDEVINS pDevIns, ACPIState *pThis, uint32_t sts, uint32_t en)
820{
821 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
822
823 const bool old_level = acpiSCILevel(pDevIns, pThis);
824 pThis->pm1a_en = en;
825 pThis->pm1a_sts = sts;
826 const bool new_level = acpiSCILevel(pDevIns, pThis);
827
828 LogFunc(("old=%x new=%x\n", old_level, new_level));
829
830 if (new_level != old_level)
831 acpiSetIrq(pDevIns, new_level);
832}
833
834#ifdef IN_RING3
835
836/**
837 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
838 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
839 *
840 * Caller must hold the state lock.
841 *
842 * @param pDevIns The PDM device instance.
843 * @param pThis The ACPI shared instance data.
844 * @param sts The new GPE0.STS value.
845 * @param en The new GPE0.EN value.
846 */
847static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, ACPIState *pThis, uint32_t sts, uint32_t en)
848{
849 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
850
851 const bool old_level = acpiSCILevel(pDevIns, pThis);
852 pThis->gpe0_en = en;
853 pThis->gpe0_sts = sts;
854 const bool new_level = acpiSCILevel(pDevIns, pThis);
855
856 LogFunc(("old=%x new=%x\n", old_level, new_level));
857
858 if (new_level != old_level)
859 acpiSetIrq(pDevIns, new_level);
860}
861
862/**
863 * Used by acpiR3PM1aCtlWrite to power off the VM.
864 *
865 * @param pDevIns The device instance.
866 * @returns Strict VBox status code.
867 */
868static int acpiR3DoPowerOff(PPDMDEVINS pDevIns)
869{
870 int rc = PDMDevHlpVMPowerOff(pDevIns);
871 AssertRC(rc);
872 return rc;
873}
874
875/**
876 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
877 *
878 * @param pDevIns The device instance.
879 * @param pThis The ACPI shared instance data.
880 * @returns Strict VBox status code.
881 */
882static int acpiR3DoSleep(PPDMDEVINS pDevIns, ACPIState *pThis)
883{
884 /* We must set WAK_STS on resume (includes restore) so the guest knows that
885 we've woken up and can continue executing code. The guest is probably
886 reading the PMSTS register in a loop to check this. */
887 int rc;
888 pThis->fSetWakeupOnResume = true;
889 if (pThis->fSuspendToSavedState)
890 {
891 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
892 if (rc != VERR_NOT_SUPPORTED)
893 AssertRC(rc);
894 else
895 {
896 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
897 rc = PDMDevHlpVMSuspend(pDevIns);
898 AssertRC(rc);
899 }
900 }
901 else
902 {
903 rc = PDMDevHlpVMSuspend(pDevIns);
904 AssertRC(rc);
905 }
906 return rc;
907}
908
909
910/**
911 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
912 */
913static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
914{
915 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
916 PPDMDEVINS pDevIns = pThis->pDevIns;
917 DEVACPI_LOCK_R3(pDevIns, pThis);
918
919 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
920 pThis->fPowerButtonHandled = false;
921 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
922
923 DEVACPI_UNLOCK(pDevIns, pThis);
924 return VINF_SUCCESS;
925}
926
927/**
928 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
929 */
930static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
931{
932 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
933 PPDMDEVINS pDevIns = pThis->pDevIns;
934 DEVACPI_LOCK_R3(pDevIns, pThis);
935
936 *pfHandled = pThis->fPowerButtonHandled;
937
938 DEVACPI_UNLOCK(pDevIns, pThis);
939 return VINF_SUCCESS;
940}
941
942/**
943 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
944 * Guest entered into G0 (working) or G1 (sleeping)}
945 */
946static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
947{
948 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
949 PPDMDEVINS pDevIns = pThis->pDevIns;
950 DEVACPI_LOCK_R3(pDevIns, pThis);
951
952 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
953
954 DEVACPI_UNLOCK(pDevIns, pThis);
955 return VINF_SUCCESS;
956}
957
958/**
959 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
960 */
961static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
962{
963 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
964 PPDMDEVINS pDevIns = pThis->pDevIns;
965 DEVACPI_LOCK_R3(pDevIns, pThis);
966
967 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
968
969 DEVACPI_UNLOCK(pDevIns, pThis);
970 return VINF_SUCCESS;
971}
972
973/**
974 * Send an ACPI sleep button event.
975 *
976 * @returns VBox status code
977 * @param pInterface Pointer to the interface structure containing the called function pointer.
978 */
979static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
980{
981 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
982 PPDMDEVINS pDevIns = pThis->pDevIns;
983 DEVACPI_LOCK_R3(pDevIns, pThis);
984
985 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
986
987 DEVACPI_UNLOCK(pDevIns, pThis);
988 return VINF_SUCCESS;
989}
990
991/**
992 * Send an ACPI monitor hot-plug event.
993 *
994 * @returns VBox status code
995 * @param pInterface Pointer to the interface structure containing the
996 * called function pointer.
997 */
998static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
999{
1000 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
1001 PPDMDEVINS pDevIns = pThis->pDevIns;
1002 DEVACPI_LOCK_R3(pDevIns, pThis);
1003
1004 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1005
1006 DEVACPI_UNLOCK(pDevIns, pThis);
1007 return VINF_SUCCESS;
1008}
1009
1010/**
1011 * Send an ACPI battery status change event.
1012 *
1013 * @returns VBox status code
1014 * @param pInterface Pointer to the interface structure containing the
1015 * called function pointer.
1016 */
1017static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1018{
1019 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
1020 PPDMDEVINS pDevIns = pThis->pDevIns;
1021 DEVACPI_LOCK_R3(pDevIns, pThis);
1022
1023 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1024
1025 DEVACPI_UNLOCK(pDevIns, pThis);
1026 return VINF_SUCCESS;
1027}
1028
1029/**
1030 * Used by acpiR3PmTimer to re-arm the PM timer.
1031 *
1032 * The caller is expected to either hold the clock lock or to have made sure
1033 * the VM is resetting or loading state.
1034 *
1035 * @param pDevIns The device instance.
1036 * @param pThis The ACPI shared instance data.
1037 * @param uNow The current time.
1038 */
1039static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, ACPIState *pThis, uint64_t uNow)
1040{
1041 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1042 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1043 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1044 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1045 Log(("acpi: uInterval = %RU64\n", uInterval));
1046}
1047
1048#endif /* IN_RING3 */
1049
1050/**
1051 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1052 *
1053 * The caller is expected to either hold the clock lock or to have made sure
1054 * the VM is resetting or loading state.
1055 *
1056 * @param pDevIns The PDM device instance.
1057 * @param pThis The ACPI instance
1058 * @param u64Now The current time
1059 */
1060static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, ACPIState *pThis, uint64_t u64Now)
1061{
1062 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1063 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1064 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1065
1066 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ,
1067 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1068 & TMR_VAL_MASK;
1069
1070 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1071 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1072}
1073
1074#ifdef IN_RING3
1075
1076/**
1077 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1078 */
1079static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1080{
1081 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1082 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1083 RT_NOREF(pTimer, pvUser);
1084
1085 DEVACPI_LOCK_R3(pDevIns, pThis);
1086 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1087 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1088 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1089 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1090 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1091 DEVACPI_UNLOCK(pDevIns, pThis);
1092
1093 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
1094}
1095
1096/**
1097 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1098 * acpiR3LoadState.
1099 *
1100 * @returns VINF_SUCCESS.
1101 * @param pThis The ACPI shared instance data.
1102 */
1103static int acpiR3FetchBatteryStatus(ACPIState *pThis)
1104{
1105 uint32_t *p = pThis->au8BatteryInfo;
1106 bool fPresent; /* battery present? */
1107 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1108 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1109 uint32_t hostPresentRate; /* 0..1000 */
1110 int rc;
1111
1112 if (!pThis->pDrv)
1113 return VINF_SUCCESS;
1114 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
1115 &hostBatteryState, &hostPresentRate);
1116 AssertRC(rc);
1117
1118 /* default values */
1119 p[BAT_STATUS_STATE] = hostBatteryState;
1120 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1121 : hostPresentRate * 50; /* mW */
1122 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1123 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1124
1125 /* did we get a valid battery state? */
1126 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1127 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1128 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1129 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1130
1131 return VINF_SUCCESS;
1132}
1133
1134/**
1135 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1136 * acpiR3LoadState.
1137 *
1138 * @returns VINF_SUCCESS.
1139 * @param pThis The ACPI shared instance data.
1140 */
1141static int acpiR3FetchBatteryInfo(ACPIState *pThis)
1142{
1143 uint32_t *p = pThis->au8BatteryInfo;
1144
1145 p[BAT_INFO_UNITS] = 0; /* mWh */
1146 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1147 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1148 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1149 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1150 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1151 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1152 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1153 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1154
1155 return VINF_SUCCESS;
1156}
1157
1158/**
1159 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1160 *
1161 * @returns status mask or 0.
1162 * @param pThis The ACPI shared instance data.
1163 */
1164static uint32_t acpiR3GetBatteryDeviceStatus(ACPIState *pThis)
1165{
1166 bool fPresent; /* battery present? */
1167 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1168 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1169 uint32_t hostPresentRate; /* 0..1000 */
1170 int rc;
1171
1172 if (!pThis->pDrv)
1173 return 0;
1174 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
1175 &hostBatteryState, &hostPresentRate);
1176 AssertRC(rc);
1177
1178 return fPresent
1179 ? STA_DEVICE_PRESENT_MASK /* present */
1180 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1181 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1182 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1183 | STA_BATTERY_PRESENT_MASK /* battery is present */
1184 : 0; /* device not present */
1185}
1186
1187/**
1188 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1189 *
1190 * @returns status.
1191 * @param pThis The ACPI shared instance data.
1192 */
1193static uint32_t acpiR3GetPowerSource(ACPIState *pThis)
1194{
1195 /* query the current power source from the host driver */
1196 if (!pThis->pDrv)
1197 return AC_ONLINE;
1198
1199 PDMACPIPOWERSOURCE ps;
1200 int rc = pThis->pDrv->pfnQueryPowerSource(pThis->pDrv, &ps);
1201 AssertRC(rc);
1202 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1203}
1204
1205/**
1206 * @callback_method_impl{FNIOMIOPORTOUT, Battery status index}
1207 */
1208PDMBOTHCBDECL(int) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1209{
1210 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1211 if (cb != 4)
1212 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1213
1214 ACPIState *pThis = (ACPIState *)pvUser;
1215 DEVACPI_LOCK_R3(pDevIns, pThis);
1216
1217 u32 >>= pThis->u8IndexShift;
1218 /* see comment at the declaration of u8IndexShift */
1219 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1220 {
1221 pThis->u8IndexShift = 2;
1222 u32 >>= 2;
1223 }
1224 Assert(u32 < BAT_INDEX_LAST);
1225 pThis->uBatteryIndex = u32;
1226
1227 DEVACPI_UNLOCK(pDevIns, pThis);
1228 return VINF_SUCCESS;
1229}
1230
1231/**
1232 * @callback_method_impl{FNIOMIOPORTIN, Battery status data}
1233 */
1234PDMBOTHCBDECL(int) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1235{
1236 if (cb != 4)
1237 return VERR_IOM_IOPORT_UNUSED;
1238
1239 ACPIState *pThis = (ACPIState *)pvUser;
1240 DEVACPI_LOCK_R3(pDevIns, pThis);
1241
1242 int rc = VINF_SUCCESS;
1243 switch (pThis->uBatteryIndex)
1244 {
1245 case BAT_STATUS_STATE:
1246 acpiR3FetchBatteryStatus(pThis);
1247 RT_FALL_THRU();
1248 case BAT_STATUS_PRESENT_RATE:
1249 case BAT_STATUS_REMAINING_CAPACITY:
1250 case BAT_STATUS_PRESENT_VOLTAGE:
1251 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1252 break;
1253
1254 case BAT_INFO_UNITS:
1255 acpiR3FetchBatteryInfo(pThis);
1256 RT_FALL_THRU();
1257 case BAT_INFO_DESIGN_CAPACITY:
1258 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1259 case BAT_INFO_TECHNOLOGY:
1260 case BAT_INFO_DESIGN_VOLTAGE:
1261 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1262 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1263 case BAT_INFO_CAPACITY_GRANULARITY_1:
1264 case BAT_INFO_CAPACITY_GRANULARITY_2:
1265 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1266 break;
1267
1268 case BAT_DEVICE_STATUS:
1269 *pu32 = acpiR3GetBatteryDeviceStatus(pThis);
1270 break;
1271
1272 case BAT_POWER_SOURCE:
1273 *pu32 = acpiR3GetPowerSource(pThis);
1274 break;
1275
1276 default:
1277 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1278 *pu32 = UINT32_MAX;
1279 break;
1280 }
1281
1282 DEVACPI_UNLOCK(pDevIns, pThis);
1283 return rc;
1284}
1285
1286/**
1287 * @callback_method_impl{FNIOMIOPORTOUT, System info index}
1288 */
1289PDMBOTHCBDECL(int) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1290{
1291 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1292 if (cb != 4)
1293 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1294
1295 ACPIState *pThis = (ACPIState *)pvUser;
1296 DEVACPI_LOCK_R3(pDevIns, pThis);
1297
1298 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1299 pThis->uSystemInfoIndex = u32;
1300 else
1301 {
1302 /* see comment at the declaration of u8IndexShift */
1303 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1304 {
1305 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1306 pThis->u8IndexShift = 2;
1307 }
1308
1309 u32 >>= pThis->u8IndexShift;
1310 Assert(u32 < SYSTEM_INFO_INDEX_END);
1311 pThis->uSystemInfoIndex = u32;
1312 }
1313
1314 DEVACPI_UNLOCK(pDevIns, pThis);
1315 return VINF_SUCCESS;
1316}
1317
1318/**
1319 * @callback_method_impl{FNIOMIOPORTIN, System info data}
1320 */
1321PDMBOTHCBDECL(int) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1322{
1323 if (cb != 4)
1324 return VERR_IOM_IOPORT_UNUSED;
1325
1326 ACPIState *pThis = (ACPIState *)pvUser;
1327 DEVACPI_LOCK_R3(pDevIns, pThis);
1328
1329 int rc = VINF_SUCCESS;
1330 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1331 switch (uSystemInfoIndex)
1332 {
1333 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1334 *pu32 = pThis->cbRamLow;
1335 break;
1336
1337 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1338 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1339 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1340 break;
1341
1342 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1343 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1344 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1345 break;
1346
1347 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1348 *pu32 = pThis->u8UseIOApic;
1349 break;
1350
1351 case SYSTEM_INFO_INDEX_HPET_STATUS:
1352 *pu32 = pThis->fUseHpet
1353 ? ( STA_DEVICE_PRESENT_MASK
1354 | STA_DEVICE_ENABLED_MASK
1355 | STA_DEVICE_SHOW_IN_UI_MASK
1356 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1357 : 0;
1358 break;
1359
1360 case SYSTEM_INFO_INDEX_SMC_STATUS:
1361 *pu32 = pThis->fUseSmc
1362 ? ( STA_DEVICE_PRESENT_MASK
1363 | STA_DEVICE_ENABLED_MASK
1364 /* no need to show this device in the UI */
1365 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1366 : 0;
1367 break;
1368
1369 case SYSTEM_INFO_INDEX_FDC_STATUS:
1370 *pu32 = pThis->fUseFdc
1371 ? ( STA_DEVICE_PRESENT_MASK
1372 | STA_DEVICE_ENABLED_MASK
1373 | STA_DEVICE_SHOW_IN_UI_MASK
1374 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1375 : 0;
1376 break;
1377
1378 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1379 *pu32 = pThis->u32NicPciAddress;
1380 break;
1381
1382 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1383 *pu32 = pThis->u32AudioPciAddress;
1384 break;
1385
1386 case SYSTEM_INFO_INDEX_POWER_STATES:
1387 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1388 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1389 *pu32 |= RT_BIT(1);
1390 if (pThis->fS4Enabled)
1391 *pu32 |= RT_BIT(4);
1392 break;
1393
1394 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1395 *pu32 = pThis->u32IocPciAddress;
1396 break;
1397
1398 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1399 *pu32 = pThis->u32HbcPciAddress;
1400 break;
1401
1402 case SYSTEM_INFO_INDEX_PCI_BASE:
1403 /** @todo couldn't MCFG be in 64-bit range? */
1404 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1405 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1406 break;
1407
1408 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1409 /** @todo couldn't MCFG be in 64-bit range? */
1410 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1411 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1412 break;
1413
1414 case SYSTEM_INFO_INDEX_RTC_STATUS:
1415 *pu32 = pThis->fShowRtc
1416 ? ( STA_DEVICE_PRESENT_MASK
1417 | STA_DEVICE_ENABLED_MASK
1418 | STA_DEVICE_SHOW_IN_UI_MASK
1419 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1420 : 0;
1421 break;
1422
1423 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1424 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1425 {
1426 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1427 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1428 }
1429 else
1430 {
1431 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1432 pThis->idCpuLockCheck);
1433 /* Always return locked status just to be safe */
1434 *pu32 = 1;
1435 }
1436 break;
1437
1438 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1439 *pu32 = pThis->u32CpuEventType;
1440 break;
1441
1442 case SYSTEM_INFO_INDEX_CPU_EVENT:
1443 *pu32 = pThis->u32CpuEvent;
1444 break;
1445
1446 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1447 *pu32 = pThis->uSerial0IoPortBase;
1448 break;
1449
1450 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1451 *pu32 = pThis->uSerial0Irq;
1452 break;
1453
1454 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1455 *pu32 = pThis->uSerial1IoPortBase;
1456 break;
1457
1458 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1459 *pu32 = pThis->uSerial1Irq;
1460 break;
1461
1462 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1463 *pu32 = pThis->uSerial2IoPortBase;
1464 break;
1465
1466 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1467 *pu32 = pThis->uSerial2Irq;
1468 break;
1469
1470 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1471 *pu32 = pThis->uSerial3IoPortBase;
1472 break;
1473
1474 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1475 *pu32 = pThis->uSerial3Irq;
1476 break;
1477
1478 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1479 *pu32 = pThis->uParallel0IoPortBase;
1480 break;
1481
1482 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1483 *pu32 = pThis->uParallel0Irq;
1484 break;
1485
1486 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1487 *pu32 = pThis->uParallel1IoPortBase;
1488 break;
1489
1490 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1491 *pu32 = pThis->uParallel1Irq;
1492 break;
1493
1494 case SYSTEM_INFO_INDEX_END:
1495 /** @todo why isn't this setting any output value? */
1496 break;
1497
1498 /* Solaris 9 tries to read from this index */
1499 case SYSTEM_INFO_INDEX_INVALID:
1500 *pu32 = 0;
1501 break;
1502
1503 default:
1504 *pu32 = UINT32_MAX;
1505 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1506 break;
1507 }
1508
1509 DEVACPI_UNLOCK(pDevIns, pThis);
1510 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, rc));
1511 return rc;
1512}
1513
1514/**
1515 * @callback_method_impl{FNIOMIOPORTOUT, System info data}
1516 */
1517PDMBOTHCBDECL(int) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1518{
1519 ACPIState *pThis = (ACPIState *)pvUser;
1520 if (cb != 4)
1521 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1522
1523 DEVACPI_LOCK_R3(pDevIns, pThis);
1524 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, pThis->uSystemInfoIndex));
1525
1526 int rc = VINF_SUCCESS;
1527 switch (pThis->uSystemInfoIndex)
1528 {
1529 case SYSTEM_INFO_INDEX_INVALID:
1530 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1531 pThis->u8IndexShift = 0;
1532 break;
1533
1534 case SYSTEM_INFO_INDEX_VALID:
1535 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1536 pThis->u8IndexShift = 2;
1537 break;
1538
1539 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1540 pThis->idCpuLockCheck = u32;
1541 break;
1542
1543 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1544 if (u32 < pThis->cCpus)
1545 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1546 else
1547 LogRel(("ACPI: CPU %u does not exist\n", u32));
1548 break;
1549
1550 default:
1551 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1552 break;
1553 }
1554
1555 DEVACPI_UNLOCK(pDevIns, pThis);
1556 return rc;
1557}
1558
1559/**
1560 * @callback_method_impl{FNIOMIOPORTIN, PM1a Enable}
1561 */
1562PDMBOTHCBDECL(int) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1563{
1564 NOREF(pDevIns); NOREF(Port);
1565 if (cb != 2)
1566 return VERR_IOM_IOPORT_UNUSED;
1567
1568 ACPIState *pThis = (ACPIState *)pvUser;
1569 DEVACPI_LOCK_R3(pDevIns, pThis);
1570
1571 *pu32 = pThis->pm1a_en;
1572
1573 DEVACPI_UNLOCK(pDevIns, pThis);
1574 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1575 return VINF_SUCCESS;
1576}
1577
1578/**
1579 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Enable}
1580 */
1581PDMBOTHCBDECL(int) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1582{
1583 if (cb != 2 && cb != 4)
1584 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1585
1586 ACPIState *pThis = (ACPIState *)pvUser;
1587 DEVACPI_LOCK_R3(pDevIns, pThis);
1588
1589 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1590 u32 &= ~(RSR_EN | IGN_EN);
1591 u32 &= 0xffff;
1592 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1593
1594 DEVACPI_UNLOCK(pDevIns, pThis);
1595 return VINF_SUCCESS;
1596}
1597
1598/**
1599 * @callback_method_impl{FNIOMIOPORTIN, PM1a Status}
1600 */
1601PDMBOTHCBDECL(int) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1602{
1603 if (cb != 2)
1604 {
1605 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1606 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1607 }
1608
1609 ACPIState *pThis = (ACPIState *)pvUser;
1610 DEVACPI_LOCK_R3(pDevIns, pThis);
1611
1612 *pu32 = pThis->pm1a_sts;
1613
1614 DEVACPI_UNLOCK(pDevIns, pThis);
1615 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1616 return VINF_SUCCESS;
1617}
1618
1619/**
1620 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Status}
1621 */
1622PDMBOTHCBDECL(int) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1623{
1624 if (cb != 2 && cb != 4)
1625 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1626
1627 ACPIState *pThis = (ACPIState *)pvUser;
1628 DEVACPI_LOCK_R3(pDevIns, pThis);
1629
1630 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1631 u32 &= 0xffff;
1632 if (u32 & PWRBTN_STS)
1633 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1634 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1635 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1636
1637 DEVACPI_UNLOCK(pDevIns, pThis);
1638 return VINF_SUCCESS;
1639}
1640
1641/**
1642 * @callback_method_impl{FNIOMIOPORTIN, PM1a Control}
1643 */
1644PDMBOTHCBDECL(int) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1645{
1646 if (cb != 2)
1647 {
1648 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1649 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1650 }
1651
1652 ACPIState *pThis = (ACPIState *)pvUser;
1653 DEVACPI_LOCK_R3(pDevIns, pThis);
1654
1655 *pu32 = pThis->pm1a_ctl;
1656
1657 DEVACPI_UNLOCK(pDevIns, pThis);
1658 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1659 return VINF_SUCCESS;
1660}
1661
1662/**
1663 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Control}
1664 */
1665PDMBOTHCBDECL(int) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1666{
1667 if (cb != 2 && cb != 4)
1668 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1669
1670 ACPIState *pThis = (ACPIState *)pvUser;
1671 DEVACPI_LOCK_R3(pDevIns, pThis);
1672
1673 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1674 u32 &= 0xffff;
1675 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1676
1677 int rc = VINF_SUCCESS;
1678 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1679 if (uSleepState != pThis->uSleepState)
1680 {
1681 pThis->uSleepState = uSleepState;
1682 switch (uSleepState)
1683 {
1684 case 0x00: /* S0 */
1685 break;
1686
1687 case 0x01: /* S1 */
1688 if (pThis->fS1Enabled)
1689 {
1690 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1691 rc = acpiR3DoSleep(pDevIns, pThis);
1692 break;
1693 }
1694 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1695 RT_FALL_THRU();
1696
1697 case 0x04: /* S4 */
1698 if (pThis->fS4Enabled)
1699 {
1700 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1701 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1702 break;
1703 }
1704 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1705 RT_FALL_THRU();
1706
1707 case 0x05: /* S5 */
1708 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1709 rc = acpiR3DoPowerOff(pDevIns);
1710 break;
1711
1712 default:
1713 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1714 break;
1715 }
1716 }
1717
1718 DEVACPI_UNLOCK(pDevIns, pThis);
1719 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", rc));
1720 return rc;
1721}
1722
1723#endif /* IN_RING3 */
1724
1725/**
1726 * @callback_method_impl{FNIOMIOPORTIN, PMTMR}
1727 *
1728 * @remarks Only I/O port currently implemented in all contexts.
1729 */
1730PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1731{
1732 if (cb != 4)
1733 return VERR_IOM_IOPORT_UNUSED;
1734
1735 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1736
1737 /*
1738 * We use the clock lock to serialize access to u64PmTimerInitial and to
1739 * make sure we get a reliable time from the clock
1740 * as well as and to prevent uPmTimerVal from being updated during read.
1741 */
1742
1743 int rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VINF_IOM_R3_IOPORT_READ);
1744 if (rc == VINF_SUCCESS)
1745 {
1746 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1747 if (rc == VINF_SUCCESS)
1748 {
1749 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1750 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1751 *pu32 = pThis->uPmTimerVal;
1752
1753 DEVACPI_UNLOCK(pDevIns, pThis);
1754 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
1755
1756 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1757 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1758
1759#if 0
1760 /** @todo temporary: sanity check against running backwards */
1761 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1762 if (*pu32 - uOld >= 0x10000000)
1763 {
1764# if defined(IN_RING0)
1765 pThis->uPmTimeA = uOld;
1766 pThis->uPmTimeB = *pu32;
1767 return VERR_TM_TIMER_BAD_CLOCK;
1768# elif defined(IN_RING3)
1769 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1770# endif
1771 }
1772#endif
1773 }
1774 else
1775 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
1776 }
1777 NOREF(pvUser); NOREF(Port);
1778 return rc;
1779}
1780
1781#ifdef IN_RING3
1782
1783static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1784{
1785 RT_NOREF(pszArgs);
1786 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1787 pHlp->pfnPrintf(pHlp,
1788 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
1789}
1790
1791/**
1792 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Status}
1793 */
1794PDMBOTHCBDECL(int) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1795{
1796 if (cb != 1)
1797 {
1798 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1799 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1800 }
1801
1802 ACPIState *pThis = (ACPIState *)pvUser;
1803 DEVACPI_LOCK_R3(pDevIns, pThis);
1804
1805 *pu32 = pThis->gpe0_sts & 0xff;
1806
1807 DEVACPI_UNLOCK(pDevIns, pThis);
1808 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1809 return VINF_SUCCESS;
1810}
1811
1812/**
1813 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Status}
1814 */
1815PDMBOTHCBDECL(int) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1816{
1817 if (cb != 1)
1818 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1819
1820 ACPIState *pThis = (ACPIState *)pvUser;
1821 DEVACPI_LOCK_R3(pDevIns, pThis);
1822
1823 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1824 u32 = pThis->gpe0_sts & ~u32;
1825 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1826
1827 DEVACPI_UNLOCK(pDevIns, pThis);
1828 return VINF_SUCCESS;
1829}
1830
1831/**
1832 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Enable}
1833 */
1834PDMBOTHCBDECL(int) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1835{
1836 if (cb != 1)
1837 {
1838 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1839 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1840 }
1841
1842 ACPIState *pThis = (ACPIState *)pvUser;
1843 DEVACPI_LOCK_R3(pDevIns, pThis);
1844
1845 *pu32 = pThis->gpe0_en & 0xff;
1846
1847 DEVACPI_UNLOCK(pDevIns, pThis);
1848 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1849 return VINF_SUCCESS;
1850}
1851
1852/**
1853 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Enable}
1854 */
1855PDMBOTHCBDECL(int) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1856{
1857 if (cb != 1)
1858 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1859
1860 ACPIState *pThis = (ACPIState *)pvUser;
1861 DEVACPI_LOCK_R3(pDevIns, pThis);
1862
1863 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1864 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
1865
1866 DEVACPI_UNLOCK(pDevIns, pThis);
1867 return VINF_SUCCESS;
1868}
1869
1870/**
1871 * @callback_method_impl{FNIOMIOPORTOUT, SMI_CMD}
1872 */
1873PDMBOTHCBDECL(int) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1874{
1875 Log(("acpiR3SmiWrite %#x\n", u32));
1876 if (cb != 1)
1877 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1878
1879 ACPIState *pThis = (ACPIState *)pvUser;
1880 DEVACPI_LOCK_R3(pDevIns, pThis);
1881
1882 if (u32 == ACPI_ENABLE)
1883 pThis->pm1a_ctl |= SCI_EN;
1884 else if (u32 == ACPI_DISABLE)
1885 pThis->pm1a_ctl &= ~SCI_EN;
1886 else
1887 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1888
1889 DEVACPI_UNLOCK(pDevIns, pThis);
1890 return VINF_SUCCESS;
1891}
1892
1893/**
1894 * @callback_method_impl{FNIOMIOPORTOUT, ACPI_RESET_BLK}
1895 */
1896PDMBOTHCBDECL(int) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1897{
1898 Log(("acpiR3ResetWrite: %#x\n", u32));
1899 NOREF(pvUser);
1900 if (cb != 1)
1901 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1902
1903 /* No state locking required. */
1904 int rc = VINF_SUCCESS;
1905 if (u32 == ACPI_RESET_REG_VAL)
1906 {
1907 LogRel(("ACPI: Reset initiated by ACPI\n"));
1908 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
1909 }
1910 else
1911 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1912
1913 return rc;
1914}
1915
1916# ifdef DEBUG_ACPI
1917
1918/**
1919 * @callback_method_impl{FNIOMIOPORTOUT, Debug hex value logger}
1920 */
1921PDMBOTHCBDECL(int) acpiR3DhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1922{
1923 NOREF(pvUser);
1924 switch (cb)
1925 {
1926 case 1:
1927 Log(("%#x\n", u32 & 0xff));
1928 break;
1929 case 2:
1930 Log(("%#6x\n", u32 & 0xffff));
1931 break;
1932 case 4:
1933 Log(("%#10x\n", u32));
1934 break;
1935 default:
1936 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1937 }
1938 return VINF_SUCCESS;
1939}
1940
1941/**
1942 * @callback_method_impl{FNIOMIOPORTOUT, Debug char logger}
1943 */
1944PDMBOTHCBDECL(int) acpiR3DchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1945{
1946 NOREF(pvUser);
1947 switch (cb)
1948 {
1949 case 1:
1950 Log(("%c", u32 & 0xff));
1951 break;
1952 default:
1953 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1954 }
1955 return VINF_SUCCESS;
1956}
1957
1958# endif /* DEBUG_ACPI */
1959
1960/**
1961 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
1962 *
1963 * @param pDevIns The PDM device instance.
1964 * @param pThis The ACPI shared instance data.
1965 */
1966static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, ACPIState *pThis)
1967{
1968 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1969 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
1970 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
1971 pPciDev->abConfig[PMBA + 2] = 0x00;
1972 pPciDev->abConfig[PMBA + 3] = 0x00;
1973}
1974
1975/**
1976 * Used to calculate the value of a PM I/O port.
1977 *
1978 * @returns The actual I/O port value.
1979 * @param pThis The ACPI shared instance data.
1980 * @param offset The offset into the I/O space, or -1 if invalid.
1981 */
1982static RTIOPORT acpiR3CalcPmPort(ACPIState *pThis, int32_t offset)
1983{
1984 Assert(pThis->uPmIoPortBase != 0);
1985
1986 if (offset == -1)
1987 return 0;
1988
1989 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
1990}
1991
1992/**
1993 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to register the PM1a, PM
1994 * timer and GPE0 I/O ports.
1995 *
1996 * @returns VBox status code.
1997 * @param pDevIns The device instance.
1998 * @param pThis The ACPI shared instance data.
1999 */
2000static int acpiR3RegisterPmHandlers(PPDMDEVINS pDevIns, ACPIState *pThis)
2001{
2002 if (pThis->uPmIoPortBase == 0)
2003 return VINF_SUCCESS;
2004
2005#define R(offset, cnt, writer, reader, description) \
2006 do { \
2007 int rc = PDMDevHlpIOPortRegister(pDevIns, acpiR3CalcPmPort(pThis, offset), cnt, pThis, writer, reader, \
2008 NULL, NULL, description); \
2009 if (RT_FAILURE(rc)) \
2010 return rc; \
2011 } while (0)
2012#define L (GPE0_BLK_LEN / 2)
2013
2014 R(PM1a_EVT_OFFSET+2, 1, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, "ACPI PM1a Enable");
2015 R(PM1a_EVT_OFFSET, 1, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, "ACPI PM1a Status");
2016 R(PM1a_CTL_OFFSET, 1, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, "ACPI PM1a Control");
2017 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
2018 R(GPE0_OFFSET + L, L, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, "ACPI GPE0 Enable");
2019 R(GPE0_OFFSET, L, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, "ACPI GPE0 Status");
2020#undef L
2021#undef R
2022
2023 /* register RC stuff */
2024 if (pDevIns->fRCEnabled)
2025 {
2026 int rc = PDMDevHlpIOPortRegisterRC(pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
2027 1, 0, NULL, "acpiPMTmrRead",
2028 NULL, NULL, "ACPI PM Timer");
2029 AssertRCReturn(rc, rc);
2030 }
2031
2032 /* register R0 stuff */
2033 if (pDevIns->fR0Enabled)
2034 {
2035 int rc = PDMDevHlpIOPortRegisterR0(pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
2036 1, 0, NULL, "acpiPMTmrRead",
2037 NULL, NULL, "ACPI PM Timer");
2038 AssertRCReturn(rc, rc);
2039 }
2040
2041 return VINF_SUCCESS;
2042}
2043
2044/**
2045 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unregister the PM1a, PM
2046 * timer and GPE0 I/O ports.
2047 *
2048 * @returns VBox status code.
2049 * @param pDevIns The device instance.
2050 * @param pThis The ACPI shared instance data.
2051 */
2052static int acpiR3UnregisterPmHandlers(PPDMDEVINS pDevIns, ACPIState *pThis)
2053{
2054 if (pThis->uPmIoPortBase == 0)
2055 return VINF_SUCCESS;
2056
2057#define U(offset, cnt) \
2058 do { \
2059 int rc = PDMDevHlpIOPortDeregister(pDevIns, acpiR3CalcPmPort(pThis, offset), cnt); \
2060 AssertRCReturn(rc, rc); \
2061 } while (0)
2062#define L (GPE0_BLK_LEN / 2)
2063
2064 U(PM1a_EVT_OFFSET+2, 1);
2065 U(PM1a_EVT_OFFSET, 1);
2066 U(PM1a_CTL_OFFSET, 1);
2067 U(PM_TMR_OFFSET, 1);
2068 U(GPE0_OFFSET + L, L);
2069 U(GPE0_OFFSET, L);
2070#undef L
2071#undef U
2072
2073 return VINF_SUCCESS;
2074}
2075
2076/**
2077 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2078 * PM1a, PM timer and GPE0 ports.
2079 *
2080 * @returns VBox status code.
2081 *
2082 * @param pDevIns The device instance.
2083 * @param pThis The ACPI shared instance data.
2084 * @param NewIoPortBase The new base address of the I/O ports.
2085 */
2086static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, ACPIState *pThis, RTIOPORT NewIoPortBase)
2087{
2088 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2089 if (NewIoPortBase != pThis->uPmIoPortBase)
2090 {
2091 int rc = acpiR3UnregisterPmHandlers(pDevIns, pThis);
2092 if (RT_FAILURE(rc))
2093 return rc;
2094
2095 pThis->uPmIoPortBase = NewIoPortBase;
2096
2097 rc = acpiR3RegisterPmHandlers(pDevIns, pThis);
2098 if (RT_FAILURE(rc))
2099 return rc;
2100
2101 /* We have to update FADT table acccording to the new base */
2102 rc = acpiR3PlantTables(pDevIns, pThis);
2103 AssertRC(rc);
2104 if (RT_FAILURE(rc))
2105 return rc;
2106 }
2107
2108 return VINF_SUCCESS;
2109}
2110
2111/**
2112 * @callback_method_impl{FNIOMIOPORTOUT, SMBus}
2113 */
2114PDMBOTHCBDECL(int) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2115{
2116 ACPIState *pThis = (ACPIState *)pvUser;
2117
2118 LogFunc(("Port=%#x u32=%#x cb=%u\n", Port, u32, cb));
2119 uint8_t off = Port & 0x000f;
2120 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2121 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2122 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
2123
2124 DEVACPI_LOCK_R3(pDevIns, pThis);
2125 switch (off)
2126 {
2127 case SMBHSTSTS_OFF:
2128 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2129 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2130 break;
2131 case SMBSLVSTS_OFF:
2132 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2133 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2134 break;
2135 case SMBHSTCNT_OFF:
2136 {
2137 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2138
2139 const bool old_level = acpiSCILevel(pDevIns, pThis);
2140 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2141 if (u32 & SMBHSTCNT_START)
2142 {
2143 /* Start, trigger error as this is a dummy implementation */
2144 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2145 }
2146 if (u32 & SMBHSTCNT_KILL)
2147 {
2148 /* Kill */
2149 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2150 }
2151 const bool new_level = acpiSCILevel(pDevIns, pThis);
2152
2153 LogFunc(("old=%x new=%x\n", old_level, new_level));
2154
2155 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2156 * needs to be implemented later if it ever becomes relevant. */
2157 if (new_level != old_level)
2158 acpiSetIrq(pDevIns, new_level);
2159 break;
2160 }
2161 case SMBHSTCMD_OFF:
2162 pThis->u8SMBusHstCmd = u32;
2163 break;
2164 case SMBHSTADD_OFF:
2165 pThis->u8SMBusHstAdd = u32;
2166 break;
2167 case SMBHSTDAT0_OFF:
2168 pThis->u8SMBusHstDat0 = u32;
2169 break;
2170 case SMBHSTDAT1_OFF:
2171 pThis->u8SMBusHstDat1 = u32;
2172 break;
2173 case SMBBLKDAT_OFF:
2174 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2175 pThis->u8SMBusBlkIdx++;
2176 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2177 break;
2178 case SMBSLVCNT_OFF:
2179 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2180 break;
2181 case SMBSHDWCMD_OFF:
2182 /* readonly register */
2183 break;
2184 case SMBSLVEVT_OFF:
2185 pThis->u16SMBusSlvEvt = u32;
2186 break;
2187 case SMBSLVDAT_OFF:
2188 /* readonly register */
2189 break;
2190 default:
2191 /* caught by the sanity check above */
2192 ;
2193 }
2194
2195 DEVACPI_UNLOCK(pDevIns, pThis);
2196 return VINF_SUCCESS;
2197}
2198
2199/**
2200 * @callback_method_impl{FNIOMIOPORTIN, SMBus}
2201 */
2202PDMBOTHCBDECL(int) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2203{
2204 RT_NOREF1(pDevIns);
2205 ACPIState *pThis = (ACPIState *)pvUser;
2206
2207 int rc = VINF_SUCCESS;
2208 LogFunc(("Port=%#x cb=%u\n", Port, cb));
2209 uint8_t off = Port & 0x000f;
2210 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2211 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2212 return VERR_IOM_IOPORT_UNUSED;
2213
2214 DEVACPI_LOCK_R3(pDevIns, pThis);
2215 switch (off)
2216 {
2217 case SMBHSTSTS_OFF:
2218 *pu32 = pThis->u8SMBusHstSts;
2219 break;
2220 case SMBSLVSTS_OFF:
2221 *pu32 = pThis->u8SMBusSlvSts;
2222 break;
2223 case SMBHSTCNT_OFF:
2224 pThis->u8SMBusBlkIdx = 0;
2225 *pu32 = pThis->u8SMBusHstCnt;
2226 break;
2227 case SMBHSTCMD_OFF:
2228 *pu32 = pThis->u8SMBusHstCmd;
2229 break;
2230 case SMBHSTADD_OFF:
2231 *pu32 = pThis->u8SMBusHstAdd;
2232 break;
2233 case SMBHSTDAT0_OFF:
2234 *pu32 = pThis->u8SMBusHstDat0;
2235 break;
2236 case SMBHSTDAT1_OFF:
2237 *pu32 = pThis->u8SMBusHstDat1;
2238 break;
2239 case SMBBLKDAT_OFF:
2240 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2241 pThis->u8SMBusBlkIdx++;
2242 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2243 break;
2244 case SMBSLVCNT_OFF:
2245 *pu32 = pThis->u8SMBusSlvCnt;
2246 break;
2247 case SMBSHDWCMD_OFF:
2248 *pu32 = pThis->u8SMBusShdwCmd;
2249 break;
2250 case SMBSLVEVT_OFF:
2251 *pu32 = pThis->u16SMBusSlvEvt;
2252 break;
2253 case SMBSLVDAT_OFF:
2254 *pu32 = pThis->u16SMBusSlvDat;
2255 break;
2256 default:
2257 /* caught by the sanity check above */
2258 rc = VERR_IOM_IOPORT_UNUSED;
2259 }
2260
2261 DEVACPI_UNLOCK(pDevIns, pThis);
2262 LogFunc(("Port=%#x u32=%#x cb=%u rc=%Rrc\n", Port, *pu32, cb, rc));
2263 return rc;
2264}
2265
2266/**
2267 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2268 *
2269 * @param pDevIns The PDM device instance.
2270 * @param pThis The ACPI shared instance data.
2271 */
2272static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, ACPIState *pThis)
2273{
2274 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2275 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2276 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2277 pPciDev->abConfig[SMBBA+2] = 0x00;
2278 pPciDev->abConfig[SMBBA+3] = 0x00;
2279 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2280 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2281 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2282 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2283 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2284}
2285
2286/**
2287 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2288 *
2289 * @param pThis The ACPI shared instance data.
2290 */
2291static void acpiR3SMBusResetDevice(ACPIState *pThis)
2292{
2293 pThis->u8SMBusHstSts = 0x00;
2294 pThis->u8SMBusSlvSts = 0x00;
2295 pThis->u8SMBusHstCnt = 0x00;
2296 pThis->u8SMBusHstCmd = 0x00;
2297 pThis->u8SMBusHstAdd = 0x00;
2298 pThis->u8SMBusHstDat0 = 0x00;
2299 pThis->u8SMBusHstDat1 = 0x00;
2300 pThis->u8SMBusSlvCnt = 0x00;
2301 pThis->u8SMBusShdwCmd = 0x00;
2302 pThis->u16SMBusSlvEvt = 0x0000;
2303 pThis->u16SMBusSlvDat = 0x0000;
2304 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2305 pThis->u8SMBusBlkIdx = 0;
2306}
2307
2308/**
2309 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to register the SMBus ports.
2310 *
2311 * @returns VBox status code.
2312 * @param pDevIns The device instance.
2313 * @param pThis The ACPI shared instance data.
2314 */
2315static int acpiR3RegisterSMBusHandlers(PPDMDEVINS pDevIns, ACPIState *pThis)
2316{
2317 if (pThis->uSMBusIoPortBase == 0)
2318 return VINF_SUCCESS;
2319
2320 int rc = PDMDevHlpIOPortRegister(pDevIns, pThis->uSMBusIoPortBase, 16, pThis, acpiR3SMBusWrite, acpiR3SMBusRead, NULL, NULL, "SMBus");
2321 if (RT_FAILURE(rc))
2322 return rc;
2323
2324 return VINF_SUCCESS;
2325}
2326
2327/**
2328 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unregister the SMBus ports.
2329 *
2330 * @returns VBox status code.
2331 * @param pDevIns The device instance.
2332 * @param pThis The ACPI shared instance data.
2333 */
2334static int acpiR3UnregisterSMBusHandlers(PPDMDEVINS pDevIns, ACPIState *pThis)
2335{
2336 if (pThis->uSMBusIoPortBase == 0)
2337 return VINF_SUCCESS;
2338
2339 int rc = PDMDevHlpIOPortDeregister(pDevIns, pThis->uSMBusIoPortBase, 16);
2340 AssertRCReturn(rc, rc);
2341
2342 return VINF_SUCCESS;
2343}
2344
2345/**
2346 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2347 * SMBus ports.
2348 *
2349 * @returns VBox status code.
2350 *
2351 * @param pDevIns The device instance.
2352 * @param pThis The ACPI shared instance data.
2353 * @param NewIoPortBase The new base address of the I/O ports.
2354 */
2355static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, ACPIState *pThis, RTIOPORT NewIoPortBase)
2356{
2357 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2358 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2359 {
2360 int rc = acpiR3UnregisterSMBusHandlers(pDevIns, pThis);
2361 if (RT_FAILURE(rc))
2362 return rc;
2363
2364 pThis->uSMBusIoPortBase = NewIoPortBase;
2365
2366 rc = acpiR3RegisterSMBusHandlers(pDevIns, pThis);
2367 if (RT_FAILURE(rc))
2368 return rc;
2369
2370#if 0 /* is there an FADT table entry for the SMBus base? */
2371 /* We have to update FADT table acccording to the new base */
2372 rc = acpiR3PlantTables(pThis);
2373 AssertRC(rc);
2374 if (RT_FAILURE(rc))
2375 return rc;
2376#endif
2377 }
2378
2379 return VINF_SUCCESS;
2380}
2381
2382
2383/**
2384 * Saved state structure description, version 4.
2385 */
2386static const SSMFIELD g_AcpiSavedStateFields4[] =
2387{
2388 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2389 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2390 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2391 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2392 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2393 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2394 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2395 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2396 SSMFIELD_ENTRY(ACPIState, u64RamSize),
2397 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2398 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
2399 SSMFIELD_ENTRY(ACPIState, uSleepState),
2400 SSMFIELD_ENTRY_TERM()
2401};
2402
2403/**
2404 * Saved state structure description, version 5.
2405 */
2406static const SSMFIELD g_AcpiSavedStateFields5[] =
2407{
2408 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2409 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2410 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2411 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2412 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2413 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2414 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2415 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2416 SSMFIELD_ENTRY(ACPIState, uSleepState),
2417 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2418 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2419 SSMFIELD_ENTRY_TERM()
2420};
2421
2422/**
2423 * Saved state structure description, version 6.
2424 */
2425static const SSMFIELD g_AcpiSavedStateFields6[] =
2426{
2427 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2428 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2429 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2430 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2431 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2432 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2433 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2434 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2435 SSMFIELD_ENTRY(ACPIState, uSleepState),
2436 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2437 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2438 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2439 SSMFIELD_ENTRY_TERM()
2440};
2441
2442/**
2443 * Saved state structure description, version 7.
2444 */
2445static const SSMFIELD g_AcpiSavedStateFields7[] =
2446{
2447 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2448 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2449 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2450 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2451 SSMFIELD_ENTRY(ACPIState, uPmTimerVal),
2452 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2453 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2454 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2455 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2456 SSMFIELD_ENTRY(ACPIState, uSleepState),
2457 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2458 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2459 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2460 SSMFIELD_ENTRY_TERM()
2461};
2462
2463/**
2464 * Saved state structure description, version 8.
2465 */
2466static const SSMFIELD g_AcpiSavedStateFields8[] =
2467{
2468 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2469 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2470 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2471 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2472 SSMFIELD_ENTRY(ACPIState, uPmTimerVal),
2473 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2474 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2475 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2476 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2477 SSMFIELD_ENTRY(ACPIState, uSleepState),
2478 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2479 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2480 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2481 SSMFIELD_ENTRY(ACPIState, uSMBusIoPortBase),
2482 SSMFIELD_ENTRY(ACPIState, u8SMBusHstSts),
2483 SSMFIELD_ENTRY(ACPIState, u8SMBusSlvSts),
2484 SSMFIELD_ENTRY(ACPIState, u8SMBusHstCnt),
2485 SSMFIELD_ENTRY(ACPIState, u8SMBusHstCmd),
2486 SSMFIELD_ENTRY(ACPIState, u8SMBusHstAdd),
2487 SSMFIELD_ENTRY(ACPIState, u8SMBusHstDat0),
2488 SSMFIELD_ENTRY(ACPIState, u8SMBusHstDat1),
2489 SSMFIELD_ENTRY(ACPIState, u8SMBusSlvCnt),
2490 SSMFIELD_ENTRY(ACPIState, u8SMBusShdwCmd),
2491 SSMFIELD_ENTRY(ACPIState, u16SMBusSlvEvt),
2492 SSMFIELD_ENTRY(ACPIState, u16SMBusSlvDat),
2493 SSMFIELD_ENTRY(ACPIState, au8SMBusBlkDat),
2494 SSMFIELD_ENTRY(ACPIState, u8SMBusBlkIdx),
2495 SSMFIELD_ENTRY_TERM()
2496};
2497
2498/**
2499 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2500 */
2501static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2502{
2503 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2504 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2505 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2506}
2507
2508/**
2509 * @callback_method_impl{FNSSMDEVLOADEXEC}
2510 */
2511static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2512{
2513 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2514 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2515 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2516
2517 /*
2518 * Unregister PM handlers, will register with actual base after state
2519 * successfully loaded.
2520 */
2521 int rc = acpiR3UnregisterPmHandlers(pDevIns, pThis);
2522 if (RT_FAILURE(rc))
2523 return rc;
2524
2525 /*
2526 * Unregister SMBus handlers, will register with actual base after state
2527 * successfully loaded.
2528 */
2529 rc = acpiR3UnregisterSMBusHandlers(pDevIns, pThis);
2530 if (RT_FAILURE(rc))
2531 return rc;
2532 acpiR3SMBusResetDevice(pThis);
2533
2534 switch (uVersion)
2535 {
2536 case 4:
2537 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2538 break;
2539 case 5:
2540 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2541 break;
2542 case 6:
2543 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2544 break;
2545 case 7:
2546 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2547 break;
2548 case 8:
2549 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2550 break;
2551 default:
2552 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2553 break;
2554 }
2555 if (RT_SUCCESS(rc))
2556 {
2557 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2558 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2559 rc = acpiR3RegisterPmHandlers(pDevIns, pThis);
2560 if (RT_FAILURE(rc))
2561 return rc;
2562 rc = acpiR3RegisterSMBusHandlers(pDevIns, pThis);
2563 if (RT_FAILURE(rc))
2564 return rc;
2565 rc = acpiR3FetchBatteryStatus(pThis);
2566 if (RT_FAILURE(rc))
2567 return rc;
2568 rc = acpiR3FetchBatteryInfo(pThis);
2569 if (RT_FAILURE(rc))
2570 return rc;
2571 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2572 DEVACPI_LOCK_R3(pDevIns, pThis);
2573 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2574 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2575 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2576 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2577 DEVACPI_UNLOCK(pDevIns, pThis);
2578 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
2579 }
2580 return rc;
2581}
2582
2583/**
2584 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2585 */
2586static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2587{
2588 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IBase);
2589 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2590 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThis->IACPIPort);
2591 return NULL;
2592}
2593
2594/**
2595 * Calculate the check sum for some ACPI data before planting it.
2596 *
2597 * All the bytes must add up to 0.
2598 *
2599 * @returns check sum.
2600 * @param pvSrc What to check sum.
2601 * @param cbData The amount of data to checksum.
2602 */
2603static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2604{
2605 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2606 uint8_t uSum = 0;
2607 for (size_t i = 0; i < cbData; ++i)
2608 uSum += pbSrc[i];
2609 return -uSum;
2610}
2611
2612/**
2613 * Prepare a ACPI table header.
2614 */
2615static void acpiR3PrepareHeader(ACPIState *pThis, ACPITBLHEADER *header,
2616 const char au8Signature[4],
2617 uint32_t u32Length, uint8_t u8Revision)
2618{
2619 memcpy(header->au8Signature, au8Signature, 4);
2620 header->u32Length = RT_H2LE_U32(u32Length);
2621 header->u8Revision = u8Revision;
2622 memcpy(header->au8OemId, pThis->au8OemId, 6);
2623 memcpy(header->au8OemTabId, "VBOX", 4);
2624 memcpy(header->au8OemTabId+4, au8Signature, 4);
2625 header->u32OemRevision = RT_H2LE_U32(1);
2626 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2627 header->u32CreatorRev = pThis->u32CreatorRev;
2628}
2629
2630/**
2631 * Initialize a generic address structure (ACPIGENADDR).
2632 */
2633static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2634 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2635 uint8_t u8AccessSize, uint64_t u64Address)
2636{
2637 g->u8AddressSpaceId = u8AddressSpaceId;
2638 g->u8RegisterBitWidth = u8RegisterBitWidth;
2639 g->u8RegisterBitOffset = u8RegisterBitOffset;
2640 g->u8AccessSize = u8AccessSize;
2641 g->u64Address = RT_H2LE_U64(u64Address);
2642}
2643
2644/**
2645 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2646 */
2647DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2648{
2649 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2650}
2651
2652/**
2653 * Plant the Differentiated System Description Table (DSDT).
2654 */
2655static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2656{
2657 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2658}
2659
2660/**
2661 * Plant the Secondary System Description Table (SSDT).
2662 */
2663static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2664{
2665 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2666}
2667
2668/**
2669 * Plant the Firmware ACPI Control Structure (FACS).
2670 */
2671static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2672{
2673 ACPITBLFACS facs;
2674
2675 memset(&facs, 0, sizeof(facs));
2676 memcpy(facs.au8Signature, "FACS", 4);
2677 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2678 facs.u32HWSignature = RT_H2LE_U32(0);
2679 facs.u32FWVector = RT_H2LE_U32(0);
2680 facs.u32GlobalLock = RT_H2LE_U32(0);
2681 facs.u32Flags = RT_H2LE_U32(0);
2682 facs.u64X_FWVector = RT_H2LE_U64(0);
2683 facs.u8Version = 1;
2684
2685 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2686}
2687
2688/**
2689 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2690 */
2691static void acpiR3SetupFadt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2692 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2693{
2694 ACPITBLFADT fadt;
2695
2696 /* First the ACPI version 2+ version of the structure. */
2697 memset(&fadt, 0, sizeof(fadt));
2698 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2699 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2700 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2701 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2702 fadt.u8PreferredPMProfile = 0; /* unspecified */
2703 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2704 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2705 fadt.u8AcpiEnable = ACPI_ENABLE;
2706 fadt.u8AcpiDisable = ACPI_DISABLE;
2707 fadt.u8S4BIOSReq = 0;
2708 fadt.u8PStateCnt = 0;
2709 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2710 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2711 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2712 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2713 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2714 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2715 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2716 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2717 fadt.u8PM1EVTLEN = 4;
2718 fadt.u8PM1CTLLEN = 2;
2719 fadt.u8PM2CTLLEN = 0;
2720 fadt.u8PMTMLEN = 4;
2721 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2722 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2723 fadt.u8GPE1BASE = GPE1_BASE;
2724 fadt.u8CSTCNT = 0;
2725 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2726 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2727 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2728 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2729 fadt.u8DutyOffset = 0;
2730 fadt.u8DutyWidth = 0;
2731 fadt.u8DayAlarm = 0;
2732 fadt.u8MonAlarm = 0;
2733 fadt.u8Century = 0;
2734 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2735 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2736 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2737 | FADT_FL_FIX_RTC
2738 | FADT_FL_TMR_VAL_EXT
2739 | FADT_FL_RESET_REG_SUP);
2740
2741 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2742 if (pThis->fCpuHotPlug)
2743 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2744
2745 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2746 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2747 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2748 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2749 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2750 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2751 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2752 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2753 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2754 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2755 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2756 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2757 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2758 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2759
2760 /* Now the ACPI 1.0 version. */
2761 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2762 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2763 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2764 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2765 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2766}
2767
2768/**
2769 * Plant the root System Description Table.
2770 *
2771 * The RSDT and XSDT tables are basically identical. The only difference is 32
2772 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2773 * ACPI 2.0 and up.
2774 */
2775static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2776{
2777 ACPITBLRSDT *rsdt;
2778 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2779
2780 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2781 if (!rsdt)
2782 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2783
2784 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2785 for (unsigned int i = 0; i < nb_entries; ++i)
2786 {
2787 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2788 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2789 }
2790 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2791 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2792 RTMemFree(rsdt);
2793 return VINF_SUCCESS;
2794}
2795
2796/**
2797 * Plant the Extended System Description Table.
2798 */
2799static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2800{
2801 ACPITBLXSDT *xsdt;
2802 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2803
2804 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
2805 if (!xsdt)
2806 return VERR_NO_TMP_MEMORY;
2807
2808 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
2809
2810 if (pThis->cCustTbls > 0)
2811 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2812
2813 for (unsigned int i = 0; i < nb_entries; ++i)
2814 {
2815 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2816 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2817 }
2818 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, size);
2819 acpiR3PhysCopy(pDevIns, addr, xsdt, size);
2820 RTMemFree(xsdt);
2821 return VINF_SUCCESS;
2822}
2823
2824/**
2825 * Plant the Root System Description Pointer (RSDP).
2826 */
2827static void acpiR3SetupRsdp(ACPIState *pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2828{
2829 memset(rsdp, 0, sizeof(*rsdp));
2830
2831 /* ACPI 1.0 part (RSDT) */
2832 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2833 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2834 rsdp->u8Revision = ACPI_REVISION;
2835 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2836 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2837
2838 /* ACPI 2.0 part (XSDT) */
2839 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2840 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2841 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2842}
2843
2844/**
2845 * Multiple APIC Description Table.
2846 *
2847 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2848 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2849 * use regular C structure and proxy to raw memory instead.
2850 */
2851class AcpiTableMadt
2852{
2853 /**
2854 * All actual data stored in dynamically allocated memory pointed by this field.
2855 */
2856 uint8_t *m_pbData;
2857 /**
2858 * Number of CPU entries in this MADT.
2859 */
2860 uint32_t m_cCpus;
2861
2862 /**
2863 * Number of interrupt overrides.
2864 */
2865 uint32_t m_cIsos;
2866
2867public:
2868 /**
2869 * Address of ACPI header
2870 */
2871 inline ACPITBLHEADER *header_addr(void) const
2872 {
2873 return (ACPITBLHEADER *)m_pbData;
2874 }
2875
2876 /**
2877 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2878 * although address is the same for all of them.
2879 */
2880 inline uint32_t *u32LAPIC_addr(void) const
2881 {
2882 return (uint32_t *)(header_addr() + 1);
2883 }
2884
2885 /**
2886 * Address of APIC flags
2887 */
2888 inline uint32_t *u32Flags_addr(void) const
2889 {
2890 return (uint32_t *)(u32LAPIC_addr() + 1);
2891 }
2892
2893 /**
2894 * Address of ISO description
2895 */
2896 inline ACPITBLISO *ISO_addr(void) const
2897 {
2898 return (ACPITBLISO *)(u32Flags_addr() + 1);
2899 }
2900
2901 /**
2902 * Address of per-CPU LAPIC descriptions
2903 */
2904 inline ACPITBLLAPIC *LApics_addr(void) const
2905 {
2906 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2907 }
2908
2909 /**
2910 * Address of IO APIC description
2911 */
2912 inline ACPITBLIOAPIC *IOApic_addr(void) const
2913 {
2914 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2915 }
2916
2917 /**
2918 * Size of MADT.
2919 * Note that this function assumes IOApic to be the last field in structure.
2920 */
2921 inline uint32_t size(void) const
2922 {
2923 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2924 }
2925
2926 /**
2927 * Raw data of MADT.
2928 */
2929 inline const uint8_t *data(void) const
2930 {
2931 return m_pbData;
2932 }
2933
2934 /**
2935 * Size of MADT for given ACPI config, useful to compute layout.
2936 */
2937 static uint32_t sizeFor(ACPIState *pThis, uint32_t cIsos)
2938 {
2939 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2940 }
2941
2942 /*
2943 * Constructor, only works in Ring 3, doesn't look like a big deal.
2944 */
2945 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2946 {
2947 m_cCpus = cCpus;
2948 m_cIsos = cIsos;
2949 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2950 uint32_t cb = size();
2951 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2952 }
2953
2954 ~AcpiTableMadt()
2955 {
2956 RTMemFree(m_pbData);
2957 }
2958};
2959
2960
2961/**
2962 * Plant the Multiple APIC Description Table (MADT).
2963 *
2964 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
2965 *
2966 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
2967 */
2968static void acpiR3SetupMadt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr)
2969{
2970 uint16_t cpus = pThis->cCpus;
2971 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
2972
2973 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
2974
2975 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
2976 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
2977
2978 /* LAPICs records */
2979 ACPITBLLAPIC* lapic = madt.LApics_addr();
2980 for (uint16_t i = 0; i < cpus; i++)
2981 {
2982 lapic->u8Type = 0;
2983 lapic->u8Length = sizeof(ACPITBLLAPIC);
2984 lapic->u8ProcId = i;
2985 /** Must match numbering convention in MPTABLES */
2986 lapic->u8ApicId = i;
2987 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
2988 lapic++;
2989 }
2990
2991 /* IO-APIC record */
2992 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
2993 ioapic->u8Type = 1;
2994 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
2995 /** Must match MP tables ID */
2996 ioapic->u8IOApicId = cpus;
2997 ioapic->u8Reserved = 0;
2998 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
2999 ioapic->u32GSIB = RT_H2LE_U32(0);
3000
3001 /* Interrupt Source Overrides */
3002 /* Flags:
3003 bits[3:2]:
3004 00 conforms to the bus
3005 01 edge-triggered
3006 10 reserved
3007 11 level-triggered
3008 bits[1:0]
3009 00 conforms to the bus
3010 01 active-high
3011 10 reserved
3012 11 active-low */
3013 /* If changing, also update PDMIsaSetIrq() and MPS */
3014 ACPITBLISO* isos = madt.ISO_addr();
3015 /* Timer interrupt rule IRQ0 to GSI2 */
3016 isos[0].u8Type = 2;
3017 isos[0].u8Length = sizeof(ACPITBLISO);
3018 isos[0].u8Bus = 0; /* Must be 0 */
3019 isos[0].u8Source = 0; /* IRQ0 */
3020 isos[0].u32GSI = 2; /* connected to pin 2 */
3021 isos[0].u16Flags = 0; /* conform to the bus */
3022
3023 /* ACPI interrupt rule - IRQ9 to GSI9 */
3024 isos[1].u8Type = 2;
3025 isos[1].u8Length = sizeof(ACPITBLISO);
3026 isos[1].u8Bus = 0; /* Must be 0 */
3027 isos[1].u8Source = 9; /* IRQ9 */
3028 isos[1].u32GSI = 9; /* connected to pin 9 */
3029 isos[1].u16Flags = 0xf; /* active low, level triggered */
3030 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3031
3032 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3033 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3034}
3035
3036/**
3037 * Plant the High Performance Event Timer (HPET) descriptor.
3038 */
3039static void acpiR3SetupHpet(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr)
3040{
3041 ACPITBLHPET hpet;
3042
3043 memset(&hpet, 0, sizeof(hpet));
3044
3045 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3046 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3047 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3048 0 /* Memory address space */,
3049 64 /* Register bit width */,
3050 0 /* Bit offset */,
3051 0, /* Register access size, is it correct? */
3052 0xfed00000 /* Address */);
3053
3054 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3055 hpet.u32Number = 0;
3056 hpet.u32MinTick = 4096;
3057 hpet.u8Attributes = 0;
3058
3059 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3060
3061 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3062}
3063
3064
3065/**
3066 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3067 * descriptor.
3068 *
3069 * @param pThis The ACPI shared instance data.
3070 * @param GCPhysDst Where to plant it.
3071 */
3072static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 GCPhysDst)
3073{
3074 struct
3075 {
3076 ACPITBLMCFG hdr;
3077 ACPITBLMCFGENTRY entry;
3078 } tbl;
3079 uint8_t u8StartBus = 0;
3080 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3081
3082 RT_ZERO(tbl);
3083
3084 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3085 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3086 tbl.entry.u8StartBus = u8StartBus;
3087 tbl.entry.u8EndBus = u8EndBus;
3088 // u16PciSegmentGroup must match _SEG in ACPI table
3089
3090 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3091
3092 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3093}
3094
3095/**
3096 * Used by acpiR3PlantTables and acpiConstruct.
3097 *
3098 * @returns Guest memory address.
3099 */
3100static uint32_t apicR3FindRsdpSpace(void)
3101{
3102 return 0xe0000;
3103}
3104
3105/**
3106 * Called by acpiR3Construct to read and allocate a custom ACPI table
3107 *
3108 * @param pDevIns The device instance.
3109 * @param ppu8CustBin Address to receive the address of the table
3110 * @param pcbCustBin Address to receive the size of the the table.
3111 * @param pszCustBinFile
3112 * @param cbBufAvail Maximum space in bytes available for the custom
3113 * table (including header).
3114 */
3115static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3116 char *pszCustBinFile, uint32_t cbBufAvail)
3117{
3118 RTFILE FileCUSTBin;
3119 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3120 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3121 if (RT_SUCCESS(rc))
3122 {
3123 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3124 if (RT_SUCCESS(rc))
3125 {
3126 /* The following checks should be in sync the AssertReleaseMsg's below. */
3127 if ( *pcbCustBin > cbBufAvail
3128 || *pcbCustBin < sizeof(ACPITBLHEADER))
3129 rc = VERR_TOO_MUCH_DATA;
3130
3131 /*
3132 * Allocate buffer for the custom table binary data.
3133 */
3134 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3135 if (*ppu8CustBin)
3136 {
3137 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3138 if (RT_FAILURE(rc))
3139 {
3140 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3141 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3142 *ppu8CustBin = NULL;
3143 }
3144 }
3145 else
3146 {
3147 rc = VERR_NO_MEMORY;
3148 }
3149 RTFileClose(FileCUSTBin);
3150 }
3151 }
3152 return rc;
3153}
3154
3155/**
3156 * Create the ACPI tables in guest memory.
3157 */
3158static int acpiR3PlantTables(PPDMDEVINS pDevIns, ACPIState *pThis)
3159{
3160 int rc;
3161 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3162 RTGCPHYS32 GCPhysHpet = 0;
3163 RTGCPHYS32 GCPhysApic = 0;
3164 RTGCPHYS32 GCPhysSsdt = 0;
3165 RTGCPHYS32 GCPhysMcfg = 0;
3166 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3167 uint32_t addend = 0;
3168 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3169 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3170 uint32_t cAddr;
3171 uint32_t iMadt = 0;
3172 uint32_t iHpet = 0;
3173 uint32_t iSsdt = 0;
3174 uint32_t iMcfg = 0;
3175 uint32_t iCust = 0;
3176 size_t cbRsdt = sizeof(ACPITBLHEADER);
3177 size_t cbXsdt = sizeof(ACPITBLHEADER);
3178
3179 cAddr = 1; /* FADT */
3180 if (pThis->u8UseIOApic)
3181 iMadt = cAddr++; /* MADT */
3182
3183 if (pThis->fUseHpet)
3184 iHpet = cAddr++; /* HPET */
3185
3186 if (pThis->fUseMcfg)
3187 iMcfg = cAddr++; /* MCFG */
3188
3189 if (pThis->cCustTbls > 0)
3190 {
3191 iCust = cAddr; /* CUST */
3192 cAddr += pThis->cCustTbls;
3193 }
3194
3195 iSsdt = cAddr++; /* SSDT */
3196
3197 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3198 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3199
3200 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3201 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3202
3203 /*
3204 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3205 * The latter starts never below 4G.
3206 */
3207 PVM pVM = PDMDevHlpGetVM(pDevIns);
3208 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3209 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3210
3211 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3212 if (pThis->fPciPref64Enabled)
3213 {
3214 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3215 if (pThis->u64PciPref64Max > u64PciPref64Min)
3216 {
3217 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3218 pThis->u64PciPref64Min = u64PciPref64Min;
3219 LogRel(("ACPI: enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3220 u64PciPref64Min, pThis->u64PciPref64Max-1));
3221 }
3222 else
3223 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3224 u64PciPref64Min, pThis->u64PciPref64Max-1));
3225 }
3226 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3227 {
3228 /* Note: This is also enforced by DevPcBios.cpp. */
3229 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3230 cbBelow4GB = UINT32_C(0xfe000000);
3231 }
3232 pThis->cbRamLow = cbBelow4GB;
3233
3234 GCPhysCur = 0;
3235 GCPhysRsdt = GCPhysCur;
3236
3237 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3238 GCPhysXsdt = GCPhysCur;
3239
3240 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3241 GCPhysFadtAcpi1 = GCPhysCur;
3242
3243 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3244 GCPhysFadtAcpi2 = GCPhysCur;
3245
3246 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3247 GCPhysFacs = GCPhysCur;
3248
3249 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3250 if (pThis->u8UseIOApic)
3251 {
3252 GCPhysApic = GCPhysCur;
3253 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3254 }
3255 if (pThis->fUseHpet)
3256 {
3257 GCPhysHpet = GCPhysCur;
3258 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3259 }
3260 if (pThis->fUseMcfg)
3261 {
3262 GCPhysMcfg = GCPhysCur;
3263 /* Assume one entry */
3264 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3265 }
3266
3267 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3268 {
3269 aGCPhysCust[i] = GCPhysCur;
3270 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThis->acbCustBin[i], 16);
3271 }
3272
3273 void *pvSsdtCode = NULL;
3274 size_t cbSsdt = 0;
3275 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3276 if (RT_FAILURE(rc))
3277 return rc;
3278
3279 GCPhysSsdt = GCPhysCur;
3280 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3281
3282 GCPhysDsdt = GCPhysCur;
3283
3284 void *pvDsdtCode = NULL;
3285 size_t cbDsdt = 0;
3286 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3287 if (RT_FAILURE(rc))
3288 return rc;
3289
3290 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3291
3292 if (GCPhysCur > 0x10000)
3293 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3294 N_("Error: ACPI tables bigger than 64KB"));
3295
3296 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3297 addend = pThis->cbRamLow - 0x10000;
3298 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3299 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3300 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3301 if (pThis->u8UseIOApic)
3302 Log((" MADT 0x%08X", GCPhysApic + addend));
3303 if (pThis->fUseHpet)
3304 Log((" HPET 0x%08X", GCPhysHpet + addend));
3305 if (pThis->fUseMcfg)
3306 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3307 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3308 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3309 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3310 Log(("\n"));
3311
3312 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3313 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3314 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3315 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3316 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3317
3318 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3319 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3320 if (pThis->u8UseIOApic)
3321 {
3322 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3323 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3324 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3325 }
3326 if (pThis->fUseHpet)
3327 {
3328 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3329 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3330 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3331 }
3332 if (pThis->fUseMcfg)
3333 {
3334 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3335 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3336 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3337 }
3338 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3339 {
3340 Assert(i < MAX_CUST_TABLES);
3341 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThis->apu8CustBin[i], pThis->acbCustBin[i]);
3342 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3343 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3344 uint8_t* pSig = pThis->apu8CustBin[i];
3345 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3346 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3347 }
3348
3349 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3350 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3351 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3352 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3353
3354 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3355 if (RT_FAILURE(rc))
3356 return rc;
3357 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3358}
3359
3360/**
3361 * @callback_method_impl{FNPCICONFIGREAD}
3362 */
3363static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3364 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3365{
3366 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3367 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3368 return rcStrict;
3369}
3370
3371/**
3372 * @callback_method_impl{FNPCICONFIGWRITE}
3373 */
3374static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3375 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3376{
3377 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3378
3379 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3380 DEVACPI_LOCK_R3(pDevIns, pThis);
3381
3382 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3383 {
3384 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3385 u32Value = SCI_INT;
3386 }
3387
3388 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3389
3390 /* Assume that the base address is only changed when the corresponding
3391 * hardware functionality is disabled. The IO region is mapped when the
3392 * functionality is enabled by the guest. */
3393
3394 if (uAddress == PMREGMISC)
3395 {
3396 RTIOPORT NewIoPortBase = 0;
3397 /* Check Power Management IO Space Enable (PMIOSE) bit */
3398 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3399 {
3400 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3401 NewIoPortBase &= 0xffc0;
3402 }
3403
3404 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, NewIoPortBase);
3405 AssertRC(rc);
3406 }
3407
3408 if (uAddress == SMBHSTCFG)
3409 {
3410 RTIOPORT NewIoPortBase = 0;
3411 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3412 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3413 {
3414 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3415 NewIoPortBase &= 0xfff0;
3416 }
3417
3418 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3419 AssertRC(rc);
3420 }
3421
3422 DEVACPI_UNLOCK(pDevIns, pThis);
3423 return rcStrict;
3424}
3425
3426/**
3427 * Attach a new CPU.
3428 *
3429 * @returns VBox status code.
3430 * @param pDevIns The device instance.
3431 * @param iLUN The logical unit which is being attached.
3432 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3433 *
3434 * @remarks This code path is not used during construction.
3435 */
3436static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3437{
3438 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3439 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3440
3441 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3442 ("Hot-plug flag is not set\n"),
3443 VERR_NOT_SUPPORTED);
3444 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3445
3446 /* Check if it was already attached */
3447 int rc = VINF_SUCCESS;
3448 DEVACPI_LOCK_R3(pDevIns, pThis);
3449 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3450 {
3451 PPDMIBASE IBaseTmp;
3452 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3453 if (RT_SUCCESS(rc))
3454 {
3455 /* Enable the CPU */
3456 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3457
3458 /*
3459 * Lock the CPU because we don't know if the guest will use it or not.
3460 * Prevents ejection while the CPU is still used
3461 */
3462 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3463 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3464 pThis->u32CpuEvent = iLUN;
3465
3466 /* Notify the guest */
3467 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3468 }
3469 }
3470 DEVACPI_UNLOCK(pDevIns, pThis);
3471 return rc;
3472}
3473
3474/**
3475 * Detach notification.
3476 *
3477 * @param pDevIns The device instance.
3478 * @param iLUN The logical unit which is being detached.
3479 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3480 */
3481static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3482{
3483 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3484
3485 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3486
3487 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3488 ("Hot-plug flag is not set\n"));
3489
3490 /* Check if it was already detached */
3491 DEVACPI_LOCK_R3(pDevIns, pThis);
3492 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3493 {
3494 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3495 {
3496 /* Disable the CPU */
3497 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3498 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3499 pThis->u32CpuEvent = iLUN;
3500
3501 /* Notify the guest */
3502 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3503 }
3504 else
3505 AssertMsgFailed(("CPU is still locked by the guest\n"));
3506 }
3507 DEVACPI_UNLOCK(pDevIns, pThis);
3508}
3509
3510/**
3511 * @interface_method_impl{PDMDEVREG,pfnResume}
3512 */
3513static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3514{
3515 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3516 if (pThis->fSetWakeupOnResume)
3517 {
3518 Log(("acpiResume: setting WAK_STS\n"));
3519 pThis->fSetWakeupOnResume = false;
3520 pThis->pm1a_sts |= WAK_STS;
3521 }
3522}
3523
3524/**
3525 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3526 */
3527static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3528{
3529 RT_NOREF1(enmCtx);
3530 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3531 acpiR3PlantTables(pDevIns, pThis);
3532}
3533
3534/**
3535 * @interface_method_impl{PDMDEVREG,pfnReset}
3536 */
3537static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3538{
3539 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3540
3541 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3542 acpiSetIrq(pDevIns, 0);
3543
3544 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3545 pThis->pm1a_en = 0;
3546 pThis->pm1a_sts = 0;
3547 pThis->pm1a_ctl = 0;
3548 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3549 pThis->uPmTimerVal = 0;
3550 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3551 pThis->uPmTimeOld = pThis->uPmTimerVal;
3552 pThis->uBatteryIndex = 0;
3553 pThis->uSystemInfoIndex = 0;
3554 pThis->gpe0_en = 0;
3555 pThis->gpe0_sts = 0;
3556 pThis->uSleepState = 0;
3557 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
3558
3559 /* Real device behavior is resetting only the PM controller state,
3560 * but we're additionally doing the job of the BIOS. */
3561 acpiR3UpdatePmHandlers(pDevIns, pThis, PM_PORT_BASE);
3562 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3563
3564 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3565 * state. Real device behavior is only the SMBus controller state reset,
3566 * but we're additionally doing the job of the BIOS. */
3567 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3568 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3569 acpiR3SMBusResetDevice(pThis);
3570}
3571
3572/**
3573 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3574 */
3575static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3576{
3577 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3578 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3579 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3580 {
3581 if (pThis->apu8CustBin[i])
3582 {
3583 PDMDevHlpMMHeapFree(pDevIns, pThis->apu8CustBin[i]);
3584 pThis->apu8CustBin[i] = NULL;
3585 }
3586 }
3587 return VINF_SUCCESS;
3588}
3589
3590/**
3591 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3592 */
3593static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3594{
3595 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3596 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3597 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3598
3599 /*
3600 * Init data and set defaults.
3601 */
3602 /** @todo move more of the code up! */
3603
3604 pThis->pDevIns = pDevIns;
3605 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3606 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3607 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3608 pThis->u32CpuEventType = 0;
3609 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3610
3611 /* The first CPU can't be attached/detached */
3612 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3613 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3614
3615 /* IBase */
3616 pThis->IBase.pfnQueryInterface = acpiR3QueryInterface;
3617 /* IACPIPort */
3618 pThis->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3619 pThis->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3620 pThis->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3621 pThis->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3622 pThis->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3623 pThis->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3624 pThis->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3625
3626 /*
3627 * Set the default critical section to NOP (related to the PM timer).
3628 */
3629 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3630 AssertRCReturn(rc, rc);
3631
3632 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3633 AssertRCReturn(rc, rc);
3634
3635 /*
3636 * Validate and read the configuration.
3637 */
3638 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
3639 "IOAPIC"
3640 "|NumCPUs"
3641 "|HpetEnabled"
3642 "|McfgEnabled"
3643 "|McfgBase"
3644 "|McfgLength"
3645 "|PciPref64Enabled"
3646 "|PciPref64LimitGB"
3647 "|SmcEnabled"
3648 "|FdcEnabled"
3649 "|ShowRtc"
3650 "|ShowCpu"
3651 "|NicPciAddress"
3652 "|AudioPciAddress"
3653 "|IocPciAddress"
3654 "|HostBusPciAddress"
3655 "|EnableSuspendToDisk"
3656 "|PowerS1Enabled"
3657 "|PowerS4Enabled"
3658 "|CpuHotPlug"
3659 "|AmlFilePath"
3660 "|Serial0IoPortBase"
3661 "|Serial1IoPortBase"
3662 "|Serial2IoPortBase"
3663 "|Serial3IoPortBase"
3664 "|Serial0Irq"
3665 "|Serial1Irq"
3666 "|Serial2Irq"
3667 "|Serial3Irq"
3668 "|AcpiOemId"
3669 "|AcpiCreatorId"
3670 "|AcpiCreatorRev"
3671 "|CustomTable"
3672 "|CustomTable0"
3673 "|CustomTable1"
3674 "|CustomTable2"
3675 "|CustomTable3"
3676 "|Parallel0IoPortBase"
3677 "|Parallel1IoPortBase"
3678 "|Parallel0Irq"
3679 "|Parallel1Irq"
3680 , "");
3681
3682 /* query whether we are supposed to present an IOAPIC */
3683 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3684 if (RT_FAILURE(rc))
3685 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
3686
3687 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3688 if (RT_FAILURE(rc))
3689 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3690
3691 /* query whether we are supposed to present an FDC controller */
3692 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3693 if (RT_FAILURE(rc))
3694 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
3695
3696 /* query whether we are supposed to present HPET */
3697 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
3698 if (RT_FAILURE(rc))
3699 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
3700 /* query MCFG configuration */
3701 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
3702 if (RT_FAILURE(rc))
3703 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
3704 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
3705 if (RT_FAILURE(rc))
3706 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
3707 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
3708
3709 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
3710 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
3711 if (RT_FAILURE(rc))
3712 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
3713
3714 /* query the limit of the the 64-bit prefetchable memory window */
3715 uint64_t u64PciPref64MaxGB;
3716 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
3717 if (RT_FAILURE(rc))
3718 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
3719 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
3720
3721 /* query whether we are supposed to present SMC */
3722 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
3723 if (RT_FAILURE(rc))
3724 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
3725
3726 /* query whether we are supposed to present RTC object */
3727 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
3728 if (RT_FAILURE(rc))
3729 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
3730
3731 /* query whether we are supposed to present CPU objects */
3732 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
3733 if (RT_FAILURE(rc))
3734 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
3735
3736 /* query primary NIC PCI address */
3737 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
3738 if (RT_FAILURE(rc))
3739 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
3740
3741 /* query primary NIC PCI address */
3742 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3743 if (RT_FAILURE(rc))
3744 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
3745
3746 /* query IO controller (southbridge) PCI address */
3747 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3748 if (RT_FAILURE(rc))
3749 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
3750
3751 /* query host bus controller PCI address */
3752 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3753 if (RT_FAILURE(rc))
3754 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3755
3756 /* query whether S1 power state should be exposed */
3757 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3758 if (RT_FAILURE(rc))
3759 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3760
3761 /* query whether S4 power state should be exposed */
3762 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3763 if (RT_FAILURE(rc))
3764 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3765
3766 /* query whether S1 power state should save the VM state */
3767 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3768 if (RT_FAILURE(rc))
3769 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3770
3771 /* query whether we are allow CPU hot plugging */
3772 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3773 if (RT_FAILURE(rc))
3774 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
3775
3776 /* query serial info */
3777 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3778 if (RT_FAILURE(rc))
3779 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
3780
3781 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3782 if (RT_FAILURE(rc))
3783 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3784
3785 /* Serial 1 is enabled, get config data */
3786 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3787 if (RT_FAILURE(rc))
3788 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
3789
3790 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3791 if (RT_FAILURE(rc))
3792 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3793
3794 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
3795 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
3796 if (RT_FAILURE(rc))
3797 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
3798
3799 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
3800 if (RT_FAILURE(rc))
3801 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
3802
3803 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
3804 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
3805 if (RT_FAILURE(rc))
3806 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
3807
3808 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
3809 if (RT_FAILURE(rc))
3810 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
3811 /*
3812 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
3813 * the corresponding parallel port is not enabled.
3814 */
3815 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
3816 if (RT_FAILURE(rc))
3817 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
3818
3819 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
3820 if (RT_FAILURE(rc))
3821 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
3822
3823 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
3824 if (RT_FAILURE(rc))
3825 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
3826
3827 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
3828 if (RT_FAILURE(rc))
3829 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
3830
3831 /* Try to attach the other CPUs */
3832 for (unsigned i = 1; i < pThis->cCpus; i++)
3833 {
3834 if (pThis->fCpuHotPlug)
3835 {
3836 PPDMIBASE IBaseTmp;
3837 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3838
3839 if (RT_SUCCESS(rc))
3840 {
3841 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3842 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3843 Log(("acpi: Attached CPU %u\n", i));
3844 }
3845 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3846 Log(("acpi: CPU %u not attached yet\n", i));
3847 else
3848 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3849 }
3850 else
3851 {
3852 /* CPU is always attached if hot-plug is not enabled. */
3853 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3854 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3855 }
3856 }
3857
3858 char szOemId[16];
3859 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
3860 if (RT_FAILURE(rc))
3861 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3862 size_t cchOemId = strlen(szOemId);
3863 if (cchOemId > 6)
3864 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3865 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3866 memcpy(pThis->au8OemId, szOemId, cchOemId);
3867
3868 char szCreatorId[16];
3869 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
3870 if (RT_FAILURE(rc))
3871 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3872 size_t cchCreatorId = strlen(szCreatorId);
3873 if (cchCreatorId > 4)
3874 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3875 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3876 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
3877
3878 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3879 if (RT_FAILURE(rc))
3880 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3881
3882 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3883
3884 /*
3885 * Load custom ACPI tables.
3886 */
3887 /* Total space available for custom ACPI tables */
3888 /** @todo define as appropriate, remove as a magic number, and document
3889 * limitation in product manual */
3890 uint32_t cbBufAvail = 3072;
3891 pThis->cCustTbls = 0;
3892
3893 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
3894 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThis->apu8CustBin));
3895 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
3896 {
3897 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
3898
3899 /*
3900 * Get the custom table binary file name.
3901 */
3902 char *pszCustBinFile = NULL;
3903 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
3904 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
3905 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
3906 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3907 {
3908 rc = VINF_SUCCESS;
3909 pszCustBinFile = NULL;
3910 }
3911 else if (RT_FAILURE(rc))
3912 return PDMDEV_SET_ERROR(pDevIns, rc,
3913 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
3914 else if (!*pszCustBinFile)
3915 {
3916 MMR3HeapFree(pszCustBinFile);
3917 pszCustBinFile = NULL;
3918 }
3919
3920 /*
3921 * Determine the custom table binary size, open specified file in the process.
3922 */
3923 if (pszCustBinFile)
3924 {
3925 uint32_t idxCust = pThis->cCustTbls;
3926 rc = acpiR3ReadCustomTable(pDevIns, &pThis->apu8CustBin[idxCust],
3927 &pThis->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
3928 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
3929 idxCust, pszCustBinFile, pThis->acbCustBin[idxCust]));
3930 MMR3HeapFree(pszCustBinFile);
3931 if (RT_FAILURE(rc))
3932 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
3933 cbBufAvail -= pThis->acbCustBin[idxCust];
3934
3935 /* Update custom OEM attributes based on custom table */
3936 /** @todo is it intended for custom tables to overwrite user provided values above? */
3937 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThis->apu8CustBin[idxCust];
3938 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
3939 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
3940 pThis->u32OemRevision = pTblHdr->u32OemRevision;
3941 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
3942 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
3943
3944 pThis->cCustTbls++;
3945 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
3946 }
3947 }
3948
3949 /* Set default PM port base */
3950 pThis->uPmIoPortBase = PM_PORT_BASE;
3951
3952 /* Set default SMBus port base */
3953 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
3954
3955 /*
3956 * FDC and SMC try to use the same non-shareable interrupt (6),
3957 * enable only one device.
3958 */
3959 if (pThis->fUseSmc)
3960 pThis->fUseFdc = false;
3961
3962 /*
3963 * Plant ACPI tables.
3964 */
3965 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
3966 * au8RSDPPage here. However, there should be no harm in doing it
3967 * twice, so the lazy bird is taking the quick way out for now. */
3968 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
3969 if (!GCPhysRsdp)
3970 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
3971
3972 rc = acpiR3PlantTables(pDevIns, pThis);
3973 AssertRCReturn(rc, rc);
3974
3975 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
3976 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
3977 AssertRCReturn(rc, rc);
3978
3979 /*
3980 * Register I/O ports.
3981 */
3982 rc = acpiR3RegisterPmHandlers(pDevIns, pThis);
3983 AssertRCReturn(rc, rc);
3984
3985 rc = acpiR3RegisterSMBusHandlers(pDevIns, pThis);
3986 AssertRCReturn(rc, rc);
3987
3988#define R(addr, cnt, writer, reader, description) \
3989 do { \
3990 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, pThis, writer, reader, NULL, NULL, description); \
3991 AssertRCReturn(rc, rc); \
3992 } while (0)
3993 R(SMI_CMD, 1, acpiR3SmiWrite, NULL, "ACPI SMI");
3994#ifdef DEBUG_ACPI
3995 R(DEBUG_HEX, 1, acpiR3DhexWrite, NULL, "ACPI Debug hex");
3996 R(DEBUG_CHR, 1, acpiR3DchrWrite, NULL, "ACPI Debug char");
3997#endif
3998 R(BAT_INDEX, 1, acpiR3BatIndexWrite, NULL, "ACPI Battery status index");
3999 R(BAT_DATA, 1, NULL, acpiR3BatDataRead, "ACPI Battery status data");
4000 R(SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL, "ACPI system info index");
4001 R(SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead, "ACPI system info data");
4002 R(ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL, "ACPI Reset");
4003#undef R
4004
4005 /*
4006 * Create the PM timer.
4007 */
4008 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4009 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer);
4010 AssertRCReturn(rc, rc);
4011
4012 rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4013 AssertRCReturn(rc, rc);
4014 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4015 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4016 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
4017
4018 /*
4019 * Set up the PCI device.
4020 */
4021 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4022 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4023
4024 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4025 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4026
4027 /* See p. 50 of PIIX4 manual */
4028 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4029 PDMPciDevSetStatus(pPciDev, 0x0280);
4030
4031 PDMPciDevSetRevisionId(pPciDev, 0x08);
4032
4033 PDMPciDevSetClassProg(pPciDev, 0x00);
4034 PDMPciDevSetClassSub(pPciDev, 0x80);
4035 PDMPciDevSetClassBase(pPciDev, 0x06);
4036
4037 PDMPciDevSetHeaderType(pPciDev, 0x80);
4038
4039 PDMPciDevSetBIST(pPciDev, 0x00);
4040
4041 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4042 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4043
4044 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4045 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4046
4047 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4048 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4049 acpiR3SMBusResetDevice(pThis);
4050
4051 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4052 if (RT_FAILURE(rc))
4053 return rc;
4054
4055 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4056 AssertRCReturn(rc, rc);
4057
4058 /*
4059 * Register the saved state.
4060 */
4061 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4062 if (RT_FAILURE(rc))
4063 return rc;
4064
4065 /*
4066 * Get the corresponding connector interface
4067 */
4068 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "ACPI Driver Port");
4069 if (RT_SUCCESS(rc))
4070 {
4071 pThis->pDrv = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIACPICONNECTOR);
4072 if (!pThis->pDrv)
4073 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
4074 N_("LUN #0 doesn't have an ACPI connector interface"));
4075 }
4076 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4077 {
4078 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
4079 pDevIns->pReg->szName, pDevIns->iInstance));
4080 rc = VINF_SUCCESS;
4081 }
4082 else
4083 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4084
4085 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4086
4087 return rc;
4088}
4089
4090#else /* !IN_RING3 */
4091
4092/**
4093 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4094 */
4095static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4096{
4097 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4098 //PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4099
4100 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4101 AssertRCReturn(rc, rc);
4102
4103 return VINF_SUCCESS;
4104}
4105
4106#endif /* !IN_RING3 */
4107
4108/**
4109 * The device registration structure.
4110 */
4111const PDMDEVREG g_DeviceACPI =
4112{
4113 /* .u32Version = */ PDM_DEVREG_VERSION,
4114 /* .uReserved0 = */ 0,
4115 /* .szName = */ "acpi",
4116 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ,
4117 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4118 /* .cMaxInstances = */ ~0U,
4119 /* .uSharedVersion = */ 42,
4120 /* .cbInstanceShared = */ sizeof(ACPIState),
4121 /* .cbInstanceCC = */ 0,
4122 /* .cbInstanceRC = */ 0,
4123 /* .cMaxPciDevices = */ 1,
4124 /* .cMaxMsixVectors = */ 0,
4125 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4126#if defined(IN_RING3)
4127 /* .pszRCMod = */ "VBoxDDRC.rc",
4128 /* .pszR0Mod = */ "VBoxDDR0.r0",
4129 /* .pfnConstruct = */ acpiR3Construct,
4130 /* .pfnDestruct = */ acpiR3Destruct,
4131 /* .pfnRelocate = */ NULL,
4132 /* .pfnMemSetup = */ acpiR3MemSetup,
4133 /* .pfnPowerOn = */ NULL,
4134 /* .pfnReset = */ acpiR3Reset,
4135 /* .pfnSuspend = */ NULL,
4136 /* .pfnResume = */ acpiR3Resume,
4137 /* .pfnAttach = */ acpiR3Attach,
4138 /* .pfnDetach = */ acpiR3Detach,
4139 /* .pfnQueryInterface = */ NULL,
4140 /* .pfnInitComplete = */ NULL,
4141 /* .pfnPowerOff = */ NULL,
4142 /* .pfnSoftReset = */ NULL,
4143 /* .pfnReserved0 = */ NULL,
4144 /* .pfnReserved1 = */ NULL,
4145 /* .pfnReserved2 = */ NULL,
4146 /* .pfnReserved3 = */ NULL,
4147 /* .pfnReserved4 = */ NULL,
4148 /* .pfnReserved5 = */ NULL,
4149 /* .pfnReserved6 = */ NULL,
4150 /* .pfnReserved7 = */ NULL,
4151#elif defined(IN_RING0)
4152 /* .pfnEarlyConstruct = */ NULL,
4153 /* .pfnConstruct = */ acpiRZConstruct,
4154 /* .pfnDestruct = */ NULL,
4155 /* .pfnFinalDestruct = */ NULL,
4156 /* .pfnRequest = */ NULL,
4157 /* .pfnReserved0 = */ NULL,
4158 /* .pfnReserved1 = */ NULL,
4159 /* .pfnReserved2 = */ NULL,
4160 /* .pfnReserved3 = */ NULL,
4161 /* .pfnReserved4 = */ NULL,
4162 /* .pfnReserved5 = */ NULL,
4163 /* .pfnReserved6 = */ NULL,
4164 /* .pfnReserved7 = */ NULL,
4165#elif defined(IN_RC)
4166 /* .pfnConstruct = */ acpiRZConstruct,
4167 /* .pfnReserved0 = */ NULL,
4168 /* .pfnReserved1 = */ NULL,
4169 /* .pfnReserved2 = */ NULL,
4170 /* .pfnReserved3 = */ NULL,
4171 /* .pfnReserved4 = */ NULL,
4172 /* .pfnReserved5 = */ NULL,
4173 /* .pfnReserved6 = */ NULL,
4174 /* .pfnReserved7 = */ NULL,
4175#else
4176# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4177#endif
4178 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4179};
4180
4181#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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