VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 82014

Last change on this file since 82014 was 82014, checked in by vboxsync, 5 years ago

DevACPI: Build fix. bugref:9218
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 157.5 KB
Line 
1/* $Id: DevACPI.cpp 82014 2019-11-20 08:40:15Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#include <iprt/file.h>
33#ifdef IN_RING3
34# include <iprt/alloc.h>
35# include <iprt/string.h>
36# include <iprt/uuid.h>
37#endif /* IN_RING3 */
38
39#include "VBoxDD.h"
40
41#ifdef LOG_ENABLED
42# define DEBUG_ACPI
43#endif
44
45
46/*********************************************************************************************************************************
47* Defined Constants And Macros *
48*********************************************************************************************************************************/
49#ifdef IN_RING3
50/** Locks the device state, ring-3 only. */
51# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
52 do { \
53 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
54 AssertRC(rcLock); \
55 } while (0)
56#endif
57/** Unlocks the device state (all contexts). */
58#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
59 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
60
61
62#define DEBUG_HEX 0x3000
63#define DEBUG_CHR 0x3001
64
65/** PM Base Address PCI config space offset */
66#define PMBA 0x40
67/** PM Miscellaneous Power Management PCI config space offset */
68#define PMREGMISC 0x80
69
70#define PM_TMR_FREQ 3579545
71/** Default base for PM PIIX4 device */
72#define PM_PORT_BASE 0x4000
73/* Port offsets in PM device */
74enum
75{
76 PM1a_EVT_OFFSET = 0x00,
77 PM1b_EVT_OFFSET = -1, /**< not supported */
78 PM1a_CTL_OFFSET = 0x04,
79 PM1b_CTL_OFFSET = -1, /**< not supported */
80 PM2_CTL_OFFSET = -1, /**< not supported */
81 PM_TMR_OFFSET = 0x08,
82 GPE0_OFFSET = 0x20,
83 GPE1_OFFSET = -1 /**< not supported */
84};
85
86/* Maximum supported number of custom ACPI tables */
87#define MAX_CUST_TABLES 4
88
89/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
90#define PM_TMR_32BIT
91
92#define BAT_INDEX 0x00004040
93#define BAT_DATA 0x00004044
94#define SYSI_INDEX 0x00004048
95#define SYSI_DATA 0x0000404c
96#define ACPI_RESET_BLK 0x00004050
97
98/* PM1x status register bits */
99#define TMR_STS RT_BIT(0)
100#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
101#define BM_STS RT_BIT(4)
102#define GBL_STS RT_BIT(5)
103#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
104#define PWRBTN_STS RT_BIT(8)
105#define SLPBTN_STS RT_BIT(9)
106#define RTC_STS RT_BIT(10)
107#define IGN_STS RT_BIT(11)
108#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
109#define WAK_STS RT_BIT(15)
110#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
111
112/* PM1x enable register bits */
113#define TMR_EN RT_BIT(0)
114#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
115#define GBL_EN RT_BIT(5)
116#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
117#define PWRBTN_EN RT_BIT(8)
118#define SLPBTN_EN RT_BIT(9)
119#define RTC_EN RT_BIT(10)
120#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
121#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
122#define IGN_EN 0
123
124/* PM1x control register bits */
125#define SCI_EN RT_BIT(0)
126#define BM_RLD RT_BIT(1)
127#define GBL_RLS RT_BIT(2)
128#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
129#define IGN_CNT RT_BIT(9)
130#define SLP_TYPx_SHIFT 10
131#define SLP_TYPx_MASK 7
132#define SLP_EN RT_BIT(13)
133#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
134#define RSR_CNT (RSR1_CNT | RSR2_CNT)
135
136#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
137
138enum
139{
140 BAT_STATUS_STATE = 0x00, /**< BST battery state */
141 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
142 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
143 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
144 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
145 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
146 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
147 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
148 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
149 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
150 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
151 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
152 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
153 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
154 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
155 BAT_INDEX_LAST
156};
157
158enum
159{
160 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
161 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
162};
163
164enum
165{
166 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
167 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
168 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
169 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
170 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
171 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
172 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
173 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
174 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
175 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
176 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
177 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
178 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
179 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
180 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
181 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
182 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
183 SYSTEM_INFO_INDEX_POWER_STATES = 17,
184 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
185 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
186 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
187 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
188 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
189 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
190 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
191 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
192 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
193 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
194 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
195 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
196 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
197 SYSTEM_INFO_INDEX_END = 31,
198 SYSTEM_INFO_INDEX_INVALID = 0x80,
199 SYSTEM_INFO_INDEX_VALID = 0x200
200};
201
202#define AC_OFFLINE 0
203#define AC_ONLINE 1
204
205#define BAT_TECH_PRIMARY 1
206#define BAT_TECH_SECONDARY 2
207
208#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
209#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
210#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
211#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
212#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
213
214/** SMBus Base Address PCI config space offset */
215#define SMBBA 0x90
216/** SMBus Host Configuration PCI config space offset */
217#define SMBHSTCFG 0xd2
218/** SMBus Slave Command PCI config space offset */
219#define SMBSLVC 0xd3
220/** SMBus Slave Shadow Port 1 PCI config space offset */
221#define SMBSHDW1 0xd4
222/** SMBus Slave Shadow Port 2 PCI config space offset */
223#define SMBSHDW2 0xd5
224/** SMBus Revision Identification PCI config space offset */
225#define SMBREV 0xd6
226
227#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
228#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
229#define SMBHSTCFG_INTRSEL_SMI 0
230#define SMBHSTCFG_INTRSEL_IRQ9 4
231#define SMBHSTCFG_INTRSEL_SHIFT 1
232
233/** Default base for SMBus PIIX4 device */
234#define SMB_PORT_BASE 0x4100
235
236/** SMBus Host Status Register I/O offset */
237#define SMBHSTSTS_OFF 0x0000
238/** SMBus Slave Status Register I/O offset */
239#define SMBSLVSTS_OFF 0x0001
240/** SMBus Host Count Register I/O offset */
241#define SMBHSTCNT_OFF 0x0002
242/** SMBus Host Command Register I/O offset */
243#define SMBHSTCMD_OFF 0x0003
244/** SMBus Host Address Register I/O offset */
245#define SMBHSTADD_OFF 0x0004
246/** SMBus Host Data 0 Register I/O offset */
247#define SMBHSTDAT0_OFF 0x0005
248/** SMBus Host Data 1 Register I/O offset */
249#define SMBHSTDAT1_OFF 0x0006
250/** SMBus Block Data Register I/O offset */
251#define SMBBLKDAT_OFF 0x0007
252/** SMBus Slave Control Register I/O offset */
253#define SMBSLVCNT_OFF 0x0008
254/** SMBus Shadow Command Register I/O offset */
255#define SMBSHDWCMD_OFF 0x0009
256/** SMBus Slave Event Register I/O offset */
257#define SMBSLVEVT_OFF 0x000a
258/** SMBus Slave Data Register I/O offset */
259#define SMBSLVDAT_OFF 0x000c
260
261#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
262#define SMBHSTSTS_INTER RT_BIT(1)
263#define SMBHSTSTS_DEV_ERR RT_BIT(2)
264#define SMBHSTSTS_BUS_ERR RT_BIT(3)
265#define SMBHSTSTS_FAILED RT_BIT(4)
266#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
267
268#define SMBSLVSTS_WRITE_MASK 0x3c
269
270#define SMBHSTCNT_INTEREN RT_BIT(0)
271#define SMBHSTCNT_KILL RT_BIT(1)
272#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
273#define SMBHSTCNT_START RT_BIT(6)
274#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
275
276#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
277
278
279/*********************************************************************************************************************************
280* Structures and Typedefs *
281*********************************************************************************************************************************/
282/**
283 * The ACPI device state.
284 */
285typedef struct ACPIState
286{
287 /** Critical section protecting the ACPI state. */
288 PDMCRITSECT CritSect;
289
290 uint16_t pm1a_en;
291 uint16_t pm1a_sts;
292 uint16_t pm1a_ctl;
293 /** Number of logical CPUs in guest */
294 uint16_t cCpus;
295
296 uint64_t u64PmTimerInitial;
297 /** The PM timer. */
298 TMTIMERHANDLE hPmTimer;
299 /* PM Timer last calculated value */
300 uint32_t uPmTimerVal;
301 uint32_t Alignment0;
302
303 uint32_t gpe0_en;
304 uint32_t gpe0_sts;
305
306 uint32_t uBatteryIndex;
307 uint32_t au8BatteryInfo[13];
308
309 uint32_t uSystemInfoIndex;
310 uint64_t u64RamSize;
311 /** Offset of the 64-bit prefetchable memory window. */
312 uint64_t u64PciPref64Min;
313 /** Limit of the 64-bit prefetchable memory window. */
314 uint64_t u64PciPref64Max;
315 /** The number of bytes below 4GB. */
316 uint32_t cbRamLow;
317
318 /** Current ACPI S* state. We support S0 and S5. */
319 uint32_t uSleepState;
320 uint8_t au8RSDPPage[0x1000];
321 /** This is a workaround for incorrect index field handling by Intels ACPICA.
322 * The system info _INI method writes to offset 0x200. We either observe a
323 * write request to index 0x80 (in that case we don't change the index) or a
324 * write request to offset 0x200 (in that case we divide the index value by
325 * 4. Note that the _STA method is sometimes called prior to the _INI method
326 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
327 * acpiR3BatIndexWrite() for handling this. */
328 uint8_t u8IndexShift;
329 /** provide an I/O-APIC */
330 uint8_t u8UseIOApic;
331 /** provide a floppy controller */
332 bool fUseFdc;
333 /** If High Precision Event Timer device should be supported */
334 bool fUseHpet;
335 /** If System Management Controller device should be supported */
336 bool fUseSmc;
337 /** the guest handled the last power button event */
338 bool fPowerButtonHandled;
339 /** If ACPI CPU device should be shown */
340 bool fShowCpu;
341 /** If Real Time Clock ACPI object to be shown */
342 bool fShowRtc;
343 /** I/O port address of PM device. */
344 RTIOPORT uPmIoPortBase;
345 /** I/O port address of SMBus device. */
346 RTIOPORT uSMBusIoPortBase;
347 /** Array of flags of attached CPUs */
348 VMCPUSET CpuSetAttached;
349 /** Which CPU to check for the locked status. */
350 uint32_t idCpuLockCheck;
351 /** Mask of locked CPUs (used by the guest). */
352 VMCPUSET CpuSetLocked;
353 /** The CPU event type. */
354 uint32_t u32CpuEventType;
355 /** The CPU id affected. */
356 uint32_t u32CpuEvent;
357 /** Flag whether CPU hot plugging is enabled. */
358 bool fCpuHotPlug;
359 /** If MCFG ACPI table shown to the guest */
360 bool fUseMcfg;
361 /** if the 64-bit prefetchable memory window is shown to the guest */
362 bool fPciPref64Enabled;
363 /** Primary NIC PCI address. */
364 uint32_t u32NicPciAddress;
365 /** Primary audio card PCI address. */
366 uint32_t u32AudioPciAddress;
367 /** Flag whether S1 power state is enabled. */
368 bool fS1Enabled;
369 /** Flag whether S4 power state is enabled. */
370 bool fS4Enabled;
371 /** Flag whether S1 triggers a state save. */
372 bool fSuspendToSavedState;
373 /** Flag whether to set WAK_STS on resume (restore included). */
374 bool fSetWakeupOnResume;
375 /** PCI address of the IO controller device. */
376 uint32_t u32IocPciAddress;
377 /** PCI address of the host bus controller device. */
378 uint32_t u32HbcPciAddress;
379
380 /** Physical address of PCI config space MMIO region */
381 uint64_t u64PciConfigMMioAddress;
382 /** Length of PCI config space MMIO region */
383 uint64_t u64PciConfigMMioLength;
384 /** Serial 0 IRQ number */
385 uint8_t uSerial0Irq;
386 /** Serial 1 IRQ number */
387 uint8_t uSerial1Irq;
388 /** Serial 2 IRQ number */
389 uint8_t uSerial2Irq;
390 /** Serial 3 IRQ number */
391 uint8_t uSerial3Irq;
392 /** Serial 0 IO port base */
393 RTIOPORT uSerial0IoPortBase;
394 /** Serial 1 IO port base */
395 RTIOPORT uSerial1IoPortBase;
396 /** Serial 2 IO port base */
397 RTIOPORT uSerial2IoPortBase;
398 /** Serial 3 IO port base */
399 RTIOPORT uSerial3IoPortBase;
400
401 /** @name Parallel port config bits
402 * @{ */
403 /** Parallel 0 IRQ number */
404 uint8_t uParallel0Irq;
405 /** Parallel 1 IRQ number */
406 uint8_t uParallel1Irq;
407 /** Parallel 0 IO port base */
408 RTIOPORT uParallel0IoPortBase;
409 /** Parallel 1 IO port base */
410 RTIOPORT uParallel1IoPortBase;
411 /** @} */
412
413 uint32_t Alignment2;
414
415 /** ACPI port base interface. */
416 PDMIBASE IBase;
417 /** ACPI port interface. */
418 PDMIACPIPORT IACPIPort;
419 /** Pointer to the device instance so we can get our bearings from
420 * interface functions. */
421 PPDMDEVINSR3 pDevIns;
422
423 /** Pointer to the driver base interface. */
424 R3PTRTYPE(PPDMIBASE) pDrvBase;
425 /** Pointer to the driver connector interface. */
426 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
427
428 /** Number of custom ACPI tables */
429 uint8_t cCustTbls;
430 /** ACPI OEM ID */
431 uint8_t au8OemId[6];
432 /** ACPI Crator ID */
433 uint8_t au8CreatorId[4];
434 /** ACPI Crator Rev */
435 uint32_t u32CreatorRev;
436 /** ACPI custom OEM Tab ID */
437 uint8_t au8OemTabId[8];
438 /** ACPI custom OEM Rev */
439 uint32_t u32OemRevision;
440 uint32_t Alignment4;
441
442 /** Custom ACPI tables binary data. */
443 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
444 /** The size of the custom table binary. */
445 uint64_t acbCustBin[MAX_CUST_TABLES];
446
447 /** SMBus Host Status Register */
448 uint8_t u8SMBusHstSts;
449 /** SMBus Slave Status Register */
450 uint8_t u8SMBusSlvSts;
451 /** SMBus Host Control Register */
452 uint8_t u8SMBusHstCnt;
453 /** SMBus Host Command Register */
454 uint8_t u8SMBusHstCmd;
455 /** SMBus Host Address Register */
456 uint8_t u8SMBusHstAdd;
457 /** SMBus Host Data 0 Register */
458 uint8_t u8SMBusHstDat0;
459 /** SMBus Host Data 1 Register */
460 uint8_t u8SMBusHstDat1;
461 /** SMBus Slave Control Register */
462 uint8_t u8SMBusSlvCnt;
463 /** SMBus Shadow Command Register */
464 uint8_t u8SMBusShdwCmd;
465 /** SMBus Slave Event Register */
466 uint16_t u16SMBusSlvEvt;
467 /** SMBus Slave Data Register */
468 uint16_t u16SMBusSlvDat;
469 /** SMBus Host Block Data Buffer */
470 uint8_t au8SMBusBlkDat[32];
471 /** SMBus Host Block Index */
472 uint8_t u8SMBusBlkIdx;
473
474 /** @todo DEBUGGING */
475 uint32_t uPmTimeOld;
476 uint32_t uPmTimeA;
477 uint32_t uPmTimeB;
478 uint32_t Alignment5;
479
480 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
481 * @{ */
482 IOMIOPORTHANDLE hIoPortPm1aEn;
483 IOMIOPORTHANDLE hIoPortPm1aSts;
484 IOMIOPORTHANDLE hIoPortPm1aCtl;
485 IOMIOPORTHANDLE hIoPortPmTimer;
486 IOMIOPORTHANDLE hIoPortGpe0En;
487 IOMIOPORTHANDLE hIoPortGpe0Sts;
488 /** @} */
489
490 /** SMBus I/O ports (mapped/unmapped). */
491 IOMIOPORTHANDLE hIoPortSMBus;
492
493 /** @name Fixed I/O ports
494 * @{ */
495 /** ACPI SMI I/O port. */
496 IOMIOPORTHANDLE hIoPortSmi;
497 /** ACPI Debug hex I/O port. */
498 IOMIOPORTHANDLE hIoPortDebugHex;
499 /** ACPI Debug char I/O port. */
500 IOMIOPORTHANDLE hIoPortDebugChar;
501 /** ACPI Battery status index I/O port. */
502 IOMIOPORTHANDLE hIoPortBatteryIndex;
503 /** ACPI Battery status data I/O port. */
504 IOMIOPORTHANDLE hIoPortBatteryData;
505 /** ACPI system info index I/O port. */
506 IOMIOPORTHANDLE hIoPortSysInfoIndex;
507 /** ACPI system info data I/O port. */
508 IOMIOPORTHANDLE hIoPortSysInfoData;
509 /** ACPI Reset I/O port. */
510 IOMIOPORTHANDLE hIoPortReset;
511 /** @} */
512
513} ACPIState, ACPISTATE;
514/** Pointer to the shared ACPI device state. */
515typedef ACPISTATE *PACPISTATE;
516
517#pragma pack(1)
518
519/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
520struct ACPIGENADDR
521{
522 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
523 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
524 uint8_t u8RegisterBitOffset; /**< bit offset of register */
525 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
526 uint64_t u64Address; /**< 64-bit address of register */
527};
528AssertCompileSize(ACPIGENADDR, 12);
529
530/** Root System Description Pointer */
531struct ACPITBLRSDP
532{
533 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
534 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
535 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
536 uint8_t u8Revision; /**< revision number, currently 2 */
537#define ACPI_REVISION 2 /**< ACPI 3.0 */
538 uint32_t u32RSDT; /**< phys addr of RSDT */
539 uint32_t u32Length; /**< bytes of this table */
540 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
541 uint8_t u8ExtChecksum; /**< checksum of entire table */
542 uint8_t u8Reserved[3]; /**< reserved */
543};
544AssertCompileSize(ACPITBLRSDP, 36);
545
546/** System Description Table Header */
547struct ACPITBLHEADER
548{
549 uint8_t au8Signature[4]; /**< table identifier */
550 uint32_t u32Length; /**< length of the table including header */
551 uint8_t u8Revision; /**< revision number */
552 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
553 uint8_t au8OemId[6]; /**< OEM-supplied string */
554 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
555 uint32_t u32OemRevision; /**< OEM-supplied revision number */
556 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
557 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
558};
559AssertCompileSize(ACPITBLHEADER, 36);
560
561/** Root System Description Table */
562struct ACPITBLRSDT
563{
564 ACPITBLHEADER header;
565 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
566};
567AssertCompileSize(ACPITBLRSDT, 40);
568
569/** Extended System Description Table */
570struct ACPITBLXSDT
571{
572 ACPITBLHEADER header;
573 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
574};
575AssertCompileSize(ACPITBLXSDT, 44);
576
577/** Fixed ACPI Description Table */
578struct ACPITBLFADT
579{
580 ACPITBLHEADER header;
581 uint32_t u32FACS; /**< phys. address of FACS */
582 uint32_t u32DSDT; /**< phys. address of DSDT */
583 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
584#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
585#define INT_MODEL_MULTIPLE_APIC 2
586 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
587 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
588#define SCI_INT 9
589 uint32_t u32SMICmd; /**< system port address of SMI command port */
590#define SMI_CMD 0x0000442e
591 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
592#define ACPI_ENABLE 0xa1
593 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
594#define ACPI_DISABLE 0xa0
595 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
596 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
597 state control responsibility */
598 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
599 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
600 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
601 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
602 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
603 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
604 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
605 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
606 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
607 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
608 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
609 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
610 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
611#define GPE0_BLK_LEN 2
612 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
613#define GPE1_BLK_LEN 0
614 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
615#define GPE1_BASE 0
616 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
617 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
618#define P_LVL2_LAT 101 /**< C2 state not supported */
619 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
620#define P_LVL3_LAT 1001 /**< C3 state not supported */
621 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
622 lines from any processors memory caches */
623#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
624 uint16_t u16FlushStride; /**< cache line width */
625#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
626 uint8_t u8DutyOffset;
627 uint8_t u8DutyWidth;
628 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
629 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
630 uint8_t u8Century; /**< RTC CMOS RAM index of century */
631 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
632#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
633 (COM too?) */
634#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
635#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
636#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
637#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
638 uint8_t u8Must0_0; /**< must be 0 */
639 uint32_t u32Flags; /**< fixed feature flags */
640#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
641#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
642#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
643#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
644#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
645#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
646#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
647#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
648#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
649#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
650#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
651#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
652#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
653#define FADT_FL_CPU_SW_SLP RT_BIT(13)
654#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
655#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
656#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
657#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
658#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
659#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
660
661/* PM Timer mask and msb */
662#ifndef PM_TMR_32BIT
663#define TMR_VAL_MSB 0x800000
664#define TMR_VAL_MASK 0xffffff
665#undef FADT_FL_TMR_VAL_EXT
666#define FADT_FL_TMR_VAL_EXT 0
667#else
668#define TMR_VAL_MSB 0x80000000
669#define TMR_VAL_MASK 0xffffffff
670#endif
671
672 /** Start of the ACPI 2.0 extension. */
673 ACPIGENADDR ResetReg; /**< ext addr of reset register */
674 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
675#define ACPI_RESET_REG_VAL 0x10
676 uint8_t au8Must0_1[3]; /**< must be 0 */
677 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
678 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
679 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
680 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
681 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
682 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
683 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
684 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
685 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
686 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
687};
688AssertCompileSize(ACPITBLFADT, 244);
689#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
690
691/** Firmware ACPI Control Structure */
692struct ACPITBLFACS
693{
694 uint8_t au8Signature[4]; /**< 'FACS' */
695 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
696 uint32_t u32HWSignature; /**< systems HW signature at last boot */
697 uint32_t u32FWVector; /**< address of waking vector */
698 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
699 uint32_t u32Flags; /**< FACS flags */
700 uint64_t u64X_FWVector; /**< 64-bit waking vector */
701 uint8_t u8Version; /**< version of this table */
702 uint8_t au8Reserved[31]; /**< zero */
703};
704AssertCompileSize(ACPITBLFACS, 64);
705
706/** Processor Local APIC Structure */
707struct ACPITBLLAPIC
708{
709 uint8_t u8Type; /**< 0 = LAPIC */
710 uint8_t u8Length; /**< 8 */
711 uint8_t u8ProcId; /**< processor ID */
712 uint8_t u8ApicId; /**< local APIC ID */
713 uint32_t u32Flags; /**< Flags */
714#define LAPIC_ENABLED 0x1
715};
716AssertCompileSize(ACPITBLLAPIC, 8);
717
718/** I/O APIC Structure */
719struct ACPITBLIOAPIC
720{
721 uint8_t u8Type; /**< 1 == I/O APIC */
722 uint8_t u8Length; /**< 12 */
723 uint8_t u8IOApicId; /**< I/O APIC ID */
724 uint8_t u8Reserved; /**< 0 */
725 uint32_t u32Address; /**< phys address to access I/O APIC */
726 uint32_t u32GSIB; /**< global system interrupt number to start */
727};
728AssertCompileSize(ACPITBLIOAPIC, 12);
729
730/** Interrupt Source Override Structure */
731struct ACPITBLISO
732{
733 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
734 uint8_t u8Length; /**< 10 */
735 uint8_t u8Bus; /**< Bus */
736 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
737 uint32_t u32GSI; /**< Global System Interrupt */
738 uint16_t u16Flags; /**< MPS INTI flags Global */
739};
740AssertCompileSize(ACPITBLISO, 10);
741#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
742
743/** HPET Descriptor Structure */
744struct ACPITBLHPET
745{
746 ACPITBLHEADER aHeader;
747 uint32_t u32Id; /**< hardware ID of event timer block
748 [31:16] PCI vendor ID of first timer block
749 [15] legacy replacement IRQ routing capable
750 [14] reserved
751 [13] COUNT_SIZE_CAP counter size
752 [12:8] number of comparators in first timer block
753 [7:0] hardware rev ID */
754 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
755 uint8_t u32Number; /**< sequence number starting at 0 */
756 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
757 lost interrupts while the counter is programmed
758 to operate in periodic mode. Unit: clock tick. */
759 uint8_t u8Attributes; /**< page protection and OEM attribute. */
760};
761AssertCompileSize(ACPITBLHPET, 56);
762
763/** MCFG Descriptor Structure */
764typedef struct ACPITBLMCFG
765{
766 ACPITBLHEADER aHeader;
767 uint64_t u64Reserved;
768} ACPITBLMCFG;
769AssertCompileSize(ACPITBLMCFG, 44);
770
771/** Number of such entries can be computed from the whole table length in header */
772typedef struct ACPITBLMCFGENTRY
773{
774 uint64_t u64BaseAddress;
775 uint16_t u16PciSegmentGroup;
776 uint8_t u8StartBus;
777 uint8_t u8EndBus;
778 uint32_t u32Reserved;
779} ACPITBLMCFGENTRY;
780AssertCompileSize(ACPITBLMCFGENTRY, 16);
781
782#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
783
784/** Custom Description Table */
785struct ACPITBLCUST
786{
787 ACPITBLHEADER header;
788 uint8_t au8Data[476];
789};
790AssertCompileSize(ACPITBLCUST, 512);
791
792
793#pragma pack()
794
795
796#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
797
798
799/*********************************************************************************************************************************
800* Internal Functions *
801*********************************************************************************************************************************/
802#ifdef IN_RING3
803static int acpiR3PlantTables(PPDMDEVINS pDevIns, ACPIState *pThis);
804#endif
805
806/* SCI, usually IRQ9 */
807DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
808{
809 PDMDevHlpPCISetIrq(pDevIns, 0, level);
810}
811
812DECLINLINE(bool) pm1a_level(ACPIState *pThis)
813{
814 return (pThis->pm1a_ctl & SCI_EN)
815 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
816}
817
818DECLINLINE(bool) gpe0_level(ACPIState *pThis)
819{
820 return !!(pThis->gpe0_en & pThis->gpe0_sts);
821}
822
823DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, ACPIState *pThis)
824{
825 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
826 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
827 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
828 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
829 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
830}
831
832DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, ACPIState *pThis)
833{
834 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
835}
836
837/**
838 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
839 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
840 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
841 * registers and trigger IRQs.
842 *
843 * Caller must hold the state lock.
844 *
845 * @param pDevIns The PDM device instance.
846 * @param pThis The ACPI shared instance data.
847 * @param sts The new PM1a.STS value.
848 * @param en The new PM1a.EN value.
849 */
850static void acpiUpdatePm1a(PPDMDEVINS pDevIns, ACPIState *pThis, uint32_t sts, uint32_t en)
851{
852 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
853
854 const bool old_level = acpiSCILevel(pDevIns, pThis);
855 pThis->pm1a_en = en;
856 pThis->pm1a_sts = sts;
857 const bool new_level = acpiSCILevel(pDevIns, pThis);
858
859 LogFunc(("old=%x new=%x\n", old_level, new_level));
860
861 if (new_level != old_level)
862 acpiSetIrq(pDevIns, new_level);
863}
864
865#ifdef IN_RING3
866
867/**
868 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
869 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
870 *
871 * Caller must hold the state lock.
872 *
873 * @param pDevIns The PDM device instance.
874 * @param pThis The ACPI shared instance data.
875 * @param sts The new GPE0.STS value.
876 * @param en The new GPE0.EN value.
877 */
878static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, ACPIState *pThis, uint32_t sts, uint32_t en)
879{
880 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
881
882 const bool old_level = acpiSCILevel(pDevIns, pThis);
883 pThis->gpe0_en = en;
884 pThis->gpe0_sts = sts;
885 const bool new_level = acpiSCILevel(pDevIns, pThis);
886
887 LogFunc(("old=%x new=%x\n", old_level, new_level));
888
889 if (new_level != old_level)
890 acpiSetIrq(pDevIns, new_level);
891}
892
893/**
894 * Used by acpiR3PM1aCtlWrite to power off the VM.
895 *
896 * @param pDevIns The device instance.
897 * @returns Strict VBox status code.
898 */
899static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
900{
901 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
902 AssertRC(VBOXSTRICTRC_VAL(rc));
903 return rc;
904}
905
906/**
907 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
908 *
909 * @param pDevIns The device instance.
910 * @param pThis The ACPI shared instance data.
911 * @returns Strict VBox status code.
912 */
913static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, ACPIState *pThis)
914{
915 /* We must set WAK_STS on resume (includes restore) so the guest knows that
916 we've woken up and can continue executing code. The guest is probably
917 reading the PMSTS register in a loop to check this. */
918 VBOXSTRICTRC rc;
919 pThis->fSetWakeupOnResume = true;
920 if (pThis->fSuspendToSavedState)
921 {
922 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
923 if (rc != VERR_NOT_SUPPORTED)
924 AssertRC(VBOXSTRICTRC_VAL(rc));
925 else
926 {
927 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
928 rc = PDMDevHlpVMSuspend(pDevIns);
929 AssertRC(VBOXSTRICTRC_VAL(rc));
930 }
931 }
932 else
933 {
934 rc = PDMDevHlpVMSuspend(pDevIns);
935 AssertRC(VBOXSTRICTRC_VAL(rc));
936 }
937 return rc;
938}
939
940
941/**
942 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
943 */
944static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
945{
946 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
947 PPDMDEVINS pDevIns = pThis->pDevIns;
948 DEVACPI_LOCK_R3(pDevIns, pThis);
949
950 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
951 pThis->fPowerButtonHandled = false;
952 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
953
954 DEVACPI_UNLOCK(pDevIns, pThis);
955 return VINF_SUCCESS;
956}
957
958/**
959 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
960 */
961static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
962{
963 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
964 PPDMDEVINS pDevIns = pThis->pDevIns;
965 DEVACPI_LOCK_R3(pDevIns, pThis);
966
967 *pfHandled = pThis->fPowerButtonHandled;
968
969 DEVACPI_UNLOCK(pDevIns, pThis);
970 return VINF_SUCCESS;
971}
972
973/**
974 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
975 * Guest entered into G0 (working) or G1 (sleeping)}
976 */
977static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
978{
979 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
980 PPDMDEVINS pDevIns = pThis->pDevIns;
981 DEVACPI_LOCK_R3(pDevIns, pThis);
982
983 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
984
985 DEVACPI_UNLOCK(pDevIns, pThis);
986 return VINF_SUCCESS;
987}
988
989/**
990 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
991 */
992static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
993{
994 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
995 PPDMDEVINS pDevIns = pThis->pDevIns;
996 DEVACPI_LOCK_R3(pDevIns, pThis);
997
998 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
999
1000 DEVACPI_UNLOCK(pDevIns, pThis);
1001 return VINF_SUCCESS;
1002}
1003
1004/**
1005 * Send an ACPI sleep button event.
1006 *
1007 * @returns VBox status code
1008 * @param pInterface Pointer to the interface structure containing the called function pointer.
1009 */
1010static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1011{
1012 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
1013 PPDMDEVINS pDevIns = pThis->pDevIns;
1014 DEVACPI_LOCK_R3(pDevIns, pThis);
1015
1016 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1017
1018 DEVACPI_UNLOCK(pDevIns, pThis);
1019 return VINF_SUCCESS;
1020}
1021
1022/**
1023 * Send an ACPI monitor hot-plug event.
1024 *
1025 * @returns VBox status code
1026 * @param pInterface Pointer to the interface structure containing the
1027 * called function pointer.
1028 */
1029static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1030{
1031 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
1032 PPDMDEVINS pDevIns = pThis->pDevIns;
1033 DEVACPI_LOCK_R3(pDevIns, pThis);
1034
1035 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1036
1037 DEVACPI_UNLOCK(pDevIns, pThis);
1038 return VINF_SUCCESS;
1039}
1040
1041/**
1042 * Send an ACPI battery status change event.
1043 *
1044 * @returns VBox status code
1045 * @param pInterface Pointer to the interface structure containing the
1046 * called function pointer.
1047 */
1048static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1049{
1050 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
1051 PPDMDEVINS pDevIns = pThis->pDevIns;
1052 DEVACPI_LOCK_R3(pDevIns, pThis);
1053
1054 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1055
1056 DEVACPI_UNLOCK(pDevIns, pThis);
1057 return VINF_SUCCESS;
1058}
1059
1060/**
1061 * Used by acpiR3PmTimer to re-arm the PM timer.
1062 *
1063 * The caller is expected to either hold the clock lock or to have made sure
1064 * the VM is resetting or loading state.
1065 *
1066 * @param pDevIns The device instance.
1067 * @param pThis The ACPI shared instance data.
1068 * @param uNow The current time.
1069 */
1070static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, ACPIState *pThis, uint64_t uNow)
1071{
1072 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1073 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1074 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1075 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1076 Log(("acpi: uInterval = %RU64\n", uInterval));
1077}
1078
1079#endif /* IN_RING3 */
1080
1081/**
1082 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1083 *
1084 * The caller is expected to either hold the clock lock or to have made sure
1085 * the VM is resetting or loading state.
1086 *
1087 * @param pDevIns The PDM device instance.
1088 * @param pThis The ACPI instance
1089 * @param u64Now The current time
1090 */
1091static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, ACPIState *pThis, uint64_t u64Now)
1092{
1093 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1094 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1095 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1096
1097 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ,
1098 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1099 & TMR_VAL_MASK;
1100
1101 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1102 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1103}
1104
1105#ifdef IN_RING3
1106
1107/**
1108 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1109 */
1110static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1111{
1112 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1113 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1114 RT_NOREF(pTimer, pvUser);
1115
1116 DEVACPI_LOCK_R3(pDevIns, pThis);
1117 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1118 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1119 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1120 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1121 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1122 DEVACPI_UNLOCK(pDevIns, pThis);
1123
1124 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
1125}
1126
1127/**
1128 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1129 * acpiR3LoadState.
1130 *
1131 * @returns VINF_SUCCESS.
1132 * @param pThis The ACPI shared instance data.
1133 */
1134static int acpiR3FetchBatteryStatus(ACPIState *pThis)
1135{
1136 uint32_t *p = pThis->au8BatteryInfo;
1137 bool fPresent; /* battery present? */
1138 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1139 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1140 uint32_t hostPresentRate; /* 0..1000 */
1141 int rc;
1142
1143 if (!pThis->pDrv)
1144 return VINF_SUCCESS;
1145 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
1146 &hostBatteryState, &hostPresentRate);
1147 AssertRC(rc);
1148
1149 /* default values */
1150 p[BAT_STATUS_STATE] = hostBatteryState;
1151 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1152 : hostPresentRate * 50; /* mW */
1153 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1154 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1155
1156 /* did we get a valid battery state? */
1157 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1158 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1159 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1160 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1161
1162 return VINF_SUCCESS;
1163}
1164
1165/**
1166 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1167 * acpiR3LoadState.
1168 *
1169 * @returns VINF_SUCCESS.
1170 * @param pThis The ACPI shared instance data.
1171 */
1172static int acpiR3FetchBatteryInfo(ACPIState *pThis)
1173{
1174 uint32_t *p = pThis->au8BatteryInfo;
1175
1176 p[BAT_INFO_UNITS] = 0; /* mWh */
1177 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1178 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1179 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1180 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1181 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1182 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1183 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1184 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1185
1186 return VINF_SUCCESS;
1187}
1188
1189/**
1190 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1191 *
1192 * @returns status mask or 0.
1193 * @param pThis The ACPI shared instance data.
1194 */
1195static uint32_t acpiR3GetBatteryDeviceStatus(ACPIState *pThis)
1196{
1197 bool fPresent; /* battery present? */
1198 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1199 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1200 uint32_t hostPresentRate; /* 0..1000 */
1201 int rc;
1202
1203 if (!pThis->pDrv)
1204 return 0;
1205 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
1206 &hostBatteryState, &hostPresentRate);
1207 AssertRC(rc);
1208
1209 return fPresent
1210 ? STA_DEVICE_PRESENT_MASK /* present */
1211 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1212 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1213 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1214 | STA_BATTERY_PRESENT_MASK /* battery is present */
1215 : 0; /* device not present */
1216}
1217
1218/**
1219 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1220 *
1221 * @returns status.
1222 * @param pThis The ACPI shared instance data.
1223 */
1224static uint32_t acpiR3GetPowerSource(ACPIState *pThis)
1225{
1226 /* query the current power source from the host driver */
1227 if (!pThis->pDrv)
1228 return AC_ONLINE;
1229
1230 PDMACPIPOWERSOURCE ps;
1231 int rc = pThis->pDrv->pfnQueryPowerSource(pThis->pDrv, &ps);
1232 AssertRC(rc);
1233 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1234}
1235
1236/**
1237 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1238 */
1239static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1240{
1241 RT_NOREF(pvUser, offPort);
1242 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1243 if (cb != 4)
1244 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1245
1246 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1247 DEVACPI_LOCK_R3(pDevIns, pThis);
1248
1249 u32 >>= pThis->u8IndexShift;
1250 /* see comment at the declaration of u8IndexShift */
1251 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1252 {
1253 pThis->u8IndexShift = 2;
1254 u32 >>= 2;
1255 }
1256 Assert(u32 < BAT_INDEX_LAST);
1257 pThis->uBatteryIndex = u32;
1258
1259 DEVACPI_UNLOCK(pDevIns, pThis);
1260 return VINF_SUCCESS;
1261}
1262
1263/**
1264 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1265 */
1266static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1267{
1268 RT_NOREF(pvUser, offPort);
1269 if (cb != 4)
1270 return VERR_IOM_IOPORT_UNUSED;
1271
1272 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1273 DEVACPI_LOCK_R3(pDevIns, pThis);
1274
1275 VBOXSTRICTRC rc = VINF_SUCCESS;
1276 switch (pThis->uBatteryIndex)
1277 {
1278 case BAT_STATUS_STATE:
1279 acpiR3FetchBatteryStatus(pThis);
1280 RT_FALL_THRU();
1281 case BAT_STATUS_PRESENT_RATE:
1282 case BAT_STATUS_REMAINING_CAPACITY:
1283 case BAT_STATUS_PRESENT_VOLTAGE:
1284 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1285 break;
1286
1287 case BAT_INFO_UNITS:
1288 acpiR3FetchBatteryInfo(pThis);
1289 RT_FALL_THRU();
1290 case BAT_INFO_DESIGN_CAPACITY:
1291 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1292 case BAT_INFO_TECHNOLOGY:
1293 case BAT_INFO_DESIGN_VOLTAGE:
1294 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1295 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1296 case BAT_INFO_CAPACITY_GRANULARITY_1:
1297 case BAT_INFO_CAPACITY_GRANULARITY_2:
1298 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1299 break;
1300
1301 case BAT_DEVICE_STATUS:
1302 *pu32 = acpiR3GetBatteryDeviceStatus(pThis);
1303 break;
1304
1305 case BAT_POWER_SOURCE:
1306 *pu32 = acpiR3GetPowerSource(pThis);
1307 break;
1308
1309 default:
1310 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1311 *pu32 = UINT32_MAX;
1312 break;
1313 }
1314
1315 DEVACPI_UNLOCK(pDevIns, pThis);
1316 return rc;
1317}
1318
1319/**
1320 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1321 */
1322static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1323{
1324 RT_NOREF(pvUser, offPort);
1325 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1326 if (cb != 4)
1327 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1328
1329 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1330 DEVACPI_LOCK_R3(pDevIns, pThis);
1331
1332 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1333 pThis->uSystemInfoIndex = u32;
1334 else
1335 {
1336 /* see comment at the declaration of u8IndexShift */
1337 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1338 {
1339 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1340 pThis->u8IndexShift = 2;
1341 }
1342
1343 u32 >>= pThis->u8IndexShift;
1344 Assert(u32 < SYSTEM_INFO_INDEX_END);
1345 pThis->uSystemInfoIndex = u32;
1346 }
1347
1348 DEVACPI_UNLOCK(pDevIns, pThis);
1349 return VINF_SUCCESS;
1350}
1351
1352/**
1353 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1354 */
1355static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1356{
1357 RT_NOREF(pvUser, offPort);
1358 if (cb != 4)
1359 return VERR_IOM_IOPORT_UNUSED;
1360
1361 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1362 DEVACPI_LOCK_R3(pDevIns, pThis);
1363
1364 VBOXSTRICTRC rc = VINF_SUCCESS;
1365 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1366 switch (uSystemInfoIndex)
1367 {
1368 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1369 *pu32 = pThis->cbRamLow;
1370 break;
1371
1372 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1373 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1374 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1375 break;
1376
1377 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1378 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1379 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1380 break;
1381
1382 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1383 *pu32 = pThis->u8UseIOApic;
1384 break;
1385
1386 case SYSTEM_INFO_INDEX_HPET_STATUS:
1387 *pu32 = pThis->fUseHpet
1388 ? ( STA_DEVICE_PRESENT_MASK
1389 | STA_DEVICE_ENABLED_MASK
1390 | STA_DEVICE_SHOW_IN_UI_MASK
1391 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1392 : 0;
1393 break;
1394
1395 case SYSTEM_INFO_INDEX_SMC_STATUS:
1396 *pu32 = pThis->fUseSmc
1397 ? ( STA_DEVICE_PRESENT_MASK
1398 | STA_DEVICE_ENABLED_MASK
1399 /* no need to show this device in the UI */
1400 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1401 : 0;
1402 break;
1403
1404 case SYSTEM_INFO_INDEX_FDC_STATUS:
1405 *pu32 = pThis->fUseFdc
1406 ? ( STA_DEVICE_PRESENT_MASK
1407 | STA_DEVICE_ENABLED_MASK
1408 | STA_DEVICE_SHOW_IN_UI_MASK
1409 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1410 : 0;
1411 break;
1412
1413 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1414 *pu32 = pThis->u32NicPciAddress;
1415 break;
1416
1417 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1418 *pu32 = pThis->u32AudioPciAddress;
1419 break;
1420
1421 case SYSTEM_INFO_INDEX_POWER_STATES:
1422 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1423 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1424 *pu32 |= RT_BIT(1);
1425 if (pThis->fS4Enabled)
1426 *pu32 |= RT_BIT(4);
1427 break;
1428
1429 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1430 *pu32 = pThis->u32IocPciAddress;
1431 break;
1432
1433 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1434 *pu32 = pThis->u32HbcPciAddress;
1435 break;
1436
1437 case SYSTEM_INFO_INDEX_PCI_BASE:
1438 /** @todo couldn't MCFG be in 64-bit range? */
1439 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1440 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1441 break;
1442
1443 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1444 /** @todo couldn't MCFG be in 64-bit range? */
1445 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1446 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1447 break;
1448
1449 case SYSTEM_INFO_INDEX_RTC_STATUS:
1450 *pu32 = pThis->fShowRtc
1451 ? ( STA_DEVICE_PRESENT_MASK
1452 | STA_DEVICE_ENABLED_MASK
1453 | STA_DEVICE_SHOW_IN_UI_MASK
1454 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1455 : 0;
1456 break;
1457
1458 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1459 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1460 {
1461 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1462 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1463 }
1464 else
1465 {
1466 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1467 pThis->idCpuLockCheck);
1468 /* Always return locked status just to be safe */
1469 *pu32 = 1;
1470 }
1471 break;
1472
1473 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1474 *pu32 = pThis->u32CpuEventType;
1475 break;
1476
1477 case SYSTEM_INFO_INDEX_CPU_EVENT:
1478 *pu32 = pThis->u32CpuEvent;
1479 break;
1480
1481 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1482 *pu32 = pThis->uSerial0IoPortBase;
1483 break;
1484
1485 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1486 *pu32 = pThis->uSerial0Irq;
1487 break;
1488
1489 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1490 *pu32 = pThis->uSerial1IoPortBase;
1491 break;
1492
1493 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1494 *pu32 = pThis->uSerial1Irq;
1495 break;
1496
1497 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1498 *pu32 = pThis->uSerial2IoPortBase;
1499 break;
1500
1501 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1502 *pu32 = pThis->uSerial2Irq;
1503 break;
1504
1505 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1506 *pu32 = pThis->uSerial3IoPortBase;
1507 break;
1508
1509 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1510 *pu32 = pThis->uSerial3Irq;
1511 break;
1512
1513 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1514 *pu32 = pThis->uParallel0IoPortBase;
1515 break;
1516
1517 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1518 *pu32 = pThis->uParallel0Irq;
1519 break;
1520
1521 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1522 *pu32 = pThis->uParallel1IoPortBase;
1523 break;
1524
1525 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1526 *pu32 = pThis->uParallel1Irq;
1527 break;
1528
1529 case SYSTEM_INFO_INDEX_END:
1530 /** @todo why isn't this setting any output value? */
1531 break;
1532
1533 /* Solaris 9 tries to read from this index */
1534 case SYSTEM_INFO_INDEX_INVALID:
1535 *pu32 = 0;
1536 break;
1537
1538 default:
1539 *pu32 = UINT32_MAX;
1540 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1541 break;
1542 }
1543
1544 DEVACPI_UNLOCK(pDevIns, pThis);
1545 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1546 return rc;
1547}
1548
1549/**
1550 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1551 */
1552static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1553{
1554 RT_NOREF(pvUser, offPort);
1555 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1556 if (cb != 4)
1557 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1558
1559 DEVACPI_LOCK_R3(pDevIns, pThis);
1560 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1561
1562 VBOXSTRICTRC rc = VINF_SUCCESS;
1563 switch (pThis->uSystemInfoIndex)
1564 {
1565 case SYSTEM_INFO_INDEX_INVALID:
1566 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1567 pThis->u8IndexShift = 0;
1568 break;
1569
1570 case SYSTEM_INFO_INDEX_VALID:
1571 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1572 pThis->u8IndexShift = 2;
1573 break;
1574
1575 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1576 pThis->idCpuLockCheck = u32;
1577 break;
1578
1579 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1580 if (u32 < pThis->cCpus)
1581 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1582 else
1583 LogRel(("ACPI: CPU %u does not exist\n", u32));
1584 break;
1585
1586 default:
1587 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1588 break;
1589 }
1590
1591 DEVACPI_UNLOCK(pDevIns, pThis);
1592 return rc;
1593}
1594
1595/**
1596 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1597 */
1598static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1599{
1600 RT_NOREF(offPort, pvUser);
1601 if (cb != 2)
1602 return VERR_IOM_IOPORT_UNUSED;
1603
1604 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1605 DEVACPI_LOCK_R3(pDevIns, pThis);
1606
1607 *pu32 = pThis->pm1a_en;
1608
1609 DEVACPI_UNLOCK(pDevIns, pThis);
1610 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1611 return VINF_SUCCESS;
1612}
1613
1614/**
1615 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1616 */
1617static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1618{
1619 RT_NOREF(offPort, pvUser);
1620 if (cb != 2 && cb != 4)
1621 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1622
1623 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1624 DEVACPI_LOCK_R3(pDevIns, pThis);
1625
1626 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1627 u32 &= ~(RSR_EN | IGN_EN);
1628 u32 &= 0xffff;
1629 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1630
1631 DEVACPI_UNLOCK(pDevIns, pThis);
1632 return VINF_SUCCESS;
1633}
1634
1635/**
1636 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1637 */
1638static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1639{
1640 RT_NOREF(offPort, pvUser);
1641 if (cb != 2)
1642 {
1643 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1644 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1645 }
1646
1647 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1648 DEVACPI_LOCK_R3(pDevIns, pThis);
1649
1650 *pu32 = pThis->pm1a_sts;
1651
1652 DEVACPI_UNLOCK(pDevIns, pThis);
1653 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1654 return VINF_SUCCESS;
1655}
1656
1657/**
1658 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1659 */
1660static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1661{
1662 RT_NOREF(offPort, pvUser);
1663 if (cb != 2 && cb != 4)
1664 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1665
1666 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1667 DEVACPI_LOCK_R3(pDevIns, pThis);
1668
1669 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1670 u32 &= 0xffff;
1671 if (u32 & PWRBTN_STS)
1672 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1673 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1674 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1675
1676 DEVACPI_UNLOCK(pDevIns, pThis);
1677 return VINF_SUCCESS;
1678}
1679
1680/**
1681 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1682 */
1683static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1684{
1685 RT_NOREF(offPort, pvUser);
1686 if (cb != 2)
1687 {
1688 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1689 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1690 }
1691
1692 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1693 DEVACPI_LOCK_R3(pDevIns, pThis);
1694
1695 *pu32 = pThis->pm1a_ctl;
1696
1697 DEVACPI_UNLOCK(pDevIns, pThis);
1698 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1699 return VINF_SUCCESS;
1700}
1701
1702/**
1703 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1704 */
1705static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1706{
1707 RT_NOREF(offPort, pvUser);
1708 if (cb != 2 && cb != 4)
1709 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1710
1711 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1712 DEVACPI_LOCK_R3(pDevIns, pThis);
1713
1714 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1715 u32 &= 0xffff;
1716 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1717
1718 VBOXSTRICTRC rc = VINF_SUCCESS;
1719 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1720 if (uSleepState != pThis->uSleepState)
1721 {
1722 pThis->uSleepState = uSleepState;
1723 switch (uSleepState)
1724 {
1725 case 0x00: /* S0 */
1726 break;
1727
1728 case 0x01: /* S1 */
1729 if (pThis->fS1Enabled)
1730 {
1731 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1732 rc = acpiR3DoSleep(pDevIns, pThis);
1733 break;
1734 }
1735 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1736 RT_FALL_THRU();
1737
1738 case 0x04: /* S4 */
1739 if (pThis->fS4Enabled)
1740 {
1741 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1742 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1743 break;
1744 }
1745 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1746 RT_FALL_THRU();
1747
1748 case 0x05: /* S5 */
1749 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1750 rc = acpiR3DoPowerOff(pDevIns);
1751 break;
1752
1753 default:
1754 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1755 break;
1756 }
1757 }
1758
1759 DEVACPI_UNLOCK(pDevIns, pThis);
1760 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1761 return rc;
1762}
1763
1764#endif /* IN_RING3 */
1765
1766/**
1767 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1768 *
1769 * @remarks The only I/O port currently implemented in all contexts.
1770 */
1771static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1772{
1773 RT_NOREF(offPort, pvUser);
1774 if (cb != 4)
1775 return VERR_IOM_IOPORT_UNUSED;
1776
1777 /*
1778 * We use the clock lock to serialize access to u64PmTimerInitial and to
1779 * make sure we get a reliable time from the clock
1780 * as well as and to prevent uPmTimerVal from being updated during read.
1781 */
1782 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1783 VBOXSTRICTRC rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VINF_IOM_R3_IOPORT_READ);
1784 if (rc == VINF_SUCCESS)
1785 {
1786 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1787 if (rc == VINF_SUCCESS)
1788 {
1789 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1790 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1791 *pu32 = pThis->uPmTimerVal;
1792
1793 DEVACPI_UNLOCK(pDevIns, pThis);
1794 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
1795
1796 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1797 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1798
1799#if 0
1800 /** @todo temporary: sanity check against running backwards */
1801 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1802 if (*pu32 - uOld >= 0x10000000)
1803 {
1804# if defined(IN_RING0)
1805 pThis->uPmTimeA = uOld;
1806 pThis->uPmTimeB = *pu32;
1807 return VERR_TM_TIMER_BAD_CLOCK;
1808# elif defined(IN_RING3)
1809 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1810# endif
1811 }
1812#endif
1813 }
1814 else
1815 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
1816 }
1817 return rc;
1818}
1819
1820#ifdef IN_RING3
1821
1822/**
1823 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
1824 */
1825static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1826{
1827 RT_NOREF(offPort, pvUser);
1828 if (cb != 1)
1829 {
1830 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1831 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1832 }
1833
1834 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1835 DEVACPI_LOCK_R3(pDevIns, pThis);
1836
1837 *pu32 = pThis->gpe0_sts & 0xff;
1838
1839 DEVACPI_UNLOCK(pDevIns, pThis);
1840 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1841 return VINF_SUCCESS;
1842}
1843
1844/**
1845 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
1846 */
1847static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1848{
1849 RT_NOREF(offPort, pvUser);
1850 if (cb != 1)
1851 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1852
1853 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1854 DEVACPI_LOCK_R3(pDevIns, pThis);
1855
1856 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1857 u32 = pThis->gpe0_sts & ~u32;
1858 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1859
1860 DEVACPI_UNLOCK(pDevIns, pThis);
1861 return VINF_SUCCESS;
1862}
1863
1864/**
1865 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
1866 */
1867static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1868{
1869 RT_NOREF(offPort, pvUser);
1870 if (cb != 1)
1871 {
1872 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1873 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1874 }
1875
1876 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1877 DEVACPI_LOCK_R3(pDevIns, pThis);
1878
1879 *pu32 = pThis->gpe0_en & 0xff;
1880
1881 DEVACPI_UNLOCK(pDevIns, pThis);
1882 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1883 return VINF_SUCCESS;
1884}
1885
1886/**
1887 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
1888 */
1889static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1890{
1891 RT_NOREF(offPort, pvUser);
1892 if (cb != 1)
1893 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1894
1895 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1896 DEVACPI_LOCK_R3(pDevIns, pThis);
1897
1898 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1899 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
1900
1901 DEVACPI_UNLOCK(pDevIns, pThis);
1902 return VINF_SUCCESS;
1903}
1904
1905/**
1906 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
1907 */
1908static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1909{
1910 RT_NOREF(offPort, pvUser);
1911 Log(("acpiR3SmiWrite %#x\n", u32));
1912 if (cb != 1)
1913 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1914
1915 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1916 DEVACPI_LOCK_R3(pDevIns, pThis);
1917
1918 if (u32 == ACPI_ENABLE)
1919 pThis->pm1a_ctl |= SCI_EN;
1920 else if (u32 == ACPI_DISABLE)
1921 pThis->pm1a_ctl &= ~SCI_EN;
1922 else
1923 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1924
1925 DEVACPI_UNLOCK(pDevIns, pThis);
1926 return VINF_SUCCESS;
1927}
1928
1929/**
1930 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
1931 */
1932static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1933{
1934 RT_NOREF(offPort, pvUser);
1935 Log(("acpiR3ResetWrite: %#x\n", u32));
1936 NOREF(pvUser);
1937 if (cb != 1)
1938 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1939
1940 /* No state locking required. */
1941 VBOXSTRICTRC rc;
1942 if (u32 == ACPI_RESET_REG_VAL)
1943 {
1944 LogRel(("ACPI: Reset initiated by ACPI\n"));
1945 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
1946 }
1947 else
1948 {
1949 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1950 rc = VINF_SUCCESS;
1951 }
1952
1953 return rc;
1954}
1955
1956# ifdef DEBUG_ACPI
1957
1958/**
1959 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
1960 */
1961static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1962{
1963 NOREF(pvUser);
1964 switch (cb)
1965 {
1966 case 1:
1967 Log(("%#x\n", u32 & 0xff));
1968 break;
1969 case 2:
1970 Log(("%#6x\n", u32 & 0xffff));
1971 break;
1972 case 4:
1973 Log(("%#10x\n", u32));
1974 break;
1975 default:
1976 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1977 }
1978 return VINF_SUCCESS;
1979}
1980
1981/**
1982 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
1983 */
1984static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1985{
1986 NOREF(pvUser);
1987 switch (cb)
1988 {
1989 case 1:
1990 Log(("%c", u32 & 0xff));
1991 break;
1992 default:
1993 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1994 }
1995 return VINF_SUCCESS;
1996}
1997
1998# endif /* DEBUG_ACPI */
1999
2000/**
2001 * @callback_method_impl{FNDBGFHANDLERDEV}
2002 */
2003static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2004{
2005 RT_NOREF(pszArgs);
2006 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2007 pHlp->pfnPrintf(pHlp,
2008 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2009}
2010
2011/**
2012 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2013 *
2014 * @param pDevIns The PDM device instance.
2015 * @param pThis The ACPI shared instance data.
2016 */
2017static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, ACPIState *pThis)
2018{
2019 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2020 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2021 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2022 pPciDev->abConfig[PMBA + 2] = 0x00;
2023 pPciDev->abConfig[PMBA + 3] = 0x00;
2024}
2025
2026/**
2027 * Used to calculate the value of a PM I/O port.
2028 *
2029 * @returns The actual I/O port value.
2030 * @param pThis The ACPI shared instance data.
2031 * @param offset The offset into the I/O space, or -1 if invalid.
2032 */
2033static RTIOPORT acpiR3CalcPmPort(ACPIState *pThis, int32_t offset)
2034{
2035 Assert(pThis->uPmIoPortBase != 0);
2036
2037 if (offset == -1)
2038 return 0;
2039
2040 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2041}
2042
2043/**
2044 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2045 * timer and GPE0 I/O ports.
2046 *
2047 * @returns VBox status code.
2048 * @param pDevIns The device instance.
2049 * @param pThis The ACPI shared instance data.
2050 */
2051static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, ACPIState *pThis)
2052{
2053 if (pThis->uPmIoPortBase == 0)
2054 return VINF_SUCCESS;
2055
2056 int rc;
2057 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2058 AssertRCReturn(rc, rc);
2059 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2060 AssertRCReturn(rc, rc);
2061 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2062 AssertRCReturn(rc, rc);
2063 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2064 AssertRCReturn(rc, rc);
2065 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2066 AssertRCReturn(rc, rc);
2067 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2068
2069 return VINF_SUCCESS;
2070}
2071
2072/**
2073 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2074 * timer and GPE0 I/O ports.
2075 *
2076 * @returns VBox status code.
2077 * @param pDevIns The device instance.
2078 * @param pThis The ACPI shared instance data.
2079 */
2080static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, ACPIState *pThis)
2081{
2082 if (pThis->uPmIoPortBase != 0)
2083 {
2084 int rc;
2085 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2086 AssertRCReturn(rc, rc);
2087 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2088 AssertRCReturn(rc, rc);
2089 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2090 AssertRCReturn(rc, rc);
2091 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2092 AssertRCReturn(rc, rc);
2093 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2094 AssertRCReturn(rc, rc);
2095 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2096 AssertRCReturn(rc, rc);
2097 }
2098 return VINF_SUCCESS;
2099}
2100
2101/**
2102 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2103 * PM1a, PM timer and GPE0 ports.
2104 *
2105 * @returns VBox status code.
2106 *
2107 * @param pDevIns The device instance.
2108 * @param pThis The ACPI shared instance data.
2109 * @param NewIoPortBase The new base address of the I/O ports.
2110 */
2111static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, ACPIState *pThis, RTIOPORT NewIoPortBase)
2112{
2113 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2114 if (NewIoPortBase != pThis->uPmIoPortBase)
2115 {
2116 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2117 if (RT_FAILURE(rc))
2118 return rc;
2119
2120 pThis->uPmIoPortBase = NewIoPortBase;
2121
2122 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2123 if (RT_FAILURE(rc))
2124 return rc;
2125
2126 /* We have to update FADT table acccording to the new base */
2127 rc = acpiR3PlantTables(pDevIns, pThis);
2128 AssertRC(rc);
2129 if (RT_FAILURE(rc))
2130 return rc;
2131 }
2132
2133 return VINF_SUCCESS;
2134}
2135
2136/**
2137 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2138 */
2139static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2140{
2141 RT_NOREF(pvUser);
2142 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2143
2144 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2145 uint8_t off = offPort & 0x000f;
2146 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2147 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2148 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2149
2150 DEVACPI_LOCK_R3(pDevIns, pThis);
2151 switch (off)
2152 {
2153 case SMBHSTSTS_OFF:
2154 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2155 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2156 break;
2157 case SMBSLVSTS_OFF:
2158 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2159 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2160 break;
2161 case SMBHSTCNT_OFF:
2162 {
2163 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2164
2165 const bool old_level = acpiSCILevel(pDevIns, pThis);
2166 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2167 if (u32 & SMBHSTCNT_START)
2168 {
2169 /* Start, trigger error as this is a dummy implementation */
2170 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2171 }
2172 if (u32 & SMBHSTCNT_KILL)
2173 {
2174 /* Kill */
2175 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2176 }
2177 const bool new_level = acpiSCILevel(pDevIns, pThis);
2178
2179 LogFunc(("old=%x new=%x\n", old_level, new_level));
2180
2181 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2182 * needs to be implemented later if it ever becomes relevant. */
2183 if (new_level != old_level)
2184 acpiSetIrq(pDevIns, new_level);
2185 break;
2186 }
2187 case SMBHSTCMD_OFF:
2188 pThis->u8SMBusHstCmd = u32;
2189 break;
2190 case SMBHSTADD_OFF:
2191 pThis->u8SMBusHstAdd = u32;
2192 break;
2193 case SMBHSTDAT0_OFF:
2194 pThis->u8SMBusHstDat0 = u32;
2195 break;
2196 case SMBHSTDAT1_OFF:
2197 pThis->u8SMBusHstDat1 = u32;
2198 break;
2199 case SMBBLKDAT_OFF:
2200 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2201 pThis->u8SMBusBlkIdx++;
2202 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2203 break;
2204 case SMBSLVCNT_OFF:
2205 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2206 break;
2207 case SMBSHDWCMD_OFF:
2208 /* readonly register */
2209 break;
2210 case SMBSLVEVT_OFF:
2211 pThis->u16SMBusSlvEvt = u32;
2212 break;
2213 case SMBSLVDAT_OFF:
2214 /* readonly register */
2215 break;
2216 default:
2217 /* caught by the sanity check above */
2218 ;
2219 }
2220
2221 DEVACPI_UNLOCK(pDevIns, pThis);
2222 return VINF_SUCCESS;
2223}
2224
2225/**
2226 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2227 */
2228static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2229{
2230 RT_NOREF(pvUser);
2231 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2232
2233 VBOXSTRICTRC rc = VINF_SUCCESS;
2234 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2235 uint8_t const off = offPort & 0x000f;
2236 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2237 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2238 return VERR_IOM_IOPORT_UNUSED;
2239
2240 DEVACPI_LOCK_R3(pDevIns, pThis);
2241 switch (off)
2242 {
2243 case SMBHSTSTS_OFF:
2244 *pu32 = pThis->u8SMBusHstSts;
2245 break;
2246 case SMBSLVSTS_OFF:
2247 *pu32 = pThis->u8SMBusSlvSts;
2248 break;
2249 case SMBHSTCNT_OFF:
2250 pThis->u8SMBusBlkIdx = 0;
2251 *pu32 = pThis->u8SMBusHstCnt;
2252 break;
2253 case SMBHSTCMD_OFF:
2254 *pu32 = pThis->u8SMBusHstCmd;
2255 break;
2256 case SMBHSTADD_OFF:
2257 *pu32 = pThis->u8SMBusHstAdd;
2258 break;
2259 case SMBHSTDAT0_OFF:
2260 *pu32 = pThis->u8SMBusHstDat0;
2261 break;
2262 case SMBHSTDAT1_OFF:
2263 *pu32 = pThis->u8SMBusHstDat1;
2264 break;
2265 case SMBBLKDAT_OFF:
2266 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2267 pThis->u8SMBusBlkIdx++;
2268 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2269 break;
2270 case SMBSLVCNT_OFF:
2271 *pu32 = pThis->u8SMBusSlvCnt;
2272 break;
2273 case SMBSHDWCMD_OFF:
2274 *pu32 = pThis->u8SMBusShdwCmd;
2275 break;
2276 case SMBSLVEVT_OFF:
2277 *pu32 = pThis->u16SMBusSlvEvt;
2278 break;
2279 case SMBSLVDAT_OFF:
2280 *pu32 = pThis->u16SMBusSlvDat;
2281 break;
2282 default:
2283 /* caught by the sanity check above */
2284 rc = VERR_IOM_IOPORT_UNUSED;
2285 }
2286 DEVACPI_UNLOCK(pDevIns, pThis);
2287
2288 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2289 return rc;
2290}
2291
2292/**
2293 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2294 *
2295 * @param pDevIns The PDM device instance.
2296 * @param pThis The ACPI shared instance data.
2297 */
2298static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, ACPIState *pThis)
2299{
2300 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2301 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2302 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2303 pPciDev->abConfig[SMBBA+2] = 0x00;
2304 pPciDev->abConfig[SMBBA+3] = 0x00;
2305 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2306 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2307 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2308 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2309 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2310}
2311
2312/**
2313 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2314 *
2315 * @param pThis The ACPI shared instance data.
2316 */
2317static void acpiR3SMBusResetDevice(ACPIState *pThis)
2318{
2319 pThis->u8SMBusHstSts = 0x00;
2320 pThis->u8SMBusSlvSts = 0x00;
2321 pThis->u8SMBusHstCnt = 0x00;
2322 pThis->u8SMBusHstCmd = 0x00;
2323 pThis->u8SMBusHstAdd = 0x00;
2324 pThis->u8SMBusHstDat0 = 0x00;
2325 pThis->u8SMBusHstDat1 = 0x00;
2326 pThis->u8SMBusSlvCnt = 0x00;
2327 pThis->u8SMBusShdwCmd = 0x00;
2328 pThis->u16SMBusSlvEvt = 0x0000;
2329 pThis->u16SMBusSlvDat = 0x0000;
2330 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2331 pThis->u8SMBusBlkIdx = 0;
2332}
2333
2334/**
2335 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2336 *
2337 * @returns VBox status code.
2338 * @param pDevIns The device instance.
2339 * @param pThis The ACPI shared instance data.
2340 */
2341static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, ACPIState *pThis)
2342{
2343 if (pThis->uSMBusIoPortBase != 0)
2344 {
2345 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2346 AssertRCReturn(rc, rc);
2347 }
2348 return VINF_SUCCESS;
2349}
2350
2351/**
2352 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2353 *
2354 * @returns VBox status code.
2355 * @param pDevIns The device instance.
2356 * @param pThis The ACPI shared instance data.
2357 */
2358static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, ACPIState *pThis)
2359{
2360 if (pThis->uSMBusIoPortBase != 0)
2361 {
2362 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2363 AssertRCReturn(rc, rc);
2364 }
2365 return VINF_SUCCESS;
2366}
2367
2368/**
2369 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2370 * SMBus ports.
2371 *
2372 * @returns VBox status code.
2373 *
2374 * @param pDevIns The device instance.
2375 * @param pThis The ACPI shared instance data.
2376 * @param NewIoPortBase The new base address of the I/O ports.
2377 */
2378static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, ACPIState *pThis, RTIOPORT NewIoPortBase)
2379{
2380 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2381 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2382 {
2383 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2384 AssertRCReturn(rc, rc);
2385
2386 pThis->uSMBusIoPortBase = NewIoPortBase;
2387
2388 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2389 AssertRCReturn(rc, rc);
2390
2391#if 0 /* is there an FADT table entry for the SMBus base? */
2392 /* We have to update FADT table acccording to the new base */
2393 rc = acpiR3PlantTables(pThis);
2394 AssertRC(rc);
2395 if (RT_FAILURE(rc))
2396 return rc;
2397#endif
2398 }
2399
2400 return VINF_SUCCESS;
2401}
2402
2403
2404/**
2405 * Saved state structure description, version 4.
2406 */
2407static const SSMFIELD g_AcpiSavedStateFields4[] =
2408{
2409 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2410 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2411 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2412 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2413 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2414 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2415 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2416 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2417 SSMFIELD_ENTRY(ACPIState, u64RamSize),
2418 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2419 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
2420 SSMFIELD_ENTRY(ACPIState, uSleepState),
2421 SSMFIELD_ENTRY_TERM()
2422};
2423
2424/**
2425 * Saved state structure description, version 5.
2426 */
2427static const SSMFIELD g_AcpiSavedStateFields5[] =
2428{
2429 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2430 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2431 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2432 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2433 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2434 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2435 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2436 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2437 SSMFIELD_ENTRY(ACPIState, uSleepState),
2438 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2439 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2440 SSMFIELD_ENTRY_TERM()
2441};
2442
2443/**
2444 * Saved state structure description, version 6.
2445 */
2446static const SSMFIELD g_AcpiSavedStateFields6[] =
2447{
2448 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2449 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2450 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2451 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2452 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2453 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2454 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2455 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2456 SSMFIELD_ENTRY(ACPIState, uSleepState),
2457 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2458 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2459 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2460 SSMFIELD_ENTRY_TERM()
2461};
2462
2463/**
2464 * Saved state structure description, version 7.
2465 */
2466static const SSMFIELD g_AcpiSavedStateFields7[] =
2467{
2468 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2469 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2470 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2471 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2472 SSMFIELD_ENTRY(ACPIState, uPmTimerVal),
2473 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2474 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2475 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2476 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2477 SSMFIELD_ENTRY(ACPIState, uSleepState),
2478 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2479 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2480 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2481 SSMFIELD_ENTRY_TERM()
2482};
2483
2484/**
2485 * Saved state structure description, version 8.
2486 */
2487static const SSMFIELD g_AcpiSavedStateFields8[] =
2488{
2489 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2490 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2491 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2492 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
2493 SSMFIELD_ENTRY(ACPIState, uPmTimerVal),
2494 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2495 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2496 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2497 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2498 SSMFIELD_ENTRY(ACPIState, uSleepState),
2499 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2500 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2501 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2502 SSMFIELD_ENTRY(ACPIState, uSMBusIoPortBase),
2503 SSMFIELD_ENTRY(ACPIState, u8SMBusHstSts),
2504 SSMFIELD_ENTRY(ACPIState, u8SMBusSlvSts),
2505 SSMFIELD_ENTRY(ACPIState, u8SMBusHstCnt),
2506 SSMFIELD_ENTRY(ACPIState, u8SMBusHstCmd),
2507 SSMFIELD_ENTRY(ACPIState, u8SMBusHstAdd),
2508 SSMFIELD_ENTRY(ACPIState, u8SMBusHstDat0),
2509 SSMFIELD_ENTRY(ACPIState, u8SMBusHstDat1),
2510 SSMFIELD_ENTRY(ACPIState, u8SMBusSlvCnt),
2511 SSMFIELD_ENTRY(ACPIState, u8SMBusShdwCmd),
2512 SSMFIELD_ENTRY(ACPIState, u16SMBusSlvEvt),
2513 SSMFIELD_ENTRY(ACPIState, u16SMBusSlvDat),
2514 SSMFIELD_ENTRY(ACPIState, au8SMBusBlkDat),
2515 SSMFIELD_ENTRY(ACPIState, u8SMBusBlkIdx),
2516 SSMFIELD_ENTRY_TERM()
2517};
2518
2519/**
2520 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2521 */
2522static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2523{
2524 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2525 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2526 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2527}
2528
2529/**
2530 * @callback_method_impl{FNSSMDEVLOADEXEC}
2531 */
2532static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2533{
2534 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2535 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2536 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2537
2538 /*
2539 * Unmap PM I/O ports, will remap it with the actual base after state
2540 * successfully loaded.
2541 */
2542 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2543 if (RT_FAILURE(rc))
2544 return rc;
2545
2546 /*
2547 * Unregister SMBus handlers, will register with actual base after state
2548 * successfully loaded.
2549 */
2550 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2551 AssertRCReturn(rc, rc);
2552 acpiR3SMBusResetDevice(pThis);
2553
2554 switch (uVersion)
2555 {
2556 case 4:
2557 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2558 break;
2559 case 5:
2560 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2561 break;
2562 case 6:
2563 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2564 break;
2565 case 7:
2566 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2567 break;
2568 case 8:
2569 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2570 break;
2571 default:
2572 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2573 break;
2574 }
2575 if (RT_SUCCESS(rc))
2576 {
2577 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2578 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2579 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2580 if (RT_FAILURE(rc))
2581 return rc;
2582 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2583 if (RT_FAILURE(rc))
2584 return rc;
2585 rc = acpiR3FetchBatteryStatus(pThis);
2586 if (RT_FAILURE(rc))
2587 return rc;
2588 rc = acpiR3FetchBatteryInfo(pThis);
2589 if (RT_FAILURE(rc))
2590 return rc;
2591 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2592 DEVACPI_LOCK_R3(pDevIns, pThis);
2593 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2594 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2595 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2596 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2597 DEVACPI_UNLOCK(pDevIns, pThis);
2598 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
2599 }
2600 return rc;
2601}
2602
2603/**
2604 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2605 */
2606static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2607{
2608 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IBase);
2609 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2610 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThis->IACPIPort);
2611 return NULL;
2612}
2613
2614/**
2615 * Calculate the check sum for some ACPI data before planting it.
2616 *
2617 * All the bytes must add up to 0.
2618 *
2619 * @returns check sum.
2620 * @param pvSrc What to check sum.
2621 * @param cbData The amount of data to checksum.
2622 */
2623static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2624{
2625 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2626 uint8_t uSum = 0;
2627 for (size_t i = 0; i < cbData; ++i)
2628 uSum += pbSrc[i];
2629 return -uSum;
2630}
2631
2632/**
2633 * Prepare a ACPI table header.
2634 */
2635static void acpiR3PrepareHeader(ACPIState *pThis, ACPITBLHEADER *header,
2636 const char au8Signature[4],
2637 uint32_t u32Length, uint8_t u8Revision)
2638{
2639 memcpy(header->au8Signature, au8Signature, 4);
2640 header->u32Length = RT_H2LE_U32(u32Length);
2641 header->u8Revision = u8Revision;
2642 memcpy(header->au8OemId, pThis->au8OemId, 6);
2643 memcpy(header->au8OemTabId, "VBOX", 4);
2644 memcpy(header->au8OemTabId+4, au8Signature, 4);
2645 header->u32OemRevision = RT_H2LE_U32(1);
2646 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2647 header->u32CreatorRev = pThis->u32CreatorRev;
2648}
2649
2650/**
2651 * Initialize a generic address structure (ACPIGENADDR).
2652 */
2653static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2654 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2655 uint8_t u8AccessSize, uint64_t u64Address)
2656{
2657 g->u8AddressSpaceId = u8AddressSpaceId;
2658 g->u8RegisterBitWidth = u8RegisterBitWidth;
2659 g->u8RegisterBitOffset = u8RegisterBitOffset;
2660 g->u8AccessSize = u8AccessSize;
2661 g->u64Address = RT_H2LE_U64(u64Address);
2662}
2663
2664/**
2665 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2666 */
2667DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2668{
2669 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2670}
2671
2672/**
2673 * Plant the Differentiated System Description Table (DSDT).
2674 */
2675static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2676{
2677 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2678}
2679
2680/**
2681 * Plant the Secondary System Description Table (SSDT).
2682 */
2683static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2684{
2685 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2686}
2687
2688/**
2689 * Plant the Firmware ACPI Control Structure (FACS).
2690 */
2691static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2692{
2693 ACPITBLFACS facs;
2694
2695 memset(&facs, 0, sizeof(facs));
2696 memcpy(facs.au8Signature, "FACS", 4);
2697 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2698 facs.u32HWSignature = RT_H2LE_U32(0);
2699 facs.u32FWVector = RT_H2LE_U32(0);
2700 facs.u32GlobalLock = RT_H2LE_U32(0);
2701 facs.u32Flags = RT_H2LE_U32(0);
2702 facs.u64X_FWVector = RT_H2LE_U64(0);
2703 facs.u8Version = 1;
2704
2705 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2706}
2707
2708/**
2709 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2710 */
2711static void acpiR3SetupFadt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2712 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2713{
2714 ACPITBLFADT fadt;
2715
2716 /* First the ACPI version 2+ version of the structure. */
2717 memset(&fadt, 0, sizeof(fadt));
2718 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2719 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2720 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2721 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2722 fadt.u8PreferredPMProfile = 0; /* unspecified */
2723 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2724 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2725 fadt.u8AcpiEnable = ACPI_ENABLE;
2726 fadt.u8AcpiDisable = ACPI_DISABLE;
2727 fadt.u8S4BIOSReq = 0;
2728 fadt.u8PStateCnt = 0;
2729 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2730 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2731 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2732 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2733 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2734 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2735 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2736 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2737 fadt.u8PM1EVTLEN = 4;
2738 fadt.u8PM1CTLLEN = 2;
2739 fadt.u8PM2CTLLEN = 0;
2740 fadt.u8PMTMLEN = 4;
2741 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2742 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2743 fadt.u8GPE1BASE = GPE1_BASE;
2744 fadt.u8CSTCNT = 0;
2745 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2746 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2747 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2748 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2749 fadt.u8DutyOffset = 0;
2750 fadt.u8DutyWidth = 0;
2751 fadt.u8DayAlarm = 0;
2752 fadt.u8MonAlarm = 0;
2753 fadt.u8Century = 0;
2754 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2755 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2756 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2757 | FADT_FL_FIX_RTC
2758 | FADT_FL_TMR_VAL_EXT
2759 | FADT_FL_RESET_REG_SUP);
2760
2761 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2762 if (pThis->fCpuHotPlug)
2763 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2764
2765 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2766 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2767 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2768 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2769 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2770 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2771 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2772 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2773 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2774 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2775 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2776 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2777 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2778 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2779
2780 /* Now the ACPI 1.0 version. */
2781 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2782 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2783 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2784 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2785 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2786}
2787
2788/**
2789 * Plant the root System Description Table.
2790 *
2791 * The RSDT and XSDT tables are basically identical. The only difference is 32
2792 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2793 * ACPI 2.0 and up.
2794 */
2795static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2796{
2797 ACPITBLRSDT *rsdt;
2798 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2799
2800 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2801 if (!rsdt)
2802 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2803
2804 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2805 for (unsigned int i = 0; i < nb_entries; ++i)
2806 {
2807 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2808 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2809 }
2810 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2811 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2812 RTMemFree(rsdt);
2813 return VINF_SUCCESS;
2814}
2815
2816/**
2817 * Plant the Extended System Description Table.
2818 */
2819static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2820{
2821 ACPITBLXSDT *xsdt;
2822 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2823
2824 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
2825 if (!xsdt)
2826 return VERR_NO_TMP_MEMORY;
2827
2828 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
2829
2830 if (pThis->cCustTbls > 0)
2831 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2832
2833 for (unsigned int i = 0; i < nb_entries; ++i)
2834 {
2835 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2836 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2837 }
2838 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, size);
2839 acpiR3PhysCopy(pDevIns, addr, xsdt, size);
2840 RTMemFree(xsdt);
2841 return VINF_SUCCESS;
2842}
2843
2844/**
2845 * Plant the Root System Description Pointer (RSDP).
2846 */
2847static void acpiR3SetupRsdp(ACPIState *pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2848{
2849 memset(rsdp, 0, sizeof(*rsdp));
2850
2851 /* ACPI 1.0 part (RSDT) */
2852 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2853 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2854 rsdp->u8Revision = ACPI_REVISION;
2855 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2856 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2857
2858 /* ACPI 2.0 part (XSDT) */
2859 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2860 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2861 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2862}
2863
2864/**
2865 * Multiple APIC Description Table.
2866 *
2867 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2868 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2869 * use regular C structure and proxy to raw memory instead.
2870 */
2871class AcpiTableMadt
2872{
2873 /**
2874 * All actual data stored in dynamically allocated memory pointed by this field.
2875 */
2876 uint8_t *m_pbData;
2877 /**
2878 * Number of CPU entries in this MADT.
2879 */
2880 uint32_t m_cCpus;
2881
2882 /**
2883 * Number of interrupt overrides.
2884 */
2885 uint32_t m_cIsos;
2886
2887public:
2888 /**
2889 * Address of ACPI header
2890 */
2891 inline ACPITBLHEADER *header_addr(void) const
2892 {
2893 return (ACPITBLHEADER *)m_pbData;
2894 }
2895
2896 /**
2897 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2898 * although address is the same for all of them.
2899 */
2900 inline uint32_t *u32LAPIC_addr(void) const
2901 {
2902 return (uint32_t *)(header_addr() + 1);
2903 }
2904
2905 /**
2906 * Address of APIC flags
2907 */
2908 inline uint32_t *u32Flags_addr(void) const
2909 {
2910 return (uint32_t *)(u32LAPIC_addr() + 1);
2911 }
2912
2913 /**
2914 * Address of ISO description
2915 */
2916 inline ACPITBLISO *ISO_addr(void) const
2917 {
2918 return (ACPITBLISO *)(u32Flags_addr() + 1);
2919 }
2920
2921 /**
2922 * Address of per-CPU LAPIC descriptions
2923 */
2924 inline ACPITBLLAPIC *LApics_addr(void) const
2925 {
2926 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2927 }
2928
2929 /**
2930 * Address of IO APIC description
2931 */
2932 inline ACPITBLIOAPIC *IOApic_addr(void) const
2933 {
2934 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2935 }
2936
2937 /**
2938 * Size of MADT.
2939 * Note that this function assumes IOApic to be the last field in structure.
2940 */
2941 inline uint32_t size(void) const
2942 {
2943 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2944 }
2945
2946 /**
2947 * Raw data of MADT.
2948 */
2949 inline const uint8_t *data(void) const
2950 {
2951 return m_pbData;
2952 }
2953
2954 /**
2955 * Size of MADT for given ACPI config, useful to compute layout.
2956 */
2957 static uint32_t sizeFor(ACPIState *pThis, uint32_t cIsos)
2958 {
2959 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2960 }
2961
2962 /*
2963 * Constructor, only works in Ring 3, doesn't look like a big deal.
2964 */
2965 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2966 {
2967 m_cCpus = cCpus;
2968 m_cIsos = cIsos;
2969 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2970 uint32_t cb = size();
2971 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2972 }
2973
2974 ~AcpiTableMadt()
2975 {
2976 RTMemFree(m_pbData);
2977 }
2978};
2979
2980
2981/**
2982 * Plant the Multiple APIC Description Table (MADT).
2983 *
2984 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
2985 *
2986 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
2987 */
2988static void acpiR3SetupMadt(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr)
2989{
2990 uint16_t cpus = pThis->cCpus;
2991 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
2992
2993 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
2994
2995 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
2996 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
2997
2998 /* LAPICs records */
2999 ACPITBLLAPIC* lapic = madt.LApics_addr();
3000 for (uint16_t i = 0; i < cpus; i++)
3001 {
3002 lapic->u8Type = 0;
3003 lapic->u8Length = sizeof(ACPITBLLAPIC);
3004 lapic->u8ProcId = i;
3005 /** Must match numbering convention in MPTABLES */
3006 lapic->u8ApicId = i;
3007 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3008 lapic++;
3009 }
3010
3011 /* IO-APIC record */
3012 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3013 ioapic->u8Type = 1;
3014 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3015 /** Must match MP tables ID */
3016 ioapic->u8IOApicId = cpus;
3017 ioapic->u8Reserved = 0;
3018 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3019 ioapic->u32GSIB = RT_H2LE_U32(0);
3020
3021 /* Interrupt Source Overrides */
3022 /* Flags:
3023 bits[3:2]:
3024 00 conforms to the bus
3025 01 edge-triggered
3026 10 reserved
3027 11 level-triggered
3028 bits[1:0]
3029 00 conforms to the bus
3030 01 active-high
3031 10 reserved
3032 11 active-low */
3033 /* If changing, also update PDMIsaSetIrq() and MPS */
3034 ACPITBLISO* isos = madt.ISO_addr();
3035 /* Timer interrupt rule IRQ0 to GSI2 */
3036 isos[0].u8Type = 2;
3037 isos[0].u8Length = sizeof(ACPITBLISO);
3038 isos[0].u8Bus = 0; /* Must be 0 */
3039 isos[0].u8Source = 0; /* IRQ0 */
3040 isos[0].u32GSI = 2; /* connected to pin 2 */
3041 isos[0].u16Flags = 0; /* conform to the bus */
3042
3043 /* ACPI interrupt rule - IRQ9 to GSI9 */
3044 isos[1].u8Type = 2;
3045 isos[1].u8Length = sizeof(ACPITBLISO);
3046 isos[1].u8Bus = 0; /* Must be 0 */
3047 isos[1].u8Source = 9; /* IRQ9 */
3048 isos[1].u32GSI = 9; /* connected to pin 9 */
3049 isos[1].u16Flags = 0xf; /* active low, level triggered */
3050 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3051
3052 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3053 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3054}
3055
3056/**
3057 * Plant the High Performance Event Timer (HPET) descriptor.
3058 */
3059static void acpiR3SetupHpet(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 addr)
3060{
3061 ACPITBLHPET hpet;
3062
3063 memset(&hpet, 0, sizeof(hpet));
3064
3065 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3066 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3067 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3068 0 /* Memory address space */,
3069 64 /* Register bit width */,
3070 0 /* Bit offset */,
3071 0, /* Register access size, is it correct? */
3072 0xfed00000 /* Address */);
3073
3074 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3075 hpet.u32Number = 0;
3076 hpet.u32MinTick = 4096;
3077 hpet.u8Attributes = 0;
3078
3079 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3080
3081 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3082}
3083
3084
3085/**
3086 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3087 * descriptor.
3088 *
3089 * @param pThis The ACPI shared instance data.
3090 * @param GCPhysDst Where to plant it.
3091 */
3092static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, ACPIState *pThis, RTGCPHYS32 GCPhysDst)
3093{
3094 struct
3095 {
3096 ACPITBLMCFG hdr;
3097 ACPITBLMCFGENTRY entry;
3098 } tbl;
3099 uint8_t u8StartBus = 0;
3100 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3101
3102 RT_ZERO(tbl);
3103
3104 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3105 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3106 tbl.entry.u8StartBus = u8StartBus;
3107 tbl.entry.u8EndBus = u8EndBus;
3108 // u16PciSegmentGroup must match _SEG in ACPI table
3109
3110 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3111
3112 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3113}
3114
3115/**
3116 * Used by acpiR3PlantTables and acpiConstruct.
3117 *
3118 * @returns Guest memory address.
3119 */
3120static uint32_t apicR3FindRsdpSpace(void)
3121{
3122 return 0xe0000;
3123}
3124
3125/**
3126 * Called by acpiR3Construct to read and allocate a custom ACPI table
3127 *
3128 * @param pDevIns The device instance.
3129 * @param ppu8CustBin Address to receive the address of the table
3130 * @param pcbCustBin Address to receive the size of the the table.
3131 * @param pszCustBinFile
3132 * @param cbBufAvail Maximum space in bytes available for the custom
3133 * table (including header).
3134 */
3135static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3136 char *pszCustBinFile, uint32_t cbBufAvail)
3137{
3138 RTFILE FileCUSTBin;
3139 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3140 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3141 if (RT_SUCCESS(rc))
3142 {
3143 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3144 if (RT_SUCCESS(rc))
3145 {
3146 /* The following checks should be in sync the AssertReleaseMsg's below. */
3147 if ( *pcbCustBin > cbBufAvail
3148 || *pcbCustBin < sizeof(ACPITBLHEADER))
3149 rc = VERR_TOO_MUCH_DATA;
3150
3151 /*
3152 * Allocate buffer for the custom table binary data.
3153 */
3154 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3155 if (*ppu8CustBin)
3156 {
3157 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3158 if (RT_FAILURE(rc))
3159 {
3160 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3161 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3162 *ppu8CustBin = NULL;
3163 }
3164 }
3165 else
3166 {
3167 rc = VERR_NO_MEMORY;
3168 }
3169 RTFileClose(FileCUSTBin);
3170 }
3171 }
3172 return rc;
3173}
3174
3175/**
3176 * Create the ACPI tables in guest memory.
3177 */
3178static int acpiR3PlantTables(PPDMDEVINS pDevIns, ACPIState *pThis)
3179{
3180 int rc;
3181 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3182 RTGCPHYS32 GCPhysHpet = 0;
3183 RTGCPHYS32 GCPhysApic = 0;
3184 RTGCPHYS32 GCPhysSsdt = 0;
3185 RTGCPHYS32 GCPhysMcfg = 0;
3186 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3187 uint32_t addend = 0;
3188 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3189 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3190 uint32_t cAddr;
3191 uint32_t iMadt = 0;
3192 uint32_t iHpet = 0;
3193 uint32_t iSsdt = 0;
3194 uint32_t iMcfg = 0;
3195 uint32_t iCust = 0;
3196 size_t cbRsdt = sizeof(ACPITBLHEADER);
3197 size_t cbXsdt = sizeof(ACPITBLHEADER);
3198
3199 cAddr = 1; /* FADT */
3200 if (pThis->u8UseIOApic)
3201 iMadt = cAddr++; /* MADT */
3202
3203 if (pThis->fUseHpet)
3204 iHpet = cAddr++; /* HPET */
3205
3206 if (pThis->fUseMcfg)
3207 iMcfg = cAddr++; /* MCFG */
3208
3209 if (pThis->cCustTbls > 0)
3210 {
3211 iCust = cAddr; /* CUST */
3212 cAddr += pThis->cCustTbls;
3213 }
3214
3215 iSsdt = cAddr++; /* SSDT */
3216
3217 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3218 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3219
3220 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3221 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3222
3223 /*
3224 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3225 * The latter starts never below 4G.
3226 */
3227 PVM pVM = PDMDevHlpGetVM(pDevIns);
3228 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3229 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3230
3231 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3232 if (pThis->fPciPref64Enabled)
3233 {
3234 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3235 if (pThis->u64PciPref64Max > u64PciPref64Min)
3236 {
3237 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3238 pThis->u64PciPref64Min = u64PciPref64Min;
3239 LogRel(("ACPI: enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3240 u64PciPref64Min, pThis->u64PciPref64Max-1));
3241 }
3242 else
3243 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3244 u64PciPref64Min, pThis->u64PciPref64Max-1));
3245 }
3246 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3247 {
3248 /* Note: This is also enforced by DevPcBios.cpp. */
3249 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3250 cbBelow4GB = UINT32_C(0xfe000000);
3251 }
3252 pThis->cbRamLow = cbBelow4GB;
3253
3254 GCPhysCur = 0;
3255 GCPhysRsdt = GCPhysCur;
3256
3257 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3258 GCPhysXsdt = GCPhysCur;
3259
3260 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3261 GCPhysFadtAcpi1 = GCPhysCur;
3262
3263 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3264 GCPhysFadtAcpi2 = GCPhysCur;
3265
3266 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3267 GCPhysFacs = GCPhysCur;
3268
3269 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3270 if (pThis->u8UseIOApic)
3271 {
3272 GCPhysApic = GCPhysCur;
3273 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3274 }
3275 if (pThis->fUseHpet)
3276 {
3277 GCPhysHpet = GCPhysCur;
3278 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3279 }
3280 if (pThis->fUseMcfg)
3281 {
3282 GCPhysMcfg = GCPhysCur;
3283 /* Assume one entry */
3284 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3285 }
3286
3287 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3288 {
3289 aGCPhysCust[i] = GCPhysCur;
3290 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThis->acbCustBin[i], 16);
3291 }
3292
3293 void *pvSsdtCode = NULL;
3294 size_t cbSsdt = 0;
3295 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3296 if (RT_FAILURE(rc))
3297 return rc;
3298
3299 GCPhysSsdt = GCPhysCur;
3300 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3301
3302 GCPhysDsdt = GCPhysCur;
3303
3304 void *pvDsdtCode = NULL;
3305 size_t cbDsdt = 0;
3306 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3307 if (RT_FAILURE(rc))
3308 return rc;
3309
3310 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3311
3312 if (GCPhysCur > 0x10000)
3313 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3314 N_("Error: ACPI tables bigger than 64KB"));
3315
3316 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3317 addend = pThis->cbRamLow - 0x10000;
3318 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3319 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3320 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3321 if (pThis->u8UseIOApic)
3322 Log((" MADT 0x%08X", GCPhysApic + addend));
3323 if (pThis->fUseHpet)
3324 Log((" HPET 0x%08X", GCPhysHpet + addend));
3325 if (pThis->fUseMcfg)
3326 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3327 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3328 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3329 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3330 Log(("\n"));
3331
3332 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3333 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3334 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3335 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3336 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3337
3338 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3339 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3340 if (pThis->u8UseIOApic)
3341 {
3342 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3343 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3344 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3345 }
3346 if (pThis->fUseHpet)
3347 {
3348 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3349 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3350 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3351 }
3352 if (pThis->fUseMcfg)
3353 {
3354 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3355 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3356 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3357 }
3358 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3359 {
3360 Assert(i < MAX_CUST_TABLES);
3361 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThis->apu8CustBin[i], pThis->acbCustBin[i]);
3362 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3363 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3364 uint8_t* pSig = pThis->apu8CustBin[i];
3365 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3366 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3367 }
3368
3369 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3370 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3371 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3372 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3373
3374 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3375 if (RT_FAILURE(rc))
3376 return rc;
3377 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3378}
3379
3380/**
3381 * @callback_method_impl{FNPCICONFIGREAD}
3382 */
3383static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3384 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3385{
3386 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3387 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3388 return rcStrict;
3389}
3390
3391/**
3392 * @callback_method_impl{FNPCICONFIGWRITE}
3393 */
3394static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3395 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3396{
3397 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3398
3399 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3400 DEVACPI_LOCK_R3(pDevIns, pThis);
3401
3402 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3403 {
3404 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3405 u32Value = SCI_INT;
3406 }
3407
3408 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3409
3410 /* Assume that the base address is only changed when the corresponding
3411 * hardware functionality is disabled. The IO region is mapped when the
3412 * functionality is enabled by the guest. */
3413
3414 if (uAddress == PMREGMISC)
3415 {
3416 RTIOPORT NewIoPortBase = 0;
3417 /* Check Power Management IO Space Enable (PMIOSE) bit */
3418 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3419 {
3420 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3421 NewIoPortBase &= 0xffc0;
3422 }
3423
3424 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, NewIoPortBase);
3425 AssertRC(rc);
3426 }
3427
3428 if (uAddress == SMBHSTCFG)
3429 {
3430 RTIOPORT NewIoPortBase = 0;
3431 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3432 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3433 {
3434 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3435 NewIoPortBase &= 0xfff0;
3436 }
3437
3438 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3439 AssertRC(rc);
3440 }
3441
3442 DEVACPI_UNLOCK(pDevIns, pThis);
3443 return rcStrict;
3444}
3445
3446/**
3447 * Attach a new CPU.
3448 *
3449 * @returns VBox status code.
3450 * @param pDevIns The device instance.
3451 * @param iLUN The logical unit which is being attached.
3452 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3453 *
3454 * @remarks This code path is not used during construction.
3455 */
3456static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3457{
3458 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3459 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3460
3461 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3462 ("Hot-plug flag is not set\n"),
3463 VERR_NOT_SUPPORTED);
3464 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3465
3466 /* Check if it was already attached */
3467 int rc = VINF_SUCCESS;
3468 DEVACPI_LOCK_R3(pDevIns, pThis);
3469 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3470 {
3471 PPDMIBASE IBaseTmp;
3472 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3473 if (RT_SUCCESS(rc))
3474 {
3475 /* Enable the CPU */
3476 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3477
3478 /*
3479 * Lock the CPU because we don't know if the guest will use it or not.
3480 * Prevents ejection while the CPU is still used
3481 */
3482 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3483 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3484 pThis->u32CpuEvent = iLUN;
3485
3486 /* Notify the guest */
3487 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3488 }
3489 }
3490 DEVACPI_UNLOCK(pDevIns, pThis);
3491 return rc;
3492}
3493
3494/**
3495 * Detach notification.
3496 *
3497 * @param pDevIns The device instance.
3498 * @param iLUN The logical unit which is being detached.
3499 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3500 */
3501static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3502{
3503 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3504
3505 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3506
3507 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3508 ("Hot-plug flag is not set\n"));
3509
3510 /* Check if it was already detached */
3511 DEVACPI_LOCK_R3(pDevIns, pThis);
3512 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3513 {
3514 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3515 {
3516 /* Disable the CPU */
3517 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3518 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3519 pThis->u32CpuEvent = iLUN;
3520
3521 /* Notify the guest */
3522 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3523 }
3524 else
3525 AssertMsgFailed(("CPU is still locked by the guest\n"));
3526 }
3527 DEVACPI_UNLOCK(pDevIns, pThis);
3528}
3529
3530/**
3531 * @interface_method_impl{PDMDEVREG,pfnResume}
3532 */
3533static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3534{
3535 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3536 if (pThis->fSetWakeupOnResume)
3537 {
3538 Log(("acpiResume: setting WAK_STS\n"));
3539 pThis->fSetWakeupOnResume = false;
3540 pThis->pm1a_sts |= WAK_STS;
3541 }
3542}
3543
3544/**
3545 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3546 */
3547static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3548{
3549 RT_NOREF1(enmCtx);
3550 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3551 acpiR3PlantTables(pDevIns, pThis);
3552}
3553
3554/**
3555 * @interface_method_impl{PDMDEVREG,pfnReset}
3556 */
3557static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3558{
3559 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3560
3561 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3562 acpiSetIrq(pDevIns, 0);
3563
3564 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3565 pThis->pm1a_en = 0;
3566 pThis->pm1a_sts = 0;
3567 pThis->pm1a_ctl = 0;
3568 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3569 pThis->uPmTimerVal = 0;
3570 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3571 pThis->uPmTimeOld = pThis->uPmTimerVal;
3572 pThis->uBatteryIndex = 0;
3573 pThis->uSystemInfoIndex = 0;
3574 pThis->gpe0_en = 0;
3575 pThis->gpe0_sts = 0;
3576 pThis->uSleepState = 0;
3577 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
3578
3579 /* Real device behavior is resetting only the PM controller state,
3580 * but we're additionally doing the job of the BIOS. */
3581 acpiR3UpdatePmHandlers(pDevIns, pThis, PM_PORT_BASE);
3582 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3583
3584 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3585 * state. Real device behavior is only the SMBus controller state reset,
3586 * but we're additionally doing the job of the BIOS. */
3587 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3588 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3589 acpiR3SMBusResetDevice(pThis);
3590}
3591
3592/**
3593 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3594 */
3595static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3596{
3597 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3598 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3599 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3600 {
3601 if (pThis->apu8CustBin[i])
3602 {
3603 PDMDevHlpMMHeapFree(pDevIns, pThis->apu8CustBin[i]);
3604 pThis->apu8CustBin[i] = NULL;
3605 }
3606 }
3607 return VINF_SUCCESS;
3608}
3609
3610/**
3611 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3612 */
3613static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3614{
3615 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3616 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3617 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3618
3619 /*
3620 * Init data and set defaults.
3621 */
3622 /** @todo move more of the code up! */
3623
3624 pThis->pDevIns = pDevIns;
3625 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3626 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3627 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3628 pThis->u32CpuEventType = 0;
3629 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3630
3631 /* The first CPU can't be attached/detached */
3632 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3633 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3634
3635 /* IBase */
3636 pThis->IBase.pfnQueryInterface = acpiR3QueryInterface;
3637 /* IACPIPort */
3638 pThis->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3639 pThis->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3640 pThis->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3641 pThis->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3642 pThis->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3643 pThis->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3644 pThis->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3645
3646 /*
3647 * Set the default critical section to NOP (related to the PM timer).
3648 */
3649 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3650 AssertRCReturn(rc, rc);
3651
3652 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3653 AssertRCReturn(rc, rc);
3654
3655 /*
3656 * Validate and read the configuration.
3657 */
3658 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
3659 "IOAPIC"
3660 "|NumCPUs"
3661 "|HpetEnabled"
3662 "|McfgEnabled"
3663 "|McfgBase"
3664 "|McfgLength"
3665 "|PciPref64Enabled"
3666 "|PciPref64LimitGB"
3667 "|SmcEnabled"
3668 "|FdcEnabled"
3669 "|ShowRtc"
3670 "|ShowCpu"
3671 "|NicPciAddress"
3672 "|AudioPciAddress"
3673 "|IocPciAddress"
3674 "|HostBusPciAddress"
3675 "|EnableSuspendToDisk"
3676 "|PowerS1Enabled"
3677 "|PowerS4Enabled"
3678 "|CpuHotPlug"
3679 "|AmlFilePath"
3680 "|Serial0IoPortBase"
3681 "|Serial1IoPortBase"
3682 "|Serial2IoPortBase"
3683 "|Serial3IoPortBase"
3684 "|Serial0Irq"
3685 "|Serial1Irq"
3686 "|Serial2Irq"
3687 "|Serial3Irq"
3688 "|AcpiOemId"
3689 "|AcpiCreatorId"
3690 "|AcpiCreatorRev"
3691 "|CustomTable"
3692 "|CustomTable0"
3693 "|CustomTable1"
3694 "|CustomTable2"
3695 "|CustomTable3"
3696 "|Parallel0IoPortBase"
3697 "|Parallel1IoPortBase"
3698 "|Parallel0Irq"
3699 "|Parallel1Irq"
3700 , "");
3701
3702 /* query whether we are supposed to present an IOAPIC */
3703 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3704 if (RT_FAILURE(rc))
3705 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
3706
3707 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3708 if (RT_FAILURE(rc))
3709 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3710
3711 /* query whether we are supposed to present an FDC controller */
3712 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3713 if (RT_FAILURE(rc))
3714 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
3715
3716 /* query whether we are supposed to present HPET */
3717 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
3718 if (RT_FAILURE(rc))
3719 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
3720 /* query MCFG configuration */
3721 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
3722 if (RT_FAILURE(rc))
3723 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
3724 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
3725 if (RT_FAILURE(rc))
3726 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
3727 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
3728
3729 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
3730 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
3731 if (RT_FAILURE(rc))
3732 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
3733
3734 /* query the limit of the the 64-bit prefetchable memory window */
3735 uint64_t u64PciPref64MaxGB;
3736 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
3737 if (RT_FAILURE(rc))
3738 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
3739 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
3740
3741 /* query whether we are supposed to present SMC */
3742 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
3743 if (RT_FAILURE(rc))
3744 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
3745
3746 /* query whether we are supposed to present RTC object */
3747 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
3748 if (RT_FAILURE(rc))
3749 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
3750
3751 /* query whether we are supposed to present CPU objects */
3752 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
3753 if (RT_FAILURE(rc))
3754 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
3755
3756 /* query primary NIC PCI address */
3757 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
3758 if (RT_FAILURE(rc))
3759 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
3760
3761 /* query primary NIC PCI address */
3762 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3763 if (RT_FAILURE(rc))
3764 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
3765
3766 /* query IO controller (southbridge) PCI address */
3767 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3768 if (RT_FAILURE(rc))
3769 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
3770
3771 /* query host bus controller PCI address */
3772 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3773 if (RT_FAILURE(rc))
3774 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3775
3776 /* query whether S1 power state should be exposed */
3777 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3778 if (RT_FAILURE(rc))
3779 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3780
3781 /* query whether S4 power state should be exposed */
3782 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3783 if (RT_FAILURE(rc))
3784 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3785
3786 /* query whether S1 power state should save the VM state */
3787 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3788 if (RT_FAILURE(rc))
3789 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3790
3791 /* query whether we are allow CPU hot plugging */
3792 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3793 if (RT_FAILURE(rc))
3794 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
3795
3796 /* query serial info */
3797 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3798 if (RT_FAILURE(rc))
3799 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
3800
3801 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3802 if (RT_FAILURE(rc))
3803 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3804
3805 /* Serial 1 is enabled, get config data */
3806 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3807 if (RT_FAILURE(rc))
3808 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
3809
3810 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3811 if (RT_FAILURE(rc))
3812 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3813
3814 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
3815 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
3816 if (RT_FAILURE(rc))
3817 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
3818
3819 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
3820 if (RT_FAILURE(rc))
3821 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
3822
3823 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
3824 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
3825 if (RT_FAILURE(rc))
3826 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
3827
3828 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
3829 if (RT_FAILURE(rc))
3830 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
3831 /*
3832 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
3833 * the corresponding parallel port is not enabled.
3834 */
3835 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
3836 if (RT_FAILURE(rc))
3837 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
3838
3839 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
3840 if (RT_FAILURE(rc))
3841 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
3842
3843 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
3844 if (RT_FAILURE(rc))
3845 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
3846
3847 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
3848 if (RT_FAILURE(rc))
3849 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
3850
3851 /* Try to attach the other CPUs */
3852 for (unsigned i = 1; i < pThis->cCpus; i++)
3853 {
3854 if (pThis->fCpuHotPlug)
3855 {
3856 PPDMIBASE IBaseTmp;
3857 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3858
3859 if (RT_SUCCESS(rc))
3860 {
3861 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3862 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3863 Log(("acpi: Attached CPU %u\n", i));
3864 }
3865 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3866 Log(("acpi: CPU %u not attached yet\n", i));
3867 else
3868 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3869 }
3870 else
3871 {
3872 /* CPU is always attached if hot-plug is not enabled. */
3873 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3874 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3875 }
3876 }
3877
3878 char szOemId[16];
3879 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
3880 if (RT_FAILURE(rc))
3881 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3882 size_t cchOemId = strlen(szOemId);
3883 if (cchOemId > 6)
3884 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3885 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3886 memcpy(pThis->au8OemId, szOemId, cchOemId);
3887
3888 char szCreatorId[16];
3889 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
3890 if (RT_FAILURE(rc))
3891 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3892 size_t cchCreatorId = strlen(szCreatorId);
3893 if (cchCreatorId > 4)
3894 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3895 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3896 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
3897
3898 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3899 if (RT_FAILURE(rc))
3900 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3901
3902 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3903
3904 /*
3905 * Load custom ACPI tables.
3906 */
3907 /* Total space available for custom ACPI tables */
3908 /** @todo define as appropriate, remove as a magic number, and document
3909 * limitation in product manual */
3910 uint32_t cbBufAvail = 3072;
3911 pThis->cCustTbls = 0;
3912
3913 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
3914 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThis->apu8CustBin));
3915 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
3916 {
3917 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
3918
3919 /*
3920 * Get the custom table binary file name.
3921 */
3922 char *pszCustBinFile = NULL;
3923 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
3924 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
3925 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
3926 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3927 {
3928 rc = VINF_SUCCESS;
3929 pszCustBinFile = NULL;
3930 }
3931 else if (RT_FAILURE(rc))
3932 return PDMDEV_SET_ERROR(pDevIns, rc,
3933 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
3934 else if (!*pszCustBinFile)
3935 {
3936 MMR3HeapFree(pszCustBinFile);
3937 pszCustBinFile = NULL;
3938 }
3939
3940 /*
3941 * Determine the custom table binary size, open specified file in the process.
3942 */
3943 if (pszCustBinFile)
3944 {
3945 uint32_t idxCust = pThis->cCustTbls;
3946 rc = acpiR3ReadCustomTable(pDevIns, &pThis->apu8CustBin[idxCust],
3947 &pThis->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
3948 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
3949 idxCust, pszCustBinFile, pThis->acbCustBin[idxCust]));
3950 MMR3HeapFree(pszCustBinFile);
3951 if (RT_FAILURE(rc))
3952 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
3953 cbBufAvail -= pThis->acbCustBin[idxCust];
3954
3955 /* Update custom OEM attributes based on custom table */
3956 /** @todo is it intended for custom tables to overwrite user provided values above? */
3957 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThis->apu8CustBin[idxCust];
3958 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
3959 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
3960 pThis->u32OemRevision = pTblHdr->u32OemRevision;
3961 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
3962 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
3963
3964 pThis->cCustTbls++;
3965 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
3966 }
3967 }
3968
3969 /* Set default PM port base */
3970 pThis->uPmIoPortBase = PM_PORT_BASE;
3971
3972 /* Set default SMBus port base */
3973 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
3974
3975 /*
3976 * FDC and SMC try to use the same non-shareable interrupt (6),
3977 * enable only one device.
3978 */
3979 if (pThis->fUseSmc)
3980 pThis->fUseFdc = false;
3981
3982 /*
3983 * Plant ACPI tables.
3984 */
3985 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
3986 * au8RSDPPage here. However, there should be no harm in doing it
3987 * twice, so the lazy bird is taking the quick way out for now. */
3988 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
3989 if (!GCPhysRsdp)
3990 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
3991
3992 rc = acpiR3PlantTables(pDevIns, pThis);
3993 AssertRCReturn(rc, rc);
3994
3995 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
3996 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
3997 AssertRCReturn(rc, rc);
3998
3999 /*
4000 * Create the PM I/O ports. These can be unmapped and remapped.
4001 */
4002 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4003 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4004 AssertRCReturn(rc, rc);
4005 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4006 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4007 AssertRCReturn(rc, rc);
4008 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4009 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4010 AssertRCReturn(rc, rc);
4011 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4012 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4013 AssertRCReturn(rc, rc);
4014 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4015 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4016 AssertRCReturn(rc, rc);
4017 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4018 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4019 AssertRCReturn(rc, rc);
4020 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4021 AssertRCReturn(rc, rc);
4022
4023 /*
4024 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4025 */
4026 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4027 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4028 AssertRCReturn(rc, rc);
4029 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4030 AssertRCReturn(rc, rc);
4031
4032 /*
4033 * Create and map the fixed I/O ports.
4034 */
4035 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4036 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4037 AssertRCReturn(rc, rc);
4038#ifdef DEBUG_ACPI
4039 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4040 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4041 AssertRCReturn(rc, rc);
4042 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4043 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4044 AssertRCReturn(rc, rc);
4045#endif
4046 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4047 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4048 AssertRCReturn(rc, rc);
4049 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4050 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4051 AssertRCReturn(rc, rc);
4052 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4053 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4054 AssertRCReturn(rc, rc);
4055 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4056 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4057 AssertRCReturn(rc, rc);
4058 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4059 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4060 AssertRCReturn(rc, rc);
4061
4062 /*
4063 * Create the PM timer.
4064 */
4065 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4066 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer);
4067 AssertRCReturn(rc, rc);
4068
4069 rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4070 AssertRCReturn(rc, rc);
4071 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4072 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4073 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
4074
4075 /*
4076 * Set up the PCI device.
4077 */
4078 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4079 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4080
4081 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4082 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4083
4084 /* See p. 50 of PIIX4 manual */
4085 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4086 PDMPciDevSetStatus(pPciDev, 0x0280);
4087
4088 PDMPciDevSetRevisionId(pPciDev, 0x08);
4089
4090 PDMPciDevSetClassProg(pPciDev, 0x00);
4091 PDMPciDevSetClassSub(pPciDev, 0x80);
4092 PDMPciDevSetClassBase(pPciDev, 0x06);
4093
4094 PDMPciDevSetHeaderType(pPciDev, 0x80);
4095
4096 PDMPciDevSetBIST(pPciDev, 0x00);
4097
4098 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4099 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4100
4101 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4102 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4103
4104 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4105 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4106 acpiR3SMBusResetDevice(pThis);
4107
4108 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4109 if (RT_FAILURE(rc))
4110 return rc;
4111
4112 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4113 AssertRCReturn(rc, rc);
4114
4115 /*
4116 * Register the saved state.
4117 */
4118 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4119 if (RT_FAILURE(rc))
4120 return rc;
4121
4122 /*
4123 * Get the corresponding connector interface
4124 */
4125 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "ACPI Driver Port");
4126 if (RT_SUCCESS(rc))
4127 {
4128 pThis->pDrv = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIACPICONNECTOR);
4129 if (!pThis->pDrv)
4130 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
4131 N_("LUN #0 doesn't have an ACPI connector interface"));
4132 }
4133 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4134 {
4135 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
4136 pDevIns->pReg->szName, pDevIns->iInstance));
4137 rc = VINF_SUCCESS;
4138 }
4139 else
4140 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4141
4142 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4143
4144 return rc;
4145}
4146
4147#else /* !IN_RING3 */
4148
4149/**
4150 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4151 */
4152static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4153{
4154 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4155 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4156
4157 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4158 AssertRCReturn(rc, rc);
4159
4160 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4161 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4162 AssertRCReturn(rc, rc);
4163
4164 return VINF_SUCCESS;
4165}
4166
4167#endif /* !IN_RING3 */
4168
4169/**
4170 * The device registration structure.
4171 */
4172const PDMDEVREG g_DeviceACPI =
4173{
4174 /* .u32Version = */ PDM_DEVREG_VERSION,
4175 /* .uReserved0 = */ 0,
4176 /* .szName = */ "acpi",
4177 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4178 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4179 /* .cMaxInstances = */ ~0U,
4180 /* .uSharedVersion = */ 42,
4181 /* .cbInstanceShared = */ sizeof(ACPIState),
4182 /* .cbInstanceCC = */ 0,
4183 /* .cbInstanceRC = */ 0,
4184 /* .cMaxPciDevices = */ 1,
4185 /* .cMaxMsixVectors = */ 0,
4186 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4187#if defined(IN_RING3)
4188 /* .pszRCMod = */ "VBoxDDRC.rc",
4189 /* .pszR0Mod = */ "VBoxDDR0.r0",
4190 /* .pfnConstruct = */ acpiR3Construct,
4191 /* .pfnDestruct = */ acpiR3Destruct,
4192 /* .pfnRelocate = */ NULL,
4193 /* .pfnMemSetup = */ acpiR3MemSetup,
4194 /* .pfnPowerOn = */ NULL,
4195 /* .pfnReset = */ acpiR3Reset,
4196 /* .pfnSuspend = */ NULL,
4197 /* .pfnResume = */ acpiR3Resume,
4198 /* .pfnAttach = */ acpiR3Attach,
4199 /* .pfnDetach = */ acpiR3Detach,
4200 /* .pfnQueryInterface = */ NULL,
4201 /* .pfnInitComplete = */ NULL,
4202 /* .pfnPowerOff = */ NULL,
4203 /* .pfnSoftReset = */ NULL,
4204 /* .pfnReserved0 = */ NULL,
4205 /* .pfnReserved1 = */ NULL,
4206 /* .pfnReserved2 = */ NULL,
4207 /* .pfnReserved3 = */ NULL,
4208 /* .pfnReserved4 = */ NULL,
4209 /* .pfnReserved5 = */ NULL,
4210 /* .pfnReserved6 = */ NULL,
4211 /* .pfnReserved7 = */ NULL,
4212#elif defined(IN_RING0)
4213 /* .pfnEarlyConstruct = */ NULL,
4214 /* .pfnConstruct = */ acpiRZConstruct,
4215 /* .pfnDestruct = */ NULL,
4216 /* .pfnFinalDestruct = */ NULL,
4217 /* .pfnRequest = */ NULL,
4218 /* .pfnReserved0 = */ NULL,
4219 /* .pfnReserved1 = */ NULL,
4220 /* .pfnReserved2 = */ NULL,
4221 /* .pfnReserved3 = */ NULL,
4222 /* .pfnReserved4 = */ NULL,
4223 /* .pfnReserved5 = */ NULL,
4224 /* .pfnReserved6 = */ NULL,
4225 /* .pfnReserved7 = */ NULL,
4226#elif defined(IN_RC)
4227 /* .pfnConstruct = */ acpiRZConstruct,
4228 /* .pfnReserved0 = */ NULL,
4229 /* .pfnReserved1 = */ NULL,
4230 /* .pfnReserved2 = */ NULL,
4231 /* .pfnReserved3 = */ NULL,
4232 /* .pfnReserved4 = */ NULL,
4233 /* .pfnReserved5 = */ NULL,
4234 /* .pfnReserved6 = */ NULL,
4235 /* .pfnReserved7 = */ NULL,
4236#else
4237# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4238#endif
4239 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4240};
4241
4242#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette