VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 82064

Last change on this file since 82064 was 82020, checked in by vboxsync, 5 years ago

DevACPI: Split the state structure. bugref:9218
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1/* $Id: DevACPI.cpp 82020 2019-11-20 11:36:21Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#include <iprt/file.h>
33#ifdef IN_RING3
34# include <iprt/alloc.h>
35# include <iprt/string.h>
36# include <iprt/uuid.h>
37#endif /* IN_RING3 */
38
39#include "VBoxDD.h"
40
41#ifdef LOG_ENABLED
42# define DEBUG_ACPI
43#endif
44
45
46/*********************************************************************************************************************************
47* Defined Constants And Macros *
48*********************************************************************************************************************************/
49#ifdef IN_RING3
50/** Locks the device state, ring-3 only. */
51# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
52 do { \
53 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
54 AssertRC(rcLock); \
55 } while (0)
56#endif
57/** Unlocks the device state (all contexts). */
58#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
59 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
60
61
62#define DEBUG_HEX 0x3000
63#define DEBUG_CHR 0x3001
64
65/** PM Base Address PCI config space offset */
66#define PMBA 0x40
67/** PM Miscellaneous Power Management PCI config space offset */
68#define PMREGMISC 0x80
69
70#define PM_TMR_FREQ 3579545
71/** Default base for PM PIIX4 device */
72#define PM_PORT_BASE 0x4000
73/* Port offsets in PM device */
74enum
75{
76 PM1a_EVT_OFFSET = 0x00,
77 PM1b_EVT_OFFSET = -1, /**< not supported */
78 PM1a_CTL_OFFSET = 0x04,
79 PM1b_CTL_OFFSET = -1, /**< not supported */
80 PM2_CTL_OFFSET = -1, /**< not supported */
81 PM_TMR_OFFSET = 0x08,
82 GPE0_OFFSET = 0x20,
83 GPE1_OFFSET = -1 /**< not supported */
84};
85
86/* Maximum supported number of custom ACPI tables */
87#define MAX_CUST_TABLES 4
88
89/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
90#define PM_TMR_32BIT
91
92#define BAT_INDEX 0x00004040
93#define BAT_DATA 0x00004044
94#define SYSI_INDEX 0x00004048
95#define SYSI_DATA 0x0000404c
96#define ACPI_RESET_BLK 0x00004050
97
98/* PM1x status register bits */
99#define TMR_STS RT_BIT(0)
100#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
101#define BM_STS RT_BIT(4)
102#define GBL_STS RT_BIT(5)
103#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
104#define PWRBTN_STS RT_BIT(8)
105#define SLPBTN_STS RT_BIT(9)
106#define RTC_STS RT_BIT(10)
107#define IGN_STS RT_BIT(11)
108#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
109#define WAK_STS RT_BIT(15)
110#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
111
112/* PM1x enable register bits */
113#define TMR_EN RT_BIT(0)
114#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
115#define GBL_EN RT_BIT(5)
116#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
117#define PWRBTN_EN RT_BIT(8)
118#define SLPBTN_EN RT_BIT(9)
119#define RTC_EN RT_BIT(10)
120#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
121#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
122#define IGN_EN 0
123
124/* PM1x control register bits */
125#define SCI_EN RT_BIT(0)
126#define BM_RLD RT_BIT(1)
127#define GBL_RLS RT_BIT(2)
128#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
129#define IGN_CNT RT_BIT(9)
130#define SLP_TYPx_SHIFT 10
131#define SLP_TYPx_MASK 7
132#define SLP_EN RT_BIT(13)
133#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
134#define RSR_CNT (RSR1_CNT | RSR2_CNT)
135
136#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
137
138enum
139{
140 BAT_STATUS_STATE = 0x00, /**< BST battery state */
141 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
142 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
143 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
144 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
145 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
146 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
147 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
148 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
149 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
150 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
151 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
152 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
153 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
154 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
155 BAT_INDEX_LAST
156};
157
158enum
159{
160 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
161 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
162};
163
164enum
165{
166 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
167 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
168 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
169 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
170 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
171 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
172 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
173 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
174 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
175 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
176 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
177 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
178 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
179 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
180 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
181 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
182 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
183 SYSTEM_INFO_INDEX_POWER_STATES = 17,
184 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
185 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
186 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
187 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
188 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
189 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
190 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
191 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
192 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
193 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
194 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
195 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
196 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
197 SYSTEM_INFO_INDEX_END = 31,
198 SYSTEM_INFO_INDEX_INVALID = 0x80,
199 SYSTEM_INFO_INDEX_VALID = 0x200
200};
201
202#define AC_OFFLINE 0
203#define AC_ONLINE 1
204
205#define BAT_TECH_PRIMARY 1
206#define BAT_TECH_SECONDARY 2
207
208#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
209#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
210#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
211#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
212#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
213
214/** SMBus Base Address PCI config space offset */
215#define SMBBA 0x90
216/** SMBus Host Configuration PCI config space offset */
217#define SMBHSTCFG 0xd2
218/** SMBus Slave Command PCI config space offset */
219#define SMBSLVC 0xd3
220/** SMBus Slave Shadow Port 1 PCI config space offset */
221#define SMBSHDW1 0xd4
222/** SMBus Slave Shadow Port 2 PCI config space offset */
223#define SMBSHDW2 0xd5
224/** SMBus Revision Identification PCI config space offset */
225#define SMBREV 0xd6
226
227#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
228#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
229#define SMBHSTCFG_INTRSEL_SMI 0
230#define SMBHSTCFG_INTRSEL_IRQ9 4
231#define SMBHSTCFG_INTRSEL_SHIFT 1
232
233/** Default base for SMBus PIIX4 device */
234#define SMB_PORT_BASE 0x4100
235
236/** SMBus Host Status Register I/O offset */
237#define SMBHSTSTS_OFF 0x0000
238/** SMBus Slave Status Register I/O offset */
239#define SMBSLVSTS_OFF 0x0001
240/** SMBus Host Count Register I/O offset */
241#define SMBHSTCNT_OFF 0x0002
242/** SMBus Host Command Register I/O offset */
243#define SMBHSTCMD_OFF 0x0003
244/** SMBus Host Address Register I/O offset */
245#define SMBHSTADD_OFF 0x0004
246/** SMBus Host Data 0 Register I/O offset */
247#define SMBHSTDAT0_OFF 0x0005
248/** SMBus Host Data 1 Register I/O offset */
249#define SMBHSTDAT1_OFF 0x0006
250/** SMBus Block Data Register I/O offset */
251#define SMBBLKDAT_OFF 0x0007
252/** SMBus Slave Control Register I/O offset */
253#define SMBSLVCNT_OFF 0x0008
254/** SMBus Shadow Command Register I/O offset */
255#define SMBSHDWCMD_OFF 0x0009
256/** SMBus Slave Event Register I/O offset */
257#define SMBSLVEVT_OFF 0x000a
258/** SMBus Slave Data Register I/O offset */
259#define SMBSLVDAT_OFF 0x000c
260
261#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
262#define SMBHSTSTS_INTER RT_BIT(1)
263#define SMBHSTSTS_DEV_ERR RT_BIT(2)
264#define SMBHSTSTS_BUS_ERR RT_BIT(3)
265#define SMBHSTSTS_FAILED RT_BIT(4)
266#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
267
268#define SMBSLVSTS_WRITE_MASK 0x3c
269
270#define SMBHSTCNT_INTEREN RT_BIT(0)
271#define SMBHSTCNT_KILL RT_BIT(1)
272#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
273#define SMBHSTCNT_START RT_BIT(6)
274#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
275
276#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
277
278
279/*********************************************************************************************************************************
280* Structures and Typedefs *
281*********************************************************************************************************************************/
282/**
283 * The shared ACPI device state.
284 */
285typedef struct ACPISTATE
286{
287 /** Critical section protecting the ACPI state. */
288 PDMCRITSECT CritSect;
289
290 uint16_t pm1a_en;
291 uint16_t pm1a_sts;
292 uint16_t pm1a_ctl;
293 /** Number of logical CPUs in guest */
294 uint16_t cCpus;
295
296 uint64_t u64PmTimerInitial;
297 /** The PM timer. */
298 TMTIMERHANDLE hPmTimer;
299 /* PM Timer last calculated value */
300 uint32_t uPmTimerVal;
301 uint32_t Alignment0;
302
303 uint32_t gpe0_en;
304 uint32_t gpe0_sts;
305
306 uint32_t uBatteryIndex;
307 uint32_t au8BatteryInfo[13];
308
309 uint32_t uSystemInfoIndex;
310 uint32_t u32Alignment0;
311 uint64_t u64RamSize;
312 /** Offset of the 64-bit prefetchable memory window. */
313 uint64_t u64PciPref64Min;
314 /** Limit of the 64-bit prefetchable memory window. */
315 uint64_t u64PciPref64Max;
316 /** The number of bytes below 4GB. */
317 uint32_t cbRamLow;
318
319 /** Current ACPI S* state. We support S0 and S5. */
320 uint32_t uSleepState;
321 uint8_t au8RSDPPage[0x1000];
322 /** This is a workaround for incorrect index field handling by Intels ACPICA.
323 * The system info _INI method writes to offset 0x200. We either observe a
324 * write request to index 0x80 (in that case we don't change the index) or a
325 * write request to offset 0x200 (in that case we divide the index value by
326 * 4. Note that the _STA method is sometimes called prior to the _INI method
327 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
328 * acpiR3BatIndexWrite() for handling this. */
329 uint8_t u8IndexShift;
330 /** provide an I/O-APIC */
331 uint8_t u8UseIOApic;
332 /** provide a floppy controller */
333 bool fUseFdc;
334 /** If High Precision Event Timer device should be supported */
335 bool fUseHpet;
336 /** If System Management Controller device should be supported */
337 bool fUseSmc;
338 /** the guest handled the last power button event */
339 bool fPowerButtonHandled;
340 /** If ACPI CPU device should be shown */
341 bool fShowCpu;
342 /** If Real Time Clock ACPI object to be shown */
343 bool fShowRtc;
344 /** I/O port address of PM device. */
345 RTIOPORT uPmIoPortBase;
346 /** I/O port address of SMBus device. */
347 RTIOPORT uSMBusIoPortBase;
348 /** Which CPU to check for the locked status. */
349 uint32_t idCpuLockCheck;
350 /** Array of flags of attached CPUs */
351 VMCPUSET CpuSetAttached;
352 /** Mask of locked CPUs (used by the guest). */
353 VMCPUSET CpuSetLocked;
354 /** The CPU event type. */
355 uint32_t u32CpuEventType;
356 /** The CPU id affected. */
357 uint32_t u32CpuEvent;
358 /** Flag whether CPU hot plugging is enabled. */
359 bool fCpuHotPlug;
360 /** If MCFG ACPI table shown to the guest */
361 bool fUseMcfg;
362 /** if the 64-bit prefetchable memory window is shown to the guest */
363 bool fPciPref64Enabled;
364 bool afAlignment1;
365 /** Primary NIC PCI address. */
366 uint32_t u32NicPciAddress;
367 /** Primary audio card PCI address. */
368 uint32_t u32AudioPciAddress;
369 /** Flag whether S1 power state is enabled. */
370 bool fS1Enabled;
371 /** Flag whether S4 power state is enabled. */
372 bool fS4Enabled;
373 /** Flag whether S1 triggers a state save. */
374 bool fSuspendToSavedState;
375 /** Flag whether to set WAK_STS on resume (restore included). */
376 bool fSetWakeupOnResume;
377 /** PCI address of the IO controller device. */
378 uint32_t u32IocPciAddress;
379 /** PCI address of the host bus controller device. */
380 uint32_t u32HbcPciAddress;
381
382 /** Physical address of PCI config space MMIO region */
383 uint64_t u64PciConfigMMioAddress;
384 /** Length of PCI config space MMIO region */
385 uint64_t u64PciConfigMMioLength;
386 /** Serial 0 IRQ number */
387 uint8_t uSerial0Irq;
388 /** Serial 1 IRQ number */
389 uint8_t uSerial1Irq;
390 /** Serial 2 IRQ number */
391 uint8_t uSerial2Irq;
392 /** Serial 3 IRQ number */
393 uint8_t uSerial3Irq;
394 /** Serial 0 IO port base */
395 RTIOPORT uSerial0IoPortBase;
396 /** Serial 1 IO port base */
397 RTIOPORT uSerial1IoPortBase;
398 /** Serial 2 IO port base */
399 RTIOPORT uSerial2IoPortBase;
400 /** Serial 3 IO port base */
401 RTIOPORT uSerial3IoPortBase;
402
403 /** @name Parallel port config bits
404 * @{ */
405 /** Parallel 0 IO port base */
406 RTIOPORT uParallel0IoPortBase;
407 /** Parallel 1 IO port base */
408 RTIOPORT uParallel1IoPortBase;
409 /** Parallel 0 IRQ number */
410 uint8_t uParallel0Irq;
411 /** Parallel 1 IRQ number */
412 uint8_t uParallel1Irq;
413 /** @} */
414
415 /** Number of custom ACPI tables */
416 uint8_t cCustTbls;
417 /** ACPI OEM ID */
418 uint8_t au8OemId[6];
419 /** ACPI Crator ID */
420 uint8_t au8CreatorId[4];
421 uint8_t abAlignment2[3];
422 /** ACPI Crator Rev */
423 uint32_t u32CreatorRev;
424 /** ACPI custom OEM Tab ID */
425 uint8_t au8OemTabId[8];
426 /** ACPI custom OEM Rev */
427 uint32_t u32OemRevision;
428
429 /** SMBus Host Status Register */
430 uint8_t u8SMBusHstSts;
431 /** SMBus Slave Status Register */
432 uint8_t u8SMBusSlvSts;
433 /** SMBus Host Control Register */
434 uint8_t u8SMBusHstCnt;
435 /** SMBus Host Command Register */
436 uint8_t u8SMBusHstCmd;
437 /** SMBus Host Address Register */
438 uint8_t u8SMBusHstAdd;
439 /** SMBus Host Data 0 Register */
440 uint8_t u8SMBusHstDat0;
441 /** SMBus Host Data 1 Register */
442 uint8_t u8SMBusHstDat1;
443 /** SMBus Slave Control Register */
444 uint8_t u8SMBusSlvCnt;
445 /** SMBus Slave Event Register */
446 uint16_t u16SMBusSlvEvt;
447 /** SMBus Slave Data Register */
448 uint16_t u16SMBusSlvDat;
449 /** SMBus Shadow Command Register */
450 uint8_t u8SMBusShdwCmd;
451 /** SMBus Host Block Index */
452 uint8_t u8SMBusBlkIdx;
453 uint8_t abAlignment3[2];
454 /** SMBus Host Block Data Buffer */
455 uint8_t au8SMBusBlkDat[32];
456
457 /** @todo DEBUGGING */
458 uint32_t uPmTimeOld;
459 uint32_t uPmTimeA;
460 uint32_t uPmTimeB;
461 uint32_t Alignment5;
462
463 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
464 * @{ */
465 IOMIOPORTHANDLE hIoPortPm1aEn;
466 IOMIOPORTHANDLE hIoPortPm1aSts;
467 IOMIOPORTHANDLE hIoPortPm1aCtl;
468 IOMIOPORTHANDLE hIoPortPmTimer;
469 IOMIOPORTHANDLE hIoPortGpe0En;
470 IOMIOPORTHANDLE hIoPortGpe0Sts;
471 /** @} */
472
473 /** SMBus I/O ports (mapped/unmapped). */
474 IOMIOPORTHANDLE hIoPortSMBus;
475
476 /** @name Fixed I/O ports
477 * @{ */
478 /** ACPI SMI I/O port. */
479 IOMIOPORTHANDLE hIoPortSmi;
480 /** ACPI Debug hex I/O port. */
481 IOMIOPORTHANDLE hIoPortDebugHex;
482 /** ACPI Debug char I/O port. */
483 IOMIOPORTHANDLE hIoPortDebugChar;
484 /** ACPI Battery status index I/O port. */
485 IOMIOPORTHANDLE hIoPortBatteryIndex;
486 /** ACPI Battery status data I/O port. */
487 IOMIOPORTHANDLE hIoPortBatteryData;
488 /** ACPI system info index I/O port. */
489 IOMIOPORTHANDLE hIoPortSysInfoIndex;
490 /** ACPI system info data I/O port. */
491 IOMIOPORTHANDLE hIoPortSysInfoData;
492 /** ACPI Reset I/O port. */
493 IOMIOPORTHANDLE hIoPortReset;
494 /** @} */
495
496} ACPISTATE;
497/** Pointer to the shared ACPI device state. */
498typedef ACPISTATE *PACPISTATE;
499
500
501/**
502 * The ring-3 ACPI device state.
503 */
504typedef struct ACPISTATER3
505{
506 /** ACPI port base interface. */
507 PDMIBASE IBase;
508 /** ACPI port interface. */
509 PDMIACPIPORT IACPIPort;
510 /** Pointer to the device instance so we can get our bearings from
511 * interface functions. */
512 PPDMDEVINSR3 pDevIns;
513
514 /** Pointer to the driver base interface. */
515 R3PTRTYPE(PPDMIBASE) pDrvBase;
516 /** Pointer to the driver connector interface. */
517 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
518
519 /** Custom ACPI tables binary data. */
520 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
521 /** The size of the custom table binary. */
522 uint64_t acbCustBin[MAX_CUST_TABLES];
523} ACPISTATER3;
524/** Pointer to the ring-3 ACPI device state. */
525typedef ACPISTATER3 *PACPISTATER3;
526
527
528#pragma pack(1)
529
530/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
531struct ACPIGENADDR
532{
533 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
534 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
535 uint8_t u8RegisterBitOffset; /**< bit offset of register */
536 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
537 uint64_t u64Address; /**< 64-bit address of register */
538};
539AssertCompileSize(ACPIGENADDR, 12);
540
541/** Root System Description Pointer */
542struct ACPITBLRSDP
543{
544 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
545 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
546 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
547 uint8_t u8Revision; /**< revision number, currently 2 */
548#define ACPI_REVISION 2 /**< ACPI 3.0 */
549 uint32_t u32RSDT; /**< phys addr of RSDT */
550 uint32_t u32Length; /**< bytes of this table */
551 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
552 uint8_t u8ExtChecksum; /**< checksum of entire table */
553 uint8_t u8Reserved[3]; /**< reserved */
554};
555AssertCompileSize(ACPITBLRSDP, 36);
556
557/** System Description Table Header */
558struct ACPITBLHEADER
559{
560 uint8_t au8Signature[4]; /**< table identifier */
561 uint32_t u32Length; /**< length of the table including header */
562 uint8_t u8Revision; /**< revision number */
563 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
564 uint8_t au8OemId[6]; /**< OEM-supplied string */
565 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
566 uint32_t u32OemRevision; /**< OEM-supplied revision number */
567 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
568 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
569};
570AssertCompileSize(ACPITBLHEADER, 36);
571
572/** Root System Description Table */
573struct ACPITBLRSDT
574{
575 ACPITBLHEADER header;
576 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
577};
578AssertCompileSize(ACPITBLRSDT, 40);
579
580/** Extended System Description Table */
581struct ACPITBLXSDT
582{
583 ACPITBLHEADER header;
584 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
585};
586AssertCompileSize(ACPITBLXSDT, 44);
587
588/** Fixed ACPI Description Table */
589struct ACPITBLFADT
590{
591 ACPITBLHEADER header;
592 uint32_t u32FACS; /**< phys. address of FACS */
593 uint32_t u32DSDT; /**< phys. address of DSDT */
594 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
595#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
596#define INT_MODEL_MULTIPLE_APIC 2
597 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
598 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
599#define SCI_INT 9
600 uint32_t u32SMICmd; /**< system port address of SMI command port */
601#define SMI_CMD 0x0000442e
602 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
603#define ACPI_ENABLE 0xa1
604 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
605#define ACPI_DISABLE 0xa0
606 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
607 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
608 state control responsibility */
609 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
610 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
611 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
612 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
613 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
614 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
615 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
616 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
617 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
618 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
619 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
620 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
621 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
622#define GPE0_BLK_LEN 2
623 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
624#define GPE1_BLK_LEN 0
625 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
626#define GPE1_BASE 0
627 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
628 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
629#define P_LVL2_LAT 101 /**< C2 state not supported */
630 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
631#define P_LVL3_LAT 1001 /**< C3 state not supported */
632 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
633 lines from any processors memory caches */
634#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
635 uint16_t u16FlushStride; /**< cache line width */
636#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
637 uint8_t u8DutyOffset;
638 uint8_t u8DutyWidth;
639 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
640 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
641 uint8_t u8Century; /**< RTC CMOS RAM index of century */
642 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
643#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
644 (COM too?) */
645#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
646#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
647#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
648#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
649 uint8_t u8Must0_0; /**< must be 0 */
650 uint32_t u32Flags; /**< fixed feature flags */
651#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
652#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
653#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
654#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
655#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
656#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
657#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
658#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
659#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
660#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
661#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
662#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
663#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
664#define FADT_FL_CPU_SW_SLP RT_BIT(13)
665#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
666#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
667#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
668#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
669#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
670#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
671
672/* PM Timer mask and msb */
673#ifndef PM_TMR_32BIT
674#define TMR_VAL_MSB 0x800000
675#define TMR_VAL_MASK 0xffffff
676#undef FADT_FL_TMR_VAL_EXT
677#define FADT_FL_TMR_VAL_EXT 0
678#else
679#define TMR_VAL_MSB 0x80000000
680#define TMR_VAL_MASK 0xffffffff
681#endif
682
683 /** Start of the ACPI 2.0 extension. */
684 ACPIGENADDR ResetReg; /**< ext addr of reset register */
685 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
686#define ACPI_RESET_REG_VAL 0x10
687 uint8_t au8Must0_1[3]; /**< must be 0 */
688 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
689 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
690 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
691 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
692 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
693 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
694 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
695 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
696 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
697 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
698};
699AssertCompileSize(ACPITBLFADT, 244);
700#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
701
702/** Firmware ACPI Control Structure */
703struct ACPITBLFACS
704{
705 uint8_t au8Signature[4]; /**< 'FACS' */
706 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
707 uint32_t u32HWSignature; /**< systems HW signature at last boot */
708 uint32_t u32FWVector; /**< address of waking vector */
709 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
710 uint32_t u32Flags; /**< FACS flags */
711 uint64_t u64X_FWVector; /**< 64-bit waking vector */
712 uint8_t u8Version; /**< version of this table */
713 uint8_t au8Reserved[31]; /**< zero */
714};
715AssertCompileSize(ACPITBLFACS, 64);
716
717/** Processor Local APIC Structure */
718struct ACPITBLLAPIC
719{
720 uint8_t u8Type; /**< 0 = LAPIC */
721 uint8_t u8Length; /**< 8 */
722 uint8_t u8ProcId; /**< processor ID */
723 uint8_t u8ApicId; /**< local APIC ID */
724 uint32_t u32Flags; /**< Flags */
725#define LAPIC_ENABLED 0x1
726};
727AssertCompileSize(ACPITBLLAPIC, 8);
728
729/** I/O APIC Structure */
730struct ACPITBLIOAPIC
731{
732 uint8_t u8Type; /**< 1 == I/O APIC */
733 uint8_t u8Length; /**< 12 */
734 uint8_t u8IOApicId; /**< I/O APIC ID */
735 uint8_t u8Reserved; /**< 0 */
736 uint32_t u32Address; /**< phys address to access I/O APIC */
737 uint32_t u32GSIB; /**< global system interrupt number to start */
738};
739AssertCompileSize(ACPITBLIOAPIC, 12);
740
741/** Interrupt Source Override Structure */
742struct ACPITBLISO
743{
744 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
745 uint8_t u8Length; /**< 10 */
746 uint8_t u8Bus; /**< Bus */
747 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
748 uint32_t u32GSI; /**< Global System Interrupt */
749 uint16_t u16Flags; /**< MPS INTI flags Global */
750};
751AssertCompileSize(ACPITBLISO, 10);
752#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
753
754/** HPET Descriptor Structure */
755struct ACPITBLHPET
756{
757 ACPITBLHEADER aHeader;
758 uint32_t u32Id; /**< hardware ID of event timer block
759 [31:16] PCI vendor ID of first timer block
760 [15] legacy replacement IRQ routing capable
761 [14] reserved
762 [13] COUNT_SIZE_CAP counter size
763 [12:8] number of comparators in first timer block
764 [7:0] hardware rev ID */
765 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
766 uint8_t u32Number; /**< sequence number starting at 0 */
767 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
768 lost interrupts while the counter is programmed
769 to operate in periodic mode. Unit: clock tick. */
770 uint8_t u8Attributes; /**< page protection and OEM attribute. */
771};
772AssertCompileSize(ACPITBLHPET, 56);
773
774/** MCFG Descriptor Structure */
775typedef struct ACPITBLMCFG
776{
777 ACPITBLHEADER aHeader;
778 uint64_t u64Reserved;
779} ACPITBLMCFG;
780AssertCompileSize(ACPITBLMCFG, 44);
781
782/** Number of such entries can be computed from the whole table length in header */
783typedef struct ACPITBLMCFGENTRY
784{
785 uint64_t u64BaseAddress;
786 uint16_t u16PciSegmentGroup;
787 uint8_t u8StartBus;
788 uint8_t u8EndBus;
789 uint32_t u32Reserved;
790} ACPITBLMCFGENTRY;
791AssertCompileSize(ACPITBLMCFGENTRY, 16);
792
793#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
794
795/** Custom Description Table */
796struct ACPITBLCUST
797{
798 ACPITBLHEADER header;
799 uint8_t au8Data[476];
800};
801AssertCompileSize(ACPITBLCUST, 512);
802
803
804#pragma pack()
805
806
807#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
808
809
810/*********************************************************************************************************************************
811* Internal Functions *
812*********************************************************************************************************************************/
813#ifdef IN_RING3
814static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
815#endif
816
817/* SCI, usually IRQ9 */
818DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
819{
820 PDMDevHlpPCISetIrq(pDevIns, 0, level);
821}
822
823DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
824{
825 return (pThis->pm1a_ctl & SCI_EN)
826 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
827}
828
829DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
830{
831 return !!(pThis->gpe0_en & pThis->gpe0_sts);
832}
833
834DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
835{
836 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
837 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
838 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
839 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
840 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
841}
842
843DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
844{
845 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
846}
847
848/**
849 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
850 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
851 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
852 * registers and trigger IRQs.
853 *
854 * Caller must hold the state lock.
855 *
856 * @param pDevIns The PDM device instance.
857 * @param pThis The ACPI shared instance data.
858 * @param sts The new PM1a.STS value.
859 * @param en The new PM1a.EN value.
860 */
861static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
862{
863 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
864
865 const bool old_level = acpiSCILevel(pDevIns, pThis);
866 pThis->pm1a_en = en;
867 pThis->pm1a_sts = sts;
868 const bool new_level = acpiSCILevel(pDevIns, pThis);
869
870 LogFunc(("old=%x new=%x\n", old_level, new_level));
871
872 if (new_level != old_level)
873 acpiSetIrq(pDevIns, new_level);
874}
875
876#ifdef IN_RING3
877
878/**
879 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
880 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
881 *
882 * Caller must hold the state lock.
883 *
884 * @param pDevIns The PDM device instance.
885 * @param pThis The ACPI shared instance data.
886 * @param sts The new GPE0.STS value.
887 * @param en The new GPE0.EN value.
888 */
889static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
890{
891 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
892
893 const bool old_level = acpiSCILevel(pDevIns, pThis);
894 pThis->gpe0_en = en;
895 pThis->gpe0_sts = sts;
896 const bool new_level = acpiSCILevel(pDevIns, pThis);
897
898 LogFunc(("old=%x new=%x\n", old_level, new_level));
899
900 if (new_level != old_level)
901 acpiSetIrq(pDevIns, new_level);
902}
903
904/**
905 * Used by acpiR3PM1aCtlWrite to power off the VM.
906 *
907 * @param pDevIns The device instance.
908 * @returns Strict VBox status code.
909 */
910static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
911{
912 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
913 AssertRC(VBOXSTRICTRC_VAL(rc));
914 return rc;
915}
916
917/**
918 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
919 *
920 * @param pDevIns The device instance.
921 * @param pThis The ACPI shared instance data.
922 * @returns Strict VBox status code.
923 */
924static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
925{
926 /* We must set WAK_STS on resume (includes restore) so the guest knows that
927 we've woken up and can continue executing code. The guest is probably
928 reading the PMSTS register in a loop to check this. */
929 VBOXSTRICTRC rc;
930 pThis->fSetWakeupOnResume = true;
931 if (pThis->fSuspendToSavedState)
932 {
933 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
934 if (rc != VERR_NOT_SUPPORTED)
935 AssertRC(VBOXSTRICTRC_VAL(rc));
936 else
937 {
938 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
939 rc = PDMDevHlpVMSuspend(pDevIns);
940 AssertRC(VBOXSTRICTRC_VAL(rc));
941 }
942 }
943 else
944 {
945 rc = PDMDevHlpVMSuspend(pDevIns);
946 AssertRC(VBOXSTRICTRC_VAL(rc));
947 }
948 return rc;
949}
950
951
952/**
953 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
954 */
955static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
956{
957 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
958 PPDMDEVINS pDevIns = pThisCC->pDevIns;
959 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
960 DEVACPI_LOCK_R3(pDevIns, pThis);
961
962 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
963 pThis->fPowerButtonHandled = false;
964 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
965
966 DEVACPI_UNLOCK(pDevIns, pThis);
967 return VINF_SUCCESS;
968}
969
970/**
971 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
972 */
973static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
974{
975 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
976 PPDMDEVINS pDevIns = pThisCC->pDevIns;
977 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
978 DEVACPI_LOCK_R3(pDevIns, pThis);
979
980 *pfHandled = pThis->fPowerButtonHandled;
981
982 DEVACPI_UNLOCK(pDevIns, pThis);
983 return VINF_SUCCESS;
984}
985
986/**
987 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
988 * Guest entered into G0 (working) or G1 (sleeping)}
989 */
990static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
991{
992 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
993 PPDMDEVINS pDevIns = pThisCC->pDevIns;
994 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
995 DEVACPI_LOCK_R3(pDevIns, pThis);
996
997 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
998
999 DEVACPI_UNLOCK(pDevIns, pThis);
1000 return VINF_SUCCESS;
1001}
1002
1003/**
1004 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1005 */
1006static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1007{
1008 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1009 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1010 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1011 DEVACPI_LOCK_R3(pDevIns, pThis);
1012
1013 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1014
1015 DEVACPI_UNLOCK(pDevIns, pThis);
1016 return VINF_SUCCESS;
1017}
1018
1019/**
1020 * Send an ACPI sleep button event.
1021 *
1022 * @returns VBox status code
1023 * @param pInterface Pointer to the interface structure containing the called function pointer.
1024 */
1025static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1026{
1027 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1028 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1029 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1030 DEVACPI_LOCK_R3(pDevIns, pThis);
1031
1032 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1033
1034 DEVACPI_UNLOCK(pDevIns, pThis);
1035 return VINF_SUCCESS;
1036}
1037
1038/**
1039 * Send an ACPI monitor hot-plug event.
1040 *
1041 * @returns VBox status code
1042 * @param pInterface Pointer to the interface structure containing the
1043 * called function pointer.
1044 */
1045static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1046{
1047 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1048 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1049 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1050 DEVACPI_LOCK_R3(pDevIns, pThis);
1051
1052 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1053
1054 DEVACPI_UNLOCK(pDevIns, pThis);
1055 return VINF_SUCCESS;
1056}
1057
1058/**
1059 * Send an ACPI battery status change event.
1060 *
1061 * @returns VBox status code
1062 * @param pInterface Pointer to the interface structure containing the
1063 * called function pointer.
1064 */
1065static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1066{
1067 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1068 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1069 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1070 DEVACPI_LOCK_R3(pDevIns, pThis);
1071
1072 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1073
1074 DEVACPI_UNLOCK(pDevIns, pThis);
1075 return VINF_SUCCESS;
1076}
1077
1078/**
1079 * Used by acpiR3PmTimer to re-arm the PM timer.
1080 *
1081 * The caller is expected to either hold the clock lock or to have made sure
1082 * the VM is resetting or loading state.
1083 *
1084 * @param pDevIns The device instance.
1085 * @param pThis The ACPI shared instance data.
1086 * @param uNow The current time.
1087 */
1088static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1089{
1090 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1091 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1092 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1093 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1094 Log(("acpi: uInterval = %RU64\n", uInterval));
1095}
1096
1097#endif /* IN_RING3 */
1098
1099/**
1100 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1101 *
1102 * The caller is expected to either hold the clock lock or to have made sure
1103 * the VM is resetting or loading state.
1104 *
1105 * @param pDevIns The PDM device instance.
1106 * @param pThis The ACPI instance
1107 * @param u64Now The current time
1108 */
1109static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1110{
1111 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1112 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1113 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1114
1115 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ,
1116 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1117 & TMR_VAL_MASK;
1118
1119 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1120 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1121}
1122
1123#ifdef IN_RING3
1124
1125/**
1126 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1127 */
1128static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1129{
1130 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1131 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1132 RT_NOREF(pTimer, pvUser);
1133
1134 DEVACPI_LOCK_R3(pDevIns, pThis);
1135 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1136 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1137 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1138 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1139 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1140 DEVACPI_UNLOCK(pDevIns, pThis);
1141
1142 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
1143}
1144
1145/**
1146 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1147 * acpiR3LoadState.
1148 *
1149 * @returns VINF_SUCCESS.
1150 * @param pThis The ACPI shared instance data.
1151 * @param pThisCC The ACPI instance data for ring-3.
1152 */
1153static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1154{
1155 uint32_t *p = pThis->au8BatteryInfo;
1156 bool fPresent; /* battery present? */
1157 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1158 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1159 uint32_t hostPresentRate; /* 0..1000 */
1160 int rc;
1161
1162 if (!pThisCC->pDrv)
1163 return VINF_SUCCESS;
1164 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1165 &hostBatteryState, &hostPresentRate);
1166 AssertRC(rc);
1167
1168 /* default values */
1169 p[BAT_STATUS_STATE] = hostBatteryState;
1170 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1171 : hostPresentRate * 50; /* mW */
1172 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1173 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1174
1175 /* did we get a valid battery state? */
1176 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1177 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1178 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1179 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1180
1181 return VINF_SUCCESS;
1182}
1183
1184/**
1185 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1186 * acpiR3LoadState.
1187 *
1188 * @returns VINF_SUCCESS.
1189 * @param pThis The ACPI shared instance data.
1190 */
1191static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1192{
1193 uint32_t *p = pThis->au8BatteryInfo;
1194
1195 p[BAT_INFO_UNITS] = 0; /* mWh */
1196 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1197 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1198 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1199 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1200 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1201 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1202 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1203 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1204
1205 return VINF_SUCCESS;
1206}
1207
1208/**
1209 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1210 *
1211 * @returns status mask or 0.
1212 * @param pThisCC The ACPI instance data for ring-3.
1213 */
1214static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1215{
1216 bool fPresent; /* battery present? */
1217 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1218 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1219 uint32_t hostPresentRate; /* 0..1000 */
1220 int rc;
1221
1222 if (!pThisCC->pDrv)
1223 return 0;
1224 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1225 &hostBatteryState, &hostPresentRate);
1226 AssertRC(rc);
1227
1228 return fPresent
1229 ? STA_DEVICE_PRESENT_MASK /* present */
1230 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1231 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1232 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1233 | STA_BATTERY_PRESENT_MASK /* battery is present */
1234 : 0; /* device not present */
1235}
1236
1237/**
1238 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1239 *
1240 * @returns status.
1241 * @param pThisCC The ACPI instance data for ring-3.
1242 */
1243static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1244{
1245 /* query the current power source from the host driver */
1246 if (!pThisCC->pDrv)
1247 return AC_ONLINE;
1248
1249 PDMACPIPOWERSOURCE ps;
1250 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1251 AssertRC(rc);
1252 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1253}
1254
1255/**
1256 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1257 */
1258static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1259{
1260 RT_NOREF(pvUser, offPort);
1261 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1262 if (cb != 4)
1263 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1264
1265 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1266 DEVACPI_LOCK_R3(pDevIns, pThis);
1267
1268 u32 >>= pThis->u8IndexShift;
1269 /* see comment at the declaration of u8IndexShift */
1270 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1271 {
1272 pThis->u8IndexShift = 2;
1273 u32 >>= 2;
1274 }
1275 Assert(u32 < BAT_INDEX_LAST);
1276 pThis->uBatteryIndex = u32;
1277
1278 DEVACPI_UNLOCK(pDevIns, pThis);
1279 return VINF_SUCCESS;
1280}
1281
1282/**
1283 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1284 */
1285static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1286{
1287 RT_NOREF(pvUser, offPort);
1288 if (cb != 4)
1289 return VERR_IOM_IOPORT_UNUSED;
1290
1291 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1292 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1293 DEVACPI_LOCK_R3(pDevIns, pThis);
1294
1295 VBOXSTRICTRC rc = VINF_SUCCESS;
1296 switch (pThis->uBatteryIndex)
1297 {
1298 case BAT_STATUS_STATE:
1299 acpiR3FetchBatteryStatus(pThis, pThisCC);
1300 RT_FALL_THRU();
1301 case BAT_STATUS_PRESENT_RATE:
1302 case BAT_STATUS_REMAINING_CAPACITY:
1303 case BAT_STATUS_PRESENT_VOLTAGE:
1304 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1305 break;
1306
1307 case BAT_INFO_UNITS:
1308 acpiR3FetchBatteryInfo(pThis);
1309 RT_FALL_THRU();
1310 case BAT_INFO_DESIGN_CAPACITY:
1311 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1312 case BAT_INFO_TECHNOLOGY:
1313 case BAT_INFO_DESIGN_VOLTAGE:
1314 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1315 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1316 case BAT_INFO_CAPACITY_GRANULARITY_1:
1317 case BAT_INFO_CAPACITY_GRANULARITY_2:
1318 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1319 break;
1320
1321 case BAT_DEVICE_STATUS:
1322 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1323 break;
1324
1325 case BAT_POWER_SOURCE:
1326 *pu32 = acpiR3GetPowerSource(pThisCC);
1327 break;
1328
1329 default:
1330 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1331 *pu32 = UINT32_MAX;
1332 break;
1333 }
1334
1335 DEVACPI_UNLOCK(pDevIns, pThis);
1336 return rc;
1337}
1338
1339/**
1340 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1341 */
1342static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1343{
1344 RT_NOREF(pvUser, offPort);
1345 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1346 if (cb != 4)
1347 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1348
1349 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1350 DEVACPI_LOCK_R3(pDevIns, pThis);
1351
1352 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1353 pThis->uSystemInfoIndex = u32;
1354 else
1355 {
1356 /* see comment at the declaration of u8IndexShift */
1357 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1358 {
1359 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1360 pThis->u8IndexShift = 2;
1361 }
1362
1363 u32 >>= pThis->u8IndexShift;
1364 Assert(u32 < SYSTEM_INFO_INDEX_END);
1365 pThis->uSystemInfoIndex = u32;
1366 }
1367
1368 DEVACPI_UNLOCK(pDevIns, pThis);
1369 return VINF_SUCCESS;
1370}
1371
1372/**
1373 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1374 */
1375static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1376{
1377 RT_NOREF(pvUser, offPort);
1378 if (cb != 4)
1379 return VERR_IOM_IOPORT_UNUSED;
1380
1381 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1382 DEVACPI_LOCK_R3(pDevIns, pThis);
1383
1384 VBOXSTRICTRC rc = VINF_SUCCESS;
1385 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1386 switch (uSystemInfoIndex)
1387 {
1388 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1389 *pu32 = pThis->cbRamLow;
1390 break;
1391
1392 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1393 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1394 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1395 break;
1396
1397 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1398 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1399 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1400 break;
1401
1402 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1403 *pu32 = pThis->u8UseIOApic;
1404 break;
1405
1406 case SYSTEM_INFO_INDEX_HPET_STATUS:
1407 *pu32 = pThis->fUseHpet
1408 ? ( STA_DEVICE_PRESENT_MASK
1409 | STA_DEVICE_ENABLED_MASK
1410 | STA_DEVICE_SHOW_IN_UI_MASK
1411 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1412 : 0;
1413 break;
1414
1415 case SYSTEM_INFO_INDEX_SMC_STATUS:
1416 *pu32 = pThis->fUseSmc
1417 ? ( STA_DEVICE_PRESENT_MASK
1418 | STA_DEVICE_ENABLED_MASK
1419 /* no need to show this device in the UI */
1420 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1421 : 0;
1422 break;
1423
1424 case SYSTEM_INFO_INDEX_FDC_STATUS:
1425 *pu32 = pThis->fUseFdc
1426 ? ( STA_DEVICE_PRESENT_MASK
1427 | STA_DEVICE_ENABLED_MASK
1428 | STA_DEVICE_SHOW_IN_UI_MASK
1429 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1430 : 0;
1431 break;
1432
1433 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1434 *pu32 = pThis->u32NicPciAddress;
1435 break;
1436
1437 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1438 *pu32 = pThis->u32AudioPciAddress;
1439 break;
1440
1441 case SYSTEM_INFO_INDEX_POWER_STATES:
1442 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1443 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1444 *pu32 |= RT_BIT(1);
1445 if (pThis->fS4Enabled)
1446 *pu32 |= RT_BIT(4);
1447 break;
1448
1449 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1450 *pu32 = pThis->u32IocPciAddress;
1451 break;
1452
1453 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1454 *pu32 = pThis->u32HbcPciAddress;
1455 break;
1456
1457 case SYSTEM_INFO_INDEX_PCI_BASE:
1458 /** @todo couldn't MCFG be in 64-bit range? */
1459 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1460 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1461 break;
1462
1463 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1464 /** @todo couldn't MCFG be in 64-bit range? */
1465 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1466 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1467 break;
1468
1469 case SYSTEM_INFO_INDEX_RTC_STATUS:
1470 *pu32 = pThis->fShowRtc
1471 ? ( STA_DEVICE_PRESENT_MASK
1472 | STA_DEVICE_ENABLED_MASK
1473 | STA_DEVICE_SHOW_IN_UI_MASK
1474 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1475 : 0;
1476 break;
1477
1478 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1479 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1480 {
1481 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1482 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1483 }
1484 else
1485 {
1486 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1487 pThis->idCpuLockCheck);
1488 /* Always return locked status just to be safe */
1489 *pu32 = 1;
1490 }
1491 break;
1492
1493 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1494 *pu32 = pThis->u32CpuEventType;
1495 break;
1496
1497 case SYSTEM_INFO_INDEX_CPU_EVENT:
1498 *pu32 = pThis->u32CpuEvent;
1499 break;
1500
1501 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1502 *pu32 = pThis->uSerial0IoPortBase;
1503 break;
1504
1505 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1506 *pu32 = pThis->uSerial0Irq;
1507 break;
1508
1509 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1510 *pu32 = pThis->uSerial1IoPortBase;
1511 break;
1512
1513 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1514 *pu32 = pThis->uSerial1Irq;
1515 break;
1516
1517 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1518 *pu32 = pThis->uSerial2IoPortBase;
1519 break;
1520
1521 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1522 *pu32 = pThis->uSerial2Irq;
1523 break;
1524
1525 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1526 *pu32 = pThis->uSerial3IoPortBase;
1527 break;
1528
1529 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1530 *pu32 = pThis->uSerial3Irq;
1531 break;
1532
1533 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1534 *pu32 = pThis->uParallel0IoPortBase;
1535 break;
1536
1537 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1538 *pu32 = pThis->uParallel0Irq;
1539 break;
1540
1541 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1542 *pu32 = pThis->uParallel1IoPortBase;
1543 break;
1544
1545 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1546 *pu32 = pThis->uParallel1Irq;
1547 break;
1548
1549 case SYSTEM_INFO_INDEX_END:
1550 /** @todo why isn't this setting any output value? */
1551 break;
1552
1553 /* Solaris 9 tries to read from this index */
1554 case SYSTEM_INFO_INDEX_INVALID:
1555 *pu32 = 0;
1556 break;
1557
1558 default:
1559 *pu32 = UINT32_MAX;
1560 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1561 break;
1562 }
1563
1564 DEVACPI_UNLOCK(pDevIns, pThis);
1565 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1566 return rc;
1567}
1568
1569/**
1570 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1571 */
1572static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1573{
1574 RT_NOREF(pvUser, offPort);
1575 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1576 if (cb != 4)
1577 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1578
1579 DEVACPI_LOCK_R3(pDevIns, pThis);
1580 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1581
1582 VBOXSTRICTRC rc = VINF_SUCCESS;
1583 switch (pThis->uSystemInfoIndex)
1584 {
1585 case SYSTEM_INFO_INDEX_INVALID:
1586 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1587 pThis->u8IndexShift = 0;
1588 break;
1589
1590 case SYSTEM_INFO_INDEX_VALID:
1591 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1592 pThis->u8IndexShift = 2;
1593 break;
1594
1595 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1596 pThis->idCpuLockCheck = u32;
1597 break;
1598
1599 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1600 if (u32 < pThis->cCpus)
1601 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1602 else
1603 LogRel(("ACPI: CPU %u does not exist\n", u32));
1604 break;
1605
1606 default:
1607 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1608 break;
1609 }
1610
1611 DEVACPI_UNLOCK(pDevIns, pThis);
1612 return rc;
1613}
1614
1615/**
1616 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1617 */
1618static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1619{
1620 RT_NOREF(offPort, pvUser);
1621 if (cb != 2)
1622 return VERR_IOM_IOPORT_UNUSED;
1623
1624 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1625 DEVACPI_LOCK_R3(pDevIns, pThis);
1626
1627 *pu32 = pThis->pm1a_en;
1628
1629 DEVACPI_UNLOCK(pDevIns, pThis);
1630 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1631 return VINF_SUCCESS;
1632}
1633
1634/**
1635 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1636 */
1637static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1638{
1639 RT_NOREF(offPort, pvUser);
1640 if (cb != 2 && cb != 4)
1641 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1642
1643 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1644 DEVACPI_LOCK_R3(pDevIns, pThis);
1645
1646 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1647 u32 &= ~(RSR_EN | IGN_EN);
1648 u32 &= 0xffff;
1649 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1650
1651 DEVACPI_UNLOCK(pDevIns, pThis);
1652 return VINF_SUCCESS;
1653}
1654
1655/**
1656 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1657 */
1658static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1659{
1660 RT_NOREF(offPort, pvUser);
1661 if (cb != 2)
1662 {
1663 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1664 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1665 }
1666
1667 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1668 DEVACPI_LOCK_R3(pDevIns, pThis);
1669
1670 *pu32 = pThis->pm1a_sts;
1671
1672 DEVACPI_UNLOCK(pDevIns, pThis);
1673 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1674 return VINF_SUCCESS;
1675}
1676
1677/**
1678 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1679 */
1680static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1681{
1682 RT_NOREF(offPort, pvUser);
1683 if (cb != 2 && cb != 4)
1684 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1685
1686 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1687 DEVACPI_LOCK_R3(pDevIns, pThis);
1688
1689 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1690 u32 &= 0xffff;
1691 if (u32 & PWRBTN_STS)
1692 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1693 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1694 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1695
1696 DEVACPI_UNLOCK(pDevIns, pThis);
1697 return VINF_SUCCESS;
1698}
1699
1700/**
1701 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1702 */
1703static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1704{
1705 RT_NOREF(offPort, pvUser);
1706 if (cb != 2)
1707 {
1708 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1709 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1710 }
1711
1712 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1713 DEVACPI_LOCK_R3(pDevIns, pThis);
1714
1715 *pu32 = pThis->pm1a_ctl;
1716
1717 DEVACPI_UNLOCK(pDevIns, pThis);
1718 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1719 return VINF_SUCCESS;
1720}
1721
1722/**
1723 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1724 */
1725static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1726{
1727 RT_NOREF(offPort, pvUser);
1728 if (cb != 2 && cb != 4)
1729 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1730
1731 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1732 DEVACPI_LOCK_R3(pDevIns, pThis);
1733
1734 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1735 u32 &= 0xffff;
1736 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1737
1738 VBOXSTRICTRC rc = VINF_SUCCESS;
1739 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1740 if (uSleepState != pThis->uSleepState)
1741 {
1742 pThis->uSleepState = uSleepState;
1743 switch (uSleepState)
1744 {
1745 case 0x00: /* S0 */
1746 break;
1747
1748 case 0x01: /* S1 */
1749 if (pThis->fS1Enabled)
1750 {
1751 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1752 rc = acpiR3DoSleep(pDevIns, pThis);
1753 break;
1754 }
1755 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1756 RT_FALL_THRU();
1757
1758 case 0x04: /* S4 */
1759 if (pThis->fS4Enabled)
1760 {
1761 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1762 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1763 break;
1764 }
1765 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1766 RT_FALL_THRU();
1767
1768 case 0x05: /* S5 */
1769 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1770 rc = acpiR3DoPowerOff(pDevIns);
1771 break;
1772
1773 default:
1774 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1775 break;
1776 }
1777 }
1778
1779 DEVACPI_UNLOCK(pDevIns, pThis);
1780 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1781 return rc;
1782}
1783
1784#endif /* IN_RING3 */
1785
1786/**
1787 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1788 *
1789 * @remarks The only I/O port currently implemented in all contexts.
1790 */
1791static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1792{
1793 RT_NOREF(offPort, pvUser);
1794 if (cb != 4)
1795 return VERR_IOM_IOPORT_UNUSED;
1796
1797 /*
1798 * We use the clock lock to serialize access to u64PmTimerInitial and to
1799 * make sure we get a reliable time from the clock
1800 * as well as and to prevent uPmTimerVal from being updated during read.
1801 */
1802 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1803 VBOXSTRICTRC rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VINF_IOM_R3_IOPORT_READ);
1804 if (rc == VINF_SUCCESS)
1805 {
1806 rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1807 if (rc == VINF_SUCCESS)
1808 {
1809 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1810 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1811 *pu32 = pThis->uPmTimerVal;
1812
1813 DEVACPI_UNLOCK(pDevIns, pThis);
1814 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
1815
1816 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1817 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1818
1819#if 0
1820 /** @todo temporary: sanity check against running backwards */
1821 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1822 if (*pu32 - uOld >= 0x10000000)
1823 {
1824# if defined(IN_RING0)
1825 pThis->uPmTimeA = uOld;
1826 pThis->uPmTimeB = *pu32;
1827 return VERR_TM_TIMER_BAD_CLOCK;
1828# elif defined(IN_RING3)
1829 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1830# endif
1831 }
1832#endif
1833 }
1834 else
1835 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
1836 }
1837 return rc;
1838}
1839
1840#ifdef IN_RING3
1841
1842/**
1843 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
1844 */
1845static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1846{
1847 RT_NOREF(offPort, pvUser);
1848 if (cb != 1)
1849 {
1850 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1851 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1852 }
1853
1854 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1855 DEVACPI_LOCK_R3(pDevIns, pThis);
1856
1857 *pu32 = pThis->gpe0_sts & 0xff;
1858
1859 DEVACPI_UNLOCK(pDevIns, pThis);
1860 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1861 return VINF_SUCCESS;
1862}
1863
1864/**
1865 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
1866 */
1867static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1868{
1869 RT_NOREF(offPort, pvUser);
1870 if (cb != 1)
1871 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1872
1873 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1874 DEVACPI_LOCK_R3(pDevIns, pThis);
1875
1876 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1877 u32 = pThis->gpe0_sts & ~u32;
1878 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1879
1880 DEVACPI_UNLOCK(pDevIns, pThis);
1881 return VINF_SUCCESS;
1882}
1883
1884/**
1885 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
1886 */
1887static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1888{
1889 RT_NOREF(offPort, pvUser);
1890 if (cb != 1)
1891 {
1892 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1893 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1894 }
1895
1896 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1897 DEVACPI_LOCK_R3(pDevIns, pThis);
1898
1899 *pu32 = pThis->gpe0_en & 0xff;
1900
1901 DEVACPI_UNLOCK(pDevIns, pThis);
1902 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1903 return VINF_SUCCESS;
1904}
1905
1906/**
1907 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
1908 */
1909static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1910{
1911 RT_NOREF(offPort, pvUser);
1912 if (cb != 1)
1913 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1914
1915 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1916 DEVACPI_LOCK_R3(pDevIns, pThis);
1917
1918 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1919 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
1920
1921 DEVACPI_UNLOCK(pDevIns, pThis);
1922 return VINF_SUCCESS;
1923}
1924
1925/**
1926 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
1927 */
1928static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1929{
1930 RT_NOREF(offPort, pvUser);
1931 Log(("acpiR3SmiWrite %#x\n", u32));
1932 if (cb != 1)
1933 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1934
1935 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1936 DEVACPI_LOCK_R3(pDevIns, pThis);
1937
1938 if (u32 == ACPI_ENABLE)
1939 pThis->pm1a_ctl |= SCI_EN;
1940 else if (u32 == ACPI_DISABLE)
1941 pThis->pm1a_ctl &= ~SCI_EN;
1942 else
1943 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1944
1945 DEVACPI_UNLOCK(pDevIns, pThis);
1946 return VINF_SUCCESS;
1947}
1948
1949/**
1950 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
1951 */
1952static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1953{
1954 RT_NOREF(offPort, pvUser);
1955 Log(("acpiR3ResetWrite: %#x\n", u32));
1956 NOREF(pvUser);
1957 if (cb != 1)
1958 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1959
1960 /* No state locking required. */
1961 VBOXSTRICTRC rc;
1962 if (u32 == ACPI_RESET_REG_VAL)
1963 {
1964 LogRel(("ACPI: Reset initiated by ACPI\n"));
1965 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
1966 }
1967 else
1968 {
1969 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1970 rc = VINF_SUCCESS;
1971 }
1972
1973 return rc;
1974}
1975
1976# ifdef DEBUG_ACPI
1977
1978/**
1979 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
1980 */
1981static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1982{
1983 NOREF(pvUser);
1984 switch (cb)
1985 {
1986 case 1:
1987 Log(("%#x\n", u32 & 0xff));
1988 break;
1989 case 2:
1990 Log(("%#6x\n", u32 & 0xffff));
1991 break;
1992 case 4:
1993 Log(("%#10x\n", u32));
1994 break;
1995 default:
1996 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1997 }
1998 return VINF_SUCCESS;
1999}
2000
2001/**
2002 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2003 */
2004static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2005{
2006 NOREF(pvUser);
2007 switch (cb)
2008 {
2009 case 1:
2010 Log(("%c", u32 & 0xff));
2011 break;
2012 default:
2013 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2014 }
2015 return VINF_SUCCESS;
2016}
2017
2018# endif /* DEBUG_ACPI */
2019
2020/**
2021 * @callback_method_impl{FNDBGFHANDLERDEV}
2022 */
2023static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2024{
2025 RT_NOREF(pszArgs);
2026 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2027 pHlp->pfnPrintf(pHlp,
2028 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2029}
2030
2031/**
2032 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2033 *
2034 * @param pDevIns The PDM device instance.
2035 * @param pThis The ACPI shared instance data.
2036 */
2037static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2038{
2039 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2040 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2041 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2042 pPciDev->abConfig[PMBA + 2] = 0x00;
2043 pPciDev->abConfig[PMBA + 3] = 0x00;
2044}
2045
2046/**
2047 * Used to calculate the value of a PM I/O port.
2048 *
2049 * @returns The actual I/O port value.
2050 * @param pThis The ACPI shared instance data.
2051 * @param offset The offset into the I/O space, or -1 if invalid.
2052 */
2053static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2054{
2055 Assert(pThis->uPmIoPortBase != 0);
2056
2057 if (offset == -1)
2058 return 0;
2059
2060 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2061}
2062
2063/**
2064 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2065 * timer and GPE0 I/O ports.
2066 *
2067 * @returns VBox status code.
2068 * @param pDevIns The device instance.
2069 * @param pThis The ACPI shared instance data.
2070 */
2071static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2072{
2073 if (pThis->uPmIoPortBase == 0)
2074 return VINF_SUCCESS;
2075
2076 int rc;
2077 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2078 AssertRCReturn(rc, rc);
2079 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2080 AssertRCReturn(rc, rc);
2081 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2082 AssertRCReturn(rc, rc);
2083 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2084 AssertRCReturn(rc, rc);
2085 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2086 AssertRCReturn(rc, rc);
2087 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2088
2089 return VINF_SUCCESS;
2090}
2091
2092/**
2093 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2094 * timer and GPE0 I/O ports.
2095 *
2096 * @returns VBox status code.
2097 * @param pDevIns The device instance.
2098 * @param pThis The ACPI shared instance data.
2099 */
2100static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2101{
2102 if (pThis->uPmIoPortBase != 0)
2103 {
2104 int rc;
2105 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2106 AssertRCReturn(rc, rc);
2107 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2108 AssertRCReturn(rc, rc);
2109 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2110 AssertRCReturn(rc, rc);
2111 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2112 AssertRCReturn(rc, rc);
2113 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2114 AssertRCReturn(rc, rc);
2115 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2116 AssertRCReturn(rc, rc);
2117 }
2118 return VINF_SUCCESS;
2119}
2120
2121/**
2122 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2123 * PM1a, PM timer and GPE0 ports.
2124 *
2125 * @returns VBox status code.
2126 *
2127 * @param pDevIns The device instance.
2128 * @param pThis The ACPI shared instance data.
2129 * @param pThisCC The ACPI instance data for ring-3.
2130 * @param NewIoPortBase The new base address of the I/O ports.
2131 */
2132static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2133{
2134 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2135 if (NewIoPortBase != pThis->uPmIoPortBase)
2136 {
2137 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2138 if (RT_FAILURE(rc))
2139 return rc;
2140
2141 pThis->uPmIoPortBase = NewIoPortBase;
2142
2143 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2144 if (RT_FAILURE(rc))
2145 return rc;
2146
2147 /* We have to update FADT table acccording to the new base */
2148 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2149 AssertRC(rc);
2150 if (RT_FAILURE(rc))
2151 return rc;
2152 }
2153
2154 return VINF_SUCCESS;
2155}
2156
2157/**
2158 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2159 */
2160static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2161{
2162 RT_NOREF(pvUser);
2163 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2164
2165 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2166 uint8_t off = offPort & 0x000f;
2167 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2168 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2169 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2170
2171 DEVACPI_LOCK_R3(pDevIns, pThis);
2172 switch (off)
2173 {
2174 case SMBHSTSTS_OFF:
2175 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2176 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2177 break;
2178 case SMBSLVSTS_OFF:
2179 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2180 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2181 break;
2182 case SMBHSTCNT_OFF:
2183 {
2184 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2185
2186 const bool old_level = acpiSCILevel(pDevIns, pThis);
2187 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2188 if (u32 & SMBHSTCNT_START)
2189 {
2190 /* Start, trigger error as this is a dummy implementation */
2191 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2192 }
2193 if (u32 & SMBHSTCNT_KILL)
2194 {
2195 /* Kill */
2196 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2197 }
2198 const bool new_level = acpiSCILevel(pDevIns, pThis);
2199
2200 LogFunc(("old=%x new=%x\n", old_level, new_level));
2201
2202 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2203 * needs to be implemented later if it ever becomes relevant. */
2204 if (new_level != old_level)
2205 acpiSetIrq(pDevIns, new_level);
2206 break;
2207 }
2208 case SMBHSTCMD_OFF:
2209 pThis->u8SMBusHstCmd = u32;
2210 break;
2211 case SMBHSTADD_OFF:
2212 pThis->u8SMBusHstAdd = u32;
2213 break;
2214 case SMBHSTDAT0_OFF:
2215 pThis->u8SMBusHstDat0 = u32;
2216 break;
2217 case SMBHSTDAT1_OFF:
2218 pThis->u8SMBusHstDat1 = u32;
2219 break;
2220 case SMBBLKDAT_OFF:
2221 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2222 pThis->u8SMBusBlkIdx++;
2223 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2224 break;
2225 case SMBSLVCNT_OFF:
2226 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2227 break;
2228 case SMBSHDWCMD_OFF:
2229 /* readonly register */
2230 break;
2231 case SMBSLVEVT_OFF:
2232 pThis->u16SMBusSlvEvt = u32;
2233 break;
2234 case SMBSLVDAT_OFF:
2235 /* readonly register */
2236 break;
2237 default:
2238 /* caught by the sanity check above */
2239 ;
2240 }
2241
2242 DEVACPI_UNLOCK(pDevIns, pThis);
2243 return VINF_SUCCESS;
2244}
2245
2246/**
2247 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2248 */
2249static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2250{
2251 RT_NOREF(pvUser);
2252 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2253
2254 VBOXSTRICTRC rc = VINF_SUCCESS;
2255 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2256 uint8_t const off = offPort & 0x000f;
2257 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2258 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2259 return VERR_IOM_IOPORT_UNUSED;
2260
2261 DEVACPI_LOCK_R3(pDevIns, pThis);
2262 switch (off)
2263 {
2264 case SMBHSTSTS_OFF:
2265 *pu32 = pThis->u8SMBusHstSts;
2266 break;
2267 case SMBSLVSTS_OFF:
2268 *pu32 = pThis->u8SMBusSlvSts;
2269 break;
2270 case SMBHSTCNT_OFF:
2271 pThis->u8SMBusBlkIdx = 0;
2272 *pu32 = pThis->u8SMBusHstCnt;
2273 break;
2274 case SMBHSTCMD_OFF:
2275 *pu32 = pThis->u8SMBusHstCmd;
2276 break;
2277 case SMBHSTADD_OFF:
2278 *pu32 = pThis->u8SMBusHstAdd;
2279 break;
2280 case SMBHSTDAT0_OFF:
2281 *pu32 = pThis->u8SMBusHstDat0;
2282 break;
2283 case SMBHSTDAT1_OFF:
2284 *pu32 = pThis->u8SMBusHstDat1;
2285 break;
2286 case SMBBLKDAT_OFF:
2287 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2288 pThis->u8SMBusBlkIdx++;
2289 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2290 break;
2291 case SMBSLVCNT_OFF:
2292 *pu32 = pThis->u8SMBusSlvCnt;
2293 break;
2294 case SMBSHDWCMD_OFF:
2295 *pu32 = pThis->u8SMBusShdwCmd;
2296 break;
2297 case SMBSLVEVT_OFF:
2298 *pu32 = pThis->u16SMBusSlvEvt;
2299 break;
2300 case SMBSLVDAT_OFF:
2301 *pu32 = pThis->u16SMBusSlvDat;
2302 break;
2303 default:
2304 /* caught by the sanity check above */
2305 rc = VERR_IOM_IOPORT_UNUSED;
2306 }
2307 DEVACPI_UNLOCK(pDevIns, pThis);
2308
2309 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2310 return rc;
2311}
2312
2313/**
2314 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2315 *
2316 * @param pDevIns The PDM device instance.
2317 * @param pThis The ACPI shared instance data.
2318 */
2319static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2320{
2321 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2322 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2323 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2324 pPciDev->abConfig[SMBBA+2] = 0x00;
2325 pPciDev->abConfig[SMBBA+3] = 0x00;
2326 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2327 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2328 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2329 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2330 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2331}
2332
2333/**
2334 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2335 *
2336 * @param pThis The ACPI shared instance data.
2337 */
2338static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2339{
2340 pThis->u8SMBusHstSts = 0x00;
2341 pThis->u8SMBusSlvSts = 0x00;
2342 pThis->u8SMBusHstCnt = 0x00;
2343 pThis->u8SMBusHstCmd = 0x00;
2344 pThis->u8SMBusHstAdd = 0x00;
2345 pThis->u8SMBusHstDat0 = 0x00;
2346 pThis->u8SMBusHstDat1 = 0x00;
2347 pThis->u8SMBusSlvCnt = 0x00;
2348 pThis->u8SMBusShdwCmd = 0x00;
2349 pThis->u16SMBusSlvEvt = 0x0000;
2350 pThis->u16SMBusSlvDat = 0x0000;
2351 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2352 pThis->u8SMBusBlkIdx = 0;
2353}
2354
2355/**
2356 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2357 *
2358 * @returns VBox status code.
2359 * @param pDevIns The device instance.
2360 * @param pThis The ACPI shared instance data.
2361 */
2362static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2363{
2364 if (pThis->uSMBusIoPortBase != 0)
2365 {
2366 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2367 AssertRCReturn(rc, rc);
2368 }
2369 return VINF_SUCCESS;
2370}
2371
2372/**
2373 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2374 *
2375 * @returns VBox status code.
2376 * @param pDevIns The device instance.
2377 * @param pThis The ACPI shared instance data.
2378 */
2379static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2380{
2381 if (pThis->uSMBusIoPortBase != 0)
2382 {
2383 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2384 AssertRCReturn(rc, rc);
2385 }
2386 return VINF_SUCCESS;
2387}
2388
2389/**
2390 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2391 * SMBus ports.
2392 *
2393 * @returns VBox status code.
2394 *
2395 * @param pDevIns The device instance.
2396 * @param pThis The ACPI shared instance data.
2397 * @param NewIoPortBase The new base address of the I/O ports.
2398 */
2399static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2400{
2401 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2402 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2403 {
2404 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2405 AssertRCReturn(rc, rc);
2406
2407 pThis->uSMBusIoPortBase = NewIoPortBase;
2408
2409 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2410 AssertRCReturn(rc, rc);
2411
2412#if 0 /* is there an FADT table entry for the SMBus base? */
2413 /* We have to update FADT table acccording to the new base */
2414 rc = acpiR3PlantTables(pThis);
2415 AssertRC(rc);
2416 if (RT_FAILURE(rc))
2417 return rc;
2418#endif
2419 }
2420
2421 return VINF_SUCCESS;
2422}
2423
2424
2425/**
2426 * Saved state structure description, version 4.
2427 */
2428static const SSMFIELD g_AcpiSavedStateFields4[] =
2429{
2430 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2431 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2432 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2433 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2434 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2435 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2436 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2437 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2438 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2439 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2440 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2441 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2442 SSMFIELD_ENTRY_TERM()
2443};
2444
2445/**
2446 * Saved state structure description, version 5.
2447 */
2448static const SSMFIELD g_AcpiSavedStateFields5[] =
2449{
2450 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2451 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2452 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2453 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2454 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2455 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2456 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2457 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2458 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2459 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2460 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2461 SSMFIELD_ENTRY_TERM()
2462};
2463
2464/**
2465 * Saved state structure description, version 6.
2466 */
2467static const SSMFIELD g_AcpiSavedStateFields6[] =
2468{
2469 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2470 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2471 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2472 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2473 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2474 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2475 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2476 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2477 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2478 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2479 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2480 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2481 SSMFIELD_ENTRY_TERM()
2482};
2483
2484/**
2485 * Saved state structure description, version 7.
2486 */
2487static const SSMFIELD g_AcpiSavedStateFields7[] =
2488{
2489 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2490 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2491 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2492 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2493 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2494 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2495 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2496 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2497 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2498 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2499 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2500 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2501 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2502 SSMFIELD_ENTRY_TERM()
2503};
2504
2505/**
2506 * Saved state structure description, version 8.
2507 */
2508static const SSMFIELD g_AcpiSavedStateFields8[] =
2509{
2510 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2511 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2512 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2513 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2514 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2515 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2516 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2517 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2518 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2519 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2520 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2521 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2522 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2523 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2524 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2525 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2526 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2527 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2528 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2529 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2530 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2531 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2532 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2533 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2534 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2535 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2536 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2537 SSMFIELD_ENTRY_TERM()
2538};
2539
2540/**
2541 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2542 */
2543static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2544{
2545 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2546 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2547 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2548}
2549
2550/**
2551 * @callback_method_impl{FNSSMDEVLOADEXEC}
2552 */
2553static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2554{
2555 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2556 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2557 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2558 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2559
2560 /*
2561 * Unmap PM I/O ports, will remap it with the actual base after state
2562 * successfully loaded.
2563 */
2564 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2565 AssertRCReturn(rc, rc);
2566
2567 /*
2568 * Unregister SMBus handlers, will register with actual base after state
2569 * successfully loaded.
2570 */
2571 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2572 AssertRCReturn(rc, rc);
2573 acpiR3SMBusResetDevice(pThis);
2574
2575 switch (uVersion)
2576 {
2577 case 4:
2578 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2579 break;
2580 case 5:
2581 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2582 break;
2583 case 6:
2584 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2585 break;
2586 case 7:
2587 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2588 break;
2589 case 8:
2590 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2591 break;
2592 default:
2593 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2594 break;
2595 }
2596 if (RT_SUCCESS(rc))
2597 {
2598 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2599 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2600 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2601 AssertRCReturn(rc, rc);
2602 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2603 AssertRCReturn(rc, rc);
2604 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2605 AssertRCReturn(rc, rc);
2606 rc = acpiR3FetchBatteryInfo(pThis);
2607 AssertRCReturn(rc, rc);
2608
2609 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2610 DEVACPI_LOCK_R3(pDevIns, pThis);
2611 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2612 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2613 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2614 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2615 DEVACPI_UNLOCK(pDevIns, pThis);
2616 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
2617 }
2618 return rc;
2619}
2620
2621/**
2622 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2623 */
2624static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2625{
2626 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2627 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2628 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2629 return NULL;
2630}
2631
2632/**
2633 * Calculate the check sum for some ACPI data before planting it.
2634 *
2635 * All the bytes must add up to 0.
2636 *
2637 * @returns check sum.
2638 * @param pvSrc What to check sum.
2639 * @param cbData The amount of data to checksum.
2640 */
2641static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2642{
2643 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2644 uint8_t uSum = 0;
2645 for (size_t i = 0; i < cbData; ++i)
2646 uSum += pbSrc[i];
2647 return -uSum;
2648}
2649
2650/**
2651 * Prepare a ACPI table header.
2652 */
2653static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2654 const char au8Signature[4],
2655 uint32_t u32Length, uint8_t u8Revision)
2656{
2657 memcpy(header->au8Signature, au8Signature, 4);
2658 header->u32Length = RT_H2LE_U32(u32Length);
2659 header->u8Revision = u8Revision;
2660 memcpy(header->au8OemId, pThis->au8OemId, 6);
2661 memcpy(header->au8OemTabId, "VBOX", 4);
2662 memcpy(header->au8OemTabId+4, au8Signature, 4);
2663 header->u32OemRevision = RT_H2LE_U32(1);
2664 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2665 header->u32CreatorRev = pThis->u32CreatorRev;
2666}
2667
2668/**
2669 * Initialize a generic address structure (ACPIGENADDR).
2670 */
2671static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2672 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2673 uint8_t u8AccessSize, uint64_t u64Address)
2674{
2675 g->u8AddressSpaceId = u8AddressSpaceId;
2676 g->u8RegisterBitWidth = u8RegisterBitWidth;
2677 g->u8RegisterBitOffset = u8RegisterBitOffset;
2678 g->u8AccessSize = u8AccessSize;
2679 g->u64Address = RT_H2LE_U64(u64Address);
2680}
2681
2682/**
2683 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2684 */
2685DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2686{
2687 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2688}
2689
2690/**
2691 * Plant the Differentiated System Description Table (DSDT).
2692 */
2693static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2694{
2695 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2696}
2697
2698/**
2699 * Plant the Secondary System Description Table (SSDT).
2700 */
2701static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2702{
2703 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2704}
2705
2706/**
2707 * Plant the Firmware ACPI Control Structure (FACS).
2708 */
2709static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2710{
2711 ACPITBLFACS facs;
2712
2713 memset(&facs, 0, sizeof(facs));
2714 memcpy(facs.au8Signature, "FACS", 4);
2715 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2716 facs.u32HWSignature = RT_H2LE_U32(0);
2717 facs.u32FWVector = RT_H2LE_U32(0);
2718 facs.u32GlobalLock = RT_H2LE_U32(0);
2719 facs.u32Flags = RT_H2LE_U32(0);
2720 facs.u64X_FWVector = RT_H2LE_U64(0);
2721 facs.u8Version = 1;
2722
2723 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2724}
2725
2726/**
2727 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2728 */
2729static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2730 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2731{
2732 ACPITBLFADT fadt;
2733
2734 /* First the ACPI version 2+ version of the structure. */
2735 memset(&fadt, 0, sizeof(fadt));
2736 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2737 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2738 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2739 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2740 fadt.u8PreferredPMProfile = 0; /* unspecified */
2741 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2742 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2743 fadt.u8AcpiEnable = ACPI_ENABLE;
2744 fadt.u8AcpiDisable = ACPI_DISABLE;
2745 fadt.u8S4BIOSReq = 0;
2746 fadt.u8PStateCnt = 0;
2747 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2748 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2749 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2750 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2751 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2752 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2753 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2754 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2755 fadt.u8PM1EVTLEN = 4;
2756 fadt.u8PM1CTLLEN = 2;
2757 fadt.u8PM2CTLLEN = 0;
2758 fadt.u8PMTMLEN = 4;
2759 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2760 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2761 fadt.u8GPE1BASE = GPE1_BASE;
2762 fadt.u8CSTCNT = 0;
2763 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2764 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2765 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2766 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2767 fadt.u8DutyOffset = 0;
2768 fadt.u8DutyWidth = 0;
2769 fadt.u8DayAlarm = 0;
2770 fadt.u8MonAlarm = 0;
2771 fadt.u8Century = 0;
2772 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2773 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2774 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2775 | FADT_FL_FIX_RTC
2776 | FADT_FL_TMR_VAL_EXT
2777 | FADT_FL_RESET_REG_SUP);
2778
2779 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2780 if (pThis->fCpuHotPlug)
2781 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2782
2783 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2784 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2785 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2786 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2787 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2788 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2789 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2790 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2791 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2792 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2793 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2794 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2795 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2796 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2797
2798 /* Now the ACPI 1.0 version. */
2799 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2800 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2801 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2802 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2803 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2804}
2805
2806/**
2807 * Plant the root System Description Table.
2808 *
2809 * The RSDT and XSDT tables are basically identical. The only difference is 32
2810 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2811 * ACPI 2.0 and up.
2812 */
2813static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2814{
2815 ACPITBLRSDT *rsdt;
2816 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2817
2818 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2819 if (!rsdt)
2820 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2821
2822 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2823 for (unsigned int i = 0; i < nb_entries; ++i)
2824 {
2825 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2826 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2827 }
2828 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2829 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2830 RTMemFree(rsdt);
2831 return VINF_SUCCESS;
2832}
2833
2834/**
2835 * Plant the Extended System Description Table.
2836 */
2837static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2838{
2839 ACPITBLXSDT *xsdt;
2840 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2841 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
2842 if (!xsdt)
2843 return VERR_NO_TMP_MEMORY;
2844
2845 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
2846
2847 if (pThis->cCustTbls > 0)
2848 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2849
2850 for (unsigned int i = 0; i < nb_entries; ++i)
2851 {
2852 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2853 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2854 }
2855 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
2856 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
2857
2858 RTMemFree(xsdt);
2859 return VINF_SUCCESS;
2860}
2861
2862/**
2863 * Plant the Root System Description Pointer (RSDP).
2864 */
2865static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2866{
2867 memset(rsdp, 0, sizeof(*rsdp));
2868
2869 /* ACPI 1.0 part (RSDT) */
2870 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2871 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2872 rsdp->u8Revision = ACPI_REVISION;
2873 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2874 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2875
2876 /* ACPI 2.0 part (XSDT) */
2877 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2878 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2879 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2880}
2881
2882/**
2883 * Multiple APIC Description Table.
2884 *
2885 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2886 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2887 * use regular C structure and proxy to raw memory instead.
2888 */
2889class AcpiTableMadt
2890{
2891 /**
2892 * All actual data stored in dynamically allocated memory pointed by this field.
2893 */
2894 uint8_t *m_pbData;
2895 /**
2896 * Number of CPU entries in this MADT.
2897 */
2898 uint32_t m_cCpus;
2899
2900 /**
2901 * Number of interrupt overrides.
2902 */
2903 uint32_t m_cIsos;
2904
2905public:
2906 /**
2907 * Address of ACPI header
2908 */
2909 inline ACPITBLHEADER *header_addr(void) const
2910 {
2911 return (ACPITBLHEADER *)m_pbData;
2912 }
2913
2914 /**
2915 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2916 * although address is the same for all of them.
2917 */
2918 inline uint32_t *u32LAPIC_addr(void) const
2919 {
2920 return (uint32_t *)(header_addr() + 1);
2921 }
2922
2923 /**
2924 * Address of APIC flags
2925 */
2926 inline uint32_t *u32Flags_addr(void) const
2927 {
2928 return (uint32_t *)(u32LAPIC_addr() + 1);
2929 }
2930
2931 /**
2932 * Address of ISO description
2933 */
2934 inline ACPITBLISO *ISO_addr(void) const
2935 {
2936 return (ACPITBLISO *)(u32Flags_addr() + 1);
2937 }
2938
2939 /**
2940 * Address of per-CPU LAPIC descriptions
2941 */
2942 inline ACPITBLLAPIC *LApics_addr(void) const
2943 {
2944 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2945 }
2946
2947 /**
2948 * Address of IO APIC description
2949 */
2950 inline ACPITBLIOAPIC *IOApic_addr(void) const
2951 {
2952 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2953 }
2954
2955 /**
2956 * Size of MADT.
2957 * Note that this function assumes IOApic to be the last field in structure.
2958 */
2959 inline uint32_t size(void) const
2960 {
2961 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2962 }
2963
2964 /**
2965 * Raw data of MADT.
2966 */
2967 inline const uint8_t *data(void) const
2968 {
2969 return m_pbData;
2970 }
2971
2972 /**
2973 * Size of MADT for given ACPI config, useful to compute layout.
2974 */
2975 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
2976 {
2977 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2978 }
2979
2980 /*
2981 * Constructor, only works in Ring 3, doesn't look like a big deal.
2982 */
2983 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2984 {
2985 m_cCpus = cCpus;
2986 m_cIsos = cIsos;
2987 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2988 uint32_t cb = size();
2989 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2990 }
2991
2992 ~AcpiTableMadt()
2993 {
2994 RTMemFree(m_pbData);
2995 }
2996};
2997
2998
2999/**
3000 * Plant the Multiple APIC Description Table (MADT).
3001 *
3002 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3003 *
3004 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3005 */
3006static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3007{
3008 uint16_t cpus = pThis->cCpus;
3009 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3010
3011 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3012
3013 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3014 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3015
3016 /* LAPICs records */
3017 ACPITBLLAPIC* lapic = madt.LApics_addr();
3018 for (uint16_t i = 0; i < cpus; i++)
3019 {
3020 lapic->u8Type = 0;
3021 lapic->u8Length = sizeof(ACPITBLLAPIC);
3022 lapic->u8ProcId = i;
3023 /** Must match numbering convention in MPTABLES */
3024 lapic->u8ApicId = i;
3025 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3026 lapic++;
3027 }
3028
3029 /* IO-APIC record */
3030 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3031 ioapic->u8Type = 1;
3032 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3033 /** Must match MP tables ID */
3034 ioapic->u8IOApicId = cpus;
3035 ioapic->u8Reserved = 0;
3036 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3037 ioapic->u32GSIB = RT_H2LE_U32(0);
3038
3039 /* Interrupt Source Overrides */
3040 /* Flags:
3041 bits[3:2]:
3042 00 conforms to the bus
3043 01 edge-triggered
3044 10 reserved
3045 11 level-triggered
3046 bits[1:0]
3047 00 conforms to the bus
3048 01 active-high
3049 10 reserved
3050 11 active-low */
3051 /* If changing, also update PDMIsaSetIrq() and MPS */
3052 ACPITBLISO* isos = madt.ISO_addr();
3053 /* Timer interrupt rule IRQ0 to GSI2 */
3054 isos[0].u8Type = 2;
3055 isos[0].u8Length = sizeof(ACPITBLISO);
3056 isos[0].u8Bus = 0; /* Must be 0 */
3057 isos[0].u8Source = 0; /* IRQ0 */
3058 isos[0].u32GSI = 2; /* connected to pin 2 */
3059 isos[0].u16Flags = 0; /* conform to the bus */
3060
3061 /* ACPI interrupt rule - IRQ9 to GSI9 */
3062 isos[1].u8Type = 2;
3063 isos[1].u8Length = sizeof(ACPITBLISO);
3064 isos[1].u8Bus = 0; /* Must be 0 */
3065 isos[1].u8Source = 9; /* IRQ9 */
3066 isos[1].u32GSI = 9; /* connected to pin 9 */
3067 isos[1].u16Flags = 0xf; /* active low, level triggered */
3068 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3069
3070 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3071 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3072}
3073
3074/**
3075 * Plant the High Performance Event Timer (HPET) descriptor.
3076 */
3077static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3078{
3079 ACPITBLHPET hpet;
3080
3081 memset(&hpet, 0, sizeof(hpet));
3082
3083 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3084 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3085 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3086 0 /* Memory address space */,
3087 64 /* Register bit width */,
3088 0 /* Bit offset */,
3089 0, /* Register access size, is it correct? */
3090 0xfed00000 /* Address */);
3091
3092 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3093 hpet.u32Number = 0;
3094 hpet.u32MinTick = 4096;
3095 hpet.u8Attributes = 0;
3096
3097 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3098
3099 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3100}
3101
3102
3103/**
3104 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3105 * descriptor.
3106 *
3107 * @param pThis The ACPI shared instance data.
3108 * @param GCPhysDst Where to plant it.
3109 */
3110static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3111{
3112 struct
3113 {
3114 ACPITBLMCFG hdr;
3115 ACPITBLMCFGENTRY entry;
3116 } tbl;
3117 uint8_t u8StartBus = 0;
3118 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3119
3120 RT_ZERO(tbl);
3121
3122 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3123 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3124 tbl.entry.u8StartBus = u8StartBus;
3125 tbl.entry.u8EndBus = u8EndBus;
3126 // u16PciSegmentGroup must match _SEG in ACPI table
3127
3128 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3129
3130 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3131}
3132
3133/**
3134 * Used by acpiR3PlantTables and acpiConstruct.
3135 *
3136 * @returns Guest memory address.
3137 */
3138static uint32_t apicR3FindRsdpSpace(void)
3139{
3140 return 0xe0000;
3141}
3142
3143/**
3144 * Called by acpiR3Construct to read and allocate a custom ACPI table
3145 *
3146 * @param pDevIns The device instance.
3147 * @param ppu8CustBin Address to receive the address of the table
3148 * @param pcbCustBin Address to receive the size of the the table.
3149 * @param pszCustBinFile
3150 * @param cbBufAvail Maximum space in bytes available for the custom
3151 * table (including header).
3152 */
3153static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3154 char *pszCustBinFile, uint32_t cbBufAvail)
3155{
3156 RTFILE FileCUSTBin;
3157 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3158 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3159 if (RT_SUCCESS(rc))
3160 {
3161 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3162 if (RT_SUCCESS(rc))
3163 {
3164 /* The following checks should be in sync the AssertReleaseMsg's below. */
3165 if ( *pcbCustBin > cbBufAvail
3166 || *pcbCustBin < sizeof(ACPITBLHEADER))
3167 rc = VERR_TOO_MUCH_DATA;
3168
3169 /*
3170 * Allocate buffer for the custom table binary data.
3171 */
3172 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3173 if (*ppu8CustBin)
3174 {
3175 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3176 if (RT_FAILURE(rc))
3177 {
3178 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3179 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3180 *ppu8CustBin = NULL;
3181 }
3182 }
3183 else
3184 {
3185 rc = VERR_NO_MEMORY;
3186 }
3187 RTFileClose(FileCUSTBin);
3188 }
3189 }
3190 return rc;
3191}
3192
3193/**
3194 * Create the ACPI tables in guest memory.
3195 */
3196static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3197{
3198 int rc;
3199 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3200 RTGCPHYS32 GCPhysHpet = 0;
3201 RTGCPHYS32 GCPhysApic = 0;
3202 RTGCPHYS32 GCPhysSsdt = 0;
3203 RTGCPHYS32 GCPhysMcfg = 0;
3204 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3205 uint32_t addend = 0;
3206 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3207 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3208 uint32_t cAddr;
3209 uint32_t iMadt = 0;
3210 uint32_t iHpet = 0;
3211 uint32_t iSsdt = 0;
3212 uint32_t iMcfg = 0;
3213 uint32_t iCust = 0;
3214 size_t cbRsdt = sizeof(ACPITBLHEADER);
3215 size_t cbXsdt = sizeof(ACPITBLHEADER);
3216
3217 cAddr = 1; /* FADT */
3218 if (pThis->u8UseIOApic)
3219 iMadt = cAddr++; /* MADT */
3220
3221 if (pThis->fUseHpet)
3222 iHpet = cAddr++; /* HPET */
3223
3224 if (pThis->fUseMcfg)
3225 iMcfg = cAddr++; /* MCFG */
3226
3227 if (pThis->cCustTbls > 0)
3228 {
3229 iCust = cAddr; /* CUST */
3230 cAddr += pThis->cCustTbls;
3231 }
3232
3233 iSsdt = cAddr++; /* SSDT */
3234
3235 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3236 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3237
3238 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3239 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3240
3241 /*
3242 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3243 * The latter starts never below 4G.
3244 */
3245 PVM pVM = PDMDevHlpGetVM(pDevIns);
3246 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3247 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3248
3249 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3250 if (pThis->fPciPref64Enabled)
3251 {
3252 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3253 if (pThis->u64PciPref64Max > u64PciPref64Min)
3254 {
3255 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3256 pThis->u64PciPref64Min = u64PciPref64Min;
3257 LogRel(("ACPI: enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3258 u64PciPref64Min, pThis->u64PciPref64Max-1));
3259 }
3260 else
3261 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3262 u64PciPref64Min, pThis->u64PciPref64Max-1));
3263 }
3264 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3265 {
3266 /* Note: This is also enforced by DevPcBios.cpp. */
3267 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3268 cbBelow4GB = UINT32_C(0xfe000000);
3269 }
3270 pThis->cbRamLow = cbBelow4GB;
3271
3272 GCPhysCur = 0;
3273 GCPhysRsdt = GCPhysCur;
3274
3275 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3276 GCPhysXsdt = GCPhysCur;
3277
3278 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3279 GCPhysFadtAcpi1 = GCPhysCur;
3280
3281 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3282 GCPhysFadtAcpi2 = GCPhysCur;
3283
3284 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3285 GCPhysFacs = GCPhysCur;
3286
3287 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3288 if (pThis->u8UseIOApic)
3289 {
3290 GCPhysApic = GCPhysCur;
3291 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3292 }
3293 if (pThis->fUseHpet)
3294 {
3295 GCPhysHpet = GCPhysCur;
3296 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3297 }
3298 if (pThis->fUseMcfg)
3299 {
3300 GCPhysMcfg = GCPhysCur;
3301 /* Assume one entry */
3302 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3303 }
3304
3305 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3306 {
3307 aGCPhysCust[i] = GCPhysCur;
3308 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3309 }
3310
3311 void *pvSsdtCode = NULL;
3312 size_t cbSsdt = 0;
3313 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3314 if (RT_FAILURE(rc))
3315 return rc;
3316
3317 GCPhysSsdt = GCPhysCur;
3318 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3319
3320 GCPhysDsdt = GCPhysCur;
3321
3322 void *pvDsdtCode = NULL;
3323 size_t cbDsdt = 0;
3324 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3325 if (RT_FAILURE(rc))
3326 return rc;
3327
3328 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3329
3330 if (GCPhysCur > 0x10000)
3331 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3332 N_("Error: ACPI tables bigger than 64KB"));
3333
3334 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3335 addend = pThis->cbRamLow - 0x10000;
3336 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3337 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3338 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3339 if (pThis->u8UseIOApic)
3340 Log((" MADT 0x%08X", GCPhysApic + addend));
3341 if (pThis->fUseHpet)
3342 Log((" HPET 0x%08X", GCPhysHpet + addend));
3343 if (pThis->fUseMcfg)
3344 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3345 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3346 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3347 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3348 Log(("\n"));
3349
3350 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3351 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3352 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3353 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3354 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3355
3356 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3357 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3358 if (pThis->u8UseIOApic)
3359 {
3360 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3361 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3362 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3363 }
3364 if (pThis->fUseHpet)
3365 {
3366 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3367 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3368 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3369 }
3370 if (pThis->fUseMcfg)
3371 {
3372 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3373 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3374 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3375 }
3376 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3377 {
3378 Assert(i < MAX_CUST_TABLES);
3379 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3380 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3381 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3382 uint8_t* pSig = pThisCC->apu8CustBin[i];
3383 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3384 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3385 }
3386
3387 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3388 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3389 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3390 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3391
3392 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3393 if (RT_FAILURE(rc))
3394 return rc;
3395 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3396}
3397
3398/**
3399 * @callback_method_impl{FNPCICONFIGREAD}
3400 */
3401static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3402 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3403{
3404 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3405 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3406 return rcStrict;
3407}
3408
3409/**
3410 * @callback_method_impl{FNPCICONFIGWRITE}
3411 */
3412static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3413 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3414{
3415 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3416 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3417
3418 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3419 DEVACPI_LOCK_R3(pDevIns, pThis);
3420
3421 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3422 {
3423 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3424 u32Value = SCI_INT;
3425 }
3426
3427 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3428
3429 /* Assume that the base address is only changed when the corresponding
3430 * hardware functionality is disabled. The IO region is mapped when the
3431 * functionality is enabled by the guest. */
3432
3433 if (uAddress == PMREGMISC)
3434 {
3435 RTIOPORT NewIoPortBase = 0;
3436 /* Check Power Management IO Space Enable (PMIOSE) bit */
3437 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3438 {
3439 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3440 NewIoPortBase &= 0xffc0;
3441 }
3442
3443 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
3444 AssertRC(rc);
3445 }
3446
3447 if (uAddress == SMBHSTCFG)
3448 {
3449 RTIOPORT NewIoPortBase = 0;
3450 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3451 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3452 {
3453 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3454 NewIoPortBase &= 0xfff0;
3455 }
3456
3457 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3458 AssertRC(rc);
3459 }
3460
3461 DEVACPI_UNLOCK(pDevIns, pThis);
3462 return rcStrict;
3463}
3464
3465/**
3466 * Attach a new CPU.
3467 *
3468 * @returns VBox status code.
3469 * @param pDevIns The device instance.
3470 * @param iLUN The logical unit which is being attached.
3471 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3472 *
3473 * @remarks This code path is not used during construction.
3474 */
3475static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3476{
3477 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3478 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3479 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3480
3481 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3482 ("Hot-plug flag is not set\n"),
3483 VERR_NOT_SUPPORTED);
3484 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3485
3486 /* Check if it was already attached */
3487 int rc = VINF_SUCCESS;
3488 DEVACPI_LOCK_R3(pDevIns, pThis);
3489 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3490 {
3491 PPDMIBASE IBaseTmp;
3492 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3493 if (RT_SUCCESS(rc))
3494 {
3495 /* Enable the CPU */
3496 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3497
3498 /*
3499 * Lock the CPU because we don't know if the guest will use it or not.
3500 * Prevents ejection while the CPU is still used
3501 */
3502 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3503 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3504 pThis->u32CpuEvent = iLUN;
3505
3506 /* Notify the guest */
3507 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3508 }
3509 }
3510 DEVACPI_UNLOCK(pDevIns, pThis);
3511 return rc;
3512}
3513
3514/**
3515 * Detach notification.
3516 *
3517 * @param pDevIns The device instance.
3518 * @param iLUN The logical unit which is being detached.
3519 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3520 */
3521static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3522{
3523 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3524
3525 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3526
3527 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3528 ("Hot-plug flag is not set\n"));
3529
3530 /* Check if it was already detached */
3531 DEVACPI_LOCK_R3(pDevIns, pThis);
3532 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3533 {
3534 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3535 {
3536 /* Disable the CPU */
3537 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3538 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3539 pThis->u32CpuEvent = iLUN;
3540
3541 /* Notify the guest */
3542 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3543 }
3544 else
3545 AssertMsgFailed(("CPU is still locked by the guest\n"));
3546 }
3547 DEVACPI_UNLOCK(pDevIns, pThis);
3548}
3549
3550/**
3551 * @interface_method_impl{PDMDEVREG,pfnResume}
3552 */
3553static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3554{
3555 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3556 if (pThis->fSetWakeupOnResume)
3557 {
3558 Log(("acpiResume: setting WAK_STS\n"));
3559 pThis->fSetWakeupOnResume = false;
3560 pThis->pm1a_sts |= WAK_STS;
3561 }
3562}
3563
3564/**
3565 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3566 */
3567static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3568{
3569 RT_NOREF(enmCtx);
3570 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3571 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3572 acpiR3PlantTables(pDevIns, pThis, pThisCC);
3573}
3574
3575/**
3576 * @interface_method_impl{PDMDEVREG,pfnReset}
3577 */
3578static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3579{
3580 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3581 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3582
3583 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3584 acpiSetIrq(pDevIns, 0);
3585
3586 PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3587 pThis->pm1a_en = 0;
3588 pThis->pm1a_sts = 0;
3589 pThis->pm1a_ctl = 0;
3590 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3591 pThis->uPmTimerVal = 0;
3592 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3593 pThis->uPmTimeOld = pThis->uPmTimerVal;
3594 pThis->uBatteryIndex = 0;
3595 pThis->uSystemInfoIndex = 0;
3596 pThis->gpe0_en = 0;
3597 pThis->gpe0_sts = 0;
3598 pThis->uSleepState = 0;
3599 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
3600
3601 /* Real device behavior is resetting only the PM controller state,
3602 * but we're additionally doing the job of the BIOS. */
3603 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
3604 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3605
3606 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3607 * state. Real device behavior is only the SMBus controller state reset,
3608 * but we're additionally doing the job of the BIOS. */
3609 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3610 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3611 acpiR3SMBusResetDevice(pThis);
3612}
3613
3614/**
3615 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3616 */
3617static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3618{
3619 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3620 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3621 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3622
3623 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3624 {
3625 if (pThisCC->apu8CustBin[i])
3626 {
3627 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
3628 pThisCC->apu8CustBin[i] = NULL;
3629 }
3630 }
3631 return VINF_SUCCESS;
3632}
3633
3634/**
3635 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3636 */
3637static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3638{
3639 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3640 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3641 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3642 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3643
3644 /*
3645 * Init data and set defaults.
3646 */
3647 /** @todo move more of the code up! */
3648
3649 pThisCC->pDevIns = pDevIns;
3650 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3651 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3652 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3653 pThis->u32CpuEventType = 0;
3654 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3655
3656 /* The first CPU can't be attached/detached */
3657 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3658 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3659
3660 /* IBase */
3661 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
3662 /* IACPIPort */
3663 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3664 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3665 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3666 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3667 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3668 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3669 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3670
3671 /*
3672 * Set the default critical section to NOP (related to the PM timer).
3673 */
3674 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3675 AssertRCReturn(rc, rc);
3676
3677 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3678 AssertRCReturn(rc, rc);
3679
3680 /*
3681 * Validate and read the configuration.
3682 */
3683 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
3684 "IOAPIC"
3685 "|NumCPUs"
3686 "|HpetEnabled"
3687 "|McfgEnabled"
3688 "|McfgBase"
3689 "|McfgLength"
3690 "|PciPref64Enabled"
3691 "|PciPref64LimitGB"
3692 "|SmcEnabled"
3693 "|FdcEnabled"
3694 "|ShowRtc"
3695 "|ShowCpu"
3696 "|NicPciAddress"
3697 "|AudioPciAddress"
3698 "|IocPciAddress"
3699 "|HostBusPciAddress"
3700 "|EnableSuspendToDisk"
3701 "|PowerS1Enabled"
3702 "|PowerS4Enabled"
3703 "|CpuHotPlug"
3704 "|AmlFilePath"
3705 "|Serial0IoPortBase"
3706 "|Serial1IoPortBase"
3707 "|Serial2IoPortBase"
3708 "|Serial3IoPortBase"
3709 "|Serial0Irq"
3710 "|Serial1Irq"
3711 "|Serial2Irq"
3712 "|Serial3Irq"
3713 "|AcpiOemId"
3714 "|AcpiCreatorId"
3715 "|AcpiCreatorRev"
3716 "|CustomTable"
3717 "|CustomTable0"
3718 "|CustomTable1"
3719 "|CustomTable2"
3720 "|CustomTable3"
3721 "|Parallel0IoPortBase"
3722 "|Parallel1IoPortBase"
3723 "|Parallel0Irq"
3724 "|Parallel1Irq"
3725 , "");
3726
3727 /* query whether we are supposed to present an IOAPIC */
3728 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3729 if (RT_FAILURE(rc))
3730 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
3731
3732 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3733 if (RT_FAILURE(rc))
3734 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3735
3736 /* query whether we are supposed to present an FDC controller */
3737 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3738 if (RT_FAILURE(rc))
3739 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
3740
3741 /* query whether we are supposed to present HPET */
3742 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
3743 if (RT_FAILURE(rc))
3744 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
3745 /* query MCFG configuration */
3746 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
3747 if (RT_FAILURE(rc))
3748 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
3749 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
3750 if (RT_FAILURE(rc))
3751 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
3752 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
3753
3754 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
3755 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
3756 if (RT_FAILURE(rc))
3757 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
3758
3759 /* query the limit of the the 64-bit prefetchable memory window */
3760 uint64_t u64PciPref64MaxGB;
3761 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
3762 if (RT_FAILURE(rc))
3763 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
3764 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
3765
3766 /* query whether we are supposed to present SMC */
3767 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
3768 if (RT_FAILURE(rc))
3769 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
3770
3771 /* query whether we are supposed to present RTC object */
3772 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
3773 if (RT_FAILURE(rc))
3774 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
3775
3776 /* query whether we are supposed to present CPU objects */
3777 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
3778 if (RT_FAILURE(rc))
3779 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
3780
3781 /* query primary NIC PCI address */
3782 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
3783 if (RT_FAILURE(rc))
3784 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
3785
3786 /* query primary NIC PCI address */
3787 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3788 if (RT_FAILURE(rc))
3789 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
3790
3791 /* query IO controller (southbridge) PCI address */
3792 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3793 if (RT_FAILURE(rc))
3794 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
3795
3796 /* query host bus controller PCI address */
3797 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3798 if (RT_FAILURE(rc))
3799 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3800
3801 /* query whether S1 power state should be exposed */
3802 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3803 if (RT_FAILURE(rc))
3804 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3805
3806 /* query whether S4 power state should be exposed */
3807 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3808 if (RT_FAILURE(rc))
3809 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3810
3811 /* query whether S1 power state should save the VM state */
3812 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3813 if (RT_FAILURE(rc))
3814 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3815
3816 /* query whether we are allow CPU hot plugging */
3817 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3818 if (RT_FAILURE(rc))
3819 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
3820
3821 /* query serial info */
3822 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3823 if (RT_FAILURE(rc))
3824 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
3825
3826 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3827 if (RT_FAILURE(rc))
3828 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3829
3830 /* Serial 1 is enabled, get config data */
3831 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3832 if (RT_FAILURE(rc))
3833 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
3834
3835 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3836 if (RT_FAILURE(rc))
3837 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3838
3839 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
3840 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
3841 if (RT_FAILURE(rc))
3842 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
3843
3844 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
3845 if (RT_FAILURE(rc))
3846 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
3847
3848 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
3849 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
3850 if (RT_FAILURE(rc))
3851 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
3852
3853 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
3854 if (RT_FAILURE(rc))
3855 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
3856 /*
3857 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
3858 * the corresponding parallel port is not enabled.
3859 */
3860 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
3861 if (RT_FAILURE(rc))
3862 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
3863
3864 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
3865 if (RT_FAILURE(rc))
3866 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
3867
3868 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
3869 if (RT_FAILURE(rc))
3870 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
3871
3872 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
3873 if (RT_FAILURE(rc))
3874 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
3875
3876 /* Try to attach the other CPUs */
3877 for (unsigned i = 1; i < pThis->cCpus; i++)
3878 {
3879 if (pThis->fCpuHotPlug)
3880 {
3881 PPDMIBASE IBaseTmp;
3882 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3883
3884 if (RT_SUCCESS(rc))
3885 {
3886 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3887 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3888 Log(("acpi: Attached CPU %u\n", i));
3889 }
3890 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3891 Log(("acpi: CPU %u not attached yet\n", i));
3892 else
3893 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3894 }
3895 else
3896 {
3897 /* CPU is always attached if hot-plug is not enabled. */
3898 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3899 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3900 }
3901 }
3902
3903 char szOemId[16];
3904 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
3905 if (RT_FAILURE(rc))
3906 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3907 size_t cchOemId = strlen(szOemId);
3908 if (cchOemId > 6)
3909 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3910 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3911 memcpy(pThis->au8OemId, szOemId, cchOemId);
3912
3913 char szCreatorId[16];
3914 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
3915 if (RT_FAILURE(rc))
3916 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3917 size_t cchCreatorId = strlen(szCreatorId);
3918 if (cchCreatorId > 4)
3919 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3920 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3921 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
3922
3923 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3924 if (RT_FAILURE(rc))
3925 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3926
3927 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3928
3929 /*
3930 * Load custom ACPI tables.
3931 */
3932 /* Total space available for custom ACPI tables */
3933 /** @todo define as appropriate, remove as a magic number, and document
3934 * limitation in product manual */
3935 uint32_t cbBufAvail = 3072;
3936 pThis->cCustTbls = 0;
3937
3938 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
3939 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
3940 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
3941 {
3942 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
3943
3944 /*
3945 * Get the custom table binary file name.
3946 */
3947 char *pszCustBinFile = NULL;
3948 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
3949 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
3950 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
3951 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3952 {
3953 rc = VINF_SUCCESS;
3954 pszCustBinFile = NULL;
3955 }
3956 else if (RT_FAILURE(rc))
3957 return PDMDEV_SET_ERROR(pDevIns, rc,
3958 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
3959 else if (!*pszCustBinFile)
3960 {
3961 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
3962 pszCustBinFile = NULL;
3963 }
3964
3965 /*
3966 * Determine the custom table binary size, open specified file in the process.
3967 */
3968 if (pszCustBinFile)
3969 {
3970 uint32_t idxCust = pThis->cCustTbls;
3971 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
3972 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
3973 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
3974 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
3975 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
3976 if (RT_FAILURE(rc))
3977 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
3978 cbBufAvail -= pThisCC->acbCustBin[idxCust];
3979
3980 /* Update custom OEM attributes based on custom table */
3981 /** @todo is it intended for custom tables to overwrite user provided values above? */
3982 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
3983 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
3984 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
3985 pThis->u32OemRevision = pTblHdr->u32OemRevision;
3986 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
3987 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
3988
3989 pThis->cCustTbls++;
3990 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
3991 }
3992 }
3993
3994 /* Set default PM port base */
3995 pThis->uPmIoPortBase = PM_PORT_BASE;
3996
3997 /* Set default SMBus port base */
3998 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
3999
4000 /*
4001 * FDC and SMC try to use the same non-shareable interrupt (6),
4002 * enable only one device.
4003 */
4004 if (pThis->fUseSmc)
4005 pThis->fUseFdc = false;
4006
4007 /*
4008 * Plant ACPI tables.
4009 */
4010 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4011 * au8RSDPPage here. However, there should be no harm in doing it
4012 * twice, so the lazy bird is taking the quick way out for now. */
4013 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4014 if (!GCPhysRsdp)
4015 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4016
4017 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4018 AssertRCReturn(rc, rc);
4019
4020 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4021 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4022 AssertRCReturn(rc, rc);
4023
4024 /*
4025 * Create the PM I/O ports. These can be unmapped and remapped.
4026 */
4027 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4028 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4029 AssertRCReturn(rc, rc);
4030 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4031 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4032 AssertRCReturn(rc, rc);
4033 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4034 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4035 AssertRCReturn(rc, rc);
4036 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4037 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4038 AssertRCReturn(rc, rc);
4039 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4040 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4041 AssertRCReturn(rc, rc);
4042 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4043 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4044 AssertRCReturn(rc, rc);
4045 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4046 AssertRCReturn(rc, rc);
4047
4048 /*
4049 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4050 */
4051 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4052 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4053 AssertRCReturn(rc, rc);
4054 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4055 AssertRCReturn(rc, rc);
4056
4057 /*
4058 * Create and map the fixed I/O ports.
4059 */
4060 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4061 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4062 AssertRCReturn(rc, rc);
4063#ifdef DEBUG_ACPI
4064 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4065 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4066 AssertRCReturn(rc, rc);
4067 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4068 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4069 AssertRCReturn(rc, rc);
4070#endif
4071 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4072 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4073 AssertRCReturn(rc, rc);
4074 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4075 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4076 AssertRCReturn(rc, rc);
4077 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4078 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4079 AssertRCReturn(rc, rc);
4080 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4081 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4082 AssertRCReturn(rc, rc);
4083 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4084 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4085 AssertRCReturn(rc, rc);
4086
4087 /*
4088 * Create the PM timer.
4089 */
4090 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4091 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer);
4092 AssertRCReturn(rc, rc);
4093
4094 rc = PDMDevHlpTimerLock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4095 AssertRCReturn(rc, rc);
4096 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4097 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4098 PDMDevHlpTimerUnlock(pDevIns, pThis->hPmTimer);
4099
4100 /*
4101 * Set up the PCI device.
4102 */
4103 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4104 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4105
4106 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4107 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4108
4109 /* See p. 50 of PIIX4 manual */
4110 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4111 PDMPciDevSetStatus(pPciDev, 0x0280);
4112
4113 PDMPciDevSetRevisionId(pPciDev, 0x08);
4114
4115 PDMPciDevSetClassProg(pPciDev, 0x00);
4116 PDMPciDevSetClassSub(pPciDev, 0x80);
4117 PDMPciDevSetClassBase(pPciDev, 0x06);
4118
4119 PDMPciDevSetHeaderType(pPciDev, 0x80);
4120
4121 PDMPciDevSetBIST(pPciDev, 0x00);
4122
4123 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4124 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4125
4126 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4127 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4128
4129 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4130 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4131 acpiR3SMBusResetDevice(pThis);
4132
4133 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4134 AssertRCReturn(rc, rc);
4135
4136 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4137 AssertRCReturn(rc, rc);
4138
4139 /*
4140 * Register the saved state.
4141 */
4142 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4143 AssertRCReturn(rc, rc);
4144
4145 /*
4146 * Get the corresponding connector interface
4147 */
4148 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4149 if (RT_SUCCESS(rc))
4150 {
4151 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4152 if (!pThisCC->pDrv)
4153 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4154 }
4155 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4156 {
4157 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4158 rc = VINF_SUCCESS;
4159 }
4160 else
4161 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4162
4163 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4164
4165 return rc;
4166}
4167
4168#else /* !IN_RING3 */
4169
4170/**
4171 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4172 */
4173static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4174{
4175 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4176 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4177
4178 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4179 AssertRCReturn(rc, rc);
4180
4181 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4182 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4183 AssertRCReturn(rc, rc);
4184
4185 return VINF_SUCCESS;
4186}
4187
4188#endif /* !IN_RING3 */
4189
4190/**
4191 * The device registration structure.
4192 */
4193const PDMDEVREG g_DeviceACPI =
4194{
4195 /* .u32Version = */ PDM_DEVREG_VERSION,
4196 /* .uReserved0 = */ 0,
4197 /* .szName = */ "acpi",
4198 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4199 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4200 /* .cMaxInstances = */ ~0U,
4201 /* .uSharedVersion = */ 42,
4202 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4203 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4204 /* .cbInstanceRC = */ 0,
4205 /* .cMaxPciDevices = */ 1,
4206 /* .cMaxMsixVectors = */ 0,
4207 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4208#if defined(IN_RING3)
4209 /* .pszRCMod = */ "VBoxDDRC.rc",
4210 /* .pszR0Mod = */ "VBoxDDR0.r0",
4211 /* .pfnConstruct = */ acpiR3Construct,
4212 /* .pfnDestruct = */ acpiR3Destruct,
4213 /* .pfnRelocate = */ NULL,
4214 /* .pfnMemSetup = */ acpiR3MemSetup,
4215 /* .pfnPowerOn = */ NULL,
4216 /* .pfnReset = */ acpiR3Reset,
4217 /* .pfnSuspend = */ NULL,
4218 /* .pfnResume = */ acpiR3Resume,
4219 /* .pfnAttach = */ acpiR3Attach,
4220 /* .pfnDetach = */ acpiR3Detach,
4221 /* .pfnQueryInterface = */ NULL,
4222 /* .pfnInitComplete = */ NULL,
4223 /* .pfnPowerOff = */ NULL,
4224 /* .pfnSoftReset = */ NULL,
4225 /* .pfnReserved0 = */ NULL,
4226 /* .pfnReserved1 = */ NULL,
4227 /* .pfnReserved2 = */ NULL,
4228 /* .pfnReserved3 = */ NULL,
4229 /* .pfnReserved4 = */ NULL,
4230 /* .pfnReserved5 = */ NULL,
4231 /* .pfnReserved6 = */ NULL,
4232 /* .pfnReserved7 = */ NULL,
4233#elif defined(IN_RING0)
4234 /* .pfnEarlyConstruct = */ NULL,
4235 /* .pfnConstruct = */ acpiRZConstruct,
4236 /* .pfnDestruct = */ NULL,
4237 /* .pfnFinalDestruct = */ NULL,
4238 /* .pfnRequest = */ NULL,
4239 /* .pfnReserved0 = */ NULL,
4240 /* .pfnReserved1 = */ NULL,
4241 /* .pfnReserved2 = */ NULL,
4242 /* .pfnReserved3 = */ NULL,
4243 /* .pfnReserved4 = */ NULL,
4244 /* .pfnReserved5 = */ NULL,
4245 /* .pfnReserved6 = */ NULL,
4246 /* .pfnReserved7 = */ NULL,
4247#elif defined(IN_RC)
4248 /* .pfnConstruct = */ acpiRZConstruct,
4249 /* .pfnReserved0 = */ NULL,
4250 /* .pfnReserved1 = */ NULL,
4251 /* .pfnReserved2 = */ NULL,
4252 /* .pfnReserved3 = */ NULL,
4253 /* .pfnReserved4 = */ NULL,
4254 /* .pfnReserved5 = */ NULL,
4255 /* .pfnReserved6 = */ NULL,
4256 /* .pfnReserved7 = */ NULL,
4257#else
4258# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4259#endif
4260 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4261};
4262
4263#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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