VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 82968

Last change on this file since 82968 was 82968, checked in by vboxsync, 5 years ago

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1/* $Id: DevACPI.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#include <iprt/file.h>
33#ifdef IN_RING3
34# include <iprt/alloc.h>
35# include <iprt/string.h>
36# include <iprt/uuid.h>
37#endif /* IN_RING3 */
38
39#include "VBoxDD.h"
40
41#ifdef LOG_ENABLED
42# define DEBUG_ACPI
43#endif
44
45
46/*********************************************************************************************************************************
47* Defined Constants And Macros *
48*********************************************************************************************************************************/
49#ifdef IN_RING3
50/** Locks the device state, ring-3 only. */
51# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
52 do { \
53 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
54 AssertRC(rcLock); \
55 } while (0)
56#endif
57/** Unlocks the device state (all contexts). */
58#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
59 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
60
61
62#define DEBUG_HEX 0x3000
63#define DEBUG_CHR 0x3001
64
65/** PM Base Address PCI config space offset */
66#define PMBA 0x40
67/** PM Miscellaneous Power Management PCI config space offset */
68#define PMREGMISC 0x80
69
70#define PM_TMR_FREQ 3579545
71/** Default base for PM PIIX4 device */
72#define PM_PORT_BASE 0x4000
73/* Port offsets in PM device */
74enum
75{
76 PM1a_EVT_OFFSET = 0x00,
77 PM1b_EVT_OFFSET = -1, /**< not supported */
78 PM1a_CTL_OFFSET = 0x04,
79 PM1b_CTL_OFFSET = -1, /**< not supported */
80 PM2_CTL_OFFSET = -1, /**< not supported */
81 PM_TMR_OFFSET = 0x08,
82 GPE0_OFFSET = 0x20,
83 GPE1_OFFSET = -1 /**< not supported */
84};
85
86/* Maximum supported number of custom ACPI tables */
87#define MAX_CUST_TABLES 4
88
89/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
90#define PM_TMR_32BIT
91
92#define BAT_INDEX 0x00004040
93#define BAT_DATA 0x00004044
94#define SYSI_INDEX 0x00004048
95#define SYSI_DATA 0x0000404c
96#define ACPI_RESET_BLK 0x00004050
97
98/* PM1x status register bits */
99#define TMR_STS RT_BIT(0)
100#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
101#define BM_STS RT_BIT(4)
102#define GBL_STS RT_BIT(5)
103#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
104#define PWRBTN_STS RT_BIT(8)
105#define SLPBTN_STS RT_BIT(9)
106#define RTC_STS RT_BIT(10)
107#define IGN_STS RT_BIT(11)
108#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
109#define WAK_STS RT_BIT(15)
110#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
111
112/* PM1x enable register bits */
113#define TMR_EN RT_BIT(0)
114#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
115#define GBL_EN RT_BIT(5)
116#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
117#define PWRBTN_EN RT_BIT(8)
118#define SLPBTN_EN RT_BIT(9)
119#define RTC_EN RT_BIT(10)
120#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
121#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
122#define IGN_EN 0
123
124/* PM1x control register bits */
125#define SCI_EN RT_BIT(0)
126#define BM_RLD RT_BIT(1)
127#define GBL_RLS RT_BIT(2)
128#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
129#define IGN_CNT RT_BIT(9)
130#define SLP_TYPx_SHIFT 10
131#define SLP_TYPx_MASK 7
132#define SLP_EN RT_BIT(13)
133#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
134#define RSR_CNT (RSR1_CNT | RSR2_CNT)
135
136#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
137
138enum
139{
140 BAT_STATUS_STATE = 0x00, /**< BST battery state */
141 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
142 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
143 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
144 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
145 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
146 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
147 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
148 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
149 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
150 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
151 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
152 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
153 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
154 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
155 BAT_INDEX_LAST
156};
157
158enum
159{
160 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
161 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
162};
163
164enum
165{
166 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
167 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
168 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
169 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
170 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
171 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
172 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
173 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
174 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
175 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
176 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
177 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
178 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
179 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
180 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
181 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
182 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
183 SYSTEM_INFO_INDEX_POWER_STATES = 17,
184 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
185 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
186 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
187 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
188 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
189 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
190 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
191 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
192 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
193 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
194 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
195 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
196 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
197 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
198 SYSTEM_INFO_INDEX_END = 32,
199 SYSTEM_INFO_INDEX_INVALID = 0x80,
200 SYSTEM_INFO_INDEX_VALID = 0x200
201};
202
203#define AC_OFFLINE 0
204#define AC_ONLINE 1
205
206#define BAT_TECH_PRIMARY 1
207#define BAT_TECH_SECONDARY 2
208
209#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
210#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
211#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
212#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
213#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
214
215/** SMBus Base Address PCI config space offset */
216#define SMBBA 0x90
217/** SMBus Host Configuration PCI config space offset */
218#define SMBHSTCFG 0xd2
219/** SMBus Slave Command PCI config space offset */
220#define SMBSLVC 0xd3
221/** SMBus Slave Shadow Port 1 PCI config space offset */
222#define SMBSHDW1 0xd4
223/** SMBus Slave Shadow Port 2 PCI config space offset */
224#define SMBSHDW2 0xd5
225/** SMBus Revision Identification PCI config space offset */
226#define SMBREV 0xd6
227
228#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
229#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
230#define SMBHSTCFG_INTRSEL_SMI 0
231#define SMBHSTCFG_INTRSEL_IRQ9 4
232#define SMBHSTCFG_INTRSEL_SHIFT 1
233
234/** Default base for SMBus PIIX4 device */
235#define SMB_PORT_BASE 0x4100
236
237/** SMBus Host Status Register I/O offset */
238#define SMBHSTSTS_OFF 0x0000
239/** SMBus Slave Status Register I/O offset */
240#define SMBSLVSTS_OFF 0x0001
241/** SMBus Host Count Register I/O offset */
242#define SMBHSTCNT_OFF 0x0002
243/** SMBus Host Command Register I/O offset */
244#define SMBHSTCMD_OFF 0x0003
245/** SMBus Host Address Register I/O offset */
246#define SMBHSTADD_OFF 0x0004
247/** SMBus Host Data 0 Register I/O offset */
248#define SMBHSTDAT0_OFF 0x0005
249/** SMBus Host Data 1 Register I/O offset */
250#define SMBHSTDAT1_OFF 0x0006
251/** SMBus Block Data Register I/O offset */
252#define SMBBLKDAT_OFF 0x0007
253/** SMBus Slave Control Register I/O offset */
254#define SMBSLVCNT_OFF 0x0008
255/** SMBus Shadow Command Register I/O offset */
256#define SMBSHDWCMD_OFF 0x0009
257/** SMBus Slave Event Register I/O offset */
258#define SMBSLVEVT_OFF 0x000a
259/** SMBus Slave Data Register I/O offset */
260#define SMBSLVDAT_OFF 0x000c
261
262#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
263#define SMBHSTSTS_INTER RT_BIT(1)
264#define SMBHSTSTS_DEV_ERR RT_BIT(2)
265#define SMBHSTSTS_BUS_ERR RT_BIT(3)
266#define SMBHSTSTS_FAILED RT_BIT(4)
267#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
268
269#define SMBSLVSTS_WRITE_MASK 0x3c
270
271#define SMBHSTCNT_INTEREN RT_BIT(0)
272#define SMBHSTCNT_KILL RT_BIT(1)
273#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
274#define SMBHSTCNT_START RT_BIT(6)
275#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
276
277#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
278
279
280/*********************************************************************************************************************************
281* Structures and Typedefs *
282*********************************************************************************************************************************/
283/**
284 * The shared ACPI device state.
285 */
286typedef struct ACPISTATE
287{
288 /** Critical section protecting the ACPI state. */
289 PDMCRITSECT CritSect;
290
291 uint16_t pm1a_en;
292 uint16_t pm1a_sts;
293 uint16_t pm1a_ctl;
294 /** Number of logical CPUs in guest */
295 uint16_t cCpus;
296
297 uint64_t u64PmTimerInitial;
298 /** The PM timer. */
299 TMTIMERHANDLE hPmTimer;
300 /* PM Timer last calculated value */
301 uint32_t uPmTimerVal;
302 uint32_t Alignment0;
303
304 uint32_t gpe0_en;
305 uint32_t gpe0_sts;
306
307 uint32_t uBatteryIndex;
308 uint32_t au8BatteryInfo[13];
309
310 uint32_t uSystemInfoIndex;
311 uint32_t u32Alignment0;
312 uint64_t u64RamSize;
313 /** Offset of the 64-bit prefetchable memory window. */
314 uint64_t u64PciPref64Min;
315 /** Limit of the 64-bit prefetchable memory window. */
316 uint64_t u64PciPref64Max;
317 /** The number of bytes below 4GB. */
318 uint32_t cbRamLow;
319
320 /** Current ACPI S* state. We support S0 and S5. */
321 uint32_t uSleepState;
322 uint8_t au8RSDPPage[0x1000];
323 /** This is a workaround for incorrect index field handling by Intels ACPICA.
324 * The system info _INI method writes to offset 0x200. We either observe a
325 * write request to index 0x80 (in that case we don't change the index) or a
326 * write request to offset 0x200 (in that case we divide the index value by
327 * 4. Note that the _STA method is sometimes called prior to the _INI method
328 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
329 * acpiR3BatIndexWrite() for handling this. */
330 uint8_t u8IndexShift;
331 /** provide an I/O-APIC */
332 uint8_t u8UseIOApic;
333 /** provide a floppy controller */
334 bool fUseFdc;
335 /** If High Precision Event Timer device should be supported */
336 bool fUseHpet;
337 /** If System Management Controller device should be supported */
338 bool fUseSmc;
339 /** the guest handled the last power button event */
340 bool fPowerButtonHandled;
341 /** If ACPI CPU device should be shown */
342 bool fShowCpu;
343 /** If Real Time Clock ACPI object to be shown */
344 bool fShowRtc;
345 /** I/O port address of PM device. */
346 RTIOPORT uPmIoPortBase;
347 /** I/O port address of SMBus device. */
348 RTIOPORT uSMBusIoPortBase;
349 /** Which CPU to check for the locked status. */
350 uint32_t idCpuLockCheck;
351 /** Array of flags of attached CPUs */
352 VMCPUSET CpuSetAttached;
353 /** Mask of locked CPUs (used by the guest). */
354 VMCPUSET CpuSetLocked;
355 /** The CPU event type. */
356 uint32_t u32CpuEventType;
357 /** The CPU id affected. */
358 uint32_t u32CpuEvent;
359 /** Flag whether CPU hot plugging is enabled. */
360 bool fCpuHotPlug;
361 /** If MCFG ACPI table shown to the guest */
362 bool fUseMcfg;
363 /** if the 64-bit prefetchable memory window is shown to the guest */
364 bool fPciPref64Enabled;
365 bool afAlignment1;
366 /** Primary NIC PCI address. */
367 uint32_t u32NicPciAddress;
368 /** HD Audio PCI address. */
369 uint32_t u32AudioPciAddress;
370 /** Primary NVMe controller PCI address. */
371 uint32_t u32NvmePciAddress;
372 /** Flag whether S1 power state is enabled. */
373 bool fS1Enabled;
374 /** Flag whether S4 power state is enabled. */
375 bool fS4Enabled;
376 /** Flag whether S1 triggers a state save. */
377 bool fSuspendToSavedState;
378 /** Flag whether to set WAK_STS on resume (restore included). */
379 bool fSetWakeupOnResume;
380 /** PCI address of the IO controller device. */
381 uint32_t u32IocPciAddress;
382 /** PCI address of the host bus controller device. */
383 uint32_t u32HbcPciAddress;
384
385 /** Physical address of PCI config space MMIO region */
386 uint64_t u64PciConfigMMioAddress;
387 /** Length of PCI config space MMIO region */
388 uint64_t u64PciConfigMMioLength;
389 /** Serial 0 IRQ number */
390 uint8_t uSerial0Irq;
391 /** Serial 1 IRQ number */
392 uint8_t uSerial1Irq;
393 /** Serial 2 IRQ number */
394 uint8_t uSerial2Irq;
395 /** Serial 3 IRQ number */
396 uint8_t uSerial3Irq;
397 /** Serial 0 IO port base */
398 RTIOPORT uSerial0IoPortBase;
399 /** Serial 1 IO port base */
400 RTIOPORT uSerial1IoPortBase;
401 /** Serial 2 IO port base */
402 RTIOPORT uSerial2IoPortBase;
403 /** Serial 3 IO port base */
404 RTIOPORT uSerial3IoPortBase;
405
406 /** @name Parallel port config bits
407 * @{ */
408 /** Parallel 0 IO port base */
409 RTIOPORT uParallel0IoPortBase;
410 /** Parallel 1 IO port base */
411 RTIOPORT uParallel1IoPortBase;
412 /** Parallel 0 IRQ number */
413 uint8_t uParallel0Irq;
414 /** Parallel 1 IRQ number */
415 uint8_t uParallel1Irq;
416 /** @} */
417
418 /** Number of custom ACPI tables */
419 uint8_t cCustTbls;
420 /** ACPI OEM ID */
421 uint8_t au8OemId[6];
422 /** ACPI Crator ID */
423 uint8_t au8CreatorId[4];
424 uint8_t abAlignment2[3];
425 /** ACPI Crator Rev */
426 uint32_t u32CreatorRev;
427 /** ACPI custom OEM Tab ID */
428 uint8_t au8OemTabId[8];
429 /** ACPI custom OEM Rev */
430 uint32_t u32OemRevision;
431
432 /** SMBus Host Status Register */
433 uint8_t u8SMBusHstSts;
434 /** SMBus Slave Status Register */
435 uint8_t u8SMBusSlvSts;
436 /** SMBus Host Control Register */
437 uint8_t u8SMBusHstCnt;
438 /** SMBus Host Command Register */
439 uint8_t u8SMBusHstCmd;
440 /** SMBus Host Address Register */
441 uint8_t u8SMBusHstAdd;
442 /** SMBus Host Data 0 Register */
443 uint8_t u8SMBusHstDat0;
444 /** SMBus Host Data 1 Register */
445 uint8_t u8SMBusHstDat1;
446 /** SMBus Slave Control Register */
447 uint8_t u8SMBusSlvCnt;
448 /** SMBus Slave Event Register */
449 uint16_t u16SMBusSlvEvt;
450 /** SMBus Slave Data Register */
451 uint16_t u16SMBusSlvDat;
452 /** SMBus Shadow Command Register */
453 uint8_t u8SMBusShdwCmd;
454 /** SMBus Host Block Index */
455 uint8_t u8SMBusBlkIdx;
456 uint8_t abAlignment3[2];
457 /** SMBus Host Block Data Buffer */
458 uint8_t au8SMBusBlkDat[32];
459
460 /** @todo DEBUGGING */
461 uint32_t uPmTimeOld;
462 uint32_t uPmTimeA;
463 uint32_t uPmTimeB;
464 uint32_t Alignment5;
465
466 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
467 * @{ */
468 IOMIOPORTHANDLE hIoPortPm1aEn;
469 IOMIOPORTHANDLE hIoPortPm1aSts;
470 IOMIOPORTHANDLE hIoPortPm1aCtl;
471 IOMIOPORTHANDLE hIoPortPmTimer;
472 IOMIOPORTHANDLE hIoPortGpe0En;
473 IOMIOPORTHANDLE hIoPortGpe0Sts;
474 /** @} */
475
476 /** SMBus I/O ports (mapped/unmapped). */
477 IOMIOPORTHANDLE hIoPortSMBus;
478
479 /** @name Fixed I/O ports
480 * @{ */
481 /** ACPI SMI I/O port. */
482 IOMIOPORTHANDLE hIoPortSmi;
483 /** ACPI Debug hex I/O port. */
484 IOMIOPORTHANDLE hIoPortDebugHex;
485 /** ACPI Debug char I/O port. */
486 IOMIOPORTHANDLE hIoPortDebugChar;
487 /** ACPI Battery status index I/O port. */
488 IOMIOPORTHANDLE hIoPortBatteryIndex;
489 /** ACPI Battery status data I/O port. */
490 IOMIOPORTHANDLE hIoPortBatteryData;
491 /** ACPI system info index I/O port. */
492 IOMIOPORTHANDLE hIoPortSysInfoIndex;
493 /** ACPI system info data I/O port. */
494 IOMIOPORTHANDLE hIoPortSysInfoData;
495 /** ACPI Reset I/O port. */
496 IOMIOPORTHANDLE hIoPortReset;
497 /** @} */
498
499} ACPISTATE;
500/** Pointer to the shared ACPI device state. */
501typedef ACPISTATE *PACPISTATE;
502
503
504/**
505 * The ring-3 ACPI device state.
506 */
507typedef struct ACPISTATER3
508{
509 /** ACPI port base interface. */
510 PDMIBASE IBase;
511 /** ACPI port interface. */
512 PDMIACPIPORT IACPIPort;
513 /** Pointer to the device instance so we can get our bearings from
514 * interface functions. */
515 PPDMDEVINSR3 pDevIns;
516
517 /** Pointer to the driver base interface. */
518 R3PTRTYPE(PPDMIBASE) pDrvBase;
519 /** Pointer to the driver connector interface. */
520 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
521
522 /** Custom ACPI tables binary data. */
523 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
524 /** The size of the custom table binary. */
525 uint64_t acbCustBin[MAX_CUST_TABLES];
526} ACPISTATER3;
527/** Pointer to the ring-3 ACPI device state. */
528typedef ACPISTATER3 *PACPISTATER3;
529
530
531#pragma pack(1)
532
533/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
534struct ACPIGENADDR
535{
536 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
537 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
538 uint8_t u8RegisterBitOffset; /**< bit offset of register */
539 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
540 uint64_t u64Address; /**< 64-bit address of register */
541};
542AssertCompileSize(ACPIGENADDR, 12);
543
544/** Root System Description Pointer */
545struct ACPITBLRSDP
546{
547 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
548 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
549 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
550 uint8_t u8Revision; /**< revision number, currently 2 */
551#define ACPI_REVISION 2 /**< ACPI 3.0 */
552 uint32_t u32RSDT; /**< phys addr of RSDT */
553 uint32_t u32Length; /**< bytes of this table */
554 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
555 uint8_t u8ExtChecksum; /**< checksum of entire table */
556 uint8_t u8Reserved[3]; /**< reserved */
557};
558AssertCompileSize(ACPITBLRSDP, 36);
559
560/** System Description Table Header */
561struct ACPITBLHEADER
562{
563 uint8_t au8Signature[4]; /**< table identifier */
564 uint32_t u32Length; /**< length of the table including header */
565 uint8_t u8Revision; /**< revision number */
566 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
567 uint8_t au8OemId[6]; /**< OEM-supplied string */
568 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
569 uint32_t u32OemRevision; /**< OEM-supplied revision number */
570 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
571 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
572};
573AssertCompileSize(ACPITBLHEADER, 36);
574
575/** Root System Description Table */
576struct ACPITBLRSDT
577{
578 ACPITBLHEADER header;
579 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
580};
581AssertCompileSize(ACPITBLRSDT, 40);
582
583/** Extended System Description Table */
584struct ACPITBLXSDT
585{
586 ACPITBLHEADER header;
587 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
588};
589AssertCompileSize(ACPITBLXSDT, 44);
590
591/** Fixed ACPI Description Table */
592struct ACPITBLFADT
593{
594 ACPITBLHEADER header;
595 uint32_t u32FACS; /**< phys. address of FACS */
596 uint32_t u32DSDT; /**< phys. address of DSDT */
597 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
598#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
599#define INT_MODEL_MULTIPLE_APIC 2
600 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
601 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
602#define SCI_INT 9
603 uint32_t u32SMICmd; /**< system port address of SMI command port */
604#define SMI_CMD 0x0000442e
605 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
606#define ACPI_ENABLE 0xa1
607 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
608#define ACPI_DISABLE 0xa0
609 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
610 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
611 state control responsibility */
612 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
613 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
614 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
615 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
616 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
617 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
618 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
619 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
620 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
621 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
622 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
623 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
624 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
625#define GPE0_BLK_LEN 2
626 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
627#define GPE1_BLK_LEN 0
628 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
629#define GPE1_BASE 0
630 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
631 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
632#define P_LVL2_LAT 101 /**< C2 state not supported */
633 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
634#define P_LVL3_LAT 1001 /**< C3 state not supported */
635 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
636 lines from any processors memory caches */
637#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
638 uint16_t u16FlushStride; /**< cache line width */
639#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
640 uint8_t u8DutyOffset;
641 uint8_t u8DutyWidth;
642 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
643 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
644 uint8_t u8Century; /**< RTC CMOS RAM index of century */
645 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
646#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
647 (COM too?) */
648#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
649#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
650#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
651#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
652 uint8_t u8Must0_0; /**< must be 0 */
653 uint32_t u32Flags; /**< fixed feature flags */
654#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
655#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
656#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
657#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
658#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
659#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
660#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
661#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
662#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
663#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
664#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
665#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
666#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
667#define FADT_FL_CPU_SW_SLP RT_BIT(13)
668#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
669#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
670#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
671#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
672#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
673#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
674
675/* PM Timer mask and msb */
676#ifndef PM_TMR_32BIT
677#define TMR_VAL_MSB 0x800000
678#define TMR_VAL_MASK 0xffffff
679#undef FADT_FL_TMR_VAL_EXT
680#define FADT_FL_TMR_VAL_EXT 0
681#else
682#define TMR_VAL_MSB 0x80000000
683#define TMR_VAL_MASK 0xffffffff
684#endif
685
686 /** Start of the ACPI 2.0 extension. */
687 ACPIGENADDR ResetReg; /**< ext addr of reset register */
688 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
689#define ACPI_RESET_REG_VAL 0x10
690 uint8_t au8Must0_1[3]; /**< must be 0 */
691 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
692 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
693 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
694 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
695 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
696 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
697 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
698 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
699 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
700 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
701};
702AssertCompileSize(ACPITBLFADT, 244);
703#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
704
705/** Firmware ACPI Control Structure */
706struct ACPITBLFACS
707{
708 uint8_t au8Signature[4]; /**< 'FACS' */
709 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
710 uint32_t u32HWSignature; /**< systems HW signature at last boot */
711 uint32_t u32FWVector; /**< address of waking vector */
712 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
713 uint32_t u32Flags; /**< FACS flags */
714 uint64_t u64X_FWVector; /**< 64-bit waking vector */
715 uint8_t u8Version; /**< version of this table */
716 uint8_t au8Reserved[31]; /**< zero */
717};
718AssertCompileSize(ACPITBLFACS, 64);
719
720/** Processor Local APIC Structure */
721struct ACPITBLLAPIC
722{
723 uint8_t u8Type; /**< 0 = LAPIC */
724 uint8_t u8Length; /**< 8 */
725 uint8_t u8ProcId; /**< processor ID */
726 uint8_t u8ApicId; /**< local APIC ID */
727 uint32_t u32Flags; /**< Flags */
728#define LAPIC_ENABLED 0x1
729};
730AssertCompileSize(ACPITBLLAPIC, 8);
731
732/** I/O APIC Structure */
733struct ACPITBLIOAPIC
734{
735 uint8_t u8Type; /**< 1 == I/O APIC */
736 uint8_t u8Length; /**< 12 */
737 uint8_t u8IOApicId; /**< I/O APIC ID */
738 uint8_t u8Reserved; /**< 0 */
739 uint32_t u32Address; /**< phys address to access I/O APIC */
740 uint32_t u32GSIB; /**< global system interrupt number to start */
741};
742AssertCompileSize(ACPITBLIOAPIC, 12);
743
744/** Interrupt Source Override Structure */
745struct ACPITBLISO
746{
747 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
748 uint8_t u8Length; /**< 10 */
749 uint8_t u8Bus; /**< Bus */
750 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
751 uint32_t u32GSI; /**< Global System Interrupt */
752 uint16_t u16Flags; /**< MPS INTI flags Global */
753};
754AssertCompileSize(ACPITBLISO, 10);
755#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
756
757/** HPET Descriptor Structure */
758struct ACPITBLHPET
759{
760 ACPITBLHEADER aHeader;
761 uint32_t u32Id; /**< hardware ID of event timer block
762 [31:16] PCI vendor ID of first timer block
763 [15] legacy replacement IRQ routing capable
764 [14] reserved
765 [13] COUNT_SIZE_CAP counter size
766 [12:8] number of comparators in first timer block
767 [7:0] hardware rev ID */
768 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
769 uint8_t u32Number; /**< sequence number starting at 0 */
770 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
771 lost interrupts while the counter is programmed
772 to operate in periodic mode. Unit: clock tick. */
773 uint8_t u8Attributes; /**< page protection and OEM attribute. */
774};
775AssertCompileSize(ACPITBLHPET, 56);
776
777/** MCFG Descriptor Structure */
778typedef struct ACPITBLMCFG
779{
780 ACPITBLHEADER aHeader;
781 uint64_t u64Reserved;
782} ACPITBLMCFG;
783AssertCompileSize(ACPITBLMCFG, 44);
784
785/** Number of such entries can be computed from the whole table length in header */
786typedef struct ACPITBLMCFGENTRY
787{
788 uint64_t u64BaseAddress;
789 uint16_t u16PciSegmentGroup;
790 uint8_t u8StartBus;
791 uint8_t u8EndBus;
792 uint32_t u32Reserved;
793} ACPITBLMCFGENTRY;
794AssertCompileSize(ACPITBLMCFGENTRY, 16);
795
796#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
797
798/** Custom Description Table */
799struct ACPITBLCUST
800{
801 ACPITBLHEADER header;
802 uint8_t au8Data[476];
803};
804AssertCompileSize(ACPITBLCUST, 512);
805
806
807#pragma pack()
808
809
810#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
811
812
813/*********************************************************************************************************************************
814* Internal Functions *
815*********************************************************************************************************************************/
816#ifdef IN_RING3
817static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
818#endif
819
820/* SCI, usually IRQ9 */
821DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
822{
823 PDMDevHlpPCISetIrq(pDevIns, 0, level);
824}
825
826DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
827{
828 return (pThis->pm1a_ctl & SCI_EN)
829 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
830}
831
832DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
833{
834 return !!(pThis->gpe0_en & pThis->gpe0_sts);
835}
836
837DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
838{
839 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
840 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
841 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
842 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
843 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
844}
845
846DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
847{
848 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
849}
850
851/**
852 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
853 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
854 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
855 * registers and trigger IRQs.
856 *
857 * Caller must hold the state lock.
858 *
859 * @param pDevIns The PDM device instance.
860 * @param pThis The ACPI shared instance data.
861 * @param sts The new PM1a.STS value.
862 * @param en The new PM1a.EN value.
863 */
864static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
865{
866 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
867
868 const bool old_level = acpiSCILevel(pDevIns, pThis);
869 pThis->pm1a_en = en;
870 pThis->pm1a_sts = sts;
871 const bool new_level = acpiSCILevel(pDevIns, pThis);
872
873 LogFunc(("old=%x new=%x\n", old_level, new_level));
874
875 if (new_level != old_level)
876 acpiSetIrq(pDevIns, new_level);
877}
878
879#ifdef IN_RING3
880
881/**
882 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
883 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
884 *
885 * Caller must hold the state lock.
886 *
887 * @param pDevIns The PDM device instance.
888 * @param pThis The ACPI shared instance data.
889 * @param sts The new GPE0.STS value.
890 * @param en The new GPE0.EN value.
891 */
892static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
893{
894 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
895
896 const bool old_level = acpiSCILevel(pDevIns, pThis);
897 pThis->gpe0_en = en;
898 pThis->gpe0_sts = sts;
899 const bool new_level = acpiSCILevel(pDevIns, pThis);
900
901 LogFunc(("old=%x new=%x\n", old_level, new_level));
902
903 if (new_level != old_level)
904 acpiSetIrq(pDevIns, new_level);
905}
906
907/**
908 * Used by acpiR3PM1aCtlWrite to power off the VM.
909 *
910 * @param pDevIns The device instance.
911 * @returns Strict VBox status code.
912 */
913static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
914{
915 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
916 AssertRC(VBOXSTRICTRC_VAL(rc));
917 return rc;
918}
919
920/**
921 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
922 *
923 * @param pDevIns The device instance.
924 * @param pThis The ACPI shared instance data.
925 * @returns Strict VBox status code.
926 */
927static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
928{
929 /* We must set WAK_STS on resume (includes restore) so the guest knows that
930 we've woken up and can continue executing code. The guest is probably
931 reading the PMSTS register in a loop to check this. */
932 VBOXSTRICTRC rc;
933 pThis->fSetWakeupOnResume = true;
934 if (pThis->fSuspendToSavedState)
935 {
936 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
937 if (rc != VERR_NOT_SUPPORTED)
938 AssertRC(VBOXSTRICTRC_VAL(rc));
939 else
940 {
941 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
942 rc = PDMDevHlpVMSuspend(pDevIns);
943 AssertRC(VBOXSTRICTRC_VAL(rc));
944 }
945 }
946 else
947 {
948 rc = PDMDevHlpVMSuspend(pDevIns);
949 AssertRC(VBOXSTRICTRC_VAL(rc));
950 }
951 return rc;
952}
953
954
955/**
956 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
957 */
958static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
959{
960 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
961 PPDMDEVINS pDevIns = pThisCC->pDevIns;
962 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
963 DEVACPI_LOCK_R3(pDevIns, pThis);
964
965 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
966 pThis->fPowerButtonHandled = false;
967 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
968
969 DEVACPI_UNLOCK(pDevIns, pThis);
970 return VINF_SUCCESS;
971}
972
973/**
974 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
975 */
976static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
977{
978 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
979 PPDMDEVINS pDevIns = pThisCC->pDevIns;
980 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
981 DEVACPI_LOCK_R3(pDevIns, pThis);
982
983 *pfHandled = pThis->fPowerButtonHandled;
984
985 DEVACPI_UNLOCK(pDevIns, pThis);
986 return VINF_SUCCESS;
987}
988
989/**
990 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
991 * Guest entered into G0 (working) or G1 (sleeping)}
992 */
993static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
994{
995 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
996 PPDMDEVINS pDevIns = pThisCC->pDevIns;
997 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
998 DEVACPI_LOCK_R3(pDevIns, pThis);
999
1000 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1001
1002 DEVACPI_UNLOCK(pDevIns, pThis);
1003 return VINF_SUCCESS;
1004}
1005
1006/**
1007 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1008 */
1009static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1010{
1011 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1012 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1013 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1014 DEVACPI_LOCK_R3(pDevIns, pThis);
1015
1016 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1017
1018 DEVACPI_UNLOCK(pDevIns, pThis);
1019 return VINF_SUCCESS;
1020}
1021
1022/**
1023 * Send an ACPI sleep button event.
1024 *
1025 * @returns VBox status code
1026 * @param pInterface Pointer to the interface structure containing the called function pointer.
1027 */
1028static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1029{
1030 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1031 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1032 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1033 DEVACPI_LOCK_R3(pDevIns, pThis);
1034
1035 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1036
1037 DEVACPI_UNLOCK(pDevIns, pThis);
1038 return VINF_SUCCESS;
1039}
1040
1041/**
1042 * Send an ACPI monitor hot-plug event.
1043 *
1044 * @returns VBox status code
1045 * @param pInterface Pointer to the interface structure containing the
1046 * called function pointer.
1047 */
1048static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1049{
1050 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1051 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1052 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1053 DEVACPI_LOCK_R3(pDevIns, pThis);
1054
1055 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1056
1057 DEVACPI_UNLOCK(pDevIns, pThis);
1058 return VINF_SUCCESS;
1059}
1060
1061/**
1062 * Send an ACPI battery status change event.
1063 *
1064 * @returns VBox status code
1065 * @param pInterface Pointer to the interface structure containing the
1066 * called function pointer.
1067 */
1068static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1069{
1070 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1071 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1072 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1073 DEVACPI_LOCK_R3(pDevIns, pThis);
1074
1075 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1076
1077 DEVACPI_UNLOCK(pDevIns, pThis);
1078 return VINF_SUCCESS;
1079}
1080
1081/**
1082 * Used by acpiR3PmTimer to re-arm the PM timer.
1083 *
1084 * The caller is expected to either hold the clock lock or to have made sure
1085 * the VM is resetting or loading state.
1086 *
1087 * @param pDevIns The device instance.
1088 * @param pThis The ACPI shared instance data.
1089 * @param uNow The current time.
1090 */
1091static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1092{
1093 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1094 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1095 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1096 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1097 Log(("acpi: uInterval = %RU64\n", uInterval));
1098}
1099
1100#endif /* IN_RING3 */
1101
1102/**
1103 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1104 *
1105 * The caller is expected to either hold the clock lock or to have made sure
1106 * the VM is resetting or loading state.
1107 *
1108 * @param pDevIns The PDM device instance.
1109 * @param pThis The ACPI instance
1110 * @param u64Now The current time
1111 */
1112static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1113{
1114 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1115 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1116 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1117
1118 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ,
1119 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1120 & TMR_VAL_MASK;
1121
1122 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1123 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1124}
1125
1126#ifdef IN_RING3
1127
1128/**
1129 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1130 */
1131static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1132{
1133 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1134 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1135 RT_NOREF(pTimer, pvUser);
1136
1137 DEVACPI_LOCK_R3(pDevIns, pThis);
1138 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1139 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1140 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1141 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1142 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1143 DEVACPI_UNLOCK(pDevIns, pThis);
1144
1145 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
1146}
1147
1148/**
1149 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1150 * acpiR3LoadState.
1151 *
1152 * @returns VINF_SUCCESS.
1153 * @param pThis The ACPI shared instance data.
1154 * @param pThisCC The ACPI instance data for ring-3.
1155 */
1156static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1157{
1158 uint32_t *p = pThis->au8BatteryInfo;
1159 bool fPresent; /* battery present? */
1160 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1161 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1162 uint32_t hostPresentRate; /* 0..1000 */
1163 int rc;
1164
1165 if (!pThisCC->pDrv)
1166 return VINF_SUCCESS;
1167 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1168 &hostBatteryState, &hostPresentRate);
1169 AssertRC(rc);
1170
1171 /* default values */
1172 p[BAT_STATUS_STATE] = hostBatteryState;
1173 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1174 : hostPresentRate * 50; /* mW */
1175 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1176 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1177
1178 /* did we get a valid battery state? */
1179 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1180 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1181 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1182 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1183
1184 return VINF_SUCCESS;
1185}
1186
1187/**
1188 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1189 * acpiR3LoadState.
1190 *
1191 * @returns VINF_SUCCESS.
1192 * @param pThis The ACPI shared instance data.
1193 */
1194static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1195{
1196 uint32_t *p = pThis->au8BatteryInfo;
1197
1198 p[BAT_INFO_UNITS] = 0; /* mWh */
1199 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1200 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1201 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1202 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1203 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1204 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1205 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1206 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1207
1208 return VINF_SUCCESS;
1209}
1210
1211/**
1212 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1213 *
1214 * @returns status mask or 0.
1215 * @param pThisCC The ACPI instance data for ring-3.
1216 */
1217static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1218{
1219 bool fPresent; /* battery present? */
1220 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1221 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1222 uint32_t hostPresentRate; /* 0..1000 */
1223 int rc;
1224
1225 if (!pThisCC->pDrv)
1226 return 0;
1227 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1228 &hostBatteryState, &hostPresentRate);
1229 AssertRC(rc);
1230
1231 return fPresent
1232 ? STA_DEVICE_PRESENT_MASK /* present */
1233 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1234 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1235 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1236 | STA_BATTERY_PRESENT_MASK /* battery is present */
1237 : 0; /* device not present */
1238}
1239
1240/**
1241 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1242 *
1243 * @returns status.
1244 * @param pThisCC The ACPI instance data for ring-3.
1245 */
1246static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1247{
1248 /* query the current power source from the host driver */
1249 if (!pThisCC->pDrv)
1250 return AC_ONLINE;
1251
1252 PDMACPIPOWERSOURCE ps;
1253 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1254 AssertRC(rc);
1255 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1256}
1257
1258/**
1259 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1260 */
1261static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1262{
1263 RT_NOREF(pvUser, offPort);
1264 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1265 if (cb != 4)
1266 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1267
1268 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1269 DEVACPI_LOCK_R3(pDevIns, pThis);
1270
1271 u32 >>= pThis->u8IndexShift;
1272 /* see comment at the declaration of u8IndexShift */
1273 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1274 {
1275 pThis->u8IndexShift = 2;
1276 u32 >>= 2;
1277 }
1278 Assert(u32 < BAT_INDEX_LAST);
1279 pThis->uBatteryIndex = u32;
1280
1281 DEVACPI_UNLOCK(pDevIns, pThis);
1282 return VINF_SUCCESS;
1283}
1284
1285/**
1286 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1287 */
1288static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1289{
1290 RT_NOREF(pvUser, offPort);
1291 if (cb != 4)
1292 return VERR_IOM_IOPORT_UNUSED;
1293
1294 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1295 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1296 DEVACPI_LOCK_R3(pDevIns, pThis);
1297
1298 VBOXSTRICTRC rc = VINF_SUCCESS;
1299 switch (pThis->uBatteryIndex)
1300 {
1301 case BAT_STATUS_STATE:
1302 acpiR3FetchBatteryStatus(pThis, pThisCC);
1303 RT_FALL_THRU();
1304 case BAT_STATUS_PRESENT_RATE:
1305 case BAT_STATUS_REMAINING_CAPACITY:
1306 case BAT_STATUS_PRESENT_VOLTAGE:
1307 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1308 break;
1309
1310 case BAT_INFO_UNITS:
1311 acpiR3FetchBatteryInfo(pThis);
1312 RT_FALL_THRU();
1313 case BAT_INFO_DESIGN_CAPACITY:
1314 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1315 case BAT_INFO_TECHNOLOGY:
1316 case BAT_INFO_DESIGN_VOLTAGE:
1317 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1318 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1319 case BAT_INFO_CAPACITY_GRANULARITY_1:
1320 case BAT_INFO_CAPACITY_GRANULARITY_2:
1321 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1322 break;
1323
1324 case BAT_DEVICE_STATUS:
1325 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1326 break;
1327
1328 case BAT_POWER_SOURCE:
1329 *pu32 = acpiR3GetPowerSource(pThisCC);
1330 break;
1331
1332 default:
1333 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1334 *pu32 = UINT32_MAX;
1335 break;
1336 }
1337
1338 DEVACPI_UNLOCK(pDevIns, pThis);
1339 return rc;
1340}
1341
1342/**
1343 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1344 */
1345static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1346{
1347 RT_NOREF(pvUser, offPort);
1348 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1349 if (cb != 4)
1350 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1351
1352 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1353 DEVACPI_LOCK_R3(pDevIns, pThis);
1354
1355 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1356 pThis->uSystemInfoIndex = u32;
1357 else
1358 {
1359 /* see comment at the declaration of u8IndexShift */
1360 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1361 {
1362 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1363 pThis->u8IndexShift = 2;
1364 }
1365
1366 u32 >>= pThis->u8IndexShift;
1367 Assert(u32 < SYSTEM_INFO_INDEX_END);
1368 pThis->uSystemInfoIndex = u32;
1369 }
1370
1371 DEVACPI_UNLOCK(pDevIns, pThis);
1372 return VINF_SUCCESS;
1373}
1374
1375/**
1376 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1377 */
1378static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1379{
1380 RT_NOREF(pvUser, offPort);
1381 if (cb != 4)
1382 return VERR_IOM_IOPORT_UNUSED;
1383
1384 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1385 DEVACPI_LOCK_R3(pDevIns, pThis);
1386
1387 VBOXSTRICTRC rc = VINF_SUCCESS;
1388 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1389 switch (uSystemInfoIndex)
1390 {
1391 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1392 *pu32 = pThis->cbRamLow;
1393 break;
1394
1395 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1396 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1397 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1398 break;
1399
1400 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1401 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1402 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1403 break;
1404
1405 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1406 *pu32 = pThis->u8UseIOApic;
1407 break;
1408
1409 case SYSTEM_INFO_INDEX_HPET_STATUS:
1410 *pu32 = pThis->fUseHpet
1411 ? ( STA_DEVICE_PRESENT_MASK
1412 | STA_DEVICE_ENABLED_MASK
1413 | STA_DEVICE_SHOW_IN_UI_MASK
1414 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1415 : 0;
1416 break;
1417
1418 case SYSTEM_INFO_INDEX_SMC_STATUS:
1419 *pu32 = pThis->fUseSmc
1420 ? ( STA_DEVICE_PRESENT_MASK
1421 | STA_DEVICE_ENABLED_MASK
1422 /* no need to show this device in the UI */
1423 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1424 : 0;
1425 break;
1426
1427 case SYSTEM_INFO_INDEX_FDC_STATUS:
1428 *pu32 = pThis->fUseFdc
1429 ? ( STA_DEVICE_PRESENT_MASK
1430 | STA_DEVICE_ENABLED_MASK
1431 | STA_DEVICE_SHOW_IN_UI_MASK
1432 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1433 : 0;
1434 break;
1435
1436 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1437 *pu32 = pThis->u32NicPciAddress;
1438 break;
1439
1440 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1441 *pu32 = pThis->u32AudioPciAddress;
1442 break;
1443
1444 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1445 *pu32 = pThis->u32NvmePciAddress;
1446 break;
1447
1448 case SYSTEM_INFO_INDEX_POWER_STATES:
1449 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1450 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1451 *pu32 |= RT_BIT(1);
1452 if (pThis->fS4Enabled)
1453 *pu32 |= RT_BIT(4);
1454 break;
1455
1456 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1457 *pu32 = pThis->u32IocPciAddress;
1458 break;
1459
1460 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1461 *pu32 = pThis->u32HbcPciAddress;
1462 break;
1463
1464 case SYSTEM_INFO_INDEX_PCI_BASE:
1465 /** @todo couldn't MCFG be in 64-bit range? */
1466 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1467 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1468 break;
1469
1470 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1471 /** @todo couldn't MCFG be in 64-bit range? */
1472 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1473 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1474 break;
1475
1476 case SYSTEM_INFO_INDEX_RTC_STATUS:
1477 *pu32 = pThis->fShowRtc
1478 ? ( STA_DEVICE_PRESENT_MASK
1479 | STA_DEVICE_ENABLED_MASK
1480 | STA_DEVICE_SHOW_IN_UI_MASK
1481 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1482 : 0;
1483 break;
1484
1485 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1486 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1487 {
1488 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1489 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1490 }
1491 else
1492 {
1493 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1494 pThis->idCpuLockCheck);
1495 /* Always return locked status just to be safe */
1496 *pu32 = 1;
1497 }
1498 break;
1499
1500 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1501 *pu32 = pThis->u32CpuEventType;
1502 break;
1503
1504 case SYSTEM_INFO_INDEX_CPU_EVENT:
1505 *pu32 = pThis->u32CpuEvent;
1506 break;
1507
1508 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1509 *pu32 = pThis->uSerial0IoPortBase;
1510 break;
1511
1512 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1513 *pu32 = pThis->uSerial0Irq;
1514 break;
1515
1516 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1517 *pu32 = pThis->uSerial1IoPortBase;
1518 break;
1519
1520 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1521 *pu32 = pThis->uSerial1Irq;
1522 break;
1523
1524 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1525 *pu32 = pThis->uSerial2IoPortBase;
1526 break;
1527
1528 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1529 *pu32 = pThis->uSerial2Irq;
1530 break;
1531
1532 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1533 *pu32 = pThis->uSerial3IoPortBase;
1534 break;
1535
1536 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1537 *pu32 = pThis->uSerial3Irq;
1538 break;
1539
1540 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1541 *pu32 = pThis->uParallel0IoPortBase;
1542 break;
1543
1544 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1545 *pu32 = pThis->uParallel0Irq;
1546 break;
1547
1548 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1549 *pu32 = pThis->uParallel1IoPortBase;
1550 break;
1551
1552 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1553 *pu32 = pThis->uParallel1Irq;
1554 break;
1555
1556 case SYSTEM_INFO_INDEX_END:
1557 /** @todo why isn't this setting any output value? */
1558 break;
1559
1560 /* Solaris 9 tries to read from this index */
1561 case SYSTEM_INFO_INDEX_INVALID:
1562 *pu32 = 0;
1563 break;
1564
1565 default:
1566 *pu32 = UINT32_MAX;
1567 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1568 break;
1569 }
1570
1571 DEVACPI_UNLOCK(pDevIns, pThis);
1572 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1573 return rc;
1574}
1575
1576/**
1577 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1578 */
1579static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1580{
1581 RT_NOREF(pvUser, offPort);
1582 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1583 if (cb != 4)
1584 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1585
1586 DEVACPI_LOCK_R3(pDevIns, pThis);
1587 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1588
1589 VBOXSTRICTRC rc = VINF_SUCCESS;
1590 switch (pThis->uSystemInfoIndex)
1591 {
1592 case SYSTEM_INFO_INDEX_INVALID:
1593 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1594 pThis->u8IndexShift = 0;
1595 break;
1596
1597 case SYSTEM_INFO_INDEX_VALID:
1598 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1599 pThis->u8IndexShift = 2;
1600 break;
1601
1602 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1603 pThis->idCpuLockCheck = u32;
1604 break;
1605
1606 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1607 if (u32 < pThis->cCpus)
1608 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1609 else
1610 LogRel(("ACPI: CPU %u does not exist\n", u32));
1611 break;
1612
1613 default:
1614 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1615 break;
1616 }
1617
1618 DEVACPI_UNLOCK(pDevIns, pThis);
1619 return rc;
1620}
1621
1622/**
1623 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1624 */
1625static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1626{
1627 RT_NOREF(offPort, pvUser);
1628 if (cb != 2)
1629 return VERR_IOM_IOPORT_UNUSED;
1630
1631 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1632 DEVACPI_LOCK_R3(pDevIns, pThis);
1633
1634 *pu32 = pThis->pm1a_en;
1635
1636 DEVACPI_UNLOCK(pDevIns, pThis);
1637 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1638 return VINF_SUCCESS;
1639}
1640
1641/**
1642 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1643 */
1644static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1645{
1646 RT_NOREF(offPort, pvUser);
1647 if (cb != 2 && cb != 4)
1648 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1649
1650 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1651 DEVACPI_LOCK_R3(pDevIns, pThis);
1652
1653 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1654 u32 &= ~(RSR_EN | IGN_EN);
1655 u32 &= 0xffff;
1656 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1657
1658 DEVACPI_UNLOCK(pDevIns, pThis);
1659 return VINF_SUCCESS;
1660}
1661
1662/**
1663 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1664 */
1665static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1666{
1667 RT_NOREF(offPort, pvUser);
1668 if (cb != 2)
1669 {
1670 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1671 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1672 }
1673
1674 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1675 DEVACPI_LOCK_R3(pDevIns, pThis);
1676
1677 *pu32 = pThis->pm1a_sts;
1678
1679 DEVACPI_UNLOCK(pDevIns, pThis);
1680 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1681 return VINF_SUCCESS;
1682}
1683
1684/**
1685 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1686 */
1687static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1688{
1689 RT_NOREF(offPort, pvUser);
1690 if (cb != 2 && cb != 4)
1691 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1692
1693 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1694 DEVACPI_LOCK_R3(pDevIns, pThis);
1695
1696 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1697 u32 &= 0xffff;
1698 if (u32 & PWRBTN_STS)
1699 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1700 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1701 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1702
1703 DEVACPI_UNLOCK(pDevIns, pThis);
1704 return VINF_SUCCESS;
1705}
1706
1707/**
1708 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1709 */
1710static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1711{
1712 RT_NOREF(offPort, pvUser);
1713 if (cb != 2)
1714 {
1715 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1716 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1717 }
1718
1719 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1720 DEVACPI_LOCK_R3(pDevIns, pThis);
1721
1722 *pu32 = pThis->pm1a_ctl;
1723
1724 DEVACPI_UNLOCK(pDevIns, pThis);
1725 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1726 return VINF_SUCCESS;
1727}
1728
1729/**
1730 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1731 */
1732static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1733{
1734 RT_NOREF(offPort, pvUser);
1735 if (cb != 2 && cb != 4)
1736 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1737
1738 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1739 DEVACPI_LOCK_R3(pDevIns, pThis);
1740
1741 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1742 u32 &= 0xffff;
1743 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1744
1745 VBOXSTRICTRC rc = VINF_SUCCESS;
1746 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1747 if (uSleepState != pThis->uSleepState)
1748 {
1749 pThis->uSleepState = uSleepState;
1750 switch (uSleepState)
1751 {
1752 case 0x00: /* S0 */
1753 break;
1754
1755 case 0x01: /* S1 */
1756 if (pThis->fS1Enabled)
1757 {
1758 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1759 rc = acpiR3DoSleep(pDevIns, pThis);
1760 break;
1761 }
1762 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1763 RT_FALL_THRU();
1764
1765 case 0x04: /* S4 */
1766 if (pThis->fS4Enabled)
1767 {
1768 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1769 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1770 break;
1771 }
1772 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1773 RT_FALL_THRU();
1774
1775 case 0x05: /* S5 */
1776 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1777 rc = acpiR3DoPowerOff(pDevIns);
1778 break;
1779
1780 default:
1781 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1782 break;
1783 }
1784 }
1785
1786 DEVACPI_UNLOCK(pDevIns, pThis);
1787 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1788 return rc;
1789}
1790
1791#endif /* IN_RING3 */
1792
1793/**
1794 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1795 *
1796 * @remarks The only I/O port currently implemented in all contexts.
1797 */
1798static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1799{
1800 RT_NOREF(offPort, pvUser);
1801 if (cb != 4)
1802 return VERR_IOM_IOPORT_UNUSED;
1803
1804 /*
1805 * We use the clock lock to serialize access to u64PmTimerInitial and to
1806 * make sure we get a reliable time from the clock
1807 * as well as and to prevent uPmTimerVal from being updated during read.
1808 */
1809 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1810 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1811 if (rc == VINF_SUCCESS)
1812 {
1813 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1814 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1815 *pu32 = pThis->uPmTimerVal;
1816
1817 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
1818
1819 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1820 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1821
1822#if 0
1823 /** @todo temporary: sanity check against running backwards */
1824 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1825 if (*pu32 - uOld >= 0x10000000)
1826 {
1827# if defined(IN_RING0)
1828 pThis->uPmTimeA = uOld;
1829 pThis->uPmTimeB = *pu32;
1830 return VERR_TM_TIMER_BAD_CLOCK;
1831# elif defined(IN_RING3)
1832 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1833# endif
1834 }
1835#endif
1836 }
1837 return rc;
1838}
1839
1840#ifdef IN_RING3
1841
1842/**
1843 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
1844 */
1845static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1846{
1847 RT_NOREF(offPort, pvUser);
1848 if (cb != 1)
1849 {
1850 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1851 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1852 }
1853
1854 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1855 DEVACPI_LOCK_R3(pDevIns, pThis);
1856
1857 *pu32 = pThis->gpe0_sts & 0xff;
1858
1859 DEVACPI_UNLOCK(pDevIns, pThis);
1860 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1861 return VINF_SUCCESS;
1862}
1863
1864/**
1865 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
1866 */
1867static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1868{
1869 RT_NOREF(offPort, pvUser);
1870 if (cb != 1)
1871 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1872
1873 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1874 DEVACPI_LOCK_R3(pDevIns, pThis);
1875
1876 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1877 u32 = pThis->gpe0_sts & ~u32;
1878 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1879
1880 DEVACPI_UNLOCK(pDevIns, pThis);
1881 return VINF_SUCCESS;
1882}
1883
1884/**
1885 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
1886 */
1887static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1888{
1889 RT_NOREF(offPort, pvUser);
1890 if (cb != 1)
1891 {
1892 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1893 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1894 }
1895
1896 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1897 DEVACPI_LOCK_R3(pDevIns, pThis);
1898
1899 *pu32 = pThis->gpe0_en & 0xff;
1900
1901 DEVACPI_UNLOCK(pDevIns, pThis);
1902 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1903 return VINF_SUCCESS;
1904}
1905
1906/**
1907 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
1908 */
1909static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1910{
1911 RT_NOREF(offPort, pvUser);
1912 if (cb != 1)
1913 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1914
1915 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1916 DEVACPI_LOCK_R3(pDevIns, pThis);
1917
1918 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1919 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
1920
1921 DEVACPI_UNLOCK(pDevIns, pThis);
1922 return VINF_SUCCESS;
1923}
1924
1925/**
1926 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
1927 */
1928static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1929{
1930 RT_NOREF(offPort, pvUser);
1931 Log(("acpiR3SmiWrite %#x\n", u32));
1932 if (cb != 1)
1933 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1934
1935 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1936 DEVACPI_LOCK_R3(pDevIns, pThis);
1937
1938 if (u32 == ACPI_ENABLE)
1939 pThis->pm1a_ctl |= SCI_EN;
1940 else if (u32 == ACPI_DISABLE)
1941 pThis->pm1a_ctl &= ~SCI_EN;
1942 else
1943 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1944
1945 DEVACPI_UNLOCK(pDevIns, pThis);
1946 return VINF_SUCCESS;
1947}
1948
1949/**
1950 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
1951 */
1952static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1953{
1954 RT_NOREF(offPort, pvUser);
1955 Log(("acpiR3ResetWrite: %#x\n", u32));
1956 NOREF(pvUser);
1957 if (cb != 1)
1958 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1959
1960 /* No state locking required. */
1961 VBOXSTRICTRC rc;
1962 if (u32 == ACPI_RESET_REG_VAL)
1963 {
1964 LogRel(("ACPI: Reset initiated by ACPI\n"));
1965 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
1966 }
1967 else
1968 {
1969 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1970 rc = VINF_SUCCESS;
1971 }
1972
1973 return rc;
1974}
1975
1976# ifdef DEBUG_ACPI
1977
1978/**
1979 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
1980 */
1981static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1982{
1983 NOREF(pvUser);
1984 switch (cb)
1985 {
1986 case 1:
1987 Log(("%#x\n", u32 & 0xff));
1988 break;
1989 case 2:
1990 Log(("%#6x\n", u32 & 0xffff));
1991 break;
1992 case 4:
1993 Log(("%#10x\n", u32));
1994 break;
1995 default:
1996 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1997 }
1998 return VINF_SUCCESS;
1999}
2000
2001/**
2002 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2003 */
2004static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2005{
2006 NOREF(pvUser);
2007 switch (cb)
2008 {
2009 case 1:
2010 Log(("%c", u32 & 0xff));
2011 break;
2012 default:
2013 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2014 }
2015 return VINF_SUCCESS;
2016}
2017
2018# endif /* DEBUG_ACPI */
2019
2020/**
2021 * @callback_method_impl{FNDBGFHANDLERDEV}
2022 */
2023static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2024{
2025 RT_NOREF(pszArgs);
2026 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2027 pHlp->pfnPrintf(pHlp,
2028 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2029}
2030
2031/**
2032 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2033 *
2034 * @param pDevIns The PDM device instance.
2035 * @param pThis The ACPI shared instance data.
2036 */
2037static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2038{
2039 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2040 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2041 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2042 pPciDev->abConfig[PMBA + 2] = 0x00;
2043 pPciDev->abConfig[PMBA + 3] = 0x00;
2044}
2045
2046/**
2047 * Used to calculate the value of a PM I/O port.
2048 *
2049 * @returns The actual I/O port value.
2050 * @param pThis The ACPI shared instance data.
2051 * @param offset The offset into the I/O space, or -1 if invalid.
2052 */
2053static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2054{
2055 Assert(pThis->uPmIoPortBase != 0);
2056
2057 if (offset == -1)
2058 return 0;
2059
2060 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2061}
2062
2063/**
2064 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2065 * timer and GPE0 I/O ports.
2066 *
2067 * @returns VBox status code.
2068 * @param pDevIns The device instance.
2069 * @param pThis The ACPI shared instance data.
2070 */
2071static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2072{
2073 if (pThis->uPmIoPortBase == 0)
2074 return VINF_SUCCESS;
2075
2076 int rc;
2077 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2078 AssertRCReturn(rc, rc);
2079 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2080 AssertRCReturn(rc, rc);
2081 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2082 AssertRCReturn(rc, rc);
2083 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2084 AssertRCReturn(rc, rc);
2085 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2086 AssertRCReturn(rc, rc);
2087 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2088
2089 return VINF_SUCCESS;
2090}
2091
2092/**
2093 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2094 * timer and GPE0 I/O ports.
2095 *
2096 * @returns VBox status code.
2097 * @param pDevIns The device instance.
2098 * @param pThis The ACPI shared instance data.
2099 */
2100static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2101{
2102 if (pThis->uPmIoPortBase != 0)
2103 {
2104 int rc;
2105 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2106 AssertRCReturn(rc, rc);
2107 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2108 AssertRCReturn(rc, rc);
2109 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2110 AssertRCReturn(rc, rc);
2111 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2112 AssertRCReturn(rc, rc);
2113 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2114 AssertRCReturn(rc, rc);
2115 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2116 AssertRCReturn(rc, rc);
2117 }
2118 return VINF_SUCCESS;
2119}
2120
2121/**
2122 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2123 * PM1a, PM timer and GPE0 ports.
2124 *
2125 * @returns VBox status code.
2126 *
2127 * @param pDevIns The device instance.
2128 * @param pThis The ACPI shared instance data.
2129 * @param pThisCC The ACPI instance data for ring-3.
2130 * @param NewIoPortBase The new base address of the I/O ports.
2131 */
2132static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2133{
2134 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2135 if (NewIoPortBase != pThis->uPmIoPortBase)
2136 {
2137 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2138 if (RT_FAILURE(rc))
2139 return rc;
2140
2141 pThis->uPmIoPortBase = NewIoPortBase;
2142
2143 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2144 if (RT_FAILURE(rc))
2145 return rc;
2146
2147 /* We have to update FADT table acccording to the new base */
2148 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2149 AssertRC(rc);
2150 if (RT_FAILURE(rc))
2151 return rc;
2152 }
2153
2154 return VINF_SUCCESS;
2155}
2156
2157/**
2158 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2159 */
2160static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2161{
2162 RT_NOREF(pvUser);
2163 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2164
2165 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2166 uint8_t off = offPort & 0x000f;
2167 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2168 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2169 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2170
2171 DEVACPI_LOCK_R3(pDevIns, pThis);
2172 switch (off)
2173 {
2174 case SMBHSTSTS_OFF:
2175 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2176 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2177 break;
2178 case SMBSLVSTS_OFF:
2179 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2180 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2181 break;
2182 case SMBHSTCNT_OFF:
2183 {
2184 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2185
2186 const bool old_level = acpiSCILevel(pDevIns, pThis);
2187 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2188 if (u32 & SMBHSTCNT_START)
2189 {
2190 /* Start, trigger error as this is a dummy implementation */
2191 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2192 }
2193 if (u32 & SMBHSTCNT_KILL)
2194 {
2195 /* Kill */
2196 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2197 }
2198 const bool new_level = acpiSCILevel(pDevIns, pThis);
2199
2200 LogFunc(("old=%x new=%x\n", old_level, new_level));
2201
2202 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2203 * needs to be implemented later if it ever becomes relevant. */
2204 if (new_level != old_level)
2205 acpiSetIrq(pDevIns, new_level);
2206 break;
2207 }
2208 case SMBHSTCMD_OFF:
2209 pThis->u8SMBusHstCmd = u32;
2210 break;
2211 case SMBHSTADD_OFF:
2212 pThis->u8SMBusHstAdd = u32;
2213 break;
2214 case SMBHSTDAT0_OFF:
2215 pThis->u8SMBusHstDat0 = u32;
2216 break;
2217 case SMBHSTDAT1_OFF:
2218 pThis->u8SMBusHstDat1 = u32;
2219 break;
2220 case SMBBLKDAT_OFF:
2221 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2222 pThis->u8SMBusBlkIdx++;
2223 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2224 break;
2225 case SMBSLVCNT_OFF:
2226 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2227 break;
2228 case SMBSHDWCMD_OFF:
2229 /* readonly register */
2230 break;
2231 case SMBSLVEVT_OFF:
2232 pThis->u16SMBusSlvEvt = u32;
2233 break;
2234 case SMBSLVDAT_OFF:
2235 /* readonly register */
2236 break;
2237 default:
2238 /* caught by the sanity check above */
2239 ;
2240 }
2241
2242 DEVACPI_UNLOCK(pDevIns, pThis);
2243 return VINF_SUCCESS;
2244}
2245
2246/**
2247 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2248 */
2249static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2250{
2251 RT_NOREF(pvUser);
2252 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2253
2254 VBOXSTRICTRC rc = VINF_SUCCESS;
2255 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2256 uint8_t const off = offPort & 0x000f;
2257 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2258 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2259 return VERR_IOM_IOPORT_UNUSED;
2260
2261 DEVACPI_LOCK_R3(pDevIns, pThis);
2262 switch (off)
2263 {
2264 case SMBHSTSTS_OFF:
2265 *pu32 = pThis->u8SMBusHstSts;
2266 break;
2267 case SMBSLVSTS_OFF:
2268 *pu32 = pThis->u8SMBusSlvSts;
2269 break;
2270 case SMBHSTCNT_OFF:
2271 pThis->u8SMBusBlkIdx = 0;
2272 *pu32 = pThis->u8SMBusHstCnt;
2273 break;
2274 case SMBHSTCMD_OFF:
2275 *pu32 = pThis->u8SMBusHstCmd;
2276 break;
2277 case SMBHSTADD_OFF:
2278 *pu32 = pThis->u8SMBusHstAdd;
2279 break;
2280 case SMBHSTDAT0_OFF:
2281 *pu32 = pThis->u8SMBusHstDat0;
2282 break;
2283 case SMBHSTDAT1_OFF:
2284 *pu32 = pThis->u8SMBusHstDat1;
2285 break;
2286 case SMBBLKDAT_OFF:
2287 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2288 pThis->u8SMBusBlkIdx++;
2289 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2290 break;
2291 case SMBSLVCNT_OFF:
2292 *pu32 = pThis->u8SMBusSlvCnt;
2293 break;
2294 case SMBSHDWCMD_OFF:
2295 *pu32 = pThis->u8SMBusShdwCmd;
2296 break;
2297 case SMBSLVEVT_OFF:
2298 *pu32 = pThis->u16SMBusSlvEvt;
2299 break;
2300 case SMBSLVDAT_OFF:
2301 *pu32 = pThis->u16SMBusSlvDat;
2302 break;
2303 default:
2304 /* caught by the sanity check above */
2305 rc = VERR_IOM_IOPORT_UNUSED;
2306 }
2307 DEVACPI_UNLOCK(pDevIns, pThis);
2308
2309 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2310 return rc;
2311}
2312
2313/**
2314 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2315 *
2316 * @param pDevIns The PDM device instance.
2317 * @param pThis The ACPI shared instance data.
2318 */
2319static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2320{
2321 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2322 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2323 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2324 pPciDev->abConfig[SMBBA+2] = 0x00;
2325 pPciDev->abConfig[SMBBA+3] = 0x00;
2326 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2327 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2328 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2329 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2330 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2331}
2332
2333/**
2334 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2335 *
2336 * @param pThis The ACPI shared instance data.
2337 */
2338static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2339{
2340 pThis->u8SMBusHstSts = 0x00;
2341 pThis->u8SMBusSlvSts = 0x00;
2342 pThis->u8SMBusHstCnt = 0x00;
2343 pThis->u8SMBusHstCmd = 0x00;
2344 pThis->u8SMBusHstAdd = 0x00;
2345 pThis->u8SMBusHstDat0 = 0x00;
2346 pThis->u8SMBusHstDat1 = 0x00;
2347 pThis->u8SMBusSlvCnt = 0x00;
2348 pThis->u8SMBusShdwCmd = 0x00;
2349 pThis->u16SMBusSlvEvt = 0x0000;
2350 pThis->u16SMBusSlvDat = 0x0000;
2351 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2352 pThis->u8SMBusBlkIdx = 0;
2353}
2354
2355/**
2356 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2357 *
2358 * @returns VBox status code.
2359 * @param pDevIns The device instance.
2360 * @param pThis The ACPI shared instance data.
2361 */
2362static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2363{
2364 if (pThis->uSMBusIoPortBase != 0)
2365 {
2366 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2367 AssertRCReturn(rc, rc);
2368 }
2369 return VINF_SUCCESS;
2370}
2371
2372/**
2373 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2374 *
2375 * @returns VBox status code.
2376 * @param pDevIns The device instance.
2377 * @param pThis The ACPI shared instance data.
2378 */
2379static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2380{
2381 if (pThis->uSMBusIoPortBase != 0)
2382 {
2383 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2384 AssertRCReturn(rc, rc);
2385 }
2386 return VINF_SUCCESS;
2387}
2388
2389/**
2390 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2391 * SMBus ports.
2392 *
2393 * @returns VBox status code.
2394 *
2395 * @param pDevIns The device instance.
2396 * @param pThis The ACPI shared instance data.
2397 * @param NewIoPortBase The new base address of the I/O ports.
2398 */
2399static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2400{
2401 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2402 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2403 {
2404 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2405 AssertRCReturn(rc, rc);
2406
2407 pThis->uSMBusIoPortBase = NewIoPortBase;
2408
2409 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2410 AssertRCReturn(rc, rc);
2411
2412#if 0 /* is there an FADT table entry for the SMBus base? */
2413 /* We have to update FADT table acccording to the new base */
2414 rc = acpiR3PlantTables(pThis);
2415 AssertRC(rc);
2416 if (RT_FAILURE(rc))
2417 return rc;
2418#endif
2419 }
2420
2421 return VINF_SUCCESS;
2422}
2423
2424
2425/**
2426 * Saved state structure description, version 4.
2427 */
2428static const SSMFIELD g_AcpiSavedStateFields4[] =
2429{
2430 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2431 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2432 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2433 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2434 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2435 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2436 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2437 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2438 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2439 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2440 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2441 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2442 SSMFIELD_ENTRY_TERM()
2443};
2444
2445/**
2446 * Saved state structure description, version 5.
2447 */
2448static const SSMFIELD g_AcpiSavedStateFields5[] =
2449{
2450 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2451 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2452 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2453 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2454 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2455 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2456 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2457 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2458 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2459 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2460 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2461 SSMFIELD_ENTRY_TERM()
2462};
2463
2464/**
2465 * Saved state structure description, version 6.
2466 */
2467static const SSMFIELD g_AcpiSavedStateFields6[] =
2468{
2469 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2470 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2471 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2472 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2473 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2474 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2475 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2476 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2477 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2478 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2479 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2480 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2481 SSMFIELD_ENTRY_TERM()
2482};
2483
2484/**
2485 * Saved state structure description, version 7.
2486 */
2487static const SSMFIELD g_AcpiSavedStateFields7[] =
2488{
2489 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2490 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2491 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2492 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2493 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2494 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2495 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2496 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2497 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2498 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2499 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2500 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2501 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2502 SSMFIELD_ENTRY_TERM()
2503};
2504
2505/**
2506 * Saved state structure description, version 8.
2507 */
2508static const SSMFIELD g_AcpiSavedStateFields8[] =
2509{
2510 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2511 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2512 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2513 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2514 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2515 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2516 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2517 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2518 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2519 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2520 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2521 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2522 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2523 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2524 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2525 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2526 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2527 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2528 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2529 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2530 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2531 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2532 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2533 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2534 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2535 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2536 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2537 SSMFIELD_ENTRY_TERM()
2538};
2539
2540/**
2541 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2542 */
2543static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2544{
2545 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2546 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2547 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2548}
2549
2550/**
2551 * @callback_method_impl{FNSSMDEVLOADEXEC}
2552 */
2553static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2554{
2555 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2556 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2557 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2558 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2559
2560 /*
2561 * Unmap PM I/O ports, will remap it with the actual base after state
2562 * successfully loaded.
2563 */
2564 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2565 AssertRCReturn(rc, rc);
2566
2567 /*
2568 * Unregister SMBus handlers, will register with actual base after state
2569 * successfully loaded.
2570 */
2571 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2572 AssertRCReturn(rc, rc);
2573 acpiR3SMBusResetDevice(pThis);
2574
2575 switch (uVersion)
2576 {
2577 case 4:
2578 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2579 break;
2580 case 5:
2581 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2582 break;
2583 case 6:
2584 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2585 break;
2586 case 7:
2587 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2588 break;
2589 case 8:
2590 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2591 break;
2592 default:
2593 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2594 break;
2595 }
2596 if (RT_SUCCESS(rc))
2597 {
2598 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2599 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2600 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2601 AssertRCReturn(rc, rc);
2602 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2603 AssertRCReturn(rc, rc);
2604 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2605 AssertRCReturn(rc, rc);
2606 rc = acpiR3FetchBatteryInfo(pThis);
2607 AssertRCReturn(rc, rc);
2608
2609 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2610 DEVACPI_LOCK_R3(pDevIns, pThis);
2611 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2612 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2613 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2614 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2615 DEVACPI_UNLOCK(pDevIns, pThis);
2616 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2617 }
2618 return rc;
2619}
2620
2621/**
2622 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2623 */
2624static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2625{
2626 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2627 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2628 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2629 return NULL;
2630}
2631
2632/**
2633 * Calculate the check sum for some ACPI data before planting it.
2634 *
2635 * All the bytes must add up to 0.
2636 *
2637 * @returns check sum.
2638 * @param pvSrc What to check sum.
2639 * @param cbData The amount of data to checksum.
2640 */
2641static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2642{
2643 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2644 uint8_t uSum = 0;
2645 for (size_t i = 0; i < cbData; ++i)
2646 uSum += pbSrc[i];
2647 return -uSum;
2648}
2649
2650/**
2651 * Prepare a ACPI table header.
2652 */
2653static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2654 const char au8Signature[4],
2655 uint32_t u32Length, uint8_t u8Revision)
2656{
2657 memcpy(header->au8Signature, au8Signature, 4);
2658 header->u32Length = RT_H2LE_U32(u32Length);
2659 header->u8Revision = u8Revision;
2660 memcpy(header->au8OemId, pThis->au8OemId, 6);
2661 memcpy(header->au8OemTabId, "VBOX", 4);
2662 memcpy(header->au8OemTabId+4, au8Signature, 4);
2663 header->u32OemRevision = RT_H2LE_U32(1);
2664 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2665 header->u32CreatorRev = pThis->u32CreatorRev;
2666}
2667
2668/**
2669 * Initialize a generic address structure (ACPIGENADDR).
2670 */
2671static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2672 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2673 uint8_t u8AccessSize, uint64_t u64Address)
2674{
2675 g->u8AddressSpaceId = u8AddressSpaceId;
2676 g->u8RegisterBitWidth = u8RegisterBitWidth;
2677 g->u8RegisterBitOffset = u8RegisterBitOffset;
2678 g->u8AccessSize = u8AccessSize;
2679 g->u64Address = RT_H2LE_U64(u64Address);
2680}
2681
2682/**
2683 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2684 */
2685DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2686{
2687 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2688}
2689
2690/**
2691 * Plant the Differentiated System Description Table (DSDT).
2692 */
2693static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2694{
2695 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2696}
2697
2698/**
2699 * Plant the Secondary System Description Table (SSDT).
2700 */
2701static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2702{
2703 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2704}
2705
2706/**
2707 * Plant the Firmware ACPI Control Structure (FACS).
2708 */
2709static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2710{
2711 ACPITBLFACS facs;
2712
2713 memset(&facs, 0, sizeof(facs));
2714 memcpy(facs.au8Signature, "FACS", 4);
2715 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2716 facs.u32HWSignature = RT_H2LE_U32(0);
2717 facs.u32FWVector = RT_H2LE_U32(0);
2718 facs.u32GlobalLock = RT_H2LE_U32(0);
2719 facs.u32Flags = RT_H2LE_U32(0);
2720 facs.u64X_FWVector = RT_H2LE_U64(0);
2721 facs.u8Version = 1;
2722
2723 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2724}
2725
2726/**
2727 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2728 */
2729static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2730 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2731{
2732 ACPITBLFADT fadt;
2733
2734 /* First the ACPI version 2+ version of the structure. */
2735 memset(&fadt, 0, sizeof(fadt));
2736 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2737 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2738 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2739 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2740 fadt.u8PreferredPMProfile = 0; /* unspecified */
2741 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2742 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2743 fadt.u8AcpiEnable = ACPI_ENABLE;
2744 fadt.u8AcpiDisable = ACPI_DISABLE;
2745 fadt.u8S4BIOSReq = 0;
2746 fadt.u8PStateCnt = 0;
2747 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2748 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2749 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2750 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2751 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2752 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2753 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2754 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2755 fadt.u8PM1EVTLEN = 4;
2756 fadt.u8PM1CTLLEN = 2;
2757 fadt.u8PM2CTLLEN = 0;
2758 fadt.u8PMTMLEN = 4;
2759 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2760 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2761 fadt.u8GPE1BASE = GPE1_BASE;
2762 fadt.u8CSTCNT = 0;
2763 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2764 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2765 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2766 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2767 fadt.u8DutyOffset = 0;
2768 fadt.u8DutyWidth = 0;
2769 fadt.u8DayAlarm = 0;
2770 fadt.u8MonAlarm = 0;
2771 fadt.u8Century = 0;
2772 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2773 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2774 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2775 | FADT_FL_FIX_RTC
2776 | FADT_FL_TMR_VAL_EXT
2777 | FADT_FL_RESET_REG_SUP);
2778
2779 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2780 if (pThis->fCpuHotPlug)
2781 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2782
2783 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2784 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2785 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2786 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2787 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2788 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2789 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2790 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2791 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2792 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2793 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2794 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2795 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2796 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2797
2798 /* Now the ACPI 1.0 version. */
2799 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2800 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2801 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2802 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2803 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2804}
2805
2806/**
2807 * Plant the root System Description Table.
2808 *
2809 * The RSDT and XSDT tables are basically identical. The only difference is 32
2810 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2811 * ACPI 2.0 and up.
2812 */
2813static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2814{
2815 ACPITBLRSDT *rsdt;
2816 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2817
2818 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2819 if (!rsdt)
2820 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2821
2822 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2823 for (unsigned int i = 0; i < nb_entries; ++i)
2824 {
2825 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2826 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2827 }
2828 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2829 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2830 RTMemFree(rsdt);
2831 return VINF_SUCCESS;
2832}
2833
2834/**
2835 * Plant the Extended System Description Table.
2836 */
2837static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2838{
2839 ACPITBLXSDT *xsdt;
2840 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2841 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
2842 if (!xsdt)
2843 return VERR_NO_TMP_MEMORY;
2844
2845 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
2846
2847 if (pThis->cCustTbls > 0)
2848 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2849
2850 for (unsigned int i = 0; i < nb_entries; ++i)
2851 {
2852 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2853 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2854 }
2855 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
2856 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
2857
2858 RTMemFree(xsdt);
2859 return VINF_SUCCESS;
2860}
2861
2862/**
2863 * Plant the Root System Description Pointer (RSDP).
2864 */
2865static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2866{
2867 memset(rsdp, 0, sizeof(*rsdp));
2868
2869 /* ACPI 1.0 part (RSDT) */
2870 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2871 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2872 rsdp->u8Revision = ACPI_REVISION;
2873 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2874 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2875
2876 /* ACPI 2.0 part (XSDT) */
2877 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2878 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2879 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2880}
2881
2882/**
2883 * Multiple APIC Description Table.
2884 *
2885 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2886 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2887 * use regular C structure and proxy to raw memory instead.
2888 */
2889class AcpiTableMadt
2890{
2891 /**
2892 * All actual data stored in dynamically allocated memory pointed by this field.
2893 */
2894 uint8_t *m_pbData;
2895 /**
2896 * Number of CPU entries in this MADT.
2897 */
2898 uint32_t m_cCpus;
2899
2900 /**
2901 * Number of interrupt overrides.
2902 */
2903 uint32_t m_cIsos;
2904
2905public:
2906 /**
2907 * Address of ACPI header
2908 */
2909 inline ACPITBLHEADER *header_addr(void) const
2910 {
2911 return (ACPITBLHEADER *)m_pbData;
2912 }
2913
2914 /**
2915 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2916 * although address is the same for all of them.
2917 */
2918 inline uint32_t *u32LAPIC_addr(void) const
2919 {
2920 return (uint32_t *)(header_addr() + 1);
2921 }
2922
2923 /**
2924 * Address of APIC flags
2925 */
2926 inline uint32_t *u32Flags_addr(void) const
2927 {
2928 return (uint32_t *)(u32LAPIC_addr() + 1);
2929 }
2930
2931 /**
2932 * Address of ISO description
2933 */
2934 inline ACPITBLISO *ISO_addr(void) const
2935 {
2936 return (ACPITBLISO *)(u32Flags_addr() + 1);
2937 }
2938
2939 /**
2940 * Address of per-CPU LAPIC descriptions
2941 */
2942 inline ACPITBLLAPIC *LApics_addr(void) const
2943 {
2944 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2945 }
2946
2947 /**
2948 * Address of IO APIC description
2949 */
2950 inline ACPITBLIOAPIC *IOApic_addr(void) const
2951 {
2952 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2953 }
2954
2955 /**
2956 * Size of MADT.
2957 * Note that this function assumes IOApic to be the last field in structure.
2958 */
2959 inline uint32_t size(void) const
2960 {
2961 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2962 }
2963
2964 /**
2965 * Raw data of MADT.
2966 */
2967 inline const uint8_t *data(void) const
2968 {
2969 return m_pbData;
2970 }
2971
2972 /**
2973 * Size of MADT for given ACPI config, useful to compute layout.
2974 */
2975 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
2976 {
2977 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2978 }
2979
2980 /*
2981 * Constructor, only works in Ring 3, doesn't look like a big deal.
2982 */
2983 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2984 {
2985 m_cCpus = cCpus;
2986 m_cIsos = cIsos;
2987 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2988 uint32_t cb = size();
2989 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2990 }
2991
2992 ~AcpiTableMadt()
2993 {
2994 RTMemFree(m_pbData);
2995 }
2996};
2997
2998
2999/**
3000 * Plant the Multiple APIC Description Table (MADT).
3001 *
3002 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3003 *
3004 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3005 */
3006static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3007{
3008 uint16_t cpus = pThis->cCpus;
3009 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3010
3011 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3012
3013 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3014 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3015
3016 /* LAPICs records */
3017 ACPITBLLAPIC* lapic = madt.LApics_addr();
3018 for (uint16_t i = 0; i < cpus; i++)
3019 {
3020 lapic->u8Type = 0;
3021 lapic->u8Length = sizeof(ACPITBLLAPIC);
3022 lapic->u8ProcId = i;
3023 /** Must match numbering convention in MPTABLES */
3024 lapic->u8ApicId = i;
3025 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3026 lapic++;
3027 }
3028
3029 /* IO-APIC record */
3030 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3031 ioapic->u8Type = 1;
3032 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3033 /** Must match MP tables ID */
3034 ioapic->u8IOApicId = cpus;
3035 ioapic->u8Reserved = 0;
3036 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3037 ioapic->u32GSIB = RT_H2LE_U32(0);
3038
3039 /* Interrupt Source Overrides */
3040 /* Flags:
3041 bits[3:2]:
3042 00 conforms to the bus
3043 01 edge-triggered
3044 10 reserved
3045 11 level-triggered
3046 bits[1:0]
3047 00 conforms to the bus
3048 01 active-high
3049 10 reserved
3050 11 active-low */
3051 /* If changing, also update PDMIsaSetIrq() and MPS */
3052 ACPITBLISO* isos = madt.ISO_addr();
3053 /* Timer interrupt rule IRQ0 to GSI2 */
3054 isos[0].u8Type = 2;
3055 isos[0].u8Length = sizeof(ACPITBLISO);
3056 isos[0].u8Bus = 0; /* Must be 0 */
3057 isos[0].u8Source = 0; /* IRQ0 */
3058 isos[0].u32GSI = 2; /* connected to pin 2 */
3059 isos[0].u16Flags = 0; /* conform to the bus */
3060
3061 /* ACPI interrupt rule - IRQ9 to GSI9 */
3062 isos[1].u8Type = 2;
3063 isos[1].u8Length = sizeof(ACPITBLISO);
3064 isos[1].u8Bus = 0; /* Must be 0 */
3065 isos[1].u8Source = 9; /* IRQ9 */
3066 isos[1].u32GSI = 9; /* connected to pin 9 */
3067 isos[1].u16Flags = 0xf; /* active low, level triggered */
3068 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3069
3070 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3071 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3072}
3073
3074/**
3075 * Plant the High Performance Event Timer (HPET) descriptor.
3076 */
3077static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3078{
3079 ACPITBLHPET hpet;
3080
3081 memset(&hpet, 0, sizeof(hpet));
3082
3083 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3084 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3085 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3086 0 /* Memory address space */,
3087 64 /* Register bit width */,
3088 0 /* Bit offset */,
3089 0, /* Register access size, is it correct? */
3090 0xfed00000 /* Address */);
3091
3092 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3093 hpet.u32Number = 0;
3094 hpet.u32MinTick = 4096;
3095 hpet.u8Attributes = 0;
3096
3097 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3098
3099 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3100}
3101
3102
3103/**
3104 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3105 * descriptor.
3106 *
3107 * @param pDevIns The device instance.
3108 * @param pThis The ACPI shared instance data.
3109 * @param GCPhysDst Where to plant it.
3110 */
3111static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3112{
3113 struct
3114 {
3115 ACPITBLMCFG hdr;
3116 ACPITBLMCFGENTRY entry;
3117 } tbl;
3118 uint8_t u8StartBus = 0;
3119 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3120
3121 RT_ZERO(tbl);
3122
3123 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3124 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3125 tbl.entry.u8StartBus = u8StartBus;
3126 tbl.entry.u8EndBus = u8EndBus;
3127 // u16PciSegmentGroup must match _SEG in ACPI table
3128
3129 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3130
3131 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3132}
3133
3134/**
3135 * Used by acpiR3PlantTables and acpiConstruct.
3136 *
3137 * @returns Guest memory address.
3138 */
3139static uint32_t apicR3FindRsdpSpace(void)
3140{
3141 return 0xe0000;
3142}
3143
3144/**
3145 * Called by acpiR3Construct to read and allocate a custom ACPI table
3146 *
3147 * @param pDevIns The device instance.
3148 * @param ppu8CustBin Address to receive the address of the table
3149 * @param pcbCustBin Address to receive the size of the the table.
3150 * @param pszCustBinFile
3151 * @param cbBufAvail Maximum space in bytes available for the custom
3152 * table (including header).
3153 */
3154static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3155 char *pszCustBinFile, uint32_t cbBufAvail)
3156{
3157 RTFILE FileCUSTBin;
3158 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3159 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3160 if (RT_SUCCESS(rc))
3161 {
3162 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3163 if (RT_SUCCESS(rc))
3164 {
3165 /* The following checks should be in sync the AssertReleaseMsg's below. */
3166 if ( *pcbCustBin > cbBufAvail
3167 || *pcbCustBin < sizeof(ACPITBLHEADER))
3168 rc = VERR_TOO_MUCH_DATA;
3169
3170 /*
3171 * Allocate buffer for the custom table binary data.
3172 */
3173 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3174 if (*ppu8CustBin)
3175 {
3176 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3177 if (RT_FAILURE(rc))
3178 {
3179 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3180 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3181 *ppu8CustBin = NULL;
3182 }
3183 }
3184 else
3185 {
3186 rc = VERR_NO_MEMORY;
3187 }
3188 RTFileClose(FileCUSTBin);
3189 }
3190 }
3191 return rc;
3192}
3193
3194/**
3195 * Create the ACPI tables in guest memory.
3196 */
3197static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3198{
3199 int rc;
3200 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3201 RTGCPHYS32 GCPhysHpet = 0;
3202 RTGCPHYS32 GCPhysApic = 0;
3203 RTGCPHYS32 GCPhysSsdt = 0;
3204 RTGCPHYS32 GCPhysMcfg = 0;
3205 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3206 uint32_t addend = 0;
3207 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3208 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3209 uint32_t cAddr;
3210 uint32_t iMadt = 0;
3211 uint32_t iHpet = 0;
3212 uint32_t iSsdt = 0;
3213 uint32_t iMcfg = 0;
3214 uint32_t iCust = 0;
3215 size_t cbRsdt = sizeof(ACPITBLHEADER);
3216 size_t cbXsdt = sizeof(ACPITBLHEADER);
3217
3218 cAddr = 1; /* FADT */
3219 if (pThis->u8UseIOApic)
3220 iMadt = cAddr++; /* MADT */
3221
3222 if (pThis->fUseHpet)
3223 iHpet = cAddr++; /* HPET */
3224
3225 if (pThis->fUseMcfg)
3226 iMcfg = cAddr++; /* MCFG */
3227
3228 if (pThis->cCustTbls > 0)
3229 {
3230 iCust = cAddr; /* CUST */
3231 cAddr += pThis->cCustTbls;
3232 }
3233
3234 iSsdt = cAddr++; /* SSDT */
3235
3236 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3237 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3238
3239 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3240 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3241
3242 /*
3243 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3244 * The latter starts never below 4G.
3245 */
3246 PVM pVM = PDMDevHlpGetVM(pDevIns);
3247 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3248 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3249
3250 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3251 if (pThis->fPciPref64Enabled)
3252 {
3253 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3254 if (pThis->u64PciPref64Max > u64PciPref64Min)
3255 {
3256 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3257 pThis->u64PciPref64Min = u64PciPref64Min;
3258 LogRel(("ACPI: enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3259 u64PciPref64Min, pThis->u64PciPref64Max-1));
3260 }
3261 else
3262 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3263 u64PciPref64Min, pThis->u64PciPref64Max-1));
3264 }
3265 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3266 {
3267 /* Note: This is also enforced by DevPcBios.cpp. */
3268 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3269 cbBelow4GB = UINT32_C(0xfe000000);
3270 }
3271 pThis->cbRamLow = cbBelow4GB;
3272
3273 GCPhysCur = 0;
3274 GCPhysRsdt = GCPhysCur;
3275
3276 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3277 GCPhysXsdt = GCPhysCur;
3278
3279 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3280 GCPhysFadtAcpi1 = GCPhysCur;
3281
3282 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3283 GCPhysFadtAcpi2 = GCPhysCur;
3284
3285 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3286 GCPhysFacs = GCPhysCur;
3287
3288 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3289 if (pThis->u8UseIOApic)
3290 {
3291 GCPhysApic = GCPhysCur;
3292 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3293 }
3294 if (pThis->fUseHpet)
3295 {
3296 GCPhysHpet = GCPhysCur;
3297 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3298 }
3299 if (pThis->fUseMcfg)
3300 {
3301 GCPhysMcfg = GCPhysCur;
3302 /* Assume one entry */
3303 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3304 }
3305
3306 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3307 {
3308 aGCPhysCust[i] = GCPhysCur;
3309 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3310 }
3311
3312 void *pvSsdtCode = NULL;
3313 size_t cbSsdt = 0;
3314 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3315 if (RT_FAILURE(rc))
3316 return rc;
3317
3318 GCPhysSsdt = GCPhysCur;
3319 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3320
3321 GCPhysDsdt = GCPhysCur;
3322
3323 void *pvDsdtCode = NULL;
3324 size_t cbDsdt = 0;
3325 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3326 if (RT_FAILURE(rc))
3327 return rc;
3328
3329 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3330
3331 if (GCPhysCur > 0x10000)
3332 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3333 N_("Error: ACPI tables bigger than 64KB"));
3334
3335 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3336 addend = pThis->cbRamLow - 0x10000;
3337 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3338 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3339 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3340 if (pThis->u8UseIOApic)
3341 Log((" MADT 0x%08X", GCPhysApic + addend));
3342 if (pThis->fUseHpet)
3343 Log((" HPET 0x%08X", GCPhysHpet + addend));
3344 if (pThis->fUseMcfg)
3345 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3346 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3347 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3348 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3349 Log(("\n"));
3350
3351 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3352 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3353 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3354 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3355 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3356
3357 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3358 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3359 if (pThis->u8UseIOApic)
3360 {
3361 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3362 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3363 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3364 }
3365 if (pThis->fUseHpet)
3366 {
3367 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3368 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3369 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3370 }
3371 if (pThis->fUseMcfg)
3372 {
3373 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3374 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3375 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3376 }
3377 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3378 {
3379 Assert(i < MAX_CUST_TABLES);
3380 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3381 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3382 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3383 uint8_t* pSig = pThisCC->apu8CustBin[i];
3384 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3385 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3386 }
3387
3388 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3389 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3390 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3391 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3392
3393 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3394 if (RT_FAILURE(rc))
3395 return rc;
3396 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3397}
3398
3399/**
3400 * @callback_method_impl{FNPCICONFIGREAD}
3401 */
3402static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3403 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3404{
3405 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3406 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3407 return rcStrict;
3408}
3409
3410/**
3411 * @callback_method_impl{FNPCICONFIGWRITE}
3412 */
3413static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3414 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3415{
3416 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3417 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3418
3419 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3420 DEVACPI_LOCK_R3(pDevIns, pThis);
3421
3422 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3423 {
3424 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3425 u32Value = SCI_INT;
3426 }
3427
3428 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3429
3430 /* Assume that the base address is only changed when the corresponding
3431 * hardware functionality is disabled. The IO region is mapped when the
3432 * functionality is enabled by the guest. */
3433
3434 if (uAddress == PMREGMISC)
3435 {
3436 RTIOPORT NewIoPortBase = 0;
3437 /* Check Power Management IO Space Enable (PMIOSE) bit */
3438 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3439 {
3440 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3441 NewIoPortBase &= 0xffc0;
3442 }
3443
3444 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
3445 AssertRC(rc);
3446 }
3447
3448 if (uAddress == SMBHSTCFG)
3449 {
3450 RTIOPORT NewIoPortBase = 0;
3451 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3452 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3453 {
3454 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3455 NewIoPortBase &= 0xfff0;
3456 }
3457
3458 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3459 AssertRC(rc);
3460 }
3461
3462 DEVACPI_UNLOCK(pDevIns, pThis);
3463 return rcStrict;
3464}
3465
3466/**
3467 * Attach a new CPU.
3468 *
3469 * @returns VBox status code.
3470 * @param pDevIns The device instance.
3471 * @param iLUN The logical unit which is being attached.
3472 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3473 *
3474 * @remarks This code path is not used during construction.
3475 */
3476static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3477{
3478 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3479 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3480 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3481
3482 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3483 ("Hot-plug flag is not set\n"),
3484 VERR_NOT_SUPPORTED);
3485 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3486
3487 /* Check if it was already attached */
3488 int rc = VINF_SUCCESS;
3489 DEVACPI_LOCK_R3(pDevIns, pThis);
3490 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3491 {
3492 PPDMIBASE IBaseTmp;
3493 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3494 if (RT_SUCCESS(rc))
3495 {
3496 /* Enable the CPU */
3497 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3498
3499 /*
3500 * Lock the CPU because we don't know if the guest will use it or not.
3501 * Prevents ejection while the CPU is still used
3502 */
3503 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3504 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3505 pThis->u32CpuEvent = iLUN;
3506
3507 /* Notify the guest */
3508 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3509 }
3510 }
3511 DEVACPI_UNLOCK(pDevIns, pThis);
3512 return rc;
3513}
3514
3515/**
3516 * Detach notification.
3517 *
3518 * @param pDevIns The device instance.
3519 * @param iLUN The logical unit which is being detached.
3520 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3521 */
3522static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3523{
3524 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3525
3526 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3527
3528 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3529 ("Hot-plug flag is not set\n"));
3530
3531 /* Check if it was already detached */
3532 DEVACPI_LOCK_R3(pDevIns, pThis);
3533 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3534 {
3535 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3536 {
3537 /* Disable the CPU */
3538 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3539 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3540 pThis->u32CpuEvent = iLUN;
3541
3542 /* Notify the guest */
3543 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3544 }
3545 else
3546 AssertMsgFailed(("CPU is still locked by the guest\n"));
3547 }
3548 DEVACPI_UNLOCK(pDevIns, pThis);
3549}
3550
3551/**
3552 * @interface_method_impl{PDMDEVREG,pfnResume}
3553 */
3554static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3555{
3556 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3557 if (pThis->fSetWakeupOnResume)
3558 {
3559 Log(("acpiResume: setting WAK_STS\n"));
3560 pThis->fSetWakeupOnResume = false;
3561 pThis->pm1a_sts |= WAK_STS;
3562 }
3563}
3564
3565/**
3566 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3567 */
3568static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3569{
3570 RT_NOREF(enmCtx);
3571 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3572 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3573 acpiR3PlantTables(pDevIns, pThis, pThisCC);
3574}
3575
3576/**
3577 * @interface_method_impl{PDMDEVREG,pfnReset}
3578 */
3579static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3580{
3581 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3582 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3583
3584 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3585 acpiSetIrq(pDevIns, 0);
3586
3587 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3588 pThis->pm1a_en = 0;
3589 pThis->pm1a_sts = 0;
3590 pThis->pm1a_ctl = 0;
3591 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3592 pThis->uPmTimerVal = 0;
3593 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3594 pThis->uPmTimeOld = pThis->uPmTimerVal;
3595 pThis->uBatteryIndex = 0;
3596 pThis->uSystemInfoIndex = 0;
3597 pThis->gpe0_en = 0;
3598 pThis->gpe0_sts = 0;
3599 pThis->uSleepState = 0;
3600 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
3601
3602 /* Real device behavior is resetting only the PM controller state,
3603 * but we're additionally doing the job of the BIOS. */
3604 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
3605 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3606
3607 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3608 * state. Real device behavior is only the SMBus controller state reset,
3609 * but we're additionally doing the job of the BIOS. */
3610 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3611 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3612 acpiR3SMBusResetDevice(pThis);
3613}
3614
3615/**
3616 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3617 */
3618static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3619{
3620 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3621 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3622 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3623
3624 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3625 {
3626 if (pThisCC->apu8CustBin[i])
3627 {
3628 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
3629 pThisCC->apu8CustBin[i] = NULL;
3630 }
3631 }
3632 return VINF_SUCCESS;
3633}
3634
3635/**
3636 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3637 */
3638static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3639{
3640 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3641 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3642 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3643 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3644
3645 /*
3646 * Init data and set defaults.
3647 */
3648 /** @todo move more of the code up! */
3649
3650 pThisCC->pDevIns = pDevIns;
3651 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3652 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3653 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3654 pThis->u32CpuEventType = 0;
3655 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3656
3657 /* The first CPU can't be attached/detached */
3658 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3659 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3660
3661 /* IBase */
3662 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
3663 /* IACPIPort */
3664 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3665 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3666 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3667 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3668 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3669 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3670 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3671
3672 /*
3673 * Set the default critical section to NOP (related to the PM timer).
3674 */
3675 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3676 AssertRCReturn(rc, rc);
3677
3678 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3679 AssertRCReturn(rc, rc);
3680
3681 /*
3682 * Validate and read the configuration.
3683 */
3684 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
3685 "IOAPIC"
3686 "|NumCPUs"
3687 "|HpetEnabled"
3688 "|McfgEnabled"
3689 "|McfgBase"
3690 "|McfgLength"
3691 "|PciPref64Enabled"
3692 "|PciPref64LimitGB"
3693 "|SmcEnabled"
3694 "|FdcEnabled"
3695 "|ShowRtc"
3696 "|ShowCpu"
3697 "|NicPciAddress"
3698 "|AudioPciAddress"
3699 "|NvmePciAddress"
3700 "|IocPciAddress"
3701 "|HostBusPciAddress"
3702 "|EnableSuspendToDisk"
3703 "|PowerS1Enabled"
3704 "|PowerS4Enabled"
3705 "|CpuHotPlug"
3706 "|AmlFilePath"
3707 "|Serial0IoPortBase"
3708 "|Serial1IoPortBase"
3709 "|Serial2IoPortBase"
3710 "|Serial3IoPortBase"
3711 "|Serial0Irq"
3712 "|Serial1Irq"
3713 "|Serial2Irq"
3714 "|Serial3Irq"
3715 "|AcpiOemId"
3716 "|AcpiCreatorId"
3717 "|AcpiCreatorRev"
3718 "|CustomTable"
3719 "|CustomTable0"
3720 "|CustomTable1"
3721 "|CustomTable2"
3722 "|CustomTable3"
3723 "|Parallel0IoPortBase"
3724 "|Parallel1IoPortBase"
3725 "|Parallel0Irq"
3726 "|Parallel1Irq"
3727 , "");
3728
3729 /* query whether we are supposed to present an IOAPIC */
3730 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3731 if (RT_FAILURE(rc))
3732 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
3733
3734 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3735 if (RT_FAILURE(rc))
3736 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3737
3738 /* query whether we are supposed to present an FDC controller */
3739 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3740 if (RT_FAILURE(rc))
3741 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
3742
3743 /* query whether we are supposed to present HPET */
3744 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
3745 if (RT_FAILURE(rc))
3746 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
3747 /* query MCFG configuration */
3748 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
3749 if (RT_FAILURE(rc))
3750 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
3751 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
3752 if (RT_FAILURE(rc))
3753 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
3754 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
3755
3756 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
3757 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
3758 if (RT_FAILURE(rc))
3759 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
3760
3761 /* query the limit of the the 64-bit prefetchable memory window */
3762 uint64_t u64PciPref64MaxGB;
3763 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
3764 if (RT_FAILURE(rc))
3765 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
3766 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
3767
3768 /* query whether we are supposed to present SMC */
3769 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
3770 if (RT_FAILURE(rc))
3771 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
3772
3773 /* query whether we are supposed to present RTC object */
3774 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
3775 if (RT_FAILURE(rc))
3776 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
3777
3778 /* query whether we are supposed to present CPU objects */
3779 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
3780 if (RT_FAILURE(rc))
3781 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
3782
3783 /* query primary NIC PCI address (GIGE) */
3784 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
3785 if (RT_FAILURE(rc))
3786 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
3787
3788 /* query HD Audio PCI address (HDAA) */
3789 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3790 if (RT_FAILURE(rc))
3791 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
3792
3793 /* query NVMe PCI address (NVMA) */
3794 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
3795 if (RT_FAILURE(rc))
3796 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
3797
3798 /* query IO controller (southbridge) PCI address */
3799 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3800 if (RT_FAILURE(rc))
3801 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
3802
3803 /* query host bus controller PCI address */
3804 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3805 if (RT_FAILURE(rc))
3806 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3807
3808 /* query whether S1 power state should be exposed */
3809 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3810 if (RT_FAILURE(rc))
3811 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3812
3813 /* query whether S4 power state should be exposed */
3814 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3815 if (RT_FAILURE(rc))
3816 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3817
3818 /* query whether S1 power state should save the VM state */
3819 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3820 if (RT_FAILURE(rc))
3821 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3822
3823 /* query whether we are allow CPU hot plugging */
3824 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3825 if (RT_FAILURE(rc))
3826 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
3827
3828 /* query serial info */
3829 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3830 if (RT_FAILURE(rc))
3831 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
3832
3833 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3834 if (RT_FAILURE(rc))
3835 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3836
3837 /* Serial 1 is enabled, get config data */
3838 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3839 if (RT_FAILURE(rc))
3840 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
3841
3842 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3843 if (RT_FAILURE(rc))
3844 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3845
3846 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
3847 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
3848 if (RT_FAILURE(rc))
3849 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
3850
3851 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
3852 if (RT_FAILURE(rc))
3853 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
3854
3855 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
3856 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
3857 if (RT_FAILURE(rc))
3858 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
3859
3860 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
3861 if (RT_FAILURE(rc))
3862 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
3863 /*
3864 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
3865 * the corresponding parallel port is not enabled.
3866 */
3867 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
3868 if (RT_FAILURE(rc))
3869 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
3870
3871 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
3872 if (RT_FAILURE(rc))
3873 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
3874
3875 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
3876 if (RT_FAILURE(rc))
3877 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
3878
3879 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
3880 if (RT_FAILURE(rc))
3881 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
3882
3883 /* Try to attach the other CPUs */
3884 for (unsigned i = 1; i < pThis->cCpus; i++)
3885 {
3886 if (pThis->fCpuHotPlug)
3887 {
3888 PPDMIBASE IBaseTmp;
3889 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3890
3891 if (RT_SUCCESS(rc))
3892 {
3893 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3894 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3895 Log(("acpi: Attached CPU %u\n", i));
3896 }
3897 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3898 Log(("acpi: CPU %u not attached yet\n", i));
3899 else
3900 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3901 }
3902 else
3903 {
3904 /* CPU is always attached if hot-plug is not enabled. */
3905 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3906 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3907 }
3908 }
3909
3910 char szOemId[16];
3911 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
3912 if (RT_FAILURE(rc))
3913 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3914 size_t cchOemId = strlen(szOemId);
3915 if (cchOemId > 6)
3916 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3917 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3918 memcpy(pThis->au8OemId, szOemId, cchOemId);
3919
3920 char szCreatorId[16];
3921 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
3922 if (RT_FAILURE(rc))
3923 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3924 size_t cchCreatorId = strlen(szCreatorId);
3925 if (cchCreatorId > 4)
3926 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3927 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3928 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
3929
3930 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3931 if (RT_FAILURE(rc))
3932 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3933
3934 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3935
3936 /*
3937 * Load custom ACPI tables.
3938 */
3939 /* Total space available for custom ACPI tables */
3940 /** @todo define as appropriate, remove as a magic number, and document
3941 * limitation in product manual */
3942 uint32_t cbBufAvail = 3072;
3943 pThis->cCustTbls = 0;
3944
3945 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
3946 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
3947 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
3948 {
3949 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
3950
3951 /*
3952 * Get the custom table binary file name.
3953 */
3954 char *pszCustBinFile = NULL;
3955 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
3956 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
3957 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
3958 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3959 {
3960 rc = VINF_SUCCESS;
3961 pszCustBinFile = NULL;
3962 }
3963 else if (RT_FAILURE(rc))
3964 return PDMDEV_SET_ERROR(pDevIns, rc,
3965 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
3966 else if (!*pszCustBinFile)
3967 {
3968 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
3969 pszCustBinFile = NULL;
3970 }
3971
3972 /*
3973 * Determine the custom table binary size, open specified file in the process.
3974 */
3975 if (pszCustBinFile)
3976 {
3977 uint32_t idxCust = pThis->cCustTbls;
3978 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
3979 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
3980 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
3981 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
3982 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
3983 if (RT_FAILURE(rc))
3984 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
3985 cbBufAvail -= pThisCC->acbCustBin[idxCust];
3986
3987 /* Update custom OEM attributes based on custom table */
3988 /** @todo is it intended for custom tables to overwrite user provided values above? */
3989 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
3990 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
3991 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
3992 pThis->u32OemRevision = pTblHdr->u32OemRevision;
3993 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
3994 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
3995
3996 pThis->cCustTbls++;
3997 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
3998 }
3999 }
4000
4001 /* Set default PM port base */
4002 pThis->uPmIoPortBase = PM_PORT_BASE;
4003
4004 /* Set default SMBus port base */
4005 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4006
4007 /*
4008 * FDC and SMC try to use the same non-shareable interrupt (6),
4009 * enable only one device.
4010 */
4011 if (pThis->fUseSmc)
4012 pThis->fUseFdc = false;
4013
4014 /*
4015 * Plant ACPI tables.
4016 */
4017 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4018 * au8RSDPPage here. However, there should be no harm in doing it
4019 * twice, so the lazy bird is taking the quick way out for now. */
4020 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4021 if (!GCPhysRsdp)
4022 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4023
4024 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4025 AssertRCReturn(rc, rc);
4026
4027 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4028 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4029 AssertRCReturn(rc, rc);
4030
4031 /*
4032 * Create the PM I/O ports. These can be unmapped and remapped.
4033 */
4034 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4035 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4036 AssertRCReturn(rc, rc);
4037 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4038 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4039 AssertRCReturn(rc, rc);
4040 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4041 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4042 AssertRCReturn(rc, rc);
4043 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4044 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4045 AssertRCReturn(rc, rc);
4046 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4047 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4048 AssertRCReturn(rc, rc);
4049 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4050 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4051 AssertRCReturn(rc, rc);
4052 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4053 AssertRCReturn(rc, rc);
4054
4055 /*
4056 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4057 */
4058 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4059 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4060 AssertRCReturn(rc, rc);
4061 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4062 AssertRCReturn(rc, rc);
4063
4064 /*
4065 * Create and map the fixed I/O ports.
4066 */
4067 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4068 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4069 AssertRCReturn(rc, rc);
4070#ifdef DEBUG_ACPI
4071 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4072 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4073 AssertRCReturn(rc, rc);
4074 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4075 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4076 AssertRCReturn(rc, rc);
4077#endif
4078 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4079 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4080 AssertRCReturn(rc, rc);
4081 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4082 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4083 AssertRCReturn(rc, rc);
4084 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4085 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4086 AssertRCReturn(rc, rc);
4087 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4088 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4089 AssertRCReturn(rc, rc);
4090 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4091 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4092 AssertRCReturn(rc, rc);
4093
4094 /*
4095 * Create the PM timer.
4096 */
4097 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4098 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer);
4099 AssertRCReturn(rc, rc);
4100
4101 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4102 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4103 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4104 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4105
4106 /*
4107 * Set up the PCI device.
4108 */
4109 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4110 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4111
4112 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4113 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4114
4115 /* See p. 50 of PIIX4 manual */
4116 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4117 PDMPciDevSetStatus(pPciDev, 0x0280);
4118
4119 PDMPciDevSetRevisionId(pPciDev, 0x08);
4120
4121 PDMPciDevSetClassProg(pPciDev, 0x00);
4122 PDMPciDevSetClassSub(pPciDev, 0x80);
4123 PDMPciDevSetClassBase(pPciDev, 0x06);
4124
4125 PDMPciDevSetHeaderType(pPciDev, 0x80);
4126
4127 PDMPciDevSetBIST(pPciDev, 0x00);
4128
4129 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4130 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4131
4132 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4133 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4134
4135 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4136 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4137 acpiR3SMBusResetDevice(pThis);
4138
4139 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4140 AssertRCReturn(rc, rc);
4141
4142 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4143 AssertRCReturn(rc, rc);
4144
4145 /*
4146 * Register the saved state.
4147 */
4148 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4149 AssertRCReturn(rc, rc);
4150
4151 /*
4152 * Get the corresponding connector interface
4153 */
4154 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4155 if (RT_SUCCESS(rc))
4156 {
4157 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4158 if (!pThisCC->pDrv)
4159 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4160 }
4161 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4162 {
4163 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4164 rc = VINF_SUCCESS;
4165 }
4166 else
4167 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4168
4169 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4170
4171 return rc;
4172}
4173
4174#else /* !IN_RING3 */
4175
4176/**
4177 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4178 */
4179static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4180{
4181 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4182 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4183
4184 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4185 AssertRCReturn(rc, rc);
4186
4187 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4188 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4189 AssertRCReturn(rc, rc);
4190
4191 return VINF_SUCCESS;
4192}
4193
4194#endif /* !IN_RING3 */
4195
4196/**
4197 * The device registration structure.
4198 */
4199const PDMDEVREG g_DeviceACPI =
4200{
4201 /* .u32Version = */ PDM_DEVREG_VERSION,
4202 /* .uReserved0 = */ 0,
4203 /* .szName = */ "acpi",
4204 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4205 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4206 /* .cMaxInstances = */ ~0U,
4207 /* .uSharedVersion = */ 42,
4208 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4209 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4210 /* .cbInstanceRC = */ 0,
4211 /* .cMaxPciDevices = */ 1,
4212 /* .cMaxMsixVectors = */ 0,
4213 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4214#if defined(IN_RING3)
4215 /* .pszRCMod = */ "VBoxDDRC.rc",
4216 /* .pszR0Mod = */ "VBoxDDR0.r0",
4217 /* .pfnConstruct = */ acpiR3Construct,
4218 /* .pfnDestruct = */ acpiR3Destruct,
4219 /* .pfnRelocate = */ NULL,
4220 /* .pfnMemSetup = */ acpiR3MemSetup,
4221 /* .pfnPowerOn = */ NULL,
4222 /* .pfnReset = */ acpiR3Reset,
4223 /* .pfnSuspend = */ NULL,
4224 /* .pfnResume = */ acpiR3Resume,
4225 /* .pfnAttach = */ acpiR3Attach,
4226 /* .pfnDetach = */ acpiR3Detach,
4227 /* .pfnQueryInterface = */ NULL,
4228 /* .pfnInitComplete = */ NULL,
4229 /* .pfnPowerOff = */ NULL,
4230 /* .pfnSoftReset = */ NULL,
4231 /* .pfnReserved0 = */ NULL,
4232 /* .pfnReserved1 = */ NULL,
4233 /* .pfnReserved2 = */ NULL,
4234 /* .pfnReserved3 = */ NULL,
4235 /* .pfnReserved4 = */ NULL,
4236 /* .pfnReserved5 = */ NULL,
4237 /* .pfnReserved6 = */ NULL,
4238 /* .pfnReserved7 = */ NULL,
4239#elif defined(IN_RING0)
4240 /* .pfnEarlyConstruct = */ NULL,
4241 /* .pfnConstruct = */ acpiRZConstruct,
4242 /* .pfnDestruct = */ NULL,
4243 /* .pfnFinalDestruct = */ NULL,
4244 /* .pfnRequest = */ NULL,
4245 /* .pfnReserved0 = */ NULL,
4246 /* .pfnReserved1 = */ NULL,
4247 /* .pfnReserved2 = */ NULL,
4248 /* .pfnReserved3 = */ NULL,
4249 /* .pfnReserved4 = */ NULL,
4250 /* .pfnReserved5 = */ NULL,
4251 /* .pfnReserved6 = */ NULL,
4252 /* .pfnReserved7 = */ NULL,
4253#elif defined(IN_RC)
4254 /* .pfnConstruct = */ acpiRZConstruct,
4255 /* .pfnReserved0 = */ NULL,
4256 /* .pfnReserved1 = */ NULL,
4257 /* .pfnReserved2 = */ NULL,
4258 /* .pfnReserved3 = */ NULL,
4259 /* .pfnReserved4 = */ NULL,
4260 /* .pfnReserved5 = */ NULL,
4261 /* .pfnReserved6 = */ NULL,
4262 /* .pfnReserved7 = */ NULL,
4263#else
4264# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4265#endif
4266 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4267};
4268
4269#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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