VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 85569

Last change on this file since 85569 was 85347, checked in by vboxsync, 5 years ago

ACPI: Add IndexFields for IOMMU and SB I/O APIC. Let's see if this causes trouble.
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1/* $Id: DevACPI.cpp 85347 2020-07-15 10:17:15Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <iprt/asm-math.h>
32#include <iprt/file.h>
33#ifdef IN_RING3
34# include <iprt/alloc.h>
35# include <iprt/string.h>
36# include <iprt/uuid.h>
37#endif /* IN_RING3 */
38
39#include "VBoxDD.h"
40
41#ifdef LOG_ENABLED
42# define DEBUG_ACPI
43#endif
44
45
46/*********************************************************************************************************************************
47* Defined Constants And Macros *
48*********************************************************************************************************************************/
49#ifdef IN_RING3
50/** Locks the device state, ring-3 only. */
51# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
52 do { \
53 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
54 AssertRC(rcLock); \
55 } while (0)
56#endif
57/** Unlocks the device state (all contexts). */
58#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
59 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
60
61
62#define DEBUG_HEX 0x3000
63#define DEBUG_CHR 0x3001
64
65/** PM Base Address PCI config space offset */
66#define PMBA 0x40
67/** PM Miscellaneous Power Management PCI config space offset */
68#define PMREGMISC 0x80
69
70#define PM_TMR_FREQ 3579545
71/** Default base for PM PIIX4 device */
72#define PM_PORT_BASE 0x4000
73/* Port offsets in PM device */
74enum
75{
76 PM1a_EVT_OFFSET = 0x00,
77 PM1b_EVT_OFFSET = -1, /**< not supported */
78 PM1a_CTL_OFFSET = 0x04,
79 PM1b_CTL_OFFSET = -1, /**< not supported */
80 PM2_CTL_OFFSET = -1, /**< not supported */
81 PM_TMR_OFFSET = 0x08,
82 GPE0_OFFSET = 0x20,
83 GPE1_OFFSET = -1 /**< not supported */
84};
85
86/* Maximum supported number of custom ACPI tables */
87#define MAX_CUST_TABLES 4
88
89/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
90#define PM_TMR_32BIT
91
92#define BAT_INDEX 0x00004040
93#define BAT_DATA 0x00004044
94#define SYSI_INDEX 0x00004048
95#define SYSI_DATA 0x0000404c
96#define ACPI_RESET_BLK 0x00004050
97
98/* PM1x status register bits */
99#define TMR_STS RT_BIT(0)
100#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
101#define BM_STS RT_BIT(4)
102#define GBL_STS RT_BIT(5)
103#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
104#define PWRBTN_STS RT_BIT(8)
105#define SLPBTN_STS RT_BIT(9)
106#define RTC_STS RT_BIT(10)
107#define IGN_STS RT_BIT(11)
108#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
109#define WAK_STS RT_BIT(15)
110#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
111
112/* PM1x enable register bits */
113#define TMR_EN RT_BIT(0)
114#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
115#define GBL_EN RT_BIT(5)
116#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
117#define PWRBTN_EN RT_BIT(8)
118#define SLPBTN_EN RT_BIT(9)
119#define RTC_EN RT_BIT(10)
120#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
121#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
122#define IGN_EN 0
123
124/* PM1x control register bits */
125#define SCI_EN RT_BIT(0)
126#define BM_RLD RT_BIT(1)
127#define GBL_RLS RT_BIT(2)
128#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
129#define IGN_CNT RT_BIT(9)
130#define SLP_TYPx_SHIFT 10
131#define SLP_TYPx_MASK 7
132#define SLP_EN RT_BIT(13)
133#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
134#define RSR_CNT (RSR1_CNT | RSR2_CNT)
135
136#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
137
138enum
139{
140 BAT_STATUS_STATE = 0x00, /**< BST battery state */
141 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
142 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
143 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
144 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
145 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
146 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
147 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
148 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
149 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
150 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
151 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
152 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
153 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
154 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
155 BAT_INDEX_LAST
156};
157
158enum
159{
160 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
161 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
162};
163
164enum
165{
166 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
167 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
168 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
169 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
170 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
171 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
172 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
173 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
174 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
175 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
176 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
177 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
178 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
179 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
180 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
181 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
182 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
183 SYSTEM_INFO_INDEX_POWER_STATES = 17,
184 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
185 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
186 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
187 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
188 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
189 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
190 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
191 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
192 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
193 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
194 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
195 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
196 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
197 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
198 SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS = 32, /**< AMD IOMMU PCI address, or 0 */
199 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
200 SYSTEM_INFO_INDEX_END = 34,
201 SYSTEM_INFO_INDEX_INVALID = 0x80,
202 SYSTEM_INFO_INDEX_VALID = 0x200
203};
204
205#define AC_OFFLINE 0
206#define AC_ONLINE 1
207
208#define BAT_TECH_PRIMARY 1
209#define BAT_TECH_SECONDARY 2
210
211#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
212#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
213#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
214#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
215#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
216
217/** SMBus Base Address PCI config space offset */
218#define SMBBA 0x90
219/** SMBus Host Configuration PCI config space offset */
220#define SMBHSTCFG 0xd2
221/** SMBus Slave Command PCI config space offset */
222#define SMBSLVC 0xd3
223/** SMBus Slave Shadow Port 1 PCI config space offset */
224#define SMBSHDW1 0xd4
225/** SMBus Slave Shadow Port 2 PCI config space offset */
226#define SMBSHDW2 0xd5
227/** SMBus Revision Identification PCI config space offset */
228#define SMBREV 0xd6
229
230#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
231#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
232#define SMBHSTCFG_INTRSEL_SMI 0
233#define SMBHSTCFG_INTRSEL_IRQ9 4
234#define SMBHSTCFG_INTRSEL_SHIFT 1
235
236/** Default base for SMBus PIIX4 device */
237#define SMB_PORT_BASE 0x4100
238
239/** SMBus Host Status Register I/O offset */
240#define SMBHSTSTS_OFF 0x0000
241/** SMBus Slave Status Register I/O offset */
242#define SMBSLVSTS_OFF 0x0001
243/** SMBus Host Count Register I/O offset */
244#define SMBHSTCNT_OFF 0x0002
245/** SMBus Host Command Register I/O offset */
246#define SMBHSTCMD_OFF 0x0003
247/** SMBus Host Address Register I/O offset */
248#define SMBHSTADD_OFF 0x0004
249/** SMBus Host Data 0 Register I/O offset */
250#define SMBHSTDAT0_OFF 0x0005
251/** SMBus Host Data 1 Register I/O offset */
252#define SMBHSTDAT1_OFF 0x0006
253/** SMBus Block Data Register I/O offset */
254#define SMBBLKDAT_OFF 0x0007
255/** SMBus Slave Control Register I/O offset */
256#define SMBSLVCNT_OFF 0x0008
257/** SMBus Shadow Command Register I/O offset */
258#define SMBSHDWCMD_OFF 0x0009
259/** SMBus Slave Event Register I/O offset */
260#define SMBSLVEVT_OFF 0x000a
261/** SMBus Slave Data Register I/O offset */
262#define SMBSLVDAT_OFF 0x000c
263
264#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
265#define SMBHSTSTS_INTER RT_BIT(1)
266#define SMBHSTSTS_DEV_ERR RT_BIT(2)
267#define SMBHSTSTS_BUS_ERR RT_BIT(3)
268#define SMBHSTSTS_FAILED RT_BIT(4)
269#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
270
271#define SMBSLVSTS_WRITE_MASK 0x3c
272
273#define SMBHSTCNT_INTEREN RT_BIT(0)
274#define SMBHSTCNT_KILL RT_BIT(1)
275#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
276#define SMBHSTCNT_START RT_BIT(6)
277#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
278
279#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
280
281
282/*********************************************************************************************************************************
283* Structures and Typedefs *
284*********************************************************************************************************************************/
285/**
286 * The shared ACPI device state.
287 */
288typedef struct ACPISTATE
289{
290 /** Critical section protecting the ACPI state. */
291 PDMCRITSECT CritSect;
292
293 uint16_t pm1a_en;
294 uint16_t pm1a_sts;
295 uint16_t pm1a_ctl;
296 /** Number of logical CPUs in guest */
297 uint16_t cCpus;
298
299 uint64_t u64PmTimerInitial;
300 /** The PM timer. */
301 TMTIMERHANDLE hPmTimer;
302 /* PM Timer last calculated value */
303 uint32_t uPmTimerVal;
304 uint32_t Alignment0;
305
306 uint32_t gpe0_en;
307 uint32_t gpe0_sts;
308
309 uint32_t uBatteryIndex;
310 uint32_t au8BatteryInfo[13];
311
312 uint32_t uSystemInfoIndex;
313 uint32_t u32Alignment0;
314 uint64_t u64RamSize;
315 /** Offset of the 64-bit prefetchable memory window. */
316 uint64_t u64PciPref64Min;
317 /** Limit of the 64-bit prefetchable memory window. */
318 uint64_t u64PciPref64Max;
319 /** The number of bytes below 4GB. */
320 uint32_t cbRamLow;
321
322 /** Current ACPI S* state. We support S0 and S5. */
323 uint32_t uSleepState;
324 uint8_t au8RSDPPage[0x1000];
325 /** This is a workaround for incorrect index field handling by Intels ACPICA.
326 * The system info _INI method writes to offset 0x200. We either observe a
327 * write request to index 0x80 (in that case we don't change the index) or a
328 * write request to offset 0x200 (in that case we divide the index value by
329 * 4. Note that the _STA method is sometimes called prior to the _INI method
330 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
331 * acpiR3BatIndexWrite() for handling this. */
332 uint8_t u8IndexShift;
333 /** provide an I/O-APIC */
334 uint8_t u8UseIOApic;
335 /** provide a floppy controller */
336 bool fUseFdc;
337 /** If High Precision Event Timer device should be supported */
338 bool fUseHpet;
339 /** If System Management Controller device should be supported */
340 bool fUseSmc;
341 /** the guest handled the last power button event */
342 bool fPowerButtonHandled;
343 /** If ACPI CPU device should be shown */
344 bool fShowCpu;
345 /** If Real Time Clock ACPI object to be shown */
346 bool fShowRtc;
347 /** I/O port address of PM device. */
348 RTIOPORT uPmIoPortBase;
349 /** I/O port address of SMBus device. */
350 RTIOPORT uSMBusIoPortBase;
351 /** Which CPU to check for the locked status. */
352 uint32_t idCpuLockCheck;
353 /** Array of flags of attached CPUs */
354 VMCPUSET CpuSetAttached;
355 /** Mask of locked CPUs (used by the guest). */
356 VMCPUSET CpuSetLocked;
357 /** The CPU event type. */
358 uint32_t u32CpuEventType;
359 /** The CPU id affected. */
360 uint32_t u32CpuEvent;
361 /** Flag whether CPU hot plugging is enabled. */
362 bool fCpuHotPlug;
363 /** If MCFG ACPI table shown to the guest */
364 bool fUseMcfg;
365 /** if the 64-bit prefetchable memory window is shown to the guest */
366 bool fPciPref64Enabled;
367 bool afAlignment1;
368 /** Primary NIC PCI address. */
369 uint32_t u32NicPciAddress;
370 /** HD Audio PCI address. */
371 uint32_t u32AudioPciAddress;
372 /** Primary NVMe controller PCI address. */
373 uint32_t u32NvmePciAddress;
374 /** Flag whether S1 power state is enabled. */
375 bool fS1Enabled;
376 /** Flag whether S4 power state is enabled. */
377 bool fS4Enabled;
378 /** Flag whether S1 triggers a state save. */
379 bool fSuspendToSavedState;
380 /** Flag whether to set WAK_STS on resume (restore included). */
381 bool fSetWakeupOnResume;
382 /** PCI address of the IO controller device. */
383 uint32_t u32IocPciAddress;
384 /** PCI address of the host bus controller device. */
385 uint32_t u32HbcPciAddress;
386
387 /** Physical address of PCI config space MMIO region */
388 uint64_t u64PciConfigMMioAddress;
389 /** Length of PCI config space MMIO region */
390 uint64_t u64PciConfigMMioLength;
391 /** Serial 0 IRQ number */
392 uint8_t uSerial0Irq;
393 /** Serial 1 IRQ number */
394 uint8_t uSerial1Irq;
395 /** Serial 2 IRQ number */
396 uint8_t uSerial2Irq;
397 /** Serial 3 IRQ number */
398 uint8_t uSerial3Irq;
399 /** Serial 0 IO port base */
400 RTIOPORT uSerial0IoPortBase;
401 /** Serial 1 IO port base */
402 RTIOPORT uSerial1IoPortBase;
403 /** Serial 2 IO port base */
404 RTIOPORT uSerial2IoPortBase;
405 /** Serial 3 IO port base */
406 RTIOPORT uSerial3IoPortBase;
407
408 /** @name Parallel port config bits
409 * @{ */
410 /** Parallel 0 IO port base */
411 RTIOPORT uParallel0IoPortBase;
412 /** Parallel 1 IO port base */
413 RTIOPORT uParallel1IoPortBase;
414 /** Parallel 0 IRQ number */
415 uint8_t uParallel0Irq;
416 /** Parallel 1 IRQ number */
417 uint8_t uParallel1Irq;
418 /** @} */
419
420 /** Number of custom ACPI tables */
421 uint8_t cCustTbls;
422 /** ACPI OEM ID */
423 uint8_t au8OemId[6];
424 /** ACPI Crator ID */
425 uint8_t au8CreatorId[4];
426 uint8_t abAlignment2[3];
427 /** ACPI Crator Rev */
428 uint32_t u32CreatorRev;
429 /** ACPI custom OEM Tab ID */
430 uint8_t au8OemTabId[8];
431 /** ACPI custom OEM Rev */
432 uint32_t u32OemRevision;
433
434 /** SMBus Host Status Register */
435 uint8_t u8SMBusHstSts;
436 /** SMBus Slave Status Register */
437 uint8_t u8SMBusSlvSts;
438 /** SMBus Host Control Register */
439 uint8_t u8SMBusHstCnt;
440 /** SMBus Host Command Register */
441 uint8_t u8SMBusHstCmd;
442 /** SMBus Host Address Register */
443 uint8_t u8SMBusHstAdd;
444 /** SMBus Host Data 0 Register */
445 uint8_t u8SMBusHstDat0;
446 /** SMBus Host Data 1 Register */
447 uint8_t u8SMBusHstDat1;
448 /** SMBus Slave Control Register */
449 uint8_t u8SMBusSlvCnt;
450 /** SMBus Slave Event Register */
451 uint16_t u16SMBusSlvEvt;
452 /** SMBus Slave Data Register */
453 uint16_t u16SMBusSlvDat;
454 /** SMBus Shadow Command Register */
455 uint8_t u8SMBusShdwCmd;
456 /** SMBus Host Block Index */
457 uint8_t u8SMBusBlkIdx;
458 uint8_t abAlignment3[2];
459 /** SMBus Host Block Data Buffer */
460 uint8_t au8SMBusBlkDat[32];
461
462 /** @todo DEBUGGING */
463 uint32_t uPmTimeOld;
464 uint32_t uPmTimeA;
465 uint32_t uPmTimeB;
466 uint32_t Alignment5;
467
468 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
469 * @{ */
470 IOMIOPORTHANDLE hIoPortPm1aEn;
471 IOMIOPORTHANDLE hIoPortPm1aSts;
472 IOMIOPORTHANDLE hIoPortPm1aCtl;
473 IOMIOPORTHANDLE hIoPortPmTimer;
474 IOMIOPORTHANDLE hIoPortGpe0En;
475 IOMIOPORTHANDLE hIoPortGpe0Sts;
476 /** @} */
477
478 /** SMBus I/O ports (mapped/unmapped). */
479 IOMIOPORTHANDLE hIoPortSMBus;
480
481 /** @name Fixed I/O ports
482 * @{ */
483 /** ACPI SMI I/O port. */
484 IOMIOPORTHANDLE hIoPortSmi;
485 /** ACPI Debug hex I/O port. */
486 IOMIOPORTHANDLE hIoPortDebugHex;
487 /** ACPI Debug char I/O port. */
488 IOMIOPORTHANDLE hIoPortDebugChar;
489 /** ACPI Battery status index I/O port. */
490 IOMIOPORTHANDLE hIoPortBatteryIndex;
491 /** ACPI Battery status data I/O port. */
492 IOMIOPORTHANDLE hIoPortBatteryData;
493 /** ACPI system info index I/O port. */
494 IOMIOPORTHANDLE hIoPortSysInfoIndex;
495 /** ACPI system info data I/O port. */
496 IOMIOPORTHANDLE hIoPortSysInfoData;
497 /** ACPI Reset I/O port. */
498 IOMIOPORTHANDLE hIoPortReset;
499 /** @} */
500
501} ACPISTATE;
502/** Pointer to the shared ACPI device state. */
503typedef ACPISTATE *PACPISTATE;
504
505
506/**
507 * The ring-3 ACPI device state.
508 */
509typedef struct ACPISTATER3
510{
511 /** ACPI port base interface. */
512 PDMIBASE IBase;
513 /** ACPI port interface. */
514 PDMIACPIPORT IACPIPort;
515 /** Pointer to the device instance so we can get our bearings from
516 * interface functions. */
517 PPDMDEVINSR3 pDevIns;
518
519 /** Pointer to the driver base interface. */
520 R3PTRTYPE(PPDMIBASE) pDrvBase;
521 /** Pointer to the driver connector interface. */
522 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
523
524 /** Custom ACPI tables binary data. */
525 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
526 /** The size of the custom table binary. */
527 uint64_t acbCustBin[MAX_CUST_TABLES];
528} ACPISTATER3;
529/** Pointer to the ring-3 ACPI device state. */
530typedef ACPISTATER3 *PACPISTATER3;
531
532
533#pragma pack(1)
534
535/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
536struct ACPIGENADDR
537{
538 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
539 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
540 uint8_t u8RegisterBitOffset; /**< bit offset of register */
541 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
542 uint64_t u64Address; /**< 64-bit address of register */
543};
544AssertCompileSize(ACPIGENADDR, 12);
545
546/** Root System Description Pointer */
547struct ACPITBLRSDP
548{
549 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
550 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
551 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
552 uint8_t u8Revision; /**< revision number, currently 2 */
553#define ACPI_REVISION 2 /**< ACPI 3.0 */
554 uint32_t u32RSDT; /**< phys addr of RSDT */
555 uint32_t u32Length; /**< bytes of this table */
556 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
557 uint8_t u8ExtChecksum; /**< checksum of entire table */
558 uint8_t u8Reserved[3]; /**< reserved */
559};
560AssertCompileSize(ACPITBLRSDP, 36);
561
562/** System Description Table Header */
563struct ACPITBLHEADER
564{
565 uint8_t au8Signature[4]; /**< table identifier */
566 uint32_t u32Length; /**< length of the table including header */
567 uint8_t u8Revision; /**< revision number */
568 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
569 uint8_t au8OemId[6]; /**< OEM-supplied string */
570 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
571 uint32_t u32OemRevision; /**< OEM-supplied revision number */
572 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
573 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
574};
575AssertCompileSize(ACPITBLHEADER, 36);
576
577/** Root System Description Table */
578struct ACPITBLRSDT
579{
580 ACPITBLHEADER header;
581 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
582};
583AssertCompileSize(ACPITBLRSDT, 40);
584
585/** Extended System Description Table */
586struct ACPITBLXSDT
587{
588 ACPITBLHEADER header;
589 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
590};
591AssertCompileSize(ACPITBLXSDT, 44);
592
593/** Fixed ACPI Description Table */
594struct ACPITBLFADT
595{
596 ACPITBLHEADER header;
597 uint32_t u32FACS; /**< phys. address of FACS */
598 uint32_t u32DSDT; /**< phys. address of DSDT */
599 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
600#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
601#define INT_MODEL_MULTIPLE_APIC 2
602 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
603 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
604#define SCI_INT 9
605 uint32_t u32SMICmd; /**< system port address of SMI command port */
606#define SMI_CMD 0x0000442e
607 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
608#define ACPI_ENABLE 0xa1
609 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
610#define ACPI_DISABLE 0xa0
611 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
612 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
613 state control responsibility */
614 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
615 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
616 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
617 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
618 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
619 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
620 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
621 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
622 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
623 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
624 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
625 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
626 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
627#define GPE0_BLK_LEN 2
628 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
629#define GPE1_BLK_LEN 0
630 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
631#define GPE1_BASE 0
632 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
633 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
634#define P_LVL2_LAT 101 /**< C2 state not supported */
635 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
636#define P_LVL3_LAT 1001 /**< C3 state not supported */
637 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
638 lines from any processors memory caches */
639#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
640 uint16_t u16FlushStride; /**< cache line width */
641#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
642 uint8_t u8DutyOffset;
643 uint8_t u8DutyWidth;
644 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
645 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
646 uint8_t u8Century; /**< RTC CMOS RAM index of century */
647 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
648#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
649 (COM too?) */
650#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
651#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
652#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
653#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
654 uint8_t u8Must0_0; /**< must be 0 */
655 uint32_t u32Flags; /**< fixed feature flags */
656#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
657#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
658#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
659#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
660#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
661#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
662#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
663#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
664#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
665#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
666#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
667#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
668#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
669#define FADT_FL_CPU_SW_SLP RT_BIT(13)
670#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
671#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
672#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
673#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
674#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
675#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
676
677/* PM Timer mask and msb */
678#ifndef PM_TMR_32BIT
679#define TMR_VAL_MSB 0x800000
680#define TMR_VAL_MASK 0xffffff
681#undef FADT_FL_TMR_VAL_EXT
682#define FADT_FL_TMR_VAL_EXT 0
683#else
684#define TMR_VAL_MSB 0x80000000
685#define TMR_VAL_MASK 0xffffffff
686#endif
687
688 /** Start of the ACPI 2.0 extension. */
689 ACPIGENADDR ResetReg; /**< ext addr of reset register */
690 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
691#define ACPI_RESET_REG_VAL 0x10
692 uint8_t au8Must0_1[3]; /**< must be 0 */
693 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
694 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
695 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
696 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
697 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
698 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
699 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
700 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
701 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
702 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
703};
704AssertCompileSize(ACPITBLFADT, 244);
705#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
706
707/** Firmware ACPI Control Structure */
708struct ACPITBLFACS
709{
710 uint8_t au8Signature[4]; /**< 'FACS' */
711 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
712 uint32_t u32HWSignature; /**< systems HW signature at last boot */
713 uint32_t u32FWVector; /**< address of waking vector */
714 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
715 uint32_t u32Flags; /**< FACS flags */
716 uint64_t u64X_FWVector; /**< 64-bit waking vector */
717 uint8_t u8Version; /**< version of this table */
718 uint8_t au8Reserved[31]; /**< zero */
719};
720AssertCompileSize(ACPITBLFACS, 64);
721
722/** Processor Local APIC Structure */
723struct ACPITBLLAPIC
724{
725 uint8_t u8Type; /**< 0 = LAPIC */
726 uint8_t u8Length; /**< 8 */
727 uint8_t u8ProcId; /**< processor ID */
728 uint8_t u8ApicId; /**< local APIC ID */
729 uint32_t u32Flags; /**< Flags */
730#define LAPIC_ENABLED 0x1
731};
732AssertCompileSize(ACPITBLLAPIC, 8);
733
734/** I/O APIC Structure */
735struct ACPITBLIOAPIC
736{
737 uint8_t u8Type; /**< 1 == I/O APIC */
738 uint8_t u8Length; /**< 12 */
739 uint8_t u8IOApicId; /**< I/O APIC ID */
740 uint8_t u8Reserved; /**< 0 */
741 uint32_t u32Address; /**< phys address to access I/O APIC */
742 uint32_t u32GSIB; /**< global system interrupt number to start */
743};
744AssertCompileSize(ACPITBLIOAPIC, 12);
745
746/** Interrupt Source Override Structure */
747struct ACPITBLISO
748{
749 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
750 uint8_t u8Length; /**< 10 */
751 uint8_t u8Bus; /**< Bus */
752 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
753 uint32_t u32GSI; /**< Global System Interrupt */
754 uint16_t u16Flags; /**< MPS INTI flags Global */
755};
756AssertCompileSize(ACPITBLISO, 10);
757#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
758
759/** HPET Descriptor Structure */
760struct ACPITBLHPET
761{
762 ACPITBLHEADER aHeader;
763 uint32_t u32Id; /**< hardware ID of event timer block
764 [31:16] PCI vendor ID of first timer block
765 [15] legacy replacement IRQ routing capable
766 [14] reserved
767 [13] COUNT_SIZE_CAP counter size
768 [12:8] number of comparators in first timer block
769 [7:0] hardware rev ID */
770 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
771 uint8_t u32Number; /**< sequence number starting at 0 */
772 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
773 lost interrupts while the counter is programmed
774 to operate in periodic mode. Unit: clock tick. */
775 uint8_t u8Attributes; /**< page protection and OEM attribute. */
776};
777AssertCompileSize(ACPITBLHPET, 56);
778
779/** MCFG Descriptor Structure */
780typedef struct ACPITBLMCFG
781{
782 ACPITBLHEADER aHeader;
783 uint64_t u64Reserved;
784} ACPITBLMCFG;
785AssertCompileSize(ACPITBLMCFG, 44);
786
787/** Number of such entries can be computed from the whole table length in header */
788typedef struct ACPITBLMCFGENTRY
789{
790 uint64_t u64BaseAddress;
791 uint16_t u16PciSegmentGroup;
792 uint8_t u8StartBus;
793 uint8_t u8EndBus;
794 uint32_t u32Reserved;
795} ACPITBLMCFGENTRY;
796AssertCompileSize(ACPITBLMCFGENTRY, 16);
797
798#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
799
800/** Custom Description Table */
801struct ACPITBLCUST
802{
803 ACPITBLHEADER header;
804 uint8_t au8Data[476];
805};
806AssertCompileSize(ACPITBLCUST, 512);
807
808
809#pragma pack()
810
811
812#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
813
814
815/*********************************************************************************************************************************
816* Internal Functions *
817*********************************************************************************************************************************/
818#ifdef IN_RING3
819static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
820#endif
821
822/* SCI, usually IRQ9 */
823DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
824{
825 PDMDevHlpPCISetIrq(pDevIns, 0, level);
826}
827
828DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
829{
830 return (pThis->pm1a_ctl & SCI_EN)
831 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
832}
833
834DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
835{
836 return !!(pThis->gpe0_en & pThis->gpe0_sts);
837}
838
839DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
840{
841 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
842 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
843 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
844 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
845 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
846}
847
848DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
849{
850 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
851}
852
853/**
854 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
855 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
856 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
857 * registers and trigger IRQs.
858 *
859 * Caller must hold the state lock.
860 *
861 * @param pDevIns The PDM device instance.
862 * @param pThis The ACPI shared instance data.
863 * @param sts The new PM1a.STS value.
864 * @param en The new PM1a.EN value.
865 */
866static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
867{
868 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
869
870 const bool old_level = acpiSCILevel(pDevIns, pThis);
871 pThis->pm1a_en = en;
872 pThis->pm1a_sts = sts;
873 const bool new_level = acpiSCILevel(pDevIns, pThis);
874
875 LogFunc(("old=%x new=%x\n", old_level, new_level));
876
877 if (new_level != old_level)
878 acpiSetIrq(pDevIns, new_level);
879}
880
881#ifdef IN_RING3
882
883/**
884 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
885 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
886 *
887 * Caller must hold the state lock.
888 *
889 * @param pDevIns The PDM device instance.
890 * @param pThis The ACPI shared instance data.
891 * @param sts The new GPE0.STS value.
892 * @param en The new GPE0.EN value.
893 */
894static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
895{
896 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
897
898 const bool old_level = acpiSCILevel(pDevIns, pThis);
899 pThis->gpe0_en = en;
900 pThis->gpe0_sts = sts;
901 const bool new_level = acpiSCILevel(pDevIns, pThis);
902
903 LogFunc(("old=%x new=%x\n", old_level, new_level));
904
905 if (new_level != old_level)
906 acpiSetIrq(pDevIns, new_level);
907}
908
909/**
910 * Used by acpiR3PM1aCtlWrite to power off the VM.
911 *
912 * @param pDevIns The device instance.
913 * @returns Strict VBox status code.
914 */
915static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
916{
917 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
918 AssertRC(VBOXSTRICTRC_VAL(rc));
919 return rc;
920}
921
922/**
923 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
924 *
925 * @param pDevIns The device instance.
926 * @param pThis The ACPI shared instance data.
927 * @returns Strict VBox status code.
928 */
929static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
930{
931 /* We must set WAK_STS on resume (includes restore) so the guest knows that
932 we've woken up and can continue executing code. The guest is probably
933 reading the PMSTS register in a loop to check this. */
934 VBOXSTRICTRC rc;
935 pThis->fSetWakeupOnResume = true;
936 if (pThis->fSuspendToSavedState)
937 {
938 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
939 if (rc != VERR_NOT_SUPPORTED)
940 AssertRC(VBOXSTRICTRC_VAL(rc));
941 else
942 {
943 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
944 rc = PDMDevHlpVMSuspend(pDevIns);
945 AssertRC(VBOXSTRICTRC_VAL(rc));
946 }
947 }
948 else
949 {
950 rc = PDMDevHlpVMSuspend(pDevIns);
951 AssertRC(VBOXSTRICTRC_VAL(rc));
952 }
953 return rc;
954}
955
956
957/**
958 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
959 */
960static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
961{
962 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
963 PPDMDEVINS pDevIns = pThisCC->pDevIns;
964 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
965 DEVACPI_LOCK_R3(pDevIns, pThis);
966
967 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
968 pThis->fPowerButtonHandled = false;
969 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
970
971 DEVACPI_UNLOCK(pDevIns, pThis);
972 return VINF_SUCCESS;
973}
974
975/**
976 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
977 */
978static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
979{
980 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
981 PPDMDEVINS pDevIns = pThisCC->pDevIns;
982 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
983 DEVACPI_LOCK_R3(pDevIns, pThis);
984
985 *pfHandled = pThis->fPowerButtonHandled;
986
987 DEVACPI_UNLOCK(pDevIns, pThis);
988 return VINF_SUCCESS;
989}
990
991/**
992 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
993 * Guest entered into G0 (working) or G1 (sleeping)}
994 */
995static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
996{
997 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
998 PPDMDEVINS pDevIns = pThisCC->pDevIns;
999 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1000 DEVACPI_LOCK_R3(pDevIns, pThis);
1001
1002 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1003
1004 DEVACPI_UNLOCK(pDevIns, pThis);
1005 return VINF_SUCCESS;
1006}
1007
1008/**
1009 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1010 */
1011static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1012{
1013 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1014 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1015 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1016 DEVACPI_LOCK_R3(pDevIns, pThis);
1017
1018 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1019
1020 DEVACPI_UNLOCK(pDevIns, pThis);
1021 return VINF_SUCCESS;
1022}
1023
1024/**
1025 * Send an ACPI sleep button event.
1026 *
1027 * @returns VBox status code
1028 * @param pInterface Pointer to the interface structure containing the called function pointer.
1029 */
1030static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1031{
1032 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1033 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1034 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1035 DEVACPI_LOCK_R3(pDevIns, pThis);
1036
1037 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1038
1039 DEVACPI_UNLOCK(pDevIns, pThis);
1040 return VINF_SUCCESS;
1041}
1042
1043/**
1044 * Send an ACPI monitor hot-plug event.
1045 *
1046 * @returns VBox status code
1047 * @param pInterface Pointer to the interface structure containing the
1048 * called function pointer.
1049 */
1050static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1051{
1052 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1053 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1054 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1055 DEVACPI_LOCK_R3(pDevIns, pThis);
1056
1057 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1058
1059 DEVACPI_UNLOCK(pDevIns, pThis);
1060 return VINF_SUCCESS;
1061}
1062
1063/**
1064 * Send an ACPI battery status change event.
1065 *
1066 * @returns VBox status code
1067 * @param pInterface Pointer to the interface structure containing the
1068 * called function pointer.
1069 */
1070static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1071{
1072 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1073 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1074 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1075 DEVACPI_LOCK_R3(pDevIns, pThis);
1076
1077 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1078
1079 DEVACPI_UNLOCK(pDevIns, pThis);
1080 return VINF_SUCCESS;
1081}
1082
1083/**
1084 * Used by acpiR3PmTimer to re-arm the PM timer.
1085 *
1086 * The caller is expected to either hold the clock lock or to have made sure
1087 * the VM is resetting or loading state.
1088 *
1089 * @param pDevIns The device instance.
1090 * @param pThis The ACPI shared instance data.
1091 * @param uNow The current time.
1092 */
1093static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1094{
1095 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1096 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1097 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1098 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1099 Log(("acpi: uInterval = %RU64\n", uInterval));
1100}
1101
1102#endif /* IN_RING3 */
1103
1104/**
1105 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1106 *
1107 * The caller is expected to either hold the clock lock or to have made sure
1108 * the VM is resetting or loading state.
1109 *
1110 * @param pDevIns The PDM device instance.
1111 * @param pThis The ACPI instance
1112 * @param u64Now The current time
1113 */
1114static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1115{
1116 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1117 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1118 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1119
1120 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ,
1121 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1122 & TMR_VAL_MASK;
1123
1124 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1125 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1126}
1127
1128#ifdef IN_RING3
1129
1130/**
1131 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1132 */
1133static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1134{
1135 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1136 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1137 RT_NOREF(pTimer, pvUser);
1138
1139 DEVACPI_LOCK_R3(pDevIns, pThis);
1140 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1141 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1142 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1143 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1144 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1145 DEVACPI_UNLOCK(pDevIns, pThis);
1146
1147 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
1148}
1149
1150/**
1151 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1152 * acpiR3LoadState.
1153 *
1154 * @returns VINF_SUCCESS.
1155 * @param pThis The ACPI shared instance data.
1156 * @param pThisCC The ACPI instance data for ring-3.
1157 */
1158static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1159{
1160 uint32_t *p = pThis->au8BatteryInfo;
1161 bool fPresent; /* battery present? */
1162 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1163 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1164 uint32_t hostPresentRate; /* 0..1000 */
1165 int rc;
1166
1167 if (!pThisCC->pDrv)
1168 return VINF_SUCCESS;
1169 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1170 &hostBatteryState, &hostPresentRate);
1171 AssertRC(rc);
1172
1173 /* default values */
1174 p[BAT_STATUS_STATE] = hostBatteryState;
1175 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1176 : hostPresentRate * 50; /* mW */
1177 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1178 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1179
1180 /* did we get a valid battery state? */
1181 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1182 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1183 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1184 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1185
1186 return VINF_SUCCESS;
1187}
1188
1189/**
1190 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1191 * acpiR3LoadState.
1192 *
1193 * @returns VINF_SUCCESS.
1194 * @param pThis The ACPI shared instance data.
1195 */
1196static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1197{
1198 uint32_t *p = pThis->au8BatteryInfo;
1199
1200 p[BAT_INFO_UNITS] = 0; /* mWh */
1201 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1202 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1203 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1204 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1205 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1206 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1207 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1208 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1209
1210 return VINF_SUCCESS;
1211}
1212
1213/**
1214 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1215 *
1216 * @returns status mask or 0.
1217 * @param pThisCC The ACPI instance data for ring-3.
1218 */
1219static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1220{
1221 bool fPresent; /* battery present? */
1222 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1223 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1224 uint32_t hostPresentRate; /* 0..1000 */
1225 int rc;
1226
1227 if (!pThisCC->pDrv)
1228 return 0;
1229 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1230 &hostBatteryState, &hostPresentRate);
1231 AssertRC(rc);
1232
1233 return fPresent
1234 ? STA_DEVICE_PRESENT_MASK /* present */
1235 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1236 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1237 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1238 | STA_BATTERY_PRESENT_MASK /* battery is present */
1239 : 0; /* device not present */
1240}
1241
1242/**
1243 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1244 *
1245 * @returns status.
1246 * @param pThisCC The ACPI instance data for ring-3.
1247 */
1248static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1249{
1250 /* query the current power source from the host driver */
1251 if (!pThisCC->pDrv)
1252 return AC_ONLINE;
1253
1254 PDMACPIPOWERSOURCE ps;
1255 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1256 AssertRC(rc);
1257 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1258}
1259
1260/**
1261 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1262 */
1263static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1264{
1265 RT_NOREF(pvUser, offPort);
1266 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1267 if (cb != 4)
1268 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1269
1270 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1271 DEVACPI_LOCK_R3(pDevIns, pThis);
1272
1273 u32 >>= pThis->u8IndexShift;
1274 /* see comment at the declaration of u8IndexShift */
1275 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1276 {
1277 pThis->u8IndexShift = 2;
1278 u32 >>= 2;
1279 }
1280 Assert(u32 < BAT_INDEX_LAST);
1281 pThis->uBatteryIndex = u32;
1282
1283 DEVACPI_UNLOCK(pDevIns, pThis);
1284 return VINF_SUCCESS;
1285}
1286
1287/**
1288 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1289 */
1290static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1291{
1292 RT_NOREF(pvUser, offPort);
1293 if (cb != 4)
1294 return VERR_IOM_IOPORT_UNUSED;
1295
1296 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1297 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1298 DEVACPI_LOCK_R3(pDevIns, pThis);
1299
1300 VBOXSTRICTRC rc = VINF_SUCCESS;
1301 switch (pThis->uBatteryIndex)
1302 {
1303 case BAT_STATUS_STATE:
1304 acpiR3FetchBatteryStatus(pThis, pThisCC);
1305 RT_FALL_THRU();
1306 case BAT_STATUS_PRESENT_RATE:
1307 case BAT_STATUS_REMAINING_CAPACITY:
1308 case BAT_STATUS_PRESENT_VOLTAGE:
1309 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1310 break;
1311
1312 case BAT_INFO_UNITS:
1313 acpiR3FetchBatteryInfo(pThis);
1314 RT_FALL_THRU();
1315 case BAT_INFO_DESIGN_CAPACITY:
1316 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1317 case BAT_INFO_TECHNOLOGY:
1318 case BAT_INFO_DESIGN_VOLTAGE:
1319 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1320 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1321 case BAT_INFO_CAPACITY_GRANULARITY_1:
1322 case BAT_INFO_CAPACITY_GRANULARITY_2:
1323 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1324 break;
1325
1326 case BAT_DEVICE_STATUS:
1327 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1328 break;
1329
1330 case BAT_POWER_SOURCE:
1331 *pu32 = acpiR3GetPowerSource(pThisCC);
1332 break;
1333
1334 default:
1335 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1336 *pu32 = UINT32_MAX;
1337 break;
1338 }
1339
1340 DEVACPI_UNLOCK(pDevIns, pThis);
1341 return rc;
1342}
1343
1344/**
1345 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1346 */
1347static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1348{
1349 RT_NOREF(pvUser, offPort);
1350 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1351 if (cb != 4)
1352 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1353
1354 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1355 DEVACPI_LOCK_R3(pDevIns, pThis);
1356
1357 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1358 pThis->uSystemInfoIndex = u32;
1359 else
1360 {
1361 /* see comment at the declaration of u8IndexShift */
1362 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1363 {
1364 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1365 pThis->u8IndexShift = 2;
1366 }
1367
1368 u32 >>= pThis->u8IndexShift;
1369 Assert(u32 < SYSTEM_INFO_INDEX_END);
1370 pThis->uSystemInfoIndex = u32;
1371 }
1372
1373 DEVACPI_UNLOCK(pDevIns, pThis);
1374 return VINF_SUCCESS;
1375}
1376
1377/**
1378 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1379 */
1380static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1381{
1382 RT_NOREF(pvUser, offPort);
1383 if (cb != 4)
1384 return VERR_IOM_IOPORT_UNUSED;
1385
1386 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1387 DEVACPI_LOCK_R3(pDevIns, pThis);
1388
1389 VBOXSTRICTRC rc = VINF_SUCCESS;
1390 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1391 switch (uSystemInfoIndex)
1392 {
1393 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1394 *pu32 = pThis->cbRamLow;
1395 break;
1396
1397 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1398 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1399 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1400 break;
1401
1402 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1403 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1404 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1405 break;
1406
1407 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1408 *pu32 = pThis->u8UseIOApic;
1409 break;
1410
1411 case SYSTEM_INFO_INDEX_HPET_STATUS:
1412 *pu32 = pThis->fUseHpet
1413 ? ( STA_DEVICE_PRESENT_MASK
1414 | STA_DEVICE_ENABLED_MASK
1415 | STA_DEVICE_SHOW_IN_UI_MASK
1416 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1417 : 0;
1418 break;
1419
1420 case SYSTEM_INFO_INDEX_SMC_STATUS:
1421 *pu32 = pThis->fUseSmc
1422 ? ( STA_DEVICE_PRESENT_MASK
1423 | STA_DEVICE_ENABLED_MASK
1424 /* no need to show this device in the UI */
1425 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1426 : 0;
1427 break;
1428
1429 case SYSTEM_INFO_INDEX_FDC_STATUS:
1430 *pu32 = pThis->fUseFdc
1431 ? ( STA_DEVICE_PRESENT_MASK
1432 | STA_DEVICE_ENABLED_MASK
1433 | STA_DEVICE_SHOW_IN_UI_MASK
1434 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1435 : 0;
1436 break;
1437
1438 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1439 *pu32 = pThis->u32NicPciAddress;
1440 break;
1441
1442 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1443 *pu32 = pThis->u32AudioPciAddress;
1444 break;
1445
1446 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1447 *pu32 = pThis->u32NvmePciAddress;
1448 break;
1449
1450 case SYSTEM_INFO_INDEX_POWER_STATES:
1451 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1452 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1453 *pu32 |= RT_BIT(1);
1454 if (pThis->fS4Enabled)
1455 *pu32 |= RT_BIT(4);
1456 break;
1457
1458 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1459 *pu32 = pThis->u32IocPciAddress;
1460 break;
1461
1462 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1463 *pu32 = pThis->u32HbcPciAddress;
1464 break;
1465
1466 case SYSTEM_INFO_INDEX_PCI_BASE:
1467 /** @todo couldn't MCFG be in 64-bit range? */
1468 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1469 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1470 break;
1471
1472 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1473 /** @todo couldn't MCFG be in 64-bit range? */
1474 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1475 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1476 break;
1477
1478 case SYSTEM_INFO_INDEX_RTC_STATUS:
1479 *pu32 = pThis->fShowRtc
1480 ? ( STA_DEVICE_PRESENT_MASK
1481 | STA_DEVICE_ENABLED_MASK
1482 | STA_DEVICE_SHOW_IN_UI_MASK
1483 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1484 : 0;
1485 break;
1486
1487 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1488 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1489 {
1490 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1491 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1492 }
1493 else
1494 {
1495 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1496 pThis->idCpuLockCheck);
1497 /* Always return locked status just to be safe */
1498 *pu32 = 1;
1499 }
1500 break;
1501
1502 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1503 *pu32 = pThis->u32CpuEventType;
1504 break;
1505
1506 case SYSTEM_INFO_INDEX_CPU_EVENT:
1507 *pu32 = pThis->u32CpuEvent;
1508 break;
1509
1510 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1511 *pu32 = pThis->uSerial0IoPortBase;
1512 break;
1513
1514 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1515 *pu32 = pThis->uSerial0Irq;
1516 break;
1517
1518 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1519 *pu32 = pThis->uSerial1IoPortBase;
1520 break;
1521
1522 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1523 *pu32 = pThis->uSerial1Irq;
1524 break;
1525
1526 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1527 *pu32 = pThis->uSerial2IoPortBase;
1528 break;
1529
1530 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1531 *pu32 = pThis->uSerial2Irq;
1532 break;
1533
1534 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1535 *pu32 = pThis->uSerial3IoPortBase;
1536 break;
1537
1538 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1539 *pu32 = pThis->uSerial3Irq;
1540 break;
1541
1542 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1543 *pu32 = pThis->uParallel0IoPortBase;
1544 break;
1545
1546 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1547 *pu32 = pThis->uParallel0Irq;
1548 break;
1549
1550 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1551 *pu32 = pThis->uParallel1IoPortBase;
1552 break;
1553
1554 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1555 *pu32 = pThis->uParallel1Irq;
1556 break;
1557
1558 case SYSTEM_INFO_INDEX_END:
1559 /** @todo why isn't this setting any output value? */
1560 break;
1561
1562 /* Solaris 9 tries to read from this index */
1563 case SYSTEM_INFO_INDEX_INVALID:
1564 *pu32 = 0;
1565 break;
1566
1567 default:
1568 *pu32 = UINT32_MAX;
1569 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1570 break;
1571 }
1572
1573 DEVACPI_UNLOCK(pDevIns, pThis);
1574 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1575 return rc;
1576}
1577
1578/**
1579 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1580 */
1581static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1582{
1583 RT_NOREF(pvUser, offPort);
1584 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1585 if (cb != 4)
1586 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1587
1588 DEVACPI_LOCK_R3(pDevIns, pThis);
1589 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1590
1591 VBOXSTRICTRC rc = VINF_SUCCESS;
1592 switch (pThis->uSystemInfoIndex)
1593 {
1594 case SYSTEM_INFO_INDEX_INVALID:
1595 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1596 pThis->u8IndexShift = 0;
1597 break;
1598
1599 case SYSTEM_INFO_INDEX_VALID:
1600 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1601 pThis->u8IndexShift = 2;
1602 break;
1603
1604 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1605 pThis->idCpuLockCheck = u32;
1606 break;
1607
1608 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1609 if (u32 < pThis->cCpus)
1610 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1611 else
1612 LogRel(("ACPI: CPU %u does not exist\n", u32));
1613 break;
1614
1615 default:
1616 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1617 break;
1618 }
1619
1620 DEVACPI_UNLOCK(pDevIns, pThis);
1621 return rc;
1622}
1623
1624/**
1625 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1626 */
1627static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1628{
1629 RT_NOREF(offPort, pvUser);
1630 if (cb != 2)
1631 return VERR_IOM_IOPORT_UNUSED;
1632
1633 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1634 DEVACPI_LOCK_R3(pDevIns, pThis);
1635
1636 *pu32 = pThis->pm1a_en;
1637
1638 DEVACPI_UNLOCK(pDevIns, pThis);
1639 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1640 return VINF_SUCCESS;
1641}
1642
1643/**
1644 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1645 */
1646static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1647{
1648 RT_NOREF(offPort, pvUser);
1649 if (cb != 2 && cb != 4)
1650 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1651
1652 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1653 DEVACPI_LOCK_R3(pDevIns, pThis);
1654
1655 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1656 u32 &= ~(RSR_EN | IGN_EN);
1657 u32 &= 0xffff;
1658 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1659
1660 DEVACPI_UNLOCK(pDevIns, pThis);
1661 return VINF_SUCCESS;
1662}
1663
1664/**
1665 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1666 */
1667static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1668{
1669 RT_NOREF(offPort, pvUser);
1670 if (cb != 2)
1671 {
1672 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1673 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1674 }
1675
1676 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1677 DEVACPI_LOCK_R3(pDevIns, pThis);
1678
1679 *pu32 = pThis->pm1a_sts;
1680
1681 DEVACPI_UNLOCK(pDevIns, pThis);
1682 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1683 return VINF_SUCCESS;
1684}
1685
1686/**
1687 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1688 */
1689static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1690{
1691 RT_NOREF(offPort, pvUser);
1692 if (cb != 2 && cb != 4)
1693 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1694
1695 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1696 DEVACPI_LOCK_R3(pDevIns, pThis);
1697
1698 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1699 u32 &= 0xffff;
1700 if (u32 & PWRBTN_STS)
1701 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1702 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1703 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1704
1705 DEVACPI_UNLOCK(pDevIns, pThis);
1706 return VINF_SUCCESS;
1707}
1708
1709/**
1710 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1711 */
1712static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1713{
1714 RT_NOREF(offPort, pvUser);
1715 if (cb != 2)
1716 {
1717 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1718 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1719 }
1720
1721 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1722 DEVACPI_LOCK_R3(pDevIns, pThis);
1723
1724 *pu32 = pThis->pm1a_ctl;
1725
1726 DEVACPI_UNLOCK(pDevIns, pThis);
1727 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1728 return VINF_SUCCESS;
1729}
1730
1731/**
1732 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1733 */
1734static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1735{
1736 RT_NOREF(offPort, pvUser);
1737 if (cb != 2 && cb != 4)
1738 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1739
1740 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1741 DEVACPI_LOCK_R3(pDevIns, pThis);
1742
1743 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1744 u32 &= 0xffff;
1745 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1746
1747 VBOXSTRICTRC rc = VINF_SUCCESS;
1748 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1749 if (uSleepState != pThis->uSleepState)
1750 {
1751 pThis->uSleepState = uSleepState;
1752 switch (uSleepState)
1753 {
1754 case 0x00: /* S0 */
1755 break;
1756
1757 case 0x01: /* S1 */
1758 if (pThis->fS1Enabled)
1759 {
1760 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1761 rc = acpiR3DoSleep(pDevIns, pThis);
1762 break;
1763 }
1764 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1765 RT_FALL_THRU();
1766
1767 case 0x04: /* S4 */
1768 if (pThis->fS4Enabled)
1769 {
1770 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1771 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1772 break;
1773 }
1774 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1775 RT_FALL_THRU();
1776
1777 case 0x05: /* S5 */
1778 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1779 rc = acpiR3DoPowerOff(pDevIns);
1780 break;
1781
1782 default:
1783 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1784 break;
1785 }
1786 }
1787
1788 DEVACPI_UNLOCK(pDevIns, pThis);
1789 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1790 return rc;
1791}
1792
1793#endif /* IN_RING3 */
1794
1795/**
1796 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1797 *
1798 * @remarks The only I/O port currently implemented in all contexts.
1799 */
1800static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1801{
1802 RT_NOREF(offPort, pvUser);
1803 if (cb != 4)
1804 return VERR_IOM_IOPORT_UNUSED;
1805
1806 /*
1807 * We use the clock lock to serialize access to u64PmTimerInitial and to
1808 * make sure we get a reliable time from the clock
1809 * as well as and to prevent uPmTimerVal from being updated during read.
1810 */
1811 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1812 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1813 if (rc == VINF_SUCCESS)
1814 {
1815 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1816 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1817 *pu32 = pThis->uPmTimerVal;
1818
1819 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
1820
1821 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1822 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1823
1824#if 0
1825 /** @todo temporary: sanity check against running backwards */
1826 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1827 if (*pu32 - uOld >= 0x10000000)
1828 {
1829# if defined(IN_RING0)
1830 pThis->uPmTimeA = uOld;
1831 pThis->uPmTimeB = *pu32;
1832 return VERR_TM_TIMER_BAD_CLOCK;
1833# elif defined(IN_RING3)
1834 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1835# endif
1836 }
1837#endif
1838 }
1839 return rc;
1840}
1841
1842#ifdef IN_RING3
1843
1844/**
1845 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
1846 */
1847static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1848{
1849 RT_NOREF(offPort, pvUser);
1850 if (cb != 1)
1851 {
1852 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1853 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1854 }
1855
1856 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1857 DEVACPI_LOCK_R3(pDevIns, pThis);
1858
1859 *pu32 = pThis->gpe0_sts & 0xff;
1860
1861 DEVACPI_UNLOCK(pDevIns, pThis);
1862 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1863 return VINF_SUCCESS;
1864}
1865
1866/**
1867 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
1868 */
1869static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1870{
1871 RT_NOREF(offPort, pvUser);
1872 if (cb != 1)
1873 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1874
1875 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1876 DEVACPI_LOCK_R3(pDevIns, pThis);
1877
1878 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1879 u32 = pThis->gpe0_sts & ~u32;
1880 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1881
1882 DEVACPI_UNLOCK(pDevIns, pThis);
1883 return VINF_SUCCESS;
1884}
1885
1886/**
1887 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
1888 */
1889static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1890{
1891 RT_NOREF(offPort, pvUser);
1892 if (cb != 1)
1893 {
1894 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1895 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1896 }
1897
1898 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1899 DEVACPI_LOCK_R3(pDevIns, pThis);
1900
1901 *pu32 = pThis->gpe0_en & 0xff;
1902
1903 DEVACPI_UNLOCK(pDevIns, pThis);
1904 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1905 return VINF_SUCCESS;
1906}
1907
1908/**
1909 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
1910 */
1911static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1912{
1913 RT_NOREF(offPort, pvUser);
1914 if (cb != 1)
1915 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1916
1917 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1918 DEVACPI_LOCK_R3(pDevIns, pThis);
1919
1920 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1921 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
1922
1923 DEVACPI_UNLOCK(pDevIns, pThis);
1924 return VINF_SUCCESS;
1925}
1926
1927/**
1928 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
1929 */
1930static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1931{
1932 RT_NOREF(offPort, pvUser);
1933 Log(("acpiR3SmiWrite %#x\n", u32));
1934 if (cb != 1)
1935 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1936
1937 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1938 DEVACPI_LOCK_R3(pDevIns, pThis);
1939
1940 if (u32 == ACPI_ENABLE)
1941 pThis->pm1a_ctl |= SCI_EN;
1942 else if (u32 == ACPI_DISABLE)
1943 pThis->pm1a_ctl &= ~SCI_EN;
1944 else
1945 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1946
1947 DEVACPI_UNLOCK(pDevIns, pThis);
1948 return VINF_SUCCESS;
1949}
1950
1951/**
1952 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
1953 */
1954static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1955{
1956 RT_NOREF(offPort, pvUser);
1957 Log(("acpiR3ResetWrite: %#x\n", u32));
1958 NOREF(pvUser);
1959 if (cb != 1)
1960 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1961
1962 /* No state locking required. */
1963 VBOXSTRICTRC rc;
1964 if (u32 == ACPI_RESET_REG_VAL)
1965 {
1966 LogRel(("ACPI: Reset initiated by ACPI\n"));
1967 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
1968 }
1969 else
1970 {
1971 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1972 rc = VINF_SUCCESS;
1973 }
1974
1975 return rc;
1976}
1977
1978# ifdef DEBUG_ACPI
1979
1980/**
1981 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
1982 */
1983static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1984{
1985 NOREF(pvUser);
1986 switch (cb)
1987 {
1988 case 1:
1989 Log(("%#x\n", u32 & 0xff));
1990 break;
1991 case 2:
1992 Log(("%#6x\n", u32 & 0xffff));
1993 break;
1994 case 4:
1995 Log(("%#10x\n", u32));
1996 break;
1997 default:
1998 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1999 }
2000 return VINF_SUCCESS;
2001}
2002
2003/**
2004 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2005 */
2006static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2007{
2008 NOREF(pvUser);
2009 switch (cb)
2010 {
2011 case 1:
2012 Log(("%c", u32 & 0xff));
2013 break;
2014 default:
2015 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2016 }
2017 return VINF_SUCCESS;
2018}
2019
2020# endif /* DEBUG_ACPI */
2021
2022/**
2023 * @callback_method_impl{FNDBGFHANDLERDEV}
2024 */
2025static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2026{
2027 RT_NOREF(pszArgs);
2028 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2029 pHlp->pfnPrintf(pHlp,
2030 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2031}
2032
2033/**
2034 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2035 *
2036 * @param pDevIns The PDM device instance.
2037 * @param pThis The ACPI shared instance data.
2038 */
2039static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2040{
2041 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2042 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2043 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2044 pPciDev->abConfig[PMBA + 2] = 0x00;
2045 pPciDev->abConfig[PMBA + 3] = 0x00;
2046}
2047
2048/**
2049 * Used to calculate the value of a PM I/O port.
2050 *
2051 * @returns The actual I/O port value.
2052 * @param pThis The ACPI shared instance data.
2053 * @param offset The offset into the I/O space, or -1 if invalid.
2054 */
2055static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2056{
2057 Assert(pThis->uPmIoPortBase != 0);
2058
2059 if (offset == -1)
2060 return 0;
2061
2062 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2063}
2064
2065/**
2066 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2067 * timer and GPE0 I/O ports.
2068 *
2069 * @returns VBox status code.
2070 * @param pDevIns The device instance.
2071 * @param pThis The ACPI shared instance data.
2072 */
2073static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2074{
2075 if (pThis->uPmIoPortBase == 0)
2076 return VINF_SUCCESS;
2077
2078 int rc;
2079 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2080 AssertRCReturn(rc, rc);
2081 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2082 AssertRCReturn(rc, rc);
2083 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2084 AssertRCReturn(rc, rc);
2085 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2086 AssertRCReturn(rc, rc);
2087 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2088 AssertRCReturn(rc, rc);
2089 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2090
2091 return VINF_SUCCESS;
2092}
2093
2094/**
2095 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2096 * timer and GPE0 I/O ports.
2097 *
2098 * @returns VBox status code.
2099 * @param pDevIns The device instance.
2100 * @param pThis The ACPI shared instance data.
2101 */
2102static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2103{
2104 if (pThis->uPmIoPortBase != 0)
2105 {
2106 int rc;
2107 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2108 AssertRCReturn(rc, rc);
2109 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2110 AssertRCReturn(rc, rc);
2111 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2112 AssertRCReturn(rc, rc);
2113 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2114 AssertRCReturn(rc, rc);
2115 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2116 AssertRCReturn(rc, rc);
2117 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2118 AssertRCReturn(rc, rc);
2119 }
2120 return VINF_SUCCESS;
2121}
2122
2123/**
2124 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2125 * PM1a, PM timer and GPE0 ports.
2126 *
2127 * @returns VBox status code.
2128 *
2129 * @param pDevIns The device instance.
2130 * @param pThis The ACPI shared instance data.
2131 * @param pThisCC The ACPI instance data for ring-3.
2132 * @param NewIoPortBase The new base address of the I/O ports.
2133 */
2134static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2135{
2136 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2137 if (NewIoPortBase != pThis->uPmIoPortBase)
2138 {
2139 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2140 if (RT_FAILURE(rc))
2141 return rc;
2142
2143 pThis->uPmIoPortBase = NewIoPortBase;
2144
2145 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2146 if (RT_FAILURE(rc))
2147 return rc;
2148
2149 /* We have to update FADT table acccording to the new base */
2150 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2151 AssertRC(rc);
2152 if (RT_FAILURE(rc))
2153 return rc;
2154 }
2155
2156 return VINF_SUCCESS;
2157}
2158
2159/**
2160 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2161 */
2162static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2163{
2164 RT_NOREF(pvUser);
2165 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2166
2167 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2168 uint8_t off = offPort & 0x000f;
2169 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2170 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2171 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2172
2173 DEVACPI_LOCK_R3(pDevIns, pThis);
2174 switch (off)
2175 {
2176 case SMBHSTSTS_OFF:
2177 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2178 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2179 break;
2180 case SMBSLVSTS_OFF:
2181 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2182 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2183 break;
2184 case SMBHSTCNT_OFF:
2185 {
2186 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2187
2188 const bool old_level = acpiSCILevel(pDevIns, pThis);
2189 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2190 if (u32 & SMBHSTCNT_START)
2191 {
2192 /* Start, trigger error as this is a dummy implementation */
2193 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2194 }
2195 if (u32 & SMBHSTCNT_KILL)
2196 {
2197 /* Kill */
2198 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2199 }
2200 const bool new_level = acpiSCILevel(pDevIns, pThis);
2201
2202 LogFunc(("old=%x new=%x\n", old_level, new_level));
2203
2204 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2205 * needs to be implemented later if it ever becomes relevant. */
2206 if (new_level != old_level)
2207 acpiSetIrq(pDevIns, new_level);
2208 break;
2209 }
2210 case SMBHSTCMD_OFF:
2211 pThis->u8SMBusHstCmd = u32;
2212 break;
2213 case SMBHSTADD_OFF:
2214 pThis->u8SMBusHstAdd = u32;
2215 break;
2216 case SMBHSTDAT0_OFF:
2217 pThis->u8SMBusHstDat0 = u32;
2218 break;
2219 case SMBHSTDAT1_OFF:
2220 pThis->u8SMBusHstDat1 = u32;
2221 break;
2222 case SMBBLKDAT_OFF:
2223 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2224 pThis->u8SMBusBlkIdx++;
2225 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2226 break;
2227 case SMBSLVCNT_OFF:
2228 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2229 break;
2230 case SMBSHDWCMD_OFF:
2231 /* readonly register */
2232 break;
2233 case SMBSLVEVT_OFF:
2234 pThis->u16SMBusSlvEvt = u32;
2235 break;
2236 case SMBSLVDAT_OFF:
2237 /* readonly register */
2238 break;
2239 default:
2240 /* caught by the sanity check above */
2241 ;
2242 }
2243
2244 DEVACPI_UNLOCK(pDevIns, pThis);
2245 return VINF_SUCCESS;
2246}
2247
2248/**
2249 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2250 */
2251static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2252{
2253 RT_NOREF(pvUser);
2254 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2255
2256 VBOXSTRICTRC rc = VINF_SUCCESS;
2257 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2258 uint8_t const off = offPort & 0x000f;
2259 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2260 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2261 return VERR_IOM_IOPORT_UNUSED;
2262
2263 DEVACPI_LOCK_R3(pDevIns, pThis);
2264 switch (off)
2265 {
2266 case SMBHSTSTS_OFF:
2267 *pu32 = pThis->u8SMBusHstSts;
2268 break;
2269 case SMBSLVSTS_OFF:
2270 *pu32 = pThis->u8SMBusSlvSts;
2271 break;
2272 case SMBHSTCNT_OFF:
2273 pThis->u8SMBusBlkIdx = 0;
2274 *pu32 = pThis->u8SMBusHstCnt;
2275 break;
2276 case SMBHSTCMD_OFF:
2277 *pu32 = pThis->u8SMBusHstCmd;
2278 break;
2279 case SMBHSTADD_OFF:
2280 *pu32 = pThis->u8SMBusHstAdd;
2281 break;
2282 case SMBHSTDAT0_OFF:
2283 *pu32 = pThis->u8SMBusHstDat0;
2284 break;
2285 case SMBHSTDAT1_OFF:
2286 *pu32 = pThis->u8SMBusHstDat1;
2287 break;
2288 case SMBBLKDAT_OFF:
2289 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2290 pThis->u8SMBusBlkIdx++;
2291 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2292 break;
2293 case SMBSLVCNT_OFF:
2294 *pu32 = pThis->u8SMBusSlvCnt;
2295 break;
2296 case SMBSHDWCMD_OFF:
2297 *pu32 = pThis->u8SMBusShdwCmd;
2298 break;
2299 case SMBSLVEVT_OFF:
2300 *pu32 = pThis->u16SMBusSlvEvt;
2301 break;
2302 case SMBSLVDAT_OFF:
2303 *pu32 = pThis->u16SMBusSlvDat;
2304 break;
2305 default:
2306 /* caught by the sanity check above */
2307 rc = VERR_IOM_IOPORT_UNUSED;
2308 }
2309 DEVACPI_UNLOCK(pDevIns, pThis);
2310
2311 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2312 return rc;
2313}
2314
2315/**
2316 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2317 *
2318 * @param pDevIns The PDM device instance.
2319 * @param pThis The ACPI shared instance data.
2320 */
2321static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2322{
2323 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2324 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2325 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2326 pPciDev->abConfig[SMBBA+2] = 0x00;
2327 pPciDev->abConfig[SMBBA+3] = 0x00;
2328 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2329 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2330 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2331 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2332 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2333}
2334
2335/**
2336 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2337 *
2338 * @param pThis The ACPI shared instance data.
2339 */
2340static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2341{
2342 pThis->u8SMBusHstSts = 0x00;
2343 pThis->u8SMBusSlvSts = 0x00;
2344 pThis->u8SMBusHstCnt = 0x00;
2345 pThis->u8SMBusHstCmd = 0x00;
2346 pThis->u8SMBusHstAdd = 0x00;
2347 pThis->u8SMBusHstDat0 = 0x00;
2348 pThis->u8SMBusHstDat1 = 0x00;
2349 pThis->u8SMBusSlvCnt = 0x00;
2350 pThis->u8SMBusShdwCmd = 0x00;
2351 pThis->u16SMBusSlvEvt = 0x0000;
2352 pThis->u16SMBusSlvDat = 0x0000;
2353 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2354 pThis->u8SMBusBlkIdx = 0;
2355}
2356
2357/**
2358 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2359 *
2360 * @returns VBox status code.
2361 * @param pDevIns The device instance.
2362 * @param pThis The ACPI shared instance data.
2363 */
2364static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2365{
2366 if (pThis->uSMBusIoPortBase != 0)
2367 {
2368 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2369 AssertRCReturn(rc, rc);
2370 }
2371 return VINF_SUCCESS;
2372}
2373
2374/**
2375 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2376 *
2377 * @returns VBox status code.
2378 * @param pDevIns The device instance.
2379 * @param pThis The ACPI shared instance data.
2380 */
2381static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2382{
2383 if (pThis->uSMBusIoPortBase != 0)
2384 {
2385 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2386 AssertRCReturn(rc, rc);
2387 }
2388 return VINF_SUCCESS;
2389}
2390
2391/**
2392 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2393 * SMBus ports.
2394 *
2395 * @returns VBox status code.
2396 *
2397 * @param pDevIns The device instance.
2398 * @param pThis The ACPI shared instance data.
2399 * @param NewIoPortBase The new base address of the I/O ports.
2400 */
2401static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2402{
2403 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2404 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2405 {
2406 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2407 AssertRCReturn(rc, rc);
2408
2409 pThis->uSMBusIoPortBase = NewIoPortBase;
2410
2411 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2412 AssertRCReturn(rc, rc);
2413
2414#if 0 /* is there an FADT table entry for the SMBus base? */
2415 /* We have to update FADT table acccording to the new base */
2416 rc = acpiR3PlantTables(pThis);
2417 AssertRC(rc);
2418 if (RT_FAILURE(rc))
2419 return rc;
2420#endif
2421 }
2422
2423 return VINF_SUCCESS;
2424}
2425
2426
2427/**
2428 * Saved state structure description, version 4.
2429 */
2430static const SSMFIELD g_AcpiSavedStateFields4[] =
2431{
2432 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2433 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2434 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2435 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2436 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2437 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2438 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2439 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2440 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2441 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2442 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2443 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2444 SSMFIELD_ENTRY_TERM()
2445};
2446
2447/**
2448 * Saved state structure description, version 5.
2449 */
2450static const SSMFIELD g_AcpiSavedStateFields5[] =
2451{
2452 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2453 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2454 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2455 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2456 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2457 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2458 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2459 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2460 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2461 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2462 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2463 SSMFIELD_ENTRY_TERM()
2464};
2465
2466/**
2467 * Saved state structure description, version 6.
2468 */
2469static const SSMFIELD g_AcpiSavedStateFields6[] =
2470{
2471 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2472 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2473 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2474 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2475 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2476 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2477 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2478 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2479 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2480 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2481 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2482 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2483 SSMFIELD_ENTRY_TERM()
2484};
2485
2486/**
2487 * Saved state structure description, version 7.
2488 */
2489static const SSMFIELD g_AcpiSavedStateFields7[] =
2490{
2491 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2492 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2493 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2494 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2495 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2496 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2497 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2498 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2499 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2500 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2501 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2502 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2503 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2504 SSMFIELD_ENTRY_TERM()
2505};
2506
2507/**
2508 * Saved state structure description, version 8.
2509 */
2510static const SSMFIELD g_AcpiSavedStateFields8[] =
2511{
2512 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2513 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2514 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2515 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2516 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2517 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2518 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2519 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2520 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2521 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2522 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2523 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2524 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2525 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2526 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2527 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2528 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2529 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2530 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2531 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2532 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2533 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2534 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2535 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2536 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2537 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2538 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2539 SSMFIELD_ENTRY_TERM()
2540};
2541
2542/**
2543 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2544 */
2545static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2546{
2547 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2548 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2549 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2550}
2551
2552/**
2553 * @callback_method_impl{FNSSMDEVLOADEXEC}
2554 */
2555static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2556{
2557 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2558 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2559 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2560 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2561
2562 /*
2563 * Unmap PM I/O ports, will remap it with the actual base after state
2564 * successfully loaded.
2565 */
2566 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2567 AssertRCReturn(rc, rc);
2568
2569 /*
2570 * Unregister SMBus handlers, will register with actual base after state
2571 * successfully loaded.
2572 */
2573 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2574 AssertRCReturn(rc, rc);
2575 acpiR3SMBusResetDevice(pThis);
2576
2577 switch (uVersion)
2578 {
2579 case 4:
2580 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2581 break;
2582 case 5:
2583 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2584 break;
2585 case 6:
2586 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2587 break;
2588 case 7:
2589 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2590 break;
2591 case 8:
2592 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2593 break;
2594 default:
2595 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2596 break;
2597 }
2598 if (RT_SUCCESS(rc))
2599 {
2600 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2601 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2602 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2603 AssertRCReturn(rc, rc);
2604 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2605 AssertRCReturn(rc, rc);
2606 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2607 AssertRCReturn(rc, rc);
2608 rc = acpiR3FetchBatteryInfo(pThis);
2609 AssertRCReturn(rc, rc);
2610
2611 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2612 DEVACPI_LOCK_R3(pDevIns, pThis);
2613 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2614 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2615 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2616 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2617 DEVACPI_UNLOCK(pDevIns, pThis);
2618 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2619 }
2620 return rc;
2621}
2622
2623/**
2624 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2625 */
2626static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2627{
2628 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2629 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2630 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2631 return NULL;
2632}
2633
2634/**
2635 * Calculate the check sum for some ACPI data before planting it.
2636 *
2637 * All the bytes must add up to 0.
2638 *
2639 * @returns check sum.
2640 * @param pvSrc What to check sum.
2641 * @param cbData The amount of data to checksum.
2642 */
2643static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2644{
2645 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2646 uint8_t uSum = 0;
2647 for (size_t i = 0; i < cbData; ++i)
2648 uSum += pbSrc[i];
2649 return -uSum;
2650}
2651
2652/**
2653 * Prepare a ACPI table header.
2654 */
2655static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2656 const char au8Signature[4],
2657 uint32_t u32Length, uint8_t u8Revision)
2658{
2659 memcpy(header->au8Signature, au8Signature, 4);
2660 header->u32Length = RT_H2LE_U32(u32Length);
2661 header->u8Revision = u8Revision;
2662 memcpy(header->au8OemId, pThis->au8OemId, 6);
2663 memcpy(header->au8OemTabId, "VBOX", 4);
2664 memcpy(header->au8OemTabId+4, au8Signature, 4);
2665 header->u32OemRevision = RT_H2LE_U32(1);
2666 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2667 header->u32CreatorRev = pThis->u32CreatorRev;
2668}
2669
2670/**
2671 * Initialize a generic address structure (ACPIGENADDR).
2672 */
2673static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2674 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2675 uint8_t u8AccessSize, uint64_t u64Address)
2676{
2677 g->u8AddressSpaceId = u8AddressSpaceId;
2678 g->u8RegisterBitWidth = u8RegisterBitWidth;
2679 g->u8RegisterBitOffset = u8RegisterBitOffset;
2680 g->u8AccessSize = u8AccessSize;
2681 g->u64Address = RT_H2LE_U64(u64Address);
2682}
2683
2684/**
2685 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2686 */
2687DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2688{
2689 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2690}
2691
2692/**
2693 * Plant the Differentiated System Description Table (DSDT).
2694 */
2695static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2696{
2697 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2698}
2699
2700/**
2701 * Plant the Secondary System Description Table (SSDT).
2702 */
2703static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2704{
2705 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2706}
2707
2708/**
2709 * Plant the Firmware ACPI Control Structure (FACS).
2710 */
2711static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2712{
2713 ACPITBLFACS facs;
2714
2715 memset(&facs, 0, sizeof(facs));
2716 memcpy(facs.au8Signature, "FACS", 4);
2717 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2718 facs.u32HWSignature = RT_H2LE_U32(0);
2719 facs.u32FWVector = RT_H2LE_U32(0);
2720 facs.u32GlobalLock = RT_H2LE_U32(0);
2721 facs.u32Flags = RT_H2LE_U32(0);
2722 facs.u64X_FWVector = RT_H2LE_U64(0);
2723 facs.u8Version = 1;
2724
2725 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2726}
2727
2728/**
2729 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2730 */
2731static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2732 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2733{
2734 ACPITBLFADT fadt;
2735
2736 /* First the ACPI version 2+ version of the structure. */
2737 memset(&fadt, 0, sizeof(fadt));
2738 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2739 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2740 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2741 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2742 fadt.u8PreferredPMProfile = 0; /* unspecified */
2743 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2744 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2745 fadt.u8AcpiEnable = ACPI_ENABLE;
2746 fadt.u8AcpiDisable = ACPI_DISABLE;
2747 fadt.u8S4BIOSReq = 0;
2748 fadt.u8PStateCnt = 0;
2749 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2750 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2751 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2752 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2753 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2754 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2755 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2756 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2757 fadt.u8PM1EVTLEN = 4;
2758 fadt.u8PM1CTLLEN = 2;
2759 fadt.u8PM2CTLLEN = 0;
2760 fadt.u8PMTMLEN = 4;
2761 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2762 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2763 fadt.u8GPE1BASE = GPE1_BASE;
2764 fadt.u8CSTCNT = 0;
2765 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2766 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2767 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2768 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2769 fadt.u8DutyOffset = 0;
2770 fadt.u8DutyWidth = 0;
2771 fadt.u8DayAlarm = 0;
2772 fadt.u8MonAlarm = 0;
2773 fadt.u8Century = 0;
2774 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2775 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2776 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2777 | FADT_FL_FIX_RTC
2778 | FADT_FL_TMR_VAL_EXT
2779 | FADT_FL_RESET_REG_SUP);
2780
2781 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2782 if (pThis->fCpuHotPlug)
2783 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2784
2785 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2786 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2787 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2788 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2789 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2790 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2791 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2792 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2793 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2794 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2795 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2796 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2797 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2798 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2799
2800 /* Now the ACPI 1.0 version. */
2801 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2802 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2803 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2804 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2805 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2806}
2807
2808/**
2809 * Plant the root System Description Table.
2810 *
2811 * The RSDT and XSDT tables are basically identical. The only difference is 32
2812 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2813 * ACPI 2.0 and up.
2814 */
2815static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2816{
2817 ACPITBLRSDT *rsdt;
2818 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2819
2820 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2821 if (!rsdt)
2822 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2823
2824 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2825 for (unsigned int i = 0; i < nb_entries; ++i)
2826 {
2827 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2828 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2829 }
2830 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2831 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2832 RTMemFree(rsdt);
2833 return VINF_SUCCESS;
2834}
2835
2836/**
2837 * Plant the Extended System Description Table.
2838 */
2839static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2840{
2841 ACPITBLXSDT *xsdt;
2842 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2843 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
2844 if (!xsdt)
2845 return VERR_NO_TMP_MEMORY;
2846
2847 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
2848
2849 if (pThis->cCustTbls > 0)
2850 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2851
2852 for (unsigned int i = 0; i < nb_entries; ++i)
2853 {
2854 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2855 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2856 }
2857 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
2858 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
2859
2860 RTMemFree(xsdt);
2861 return VINF_SUCCESS;
2862}
2863
2864/**
2865 * Plant the Root System Description Pointer (RSDP).
2866 */
2867static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2868{
2869 memset(rsdp, 0, sizeof(*rsdp));
2870
2871 /* ACPI 1.0 part (RSDT) */
2872 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2873 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2874 rsdp->u8Revision = ACPI_REVISION;
2875 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2876 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2877
2878 /* ACPI 2.0 part (XSDT) */
2879 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2880 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2881 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2882}
2883
2884/**
2885 * Multiple APIC Description Table.
2886 *
2887 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2888 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2889 * use regular C structure and proxy to raw memory instead.
2890 */
2891class AcpiTableMadt
2892{
2893 /**
2894 * All actual data stored in dynamically allocated memory pointed by this field.
2895 */
2896 uint8_t *m_pbData;
2897 /**
2898 * Number of CPU entries in this MADT.
2899 */
2900 uint32_t m_cCpus;
2901
2902 /**
2903 * Number of interrupt overrides.
2904 */
2905 uint32_t m_cIsos;
2906
2907public:
2908 /**
2909 * Address of ACPI header
2910 */
2911 inline ACPITBLHEADER *header_addr(void) const
2912 {
2913 return (ACPITBLHEADER *)m_pbData;
2914 }
2915
2916 /**
2917 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2918 * although address is the same for all of them.
2919 */
2920 inline uint32_t *u32LAPIC_addr(void) const
2921 {
2922 return (uint32_t *)(header_addr() + 1);
2923 }
2924
2925 /**
2926 * Address of APIC flags
2927 */
2928 inline uint32_t *u32Flags_addr(void) const
2929 {
2930 return (uint32_t *)(u32LAPIC_addr() + 1);
2931 }
2932
2933 /**
2934 * Address of ISO description
2935 */
2936 inline ACPITBLISO *ISO_addr(void) const
2937 {
2938 return (ACPITBLISO *)(u32Flags_addr() + 1);
2939 }
2940
2941 /**
2942 * Address of per-CPU LAPIC descriptions
2943 */
2944 inline ACPITBLLAPIC *LApics_addr(void) const
2945 {
2946 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2947 }
2948
2949 /**
2950 * Address of IO APIC description
2951 */
2952 inline ACPITBLIOAPIC *IOApic_addr(void) const
2953 {
2954 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2955 }
2956
2957 /**
2958 * Size of MADT.
2959 * Note that this function assumes IOApic to be the last field in structure.
2960 */
2961 inline uint32_t size(void) const
2962 {
2963 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2964 }
2965
2966 /**
2967 * Raw data of MADT.
2968 */
2969 inline const uint8_t *data(void) const
2970 {
2971 return m_pbData;
2972 }
2973
2974 /**
2975 * Size of MADT for given ACPI config, useful to compute layout.
2976 */
2977 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
2978 {
2979 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2980 }
2981
2982 /*
2983 * Constructor, only works in Ring 3, doesn't look like a big deal.
2984 */
2985 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2986 {
2987 m_cCpus = cCpus;
2988 m_cIsos = cIsos;
2989 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2990 uint32_t cb = size();
2991 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2992 }
2993
2994 ~AcpiTableMadt()
2995 {
2996 RTMemFree(m_pbData);
2997 }
2998};
2999
3000
3001/**
3002 * Plant the Multiple APIC Description Table (MADT).
3003 *
3004 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3005 *
3006 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3007 */
3008static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3009{
3010 uint16_t cpus = pThis->cCpus;
3011 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3012
3013 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3014
3015 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3016 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3017
3018 /* LAPICs records */
3019 ACPITBLLAPIC* lapic = madt.LApics_addr();
3020 for (uint16_t i = 0; i < cpus; i++)
3021 {
3022 lapic->u8Type = 0;
3023 lapic->u8Length = sizeof(ACPITBLLAPIC);
3024 lapic->u8ProcId = i;
3025 /** Must match numbering convention in MPTABLES */
3026 lapic->u8ApicId = i;
3027 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3028 lapic++;
3029 }
3030
3031 /* IO-APIC record */
3032 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3033 ioapic->u8Type = 1;
3034 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3035 /** Must match MP tables ID */
3036 ioapic->u8IOApicId = cpus;
3037 ioapic->u8Reserved = 0;
3038 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3039 ioapic->u32GSIB = RT_H2LE_U32(0);
3040
3041 /* Interrupt Source Overrides */
3042 /* Flags:
3043 bits[3:2]:
3044 00 conforms to the bus
3045 01 edge-triggered
3046 10 reserved
3047 11 level-triggered
3048 bits[1:0]
3049 00 conforms to the bus
3050 01 active-high
3051 10 reserved
3052 11 active-low */
3053 /* If changing, also update PDMIsaSetIrq() and MPS */
3054 ACPITBLISO* isos = madt.ISO_addr();
3055 /* Timer interrupt rule IRQ0 to GSI2 */
3056 isos[0].u8Type = 2;
3057 isos[0].u8Length = sizeof(ACPITBLISO);
3058 isos[0].u8Bus = 0; /* Must be 0 */
3059 isos[0].u8Source = 0; /* IRQ0 */
3060 isos[0].u32GSI = 2; /* connected to pin 2 */
3061 isos[0].u16Flags = 0; /* conform to the bus */
3062
3063 /* ACPI interrupt rule - IRQ9 to GSI9 */
3064 isos[1].u8Type = 2;
3065 isos[1].u8Length = sizeof(ACPITBLISO);
3066 isos[1].u8Bus = 0; /* Must be 0 */
3067 isos[1].u8Source = 9; /* IRQ9 */
3068 isos[1].u32GSI = 9; /* connected to pin 9 */
3069 isos[1].u16Flags = 0xf; /* active low, level triggered */
3070 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3071
3072 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3073 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3074}
3075
3076/**
3077 * Plant the High Performance Event Timer (HPET) descriptor.
3078 */
3079static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3080{
3081 ACPITBLHPET hpet;
3082
3083 memset(&hpet, 0, sizeof(hpet));
3084
3085 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3086 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3087 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3088 0 /* Memory address space */,
3089 64 /* Register bit width */,
3090 0 /* Bit offset */,
3091 0, /* Register access size, is it correct? */
3092 0xfed00000 /* Address */);
3093
3094 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3095 hpet.u32Number = 0;
3096 hpet.u32MinTick = 4096;
3097 hpet.u8Attributes = 0;
3098
3099 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3100
3101 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3102}
3103
3104
3105/**
3106 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3107 * descriptor.
3108 *
3109 * @param pDevIns The device instance.
3110 * @param pThis The ACPI shared instance data.
3111 * @param GCPhysDst Where to plant it.
3112 */
3113static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3114{
3115 struct
3116 {
3117 ACPITBLMCFG hdr;
3118 ACPITBLMCFGENTRY entry;
3119 } tbl;
3120 uint8_t u8StartBus = 0;
3121 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3122
3123 RT_ZERO(tbl);
3124
3125 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3126 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3127 tbl.entry.u8StartBus = u8StartBus;
3128 tbl.entry.u8EndBus = u8EndBus;
3129 // u16PciSegmentGroup must match _SEG in ACPI table
3130
3131 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3132
3133 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3134}
3135
3136/**
3137 * Used by acpiR3PlantTables and acpiConstruct.
3138 *
3139 * @returns Guest memory address.
3140 */
3141static uint32_t apicR3FindRsdpSpace(void)
3142{
3143 return 0xe0000;
3144}
3145
3146/**
3147 * Called by acpiR3Construct to read and allocate a custom ACPI table
3148 *
3149 * @param pDevIns The device instance.
3150 * @param ppu8CustBin Address to receive the address of the table
3151 * @param pcbCustBin Address to receive the size of the the table.
3152 * @param pszCustBinFile
3153 * @param cbBufAvail Maximum space in bytes available for the custom
3154 * table (including header).
3155 */
3156static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3157 char *pszCustBinFile, uint32_t cbBufAvail)
3158{
3159 RTFILE FileCUSTBin;
3160 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3161 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3162 if (RT_SUCCESS(rc))
3163 {
3164 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3165 if (RT_SUCCESS(rc))
3166 {
3167 /* The following checks should be in sync the AssertReleaseMsg's below. */
3168 if ( *pcbCustBin > cbBufAvail
3169 || *pcbCustBin < sizeof(ACPITBLHEADER))
3170 rc = VERR_TOO_MUCH_DATA;
3171
3172 /*
3173 * Allocate buffer for the custom table binary data.
3174 */
3175 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3176 if (*ppu8CustBin)
3177 {
3178 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3179 if (RT_FAILURE(rc))
3180 {
3181 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3182 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3183 *ppu8CustBin = NULL;
3184 }
3185 }
3186 else
3187 {
3188 rc = VERR_NO_MEMORY;
3189 }
3190 RTFileClose(FileCUSTBin);
3191 }
3192 }
3193 return rc;
3194}
3195
3196/**
3197 * Create the ACPI tables in guest memory.
3198 */
3199static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3200{
3201 int rc;
3202 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3203 RTGCPHYS32 GCPhysHpet = 0;
3204 RTGCPHYS32 GCPhysApic = 0;
3205 RTGCPHYS32 GCPhysSsdt = 0;
3206 RTGCPHYS32 GCPhysMcfg = 0;
3207 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3208 uint32_t addend = 0;
3209 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3210 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3211 uint32_t cAddr;
3212 uint32_t iMadt = 0;
3213 uint32_t iHpet = 0;
3214 uint32_t iSsdt = 0;
3215 uint32_t iMcfg = 0;
3216 uint32_t iCust = 0;
3217 size_t cbRsdt = sizeof(ACPITBLHEADER);
3218 size_t cbXsdt = sizeof(ACPITBLHEADER);
3219
3220 cAddr = 1; /* FADT */
3221 if (pThis->u8UseIOApic)
3222 iMadt = cAddr++; /* MADT */
3223
3224 if (pThis->fUseHpet)
3225 iHpet = cAddr++; /* HPET */
3226
3227 if (pThis->fUseMcfg)
3228 iMcfg = cAddr++; /* MCFG */
3229
3230 if (pThis->cCustTbls > 0)
3231 {
3232 iCust = cAddr; /* CUST */
3233 cAddr += pThis->cCustTbls;
3234 }
3235
3236 iSsdt = cAddr++; /* SSDT */
3237
3238 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3239 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3240
3241 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3242 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3243
3244 /*
3245 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3246 * The latter starts never below 4G.
3247 */
3248 PVM pVM = PDMDevHlpGetVM(pDevIns);
3249 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3250 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3251
3252 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3253 if (pThis->fPciPref64Enabled)
3254 {
3255 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3256 if (pThis->u64PciPref64Max > u64PciPref64Min)
3257 {
3258 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3259 pThis->u64PciPref64Min = u64PciPref64Min;
3260 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3261 u64PciPref64Min, pThis->u64PciPref64Max-1));
3262 }
3263 else
3264 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3265 u64PciPref64Min, pThis->u64PciPref64Max-1));
3266 }
3267 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3268 {
3269 /* Note: This is also enforced by DevPcBios.cpp. */
3270 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3271 cbBelow4GB = UINT32_C(0xfe000000);
3272 }
3273 pThis->cbRamLow = cbBelow4GB;
3274
3275 GCPhysCur = 0;
3276 GCPhysRsdt = GCPhysCur;
3277
3278 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3279 GCPhysXsdt = GCPhysCur;
3280
3281 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3282 GCPhysFadtAcpi1 = GCPhysCur;
3283
3284 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3285 GCPhysFadtAcpi2 = GCPhysCur;
3286
3287 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3288 GCPhysFacs = GCPhysCur;
3289
3290 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3291 if (pThis->u8UseIOApic)
3292 {
3293 GCPhysApic = GCPhysCur;
3294 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3295 }
3296 if (pThis->fUseHpet)
3297 {
3298 GCPhysHpet = GCPhysCur;
3299 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3300 }
3301 if (pThis->fUseMcfg)
3302 {
3303 GCPhysMcfg = GCPhysCur;
3304 /* Assume one entry */
3305 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3306 }
3307
3308 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3309 {
3310 aGCPhysCust[i] = GCPhysCur;
3311 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3312 }
3313
3314 void *pvSsdtCode = NULL;
3315 size_t cbSsdt = 0;
3316 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3317 if (RT_FAILURE(rc))
3318 return rc;
3319
3320 GCPhysSsdt = GCPhysCur;
3321 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3322
3323 GCPhysDsdt = GCPhysCur;
3324
3325 void *pvDsdtCode = NULL;
3326 size_t cbDsdt = 0;
3327 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3328 if (RT_FAILURE(rc))
3329 return rc;
3330
3331 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3332
3333 if (GCPhysCur > 0x10000)
3334 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3335 N_("Error: ACPI tables bigger than 64KB"));
3336
3337 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3338 addend = pThis->cbRamLow - 0x10000;
3339 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3340 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3341 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3342 if (pThis->u8UseIOApic)
3343 Log((" MADT 0x%08X", GCPhysApic + addend));
3344 if (pThis->fUseHpet)
3345 Log((" HPET 0x%08X", GCPhysHpet + addend));
3346 if (pThis->fUseMcfg)
3347 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3348 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3349 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3350 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3351 Log(("\n"));
3352
3353 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3354 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3355 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3356 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3357 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3358
3359 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3360 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3361 if (pThis->u8UseIOApic)
3362 {
3363 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3364 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3365 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3366 }
3367 if (pThis->fUseHpet)
3368 {
3369 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3370 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3371 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3372 }
3373 if (pThis->fUseMcfg)
3374 {
3375 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3376 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3377 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3378 }
3379 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3380 {
3381 Assert(i < MAX_CUST_TABLES);
3382 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3383 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3384 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3385 uint8_t* pSig = pThisCC->apu8CustBin[i];
3386 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3387 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3388 }
3389
3390 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3391 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3392 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3393 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3394
3395 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3396 if (RT_FAILURE(rc))
3397 return rc;
3398 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3399}
3400
3401/**
3402 * @callback_method_impl{FNPCICONFIGREAD}
3403 */
3404static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3405 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3406{
3407 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3408 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3409 return rcStrict;
3410}
3411
3412/**
3413 * @callback_method_impl{FNPCICONFIGWRITE}
3414 */
3415static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3416 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3417{
3418 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3419 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3420
3421 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3422 DEVACPI_LOCK_R3(pDevIns, pThis);
3423
3424 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3425 {
3426 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3427 u32Value = SCI_INT;
3428 }
3429
3430 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3431
3432 /* Assume that the base address is only changed when the corresponding
3433 * hardware functionality is disabled. The IO region is mapped when the
3434 * functionality is enabled by the guest. */
3435
3436 if (uAddress == PMREGMISC)
3437 {
3438 RTIOPORT NewIoPortBase = 0;
3439 /* Check Power Management IO Space Enable (PMIOSE) bit */
3440 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3441 {
3442 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3443 NewIoPortBase &= 0xffc0;
3444 }
3445
3446 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
3447 AssertRC(rc);
3448 }
3449
3450 if (uAddress == SMBHSTCFG)
3451 {
3452 RTIOPORT NewIoPortBase = 0;
3453 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3454 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3455 {
3456 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3457 NewIoPortBase &= 0xfff0;
3458 }
3459
3460 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3461 AssertRC(rc);
3462 }
3463
3464 DEVACPI_UNLOCK(pDevIns, pThis);
3465 return rcStrict;
3466}
3467
3468/**
3469 * Attach a new CPU.
3470 *
3471 * @returns VBox status code.
3472 * @param pDevIns The device instance.
3473 * @param iLUN The logical unit which is being attached.
3474 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3475 *
3476 * @remarks This code path is not used during construction.
3477 */
3478static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3479{
3480 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3481 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3482 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3483
3484 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3485 ("Hot-plug flag is not set\n"),
3486 VERR_NOT_SUPPORTED);
3487 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3488
3489 /* Check if it was already attached */
3490 int rc = VINF_SUCCESS;
3491 DEVACPI_LOCK_R3(pDevIns, pThis);
3492 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3493 {
3494 PPDMIBASE IBaseTmp;
3495 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3496 if (RT_SUCCESS(rc))
3497 {
3498 /* Enable the CPU */
3499 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3500
3501 /*
3502 * Lock the CPU because we don't know if the guest will use it or not.
3503 * Prevents ejection while the CPU is still used
3504 */
3505 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3506 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3507 pThis->u32CpuEvent = iLUN;
3508
3509 /* Notify the guest */
3510 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3511 }
3512 }
3513 DEVACPI_UNLOCK(pDevIns, pThis);
3514 return rc;
3515}
3516
3517/**
3518 * Detach notification.
3519 *
3520 * @param pDevIns The device instance.
3521 * @param iLUN The logical unit which is being detached.
3522 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3523 */
3524static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3525{
3526 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3527
3528 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3529
3530 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3531 ("Hot-plug flag is not set\n"));
3532
3533 /* Check if it was already detached */
3534 DEVACPI_LOCK_R3(pDevIns, pThis);
3535 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3536 {
3537 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3538 {
3539 /* Disable the CPU */
3540 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3541 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3542 pThis->u32CpuEvent = iLUN;
3543
3544 /* Notify the guest */
3545 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3546 }
3547 else
3548 AssertMsgFailed(("CPU is still locked by the guest\n"));
3549 }
3550 DEVACPI_UNLOCK(pDevIns, pThis);
3551}
3552
3553/**
3554 * @interface_method_impl{PDMDEVREG,pfnResume}
3555 */
3556static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3557{
3558 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3559 if (pThis->fSetWakeupOnResume)
3560 {
3561 Log(("acpiResume: setting WAK_STS\n"));
3562 pThis->fSetWakeupOnResume = false;
3563 pThis->pm1a_sts |= WAK_STS;
3564 }
3565}
3566
3567/**
3568 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3569 */
3570static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3571{
3572 RT_NOREF(enmCtx);
3573 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3574 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3575 acpiR3PlantTables(pDevIns, pThis, pThisCC);
3576}
3577
3578/**
3579 * @interface_method_impl{PDMDEVREG,pfnReset}
3580 */
3581static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3582{
3583 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3584 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3585
3586 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3587 acpiSetIrq(pDevIns, 0);
3588
3589 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3590 pThis->pm1a_en = 0;
3591 pThis->pm1a_sts = 0;
3592 pThis->pm1a_ctl = 0;
3593 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3594 pThis->uPmTimerVal = 0;
3595 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3596 pThis->uPmTimeOld = pThis->uPmTimerVal;
3597 pThis->uBatteryIndex = 0;
3598 pThis->uSystemInfoIndex = 0;
3599 pThis->gpe0_en = 0;
3600 pThis->gpe0_sts = 0;
3601 pThis->uSleepState = 0;
3602 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
3603
3604 /* Real device behavior is resetting only the PM controller state,
3605 * but we're additionally doing the job of the BIOS. */
3606 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
3607 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3608
3609 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3610 * state. Real device behavior is only the SMBus controller state reset,
3611 * but we're additionally doing the job of the BIOS. */
3612 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3613 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3614 acpiR3SMBusResetDevice(pThis);
3615}
3616
3617/**
3618 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3619 */
3620static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3621{
3622 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3623 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3624 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3625
3626 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3627 {
3628 if (pThisCC->apu8CustBin[i])
3629 {
3630 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
3631 pThisCC->apu8CustBin[i] = NULL;
3632 }
3633 }
3634 return VINF_SUCCESS;
3635}
3636
3637/**
3638 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3639 */
3640static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3641{
3642 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3643 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3644 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3645 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3646
3647 /*
3648 * Init data and set defaults.
3649 */
3650 /** @todo move more of the code up! */
3651
3652 pThisCC->pDevIns = pDevIns;
3653 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3654 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3655 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3656 pThis->u32CpuEventType = 0;
3657 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3658
3659 /* The first CPU can't be attached/detached */
3660 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3661 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3662
3663 /* IBase */
3664 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
3665 /* IACPIPort */
3666 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3667 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3668 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3669 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3670 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3671 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3672 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3673
3674 /*
3675 * Set the default critical section to NOP (related to the PM timer).
3676 */
3677 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3678 AssertRCReturn(rc, rc);
3679
3680 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3681 AssertRCReturn(rc, rc);
3682
3683 /*
3684 * Validate and read the configuration.
3685 */
3686 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
3687 "IOAPIC"
3688 "|NumCPUs"
3689 "|HpetEnabled"
3690 "|McfgEnabled"
3691 "|McfgBase"
3692 "|McfgLength"
3693 "|PciPref64Enabled"
3694 "|PciPref64LimitGB"
3695 "|SmcEnabled"
3696 "|FdcEnabled"
3697 "|ShowRtc"
3698 "|ShowCpu"
3699 "|NicPciAddress"
3700 "|AudioPciAddress"
3701 "|NvmePciAddress"
3702 "|IocPciAddress"
3703 "|HostBusPciAddress"
3704 "|EnableSuspendToDisk"
3705 "|PowerS1Enabled"
3706 "|PowerS4Enabled"
3707 "|CpuHotPlug"
3708 "|AmlFilePath"
3709 "|Serial0IoPortBase"
3710 "|Serial1IoPortBase"
3711 "|Serial2IoPortBase"
3712 "|Serial3IoPortBase"
3713 "|Serial0Irq"
3714 "|Serial1Irq"
3715 "|Serial2Irq"
3716 "|Serial3Irq"
3717 "|AcpiOemId"
3718 "|AcpiCreatorId"
3719 "|AcpiCreatorRev"
3720 "|CustomTable"
3721 "|CustomTable0"
3722 "|CustomTable1"
3723 "|CustomTable2"
3724 "|CustomTable3"
3725 "|Parallel0IoPortBase"
3726 "|Parallel1IoPortBase"
3727 "|Parallel0Irq"
3728 "|Parallel1Irq"
3729 , "");
3730
3731 /* query whether we are supposed to present an IOAPIC */
3732 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3733 if (RT_FAILURE(rc))
3734 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
3735
3736 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3737 if (RT_FAILURE(rc))
3738 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3739
3740 /* query whether we are supposed to present an FDC controller */
3741 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3742 if (RT_FAILURE(rc))
3743 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
3744
3745 /* query whether we are supposed to present HPET */
3746 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
3747 if (RT_FAILURE(rc))
3748 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
3749 /* query MCFG configuration */
3750 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
3751 if (RT_FAILURE(rc))
3752 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
3753 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
3754 if (RT_FAILURE(rc))
3755 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
3756 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
3757
3758 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
3759 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
3760 if (RT_FAILURE(rc))
3761 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
3762
3763 /* query the limit of the the 64-bit prefetchable memory window */
3764 uint64_t u64PciPref64MaxGB;
3765 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
3766 if (RT_FAILURE(rc))
3767 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
3768 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
3769
3770 /* query whether we are supposed to present SMC */
3771 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
3772 if (RT_FAILURE(rc))
3773 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
3774
3775 /* query whether we are supposed to present RTC object */
3776 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
3777 if (RT_FAILURE(rc))
3778 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
3779
3780 /* query whether we are supposed to present CPU objects */
3781 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
3782 if (RT_FAILURE(rc))
3783 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
3784
3785 /* query primary NIC PCI address (GIGE) */
3786 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
3787 if (RT_FAILURE(rc))
3788 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
3789
3790 /* query HD Audio PCI address (HDAA) */
3791 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3792 if (RT_FAILURE(rc))
3793 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
3794
3795 /* query NVMe PCI address (NVMA) */
3796 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
3797 if (RT_FAILURE(rc))
3798 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
3799
3800 /* query IO controller (southbridge) PCI address */
3801 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3802 if (RT_FAILURE(rc))
3803 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
3804
3805 /* query host bus controller PCI address */
3806 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3807 if (RT_FAILURE(rc))
3808 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3809
3810 /* query whether S1 power state should be exposed */
3811 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3812 if (RT_FAILURE(rc))
3813 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3814
3815 /* query whether S4 power state should be exposed */
3816 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3817 if (RT_FAILURE(rc))
3818 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3819
3820 /* query whether S1 power state should save the VM state */
3821 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3822 if (RT_FAILURE(rc))
3823 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3824
3825 /* query whether we are allow CPU hot plugging */
3826 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3827 if (RT_FAILURE(rc))
3828 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
3829
3830 /* query serial info */
3831 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3832 if (RT_FAILURE(rc))
3833 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
3834
3835 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3836 if (RT_FAILURE(rc))
3837 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3838
3839 /* Serial 1 is enabled, get config data */
3840 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3841 if (RT_FAILURE(rc))
3842 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
3843
3844 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3845 if (RT_FAILURE(rc))
3846 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3847
3848 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
3849 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
3850 if (RT_FAILURE(rc))
3851 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
3852
3853 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
3854 if (RT_FAILURE(rc))
3855 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
3856
3857 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
3858 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
3859 if (RT_FAILURE(rc))
3860 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
3861
3862 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
3863 if (RT_FAILURE(rc))
3864 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
3865 /*
3866 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
3867 * the corresponding parallel port is not enabled.
3868 */
3869 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
3870 if (RT_FAILURE(rc))
3871 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
3872
3873 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
3874 if (RT_FAILURE(rc))
3875 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
3876
3877 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
3878 if (RT_FAILURE(rc))
3879 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
3880
3881 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
3882 if (RT_FAILURE(rc))
3883 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
3884
3885 /* Try to attach the other CPUs */
3886 for (unsigned i = 1; i < pThis->cCpus; i++)
3887 {
3888 if (pThis->fCpuHotPlug)
3889 {
3890 PPDMIBASE IBaseTmp;
3891 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3892
3893 if (RT_SUCCESS(rc))
3894 {
3895 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3896 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3897 Log(("acpi: Attached CPU %u\n", i));
3898 }
3899 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3900 Log(("acpi: CPU %u not attached yet\n", i));
3901 else
3902 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3903 }
3904 else
3905 {
3906 /* CPU is always attached if hot-plug is not enabled. */
3907 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3908 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3909 }
3910 }
3911
3912 char szOemId[16];
3913 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
3914 if (RT_FAILURE(rc))
3915 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3916 size_t cchOemId = strlen(szOemId);
3917 if (cchOemId > 6)
3918 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3919 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3920 memcpy(pThis->au8OemId, szOemId, cchOemId);
3921
3922 char szCreatorId[16];
3923 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
3924 if (RT_FAILURE(rc))
3925 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3926 size_t cchCreatorId = strlen(szCreatorId);
3927 if (cchCreatorId > 4)
3928 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3929 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3930 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
3931
3932 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3933 if (RT_FAILURE(rc))
3934 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3935
3936 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3937
3938 /*
3939 * Load custom ACPI tables.
3940 */
3941 /* Total space available for custom ACPI tables */
3942 /** @todo define as appropriate, remove as a magic number, and document
3943 * limitation in product manual */
3944 uint32_t cbBufAvail = 3072;
3945 pThis->cCustTbls = 0;
3946
3947 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
3948 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
3949 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
3950 {
3951 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
3952
3953 /*
3954 * Get the custom table binary file name.
3955 */
3956 char *pszCustBinFile = NULL;
3957 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
3958 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
3959 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
3960 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3961 {
3962 rc = VINF_SUCCESS;
3963 pszCustBinFile = NULL;
3964 }
3965 else if (RT_FAILURE(rc))
3966 return PDMDEV_SET_ERROR(pDevIns, rc,
3967 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
3968 else if (!*pszCustBinFile)
3969 {
3970 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
3971 pszCustBinFile = NULL;
3972 }
3973
3974 /*
3975 * Determine the custom table binary size, open specified file in the process.
3976 */
3977 if (pszCustBinFile)
3978 {
3979 uint32_t idxCust = pThis->cCustTbls;
3980 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
3981 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
3982 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
3983 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
3984 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
3985 if (RT_FAILURE(rc))
3986 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
3987 cbBufAvail -= pThisCC->acbCustBin[idxCust];
3988
3989 /* Update custom OEM attributes based on custom table */
3990 /** @todo is it intended for custom tables to overwrite user provided values above? */
3991 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
3992 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
3993 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
3994 pThis->u32OemRevision = pTblHdr->u32OemRevision;
3995 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
3996 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
3997
3998 pThis->cCustTbls++;
3999 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
4000 }
4001 }
4002
4003 /* Set default PM port base */
4004 pThis->uPmIoPortBase = PM_PORT_BASE;
4005
4006 /* Set default SMBus port base */
4007 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4008
4009 /*
4010 * FDC and SMC try to use the same non-shareable interrupt (6),
4011 * enable only one device.
4012 */
4013 if (pThis->fUseSmc)
4014 pThis->fUseFdc = false;
4015
4016 /*
4017 * Plant ACPI tables.
4018 */
4019 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4020 * au8RSDPPage here. However, there should be no harm in doing it
4021 * twice, so the lazy bird is taking the quick way out for now. */
4022 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4023 if (!GCPhysRsdp)
4024 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4025
4026 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4027 AssertRCReturn(rc, rc);
4028
4029 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4030 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4031 AssertRCReturn(rc, rc);
4032
4033 /*
4034 * Create the PM I/O ports. These can be unmapped and remapped.
4035 */
4036 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4037 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4038 AssertRCReturn(rc, rc);
4039 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4040 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4041 AssertRCReturn(rc, rc);
4042 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4043 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4044 AssertRCReturn(rc, rc);
4045 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4046 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4047 AssertRCReturn(rc, rc);
4048 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4049 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4050 AssertRCReturn(rc, rc);
4051 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4052 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4053 AssertRCReturn(rc, rc);
4054 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4055 AssertRCReturn(rc, rc);
4056
4057 /*
4058 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4059 */
4060 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4061 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4062 AssertRCReturn(rc, rc);
4063 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4064 AssertRCReturn(rc, rc);
4065
4066 /*
4067 * Create and map the fixed I/O ports.
4068 */
4069 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4070 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4071 AssertRCReturn(rc, rc);
4072#ifdef DEBUG_ACPI
4073 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4074 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4075 AssertRCReturn(rc, rc);
4076 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4077 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4078 AssertRCReturn(rc, rc);
4079#endif
4080 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4081 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4082 AssertRCReturn(rc, rc);
4083 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4084 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4085 AssertRCReturn(rc, rc);
4086 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4087 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4088 AssertRCReturn(rc, rc);
4089 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4090 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4091 AssertRCReturn(rc, rc);
4092 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4093 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4094 AssertRCReturn(rc, rc);
4095
4096 /*
4097 * Create the PM timer.
4098 */
4099 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4100 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer);
4101 AssertRCReturn(rc, rc);
4102
4103 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4104 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4105 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4106 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4107
4108 /*
4109 * Set up the PCI device.
4110 */
4111 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4112 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4113
4114 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4115 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4116
4117 /* See p. 50 of PIIX4 manual */
4118 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4119 PDMPciDevSetStatus(pPciDev, 0x0280);
4120
4121 PDMPciDevSetRevisionId(pPciDev, 0x08);
4122
4123 PDMPciDevSetClassProg(pPciDev, 0x00);
4124 PDMPciDevSetClassSub(pPciDev, 0x80);
4125 PDMPciDevSetClassBase(pPciDev, 0x06);
4126
4127 PDMPciDevSetHeaderType(pPciDev, 0x80);
4128
4129 PDMPciDevSetBIST(pPciDev, 0x00);
4130
4131 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4132 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4133
4134 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4135 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4136
4137 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4138 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4139 acpiR3SMBusResetDevice(pThis);
4140
4141 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4142 AssertRCReturn(rc, rc);
4143
4144 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4145 AssertRCReturn(rc, rc);
4146
4147 /*
4148 * Register the saved state.
4149 */
4150 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4151 AssertRCReturn(rc, rc);
4152
4153 /*
4154 * Get the corresponding connector interface
4155 */
4156 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4157 if (RT_SUCCESS(rc))
4158 {
4159 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4160 if (!pThisCC->pDrv)
4161 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4162 }
4163 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4164 {
4165 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4166 rc = VINF_SUCCESS;
4167 }
4168 else
4169 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4170
4171 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4172
4173 return rc;
4174}
4175
4176#else /* !IN_RING3 */
4177
4178/**
4179 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4180 */
4181static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4182{
4183 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4184 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4185
4186 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4187 AssertRCReturn(rc, rc);
4188
4189 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4190 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4191 AssertRCReturn(rc, rc);
4192
4193 return VINF_SUCCESS;
4194}
4195
4196#endif /* !IN_RING3 */
4197
4198/**
4199 * The device registration structure.
4200 */
4201const PDMDEVREG g_DeviceACPI =
4202{
4203 /* .u32Version = */ PDM_DEVREG_VERSION,
4204 /* .uReserved0 = */ 0,
4205 /* .szName = */ "acpi",
4206 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4207 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4208 /* .cMaxInstances = */ ~0U,
4209 /* .uSharedVersion = */ 42,
4210 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4211 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4212 /* .cbInstanceRC = */ 0,
4213 /* .cMaxPciDevices = */ 1,
4214 /* .cMaxMsixVectors = */ 0,
4215 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4216#if defined(IN_RING3)
4217 /* .pszRCMod = */ "VBoxDDRC.rc",
4218 /* .pszR0Mod = */ "VBoxDDR0.r0",
4219 /* .pfnConstruct = */ acpiR3Construct,
4220 /* .pfnDestruct = */ acpiR3Destruct,
4221 /* .pfnRelocate = */ NULL,
4222 /* .pfnMemSetup = */ acpiR3MemSetup,
4223 /* .pfnPowerOn = */ NULL,
4224 /* .pfnReset = */ acpiR3Reset,
4225 /* .pfnSuspend = */ NULL,
4226 /* .pfnResume = */ acpiR3Resume,
4227 /* .pfnAttach = */ acpiR3Attach,
4228 /* .pfnDetach = */ acpiR3Detach,
4229 /* .pfnQueryInterface = */ NULL,
4230 /* .pfnInitComplete = */ NULL,
4231 /* .pfnPowerOff = */ NULL,
4232 /* .pfnSoftReset = */ NULL,
4233 /* .pfnReserved0 = */ NULL,
4234 /* .pfnReserved1 = */ NULL,
4235 /* .pfnReserved2 = */ NULL,
4236 /* .pfnReserved3 = */ NULL,
4237 /* .pfnReserved4 = */ NULL,
4238 /* .pfnReserved5 = */ NULL,
4239 /* .pfnReserved6 = */ NULL,
4240 /* .pfnReserved7 = */ NULL,
4241#elif defined(IN_RING0)
4242 /* .pfnEarlyConstruct = */ NULL,
4243 /* .pfnConstruct = */ acpiRZConstruct,
4244 /* .pfnDestruct = */ NULL,
4245 /* .pfnFinalDestruct = */ NULL,
4246 /* .pfnRequest = */ NULL,
4247 /* .pfnReserved0 = */ NULL,
4248 /* .pfnReserved1 = */ NULL,
4249 /* .pfnReserved2 = */ NULL,
4250 /* .pfnReserved3 = */ NULL,
4251 /* .pfnReserved4 = */ NULL,
4252 /* .pfnReserved5 = */ NULL,
4253 /* .pfnReserved6 = */ NULL,
4254 /* .pfnReserved7 = */ NULL,
4255#elif defined(IN_RC)
4256 /* .pfnConstruct = */ acpiRZConstruct,
4257 /* .pfnReserved0 = */ NULL,
4258 /* .pfnReserved1 = */ NULL,
4259 /* .pfnReserved2 = */ NULL,
4260 /* .pfnReserved3 = */ NULL,
4261 /* .pfnReserved4 = */ NULL,
4262 /* .pfnReserved5 = */ NULL,
4263 /* .pfnReserved6 = */ NULL,
4264 /* .pfnReserved7 = */ NULL,
4265#else
4266# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4267#endif
4268 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4269};
4270
4271#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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