VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 85858

Last change on this file since 85858 was 85855, checked in by vboxsync, 5 years ago

AMD IOMMU: bugref:9654 ACPI fixes.
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File size: 198.4 KB
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1/* $Id: DevACPI.cpp 85855 2020-08-21 07:36:02Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <VBox/pci.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#include <iprt/asm-math.h>
33#include <iprt/file.h>
34#ifdef IN_RING3
35# include <iprt/alloc.h>
36# include <iprt/string.h>
37# include <iprt/uuid.h>
38#endif /* IN_RING3 */
39
40#include "VBoxDD.h"
41
42#ifdef LOG_ENABLED
43# define DEBUG_ACPI
44#endif
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50#ifdef IN_RING3
51/** Locks the device state, ring-3 only. */
52# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
53 do { \
54 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
55 AssertRC(rcLock); \
56 } while (0)
57#endif
58/** Unlocks the device state (all contexts). */
59#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
60 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
61
62
63#define DEBUG_HEX 0x3000
64#define DEBUG_CHR 0x3001
65
66/** PM Base Address PCI config space offset */
67#define PMBA 0x40
68/** PM Miscellaneous Power Management PCI config space offset */
69#define PMREGMISC 0x80
70
71#define PM_TMR_FREQ 3579545
72/** Default base for PM PIIX4 device */
73#define PM_PORT_BASE 0x4000
74/* Port offsets in PM device */
75enum
76{
77 PM1a_EVT_OFFSET = 0x00,
78 PM1b_EVT_OFFSET = -1, /**< not supported */
79 PM1a_CTL_OFFSET = 0x04,
80 PM1b_CTL_OFFSET = -1, /**< not supported */
81 PM2_CTL_OFFSET = -1, /**< not supported */
82 PM_TMR_OFFSET = 0x08,
83 GPE0_OFFSET = 0x20,
84 GPE1_OFFSET = -1 /**< not supported */
85};
86
87/* Maximum supported number of custom ACPI tables */
88#define MAX_CUST_TABLES 4
89
90/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
91#define PM_TMR_32BIT
92
93#define BAT_INDEX 0x00004040
94#define BAT_DATA 0x00004044
95#define SYSI_INDEX 0x00004048
96#define SYSI_DATA 0x0000404c
97#define ACPI_RESET_BLK 0x00004050
98
99/* PM1x status register bits */
100#define TMR_STS RT_BIT(0)
101#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
102#define BM_STS RT_BIT(4)
103#define GBL_STS RT_BIT(5)
104#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
105#define PWRBTN_STS RT_BIT(8)
106#define SLPBTN_STS RT_BIT(9)
107#define RTC_STS RT_BIT(10)
108#define IGN_STS RT_BIT(11)
109#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
110#define WAK_STS RT_BIT(15)
111#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
112
113/* PM1x enable register bits */
114#define TMR_EN RT_BIT(0)
115#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
116#define GBL_EN RT_BIT(5)
117#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
118#define PWRBTN_EN RT_BIT(8)
119#define SLPBTN_EN RT_BIT(9)
120#define RTC_EN RT_BIT(10)
121#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
122#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
123#define IGN_EN 0
124
125/* PM1x control register bits */
126#define SCI_EN RT_BIT(0)
127#define BM_RLD RT_BIT(1)
128#define GBL_RLS RT_BIT(2)
129#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
130#define IGN_CNT RT_BIT(9)
131#define SLP_TYPx_SHIFT 10
132#define SLP_TYPx_MASK 7
133#define SLP_EN RT_BIT(13)
134#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
135#define RSR_CNT (RSR1_CNT | RSR2_CNT)
136
137#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
138
139enum
140{
141 BAT_STATUS_STATE = 0x00, /**< BST battery state */
142 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
143 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
144 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
145 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
146 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
147 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
148 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
149 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
150 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
151 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
152 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
153 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
154 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
155 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
156 BAT_INDEX_LAST
157};
158
159enum
160{
161 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
162 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
163};
164
165enum
166{
167 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
168 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
169 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
170 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
171 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
172 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
173 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
174 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
175 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
176 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
177 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
178 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
179 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
180 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
181 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
182 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
183 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
184 SYSTEM_INFO_INDEX_POWER_STATES = 17,
185 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
186 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
187 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
188 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
189 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
190 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
191 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
192 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
193 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
194 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
195 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
196 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
197 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
198 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
199 SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS = 32, /**< AMD IOMMU PCI address, or 0 */
200 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
201 SYSTEM_INFO_INDEX_END = 34,
202 SYSTEM_INFO_INDEX_INVALID = 0x80,
203 SYSTEM_INFO_INDEX_VALID = 0x200
204};
205
206#define AC_OFFLINE 0
207#define AC_ONLINE 1
208
209#define BAT_TECH_PRIMARY 1
210#define BAT_TECH_SECONDARY 2
211
212#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
213#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
214#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
215#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
216#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
217
218/** SMBus Base Address PCI config space offset */
219#define SMBBA 0x90
220/** SMBus Host Configuration PCI config space offset */
221#define SMBHSTCFG 0xd2
222/** SMBus Slave Command PCI config space offset */
223#define SMBSLVC 0xd3
224/** SMBus Slave Shadow Port 1 PCI config space offset */
225#define SMBSHDW1 0xd4
226/** SMBus Slave Shadow Port 2 PCI config space offset */
227#define SMBSHDW2 0xd5
228/** SMBus Revision Identification PCI config space offset */
229#define SMBREV 0xd6
230
231#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
232#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
233#define SMBHSTCFG_INTRSEL_SMI 0
234#define SMBHSTCFG_INTRSEL_IRQ9 4
235#define SMBHSTCFG_INTRSEL_SHIFT 1
236
237/** Default base for SMBus PIIX4 device */
238#define SMB_PORT_BASE 0x4100
239
240/** SMBus Host Status Register I/O offset */
241#define SMBHSTSTS_OFF 0x0000
242/** SMBus Slave Status Register I/O offset */
243#define SMBSLVSTS_OFF 0x0001
244/** SMBus Host Count Register I/O offset */
245#define SMBHSTCNT_OFF 0x0002
246/** SMBus Host Command Register I/O offset */
247#define SMBHSTCMD_OFF 0x0003
248/** SMBus Host Address Register I/O offset */
249#define SMBHSTADD_OFF 0x0004
250/** SMBus Host Data 0 Register I/O offset */
251#define SMBHSTDAT0_OFF 0x0005
252/** SMBus Host Data 1 Register I/O offset */
253#define SMBHSTDAT1_OFF 0x0006
254/** SMBus Block Data Register I/O offset */
255#define SMBBLKDAT_OFF 0x0007
256/** SMBus Slave Control Register I/O offset */
257#define SMBSLVCNT_OFF 0x0008
258/** SMBus Shadow Command Register I/O offset */
259#define SMBSHDWCMD_OFF 0x0009
260/** SMBus Slave Event Register I/O offset */
261#define SMBSLVEVT_OFF 0x000a
262/** SMBus Slave Data Register I/O offset */
263#define SMBSLVDAT_OFF 0x000c
264
265#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
266#define SMBHSTSTS_INTER RT_BIT(1)
267#define SMBHSTSTS_DEV_ERR RT_BIT(2)
268#define SMBHSTSTS_BUS_ERR RT_BIT(3)
269#define SMBHSTSTS_FAILED RT_BIT(4)
270#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
271
272#define SMBSLVSTS_WRITE_MASK 0x3c
273
274#define SMBHSTCNT_INTEREN RT_BIT(0)
275#define SMBHSTCNT_KILL RT_BIT(1)
276#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
277#define SMBHSTCNT_START RT_BIT(6)
278#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
279
280#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
281
282
283/*********************************************************************************************************************************
284* Structures and Typedefs *
285*********************************************************************************************************************************/
286/**
287 * The shared ACPI device state.
288 */
289typedef struct ACPISTATE
290{
291 /** Critical section protecting the ACPI state. */
292 PDMCRITSECT CritSect;
293
294 uint16_t pm1a_en;
295 uint16_t pm1a_sts;
296 uint16_t pm1a_ctl;
297 /** Number of logical CPUs in guest */
298 uint16_t cCpus;
299
300 uint64_t u64PmTimerInitial;
301 /** The PM timer. */
302 TMTIMERHANDLE hPmTimer;
303 /* PM Timer last calculated value */
304 uint32_t uPmTimerVal;
305 uint32_t Alignment0;
306
307 uint32_t gpe0_en;
308 uint32_t gpe0_sts;
309
310 uint32_t uBatteryIndex;
311 uint32_t au8BatteryInfo[13];
312
313 uint32_t uSystemInfoIndex;
314 uint32_t u32Alignment0;
315 uint64_t u64RamSize;
316 /** Offset of the 64-bit prefetchable memory window. */
317 uint64_t u64PciPref64Min;
318 /** Limit of the 64-bit prefetchable memory window. */
319 uint64_t u64PciPref64Max;
320 /** The number of bytes below 4GB. */
321 uint32_t cbRamLow;
322
323 /** Current ACPI S* state. We support S0 and S5. */
324 uint32_t uSleepState;
325 uint8_t au8RSDPPage[0x1000];
326 /** This is a workaround for incorrect index field handling by Intels ACPICA.
327 * The system info _INI method writes to offset 0x200. We either observe a
328 * write request to index 0x80 (in that case we don't change the index) or a
329 * write request to offset 0x200 (in that case we divide the index value by
330 * 4. Note that the _STA method is sometimes called prior to the _INI method
331 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
332 * acpiR3BatIndexWrite() for handling this. */
333 uint8_t u8IndexShift;
334 /** provide an I/O-APIC */
335 uint8_t u8UseIOApic;
336 /** provide a floppy controller */
337 bool fUseFdc;
338 /** If High Precision Event Timer device should be supported */
339 bool fUseHpet;
340 /** If System Management Controller device should be supported */
341 bool fUseSmc;
342 /** the guest handled the last power button event */
343 bool fPowerButtonHandled;
344 /** If ACPI CPU device should be shown */
345 bool fShowCpu;
346 /** If Real Time Clock ACPI object to be shown */
347 bool fShowRtc;
348 /** I/O port address of PM device. */
349 RTIOPORT uPmIoPortBase;
350 /** I/O port address of SMBus device. */
351 RTIOPORT uSMBusIoPortBase;
352 /** Which CPU to check for the locked status. */
353 uint32_t idCpuLockCheck;
354 /** Array of flags of attached CPUs */
355 VMCPUSET CpuSetAttached;
356 /** Mask of locked CPUs (used by the guest). */
357 VMCPUSET CpuSetLocked;
358 /** The CPU event type. */
359 uint32_t u32CpuEventType;
360 /** The CPU id affected. */
361 uint32_t u32CpuEvent;
362 /** Flag whether CPU hot plugging is enabled. */
363 bool fCpuHotPlug;
364 /** If MCFG ACPI table shown to the guest */
365 bool fUseMcfg;
366 /** if the 64-bit prefetchable memory window is shown to the guest */
367 bool fPciPref64Enabled;
368 bool afAlignment1;
369 /** Primary NIC PCI address. */
370 uint32_t u32NicPciAddress;
371 /** HD Audio PCI address. */
372 uint32_t u32AudioPciAddress;
373 /** Primary NVMe controller PCI address. */
374 uint32_t u32NvmePciAddress;
375 /** Flag whether S1 power state is enabled. */
376 bool fS1Enabled;
377 /** Flag whether S4 power state is enabled. */
378 bool fS4Enabled;
379 /** Flag whether S1 triggers a state save. */
380 bool fSuspendToSavedState;
381 /** Flag whether to set WAK_STS on resume (restore included). */
382 bool fSetWakeupOnResume;
383 /** PCI address of the IO controller device. */
384 uint32_t u32IocPciAddress;
385 /** PCI address of the host bus controller device. */
386 uint32_t u32HbcPciAddress;
387 /** PCI address of the AMD IOMMU device. */
388 uint32_t u32IommuAmdPciAddress;
389 /** PCI address of the southbridge I/O APIC device. */
390 uint32_t u32SbIoApicPciAddress;
391
392 /** Physical address of PCI config space MMIO region */
393 uint64_t u64PciConfigMMioAddress;
394 /** Length of PCI config space MMIO region */
395 uint64_t u64PciConfigMMioLength;
396 /** Serial 0 IRQ number */
397 uint8_t uSerial0Irq;
398 /** Serial 1 IRQ number */
399 uint8_t uSerial1Irq;
400 /** Serial 2 IRQ number */
401 uint8_t uSerial2Irq;
402 /** Serial 3 IRQ number */
403 uint8_t uSerial3Irq;
404 /** Serial 0 IO port base */
405 RTIOPORT uSerial0IoPortBase;
406 /** Serial 1 IO port base */
407 RTIOPORT uSerial1IoPortBase;
408 /** Serial 2 IO port base */
409 RTIOPORT uSerial2IoPortBase;
410 /** Serial 3 IO port base */
411 RTIOPORT uSerial3IoPortBase;
412
413 /** @name Parallel port config bits
414 * @{ */
415 /** Parallel 0 IO port base */
416 RTIOPORT uParallel0IoPortBase;
417 /** Parallel 1 IO port base */
418 RTIOPORT uParallel1IoPortBase;
419 /** Parallel 0 IRQ number */
420 uint8_t uParallel0Irq;
421 /** Parallel 1 IRQ number */
422 uint8_t uParallel1Irq;
423 /** @} */
424
425 /** Number of custom ACPI tables */
426 uint8_t cCustTbls;
427 /** ACPI OEM ID */
428 uint8_t au8OemId[6];
429 /** ACPI Crator ID */
430 uint8_t au8CreatorId[4];
431 uint8_t abAlignment2[3];
432 /** ACPI Crator Rev */
433 uint32_t u32CreatorRev;
434 /** ACPI custom OEM Tab ID */
435 uint8_t au8OemTabId[8];
436 /** ACPI custom OEM Rev */
437 uint32_t u32OemRevision;
438
439 /** SMBus Host Status Register */
440 uint8_t u8SMBusHstSts;
441 /** SMBus Slave Status Register */
442 uint8_t u8SMBusSlvSts;
443 /** SMBus Host Control Register */
444 uint8_t u8SMBusHstCnt;
445 /** SMBus Host Command Register */
446 uint8_t u8SMBusHstCmd;
447 /** SMBus Host Address Register */
448 uint8_t u8SMBusHstAdd;
449 /** SMBus Host Data 0 Register */
450 uint8_t u8SMBusHstDat0;
451 /** SMBus Host Data 1 Register */
452 uint8_t u8SMBusHstDat1;
453 /** SMBus Slave Control Register */
454 uint8_t u8SMBusSlvCnt;
455 /** SMBus Slave Event Register */
456 uint16_t u16SMBusSlvEvt;
457 /** SMBus Slave Data Register */
458 uint16_t u16SMBusSlvDat;
459 /** SMBus Shadow Command Register */
460 uint8_t u8SMBusShdwCmd;
461 /** SMBus Host Block Index */
462 uint8_t u8SMBusBlkIdx;
463 uint8_t abAlignment3[2];
464 /** SMBus Host Block Data Buffer */
465 uint8_t au8SMBusBlkDat[32];
466
467 /** @todo DEBUGGING */
468 uint32_t uPmTimeOld;
469 uint32_t uPmTimeA;
470 uint32_t uPmTimeB;
471 uint32_t Alignment5;
472
473 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
474 * @{ */
475 IOMIOPORTHANDLE hIoPortPm1aEn;
476 IOMIOPORTHANDLE hIoPortPm1aSts;
477 IOMIOPORTHANDLE hIoPortPm1aCtl;
478 IOMIOPORTHANDLE hIoPortPmTimer;
479 IOMIOPORTHANDLE hIoPortGpe0En;
480 IOMIOPORTHANDLE hIoPortGpe0Sts;
481 /** @} */
482
483 /** SMBus I/O ports (mapped/unmapped). */
484 IOMIOPORTHANDLE hIoPortSMBus;
485
486 /** @name Fixed I/O ports
487 * @{ */
488 /** ACPI SMI I/O port. */
489 IOMIOPORTHANDLE hIoPortSmi;
490 /** ACPI Debug hex I/O port. */
491 IOMIOPORTHANDLE hIoPortDebugHex;
492 /** ACPI Debug char I/O port. */
493 IOMIOPORTHANDLE hIoPortDebugChar;
494 /** ACPI Battery status index I/O port. */
495 IOMIOPORTHANDLE hIoPortBatteryIndex;
496 /** ACPI Battery status data I/O port. */
497 IOMIOPORTHANDLE hIoPortBatteryData;
498 /** ACPI system info index I/O port. */
499 IOMIOPORTHANDLE hIoPortSysInfoIndex;
500 /** ACPI system info data I/O port. */
501 IOMIOPORTHANDLE hIoPortSysInfoData;
502 /** ACPI Reset I/O port. */
503 IOMIOPORTHANDLE hIoPortReset;
504 /** @} */
505
506} ACPISTATE;
507/** Pointer to the shared ACPI device state. */
508typedef ACPISTATE *PACPISTATE;
509
510
511
512/**
513 * The ring-3 ACPI device state.
514 */
515typedef struct ACPISTATER3
516{
517 /** ACPI port base interface. */
518 PDMIBASE IBase;
519 /** ACPI port interface. */
520 PDMIACPIPORT IACPIPort;
521 /** Pointer to the device instance so we can get our bearings from
522 * interface functions. */
523 PPDMDEVINSR3 pDevIns;
524
525 /** Pointer to the driver base interface. */
526 R3PTRTYPE(PPDMIBASE) pDrvBase;
527 /** Pointer to the driver connector interface. */
528 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
529
530 /** Custom ACPI tables binary data. */
531 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
532 /** The size of the custom table binary. */
533 uint64_t acbCustBin[MAX_CUST_TABLES];
534} ACPISTATER3;
535/** Pointer to the ring-3 ACPI device state. */
536typedef ACPISTATER3 *PACPISTATER3;
537
538
539#pragma pack(1)
540
541/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
542struct ACPIGENADDR
543{
544 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
545 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
546 uint8_t u8RegisterBitOffset; /**< bit offset of register */
547 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
548 uint64_t u64Address; /**< 64-bit address of register */
549};
550AssertCompileSize(ACPIGENADDR, 12);
551
552/** Root System Description Pointer */
553struct ACPITBLRSDP
554{
555 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
556 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
557 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
558 uint8_t u8Revision; /**< revision number, currently 2 */
559#define ACPI_REVISION 2 /**< ACPI 3.0 */
560 uint32_t u32RSDT; /**< phys addr of RSDT */
561 uint32_t u32Length; /**< bytes of this table */
562 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
563 uint8_t u8ExtChecksum; /**< checksum of entire table */
564 uint8_t u8Reserved[3]; /**< reserved */
565};
566AssertCompileSize(ACPITBLRSDP, 36);
567
568/** System Description Table Header */
569struct ACPITBLHEADER
570{
571 uint8_t au8Signature[4]; /**< table identifier */
572 uint32_t u32Length; /**< length of the table including header */
573 uint8_t u8Revision; /**< revision number */
574 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
575 uint8_t au8OemId[6]; /**< OEM-supplied string */
576 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
577 uint32_t u32OemRevision; /**< OEM-supplied revision number */
578 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
579 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
580};
581AssertCompileSize(ACPITBLHEADER, 36);
582
583/** Root System Description Table */
584struct ACPITBLRSDT
585{
586 ACPITBLHEADER header;
587 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
588};
589AssertCompileSize(ACPITBLRSDT, 40);
590
591/** Extended System Description Table */
592struct ACPITBLXSDT
593{
594 ACPITBLHEADER header;
595 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
596};
597AssertCompileSize(ACPITBLXSDT, 44);
598
599/** Fixed ACPI Description Table */
600struct ACPITBLFADT
601{
602 ACPITBLHEADER header;
603 uint32_t u32FACS; /**< phys. address of FACS */
604 uint32_t u32DSDT; /**< phys. address of DSDT */
605 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
606#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
607#define INT_MODEL_MULTIPLE_APIC 2
608 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
609 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
610#define SCI_INT 9
611 uint32_t u32SMICmd; /**< system port address of SMI command port */
612#define SMI_CMD 0x0000442e
613 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
614#define ACPI_ENABLE 0xa1
615 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
616#define ACPI_DISABLE 0xa0
617 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
618 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
619 state control responsibility */
620 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
621 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
622 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
623 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
624 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
625 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
626 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
627 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
628 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
629 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
630 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
631 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
632 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
633#define GPE0_BLK_LEN 2
634 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
635#define GPE1_BLK_LEN 0
636 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
637#define GPE1_BASE 0
638 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
639 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
640#define P_LVL2_LAT 101 /**< C2 state not supported */
641 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
642#define P_LVL3_LAT 1001 /**< C3 state not supported */
643 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
644 lines from any processors memory caches */
645#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
646 uint16_t u16FlushStride; /**< cache line width */
647#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
648 uint8_t u8DutyOffset;
649 uint8_t u8DutyWidth;
650 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
651 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
652 uint8_t u8Century; /**< RTC CMOS RAM index of century */
653 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
654#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
655 (COM too?) */
656#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
657#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
658#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
659#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
660 uint8_t u8Must0_0; /**< must be 0 */
661 uint32_t u32Flags; /**< fixed feature flags */
662#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
663#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
664#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
665#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
666#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
667#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
668#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
669#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
670#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
671#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
672#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
673#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
674#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
675#define FADT_FL_CPU_SW_SLP RT_BIT(13)
676#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
677#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
678#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
679#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
680#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
681#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
682
683/* PM Timer mask and msb */
684#ifndef PM_TMR_32BIT
685#define TMR_VAL_MSB 0x800000
686#define TMR_VAL_MASK 0xffffff
687#undef FADT_FL_TMR_VAL_EXT
688#define FADT_FL_TMR_VAL_EXT 0
689#else
690#define TMR_VAL_MSB 0x80000000
691#define TMR_VAL_MASK 0xffffffff
692#endif
693
694 /** Start of the ACPI 2.0 extension. */
695 ACPIGENADDR ResetReg; /**< ext addr of reset register */
696 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
697#define ACPI_RESET_REG_VAL 0x10
698 uint8_t au8Must0_1[3]; /**< must be 0 */
699 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
700 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
701 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
702 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
703 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
704 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
705 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
706 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
707 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
708 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
709};
710AssertCompileSize(ACPITBLFADT, 244);
711#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
712
713/** Firmware ACPI Control Structure */
714struct ACPITBLFACS
715{
716 uint8_t au8Signature[4]; /**< 'FACS' */
717 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
718 uint32_t u32HWSignature; /**< systems HW signature at last boot */
719 uint32_t u32FWVector; /**< address of waking vector */
720 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
721 uint32_t u32Flags; /**< FACS flags */
722 uint64_t u64X_FWVector; /**< 64-bit waking vector */
723 uint8_t u8Version; /**< version of this table */
724 uint8_t au8Reserved[31]; /**< zero */
725};
726AssertCompileSize(ACPITBLFACS, 64);
727
728/** Processor Local APIC Structure */
729struct ACPITBLLAPIC
730{
731 uint8_t u8Type; /**< 0 = LAPIC */
732 uint8_t u8Length; /**< 8 */
733 uint8_t u8ProcId; /**< processor ID */
734 uint8_t u8ApicId; /**< local APIC ID */
735 uint32_t u32Flags; /**< Flags */
736#define LAPIC_ENABLED 0x1
737};
738AssertCompileSize(ACPITBLLAPIC, 8);
739
740/** I/O APIC Structure */
741struct ACPITBLIOAPIC
742{
743 uint8_t u8Type; /**< 1 == I/O APIC */
744 uint8_t u8Length; /**< 12 */
745 uint8_t u8IOApicId; /**< I/O APIC ID */
746 uint8_t u8Reserved; /**< 0 */
747 uint32_t u32Address; /**< phys address to access I/O APIC */
748 uint32_t u32GSIB; /**< global system interrupt number to start */
749};
750AssertCompileSize(ACPITBLIOAPIC, 12);
751
752/** Interrupt Source Override Structure */
753struct ACPITBLISO
754{
755 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
756 uint8_t u8Length; /**< 10 */
757 uint8_t u8Bus; /**< Bus */
758 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
759 uint32_t u32GSI; /**< Global System Interrupt */
760 uint16_t u16Flags; /**< MPS INTI flags Global */
761};
762AssertCompileSize(ACPITBLISO, 10);
763#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
764
765/** HPET Descriptor Structure */
766struct ACPITBLHPET
767{
768 ACPITBLHEADER aHeader;
769 uint32_t u32Id; /**< hardware ID of event timer block
770 [31:16] PCI vendor ID of first timer block
771 [15] legacy replacement IRQ routing capable
772 [14] reserved
773 [13] COUNT_SIZE_CAP counter size
774 [12:8] number of comparators in first timer block
775 [7:0] hardware rev ID */
776 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
777 uint8_t u32Number; /**< sequence number starting at 0 */
778 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
779 lost interrupts while the counter is programmed
780 to operate in periodic mode. Unit: clock tick. */
781 uint8_t u8Attributes; /**< page protection and OEM attribute. */
782};
783AssertCompileSize(ACPITBLHPET, 56);
784
785#ifdef VBOX_WITH_IOMMU_AMD
786/** @name IVRS format revision field.
787 * In accordance with the AMD spec.
788 * @{ */
789/** Fixed: Supports only pre-assigned device IDs and type 10h and 11h IVHD
790 * blocks. */
791#define ACPI_IVRS_FMT_REV_FIXED 0x1
792/** Mixed: Supports pre-assigned and ACPI HID device naming and all IVHD blocks. */
793#define ACPI_IVRS_FMT_REV_MIXED 0x2
794/** @} */
795
796/** @name IVHD special device entry variety field.
797 * In accordance with the AMD spec.
798 * @{ */
799/** I/O APIC. */
800#define ACPI_IVHD_VARIETY_IOAPIC 0x1
801/** HPET. */
802#define ACPI_IVHD_VARIETY_HPET 0x2
803/** @} */
804
805/** @name IVHD device entry type codes.
806 * In accordance with the AMD spec.
807 * @{ */
808/** Reserved. */
809#define ACPI_IVHD_DEVENTRY_TYPE_RSVD 0x0
810/** All: DTE setting applies to all Device IDs. */
811#define ACPI_IVHD_DEVENTRY_TYPE_ALL 0x1
812/** Select: DTE setting applies to the device specified in DevId field. */
813#define ACPI_IVHD_DEVENTRY_TYPE_SELECT 0x2
814/** Start of range: DTE setting applies to all devices from start of range specified
815 * by the DevId field. */
816#define ACPI_IVHD_DEVENTRY_TYPE_START_RANGE 0x3
817/** End of range: DTE setting from previous type 3 entry applies to all devices
818 * incl. DevId specified by this entry. */
819#define ACPI_IVHD_DEVENTRY_TYPE_END_RANGE 0x4
820/** @} */
821
822/** @name IVHD DTE (Device Table Entry) Settings.
823 * In accordance with the AMD spec.
824 * @{ */
825/** INITPass: Identifies a device able to assert INIT interrupts. */
826#define ACPI_IVHD_DTE_INIT_PASS_SHIFT 0
827#define ACPI_IVHD_DTE_INIT_PASS_MASK UINT8_C(0x01)
828/** EIntPass: Identifies a device able to assert ExtInt interrupts. */
829#define ACPI_IVHD_DTE_EXTINT_PASS_SHIFT 1
830#define ACPI_IVHD_DTE_EXTINT_PASS_MASK UINT8_C(0x02)
831/** NMIPass: Identifies a device able to assert NMI interrupts. */
832#define ACPI_IVHD_DTE_NMI_PASS_SHIFT 2
833#define ACPI_IVHD_DTE_NMI_PASS_MASK UINT8_C(0x04)
834/** Bit 3 reserved. */
835#define ACPI_IVHD_DTE_RSVD_3_SHIFT 3
836#define ACPI_IVHD_DTE_RSVD_3_MASK UINT8_C(0x08)
837/** SysMgt: Identifies a device able to assert system management messages. */
838#define ACPI_IVHD_DTE_SYS_MGT_SHIFT 4
839#define ACPI_IVHD_DTE_SYS_MGT_MASK UINT8_C(0x30)
840/** Lint0Pass: Identifies a device able to assert LINT0 interrupts. */
841#define ACPI_IVHD_DTE_LINT0_PASS_SHIFT 6
842#define ACPI_IVHD_DTE_LINT0_PASS_MASK UINT8_C(0x40)
843/** Lint0Pass: Identifies a device able to assert LINT1 interrupts. */
844#define ACPI_IVHD_DTE_LINT1_PASS_SHIFT 7
845#define ACPI_IVHD_DTE_LINT1_PASS_MASK UINT8_C(0x80)
846RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVHD_DTE_, UINT8_C(0), UINT8_MAX,
847 (INIT_PASS, EXTINT_PASS, NMI_PASS, RSVD_3, SYS_MGT, LINT0_PASS, LINT1_PASS));
848/** @} */
849
850/** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry
851 * (4-byte). In accordance with the AMD spec. */
852typedef struct ACPIIVHDDEVENTRY4
853{
854 uint8_t u8DevEntryType; /**< Device entry type. */
855 uint16_t u16DevId; /**< Device ID. */
856 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
857} ACPIIVHDDEVENTRY4;
858AssertCompileSize(ACPIIVHDDEVENTRY4, 4);
859
860/** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Device Entry
861 * (8-byte). In accordance with the AMD spec. */
862typedef struct ACPIIVHDDEVENTRY8
863{
864 uint8_t u8DevEntryType; /**< Device entry type. */
865 union
866 {
867 /** Reserved: When u8DevEntryType is 0x40, 0x41, 0x44 or 0x45 (or 0x49-0x7F). */
868 struct
869 {
870 uint8_t au8Rsvd0[7]; /**< Reserved (MBZ). */
871 } rsvd;
872 /** Alias Select: When u8DevEntryType is 0x42 or 0x43. */
873 struct
874 {
875 uint16_t u16DevIdA; /**< Device ID A. */
876 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
877 uint8_t u8Rsvd0; /**< Reserved (MBZ). */
878 uint16_t u16DevIdB; /**< Device ID B. */
879 uint8_t u8Rsvd1; /**< Reserved (MBZ). */
880 } alias;
881 /** Extended Select: When u8DevEntryType is 0x46 or 0x47. */
882 struct
883 {
884 uint16_t u16DevId; /**< Device ID. */
885 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
886 uint32_t u32ExtDteSetting; /**< Extended DTE setting. */
887 } ext;
888 /** Special Device: When u8DevEntryType is 0x48. */
889 struct
890 {
891 uint16_t u16Rsvd0; /**< Reserved (MBZ). */
892 uint8_t u8DteSetting; /**< DTE (Device Table Entry) setting. */
893 uint8_t u8Handle; /**< Handle contains I/O APIC ID or HPET number. */
894 uint16_t u16DevIdB; /**< Device ID B (I/O APIC or HPET). */
895 uint8_t u8Variety; /**< Whether this is the HPET or I/O APIC. */
896 } special;
897 } u;
898} ACPIIVHDDEVENTRY8;
899AssertCompileSize(ACPIIVHDDEVENTRY8, 8);
900
901/** @name IVHD Type 10h Flags.
902 * In accordance with the AMD spec.
903 * @{ */
904/** Peripheral page request support. */
905#define ACPI_IVHD_10H_F_PPR_SUP RT_BIT(7)
906/** Prefetch IOMMU pages command support. */
907#define ACPI_IVHD_10H_F_PREF_SUP RT_BIT(6)
908/** Coherent control. */
909#define ACPI_IVHD_10H_F_COHERENT RT_BIT(5)
910/** Remote IOTLB support. */
911#define ACPI_IVHD_10H_F_IOTLB_SUP RT_BIT(4)
912/** Isochronous control. */
913#define ACPI_IVHD_10H_F_ISOC RT_BIT(3)
914/** Response Pass Posted Write. */
915#define ACPI_IVHD_10H_F_RES_PASS_PW RT_BIT(2)
916/** Pass Posted Write. */
917#define ACPI_IVHD_10H_F_PASS_PW RT_BIT(1)
918/** HyperTransport Tunnel. */
919#define ACPI_IVHD_10H_F_HT_TUNNEL RT_BIT(0)
920/** @} */
921
922/** @name IVRS IVinfo field.
923 * In accordance with the AMD spec.
924 * @{ */
925/** EFRSup: Extended Feature Support. */
926#define ACPI_IVINFO_BF_EFR_SUP_SHIFT 0
927#define ACPI_IVINFO_BF_EFR_SUP_MASK UINT32_C(0x00000001)
928/** DMA Remap Sup: DMA remapping support (pre-boot DMA protection with
929 * mandatory remapping of device accessed memory). */
930#define ACPI_IVINFO_BF_DMA_REMAP_SUP_SHIFT 1
931#define ACPI_IVINFO_BF_DMA_REMAP_SUP_MASK UINT32_C(0x00000002)
932/** Bits 4:2 reserved. */
933#define ACPI_IVINFO_BF_RSVD_2_4_SHIFT 2
934#define ACPI_IVINFO_BF_RSVD_2_4_MASK UINT32_C(0x0000001c)
935/** GVASize: Guest virtual-address size. */
936#define ACPI_IVINFO_BF_GVA_SIZE_SHIFT 5
937#define ACPI_IVINFO_BF_GVA_SIZE_MASK UINT32_C(0x000000e0)
938/** PASize: System physical address size. */
939#define ACPI_IVINFO_BF_PA_SIZE_SHIFT 8
940#define ACPI_IVINFO_BF_PA_SIZE_MASK UINT32_C(0x00007f00)
941/** VASize: Virtual address size. */
942#define ACPI_IVINFO_BF_VA_SIZE_SHIFT 15
943#define ACPI_IVINFO_BF_VA_SIZE_MASK UINT32_C(0x003f8000)
944/** HTAtsResv: HyperTransport ATS-response address translation range reserved. */
945#define ACPI_IVINFO_BF_HT_ATS_RESV_SHIFT 22
946#define ACPI_IVINFO_BF_HT_ATS_RESV_MASK UINT32_C(0x00400000)
947/** Bits 31:23 reserved. */
948#define ACPI_IVINFO_BF_RSVD_23_31_SHIFT 23
949#define ACPI_IVINFO_BF_RSVD_23_31_MASK UINT32_C(0xff800000)
950RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IVINFO_BF_, UINT32_C(0), UINT32_MAX,
951 (EFR_SUP, DMA_REMAP_SUP, RSVD_2_4, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_31));
952/** @} */
953
954/** @name IVHD IOMMU info flags.
955 * In accordance with the AMD spec.
956 * @{ */
957/** MSI message number for the event log. */
958#define ACPI_IOMMU_INFO_BF_MSI_NUM_SHIFT 0
959#define ACPI_IOMMU_INFO_BF_MSI_NUM_MASK UINT16_C(0x001f)
960/** Bits 7:5 reserved. */
961#define ACPI_IOMMU_INFO_BF_RSVD_5_7_SHIFT 5
962#define ACPI_IOMMU_INFO_BF_RSVD_5_7_MASK UINT16_C(0x00e0)
963/** IOMMU HyperTransport Unit ID number. */
964#define ACPI_IOMMU_INFO_BF_UNIT_ID_SHIFT 8
965#define ACPI_IOMMU_INFO_BF_UNIT_ID_MASK UINT16_C(0x1f00)
966/** Bits 15:13 reserved. */
967#define ACPI_IOMMU_INFO_BF_RSVD_13_15_SHIFT 13
968#define ACPI_IOMMU_INFO_BF_RSVD_13_15_MASK UINT16_C(0xe000)
969RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_INFO_BF_, UINT16_C(0), UINT16_MAX,
970 (MSI_NUM, RSVD_5_7, UNIT_ID, RSVD_13_15));
971/** @} */
972
973/** @name IVHD IOMMU feature reporting field.
974 * In accordance with the AMD spec.
975 * @{ */
976/** x2APIC supported for peripherals. */
977#define ACPI_IOMMU_FEAT_BF_XT_SUP_SHIFT 0
978#define ACPI_IOMMU_FEAT_BF_XT_SUP_MASK UINT32_C(0x00000001)
979/** NX supported for I/O. */
980#define ACPI_IOMMU_FEAT_BF_NX_SUP_SHIFT 1
981#define ACPI_IOMMU_FEAT_BF_NX_SUP_MASK UINT32_C(0x00000002)
982/** GT (Guest Translation) supported. */
983#define ACPI_IOMMU_FEAT_BF_GT_SUP_SHIFT 2
984#define ACPI_IOMMU_FEAT_BF_GT_SUP_MASK UINT32_C(0x00000004)
985/** GLX (Number of guest CR3 tables) supported. */
986#define ACPI_IOMMU_FEAT_BF_GLX_SUP_SHIFT 3
987#define ACPI_IOMMU_FEAT_BF_GLX_SUP_MASK UINT32_C(0x00000018)
988/** IA (INVALIDATE_IOMMU_ALL) command supported. */
989#define ACPI_IOMMU_FEAT_BF_IA_SUP_SHIFT 5
990#define ACPI_IOMMU_FEAT_BF_IA_SUP_MASK UINT32_C(0x00000020)
991/** GA (Guest virtual APIC) supported. */
992#define ACPI_IOMMU_FEAT_BF_GA_SUP_SHIFT 6
993#define ACPI_IOMMU_FEAT_BF_GA_SUP_MASK UINT32_C(0x00000040)
994/** HE (Hardware error) registers supported. */
995#define ACPI_IOMMU_FEAT_BF_HE_SUP_SHIFT 7
996#define ACPI_IOMMU_FEAT_BF_HE_SUP_MASK UINT32_C(0x00000080)
997/** PASMax (maximum PASID) supported. Ignored if PPRSup=0. */
998#define ACPI_IOMMU_FEAT_BF_PAS_MAX_SHIFT 8
999#define ACPI_IOMMU_FEAT_BF_PAS_MAX_MASK UINT32_C(0x00001f00)
1000/** PNCounters (Number of performance counters per counter bank) supported. */
1001#define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_SHIFT 13
1002#define ACPI_IOMMU_FEAT_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)
1003/** PNBanks (Number of performance counter banks) supported. */
1004#define ACPI_IOMMU_FEAT_BF_PN_BANKS_SHIFT 17
1005#define ACPI_IOMMU_FEAT_BF_PN_BANKS_MASK UINT32_C(0x007e0000)
1006/** MSINumPPR (MSI number for peripheral page requests). */
1007#define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_SHIFT 23
1008#define ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)
1009/** GATS (Guest address translation size). MBZ when GTSup=0. */
1010#define ACPI_IOMMU_FEAT_BF_GATS_SHIFT 28
1011#define ACPI_IOMMU_FEAT_BF_GATS_MASK UINT32_C(0x30000000)
1012/** HATS (Host address translation size). */
1013#define ACPI_IOMMU_FEAT_BF_HATS_SHIFT 30
1014#define ACPI_IOMMU_FEAT_BF_HATS_MASK UINT32_C(0xc0000000)
1015RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_FEAT_BF_, UINT32_C(0), UINT32_MAX,
1016 (XT_SUP, NX_SUP, GT_SUP, GLX_SUP, IA_SUP, GA_SUP, HE_SUP, PAS_MAX, PN_COUNTERS, PN_BANKS,
1017 MSI_NUM_PPR, GATS, HATS));
1018/** @} */
1019
1020/** @name IOMMU Extended Feature Register (PCI/MMIO/ACPI).
1021 * In accordance with the AMD spec.
1022 * @{ */
1023/** PreFSup: Prefetch support (RO). */
1024#define IOMMU_EXT_FEAT_BF_PREF_SUP_SHIFT 0
1025#define IOMMU_EXT_FEAT_BF_PREF_SUP_MASK UINT64_C(0x0000000000000001)
1026/** PPRSup: Peripheral Page Request (PPR) support (RO). */
1027#define IOMMU_EXT_FEAT_BF_PPR_SUP_SHIFT 1
1028#define IOMMU_EXT_FEAT_BF_PPR_SUP_MASK UINT64_C(0x0000000000000002)
1029/** XTSup: x2APIC support (RO). */
1030#define IOMMU_EXT_FEAT_BF_X2APIC_SUP_SHIFT 2
1031#define IOMMU_EXT_FEAT_BF_X2APIC_SUP_MASK UINT64_C(0x0000000000000004)
1032/** NXSup: No Execute (PMR and PRIV) support (RO). */
1033#define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_SHIFT 3
1034#define IOMMU_EXT_FEAT_BF_NO_EXEC_SUP_MASK UINT64_C(0x0000000000000008)
1035/** GTSup: Guest Translation support (RO). */
1036#define IOMMU_EXT_FEAT_BF_GT_SUP_SHIFT 4
1037#define IOMMU_EXT_FEAT_BF_GT_SUP_MASK UINT64_C(0x0000000000000010)
1038/** Bit 5 reserved. */
1039#define IOMMU_EXT_FEAT_BF_RSVD_5_SHIFT 5
1040#define IOMMU_EXT_FEAT_BF_RSVD_5_MASK UINT64_C(0x0000000000000020)
1041/** IASup: INVALIDATE_IOMMU_ALL command support (RO). */
1042#define IOMMU_EXT_FEAT_BF_IA_SUP_SHIFT 6
1043#define IOMMU_EXT_FEAT_BF_IA_SUP_MASK UINT64_C(0x0000000000000040)
1044/** GASup: Guest virtual-APIC support (RO). */
1045#define IOMMU_EXT_FEAT_BF_GA_SUP_SHIFT 7
1046#define IOMMU_EXT_FEAT_BF_GA_SUP_MASK UINT64_C(0x0000000000000080)
1047/** HESup: Hardware error registers support (RO). */
1048#define IOMMU_EXT_FEAT_BF_HE_SUP_SHIFT 8
1049#define IOMMU_EXT_FEAT_BF_HE_SUP_MASK UINT64_C(0x0000000000000100)
1050/** PCSup: Performance counters support (RO). */
1051#define IOMMU_EXT_FEAT_BF_PC_SUP_SHIFT 9
1052#define IOMMU_EXT_FEAT_BF_PC_SUP_MASK UINT64_C(0x0000000000000200)
1053/** HATS: Host Address Translation Size (RO). */
1054#define IOMMU_EXT_FEAT_BF_HATS_SHIFT 10
1055#define IOMMU_EXT_FEAT_BF_HATS_MASK UINT64_C(0x0000000000000c00)
1056/** GATS: Guest Address Translation Size (RO). */
1057#define IOMMU_EXT_FEAT_BF_GATS_SHIFT 12
1058#define IOMMU_EXT_FEAT_BF_GATS_MASK UINT64_C(0x0000000000003000)
1059/** GLXSup: Guest CR3 root table level support (RO). */
1060#define IOMMU_EXT_FEAT_BF_GLX_SUP_SHIFT 14
1061#define IOMMU_EXT_FEAT_BF_GLX_SUP_MASK UINT64_C(0x000000000000c000)
1062/** SmiFSup: SMI filter register support (RO). */
1063#define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_SHIFT 16
1064#define IOMMU_EXT_FEAT_BF_SMI_FLT_SUP_MASK UINT64_C(0x0000000000030000)
1065/** SmiFRC: SMI filter register count (RO). */
1066#define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_SHIFT 18
1067#define IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT_MASK UINT64_C(0x00000000001c0000)
1068/** GAMSup: Guest virtual-APIC modes support (RO). */
1069#define IOMMU_EXT_FEAT_BF_GAM_SUP_SHIFT 21
1070#define IOMMU_EXT_FEAT_BF_GAM_SUP_MASK UINT64_C(0x0000000000e00000)
1071/** DualPprLogSup: Dual PPR Log support (RO). */
1072#define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_SHIFT 24
1073#define IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP_MASK UINT64_C(0x0000000003000000)
1074/** Bits 27:26 reserved. */
1075#define IOMMU_EXT_FEAT_BF_RSVD_26_27_SHIFT 26
1076#define IOMMU_EXT_FEAT_BF_RSVD_26_27_MASK UINT64_C(0x000000000c000000)
1077/** DualEventLogSup: Dual Event Log support (RO). */
1078#define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_SHIFT 28
1079#define IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP_MASK UINT64_C(0x0000000030000000)
1080/** Bits 31:30 reserved. */
1081#define IOMMU_EXT_FEAT_BF_RSVD_30_31_SHIFT 30
1082#define IOMMU_EXT_FEAT_BF_RSVD_30_31_MASK UINT64_C(0x00000000c0000000)
1083/** PASMax: Maximum PASID support (RO). */
1084#define IOMMU_EXT_FEAT_BF_PASID_MAX_SHIFT 32
1085#define IOMMU_EXT_FEAT_BF_PASID_MAX_MASK UINT64_C(0x0000001f00000000)
1086/** USSup: User/Supervisor support (RO). */
1087#define IOMMU_EXT_FEAT_BF_US_SUP_SHIFT 37
1088#define IOMMU_EXT_FEAT_BF_US_SUP_MASK UINT64_C(0x0000002000000000)
1089/** DevTblSegSup: Segmented Device Table support (RO). */
1090#define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_SHIFT 38
1091#define IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP_MASK UINT64_C(0x000000c000000000)
1092/** PprOverflwEarlySup: PPR Log Overflow Early warning support (RO). */
1093#define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_SHIFT 40
1094#define IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY_MASK UINT64_C(0x0000010000000000)
1095/** PprAutoRspSup: PPR Automatic Response support (RO). */
1096#define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_SHIFT 41
1097#define IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP_MASK UINT64_C(0x0000020000000000)
1098/** MarcSup: Memory Access and Routing (MARC) support (RO). */
1099#define IOMMU_EXT_FEAT_BF_MARC_SUP_SHIFT 42
1100#define IOMMU_EXT_FEAT_BF_MARC_SUP_MASK UINT64_C(0x00000c0000000000)
1101/** BlkStopMrkSup: Block StopMark message support (RO). */
1102#define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_SHIFT 44
1103#define IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP_MASK UINT64_C(0x0000100000000000)
1104/** PerfOptSup: IOMMU Performance Optimization support (RO). */
1105#define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_SHIFT 45
1106#define IOMMU_EXT_FEAT_BF_PERF_OPT_SUP_MASK UINT64_C(0x0000200000000000)
1107/** MsiCapMmioSup: MSI-Capability Register MMIO access support (RO). */
1108#define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_SHIFT 46
1109#define IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP_MASK UINT64_C(0x0000400000000000)
1110/** Bit 47 reserved. */
1111#define IOMMU_EXT_FEAT_BF_RSVD_47_SHIFT 47
1112#define IOMMU_EXT_FEAT_BF_RSVD_47_MASK UINT64_C(0x0000800000000000)
1113/** GIoSup: Guest I/O Protection support (RO). */
1114#define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_SHIFT 48
1115#define IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP_MASK UINT64_C(0x0001000000000000)
1116/** HASup: Host Access support (RO). */
1117#define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_SHIFT 49
1118#define IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP_MASK UINT64_C(0x0002000000000000)
1119/** EPHSup: Enhandled PPR Handling support (RO). */
1120#define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_SHIFT 50
1121#define IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP_MASK UINT64_C(0x0004000000000000)
1122/** AttrFWSup: Attribute Forward support (RO). */
1123#define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_SHIFT 51
1124#define IOMMU_EXT_FEAT_BF_ATTR_FW_SUP_MASK UINT64_C(0x0008000000000000)
1125/** HDSup: Host Dirty Support (RO). */
1126#define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_SHIFT 52
1127#define IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP_MASK UINT64_C(0x0010000000000000)
1128/** Bit 53 reserved. */
1129#define IOMMU_EXT_FEAT_BF_RSVD_53_SHIFT 53
1130#define IOMMU_EXT_FEAT_BF_RSVD_53_MASK UINT64_C(0x0020000000000000)
1131/** InvIotlbTypeSup: Invalidate IOTLB type support (RO). */
1132#define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_SHIFT 54
1133#define IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP_MASK UINT64_C(0x0040000000000000)
1134/** Bits 60:55 reserved. */
1135#define IOMMU_EXT_FEAT_BF_RSVD_55_60_SHIFT 55
1136#define IOMMU_EXT_FEAT_BF_RSVD_55_60_MASK UINT64_C(0x1f80000000000000)
1137/** GAUpdateDisSup: Support disabling hardware update on guest page table access
1138 * (RO). */
1139#define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_SHIFT 61
1140#define IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP_MASK UINT64_C(0x2000000000000000)
1141/** ForcePhysDestSup: Force Physical Destination Mode for Remapped Interrupt
1142 * support (RO). */
1143#define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_SHIFT 62
1144#define IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP_MASK UINT64_C(0x4000000000000000)
1145/** Bit 63 reserved. */
1146#define IOMMU_EXT_FEAT_BF_RSVD_63_SHIFT 63
1147#define IOMMU_EXT_FEAT_BF_RSVD_63_MASK UINT64_C(0x8000000000000000)
1148RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_EXT_FEAT_BF_, UINT64_C(0), UINT64_MAX,
1149 (PREF_SUP, PPR_SUP, X2APIC_SUP, NO_EXEC_SUP, GT_SUP, RSVD_5, IA_SUP, GA_SUP, HE_SUP, PC_SUP,
1150 HATS, GATS, GLX_SUP, SMI_FLT_SUP, SMI_FLT_REG_CNT, GAM_SUP, DUAL_PPR_LOG_SUP, RSVD_26_27,
1151 DUAL_EVT_LOG_SUP, RSVD_30_31, PASID_MAX, US_SUP, DEV_TBL_SEG_SUP, PPR_OVERFLOW_EARLY,
1152 PPR_AUTO_RES_SUP, MARC_SUP, BLKSTOP_MARK_SUP, PERF_OPT_SUP, MSI_CAP_MMIO_SUP, RSVD_47,
1153 GST_IO_PROT_SUP, HST_ACCESS_SUP, ENHANCED_PPR_SUP, ATTR_FW_SUP, HST_DIRTY_SUP, RSVD_53,
1154 INV_IOTLB_TYPE_SUP, RSVD_55_60, GA_UPDATE_DIS_SUP, FORCE_PHYS_DST_SUP, RSVD_63));
1155/** @} */
1156
1157/** IVHD (I/O Virtualization Hardware Definition) Type 10h.
1158 * In accordance with the AMD spec. */
1159typedef struct ACPIIVHDTYPE10
1160{
1161 uint8_t u8Type; /**< Type: Must be 0x10. */
1162 uint8_t u8Flags; /**< Flags (see ACPI_IVHD_10H_F_XXX). */
1163 uint16_t u16Length; /**< Length of IVHD including IVHD device entries. */
1164 uint16_t u16DeviceId; /**< Device ID of the IOMMU. */
1165 uint16_t u16CapOffset; /**< Offset in Capability space for control fields of IOMMU. */
1166 uint64_t u64BaseAddress; /**< Base address of IOMMU control registers in MMIO space. */
1167 uint16_t u16PciSegmentGroup; /**< PCI segment group number. */
1168 uint16_t u16IommuInfo; /**< Interrupt number and Unit ID. */
1169 uint32_t u32Features; /**< IOMMU feature reporting. */
1170 /* IVHD device entry block follows. */
1171} ACPIIVHDTYPE10;
1172AssertCompileSize(ACPIIVHDTYPE10, 24);
1173
1174/** @name IVHD Type 11h Flags.
1175 * In accordance with the AMD spec.
1176 * @{ */
1177/** Coherent control. */
1178#define ACPI_IVHD_11H_F_COHERENT RT_BIT(5)
1179/** Remote IOTLB support. */
1180#define ACPI_IVHD_11H_F_IOTLB_SUP RT_BIT(4)
1181/** Isochronous control. */
1182#define ACPI_IVHD_11H_F_ISOC RT_BIT(3)
1183/** Response Pass Posted Write. */
1184#define ACPI_IVHD_11H_F_RES_PASS_PW RT_BIT(2)
1185/** Pass Posted Write. */
1186#define ACPI_IVHD_11H_F_PASS_PW RT_BIT(1)
1187/** HyperTransport Tunnel. */
1188#define ACPI_IVHD_11H_F_HT_TUNNEL RT_BIT(0)
1189/** @} */
1190
1191/** @name IVHD IOMMU Type 11 Attributes field.
1192 * In accordance with the AMD spec.
1193 * @{ */
1194/** Bits 12:0 reserved. */
1195#define ACPI_IOMMU_ATTR_BF_RSVD_0_12_SHIFT 0
1196#define ACPI_IOMMU_ATTR_BF_RSVD_0_12_MASK UINT32_C(0x00001fff)
1197/** PNCounters: Number of performance counters per counter bank. */
1198#define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_SHIFT 13
1199#define ACPI_IOMMU_ATTR_BF_PN_COUNTERS_MASK UINT32_C(0x0001e000)
1200/** PNBanks: Number of performance counter banks. */
1201#define ACPI_IOMMU_ATTR_BF_PN_BANKS_SHIFT 17
1202#define ACPI_IOMMU_ATTR_BF_PN_BANKS_MASK UINT32_C(0x007e0000)
1203/** MSINumPPR: MSI number for peripheral page requests (PPR). */
1204#define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_SHIFT 23
1205#define ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR_MASK UINT32_C(0x0f800000)
1206/** Bits 31:28 reserved. */
1207#define ACPI_IOMMU_ATTR_BF_RSVD_28_31_SHIFT 28
1208#define ACPI_IOMMU_ATTR_BF_RSVD_28_31_MASK UINT32_C(0xf0000000)
1209RT_BF_ASSERT_COMPILE_CHECKS(ACPI_IOMMU_ATTR_BF_, UINT32_C(0), UINT32_MAX,
1210 (RSVD_0_12, PN_COUNTERS, PN_BANKS, MSI_NUM_PPR, RSVD_28_31));
1211/** @} */
1212
1213/** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 11h.
1214 * In accordance with the AMD spec. */
1215typedef struct ACPIIVHDTYPE11
1216{
1217 uint8_t u8Type; /**< Type: Must be 0x11. */
1218 uint8_t u8Flags; /**< Flags. */
1219 uint16_t u16Length; /**< Length: Size starting from Type fields incl. IVHD device entries. */
1220 uint16_t u16DeviceId; /**< Device ID of the IOMMU. */
1221 uint16_t u16CapOffset; /**< Offset in Capability space for control fields of IOMMU. */
1222 uint64_t u64BaseAddress; /**< Base address of IOMMU control registers in MMIO space. */
1223 uint16_t u16PciSegmentGroup; /**< PCI segment group number. */
1224 uint16_t u16IommuInfo; /**< Interrupt number and unit ID. */
1225 uint32_t u32IommuAttr; /**< IOMMU info. not reported in EFR. */
1226 uint64_t u64EfrRegister; /**< Extended Feature Register (must be identical to its MMIO shadow). */
1227 uint64_t u64Rsvd0; /**< Reserved for future. */
1228 /* IVHD device entry block follows. */
1229} ACPIIVHDTYPE11;
1230AssertCompileSize(ACPIIVHDTYPE11, 40);
1231
1232/** AMD IOMMU: IVHD (I/O Virtualization Hardware Definition) Type 40h.
1233 * In accordance with the AMD spec. */
1234typedef struct ACPIIVHDTYPE11 ACPIIVHDTYPE40;
1235
1236/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
1237 * In accordance with the AMD spec. */
1238typedef struct ACPIIVRS
1239{
1240 ACPITBLHEADER header;
1241 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
1242 uint64_t u64Rsvd; /**< Reserved (MBZ). */
1243 /* IVHD type block follows. */
1244} ACPIIVRS;
1245AssertCompileSize(ACPIIVRS, 48);
1246AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
1247
1248/**
1249 * AMD IOMMU: The ACPI table.
1250 */
1251typedef struct ACPITBLIOMMU
1252{
1253 ACPIIVRS Hdr;
1254 ACPIIVHDTYPE10 IvhdType10;
1255 ACPIIVHDDEVENTRY4 IvhdType10Start;
1256 ACPIIVHDDEVENTRY4 IvhdType10End;
1257 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
1258 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
1259 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
1260 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
1261
1262 ACPIIVHDTYPE11 IvhdType11;
1263 ACPIIVHDDEVENTRY4 IvhdType11Start;
1264 ACPIIVHDDEVENTRY4 IvhdType11End;
1265 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
1266 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
1267 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
1268 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
1269} ACPITBLIOMMU;
1270AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
1271AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
1272AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
1273AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
1274#endif
1275
1276/** MCFG Descriptor Structure */
1277typedef struct ACPITBLMCFG
1278{
1279 ACPITBLHEADER aHeader;
1280 uint64_t u64Reserved;
1281} ACPITBLMCFG;
1282AssertCompileSize(ACPITBLMCFG, 44);
1283
1284/** Number of such entries can be computed from the whole table length in header */
1285typedef struct ACPITBLMCFGENTRY
1286{
1287 uint64_t u64BaseAddress;
1288 uint16_t u16PciSegmentGroup;
1289 uint8_t u8StartBus;
1290 uint8_t u8EndBus;
1291 uint32_t u32Reserved;
1292} ACPITBLMCFGENTRY;
1293AssertCompileSize(ACPITBLMCFGENTRY, 16);
1294
1295#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
1296
1297/** Custom Description Table */
1298struct ACPITBLCUST
1299{
1300 ACPITBLHEADER header;
1301 uint8_t au8Data[476];
1302};
1303AssertCompileSize(ACPITBLCUST, 512);
1304
1305
1306#pragma pack()
1307
1308
1309#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
1310
1311
1312/*********************************************************************************************************************************
1313* Internal Functions *
1314*********************************************************************************************************************************/
1315#ifdef IN_RING3
1316static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
1317#endif
1318
1319/* SCI, usually IRQ9 */
1320DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
1321{
1322 PDMDevHlpPCISetIrq(pDevIns, 0, level);
1323}
1324
1325DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
1326{
1327 return (pThis->pm1a_ctl & SCI_EN)
1328 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
1329}
1330
1331DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
1332{
1333 return !!(pThis->gpe0_en & pThis->gpe0_sts);
1334}
1335
1336DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
1337{
1338 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1339 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
1340 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
1341 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
1342 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
1343}
1344
1345DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
1346{
1347 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
1348}
1349
1350/**
1351 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
1352 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
1353 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
1354 * registers and trigger IRQs.
1355 *
1356 * Caller must hold the state lock.
1357 *
1358 * @param pDevIns The PDM device instance.
1359 * @param pThis The ACPI shared instance data.
1360 * @param sts The new PM1a.STS value.
1361 * @param en The new PM1a.EN value.
1362 */
1363static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1364{
1365 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1366
1367 const bool old_level = acpiSCILevel(pDevIns, pThis);
1368 pThis->pm1a_en = en;
1369 pThis->pm1a_sts = sts;
1370 const bool new_level = acpiSCILevel(pDevIns, pThis);
1371
1372 LogFunc(("old=%x new=%x\n", old_level, new_level));
1373
1374 if (new_level != old_level)
1375 acpiSetIrq(pDevIns, new_level);
1376}
1377
1378#ifdef IN_RING3
1379
1380/**
1381 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
1382 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
1383 *
1384 * Caller must hold the state lock.
1385 *
1386 * @param pDevIns The PDM device instance.
1387 * @param pThis The ACPI shared instance data.
1388 * @param sts The new GPE0.STS value.
1389 * @param en The new GPE0.EN value.
1390 */
1391static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1392{
1393 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1394
1395 const bool old_level = acpiSCILevel(pDevIns, pThis);
1396 pThis->gpe0_en = en;
1397 pThis->gpe0_sts = sts;
1398 const bool new_level = acpiSCILevel(pDevIns, pThis);
1399
1400 LogFunc(("old=%x new=%x\n", old_level, new_level));
1401
1402 if (new_level != old_level)
1403 acpiSetIrq(pDevIns, new_level);
1404}
1405
1406/**
1407 * Used by acpiR3PM1aCtlWrite to power off the VM.
1408 *
1409 * @param pDevIns The device instance.
1410 * @returns Strict VBox status code.
1411 */
1412static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
1413{
1414 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
1415 AssertRC(VBOXSTRICTRC_VAL(rc));
1416 return rc;
1417}
1418
1419/**
1420 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
1421 *
1422 * @param pDevIns The device instance.
1423 * @param pThis The ACPI shared instance data.
1424 * @returns Strict VBox status code.
1425 */
1426static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
1427{
1428 /* We must set WAK_STS on resume (includes restore) so the guest knows that
1429 we've woken up and can continue executing code. The guest is probably
1430 reading the PMSTS register in a loop to check this. */
1431 VBOXSTRICTRC rc;
1432 pThis->fSetWakeupOnResume = true;
1433 if (pThis->fSuspendToSavedState)
1434 {
1435 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
1436 if (rc != VERR_NOT_SUPPORTED)
1437 AssertRC(VBOXSTRICTRC_VAL(rc));
1438 else
1439 {
1440 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
1441 rc = PDMDevHlpVMSuspend(pDevIns);
1442 AssertRC(VBOXSTRICTRC_VAL(rc));
1443 }
1444 }
1445 else
1446 {
1447 rc = PDMDevHlpVMSuspend(pDevIns);
1448 AssertRC(VBOXSTRICTRC_VAL(rc));
1449 }
1450 return rc;
1451}
1452
1453
1454/**
1455 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
1456 */
1457static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
1458{
1459 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1460 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1461 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1462 DEVACPI_LOCK_R3(pDevIns, pThis);
1463
1464 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1465 pThis->fPowerButtonHandled = false;
1466 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1467
1468 DEVACPI_UNLOCK(pDevIns, pThis);
1469 return VINF_SUCCESS;
1470}
1471
1472/**
1473 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
1474 */
1475static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1476{
1477 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1478 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1479 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1480 DEVACPI_LOCK_R3(pDevIns, pThis);
1481
1482 *pfHandled = pThis->fPowerButtonHandled;
1483
1484 DEVACPI_UNLOCK(pDevIns, pThis);
1485 return VINF_SUCCESS;
1486}
1487
1488/**
1489 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1490 * Guest entered into G0 (working) or G1 (sleeping)}
1491 */
1492static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1493{
1494 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1495 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1496 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1497 DEVACPI_LOCK_R3(pDevIns, pThis);
1498
1499 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1500
1501 DEVACPI_UNLOCK(pDevIns, pThis);
1502 return VINF_SUCCESS;
1503}
1504
1505/**
1506 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1507 */
1508static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1509{
1510 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1511 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1512 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1513 DEVACPI_LOCK_R3(pDevIns, pThis);
1514
1515 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1516
1517 DEVACPI_UNLOCK(pDevIns, pThis);
1518 return VINF_SUCCESS;
1519}
1520
1521/**
1522 * Send an ACPI sleep button event.
1523 *
1524 * @returns VBox status code
1525 * @param pInterface Pointer to the interface structure containing the called function pointer.
1526 */
1527static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1528{
1529 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1530 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1531 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1532 DEVACPI_LOCK_R3(pDevIns, pThis);
1533
1534 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1535
1536 DEVACPI_UNLOCK(pDevIns, pThis);
1537 return VINF_SUCCESS;
1538}
1539
1540/**
1541 * Send an ACPI monitor hot-plug event.
1542 *
1543 * @returns VBox status code
1544 * @param pInterface Pointer to the interface structure containing the
1545 * called function pointer.
1546 */
1547static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1548{
1549 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1550 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1551 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1552 DEVACPI_LOCK_R3(pDevIns, pThis);
1553
1554 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1555
1556 DEVACPI_UNLOCK(pDevIns, pThis);
1557 return VINF_SUCCESS;
1558}
1559
1560/**
1561 * Send an ACPI battery status change event.
1562 *
1563 * @returns VBox status code
1564 * @param pInterface Pointer to the interface structure containing the
1565 * called function pointer.
1566 */
1567static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1568{
1569 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1570 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1571 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1572 DEVACPI_LOCK_R3(pDevIns, pThis);
1573
1574 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1575
1576 DEVACPI_UNLOCK(pDevIns, pThis);
1577 return VINF_SUCCESS;
1578}
1579
1580/**
1581 * Used by acpiR3PmTimer to re-arm the PM timer.
1582 *
1583 * The caller is expected to either hold the clock lock or to have made sure
1584 * the VM is resetting or loading state.
1585 *
1586 * @param pDevIns The device instance.
1587 * @param pThis The ACPI shared instance data.
1588 * @param uNow The current time.
1589 */
1590static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1591{
1592 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1593 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1594 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1595 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1596 Log(("acpi: uInterval = %RU64\n", uInterval));
1597}
1598
1599#endif /* IN_RING3 */
1600
1601/**
1602 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1603 *
1604 * The caller is expected to either hold the clock lock or to have made sure
1605 * the VM is resetting or loading state.
1606 *
1607 * @param pDevIns The PDM device instance.
1608 * @param pThis The ACPI instance
1609 * @param u64Now The current time
1610 */
1611static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1612{
1613 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1614 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1615 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1616
1617 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ,
1618 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1619 & TMR_VAL_MASK;
1620
1621 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1622 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1623}
1624
1625#ifdef IN_RING3
1626
1627/**
1628 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1629 */
1630static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1631{
1632 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1633 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1634 RT_NOREF(pTimer, pvUser);
1635
1636 DEVACPI_LOCK_R3(pDevIns, pThis);
1637 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1638 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1639 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1640 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1641 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1642 DEVACPI_UNLOCK(pDevIns, pThis);
1643
1644 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
1645}
1646
1647/**
1648 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1649 * acpiR3LoadState.
1650 *
1651 * @returns VINF_SUCCESS.
1652 * @param pThis The ACPI shared instance data.
1653 * @param pThisCC The ACPI instance data for ring-3.
1654 */
1655static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1656{
1657 uint32_t *p = pThis->au8BatteryInfo;
1658 bool fPresent; /* battery present? */
1659 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1660 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1661 uint32_t hostPresentRate; /* 0..1000 */
1662 int rc;
1663
1664 if (!pThisCC->pDrv)
1665 return VINF_SUCCESS;
1666 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1667 &hostBatteryState, &hostPresentRate);
1668 AssertRC(rc);
1669
1670 /* default values */
1671 p[BAT_STATUS_STATE] = hostBatteryState;
1672 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1673 : hostPresentRate * 50; /* mW */
1674 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1675 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1676
1677 /* did we get a valid battery state? */
1678 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1679 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1680 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1681 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1682
1683 return VINF_SUCCESS;
1684}
1685
1686/**
1687 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1688 * acpiR3LoadState.
1689 *
1690 * @returns VINF_SUCCESS.
1691 * @param pThis The ACPI shared instance data.
1692 */
1693static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1694{
1695 uint32_t *p = pThis->au8BatteryInfo;
1696
1697 p[BAT_INFO_UNITS] = 0; /* mWh */
1698 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1699 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1700 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1701 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1702 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1703 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1704 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1705 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1706
1707 return VINF_SUCCESS;
1708}
1709
1710/**
1711 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1712 *
1713 * @returns status mask or 0.
1714 * @param pThisCC The ACPI instance data for ring-3.
1715 */
1716static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1717{
1718 bool fPresent; /* battery present? */
1719 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1720 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1721 uint32_t hostPresentRate; /* 0..1000 */
1722 int rc;
1723
1724 if (!pThisCC->pDrv)
1725 return 0;
1726 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1727 &hostBatteryState, &hostPresentRate);
1728 AssertRC(rc);
1729
1730 return fPresent
1731 ? STA_DEVICE_PRESENT_MASK /* present */
1732 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1733 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1734 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1735 | STA_BATTERY_PRESENT_MASK /* battery is present */
1736 : 0; /* device not present */
1737}
1738
1739/**
1740 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1741 *
1742 * @returns status.
1743 * @param pThisCC The ACPI instance data for ring-3.
1744 */
1745static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1746{
1747 /* query the current power source from the host driver */
1748 if (!pThisCC->pDrv)
1749 return AC_ONLINE;
1750
1751 PDMACPIPOWERSOURCE ps;
1752 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1753 AssertRC(rc);
1754 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1755}
1756
1757/**
1758 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1759 */
1760static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1761{
1762 RT_NOREF(pvUser, offPort);
1763 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1764 if (cb != 4)
1765 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1766
1767 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1768 DEVACPI_LOCK_R3(pDevIns, pThis);
1769
1770 u32 >>= pThis->u8IndexShift;
1771 /* see comment at the declaration of u8IndexShift */
1772 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1773 {
1774 pThis->u8IndexShift = 2;
1775 u32 >>= 2;
1776 }
1777 Assert(u32 < BAT_INDEX_LAST);
1778 pThis->uBatteryIndex = u32;
1779
1780 DEVACPI_UNLOCK(pDevIns, pThis);
1781 return VINF_SUCCESS;
1782}
1783
1784/**
1785 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1786 */
1787static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1788{
1789 RT_NOREF(pvUser, offPort);
1790 if (cb != 4)
1791 return VERR_IOM_IOPORT_UNUSED;
1792
1793 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1794 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1795 DEVACPI_LOCK_R3(pDevIns, pThis);
1796
1797 VBOXSTRICTRC rc = VINF_SUCCESS;
1798 switch (pThis->uBatteryIndex)
1799 {
1800 case BAT_STATUS_STATE:
1801 acpiR3FetchBatteryStatus(pThis, pThisCC);
1802 RT_FALL_THRU();
1803 case BAT_STATUS_PRESENT_RATE:
1804 case BAT_STATUS_REMAINING_CAPACITY:
1805 case BAT_STATUS_PRESENT_VOLTAGE:
1806 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1807 break;
1808
1809 case BAT_INFO_UNITS:
1810 acpiR3FetchBatteryInfo(pThis);
1811 RT_FALL_THRU();
1812 case BAT_INFO_DESIGN_CAPACITY:
1813 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1814 case BAT_INFO_TECHNOLOGY:
1815 case BAT_INFO_DESIGN_VOLTAGE:
1816 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1817 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1818 case BAT_INFO_CAPACITY_GRANULARITY_1:
1819 case BAT_INFO_CAPACITY_GRANULARITY_2:
1820 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1821 break;
1822
1823 case BAT_DEVICE_STATUS:
1824 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1825 break;
1826
1827 case BAT_POWER_SOURCE:
1828 *pu32 = acpiR3GetPowerSource(pThisCC);
1829 break;
1830
1831 default:
1832 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1833 *pu32 = UINT32_MAX;
1834 break;
1835 }
1836
1837 DEVACPI_UNLOCK(pDevIns, pThis);
1838 return rc;
1839}
1840
1841/**
1842 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1843 */
1844static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1845{
1846 RT_NOREF(pvUser, offPort);
1847 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1848 if (cb != 4)
1849 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1850
1851 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1852 DEVACPI_LOCK_R3(pDevIns, pThis);
1853
1854 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1855 pThis->uSystemInfoIndex = u32;
1856 else
1857 {
1858 /* see comment at the declaration of u8IndexShift */
1859 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1860 {
1861 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1862 pThis->u8IndexShift = 2;
1863 }
1864
1865 u32 >>= pThis->u8IndexShift;
1866 AssertMsg(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1867 pThis->uSystemInfoIndex = u32;
1868 }
1869
1870 DEVACPI_UNLOCK(pDevIns, pThis);
1871 return VINF_SUCCESS;
1872}
1873
1874/**
1875 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1876 */
1877static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1878{
1879 RT_NOREF(pvUser, offPort);
1880 if (cb != 4)
1881 return VERR_IOM_IOPORT_UNUSED;
1882
1883 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1884 DEVACPI_LOCK_R3(pDevIns, pThis);
1885
1886 VBOXSTRICTRC rc = VINF_SUCCESS;
1887 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1888 switch (uSystemInfoIndex)
1889 {
1890 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1891 *pu32 = pThis->cbRamLow;
1892 break;
1893
1894 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1895 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1896 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1897 break;
1898
1899 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1900 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1901 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1902 break;
1903
1904 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1905 *pu32 = pThis->u8UseIOApic;
1906 break;
1907
1908 case SYSTEM_INFO_INDEX_HPET_STATUS:
1909 *pu32 = pThis->fUseHpet
1910 ? ( STA_DEVICE_PRESENT_MASK
1911 | STA_DEVICE_ENABLED_MASK
1912 | STA_DEVICE_SHOW_IN_UI_MASK
1913 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1914 : 0;
1915 break;
1916
1917 case SYSTEM_INFO_INDEX_SMC_STATUS:
1918 *pu32 = pThis->fUseSmc
1919 ? ( STA_DEVICE_PRESENT_MASK
1920 | STA_DEVICE_ENABLED_MASK
1921 /* no need to show this device in the UI */
1922 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1923 : 0;
1924 break;
1925
1926 case SYSTEM_INFO_INDEX_FDC_STATUS:
1927 *pu32 = pThis->fUseFdc
1928 ? ( STA_DEVICE_PRESENT_MASK
1929 | STA_DEVICE_ENABLED_MASK
1930 | STA_DEVICE_SHOW_IN_UI_MASK
1931 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1932 : 0;
1933 break;
1934
1935 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1936 *pu32 = pThis->u32NicPciAddress;
1937 break;
1938
1939 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1940 *pu32 = pThis->u32AudioPciAddress;
1941 break;
1942
1943 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1944 *pu32 = pThis->u32NvmePciAddress;
1945 break;
1946
1947 case SYSTEM_INFO_INDEX_POWER_STATES:
1948 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1949 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1950 *pu32 |= RT_BIT(1);
1951 if (pThis->fS4Enabled)
1952 *pu32 |= RT_BIT(4);
1953 break;
1954
1955 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1956 *pu32 = pThis->u32IocPciAddress;
1957 break;
1958
1959 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1960 *pu32 = pThis->u32HbcPciAddress;
1961 break;
1962
1963 case SYSTEM_INFO_INDEX_PCI_BASE:
1964 /** @todo couldn't MCFG be in 64-bit range? */
1965 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1966 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1967 break;
1968
1969 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1970 /** @todo couldn't MCFG be in 64-bit range? */
1971 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1972 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1973 break;
1974
1975 case SYSTEM_INFO_INDEX_RTC_STATUS:
1976 *pu32 = pThis->fShowRtc
1977 ? ( STA_DEVICE_PRESENT_MASK
1978 | STA_DEVICE_ENABLED_MASK
1979 | STA_DEVICE_SHOW_IN_UI_MASK
1980 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1981 : 0;
1982 break;
1983
1984 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1985 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1986 {
1987 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1988 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1989 }
1990 else
1991 {
1992 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1993 pThis->idCpuLockCheck);
1994 /* Always return locked status just to be safe */
1995 *pu32 = 1;
1996 }
1997 break;
1998
1999 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
2000 *pu32 = pThis->u32CpuEventType;
2001 break;
2002
2003 case SYSTEM_INFO_INDEX_CPU_EVENT:
2004 *pu32 = pThis->u32CpuEvent;
2005 break;
2006
2007 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
2008 *pu32 = pThis->uSerial0IoPortBase;
2009 break;
2010
2011 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
2012 *pu32 = pThis->uSerial0Irq;
2013 break;
2014
2015 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
2016 *pu32 = pThis->uSerial1IoPortBase;
2017 break;
2018
2019 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
2020 *pu32 = pThis->uSerial1Irq;
2021 break;
2022
2023 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
2024 *pu32 = pThis->uSerial2IoPortBase;
2025 break;
2026
2027 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
2028 *pu32 = pThis->uSerial2Irq;
2029 break;
2030
2031 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
2032 *pu32 = pThis->uSerial3IoPortBase;
2033 break;
2034
2035 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
2036 *pu32 = pThis->uSerial3Irq;
2037 break;
2038
2039 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
2040 *pu32 = pThis->uParallel0IoPortBase;
2041 break;
2042
2043 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
2044 *pu32 = pThis->uParallel0Irq;
2045 break;
2046
2047 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
2048 *pu32 = pThis->uParallel1IoPortBase;
2049 break;
2050
2051 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
2052 *pu32 = pThis->uParallel1Irq;
2053 break;
2054
2055 case SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS:
2056 *pu32 = pThis->u32IommuAmdPciAddress;
2057 break;
2058
2059 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
2060 *pu32 = pThis->u32SbIoApicPciAddress;
2061 break;
2062
2063 case SYSTEM_INFO_INDEX_END:
2064 /** @todo why isn't this setting any output value? */
2065 break;
2066
2067 /* Solaris 9 tries to read from this index */
2068 case SYSTEM_INFO_INDEX_INVALID:
2069 *pu32 = 0;
2070 break;
2071
2072 default:
2073 *pu32 = UINT32_MAX;
2074 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
2075 break;
2076 }
2077
2078 DEVACPI_UNLOCK(pDevIns, pThis);
2079 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
2080 return rc;
2081}
2082
2083/**
2084 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
2085 */
2086static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2087{
2088 RT_NOREF(pvUser, offPort);
2089 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2090 if (cb != 4)
2091 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
2092
2093 DEVACPI_LOCK_R3(pDevIns, pThis);
2094 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
2095
2096 VBOXSTRICTRC rc = VINF_SUCCESS;
2097 switch (pThis->uSystemInfoIndex)
2098 {
2099 case SYSTEM_INFO_INDEX_INVALID:
2100 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
2101 pThis->u8IndexShift = 0;
2102 break;
2103
2104 case SYSTEM_INFO_INDEX_VALID:
2105 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
2106 pThis->u8IndexShift = 2;
2107 break;
2108
2109 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
2110 pThis->idCpuLockCheck = u32;
2111 break;
2112
2113 case SYSTEM_INFO_INDEX_CPU_LOCKED:
2114 if (u32 < pThis->cCpus)
2115 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
2116 else
2117 LogRel(("ACPI: CPU %u does not exist\n", u32));
2118 break;
2119
2120 default:
2121 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
2122 break;
2123 }
2124
2125 DEVACPI_UNLOCK(pDevIns, pThis);
2126 return rc;
2127}
2128
2129/**
2130 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
2131 */
2132static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2133{
2134 RT_NOREF(offPort, pvUser);
2135 if (cb != 2)
2136 return VERR_IOM_IOPORT_UNUSED;
2137
2138 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2139 DEVACPI_LOCK_R3(pDevIns, pThis);
2140
2141 *pu32 = pThis->pm1a_en;
2142
2143 DEVACPI_UNLOCK(pDevIns, pThis);
2144 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
2145 return VINF_SUCCESS;
2146}
2147
2148/**
2149 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
2150 */
2151static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2152{
2153 RT_NOREF(offPort, pvUser);
2154 if (cb != 2 && cb != 4)
2155 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2156
2157 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2158 DEVACPI_LOCK_R3(pDevIns, pThis);
2159
2160 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
2161 u32 &= ~(RSR_EN | IGN_EN);
2162 u32 &= 0xffff;
2163 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
2164
2165 DEVACPI_UNLOCK(pDevIns, pThis);
2166 return VINF_SUCCESS;
2167}
2168
2169/**
2170 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
2171 */
2172static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2173{
2174 RT_NOREF(offPort, pvUser);
2175 if (cb != 2)
2176 {
2177 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2178 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2179 }
2180
2181 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2182 DEVACPI_LOCK_R3(pDevIns, pThis);
2183
2184 *pu32 = pThis->pm1a_sts;
2185
2186 DEVACPI_UNLOCK(pDevIns, pThis);
2187 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
2188 return VINF_SUCCESS;
2189}
2190
2191/**
2192 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
2193 */
2194static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2195{
2196 RT_NOREF(offPort, pvUser);
2197 if (cb != 2 && cb != 4)
2198 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2199
2200 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2201 DEVACPI_LOCK_R3(pDevIns, pThis);
2202
2203 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
2204 u32 &= 0xffff;
2205 if (u32 & PWRBTN_STS)
2206 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
2207 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
2208 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
2209
2210 DEVACPI_UNLOCK(pDevIns, pThis);
2211 return VINF_SUCCESS;
2212}
2213
2214/**
2215 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
2216 */
2217static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2218{
2219 RT_NOREF(offPort, pvUser);
2220 if (cb != 2)
2221 {
2222 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2223 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2224 }
2225
2226 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2227 DEVACPI_LOCK_R3(pDevIns, pThis);
2228
2229 *pu32 = pThis->pm1a_ctl;
2230
2231 DEVACPI_UNLOCK(pDevIns, pThis);
2232 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
2233 return VINF_SUCCESS;
2234}
2235
2236/**
2237 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
2238 */
2239static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2240{
2241 RT_NOREF(offPort, pvUser);
2242 if (cb != 2 && cb != 4)
2243 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2244
2245 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2246 DEVACPI_LOCK_R3(pDevIns, pThis);
2247
2248 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
2249 u32 &= 0xffff;
2250 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
2251
2252 VBOXSTRICTRC rc = VINF_SUCCESS;
2253 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
2254 if (uSleepState != pThis->uSleepState)
2255 {
2256 pThis->uSleepState = uSleepState;
2257 switch (uSleepState)
2258 {
2259 case 0x00: /* S0 */
2260 break;
2261
2262 case 0x01: /* S1 */
2263 if (pThis->fS1Enabled)
2264 {
2265 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
2266 rc = acpiR3DoSleep(pDevIns, pThis);
2267 break;
2268 }
2269 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
2270 RT_FALL_THRU();
2271
2272 case 0x04: /* S4 */
2273 if (pThis->fS4Enabled)
2274 {
2275 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
2276 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
2277 break;
2278 }
2279 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
2280 RT_FALL_THRU();
2281
2282 case 0x05: /* S5 */
2283 LogRel(("ACPI: Entering S5 power state (power down)\n"));
2284 rc = acpiR3DoPowerOff(pDevIns);
2285 break;
2286
2287 default:
2288 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
2289 break;
2290 }
2291 }
2292
2293 DEVACPI_UNLOCK(pDevIns, pThis);
2294 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2295 return rc;
2296}
2297
2298#endif /* IN_RING3 */
2299
2300/**
2301 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
2302 *
2303 * @remarks The only I/O port currently implemented in all contexts.
2304 */
2305static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2306{
2307 RT_NOREF(offPort, pvUser);
2308 if (cb != 4)
2309 return VERR_IOM_IOPORT_UNUSED;
2310
2311 /*
2312 * We use the clock lock to serialize access to u64PmTimerInitial and to
2313 * make sure we get a reliable time from the clock
2314 * as well as and to prevent uPmTimerVal from being updated during read.
2315 */
2316 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2317 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
2318 if (rc == VINF_SUCCESS)
2319 {
2320 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2321 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2322 *pu32 = pThis->uPmTimerVal;
2323
2324 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
2325
2326 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
2327 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
2328
2329#if 0
2330 /** @todo temporary: sanity check against running backwards */
2331 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
2332 if (*pu32 - uOld >= 0x10000000)
2333 {
2334# if defined(IN_RING0)
2335 pThis->uPmTimeA = uOld;
2336 pThis->uPmTimeB = *pu32;
2337 return VERR_TM_TIMER_BAD_CLOCK;
2338# elif defined(IN_RING3)
2339 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
2340# endif
2341 }
2342#endif
2343 }
2344 return rc;
2345}
2346
2347#ifdef IN_RING3
2348
2349/**
2350 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
2351 */
2352static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2353{
2354 RT_NOREF(offPort, pvUser);
2355 if (cb != 1)
2356 {
2357 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2358 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2359 }
2360
2361 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2362 DEVACPI_LOCK_R3(pDevIns, pThis);
2363
2364 *pu32 = pThis->gpe0_sts & 0xff;
2365
2366 DEVACPI_UNLOCK(pDevIns, pThis);
2367 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
2368 return VINF_SUCCESS;
2369}
2370
2371/**
2372 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
2373 */
2374static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2375{
2376 RT_NOREF(offPort, pvUser);
2377 if (cb != 1)
2378 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2379
2380 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2381 DEVACPI_LOCK_R3(pDevIns, pThis);
2382
2383 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
2384 u32 = pThis->gpe0_sts & ~u32;
2385 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
2386
2387 DEVACPI_UNLOCK(pDevIns, pThis);
2388 return VINF_SUCCESS;
2389}
2390
2391/**
2392 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
2393 */
2394static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2395{
2396 RT_NOREF(offPort, pvUser);
2397 if (cb != 1)
2398 {
2399 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2400 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2401 }
2402
2403 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2404 DEVACPI_LOCK_R3(pDevIns, pThis);
2405
2406 *pu32 = pThis->gpe0_en & 0xff;
2407
2408 DEVACPI_UNLOCK(pDevIns, pThis);
2409 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
2410 return VINF_SUCCESS;
2411}
2412
2413/**
2414 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
2415 */
2416static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2417{
2418 RT_NOREF(offPort, pvUser);
2419 if (cb != 1)
2420 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2421
2422 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2423 DEVACPI_LOCK_R3(pDevIns, pThis);
2424
2425 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
2426 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
2427
2428 DEVACPI_UNLOCK(pDevIns, pThis);
2429 return VINF_SUCCESS;
2430}
2431
2432/**
2433 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
2434 */
2435static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2436{
2437 RT_NOREF(offPort, pvUser);
2438 Log(("acpiR3SmiWrite %#x\n", u32));
2439 if (cb != 1)
2440 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2441
2442 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2443 DEVACPI_LOCK_R3(pDevIns, pThis);
2444
2445 if (u32 == ACPI_ENABLE)
2446 pThis->pm1a_ctl |= SCI_EN;
2447 else if (u32 == ACPI_DISABLE)
2448 pThis->pm1a_ctl &= ~SCI_EN;
2449 else
2450 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2451
2452 DEVACPI_UNLOCK(pDevIns, pThis);
2453 return VINF_SUCCESS;
2454}
2455
2456/**
2457 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2458 */
2459static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2460{
2461 RT_NOREF(offPort, pvUser);
2462 Log(("acpiR3ResetWrite: %#x\n", u32));
2463 NOREF(pvUser);
2464 if (cb != 1)
2465 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2466
2467 /* No state locking required. */
2468 VBOXSTRICTRC rc;
2469 if (u32 == ACPI_RESET_REG_VAL)
2470 {
2471 LogRel(("ACPI: Reset initiated by ACPI\n"));
2472 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2473 }
2474 else
2475 {
2476 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2477 rc = VINF_SUCCESS;
2478 }
2479
2480 return rc;
2481}
2482
2483# ifdef DEBUG_ACPI
2484
2485/**
2486 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2487 */
2488static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2489{
2490 NOREF(pvUser);
2491 switch (cb)
2492 {
2493 case 1:
2494 Log(("%#x\n", u32 & 0xff));
2495 break;
2496 case 2:
2497 Log(("%#6x\n", u32 & 0xffff));
2498 break;
2499 case 4:
2500 Log(("%#10x\n", u32));
2501 break;
2502 default:
2503 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2504 }
2505 return VINF_SUCCESS;
2506}
2507
2508/**
2509 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2510 */
2511static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2512{
2513 NOREF(pvUser);
2514 switch (cb)
2515 {
2516 case 1:
2517 Log(("%c", u32 & 0xff));
2518 break;
2519 default:
2520 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2521 }
2522 return VINF_SUCCESS;
2523}
2524
2525# endif /* DEBUG_ACPI */
2526
2527/**
2528 * @callback_method_impl{FNDBGFHANDLERDEV}
2529 */
2530static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2531{
2532 RT_NOREF(pszArgs);
2533 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2534 pHlp->pfnPrintf(pHlp,
2535 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2536}
2537
2538/**
2539 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2540 *
2541 * @param pDevIns The PDM device instance.
2542 * @param pThis The ACPI shared instance data.
2543 */
2544static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2545{
2546 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2547 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2548 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2549 pPciDev->abConfig[PMBA + 2] = 0x00;
2550 pPciDev->abConfig[PMBA + 3] = 0x00;
2551}
2552
2553/**
2554 * Used to calculate the value of a PM I/O port.
2555 *
2556 * @returns The actual I/O port value.
2557 * @param pThis The ACPI shared instance data.
2558 * @param offset The offset into the I/O space, or -1 if invalid.
2559 */
2560static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2561{
2562 Assert(pThis->uPmIoPortBase != 0);
2563
2564 if (offset == -1)
2565 return 0;
2566
2567 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2568}
2569
2570/**
2571 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2572 * timer and GPE0 I/O ports.
2573 *
2574 * @returns VBox status code.
2575 * @param pDevIns The device instance.
2576 * @param pThis The ACPI shared instance data.
2577 */
2578static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2579{
2580 if (pThis->uPmIoPortBase == 0)
2581 return VINF_SUCCESS;
2582
2583 int rc;
2584 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2585 AssertRCReturn(rc, rc);
2586 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2587 AssertRCReturn(rc, rc);
2588 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2589 AssertRCReturn(rc, rc);
2590 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2591 AssertRCReturn(rc, rc);
2592 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2593 AssertRCReturn(rc, rc);
2594 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2595
2596 return VINF_SUCCESS;
2597}
2598
2599/**
2600 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2601 * timer and GPE0 I/O ports.
2602 *
2603 * @returns VBox status code.
2604 * @param pDevIns The device instance.
2605 * @param pThis The ACPI shared instance data.
2606 */
2607static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2608{
2609 if (pThis->uPmIoPortBase != 0)
2610 {
2611 int rc;
2612 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2613 AssertRCReturn(rc, rc);
2614 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2615 AssertRCReturn(rc, rc);
2616 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2617 AssertRCReturn(rc, rc);
2618 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2619 AssertRCReturn(rc, rc);
2620 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2621 AssertRCReturn(rc, rc);
2622 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2623 AssertRCReturn(rc, rc);
2624 }
2625 return VINF_SUCCESS;
2626}
2627
2628/**
2629 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2630 * PM1a, PM timer and GPE0 ports.
2631 *
2632 * @returns VBox status code.
2633 *
2634 * @param pDevIns The device instance.
2635 * @param pThis The ACPI shared instance data.
2636 * @param pThisCC The ACPI instance data for ring-3.
2637 * @param NewIoPortBase The new base address of the I/O ports.
2638 */
2639static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2640{
2641 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2642 if (NewIoPortBase != pThis->uPmIoPortBase)
2643 {
2644 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2645 if (RT_FAILURE(rc))
2646 return rc;
2647
2648 pThis->uPmIoPortBase = NewIoPortBase;
2649
2650 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2651 if (RT_FAILURE(rc))
2652 return rc;
2653
2654 /* We have to update FADT table acccording to the new base */
2655 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2656 AssertRC(rc);
2657 if (RT_FAILURE(rc))
2658 return rc;
2659 }
2660
2661 return VINF_SUCCESS;
2662}
2663
2664/**
2665 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2666 */
2667static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2668{
2669 RT_NOREF(pvUser);
2670 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2671
2672 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2673 uint8_t off = offPort & 0x000f;
2674 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2675 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2676 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2677
2678 DEVACPI_LOCK_R3(pDevIns, pThis);
2679 switch (off)
2680 {
2681 case SMBHSTSTS_OFF:
2682 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2683 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2684 break;
2685 case SMBSLVSTS_OFF:
2686 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2687 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2688 break;
2689 case SMBHSTCNT_OFF:
2690 {
2691 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2692
2693 const bool old_level = acpiSCILevel(pDevIns, pThis);
2694 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2695 if (u32 & SMBHSTCNT_START)
2696 {
2697 /* Start, trigger error as this is a dummy implementation */
2698 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2699 }
2700 if (u32 & SMBHSTCNT_KILL)
2701 {
2702 /* Kill */
2703 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2704 }
2705 const bool new_level = acpiSCILevel(pDevIns, pThis);
2706
2707 LogFunc(("old=%x new=%x\n", old_level, new_level));
2708
2709 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2710 * needs to be implemented later if it ever becomes relevant. */
2711 if (new_level != old_level)
2712 acpiSetIrq(pDevIns, new_level);
2713 break;
2714 }
2715 case SMBHSTCMD_OFF:
2716 pThis->u8SMBusHstCmd = u32;
2717 break;
2718 case SMBHSTADD_OFF:
2719 pThis->u8SMBusHstAdd = u32;
2720 break;
2721 case SMBHSTDAT0_OFF:
2722 pThis->u8SMBusHstDat0 = u32;
2723 break;
2724 case SMBHSTDAT1_OFF:
2725 pThis->u8SMBusHstDat1 = u32;
2726 break;
2727 case SMBBLKDAT_OFF:
2728 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2729 pThis->u8SMBusBlkIdx++;
2730 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2731 break;
2732 case SMBSLVCNT_OFF:
2733 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2734 break;
2735 case SMBSHDWCMD_OFF:
2736 /* readonly register */
2737 break;
2738 case SMBSLVEVT_OFF:
2739 pThis->u16SMBusSlvEvt = u32;
2740 break;
2741 case SMBSLVDAT_OFF:
2742 /* readonly register */
2743 break;
2744 default:
2745 /* caught by the sanity check above */
2746 ;
2747 }
2748
2749 DEVACPI_UNLOCK(pDevIns, pThis);
2750 return VINF_SUCCESS;
2751}
2752
2753/**
2754 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2755 */
2756static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2757{
2758 RT_NOREF(pvUser);
2759 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2760
2761 VBOXSTRICTRC rc = VINF_SUCCESS;
2762 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2763 uint8_t const off = offPort & 0x000f;
2764 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2765 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2766 return VERR_IOM_IOPORT_UNUSED;
2767
2768 DEVACPI_LOCK_R3(pDevIns, pThis);
2769 switch (off)
2770 {
2771 case SMBHSTSTS_OFF:
2772 *pu32 = pThis->u8SMBusHstSts;
2773 break;
2774 case SMBSLVSTS_OFF:
2775 *pu32 = pThis->u8SMBusSlvSts;
2776 break;
2777 case SMBHSTCNT_OFF:
2778 pThis->u8SMBusBlkIdx = 0;
2779 *pu32 = pThis->u8SMBusHstCnt;
2780 break;
2781 case SMBHSTCMD_OFF:
2782 *pu32 = pThis->u8SMBusHstCmd;
2783 break;
2784 case SMBHSTADD_OFF:
2785 *pu32 = pThis->u8SMBusHstAdd;
2786 break;
2787 case SMBHSTDAT0_OFF:
2788 *pu32 = pThis->u8SMBusHstDat0;
2789 break;
2790 case SMBHSTDAT1_OFF:
2791 *pu32 = pThis->u8SMBusHstDat1;
2792 break;
2793 case SMBBLKDAT_OFF:
2794 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2795 pThis->u8SMBusBlkIdx++;
2796 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2797 break;
2798 case SMBSLVCNT_OFF:
2799 *pu32 = pThis->u8SMBusSlvCnt;
2800 break;
2801 case SMBSHDWCMD_OFF:
2802 *pu32 = pThis->u8SMBusShdwCmd;
2803 break;
2804 case SMBSLVEVT_OFF:
2805 *pu32 = pThis->u16SMBusSlvEvt;
2806 break;
2807 case SMBSLVDAT_OFF:
2808 *pu32 = pThis->u16SMBusSlvDat;
2809 break;
2810 default:
2811 /* caught by the sanity check above */
2812 rc = VERR_IOM_IOPORT_UNUSED;
2813 }
2814 DEVACPI_UNLOCK(pDevIns, pThis);
2815
2816 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2817 return rc;
2818}
2819
2820/**
2821 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2822 *
2823 * @param pDevIns The PDM device instance.
2824 * @param pThis The ACPI shared instance data.
2825 */
2826static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2827{
2828 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2829 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2830 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2831 pPciDev->abConfig[SMBBA+2] = 0x00;
2832 pPciDev->abConfig[SMBBA+3] = 0x00;
2833 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2834 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2835 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2836 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2837 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2838}
2839
2840/**
2841 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2842 *
2843 * @param pThis The ACPI shared instance data.
2844 */
2845static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2846{
2847 pThis->u8SMBusHstSts = 0x00;
2848 pThis->u8SMBusSlvSts = 0x00;
2849 pThis->u8SMBusHstCnt = 0x00;
2850 pThis->u8SMBusHstCmd = 0x00;
2851 pThis->u8SMBusHstAdd = 0x00;
2852 pThis->u8SMBusHstDat0 = 0x00;
2853 pThis->u8SMBusHstDat1 = 0x00;
2854 pThis->u8SMBusSlvCnt = 0x00;
2855 pThis->u8SMBusShdwCmd = 0x00;
2856 pThis->u16SMBusSlvEvt = 0x0000;
2857 pThis->u16SMBusSlvDat = 0x0000;
2858 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2859 pThis->u8SMBusBlkIdx = 0;
2860}
2861
2862/**
2863 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2864 *
2865 * @returns VBox status code.
2866 * @param pDevIns The device instance.
2867 * @param pThis The ACPI shared instance data.
2868 */
2869static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2870{
2871 if (pThis->uSMBusIoPortBase != 0)
2872 {
2873 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2874 AssertRCReturn(rc, rc);
2875 }
2876 return VINF_SUCCESS;
2877}
2878
2879/**
2880 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2881 *
2882 * @returns VBox status code.
2883 * @param pDevIns The device instance.
2884 * @param pThis The ACPI shared instance data.
2885 */
2886static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2887{
2888 if (pThis->uSMBusIoPortBase != 0)
2889 {
2890 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2891 AssertRCReturn(rc, rc);
2892 }
2893 return VINF_SUCCESS;
2894}
2895
2896/**
2897 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2898 * SMBus ports.
2899 *
2900 * @returns VBox status code.
2901 *
2902 * @param pDevIns The device instance.
2903 * @param pThis The ACPI shared instance data.
2904 * @param NewIoPortBase The new base address of the I/O ports.
2905 */
2906static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2907{
2908 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2909 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2910 {
2911 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2912 AssertRCReturn(rc, rc);
2913
2914 pThis->uSMBusIoPortBase = NewIoPortBase;
2915
2916 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2917 AssertRCReturn(rc, rc);
2918
2919#if 0 /* is there an FADT table entry for the SMBus base? */
2920 /* We have to update FADT table acccording to the new base */
2921 rc = acpiR3PlantTables(pThis);
2922 AssertRC(rc);
2923 if (RT_FAILURE(rc))
2924 return rc;
2925#endif
2926 }
2927
2928 return VINF_SUCCESS;
2929}
2930
2931
2932/**
2933 * Saved state structure description, version 4.
2934 */
2935static const SSMFIELD g_AcpiSavedStateFields4[] =
2936{
2937 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2938 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2939 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2940 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2941 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2942 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2943 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2944 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2945 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2946 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2947 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2948 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2949 SSMFIELD_ENTRY_TERM()
2950};
2951
2952/**
2953 * Saved state structure description, version 5.
2954 */
2955static const SSMFIELD g_AcpiSavedStateFields5[] =
2956{
2957 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2958 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2959 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2960 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2961 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2962 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2963 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2964 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2965 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2966 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2967 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2968 SSMFIELD_ENTRY_TERM()
2969};
2970
2971/**
2972 * Saved state structure description, version 6.
2973 */
2974static const SSMFIELD g_AcpiSavedStateFields6[] =
2975{
2976 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2977 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2978 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2979 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2980 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2981 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2982 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2983 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2984 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2985 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2986 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2987 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2988 SSMFIELD_ENTRY_TERM()
2989};
2990
2991/**
2992 * Saved state structure description, version 7.
2993 */
2994static const SSMFIELD g_AcpiSavedStateFields7[] =
2995{
2996 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2997 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2998 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2999 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
3000 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
3001 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
3002 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
3003 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
3004 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
3005 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
3006 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
3007 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
3008 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
3009 SSMFIELD_ENTRY_TERM()
3010};
3011
3012/**
3013 * Saved state structure description, version 8.
3014 */
3015static const SSMFIELD g_AcpiSavedStateFields8[] =
3016{
3017 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
3018 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
3019 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
3020 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
3021 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
3022 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
3023 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
3024 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
3025 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
3026 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
3027 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
3028 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
3029 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
3030 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
3031 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
3032 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
3033 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
3034 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
3035 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
3036 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
3037 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
3038 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
3039 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
3040 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
3041 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
3042 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
3043 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
3044 SSMFIELD_ENTRY_TERM()
3045};
3046
3047/**
3048 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3049 */
3050static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3051{
3052 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3053 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3054 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
3055}
3056
3057/**
3058 * @callback_method_impl{FNSSMDEVLOADEXEC}
3059 */
3060static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3061{
3062 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3063 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3064 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3065 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3066
3067 /*
3068 * Unmap PM I/O ports, will remap it with the actual base after state
3069 * successfully loaded.
3070 */
3071 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
3072 AssertRCReturn(rc, rc);
3073
3074 /*
3075 * Unregister SMBus handlers, will register with actual base after state
3076 * successfully loaded.
3077 */
3078 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
3079 AssertRCReturn(rc, rc);
3080 acpiR3SMBusResetDevice(pThis);
3081
3082 switch (uVersion)
3083 {
3084 case 4:
3085 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
3086 break;
3087 case 5:
3088 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
3089 break;
3090 case 6:
3091 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
3092 break;
3093 case 7:
3094 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
3095 break;
3096 case 8:
3097 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
3098 break;
3099 default:
3100 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3101 break;
3102 }
3103 if (RT_SUCCESS(rc))
3104 {
3105 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
3106 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
3107 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
3108 AssertRCReturn(rc, rc);
3109 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
3110 AssertRCReturn(rc, rc);
3111 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
3112 AssertRCReturn(rc, rc);
3113 rc = acpiR3FetchBatteryInfo(pThis);
3114 AssertRCReturn(rc, rc);
3115
3116 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3117 DEVACPI_LOCK_R3(pDevIns, pThis);
3118 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3119 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
3120 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
3121 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
3122 DEVACPI_UNLOCK(pDevIns, pThis);
3123 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
3124 }
3125 return rc;
3126}
3127
3128/**
3129 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
3130 */
3131static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
3132{
3133 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
3134 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
3135 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
3136 return NULL;
3137}
3138
3139/**
3140 * Calculate the check sum for some ACPI data before planting it.
3141 *
3142 * All the bytes must add up to 0.
3143 *
3144 * @returns check sum.
3145 * @param pvSrc What to check sum.
3146 * @param cbData The amount of data to checksum.
3147 */
3148static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
3149{
3150 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
3151 uint8_t uSum = 0;
3152 for (size_t i = 0; i < cbData; ++i)
3153 uSum += pbSrc[i];
3154 return -uSum;
3155}
3156
3157/**
3158 * Prepare a ACPI table header.
3159 */
3160static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
3161 const char au8Signature[4],
3162 uint32_t u32Length, uint8_t u8Revision)
3163{
3164 memcpy(header->au8Signature, au8Signature, 4);
3165 header->u32Length = RT_H2LE_U32(u32Length);
3166 header->u8Revision = u8Revision;
3167 memcpy(header->au8OemId, pThis->au8OemId, 6);
3168 memcpy(header->au8OemTabId, "VBOX", 4);
3169 memcpy(header->au8OemTabId+4, au8Signature, 4);
3170 header->u32OemRevision = RT_H2LE_U32(1);
3171 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
3172 header->u32CreatorRev = pThis->u32CreatorRev;
3173}
3174
3175/**
3176 * Initialize a generic address structure (ACPIGENADDR).
3177 */
3178static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
3179 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
3180 uint8_t u8AccessSize, uint64_t u64Address)
3181{
3182 g->u8AddressSpaceId = u8AddressSpaceId;
3183 g->u8RegisterBitWidth = u8RegisterBitWidth;
3184 g->u8RegisterBitOffset = u8RegisterBitOffset;
3185 g->u8AccessSize = u8AccessSize;
3186 g->u64Address = RT_H2LE_U64(u64Address);
3187}
3188
3189/**
3190 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
3191 */
3192DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
3193{
3194 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
3195}
3196
3197/**
3198 * Plant the Differentiated System Description Table (DSDT).
3199 */
3200static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
3201{
3202 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
3203}
3204
3205/**
3206 * Plant the Secondary System Description Table (SSDT).
3207 */
3208static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
3209{
3210 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
3211}
3212
3213/**
3214 * Plant the Firmware ACPI Control Structure (FACS).
3215 */
3216static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
3217{
3218 ACPITBLFACS facs;
3219
3220 memset(&facs, 0, sizeof(facs));
3221 memcpy(facs.au8Signature, "FACS", 4);
3222 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
3223 facs.u32HWSignature = RT_H2LE_U32(0);
3224 facs.u32FWVector = RT_H2LE_U32(0);
3225 facs.u32GlobalLock = RT_H2LE_U32(0);
3226 facs.u32Flags = RT_H2LE_U32(0);
3227 facs.u64X_FWVector = RT_H2LE_U64(0);
3228 facs.u8Version = 1;
3229
3230 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
3231}
3232
3233/**
3234 * Plant the Fixed ACPI Description Table (FADT aka FACP).
3235 */
3236static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
3237 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
3238{
3239 ACPITBLFADT fadt;
3240
3241 /* First the ACPI version 2+ version of the structure. */
3242 memset(&fadt, 0, sizeof(fadt));
3243 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
3244 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
3245 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
3246 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
3247 fadt.u8PreferredPMProfile = 0; /* unspecified */
3248 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
3249 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
3250 fadt.u8AcpiEnable = ACPI_ENABLE;
3251 fadt.u8AcpiDisable = ACPI_DISABLE;
3252 fadt.u8S4BIOSReq = 0;
3253 fadt.u8PStateCnt = 0;
3254 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
3255 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
3256 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
3257 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
3258 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
3259 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
3260 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
3261 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
3262 fadt.u8PM1EVTLEN = 4;
3263 fadt.u8PM1CTLLEN = 2;
3264 fadt.u8PM2CTLLEN = 0;
3265 fadt.u8PMTMLEN = 4;
3266 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
3267 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
3268 fadt.u8GPE1BASE = GPE1_BASE;
3269 fadt.u8CSTCNT = 0;
3270 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
3271 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
3272 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
3273 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
3274 fadt.u8DutyOffset = 0;
3275 fadt.u8DutyWidth = 0;
3276 fadt.u8DayAlarm = 0;
3277 fadt.u8MonAlarm = 0;
3278 fadt.u8Century = 0;
3279 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
3280 /** @note WBINVD is required for ACPI versions newer than 1.0 */
3281 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
3282 | FADT_FL_FIX_RTC
3283 | FADT_FL_TMR_VAL_EXT
3284 | FADT_FL_RESET_REG_SUP);
3285
3286 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
3287 if (pThis->fCpuHotPlug)
3288 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
3289
3290 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
3291 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
3292 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
3293 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
3294 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
3295 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
3296 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
3297 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
3298 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
3299 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
3300 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
3301 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
3302 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
3303 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
3304
3305 /* Now the ACPI 1.0 version. */
3306 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
3307 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
3308 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
3309 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
3310 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
3311}
3312
3313/**
3314 * Plant the root System Description Table.
3315 *
3316 * The RSDT and XSDT tables are basically identical. The only difference is 32
3317 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
3318 * ACPI 2.0 and up.
3319 */
3320static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3321{
3322 ACPITBLRSDT *rsdt;
3323 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
3324
3325 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
3326 if (!rsdt)
3327 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
3328
3329 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
3330 for (unsigned int i = 0; i < nb_entries; ++i)
3331 {
3332 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
3333 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
3334 }
3335 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
3336 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
3337 RTMemFree(rsdt);
3338 return VINF_SUCCESS;
3339}
3340
3341/**
3342 * Plant the Extended System Description Table.
3343 */
3344static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3345{
3346 ACPITBLXSDT *xsdt;
3347 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
3348 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
3349 if (!xsdt)
3350 return VERR_NO_TMP_MEMORY;
3351
3352 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
3353
3354 if (pThis->cCustTbls > 0)
3355 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
3356
3357 for (unsigned int i = 0; i < nb_entries; ++i)
3358 {
3359 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
3360 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
3361 }
3362 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
3363 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
3364
3365 RTMemFree(xsdt);
3366 return VINF_SUCCESS;
3367}
3368
3369/**
3370 * Plant the Root System Description Pointer (RSDP).
3371 */
3372static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
3373{
3374 memset(rsdp, 0, sizeof(*rsdp));
3375
3376 /* ACPI 1.0 part (RSDT) */
3377 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
3378 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
3379 rsdp->u8Revision = ACPI_REVISION;
3380 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
3381 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
3382
3383 /* ACPI 2.0 part (XSDT) */
3384 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
3385 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
3386 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
3387}
3388
3389/**
3390 * Multiple APIC Description Table.
3391 *
3392 * This structure looks somewhat convoluted due layout of MADT table in MP case.
3393 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
3394 * use regular C structure and proxy to raw memory instead.
3395 */
3396class AcpiTableMadt
3397{
3398 /**
3399 * All actual data stored in dynamically allocated memory pointed by this field.
3400 */
3401 uint8_t *m_pbData;
3402 /**
3403 * Number of CPU entries in this MADT.
3404 */
3405 uint32_t m_cCpus;
3406
3407 /**
3408 * Number of interrupt overrides.
3409 */
3410 uint32_t m_cIsos;
3411
3412public:
3413 /**
3414 * Address of ACPI header
3415 */
3416 inline ACPITBLHEADER *header_addr(void) const
3417 {
3418 return (ACPITBLHEADER *)m_pbData;
3419 }
3420
3421 /**
3422 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
3423 * although address is the same for all of them.
3424 */
3425 inline uint32_t *u32LAPIC_addr(void) const
3426 {
3427 return (uint32_t *)(header_addr() + 1);
3428 }
3429
3430 /**
3431 * Address of APIC flags
3432 */
3433 inline uint32_t *u32Flags_addr(void) const
3434 {
3435 return (uint32_t *)(u32LAPIC_addr() + 1);
3436 }
3437
3438 /**
3439 * Address of ISO description
3440 */
3441 inline ACPITBLISO *ISO_addr(void) const
3442 {
3443 return (ACPITBLISO *)(u32Flags_addr() + 1);
3444 }
3445
3446 /**
3447 * Address of per-CPU LAPIC descriptions
3448 */
3449 inline ACPITBLLAPIC *LApics_addr(void) const
3450 {
3451 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3452 }
3453
3454 /**
3455 * Address of IO APIC description
3456 */
3457 inline ACPITBLIOAPIC *IOApic_addr(void) const
3458 {
3459 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3460 }
3461
3462 /**
3463 * Size of MADT.
3464 * Note that this function assumes IOApic to be the last field in structure.
3465 */
3466 inline uint32_t size(void) const
3467 {
3468 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3469 }
3470
3471 /**
3472 * Raw data of MADT.
3473 */
3474 inline const uint8_t *data(void) const
3475 {
3476 return m_pbData;
3477 }
3478
3479 /**
3480 * Size of MADT for given ACPI config, useful to compute layout.
3481 */
3482 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3483 {
3484 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3485 }
3486
3487 /*
3488 * Constructor, only works in Ring 3, doesn't look like a big deal.
3489 */
3490 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3491 {
3492 m_cCpus = cCpus;
3493 m_cIsos = cIsos;
3494 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3495 uint32_t cb = size();
3496 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3497 }
3498
3499 ~AcpiTableMadt()
3500 {
3501 RTMemFree(m_pbData);
3502 }
3503};
3504
3505
3506/**
3507 * Plant the Multiple APIC Description Table (MADT).
3508 *
3509 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3510 *
3511 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3512 */
3513static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3514{
3515 uint16_t cpus = pThis->cCpus;
3516 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3517
3518 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3519
3520 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3521 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3522
3523 /* LAPICs records */
3524 ACPITBLLAPIC* lapic = madt.LApics_addr();
3525 for (uint16_t i = 0; i < cpus; i++)
3526 {
3527 lapic->u8Type = 0;
3528 lapic->u8Length = sizeof(ACPITBLLAPIC);
3529 lapic->u8ProcId = i;
3530 /** Must match numbering convention in MPTABLES */
3531 lapic->u8ApicId = i;
3532 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3533 lapic++;
3534 }
3535
3536 /* IO-APIC record */
3537 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3538 ioapic->u8Type = 1;
3539 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3540 /** Must match MP tables ID */
3541 ioapic->u8IOApicId = cpus;
3542 ioapic->u8Reserved = 0;
3543 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3544 ioapic->u32GSIB = RT_H2LE_U32(0);
3545
3546 /* Interrupt Source Overrides */
3547 /* Flags:
3548 bits[3:2]:
3549 00 conforms to the bus
3550 01 edge-triggered
3551 10 reserved
3552 11 level-triggered
3553 bits[1:0]
3554 00 conforms to the bus
3555 01 active-high
3556 10 reserved
3557 11 active-low */
3558 /* If changing, also update PDMIsaSetIrq() and MPS */
3559 ACPITBLISO* isos = madt.ISO_addr();
3560 /* Timer interrupt rule IRQ0 to GSI2 */
3561 isos[0].u8Type = 2;
3562 isos[0].u8Length = sizeof(ACPITBLISO);
3563 isos[0].u8Bus = 0; /* Must be 0 */
3564 isos[0].u8Source = 0; /* IRQ0 */
3565 isos[0].u32GSI = 2; /* connected to pin 2 */
3566 isos[0].u16Flags = 0; /* conform to the bus */
3567
3568 /* ACPI interrupt rule - IRQ9 to GSI9 */
3569 isos[1].u8Type = 2;
3570 isos[1].u8Length = sizeof(ACPITBLISO);
3571 isos[1].u8Bus = 0; /* Must be 0 */
3572 isos[1].u8Source = 9; /* IRQ9 */
3573 isos[1].u32GSI = 9; /* connected to pin 9 */
3574 isos[1].u16Flags = 0xf; /* active low, level triggered */
3575 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3576
3577 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3578 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3579}
3580
3581/**
3582 * Plant the High Performance Event Timer (HPET) descriptor.
3583 */
3584static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3585{
3586 ACPITBLHPET hpet;
3587
3588 memset(&hpet, 0, sizeof(hpet));
3589
3590 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3591 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3592 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3593 0 /* Memory address space */,
3594 64 /* Register bit width */,
3595 0 /* Bit offset */,
3596 0, /* Register access size, is it correct? */
3597 0xfed00000 /* Address */);
3598
3599 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3600 hpet.u32Number = 0;
3601 hpet.u32MinTick = 4096;
3602 hpet.u8Attributes = 0;
3603
3604 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3605
3606 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3607}
3608
3609
3610#ifdef VBOX_WITH_IOMMU_AMD
3611/**
3612 * Plant the AMD IOMMU descriptor.
3613 */
3614static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3615{
3616 ACPITBLIOMMU Ivrs;
3617 RT_ZERO(Ivrs);
3618
3619 uint16_t const uIommuBus = 0;
3620 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuAmdPciAddress);
3621 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuAmdPciAddress);
3622
3623 /* IVRS header. */
3624 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3625 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3626 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3627 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 0)
3628 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3629 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3630 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64); /* Virt. Addr size (64 bits) */
3631
3632 /* IVHD type 10 definition block. */
3633 Ivrs.IvhdType10.u8Type = 0x10;
3634 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3635 + sizeof(Ivrs.IvhdType10Start)
3636 + sizeof(Ivrs.IvhdType10End)
3637 + sizeof(Ivrs.IvhdType10Rsvd0)
3638 + sizeof(Ivrs.IvhdType10Rsvd1)
3639 + sizeof(Ivrs.IvhdType10IoApic)
3640 + sizeof(Ivrs.IvhdType10Hpet);
3641 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3642 Ivrs.IvhdType10.u16CapOffset = 0; /* 0=No multiple IOMMU functionality. */
3643 Ivrs.IvhdType10.u64BaseAddress = 0xfeb80000; /* MMIO base address: Taken from real hardware ACPI dumps. */
3644 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3645 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3646 Ivrs.IvhdType10.u8Flags = 0; /* Remote IOTLB, Prefetch IOMMU pages features etc. - currently none supported. */
3647 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3648 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3649 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3650 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3651 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3652 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3653 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3654 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3655 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3656 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3657 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3658 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3659 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3660 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3661 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3662 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, 6 & 3); /* IOMMU_MAX_HOST_PT_LEVEL & 3*/
3663 /* Start range from BDF (00:01:00). */
3664 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3665 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3666 Ivrs.IvhdType10Start.u8DteSetting = 0;
3667 /* End range at BDF (ff:1f:7). */
3668 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3669 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3670 Ivrs.IvhdType10End.u8DteSetting = 0;
3671
3672 /* Southbridge I/O APIC special device entry. */
3673 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3674 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3675 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3676 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3677 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3678 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3679 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3680 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3681 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3682 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3683
3684 /* HPET special device entry. */
3685 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3686 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3687 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3688 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3689 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3690 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3691
3692 /* IVHD type 11 definition block. */
3693 Ivrs.IvhdType11.u8Type = 0x11;
3694 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3695 + sizeof(Ivrs.IvhdType11Start)
3696 + sizeof(Ivrs.IvhdType11End)
3697 + sizeof(Ivrs.IvhdType11Rsvd0)
3698 + sizeof(Ivrs.IvhdType11Rsvd1)
3699 + sizeof(Ivrs.IvhdType11IoApic)
3700 + sizeof(Ivrs.IvhdType11Hpet);
3701 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3702 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3703 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3704 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3705 Ivrs.IvhdType11.u8Flags = Ivrs.IvhdType10.u8Flags;
3706 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3707 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3708 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3709 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3710 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3711 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3712 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3713 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3714 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3715 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3716 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 0)
3717 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3718 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3719 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3720 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, 6 /* IOMMU_MAX_HOST_PT_LEVEL */ & 3)
3721 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3722 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3723 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3724 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3725 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3726 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3727 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3728 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3729 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3730 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, 3 /* IOMMU_MAX_DEV_TAB_SEGMENTS */)
3731 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3732 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3733 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3734 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3735 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3736 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3737 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3738 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3739 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3740 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3741 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3742 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3743 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3744 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3745
3746 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3747 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3748 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3749 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3750 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3751 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3752 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3753
3754 /* Finally, Compute checksum. */
3755 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3756
3757 /* Plant the ACPI table. */
3758 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3759}
3760#endif
3761
3762
3763/**
3764 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3765 * descriptor.
3766 *
3767 * @param pDevIns The device instance.
3768 * @param pThis The ACPI shared instance data.
3769 * @param GCPhysDst Where to plant it.
3770 */
3771static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3772{
3773 struct
3774 {
3775 ACPITBLMCFG hdr;
3776 ACPITBLMCFGENTRY entry;
3777 } tbl;
3778 uint8_t u8StartBus = 0;
3779 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3780
3781 RT_ZERO(tbl);
3782
3783 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3784 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3785 tbl.entry.u8StartBus = u8StartBus;
3786 tbl.entry.u8EndBus = u8EndBus;
3787 // u16PciSegmentGroup must match _SEG in ACPI table
3788
3789 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3790
3791 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3792}
3793
3794/**
3795 * Used by acpiR3PlantTables and acpiConstruct.
3796 *
3797 * @returns Guest memory address.
3798 */
3799static uint32_t apicR3FindRsdpSpace(void)
3800{
3801 return 0xe0000;
3802}
3803
3804/**
3805 * Called by acpiR3Construct to read and allocate a custom ACPI table
3806 *
3807 * @param pDevIns The device instance.
3808 * @param ppu8CustBin Address to receive the address of the table
3809 * @param pcbCustBin Address to receive the size of the the table.
3810 * @param pszCustBinFile
3811 * @param cbBufAvail Maximum space in bytes available for the custom
3812 * table (including header).
3813 */
3814static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3815 char *pszCustBinFile, uint32_t cbBufAvail)
3816{
3817 RTFILE FileCUSTBin;
3818 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3819 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3820 if (RT_SUCCESS(rc))
3821 {
3822 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3823 if (RT_SUCCESS(rc))
3824 {
3825 /* The following checks should be in sync the AssertReleaseMsg's below. */
3826 if ( *pcbCustBin > cbBufAvail
3827 || *pcbCustBin < sizeof(ACPITBLHEADER))
3828 rc = VERR_TOO_MUCH_DATA;
3829
3830 /*
3831 * Allocate buffer for the custom table binary data.
3832 */
3833 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3834 if (*ppu8CustBin)
3835 {
3836 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3837 if (RT_FAILURE(rc))
3838 {
3839 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3840 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3841 *ppu8CustBin = NULL;
3842 }
3843 }
3844 else
3845 {
3846 rc = VERR_NO_MEMORY;
3847 }
3848 RTFileClose(FileCUSTBin);
3849 }
3850 }
3851 return rc;
3852}
3853
3854/**
3855 * Create the ACPI tables in guest memory.
3856 */
3857static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3858{
3859 int rc;
3860 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3861 RTGCPHYS32 GCPhysHpet = 0;
3862#ifdef VBOX_WITH_IOMMU_AMD
3863 RTGCPHYS32 GCPhysIommuAmd = 0;
3864#endif
3865 RTGCPHYS32 GCPhysApic = 0;
3866 RTGCPHYS32 GCPhysSsdt = 0;
3867 RTGCPHYS32 GCPhysMcfg = 0;
3868 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3869 uint32_t addend = 0;
3870#ifdef VBOX_WITH_IOMMU_AMD
3871 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3872 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3873#else
3874 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3875 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3876#endif
3877 uint32_t cAddr;
3878 uint32_t iMadt = 0;
3879 uint32_t iHpet = 0;
3880#ifdef VBOX_WITH_IOMMU_AMD
3881 uint32_t iIommuAmd = 0;
3882#endif
3883 uint32_t iSsdt = 0;
3884 uint32_t iMcfg = 0;
3885 uint32_t iCust = 0;
3886 size_t cbRsdt = sizeof(ACPITBLHEADER);
3887 size_t cbXsdt = sizeof(ACPITBLHEADER);
3888
3889 cAddr = 1; /* FADT */
3890 if (pThis->u8UseIOApic)
3891 iMadt = cAddr++; /* MADT */
3892
3893 if (pThis->fUseHpet)
3894 iHpet = cAddr++; /* HPET */
3895
3896#ifdef VBOX_WITH_IOMMU_AMD
3897 if (pThis->u32IommuAmdPciAddress)
3898 iIommuAmd = cAddr++; /* IOMMU (AMD) */
3899#endif
3900
3901 if (pThis->fUseMcfg)
3902 iMcfg = cAddr++; /* MCFG */
3903
3904 if (pThis->cCustTbls > 0)
3905 {
3906 iCust = cAddr; /* CUST */
3907 cAddr += pThis->cCustTbls;
3908 }
3909
3910 iSsdt = cAddr++; /* SSDT */
3911
3912 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3913 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3914
3915 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3916 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3917
3918 /*
3919 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3920 * The latter starts never below 4G.
3921 */
3922 PVM pVM = PDMDevHlpGetVM(pDevIns);
3923 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3924 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3925
3926 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3927 if (pThis->fPciPref64Enabled)
3928 {
3929 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3930 if (pThis->u64PciPref64Max > u64PciPref64Min)
3931 {
3932 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3933 pThis->u64PciPref64Min = u64PciPref64Min;
3934 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3935 u64PciPref64Min, pThis->u64PciPref64Max-1));
3936 }
3937 else
3938 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3939 u64PciPref64Min, pThis->u64PciPref64Max-1));
3940 }
3941 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3942 {
3943 /* Note: This is also enforced by DevPcBios.cpp. */
3944 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3945 cbBelow4GB = UINT32_C(0xfe000000);
3946 }
3947 pThis->cbRamLow = cbBelow4GB;
3948
3949 GCPhysCur = 0;
3950 GCPhysRsdt = GCPhysCur;
3951
3952 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3953 GCPhysXsdt = GCPhysCur;
3954
3955 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3956 GCPhysFadtAcpi1 = GCPhysCur;
3957
3958 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3959 GCPhysFadtAcpi2 = GCPhysCur;
3960
3961 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3962 GCPhysFacs = GCPhysCur;
3963
3964 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3965 if (pThis->u8UseIOApic)
3966 {
3967 GCPhysApic = GCPhysCur;
3968 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3969 }
3970 if (pThis->fUseHpet)
3971 {
3972 GCPhysHpet = GCPhysCur;
3973 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3974 }
3975#ifdef VBOX_WITH_IOMMU_AMD
3976 if (pThis->u32IommuAmdPciAddress)
3977 {
3978 GCPhysIommuAmd = GCPhysCur;
3979 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3980 }
3981#endif
3982 if (pThis->fUseMcfg)
3983 {
3984 GCPhysMcfg = GCPhysCur;
3985 /* Assume one entry */
3986 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3987 }
3988
3989 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3990 {
3991 aGCPhysCust[i] = GCPhysCur;
3992 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3993 }
3994
3995 void *pvSsdtCode = NULL;
3996 size_t cbSsdt = 0;
3997 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3998 if (RT_FAILURE(rc))
3999 return rc;
4000
4001 GCPhysSsdt = GCPhysCur;
4002 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
4003
4004 GCPhysDsdt = GCPhysCur;
4005
4006 void *pvDsdtCode = NULL;
4007 size_t cbDsdt = 0;
4008 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
4009 if (RT_FAILURE(rc))
4010 return rc;
4011
4012 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
4013
4014 if (GCPhysCur > 0x10000)
4015 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
4016 N_("Error: ACPI tables bigger than 64KB"));
4017
4018 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
4019 addend = pThis->cbRamLow - 0x10000;
4020 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
4021 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
4022 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
4023 if (pThis->u8UseIOApic)
4024 Log((" MADT 0x%08X", GCPhysApic + addend));
4025 if (pThis->fUseHpet)
4026 Log((" HPET 0x%08X", GCPhysHpet + addend));
4027 if (pThis->fUseMcfg)
4028 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
4029 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4030 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
4031 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
4032 Log(("\n"));
4033
4034 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
4035 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
4036 acpiCleanupDsdt(pDevIns, pvDsdtCode);
4037 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
4038 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
4039
4040 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
4041 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
4042 if (pThis->u8UseIOApic)
4043 {
4044 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
4045 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
4046 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
4047 }
4048 if (pThis->fUseHpet)
4049 {
4050 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
4051 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
4052 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
4053 }
4054#ifdef VBOX_WITH_IOMMU_AMD
4055 if (pThis->u32IommuAmdPciAddress)
4056 {
4057 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommuAmd + addend);
4058 aGCPhysRsdt[iIommuAmd] = GCPhysIommuAmd + addend;
4059 aGCPhysXsdt[iIommuAmd] = GCPhysIommuAmd + addend;
4060 }
4061#endif
4062 if (pThis->fUseMcfg)
4063 {
4064 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
4065 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
4066 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
4067 }
4068 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4069 {
4070 Assert(i < MAX_CUST_TABLES);
4071 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
4072 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
4073 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
4074 uint8_t* pSig = pThisCC->apu8CustBin[i];
4075 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
4076 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
4077 }
4078
4079 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
4080 acpiCleanupSsdt(pDevIns, pvSsdtCode);
4081 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
4082 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
4083
4084 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
4085 if (RT_FAILURE(rc))
4086 return rc;
4087 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
4088}
4089
4090/**
4091 * @callback_method_impl{FNPCICONFIGREAD}
4092 */
4093static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
4094 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
4095{
4096 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4097 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
4098 return rcStrict;
4099}
4100
4101/**
4102 * @callback_method_impl{FNPCICONFIGWRITE}
4103 */
4104static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
4105 uint32_t uAddress, unsigned cb, uint32_t u32Value)
4106{
4107 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4108 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4109
4110 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
4111 DEVACPI_LOCK_R3(pDevIns, pThis);
4112
4113 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
4114 {
4115 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
4116 u32Value = SCI_INT;
4117 }
4118
4119 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4120
4121 /* Assume that the base address is only changed when the corresponding
4122 * hardware functionality is disabled. The IO region is mapped when the
4123 * functionality is enabled by the guest. */
4124
4125 if (uAddress == PMREGMISC)
4126 {
4127 RTIOPORT NewIoPortBase = 0;
4128 /* Check Power Management IO Space Enable (PMIOSE) bit */
4129 if (pPciDev->abConfig[PMREGMISC] & 0x01)
4130 {
4131 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
4132 NewIoPortBase &= 0xffc0;
4133 }
4134
4135 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
4136 AssertRC(rc);
4137 }
4138
4139 if (uAddress == SMBHSTCFG)
4140 {
4141 RTIOPORT NewIoPortBase = 0;
4142 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
4143 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
4144 {
4145 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
4146 NewIoPortBase &= 0xfff0;
4147 }
4148
4149 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
4150 AssertRC(rc);
4151 }
4152
4153 DEVACPI_UNLOCK(pDevIns, pThis);
4154 return rcStrict;
4155}
4156
4157/**
4158 * Attach a new CPU.
4159 *
4160 * @returns VBox status code.
4161 * @param pDevIns The device instance.
4162 * @param iLUN The logical unit which is being attached.
4163 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4164 *
4165 * @remarks This code path is not used during construction.
4166 */
4167static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4168{
4169 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4170 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4171 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4172
4173 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4174 ("Hot-plug flag is not set\n"),
4175 VERR_NOT_SUPPORTED);
4176 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
4177
4178 /* Check if it was already attached */
4179 int rc = VINF_SUCCESS;
4180 DEVACPI_LOCK_R3(pDevIns, pThis);
4181 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4182 {
4183 PPDMIBASE IBaseTmp;
4184 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4185 if (RT_SUCCESS(rc))
4186 {
4187 /* Enable the CPU */
4188 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
4189
4190 /*
4191 * Lock the CPU because we don't know if the guest will use it or not.
4192 * Prevents ejection while the CPU is still used
4193 */
4194 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
4195 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
4196 pThis->u32CpuEvent = iLUN;
4197
4198 /* Notify the guest */
4199 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4200 }
4201 }
4202 DEVACPI_UNLOCK(pDevIns, pThis);
4203 return rc;
4204}
4205
4206/**
4207 * Detach notification.
4208 *
4209 * @param pDevIns The device instance.
4210 * @param iLUN The logical unit which is being detached.
4211 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4212 */
4213static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4214{
4215 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4216
4217 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4218
4219 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4220 ("Hot-plug flag is not set\n"));
4221
4222 /* Check if it was already detached */
4223 DEVACPI_LOCK_R3(pDevIns, pThis);
4224 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4225 {
4226 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
4227 {
4228 /* Disable the CPU */
4229 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
4230 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
4231 pThis->u32CpuEvent = iLUN;
4232
4233 /* Notify the guest */
4234 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4235 }
4236 else
4237 AssertMsgFailed(("CPU is still locked by the guest\n"));
4238 }
4239 DEVACPI_UNLOCK(pDevIns, pThis);
4240}
4241
4242/**
4243 * @interface_method_impl{PDMDEVREG,pfnResume}
4244 */
4245static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
4246{
4247 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4248 if (pThis->fSetWakeupOnResume)
4249 {
4250 Log(("acpiResume: setting WAK_STS\n"));
4251 pThis->fSetWakeupOnResume = false;
4252 pThis->pm1a_sts |= WAK_STS;
4253 }
4254}
4255
4256/**
4257 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
4258 */
4259static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
4260{
4261 RT_NOREF(enmCtx);
4262 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4263 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4264 acpiR3PlantTables(pDevIns, pThis, pThisCC);
4265}
4266
4267/**
4268 * @interface_method_impl{PDMDEVREG,pfnReset}
4269 */
4270static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
4271{
4272 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4273 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4274
4275 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
4276 acpiSetIrq(pDevIns, 0);
4277
4278 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4279 pThis->pm1a_en = 0;
4280 pThis->pm1a_sts = 0;
4281 pThis->pm1a_ctl = 0;
4282 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4283 pThis->uPmTimerVal = 0;
4284 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4285 pThis->uPmTimeOld = pThis->uPmTimerVal;
4286 pThis->uBatteryIndex = 0;
4287 pThis->uSystemInfoIndex = 0;
4288 pThis->gpe0_en = 0;
4289 pThis->gpe0_sts = 0;
4290 pThis->uSleepState = 0;
4291 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4292
4293 /* Real device behavior is resetting only the PM controller state,
4294 * but we're additionally doing the job of the BIOS. */
4295 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
4296 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4297
4298 /* Reset SMBus base and PCI config space in addition to the SMBus controller
4299 * state. Real device behavior is only the SMBus controller state reset,
4300 * but we're additionally doing the job of the BIOS. */
4301 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
4302 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4303 acpiR3SMBusResetDevice(pThis);
4304}
4305
4306/**
4307 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4308 */
4309static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
4310{
4311 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4312 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4313 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4314
4315 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4316 {
4317 if (pThisCC->apu8CustBin[i])
4318 {
4319 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
4320 pThisCC->apu8CustBin[i] = NULL;
4321 }
4322 }
4323 return VINF_SUCCESS;
4324}
4325
4326/**
4327 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4328 */
4329static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4330{
4331 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4332 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4333 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4334 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4335
4336 /*
4337 * Init data and set defaults.
4338 */
4339 /** @todo move more of the code up! */
4340
4341 pThisCC->pDevIns = pDevIns;
4342 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
4343 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
4344 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
4345 pThis->u32CpuEventType = 0;
4346 pThis->u32CpuEvent = UINT32_C(0xffffffff);
4347
4348 /* The first CPU can't be attached/detached */
4349 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
4350 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
4351
4352 /* IBase */
4353 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
4354 /* IACPIPort */
4355 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
4356 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
4357 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
4358 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
4359 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
4360 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
4361 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
4362
4363 /*
4364 * Set the default critical section to NOP (related to the PM timer).
4365 */
4366 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4367 AssertRCReturn(rc, rc);
4368
4369 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
4370 AssertRCReturn(rc, rc);
4371
4372 /*
4373 * Validate and read the configuration.
4374 */
4375 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
4376 "IOAPIC"
4377 "|NumCPUs"
4378 "|HpetEnabled"
4379 "|McfgEnabled"
4380 "|McfgBase"
4381 "|McfgLength"
4382 "|PciPref64Enabled"
4383 "|PciPref64LimitGB"
4384 "|SmcEnabled"
4385 "|FdcEnabled"
4386 "|ShowRtc"
4387 "|ShowCpu"
4388 "|NicPciAddress"
4389 "|AudioPciAddress"
4390 "|NvmePciAddress"
4391 "|IocPciAddress"
4392 "|HostBusPciAddress"
4393 "|EnableSuspendToDisk"
4394 "|PowerS1Enabled"
4395 "|PowerS4Enabled"
4396 "|CpuHotPlug"
4397 "|AmlFilePath"
4398 "|Serial0IoPortBase"
4399 "|Serial1IoPortBase"
4400 "|Serial2IoPortBase"
4401 "|Serial3IoPortBase"
4402 "|Serial0Irq"
4403 "|Serial1Irq"
4404 "|Serial2Irq"
4405 "|Serial3Irq"
4406 "|AcpiOemId"
4407 "|AcpiCreatorId"
4408 "|AcpiCreatorRev"
4409 "|CustomTable"
4410 "|CustomTable0"
4411 "|CustomTable1"
4412 "|CustomTable2"
4413 "|CustomTable3"
4414 "|Parallel0IoPortBase"
4415 "|Parallel1IoPortBase"
4416 "|Parallel0Irq"
4417 "|Parallel1Irq"
4418 "|IommuAmdPciAddress"
4419 "|SbIoApicPciAddress"
4420 , "");
4421
4422 /* query whether we are supposed to present an IOAPIC */
4423 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
4424 if (RT_FAILURE(rc))
4425 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
4426
4427 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
4428 if (RT_FAILURE(rc))
4429 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
4430
4431 /* query whether we are supposed to present an FDC controller */
4432 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
4433 if (RT_FAILURE(rc))
4434 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
4435
4436 /* query whether we are supposed to present HPET */
4437 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
4438 if (RT_FAILURE(rc))
4439 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
4440 /* query MCFG configuration */
4441 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
4442 if (RT_FAILURE(rc))
4443 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4444 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4445 if (RT_FAILURE(rc))
4446 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4447 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4448
4449 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4450 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4451 if (RT_FAILURE(rc))
4452 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4453
4454 /* query the limit of the the 64-bit prefetchable memory window */
4455 uint64_t u64PciPref64MaxGB;
4456 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4457 if (RT_FAILURE(rc))
4458 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4459 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4460
4461 /* query whether we are supposed to present SMC */
4462 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4463 if (RT_FAILURE(rc))
4464 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4465
4466 /* query whether we are supposed to present RTC object */
4467 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4468 if (RT_FAILURE(rc))
4469 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4470
4471 /* query whether we are supposed to present CPU objects */
4472 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4473 if (RT_FAILURE(rc))
4474 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4475
4476 /* query primary NIC PCI address (GIGE) */
4477 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4478 if (RT_FAILURE(rc))
4479 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4480
4481 /* query HD Audio PCI address (HDAA) */
4482 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4483 if (RT_FAILURE(rc))
4484 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4485
4486 /* query NVMe PCI address (NVMA) */
4487 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4488 if (RT_FAILURE(rc))
4489 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4490
4491 /* query IO controller (southbridge) PCI address */
4492 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4493 if (RT_FAILURE(rc))
4494 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4495
4496 /* query host bus controller PCI address */
4497 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4498 if (RT_FAILURE(rc))
4499 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4500
4501 /* query whether S1 power state should be exposed */
4502 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4503 if (RT_FAILURE(rc))
4504 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4505
4506 /* query whether S4 power state should be exposed */
4507 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4508 if (RT_FAILURE(rc))
4509 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4510
4511 /* query whether S1 power state should save the VM state */
4512 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4513 if (RT_FAILURE(rc))
4514 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4515
4516 /* query whether we are allow CPU hot plugging */
4517 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4518 if (RT_FAILURE(rc))
4519 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4520
4521 /* query serial info */
4522 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4523 if (RT_FAILURE(rc))
4524 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4525
4526 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4527 if (RT_FAILURE(rc))
4528 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4529
4530 /* Serial 1 is enabled, get config data */
4531 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4532 if (RT_FAILURE(rc))
4533 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4534
4535 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4536 if (RT_FAILURE(rc))
4537 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4538
4539 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4540 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4541 if (RT_FAILURE(rc))
4542 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4543
4544 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4545 if (RT_FAILURE(rc))
4546 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4547
4548 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4549 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4550 if (RT_FAILURE(rc))
4551 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4552
4553 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4554 if (RT_FAILURE(rc))
4555 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4556 /*
4557 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4558 * the corresponding parallel port is not enabled.
4559 */
4560 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4561 if (RT_FAILURE(rc))
4562 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4563
4564 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4565 if (RT_FAILURE(rc))
4566 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4567
4568 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4569 if (RT_FAILURE(rc))
4570 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4571
4572 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4573 if (RT_FAILURE(rc))
4574 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4575
4576#ifdef VBOX_WITH_IOMMU_AMD
4577 /* Query IOMMU AMD address (IOMA). */
4578 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuAmdPciAddress", &pThis->u32IommuAmdPciAddress, 0);
4579 if (RT_FAILURE(rc))
4580 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdAddress\""));
4581
4582 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4583 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress, 0);
4584 if (RT_FAILURE(rc))
4585 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4586
4587 /* Warn if the SB IOAPIC is not at the required address if an AMD IOMMU is configured. */
4588 if ( pThis->u32IommuAmdPciAddress
4589 && pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4590 {
4591 /** @todo Maybe make this a VM startup failure later. */
4592 LogRel(("ACPI: Warning! Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4593 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4594 }
4595#endif
4596
4597 /* Try to attach the other CPUs */
4598 for (unsigned i = 1; i < pThis->cCpus; i++)
4599 {
4600 if (pThis->fCpuHotPlug)
4601 {
4602 PPDMIBASE IBaseTmp;
4603 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4604
4605 if (RT_SUCCESS(rc))
4606 {
4607 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4608 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4609 Log(("acpi: Attached CPU %u\n", i));
4610 }
4611 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4612 Log(("acpi: CPU %u not attached yet\n", i));
4613 else
4614 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4615 }
4616 else
4617 {
4618 /* CPU is always attached if hot-plug is not enabled. */
4619 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4620 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4621 }
4622 }
4623
4624 char szOemId[16];
4625 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4626 if (RT_FAILURE(rc))
4627 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4628 size_t cchOemId = strlen(szOemId);
4629 if (cchOemId > 6)
4630 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4631 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4632 memcpy(pThis->au8OemId, szOemId, cchOemId);
4633
4634 char szCreatorId[16];
4635 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4636 if (RT_FAILURE(rc))
4637 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4638 size_t cchCreatorId = strlen(szCreatorId);
4639 if (cchCreatorId > 4)
4640 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4641 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4642 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4643
4644 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4645 if (RT_FAILURE(rc))
4646 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4647
4648 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4649
4650 /*
4651 * Load custom ACPI tables.
4652 */
4653 /* Total space available for custom ACPI tables */
4654 /** @todo define as appropriate, remove as a magic number, and document
4655 * limitation in product manual */
4656 uint32_t cbBufAvail = 3072;
4657 pThis->cCustTbls = 0;
4658
4659 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4660 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4661 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4662 {
4663 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4664
4665 /*
4666 * Get the custom table binary file name.
4667 */
4668 char *pszCustBinFile = NULL;
4669 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4670 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4671 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4672 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4673 {
4674 rc = VINF_SUCCESS;
4675 pszCustBinFile = NULL;
4676 }
4677 else if (RT_FAILURE(rc))
4678 return PDMDEV_SET_ERROR(pDevIns, rc,
4679 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4680 else if (!*pszCustBinFile)
4681 {
4682 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4683 pszCustBinFile = NULL;
4684 }
4685
4686 /*
4687 * Determine the custom table binary size, open specified file in the process.
4688 */
4689 if (pszCustBinFile)
4690 {
4691 uint32_t idxCust = pThis->cCustTbls;
4692 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4693 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4694 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4695 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4696 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4697 if (RT_FAILURE(rc))
4698 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4699 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4700
4701 /* Update custom OEM attributes based on custom table */
4702 /** @todo is it intended for custom tables to overwrite user provided values above? */
4703 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4704 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4705 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4706 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4707 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4708 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4709
4710 pThis->cCustTbls++;
4711 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
4712 }
4713 }
4714
4715 /* Set default PM port base */
4716 pThis->uPmIoPortBase = PM_PORT_BASE;
4717
4718 /* Set default SMBus port base */
4719 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4720
4721 /*
4722 * FDC and SMC try to use the same non-shareable interrupt (6),
4723 * enable only one device.
4724 */
4725 if (pThis->fUseSmc)
4726 pThis->fUseFdc = false;
4727
4728 /*
4729 * Plant ACPI tables.
4730 */
4731 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4732 * au8RSDPPage here. However, there should be no harm in doing it
4733 * twice, so the lazy bird is taking the quick way out for now. */
4734 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4735 if (!GCPhysRsdp)
4736 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4737
4738 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4739 AssertRCReturn(rc, rc);
4740
4741 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4742 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4743 AssertRCReturn(rc, rc);
4744
4745 /*
4746 * Create the PM I/O ports. These can be unmapped and remapped.
4747 */
4748 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4749 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4750 AssertRCReturn(rc, rc);
4751 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4752 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4753 AssertRCReturn(rc, rc);
4754 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4755 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4756 AssertRCReturn(rc, rc);
4757 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4758 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4759 AssertRCReturn(rc, rc);
4760 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4761 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4762 AssertRCReturn(rc, rc);
4763 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4764 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4765 AssertRCReturn(rc, rc);
4766 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4767 AssertRCReturn(rc, rc);
4768
4769 /*
4770 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4771 */
4772 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4773 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4774 AssertRCReturn(rc, rc);
4775 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4776 AssertRCReturn(rc, rc);
4777
4778 /*
4779 * Create and map the fixed I/O ports.
4780 */
4781 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4782 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4783 AssertRCReturn(rc, rc);
4784#ifdef DEBUG_ACPI
4785 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4786 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4787 AssertRCReturn(rc, rc);
4788 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4789 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4790 AssertRCReturn(rc, rc);
4791#endif
4792 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4793 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4794 AssertRCReturn(rc, rc);
4795 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4796 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4797 AssertRCReturn(rc, rc);
4798 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4799 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4800 AssertRCReturn(rc, rc);
4801 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4802 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4803 AssertRCReturn(rc, rc);
4804 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4805 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4806 AssertRCReturn(rc, rc);
4807
4808 /*
4809 * Create the PM timer.
4810 */
4811 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4812 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer);
4813 AssertRCReturn(rc, rc);
4814
4815 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4816 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4817 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4818 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4819
4820 /*
4821 * Set up the PCI device.
4822 */
4823 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4824 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4825
4826 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4827 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4828
4829 /* See p. 50 of PIIX4 manual */
4830 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4831 PDMPciDevSetStatus(pPciDev, 0x0280);
4832
4833 PDMPciDevSetRevisionId(pPciDev, 0x08);
4834
4835 PDMPciDevSetClassProg(pPciDev, 0x00);
4836 PDMPciDevSetClassSub(pPciDev, 0x80);
4837 PDMPciDevSetClassBase(pPciDev, 0x06);
4838
4839 PDMPciDevSetHeaderType(pPciDev, 0x80);
4840
4841 PDMPciDevSetBIST(pPciDev, 0x00);
4842
4843 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4844 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4845
4846 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4847 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4848
4849 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4850 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4851 acpiR3SMBusResetDevice(pThis);
4852
4853 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4854 AssertRCReturn(rc, rc);
4855
4856 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4857 AssertRCReturn(rc, rc);
4858
4859 /*
4860 * Register the saved state.
4861 */
4862 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4863 AssertRCReturn(rc, rc);
4864
4865 /*
4866 * Get the corresponding connector interface
4867 */
4868 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4869 if (RT_SUCCESS(rc))
4870 {
4871 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4872 if (!pThisCC->pDrv)
4873 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4874 }
4875 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4876 {
4877 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4878 rc = VINF_SUCCESS;
4879 }
4880 else
4881 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4882
4883 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4884
4885 return rc;
4886}
4887
4888#else /* !IN_RING3 */
4889
4890/**
4891 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4892 */
4893static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4894{
4895 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4896 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4897
4898 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4899 AssertRCReturn(rc, rc);
4900
4901 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4902 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4903 AssertRCReturn(rc, rc);
4904
4905 return VINF_SUCCESS;
4906}
4907
4908#endif /* !IN_RING3 */
4909
4910/**
4911 * The device registration structure.
4912 */
4913const PDMDEVREG g_DeviceACPI =
4914{
4915 /* .u32Version = */ PDM_DEVREG_VERSION,
4916 /* .uReserved0 = */ 0,
4917 /* .szName = */ "acpi",
4918 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4919 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4920 /* .cMaxInstances = */ ~0U,
4921 /* .uSharedVersion = */ 42,
4922 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4923 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4924 /* .cbInstanceRC = */ 0,
4925 /* .cMaxPciDevices = */ 1,
4926 /* .cMaxMsixVectors = */ 0,
4927 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4928#if defined(IN_RING3)
4929 /* .pszRCMod = */ "VBoxDDRC.rc",
4930 /* .pszR0Mod = */ "VBoxDDR0.r0",
4931 /* .pfnConstruct = */ acpiR3Construct,
4932 /* .pfnDestruct = */ acpiR3Destruct,
4933 /* .pfnRelocate = */ NULL,
4934 /* .pfnMemSetup = */ acpiR3MemSetup,
4935 /* .pfnPowerOn = */ NULL,
4936 /* .pfnReset = */ acpiR3Reset,
4937 /* .pfnSuspend = */ NULL,
4938 /* .pfnResume = */ acpiR3Resume,
4939 /* .pfnAttach = */ acpiR3Attach,
4940 /* .pfnDetach = */ acpiR3Detach,
4941 /* .pfnQueryInterface = */ NULL,
4942 /* .pfnInitComplete = */ NULL,
4943 /* .pfnPowerOff = */ NULL,
4944 /* .pfnSoftReset = */ NULL,
4945 /* .pfnReserved0 = */ NULL,
4946 /* .pfnReserved1 = */ NULL,
4947 /* .pfnReserved2 = */ NULL,
4948 /* .pfnReserved3 = */ NULL,
4949 /* .pfnReserved4 = */ NULL,
4950 /* .pfnReserved5 = */ NULL,
4951 /* .pfnReserved6 = */ NULL,
4952 /* .pfnReserved7 = */ NULL,
4953#elif defined(IN_RING0)
4954 /* .pfnEarlyConstruct = */ NULL,
4955 /* .pfnConstruct = */ acpiRZConstruct,
4956 /* .pfnDestruct = */ NULL,
4957 /* .pfnFinalDestruct = */ NULL,
4958 /* .pfnRequest = */ NULL,
4959 /* .pfnReserved0 = */ NULL,
4960 /* .pfnReserved1 = */ NULL,
4961 /* .pfnReserved2 = */ NULL,
4962 /* .pfnReserved3 = */ NULL,
4963 /* .pfnReserved4 = */ NULL,
4964 /* .pfnReserved5 = */ NULL,
4965 /* .pfnReserved6 = */ NULL,
4966 /* .pfnReserved7 = */ NULL,
4967#elif defined(IN_RC)
4968 /* .pfnConstruct = */ acpiRZConstruct,
4969 /* .pfnReserved0 = */ NULL,
4970 /* .pfnReserved1 = */ NULL,
4971 /* .pfnReserved2 = */ NULL,
4972 /* .pfnReserved3 = */ NULL,
4973 /* .pfnReserved4 = */ NULL,
4974 /* .pfnReserved5 = */ NULL,
4975 /* .pfnReserved6 = */ NULL,
4976 /* .pfnReserved7 = */ NULL,
4977#else
4978# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4979#endif
4980 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4981};
4982
4983#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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