VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 86080

Last change on this file since 86080 was 86080, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Enable INVALIDATE_ALL command support and specify the PCI capability space offset in the ACPI tables as well.
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File size: 174.5 KB
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1/* $Id: DevACPI.cpp 86080 2020-09-10 07:08:06Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <VBox/pci.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#include <iprt/asm-math.h>
33#include <iprt/file.h>
34#ifdef IN_RING3
35# include <iprt/alloc.h>
36# include <iprt/string.h>
37# include <iprt/uuid.h>
38#endif /* IN_RING3 */
39#ifdef VBOX_WITH_IOMMU_AMD
40# include <VBox/iommu-amd.h>
41#endif
42
43#include "VBoxDD.h"
44#ifdef VBOX_WITH_IOMMU_AMD
45# include "../Bus/DevIommuAmd.h"
46#endif
47
48#ifdef LOG_ENABLED
49# define DEBUG_ACPI
50#endif
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56#ifdef IN_RING3
57/** Locks the device state, ring-3 only. */
58# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
59 do { \
60 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
61 AssertRC(rcLock); \
62 } while (0)
63#endif
64/** Unlocks the device state (all contexts). */
65#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
66 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
67
68
69#define DEBUG_HEX 0x3000
70#define DEBUG_CHR 0x3001
71
72/** PM Base Address PCI config space offset */
73#define PMBA 0x40
74/** PM Miscellaneous Power Management PCI config space offset */
75#define PMREGMISC 0x80
76
77#define PM_TMR_FREQ 3579545
78/** Default base for PM PIIX4 device */
79#define PM_PORT_BASE 0x4000
80/* Port offsets in PM device */
81enum
82{
83 PM1a_EVT_OFFSET = 0x00,
84 PM1b_EVT_OFFSET = -1, /**< not supported */
85 PM1a_CTL_OFFSET = 0x04,
86 PM1b_CTL_OFFSET = -1, /**< not supported */
87 PM2_CTL_OFFSET = -1, /**< not supported */
88 PM_TMR_OFFSET = 0x08,
89 GPE0_OFFSET = 0x20,
90 GPE1_OFFSET = -1 /**< not supported */
91};
92
93/* Maximum supported number of custom ACPI tables */
94#define MAX_CUST_TABLES 4
95
96/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
97#define PM_TMR_32BIT
98
99#define BAT_INDEX 0x00004040
100#define BAT_DATA 0x00004044
101#define SYSI_INDEX 0x00004048
102#define SYSI_DATA 0x0000404c
103#define ACPI_RESET_BLK 0x00004050
104
105/* PM1x status register bits */
106#define TMR_STS RT_BIT(0)
107#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
108#define BM_STS RT_BIT(4)
109#define GBL_STS RT_BIT(5)
110#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
111#define PWRBTN_STS RT_BIT(8)
112#define SLPBTN_STS RT_BIT(9)
113#define RTC_STS RT_BIT(10)
114#define IGN_STS RT_BIT(11)
115#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
116#define WAK_STS RT_BIT(15)
117#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
118
119/* PM1x enable register bits */
120#define TMR_EN RT_BIT(0)
121#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
122#define GBL_EN RT_BIT(5)
123#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
124#define PWRBTN_EN RT_BIT(8)
125#define SLPBTN_EN RT_BIT(9)
126#define RTC_EN RT_BIT(10)
127#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
128#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
129#define IGN_EN 0
130
131/* PM1x control register bits */
132#define SCI_EN RT_BIT(0)
133#define BM_RLD RT_BIT(1)
134#define GBL_RLS RT_BIT(2)
135#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
136#define IGN_CNT RT_BIT(9)
137#define SLP_TYPx_SHIFT 10
138#define SLP_TYPx_MASK 7
139#define SLP_EN RT_BIT(13)
140#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
141#define RSR_CNT (RSR1_CNT | RSR2_CNT)
142
143#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
144
145enum
146{
147 BAT_STATUS_STATE = 0x00, /**< BST battery state */
148 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
149 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
150 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
151 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
152 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
153 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
154 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
155 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
156 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
157 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
158 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
159 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
160 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
161 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
162 BAT_INDEX_LAST
163};
164
165enum
166{
167 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
168 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
169};
170
171enum
172{
173 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
174 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
175 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
176 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
177 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
178 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
179 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
180 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
181 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
182 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
183 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
184 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
185 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
186 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
187 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
188 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
189 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
190 SYSTEM_INFO_INDEX_POWER_STATES = 17,
191 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
192 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
193 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
194 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
195 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
196 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
197 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
198 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
199 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
200 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
201 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
202 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
203 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
204 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
205 SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS = 32, /**< AMD IOMMU PCI address, or 0 */
206 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
207 SYSTEM_INFO_INDEX_END = 34,
208 SYSTEM_INFO_INDEX_INVALID = 0x80,
209 SYSTEM_INFO_INDEX_VALID = 0x200
210};
211
212#define AC_OFFLINE 0
213#define AC_ONLINE 1
214
215#define BAT_TECH_PRIMARY 1
216#define BAT_TECH_SECONDARY 2
217
218#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
219#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
220#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
221#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
222#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
223
224/** SMBus Base Address PCI config space offset */
225#define SMBBA 0x90
226/** SMBus Host Configuration PCI config space offset */
227#define SMBHSTCFG 0xd2
228/** SMBus Slave Command PCI config space offset */
229#define SMBSLVC 0xd3
230/** SMBus Slave Shadow Port 1 PCI config space offset */
231#define SMBSHDW1 0xd4
232/** SMBus Slave Shadow Port 2 PCI config space offset */
233#define SMBSHDW2 0xd5
234/** SMBus Revision Identification PCI config space offset */
235#define SMBREV 0xd6
236
237#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
238#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
239#define SMBHSTCFG_INTRSEL_SMI 0
240#define SMBHSTCFG_INTRSEL_IRQ9 4
241#define SMBHSTCFG_INTRSEL_SHIFT 1
242
243/** Default base for SMBus PIIX4 device */
244#define SMB_PORT_BASE 0x4100
245
246/** SMBus Host Status Register I/O offset */
247#define SMBHSTSTS_OFF 0x0000
248/** SMBus Slave Status Register I/O offset */
249#define SMBSLVSTS_OFF 0x0001
250/** SMBus Host Count Register I/O offset */
251#define SMBHSTCNT_OFF 0x0002
252/** SMBus Host Command Register I/O offset */
253#define SMBHSTCMD_OFF 0x0003
254/** SMBus Host Address Register I/O offset */
255#define SMBHSTADD_OFF 0x0004
256/** SMBus Host Data 0 Register I/O offset */
257#define SMBHSTDAT0_OFF 0x0005
258/** SMBus Host Data 1 Register I/O offset */
259#define SMBHSTDAT1_OFF 0x0006
260/** SMBus Block Data Register I/O offset */
261#define SMBBLKDAT_OFF 0x0007
262/** SMBus Slave Control Register I/O offset */
263#define SMBSLVCNT_OFF 0x0008
264/** SMBus Shadow Command Register I/O offset */
265#define SMBSHDWCMD_OFF 0x0009
266/** SMBus Slave Event Register I/O offset */
267#define SMBSLVEVT_OFF 0x000a
268/** SMBus Slave Data Register I/O offset */
269#define SMBSLVDAT_OFF 0x000c
270
271#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
272#define SMBHSTSTS_INTER RT_BIT(1)
273#define SMBHSTSTS_DEV_ERR RT_BIT(2)
274#define SMBHSTSTS_BUS_ERR RT_BIT(3)
275#define SMBHSTSTS_FAILED RT_BIT(4)
276#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
277
278#define SMBSLVSTS_WRITE_MASK 0x3c
279
280#define SMBHSTCNT_INTEREN RT_BIT(0)
281#define SMBHSTCNT_KILL RT_BIT(1)
282#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
283#define SMBHSTCNT_START RT_BIT(6)
284#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
285
286#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
287
288
289/*********************************************************************************************************************************
290* Structures and Typedefs *
291*********************************************************************************************************************************/
292/**
293 * The shared ACPI device state.
294 */
295typedef struct ACPISTATE
296{
297 /** Critical section protecting the ACPI state. */
298 PDMCRITSECT CritSect;
299
300 uint16_t pm1a_en;
301 uint16_t pm1a_sts;
302 uint16_t pm1a_ctl;
303 /** Number of logical CPUs in guest */
304 uint16_t cCpus;
305
306 uint64_t u64PmTimerInitial;
307 /** The PM timer. */
308 TMTIMERHANDLE hPmTimer;
309 /* PM Timer last calculated value */
310 uint32_t uPmTimerVal;
311 uint32_t Alignment0;
312
313 uint32_t gpe0_en;
314 uint32_t gpe0_sts;
315
316 uint32_t uBatteryIndex;
317 uint32_t au8BatteryInfo[13];
318
319 uint32_t uSystemInfoIndex;
320 uint32_t u32Alignment0;
321 uint64_t u64RamSize;
322 /** Offset of the 64-bit prefetchable memory window. */
323 uint64_t u64PciPref64Min;
324 /** Limit of the 64-bit prefetchable memory window. */
325 uint64_t u64PciPref64Max;
326 /** The number of bytes below 4GB. */
327 uint32_t cbRamLow;
328
329 /** Current ACPI S* state. We support S0 and S5. */
330 uint32_t uSleepState;
331 uint8_t au8RSDPPage[0x1000];
332 /** This is a workaround for incorrect index field handling by Intels ACPICA.
333 * The system info _INI method writes to offset 0x200. We either observe a
334 * write request to index 0x80 (in that case we don't change the index) or a
335 * write request to offset 0x200 (in that case we divide the index value by
336 * 4. Note that the _STA method is sometimes called prior to the _INI method
337 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
338 * acpiR3BatIndexWrite() for handling this. */
339 uint8_t u8IndexShift;
340 /** provide an I/O-APIC */
341 uint8_t u8UseIOApic;
342 /** provide a floppy controller */
343 bool fUseFdc;
344 /** If High Precision Event Timer device should be supported */
345 bool fUseHpet;
346 /** If System Management Controller device should be supported */
347 bool fUseSmc;
348 /** the guest handled the last power button event */
349 bool fPowerButtonHandled;
350 /** If ACPI CPU device should be shown */
351 bool fShowCpu;
352 /** If Real Time Clock ACPI object to be shown */
353 bool fShowRtc;
354 /** I/O port address of PM device. */
355 RTIOPORT uPmIoPortBase;
356 /** I/O port address of SMBus device. */
357 RTIOPORT uSMBusIoPortBase;
358 /** Which CPU to check for the locked status. */
359 uint32_t idCpuLockCheck;
360 /** Array of flags of attached CPUs */
361 VMCPUSET CpuSetAttached;
362 /** Mask of locked CPUs (used by the guest). */
363 VMCPUSET CpuSetLocked;
364 /** The CPU event type. */
365 uint32_t u32CpuEventType;
366 /** The CPU id affected. */
367 uint32_t u32CpuEvent;
368 /** Flag whether CPU hot plugging is enabled. */
369 bool fCpuHotPlug;
370 /** If MCFG ACPI table shown to the guest */
371 bool fUseMcfg;
372 /** if the 64-bit prefetchable memory window is shown to the guest */
373 bool fPciPref64Enabled;
374 bool afAlignment1;
375 /** Primary NIC PCI address. */
376 uint32_t u32NicPciAddress;
377 /** HD Audio PCI address. */
378 uint32_t u32AudioPciAddress;
379 /** Primary NVMe controller PCI address. */
380 uint32_t u32NvmePciAddress;
381 /** Flag whether S1 power state is enabled. */
382 bool fS1Enabled;
383 /** Flag whether S4 power state is enabled. */
384 bool fS4Enabled;
385 /** Flag whether S1 triggers a state save. */
386 bool fSuspendToSavedState;
387 /** Flag whether to set WAK_STS on resume (restore included). */
388 bool fSetWakeupOnResume;
389 /** PCI address of the IO controller device. */
390 uint32_t u32IocPciAddress;
391 /** PCI address of the host bus controller device. */
392 uint32_t u32HbcPciAddress;
393 /** PCI address of the AMD IOMMU device. */
394 uint32_t u32IommuAmdPciAddress;
395 /** PCI address of the southbridge I/O APIC device. */
396 uint32_t u32SbIoApicPciAddress;
397
398 /** Physical address of PCI config space MMIO region */
399 uint64_t u64PciConfigMMioAddress;
400 /** Length of PCI config space MMIO region */
401 uint64_t u64PciConfigMMioLength;
402 /** Serial 0 IRQ number */
403 uint8_t uSerial0Irq;
404 /** Serial 1 IRQ number */
405 uint8_t uSerial1Irq;
406 /** Serial 2 IRQ number */
407 uint8_t uSerial2Irq;
408 /** Serial 3 IRQ number */
409 uint8_t uSerial3Irq;
410 /** Serial 0 IO port base */
411 RTIOPORT uSerial0IoPortBase;
412 /** Serial 1 IO port base */
413 RTIOPORT uSerial1IoPortBase;
414 /** Serial 2 IO port base */
415 RTIOPORT uSerial2IoPortBase;
416 /** Serial 3 IO port base */
417 RTIOPORT uSerial3IoPortBase;
418
419 /** @name Parallel port config bits
420 * @{ */
421 /** Parallel 0 IO port base */
422 RTIOPORT uParallel0IoPortBase;
423 /** Parallel 1 IO port base */
424 RTIOPORT uParallel1IoPortBase;
425 /** Parallel 0 IRQ number */
426 uint8_t uParallel0Irq;
427 /** Parallel 1 IRQ number */
428 uint8_t uParallel1Irq;
429 /** @} */
430
431 /** Number of custom ACPI tables */
432 uint8_t cCustTbls;
433 /** ACPI OEM ID */
434 uint8_t au8OemId[6];
435 /** ACPI Crator ID */
436 uint8_t au8CreatorId[4];
437 uint8_t abAlignment2[3];
438 /** ACPI Crator Rev */
439 uint32_t u32CreatorRev;
440 /** ACPI custom OEM Tab ID */
441 uint8_t au8OemTabId[8];
442 /** ACPI custom OEM Rev */
443 uint32_t u32OemRevision;
444
445 /** SMBus Host Status Register */
446 uint8_t u8SMBusHstSts;
447 /** SMBus Slave Status Register */
448 uint8_t u8SMBusSlvSts;
449 /** SMBus Host Control Register */
450 uint8_t u8SMBusHstCnt;
451 /** SMBus Host Command Register */
452 uint8_t u8SMBusHstCmd;
453 /** SMBus Host Address Register */
454 uint8_t u8SMBusHstAdd;
455 /** SMBus Host Data 0 Register */
456 uint8_t u8SMBusHstDat0;
457 /** SMBus Host Data 1 Register */
458 uint8_t u8SMBusHstDat1;
459 /** SMBus Slave Control Register */
460 uint8_t u8SMBusSlvCnt;
461 /** SMBus Slave Event Register */
462 uint16_t u16SMBusSlvEvt;
463 /** SMBus Slave Data Register */
464 uint16_t u16SMBusSlvDat;
465 /** SMBus Shadow Command Register */
466 uint8_t u8SMBusShdwCmd;
467 /** SMBus Host Block Index */
468 uint8_t u8SMBusBlkIdx;
469 uint8_t abAlignment3[2];
470 /** SMBus Host Block Data Buffer */
471 uint8_t au8SMBusBlkDat[32];
472
473 /** @todo DEBUGGING */
474 uint32_t uPmTimeOld;
475 uint32_t uPmTimeA;
476 uint32_t uPmTimeB;
477 uint32_t Alignment5;
478
479 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
480 * @{ */
481 IOMIOPORTHANDLE hIoPortPm1aEn;
482 IOMIOPORTHANDLE hIoPortPm1aSts;
483 IOMIOPORTHANDLE hIoPortPm1aCtl;
484 IOMIOPORTHANDLE hIoPortPmTimer;
485 IOMIOPORTHANDLE hIoPortGpe0En;
486 IOMIOPORTHANDLE hIoPortGpe0Sts;
487 /** @} */
488
489 /** SMBus I/O ports (mapped/unmapped). */
490 IOMIOPORTHANDLE hIoPortSMBus;
491
492 /** @name Fixed I/O ports
493 * @{ */
494 /** ACPI SMI I/O port. */
495 IOMIOPORTHANDLE hIoPortSmi;
496 /** ACPI Debug hex I/O port. */
497 IOMIOPORTHANDLE hIoPortDebugHex;
498 /** ACPI Debug char I/O port. */
499 IOMIOPORTHANDLE hIoPortDebugChar;
500 /** ACPI Battery status index I/O port. */
501 IOMIOPORTHANDLE hIoPortBatteryIndex;
502 /** ACPI Battery status data I/O port. */
503 IOMIOPORTHANDLE hIoPortBatteryData;
504 /** ACPI system info index I/O port. */
505 IOMIOPORTHANDLE hIoPortSysInfoIndex;
506 /** ACPI system info data I/O port. */
507 IOMIOPORTHANDLE hIoPortSysInfoData;
508 /** ACPI Reset I/O port. */
509 IOMIOPORTHANDLE hIoPortReset;
510 /** @} */
511
512} ACPISTATE;
513/** Pointer to the shared ACPI device state. */
514typedef ACPISTATE *PACPISTATE;
515
516
517
518/**
519 * The ring-3 ACPI device state.
520 */
521typedef struct ACPISTATER3
522{
523 /** ACPI port base interface. */
524 PDMIBASE IBase;
525 /** ACPI port interface. */
526 PDMIACPIPORT IACPIPort;
527 /** Pointer to the device instance so we can get our bearings from
528 * interface functions. */
529 PPDMDEVINSR3 pDevIns;
530
531 /** Pointer to the driver base interface. */
532 R3PTRTYPE(PPDMIBASE) pDrvBase;
533 /** Pointer to the driver connector interface. */
534 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
535
536 /** Custom ACPI tables binary data. */
537 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
538 /** The size of the custom table binary. */
539 uint64_t acbCustBin[MAX_CUST_TABLES];
540} ACPISTATER3;
541/** Pointer to the ring-3 ACPI device state. */
542typedef ACPISTATER3 *PACPISTATER3;
543
544
545#pragma pack(1)
546
547/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
548struct ACPIGENADDR
549{
550 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
551 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
552 uint8_t u8RegisterBitOffset; /**< bit offset of register */
553 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
554 uint64_t u64Address; /**< 64-bit address of register */
555};
556AssertCompileSize(ACPIGENADDR, 12);
557
558/** Root System Description Pointer */
559struct ACPITBLRSDP
560{
561 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
562 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
563 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
564 uint8_t u8Revision; /**< revision number, currently 2 */
565#define ACPI_REVISION 2 /**< ACPI 3.0 */
566 uint32_t u32RSDT; /**< phys addr of RSDT */
567 uint32_t u32Length; /**< bytes of this table */
568 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
569 uint8_t u8ExtChecksum; /**< checksum of entire table */
570 uint8_t u8Reserved[3]; /**< reserved */
571};
572AssertCompileSize(ACPITBLRSDP, 36);
573
574/** System Description Table Header */
575struct ACPITBLHEADER
576{
577 uint8_t au8Signature[4]; /**< table identifier */
578 uint32_t u32Length; /**< length of the table including header */
579 uint8_t u8Revision; /**< revision number */
580 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
581 uint8_t au8OemId[6]; /**< OEM-supplied string */
582 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
583 uint32_t u32OemRevision; /**< OEM-supplied revision number */
584 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
585 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
586};
587AssertCompileSize(ACPITBLHEADER, 36);
588
589/** Root System Description Table */
590struct ACPITBLRSDT
591{
592 ACPITBLHEADER header;
593 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
594};
595AssertCompileSize(ACPITBLRSDT, 40);
596
597/** Extended System Description Table */
598struct ACPITBLXSDT
599{
600 ACPITBLHEADER header;
601 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
602};
603AssertCompileSize(ACPITBLXSDT, 44);
604
605/** Fixed ACPI Description Table */
606struct ACPITBLFADT
607{
608 ACPITBLHEADER header;
609 uint32_t u32FACS; /**< phys. address of FACS */
610 uint32_t u32DSDT; /**< phys. address of DSDT */
611 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
612#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
613#define INT_MODEL_MULTIPLE_APIC 2
614 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
615 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
616#define SCI_INT 9
617 uint32_t u32SMICmd; /**< system port address of SMI command port */
618#define SMI_CMD 0x0000442e
619 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
620#define ACPI_ENABLE 0xa1
621 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
622#define ACPI_DISABLE 0xa0
623 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
624 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
625 state control responsibility */
626 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
627 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
628 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
629 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
630 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
631 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
632 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
633 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
634 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
635 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
636 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
637 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
638 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
639#define GPE0_BLK_LEN 2
640 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
641#define GPE1_BLK_LEN 0
642 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
643#define GPE1_BASE 0
644 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
645 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
646#define P_LVL2_LAT 101 /**< C2 state not supported */
647 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
648#define P_LVL3_LAT 1001 /**< C3 state not supported */
649 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
650 lines from any processors memory caches */
651#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
652 uint16_t u16FlushStride; /**< cache line width */
653#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
654 uint8_t u8DutyOffset;
655 uint8_t u8DutyWidth;
656 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
657 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
658 uint8_t u8Century; /**< RTC CMOS RAM index of century */
659 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
660#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
661 (COM too?) */
662#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
663#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
664#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
665#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
666 uint8_t u8Must0_0; /**< must be 0 */
667 uint32_t u32Flags; /**< fixed feature flags */
668#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
669#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
670#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
671#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
672#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
673#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
674#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
675#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
676#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
677#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
678#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
679#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
680#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
681#define FADT_FL_CPU_SW_SLP RT_BIT(13)
682#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
683#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
684#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
685#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
686#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
687#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
688
689/* PM Timer mask and msb */
690#ifndef PM_TMR_32BIT
691#define TMR_VAL_MSB 0x800000
692#define TMR_VAL_MASK 0xffffff
693#undef FADT_FL_TMR_VAL_EXT
694#define FADT_FL_TMR_VAL_EXT 0
695#else
696#define TMR_VAL_MSB 0x80000000
697#define TMR_VAL_MASK 0xffffffff
698#endif
699
700 /** Start of the ACPI 2.0 extension. */
701 ACPIGENADDR ResetReg; /**< ext addr of reset register */
702 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
703#define ACPI_RESET_REG_VAL 0x10
704 uint8_t au8Must0_1[3]; /**< must be 0 */
705 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
706 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
707 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
708 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
709 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
710 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
711 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
712 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
713 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
714 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
715};
716AssertCompileSize(ACPITBLFADT, 244);
717#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
718
719/** Firmware ACPI Control Structure */
720struct ACPITBLFACS
721{
722 uint8_t au8Signature[4]; /**< 'FACS' */
723 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
724 uint32_t u32HWSignature; /**< systems HW signature at last boot */
725 uint32_t u32FWVector; /**< address of waking vector */
726 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
727 uint32_t u32Flags; /**< FACS flags */
728 uint64_t u64X_FWVector; /**< 64-bit waking vector */
729 uint8_t u8Version; /**< version of this table */
730 uint8_t au8Reserved[31]; /**< zero */
731};
732AssertCompileSize(ACPITBLFACS, 64);
733
734/** Processor Local APIC Structure */
735struct ACPITBLLAPIC
736{
737 uint8_t u8Type; /**< 0 = LAPIC */
738 uint8_t u8Length; /**< 8 */
739 uint8_t u8ProcId; /**< processor ID */
740 uint8_t u8ApicId; /**< local APIC ID */
741 uint32_t u32Flags; /**< Flags */
742#define LAPIC_ENABLED 0x1
743};
744AssertCompileSize(ACPITBLLAPIC, 8);
745
746/** I/O APIC Structure */
747struct ACPITBLIOAPIC
748{
749 uint8_t u8Type; /**< 1 == I/O APIC */
750 uint8_t u8Length; /**< 12 */
751 uint8_t u8IOApicId; /**< I/O APIC ID */
752 uint8_t u8Reserved; /**< 0 */
753 uint32_t u32Address; /**< phys address to access I/O APIC */
754 uint32_t u32GSIB; /**< global system interrupt number to start */
755};
756AssertCompileSize(ACPITBLIOAPIC, 12);
757
758/** Interrupt Source Override Structure */
759struct ACPITBLISO
760{
761 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
762 uint8_t u8Length; /**< 10 */
763 uint8_t u8Bus; /**< Bus */
764 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
765 uint32_t u32GSI; /**< Global System Interrupt */
766 uint16_t u16Flags; /**< MPS INTI flags Global */
767};
768AssertCompileSize(ACPITBLISO, 10);
769#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
770
771/** HPET Descriptor Structure */
772struct ACPITBLHPET
773{
774 ACPITBLHEADER aHeader;
775 uint32_t u32Id; /**< hardware ID of event timer block
776 [31:16] PCI vendor ID of first timer block
777 [15] legacy replacement IRQ routing capable
778 [14] reserved
779 [13] COUNT_SIZE_CAP counter size
780 [12:8] number of comparators in first timer block
781 [7:0] hardware rev ID */
782 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
783 uint8_t u32Number; /**< sequence number starting at 0 */
784 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
785 lost interrupts while the counter is programmed
786 to operate in periodic mode. Unit: clock tick. */
787 uint8_t u8Attributes; /**< page protection and OEM attribute. */
788};
789AssertCompileSize(ACPITBLHPET, 56);
790
791#ifdef VBOX_WITH_IOMMU_AMD
792/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
793 * In accordance with the AMD spec. */
794typedef struct ACPIIVRS
795{
796 ACPITBLHEADER header;
797 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
798 uint64_t u64Rsvd; /**< Reserved (MBZ). */
799 /* IVHD type block follows. */
800} ACPIIVRS;
801AssertCompileSize(ACPIIVRS, 48);
802AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
803
804/**
805 * AMD IOMMU: The ACPI table.
806 */
807typedef struct ACPITBLIOMMU
808{
809 ACPIIVRS Hdr;
810 ACPIIVHDTYPE10 IvhdType10;
811 ACPIIVHDDEVENTRY4 IvhdType10Start;
812 ACPIIVHDDEVENTRY4 IvhdType10End;
813 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
814 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
815 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
816 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
817
818 ACPIIVHDTYPE11 IvhdType11;
819 ACPIIVHDDEVENTRY4 IvhdType11Start;
820 ACPIIVHDDEVENTRY4 IvhdType11End;
821 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
822 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
823 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
824 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
825} ACPITBLIOMMU;
826AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
827AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
828AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
829AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
830#endif
831
832/** MCFG Descriptor Structure */
833typedef struct ACPITBLMCFG
834{
835 ACPITBLHEADER aHeader;
836 uint64_t u64Reserved;
837} ACPITBLMCFG;
838AssertCompileSize(ACPITBLMCFG, 44);
839
840/** Number of such entries can be computed from the whole table length in header */
841typedef struct ACPITBLMCFGENTRY
842{
843 uint64_t u64BaseAddress;
844 uint16_t u16PciSegmentGroup;
845 uint8_t u8StartBus;
846 uint8_t u8EndBus;
847 uint32_t u32Reserved;
848} ACPITBLMCFGENTRY;
849AssertCompileSize(ACPITBLMCFGENTRY, 16);
850
851#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
852
853/** Custom Description Table */
854struct ACPITBLCUST
855{
856 ACPITBLHEADER header;
857 uint8_t au8Data[476];
858};
859AssertCompileSize(ACPITBLCUST, 512);
860
861
862#pragma pack()
863
864
865#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
866
867
868/*********************************************************************************************************************************
869* Internal Functions *
870*********************************************************************************************************************************/
871#ifdef IN_RING3
872static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
873#endif
874
875/* SCI, usually IRQ9 */
876DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
877{
878 PDMDevHlpPCISetIrq(pDevIns, 0, level);
879}
880
881DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
882{
883 return (pThis->pm1a_ctl & SCI_EN)
884 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
885}
886
887DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
888{
889 return !!(pThis->gpe0_en & pThis->gpe0_sts);
890}
891
892DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
893{
894 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
895 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
896 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
897 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
898 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
899}
900
901DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
902{
903 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
904}
905
906/**
907 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
908 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
909 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
910 * registers and trigger IRQs.
911 *
912 * Caller must hold the state lock.
913 *
914 * @param pDevIns The PDM device instance.
915 * @param pThis The ACPI shared instance data.
916 * @param sts The new PM1a.STS value.
917 * @param en The new PM1a.EN value.
918 */
919static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
920{
921 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
922
923 const bool old_level = acpiSCILevel(pDevIns, pThis);
924 pThis->pm1a_en = en;
925 pThis->pm1a_sts = sts;
926 const bool new_level = acpiSCILevel(pDevIns, pThis);
927
928 LogFunc(("old=%x new=%x\n", old_level, new_level));
929
930 if (new_level != old_level)
931 acpiSetIrq(pDevIns, new_level);
932}
933
934#ifdef IN_RING3
935
936/**
937 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
938 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
939 *
940 * Caller must hold the state lock.
941 *
942 * @param pDevIns The PDM device instance.
943 * @param pThis The ACPI shared instance data.
944 * @param sts The new GPE0.STS value.
945 * @param en The new GPE0.EN value.
946 */
947static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
948{
949 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
950
951 const bool old_level = acpiSCILevel(pDevIns, pThis);
952 pThis->gpe0_en = en;
953 pThis->gpe0_sts = sts;
954 const bool new_level = acpiSCILevel(pDevIns, pThis);
955
956 LogFunc(("old=%x new=%x\n", old_level, new_level));
957
958 if (new_level != old_level)
959 acpiSetIrq(pDevIns, new_level);
960}
961
962/**
963 * Used by acpiR3PM1aCtlWrite to power off the VM.
964 *
965 * @param pDevIns The device instance.
966 * @returns Strict VBox status code.
967 */
968static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
969{
970 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
971 AssertRC(VBOXSTRICTRC_VAL(rc));
972 return rc;
973}
974
975/**
976 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
977 *
978 * @param pDevIns The device instance.
979 * @param pThis The ACPI shared instance data.
980 * @returns Strict VBox status code.
981 */
982static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
983{
984 /* We must set WAK_STS on resume (includes restore) so the guest knows that
985 we've woken up and can continue executing code. The guest is probably
986 reading the PMSTS register in a loop to check this. */
987 VBOXSTRICTRC rc;
988 pThis->fSetWakeupOnResume = true;
989 if (pThis->fSuspendToSavedState)
990 {
991 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
992 if (rc != VERR_NOT_SUPPORTED)
993 AssertRC(VBOXSTRICTRC_VAL(rc));
994 else
995 {
996 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
997 rc = PDMDevHlpVMSuspend(pDevIns);
998 AssertRC(VBOXSTRICTRC_VAL(rc));
999 }
1000 }
1001 else
1002 {
1003 rc = PDMDevHlpVMSuspend(pDevIns);
1004 AssertRC(VBOXSTRICTRC_VAL(rc));
1005 }
1006 return rc;
1007}
1008
1009
1010/**
1011 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
1012 */
1013static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
1014{
1015 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1016 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1017 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1018 DEVACPI_LOCK_R3(pDevIns, pThis);
1019
1020 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1021 pThis->fPowerButtonHandled = false;
1022 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1023
1024 DEVACPI_UNLOCK(pDevIns, pThis);
1025 return VINF_SUCCESS;
1026}
1027
1028/**
1029 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
1030 */
1031static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1032{
1033 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1034 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1035 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1036 DEVACPI_LOCK_R3(pDevIns, pThis);
1037
1038 *pfHandled = pThis->fPowerButtonHandled;
1039
1040 DEVACPI_UNLOCK(pDevIns, pThis);
1041 return VINF_SUCCESS;
1042}
1043
1044/**
1045 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1046 * Guest entered into G0 (working) or G1 (sleeping)}
1047 */
1048static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1049{
1050 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1051 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1052 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1053 DEVACPI_LOCK_R3(pDevIns, pThis);
1054
1055 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1056
1057 DEVACPI_UNLOCK(pDevIns, pThis);
1058 return VINF_SUCCESS;
1059}
1060
1061/**
1062 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1063 */
1064static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1065{
1066 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1067 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1068 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1069 DEVACPI_LOCK_R3(pDevIns, pThis);
1070
1071 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1072
1073 DEVACPI_UNLOCK(pDevIns, pThis);
1074 return VINF_SUCCESS;
1075}
1076
1077/**
1078 * Send an ACPI sleep button event.
1079 *
1080 * @returns VBox status code
1081 * @param pInterface Pointer to the interface structure containing the called function pointer.
1082 */
1083static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1084{
1085 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1086 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1087 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1088 DEVACPI_LOCK_R3(pDevIns, pThis);
1089
1090 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1091
1092 DEVACPI_UNLOCK(pDevIns, pThis);
1093 return VINF_SUCCESS;
1094}
1095
1096/**
1097 * Send an ACPI monitor hot-plug event.
1098 *
1099 * @returns VBox status code
1100 * @param pInterface Pointer to the interface structure containing the
1101 * called function pointer.
1102 */
1103static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1104{
1105 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1106 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1107 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1108 DEVACPI_LOCK_R3(pDevIns, pThis);
1109
1110 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1111
1112 DEVACPI_UNLOCK(pDevIns, pThis);
1113 return VINF_SUCCESS;
1114}
1115
1116/**
1117 * Send an ACPI battery status change event.
1118 *
1119 * @returns VBox status code
1120 * @param pInterface Pointer to the interface structure containing the
1121 * called function pointer.
1122 */
1123static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1124{
1125 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1126 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1127 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1128 DEVACPI_LOCK_R3(pDevIns, pThis);
1129
1130 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1131
1132 DEVACPI_UNLOCK(pDevIns, pThis);
1133 return VINF_SUCCESS;
1134}
1135
1136/**
1137 * Used by acpiR3PmTimer to re-arm the PM timer.
1138 *
1139 * The caller is expected to either hold the clock lock or to have made sure
1140 * the VM is resetting or loading state.
1141 *
1142 * @param pDevIns The device instance.
1143 * @param pThis The ACPI shared instance data.
1144 * @param uNow The current time.
1145 */
1146static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1147{
1148 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1149 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1150 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1151 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1152 Log(("acpi: uInterval = %RU64\n", uInterval));
1153}
1154
1155#endif /* IN_RING3 */
1156
1157/**
1158 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1159 *
1160 * The caller is expected to either hold the clock lock or to have made sure
1161 * the VM is resetting or loading state.
1162 *
1163 * @param pDevIns The PDM device instance.
1164 * @param pThis The ACPI instance
1165 * @param u64Now The current time
1166 */
1167static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1168{
1169 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1170 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1171 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1172
1173 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ,
1174 PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1175 & TMR_VAL_MASK;
1176
1177 if ( (pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1178 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1179}
1180
1181#ifdef IN_RING3
1182
1183/**
1184 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1185 */
1186static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1187{
1188 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1189 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1190 RT_NOREF(pTimer, pvUser);
1191
1192 DEVACPI_LOCK_R3(pDevIns, pThis);
1193 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1194 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1195 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1196 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1197 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1198 DEVACPI_UNLOCK(pDevIns, pThis);
1199
1200 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
1201}
1202
1203/**
1204 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1205 * acpiR3LoadState.
1206 *
1207 * @returns VINF_SUCCESS.
1208 * @param pThis The ACPI shared instance data.
1209 * @param pThisCC The ACPI instance data for ring-3.
1210 */
1211static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1212{
1213 uint32_t *p = pThis->au8BatteryInfo;
1214 bool fPresent; /* battery present? */
1215 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1216 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1217 uint32_t hostPresentRate; /* 0..1000 */
1218 int rc;
1219
1220 if (!pThisCC->pDrv)
1221 return VINF_SUCCESS;
1222 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1223 &hostBatteryState, &hostPresentRate);
1224 AssertRC(rc);
1225
1226 /* default values */
1227 p[BAT_STATUS_STATE] = hostBatteryState;
1228 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1229 : hostPresentRate * 50; /* mW */
1230 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1231 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1232
1233 /* did we get a valid battery state? */
1234 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1235 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1236 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1237 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1238
1239 return VINF_SUCCESS;
1240}
1241
1242/**
1243 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1244 * acpiR3LoadState.
1245 *
1246 * @returns VINF_SUCCESS.
1247 * @param pThis The ACPI shared instance data.
1248 */
1249static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1250{
1251 uint32_t *p = pThis->au8BatteryInfo;
1252
1253 p[BAT_INFO_UNITS] = 0; /* mWh */
1254 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1255 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1256 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1257 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1258 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1259 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1260 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1261 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1262
1263 return VINF_SUCCESS;
1264}
1265
1266/**
1267 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1268 *
1269 * @returns status mask or 0.
1270 * @param pThisCC The ACPI instance data for ring-3.
1271 */
1272static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1273{
1274 bool fPresent; /* battery present? */
1275 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1276 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1277 uint32_t hostPresentRate; /* 0..1000 */
1278 int rc;
1279
1280 if (!pThisCC->pDrv)
1281 return 0;
1282 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1283 &hostBatteryState, &hostPresentRate);
1284 AssertRC(rc);
1285
1286 return fPresent
1287 ? STA_DEVICE_PRESENT_MASK /* present */
1288 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1289 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1290 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1291 | STA_BATTERY_PRESENT_MASK /* battery is present */
1292 : 0; /* device not present */
1293}
1294
1295/**
1296 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1297 *
1298 * @returns status.
1299 * @param pThisCC The ACPI instance data for ring-3.
1300 */
1301static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1302{
1303 /* query the current power source from the host driver */
1304 if (!pThisCC->pDrv)
1305 return AC_ONLINE;
1306
1307 PDMACPIPOWERSOURCE ps;
1308 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1309 AssertRC(rc);
1310 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1311}
1312
1313/**
1314 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1315 */
1316static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1317{
1318 RT_NOREF(pvUser, offPort);
1319 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1320 if (cb != 4)
1321 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1322
1323 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1324 DEVACPI_LOCK_R3(pDevIns, pThis);
1325
1326 u32 >>= pThis->u8IndexShift;
1327 /* see comment at the declaration of u8IndexShift */
1328 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1329 {
1330 pThis->u8IndexShift = 2;
1331 u32 >>= 2;
1332 }
1333 Assert(u32 < BAT_INDEX_LAST);
1334 pThis->uBatteryIndex = u32;
1335
1336 DEVACPI_UNLOCK(pDevIns, pThis);
1337 return VINF_SUCCESS;
1338}
1339
1340/**
1341 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1342 */
1343static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1344{
1345 RT_NOREF(pvUser, offPort);
1346 if (cb != 4)
1347 return VERR_IOM_IOPORT_UNUSED;
1348
1349 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1350 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1351 DEVACPI_LOCK_R3(pDevIns, pThis);
1352
1353 VBOXSTRICTRC rc = VINF_SUCCESS;
1354 switch (pThis->uBatteryIndex)
1355 {
1356 case BAT_STATUS_STATE:
1357 acpiR3FetchBatteryStatus(pThis, pThisCC);
1358 RT_FALL_THRU();
1359 case BAT_STATUS_PRESENT_RATE:
1360 case BAT_STATUS_REMAINING_CAPACITY:
1361 case BAT_STATUS_PRESENT_VOLTAGE:
1362 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1363 break;
1364
1365 case BAT_INFO_UNITS:
1366 acpiR3FetchBatteryInfo(pThis);
1367 RT_FALL_THRU();
1368 case BAT_INFO_DESIGN_CAPACITY:
1369 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1370 case BAT_INFO_TECHNOLOGY:
1371 case BAT_INFO_DESIGN_VOLTAGE:
1372 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1373 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1374 case BAT_INFO_CAPACITY_GRANULARITY_1:
1375 case BAT_INFO_CAPACITY_GRANULARITY_2:
1376 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1377 break;
1378
1379 case BAT_DEVICE_STATUS:
1380 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1381 break;
1382
1383 case BAT_POWER_SOURCE:
1384 *pu32 = acpiR3GetPowerSource(pThisCC);
1385 break;
1386
1387 default:
1388 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1389 *pu32 = UINT32_MAX;
1390 break;
1391 }
1392
1393 DEVACPI_UNLOCK(pDevIns, pThis);
1394 return rc;
1395}
1396
1397/**
1398 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1399 */
1400static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1401{
1402 RT_NOREF(pvUser, offPort);
1403 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1404 if (cb != 4)
1405 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1406
1407 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1408 DEVACPI_LOCK_R3(pDevIns, pThis);
1409
1410 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1411 pThis->uSystemInfoIndex = u32;
1412 else
1413 {
1414 /* see comment at the declaration of u8IndexShift */
1415 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1416 {
1417 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1418 pThis->u8IndexShift = 2;
1419 }
1420
1421 u32 >>= pThis->u8IndexShift;
1422 AssertMsg(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1423 pThis->uSystemInfoIndex = u32;
1424 }
1425
1426 DEVACPI_UNLOCK(pDevIns, pThis);
1427 return VINF_SUCCESS;
1428}
1429
1430/**
1431 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1432 */
1433static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1434{
1435 RT_NOREF(pvUser, offPort);
1436 if (cb != 4)
1437 return VERR_IOM_IOPORT_UNUSED;
1438
1439 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1440 DEVACPI_LOCK_R3(pDevIns, pThis);
1441
1442 VBOXSTRICTRC rc = VINF_SUCCESS;
1443 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1444 switch (uSystemInfoIndex)
1445 {
1446 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1447 *pu32 = pThis->cbRamLow;
1448 break;
1449
1450 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1451 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1452 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1453 break;
1454
1455 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1456 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1457 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1458 break;
1459
1460 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1461 *pu32 = pThis->u8UseIOApic;
1462 break;
1463
1464 case SYSTEM_INFO_INDEX_HPET_STATUS:
1465 *pu32 = pThis->fUseHpet
1466 ? ( STA_DEVICE_PRESENT_MASK
1467 | STA_DEVICE_ENABLED_MASK
1468 | STA_DEVICE_SHOW_IN_UI_MASK
1469 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1470 : 0;
1471 break;
1472
1473 case SYSTEM_INFO_INDEX_SMC_STATUS:
1474 *pu32 = pThis->fUseSmc
1475 ? ( STA_DEVICE_PRESENT_MASK
1476 | STA_DEVICE_ENABLED_MASK
1477 /* no need to show this device in the UI */
1478 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1479 : 0;
1480 break;
1481
1482 case SYSTEM_INFO_INDEX_FDC_STATUS:
1483 *pu32 = pThis->fUseFdc
1484 ? ( STA_DEVICE_PRESENT_MASK
1485 | STA_DEVICE_ENABLED_MASK
1486 | STA_DEVICE_SHOW_IN_UI_MASK
1487 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1488 : 0;
1489 break;
1490
1491 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1492 *pu32 = pThis->u32NicPciAddress;
1493 break;
1494
1495 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1496 *pu32 = pThis->u32AudioPciAddress;
1497 break;
1498
1499 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1500 *pu32 = pThis->u32NvmePciAddress;
1501 break;
1502
1503 case SYSTEM_INFO_INDEX_POWER_STATES:
1504 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1505 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1506 *pu32 |= RT_BIT(1);
1507 if (pThis->fS4Enabled)
1508 *pu32 |= RT_BIT(4);
1509 break;
1510
1511 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1512 *pu32 = pThis->u32IocPciAddress;
1513 break;
1514
1515 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1516 *pu32 = pThis->u32HbcPciAddress;
1517 break;
1518
1519 case SYSTEM_INFO_INDEX_PCI_BASE:
1520 /** @todo couldn't MCFG be in 64-bit range? */
1521 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1522 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1523 break;
1524
1525 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1526 /** @todo couldn't MCFG be in 64-bit range? */
1527 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1528 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1529 break;
1530
1531 case SYSTEM_INFO_INDEX_RTC_STATUS:
1532 *pu32 = pThis->fShowRtc
1533 ? ( STA_DEVICE_PRESENT_MASK
1534 | STA_DEVICE_ENABLED_MASK
1535 | STA_DEVICE_SHOW_IN_UI_MASK
1536 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1537 : 0;
1538 break;
1539
1540 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1541 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1542 {
1543 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1544 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1545 }
1546 else
1547 {
1548 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1549 pThis->idCpuLockCheck);
1550 /* Always return locked status just to be safe */
1551 *pu32 = 1;
1552 }
1553 break;
1554
1555 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1556 *pu32 = pThis->u32CpuEventType;
1557 break;
1558
1559 case SYSTEM_INFO_INDEX_CPU_EVENT:
1560 *pu32 = pThis->u32CpuEvent;
1561 break;
1562
1563 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1564 *pu32 = pThis->uSerial0IoPortBase;
1565 break;
1566
1567 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1568 *pu32 = pThis->uSerial0Irq;
1569 break;
1570
1571 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1572 *pu32 = pThis->uSerial1IoPortBase;
1573 break;
1574
1575 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1576 *pu32 = pThis->uSerial1Irq;
1577 break;
1578
1579 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1580 *pu32 = pThis->uSerial2IoPortBase;
1581 break;
1582
1583 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1584 *pu32 = pThis->uSerial2Irq;
1585 break;
1586
1587 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1588 *pu32 = pThis->uSerial3IoPortBase;
1589 break;
1590
1591 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1592 *pu32 = pThis->uSerial3Irq;
1593 break;
1594
1595 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1596 *pu32 = pThis->uParallel0IoPortBase;
1597 break;
1598
1599 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1600 *pu32 = pThis->uParallel0Irq;
1601 break;
1602
1603 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1604 *pu32 = pThis->uParallel1IoPortBase;
1605 break;
1606
1607 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1608 *pu32 = pThis->uParallel1Irq;
1609 break;
1610
1611 case SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS:
1612 *pu32 = pThis->u32IommuAmdPciAddress;
1613 break;
1614
1615 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
1616 *pu32 = pThis->u32SbIoApicPciAddress;
1617 break;
1618
1619 case SYSTEM_INFO_INDEX_END:
1620 /** @todo why isn't this setting any output value? */
1621 break;
1622
1623 /* Solaris 9 tries to read from this index */
1624 case SYSTEM_INFO_INDEX_INVALID:
1625 *pu32 = 0;
1626 break;
1627
1628 default:
1629 *pu32 = UINT32_MAX;
1630 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1631 break;
1632 }
1633
1634 DEVACPI_UNLOCK(pDevIns, pThis);
1635 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1636 return rc;
1637}
1638
1639/**
1640 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1641 */
1642static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1643{
1644 RT_NOREF(pvUser, offPort);
1645 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1646 if (cb != 4)
1647 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1648
1649 DEVACPI_LOCK_R3(pDevIns, pThis);
1650 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1651
1652 VBOXSTRICTRC rc = VINF_SUCCESS;
1653 switch (pThis->uSystemInfoIndex)
1654 {
1655 case SYSTEM_INFO_INDEX_INVALID:
1656 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1657 pThis->u8IndexShift = 0;
1658 break;
1659
1660 case SYSTEM_INFO_INDEX_VALID:
1661 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1662 pThis->u8IndexShift = 2;
1663 break;
1664
1665 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1666 pThis->idCpuLockCheck = u32;
1667 break;
1668
1669 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1670 if (u32 < pThis->cCpus)
1671 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1672 else
1673 LogRel(("ACPI: CPU %u does not exist\n", u32));
1674 break;
1675
1676 default:
1677 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1678 break;
1679 }
1680
1681 DEVACPI_UNLOCK(pDevIns, pThis);
1682 return rc;
1683}
1684
1685/**
1686 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1687 */
1688static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1689{
1690 RT_NOREF(offPort, pvUser);
1691 if (cb != 2)
1692 return VERR_IOM_IOPORT_UNUSED;
1693
1694 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1695 DEVACPI_LOCK_R3(pDevIns, pThis);
1696
1697 *pu32 = pThis->pm1a_en;
1698
1699 DEVACPI_UNLOCK(pDevIns, pThis);
1700 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1701 return VINF_SUCCESS;
1702}
1703
1704/**
1705 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1706 */
1707static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1708{
1709 RT_NOREF(offPort, pvUser);
1710 if (cb != 2 && cb != 4)
1711 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1712
1713 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1714 DEVACPI_LOCK_R3(pDevIns, pThis);
1715
1716 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1717 u32 &= ~(RSR_EN | IGN_EN);
1718 u32 &= 0xffff;
1719 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1720
1721 DEVACPI_UNLOCK(pDevIns, pThis);
1722 return VINF_SUCCESS;
1723}
1724
1725/**
1726 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1727 */
1728static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1729{
1730 RT_NOREF(offPort, pvUser);
1731 if (cb != 2)
1732 {
1733 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1734 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1735 }
1736
1737 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1738 DEVACPI_LOCK_R3(pDevIns, pThis);
1739
1740 *pu32 = pThis->pm1a_sts;
1741
1742 DEVACPI_UNLOCK(pDevIns, pThis);
1743 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1744 return VINF_SUCCESS;
1745}
1746
1747/**
1748 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1749 */
1750static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1751{
1752 RT_NOREF(offPort, pvUser);
1753 if (cb != 2 && cb != 4)
1754 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1755
1756 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1757 DEVACPI_LOCK_R3(pDevIns, pThis);
1758
1759 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1760 u32 &= 0xffff;
1761 if (u32 & PWRBTN_STS)
1762 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1763 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1764 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1765
1766 DEVACPI_UNLOCK(pDevIns, pThis);
1767 return VINF_SUCCESS;
1768}
1769
1770/**
1771 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1772 */
1773static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1774{
1775 RT_NOREF(offPort, pvUser);
1776 if (cb != 2)
1777 {
1778 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1779 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1780 }
1781
1782 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1783 DEVACPI_LOCK_R3(pDevIns, pThis);
1784
1785 *pu32 = pThis->pm1a_ctl;
1786
1787 DEVACPI_UNLOCK(pDevIns, pThis);
1788 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1789 return VINF_SUCCESS;
1790}
1791
1792/**
1793 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1794 */
1795static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1796{
1797 RT_NOREF(offPort, pvUser);
1798 if (cb != 2 && cb != 4)
1799 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1800
1801 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1802 DEVACPI_LOCK_R3(pDevIns, pThis);
1803
1804 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1805 u32 &= 0xffff;
1806 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1807
1808 VBOXSTRICTRC rc = VINF_SUCCESS;
1809 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1810 if (uSleepState != pThis->uSleepState)
1811 {
1812 pThis->uSleepState = uSleepState;
1813 switch (uSleepState)
1814 {
1815 case 0x00: /* S0 */
1816 break;
1817
1818 case 0x01: /* S1 */
1819 if (pThis->fS1Enabled)
1820 {
1821 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1822 rc = acpiR3DoSleep(pDevIns, pThis);
1823 break;
1824 }
1825 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1826 RT_FALL_THRU();
1827
1828 case 0x04: /* S4 */
1829 if (pThis->fS4Enabled)
1830 {
1831 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1832 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1833 break;
1834 }
1835 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1836 RT_FALL_THRU();
1837
1838 case 0x05: /* S5 */
1839 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1840 rc = acpiR3DoPowerOff(pDevIns);
1841 break;
1842
1843 default:
1844 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1845 break;
1846 }
1847 }
1848
1849 DEVACPI_UNLOCK(pDevIns, pThis);
1850 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1851 return rc;
1852}
1853
1854#endif /* IN_RING3 */
1855
1856/**
1857 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1858 *
1859 * @remarks The only I/O port currently implemented in all contexts.
1860 */
1861static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1862{
1863 RT_NOREF(offPort, pvUser);
1864 if (cb != 4)
1865 return VERR_IOM_IOPORT_UNUSED;
1866
1867 /*
1868 * We use the clock lock to serialize access to u64PmTimerInitial and to
1869 * make sure we get a reliable time from the clock
1870 * as well as and to prevent uPmTimerVal from being updated during read.
1871 */
1872 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1873 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1874 if (rc == VINF_SUCCESS)
1875 {
1876 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1877 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1878 *pu32 = pThis->uPmTimerVal;
1879
1880 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
1881
1882 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1883 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1884
1885#if 0
1886 /** @todo temporary: sanity check against running backwards */
1887 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1888 if (*pu32 - uOld >= 0x10000000)
1889 {
1890# if defined(IN_RING0)
1891 pThis->uPmTimeA = uOld;
1892 pThis->uPmTimeB = *pu32;
1893 return VERR_TM_TIMER_BAD_CLOCK;
1894# elif defined(IN_RING3)
1895 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1896# endif
1897 }
1898#endif
1899 }
1900 return rc;
1901}
1902
1903#ifdef IN_RING3
1904
1905/**
1906 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
1907 */
1908static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1909{
1910 RT_NOREF(offPort, pvUser);
1911 if (cb != 1)
1912 {
1913 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1914 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1915 }
1916
1917 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1918 DEVACPI_LOCK_R3(pDevIns, pThis);
1919
1920 *pu32 = pThis->gpe0_sts & 0xff;
1921
1922 DEVACPI_UNLOCK(pDevIns, pThis);
1923 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1924 return VINF_SUCCESS;
1925}
1926
1927/**
1928 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
1929 */
1930static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1931{
1932 RT_NOREF(offPort, pvUser);
1933 if (cb != 1)
1934 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1935
1936 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1937 DEVACPI_LOCK_R3(pDevIns, pThis);
1938
1939 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1940 u32 = pThis->gpe0_sts & ~u32;
1941 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1942
1943 DEVACPI_UNLOCK(pDevIns, pThis);
1944 return VINF_SUCCESS;
1945}
1946
1947/**
1948 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
1949 */
1950static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1951{
1952 RT_NOREF(offPort, pvUser);
1953 if (cb != 1)
1954 {
1955 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1956 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1957 }
1958
1959 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1960 DEVACPI_LOCK_R3(pDevIns, pThis);
1961
1962 *pu32 = pThis->gpe0_en & 0xff;
1963
1964 DEVACPI_UNLOCK(pDevIns, pThis);
1965 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1966 return VINF_SUCCESS;
1967}
1968
1969/**
1970 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
1971 */
1972static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1973{
1974 RT_NOREF(offPort, pvUser);
1975 if (cb != 1)
1976 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1977
1978 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1979 DEVACPI_LOCK_R3(pDevIns, pThis);
1980
1981 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1982 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
1983
1984 DEVACPI_UNLOCK(pDevIns, pThis);
1985 return VINF_SUCCESS;
1986}
1987
1988/**
1989 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
1990 */
1991static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1992{
1993 RT_NOREF(offPort, pvUser);
1994 Log(("acpiR3SmiWrite %#x\n", u32));
1995 if (cb != 1)
1996 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1997
1998 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1999 DEVACPI_LOCK_R3(pDevIns, pThis);
2000
2001 if (u32 == ACPI_ENABLE)
2002 pThis->pm1a_ctl |= SCI_EN;
2003 else if (u32 == ACPI_DISABLE)
2004 pThis->pm1a_ctl &= ~SCI_EN;
2005 else
2006 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2007
2008 DEVACPI_UNLOCK(pDevIns, pThis);
2009 return VINF_SUCCESS;
2010}
2011
2012/**
2013 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2014 */
2015static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2016{
2017 RT_NOREF(offPort, pvUser);
2018 Log(("acpiR3ResetWrite: %#x\n", u32));
2019 NOREF(pvUser);
2020 if (cb != 1)
2021 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2022
2023 /* No state locking required. */
2024 VBOXSTRICTRC rc;
2025 if (u32 == ACPI_RESET_REG_VAL)
2026 {
2027 LogRel(("ACPI: Reset initiated by ACPI\n"));
2028 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2029 }
2030 else
2031 {
2032 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2033 rc = VINF_SUCCESS;
2034 }
2035
2036 return rc;
2037}
2038
2039# ifdef DEBUG_ACPI
2040
2041/**
2042 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2043 */
2044static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2045{
2046 NOREF(pvUser);
2047 switch (cb)
2048 {
2049 case 1:
2050 Log(("%#x\n", u32 & 0xff));
2051 break;
2052 case 2:
2053 Log(("%#6x\n", u32 & 0xffff));
2054 break;
2055 case 4:
2056 Log(("%#10x\n", u32));
2057 break;
2058 default:
2059 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2060 }
2061 return VINF_SUCCESS;
2062}
2063
2064/**
2065 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2066 */
2067static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2068{
2069 NOREF(pvUser);
2070 switch (cb)
2071 {
2072 case 1:
2073 Log(("%c", u32 & 0xff));
2074 break;
2075 default:
2076 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2077 }
2078 return VINF_SUCCESS;
2079}
2080
2081# endif /* DEBUG_ACPI */
2082
2083/**
2084 * @callback_method_impl{FNDBGFHANDLERDEV}
2085 */
2086static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2087{
2088 RT_NOREF(pszArgs);
2089 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2090 pHlp->pfnPrintf(pHlp,
2091 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2092}
2093
2094/**
2095 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2096 *
2097 * @param pDevIns The PDM device instance.
2098 * @param pThis The ACPI shared instance data.
2099 */
2100static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2101{
2102 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2103 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2104 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2105 pPciDev->abConfig[PMBA + 2] = 0x00;
2106 pPciDev->abConfig[PMBA + 3] = 0x00;
2107}
2108
2109/**
2110 * Used to calculate the value of a PM I/O port.
2111 *
2112 * @returns The actual I/O port value.
2113 * @param pThis The ACPI shared instance data.
2114 * @param offset The offset into the I/O space, or -1 if invalid.
2115 */
2116static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2117{
2118 Assert(pThis->uPmIoPortBase != 0);
2119
2120 if (offset == -1)
2121 return 0;
2122
2123 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2124}
2125
2126/**
2127 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2128 * timer and GPE0 I/O ports.
2129 *
2130 * @returns VBox status code.
2131 * @param pDevIns The device instance.
2132 * @param pThis The ACPI shared instance data.
2133 */
2134static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2135{
2136 if (pThis->uPmIoPortBase == 0)
2137 return VINF_SUCCESS;
2138
2139 int rc;
2140 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2141 AssertRCReturn(rc, rc);
2142 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2143 AssertRCReturn(rc, rc);
2144 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2145 AssertRCReturn(rc, rc);
2146 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2147 AssertRCReturn(rc, rc);
2148 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2149 AssertRCReturn(rc, rc);
2150 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2151
2152 return VINF_SUCCESS;
2153}
2154
2155/**
2156 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2157 * timer and GPE0 I/O ports.
2158 *
2159 * @returns VBox status code.
2160 * @param pDevIns The device instance.
2161 * @param pThis The ACPI shared instance data.
2162 */
2163static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2164{
2165 if (pThis->uPmIoPortBase != 0)
2166 {
2167 int rc;
2168 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2169 AssertRCReturn(rc, rc);
2170 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2171 AssertRCReturn(rc, rc);
2172 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2173 AssertRCReturn(rc, rc);
2174 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2175 AssertRCReturn(rc, rc);
2176 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2177 AssertRCReturn(rc, rc);
2178 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2179 AssertRCReturn(rc, rc);
2180 }
2181 return VINF_SUCCESS;
2182}
2183
2184/**
2185 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2186 * PM1a, PM timer and GPE0 ports.
2187 *
2188 * @returns VBox status code.
2189 *
2190 * @param pDevIns The device instance.
2191 * @param pThis The ACPI shared instance data.
2192 * @param pThisCC The ACPI instance data for ring-3.
2193 * @param NewIoPortBase The new base address of the I/O ports.
2194 */
2195static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2196{
2197 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2198 if (NewIoPortBase != pThis->uPmIoPortBase)
2199 {
2200 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2201 if (RT_FAILURE(rc))
2202 return rc;
2203
2204 pThis->uPmIoPortBase = NewIoPortBase;
2205
2206 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2207 if (RT_FAILURE(rc))
2208 return rc;
2209
2210 /* We have to update FADT table acccording to the new base */
2211 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2212 AssertRC(rc);
2213 if (RT_FAILURE(rc))
2214 return rc;
2215 }
2216
2217 return VINF_SUCCESS;
2218}
2219
2220/**
2221 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2222 */
2223static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2224{
2225 RT_NOREF(pvUser);
2226 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2227
2228 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2229 uint8_t off = offPort & 0x000f;
2230 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2231 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2232 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2233
2234 DEVACPI_LOCK_R3(pDevIns, pThis);
2235 switch (off)
2236 {
2237 case SMBHSTSTS_OFF:
2238 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2239 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2240 break;
2241 case SMBSLVSTS_OFF:
2242 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2243 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2244 break;
2245 case SMBHSTCNT_OFF:
2246 {
2247 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2248
2249 const bool old_level = acpiSCILevel(pDevIns, pThis);
2250 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2251 if (u32 & SMBHSTCNT_START)
2252 {
2253 /* Start, trigger error as this is a dummy implementation */
2254 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2255 }
2256 if (u32 & SMBHSTCNT_KILL)
2257 {
2258 /* Kill */
2259 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2260 }
2261 const bool new_level = acpiSCILevel(pDevIns, pThis);
2262
2263 LogFunc(("old=%x new=%x\n", old_level, new_level));
2264
2265 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2266 * needs to be implemented later if it ever becomes relevant. */
2267 if (new_level != old_level)
2268 acpiSetIrq(pDevIns, new_level);
2269 break;
2270 }
2271 case SMBHSTCMD_OFF:
2272 pThis->u8SMBusHstCmd = u32;
2273 break;
2274 case SMBHSTADD_OFF:
2275 pThis->u8SMBusHstAdd = u32;
2276 break;
2277 case SMBHSTDAT0_OFF:
2278 pThis->u8SMBusHstDat0 = u32;
2279 break;
2280 case SMBHSTDAT1_OFF:
2281 pThis->u8SMBusHstDat1 = u32;
2282 break;
2283 case SMBBLKDAT_OFF:
2284 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2285 pThis->u8SMBusBlkIdx++;
2286 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2287 break;
2288 case SMBSLVCNT_OFF:
2289 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2290 break;
2291 case SMBSHDWCMD_OFF:
2292 /* readonly register */
2293 break;
2294 case SMBSLVEVT_OFF:
2295 pThis->u16SMBusSlvEvt = u32;
2296 break;
2297 case SMBSLVDAT_OFF:
2298 /* readonly register */
2299 break;
2300 default:
2301 /* caught by the sanity check above */
2302 ;
2303 }
2304
2305 DEVACPI_UNLOCK(pDevIns, pThis);
2306 return VINF_SUCCESS;
2307}
2308
2309/**
2310 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2311 */
2312static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2313{
2314 RT_NOREF(pvUser);
2315 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2316
2317 VBOXSTRICTRC rc = VINF_SUCCESS;
2318 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2319 uint8_t const off = offPort & 0x000f;
2320 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2321 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2322 return VERR_IOM_IOPORT_UNUSED;
2323
2324 DEVACPI_LOCK_R3(pDevIns, pThis);
2325 switch (off)
2326 {
2327 case SMBHSTSTS_OFF:
2328 *pu32 = pThis->u8SMBusHstSts;
2329 break;
2330 case SMBSLVSTS_OFF:
2331 *pu32 = pThis->u8SMBusSlvSts;
2332 break;
2333 case SMBHSTCNT_OFF:
2334 pThis->u8SMBusBlkIdx = 0;
2335 *pu32 = pThis->u8SMBusHstCnt;
2336 break;
2337 case SMBHSTCMD_OFF:
2338 *pu32 = pThis->u8SMBusHstCmd;
2339 break;
2340 case SMBHSTADD_OFF:
2341 *pu32 = pThis->u8SMBusHstAdd;
2342 break;
2343 case SMBHSTDAT0_OFF:
2344 *pu32 = pThis->u8SMBusHstDat0;
2345 break;
2346 case SMBHSTDAT1_OFF:
2347 *pu32 = pThis->u8SMBusHstDat1;
2348 break;
2349 case SMBBLKDAT_OFF:
2350 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2351 pThis->u8SMBusBlkIdx++;
2352 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2353 break;
2354 case SMBSLVCNT_OFF:
2355 *pu32 = pThis->u8SMBusSlvCnt;
2356 break;
2357 case SMBSHDWCMD_OFF:
2358 *pu32 = pThis->u8SMBusShdwCmd;
2359 break;
2360 case SMBSLVEVT_OFF:
2361 *pu32 = pThis->u16SMBusSlvEvt;
2362 break;
2363 case SMBSLVDAT_OFF:
2364 *pu32 = pThis->u16SMBusSlvDat;
2365 break;
2366 default:
2367 /* caught by the sanity check above */
2368 rc = VERR_IOM_IOPORT_UNUSED;
2369 }
2370 DEVACPI_UNLOCK(pDevIns, pThis);
2371
2372 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2373 return rc;
2374}
2375
2376/**
2377 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2378 *
2379 * @param pDevIns The PDM device instance.
2380 * @param pThis The ACPI shared instance data.
2381 */
2382static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2383{
2384 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2385 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2386 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2387 pPciDev->abConfig[SMBBA+2] = 0x00;
2388 pPciDev->abConfig[SMBBA+3] = 0x00;
2389 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2390 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2391 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2392 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2393 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2394}
2395
2396/**
2397 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2398 *
2399 * @param pThis The ACPI shared instance data.
2400 */
2401static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2402{
2403 pThis->u8SMBusHstSts = 0x00;
2404 pThis->u8SMBusSlvSts = 0x00;
2405 pThis->u8SMBusHstCnt = 0x00;
2406 pThis->u8SMBusHstCmd = 0x00;
2407 pThis->u8SMBusHstAdd = 0x00;
2408 pThis->u8SMBusHstDat0 = 0x00;
2409 pThis->u8SMBusHstDat1 = 0x00;
2410 pThis->u8SMBusSlvCnt = 0x00;
2411 pThis->u8SMBusShdwCmd = 0x00;
2412 pThis->u16SMBusSlvEvt = 0x0000;
2413 pThis->u16SMBusSlvDat = 0x0000;
2414 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2415 pThis->u8SMBusBlkIdx = 0;
2416}
2417
2418/**
2419 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2420 *
2421 * @returns VBox status code.
2422 * @param pDevIns The device instance.
2423 * @param pThis The ACPI shared instance data.
2424 */
2425static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2426{
2427 if (pThis->uSMBusIoPortBase != 0)
2428 {
2429 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2430 AssertRCReturn(rc, rc);
2431 }
2432 return VINF_SUCCESS;
2433}
2434
2435/**
2436 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2437 *
2438 * @returns VBox status code.
2439 * @param pDevIns The device instance.
2440 * @param pThis The ACPI shared instance data.
2441 */
2442static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2443{
2444 if (pThis->uSMBusIoPortBase != 0)
2445 {
2446 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2447 AssertRCReturn(rc, rc);
2448 }
2449 return VINF_SUCCESS;
2450}
2451
2452/**
2453 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2454 * SMBus ports.
2455 *
2456 * @returns VBox status code.
2457 *
2458 * @param pDevIns The device instance.
2459 * @param pThis The ACPI shared instance data.
2460 * @param NewIoPortBase The new base address of the I/O ports.
2461 */
2462static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2463{
2464 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2465 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2466 {
2467 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2468 AssertRCReturn(rc, rc);
2469
2470 pThis->uSMBusIoPortBase = NewIoPortBase;
2471
2472 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2473 AssertRCReturn(rc, rc);
2474
2475#if 0 /* is there an FADT table entry for the SMBus base? */
2476 /* We have to update FADT table acccording to the new base */
2477 rc = acpiR3PlantTables(pThis);
2478 AssertRC(rc);
2479 if (RT_FAILURE(rc))
2480 return rc;
2481#endif
2482 }
2483
2484 return VINF_SUCCESS;
2485}
2486
2487
2488/**
2489 * Saved state structure description, version 4.
2490 */
2491static const SSMFIELD g_AcpiSavedStateFields4[] =
2492{
2493 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2494 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2495 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2496 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2497 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2498 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2499 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2500 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2501 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2502 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2503 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2504 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2505 SSMFIELD_ENTRY_TERM()
2506};
2507
2508/**
2509 * Saved state structure description, version 5.
2510 */
2511static const SSMFIELD g_AcpiSavedStateFields5[] =
2512{
2513 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2514 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2515 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2516 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2517 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2518 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2519 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2520 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2521 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2522 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2523 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2524 SSMFIELD_ENTRY_TERM()
2525};
2526
2527/**
2528 * Saved state structure description, version 6.
2529 */
2530static const SSMFIELD g_AcpiSavedStateFields6[] =
2531{
2532 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2533 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2534 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2535 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2536 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2537 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2538 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2539 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2540 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2541 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2542 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2543 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2544 SSMFIELD_ENTRY_TERM()
2545};
2546
2547/**
2548 * Saved state structure description, version 7.
2549 */
2550static const SSMFIELD g_AcpiSavedStateFields7[] =
2551{
2552 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2553 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2554 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2555 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2556 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2557 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2558 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2559 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2560 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2561 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2562 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2563 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2564 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2565 SSMFIELD_ENTRY_TERM()
2566};
2567
2568/**
2569 * Saved state structure description, version 8.
2570 */
2571static const SSMFIELD g_AcpiSavedStateFields8[] =
2572{
2573 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2574 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2575 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2576 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2577 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2578 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2579 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2580 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2581 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2582 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2583 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2584 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2585 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2586 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2587 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2588 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2589 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2590 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2591 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2592 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2593 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2594 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2595 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2596 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2597 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2598 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2599 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2600 SSMFIELD_ENTRY_TERM()
2601};
2602
2603/**
2604 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2605 */
2606static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2607{
2608 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2609 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2610 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2611}
2612
2613/**
2614 * @callback_method_impl{FNSSMDEVLOADEXEC}
2615 */
2616static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2617{
2618 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2619 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2620 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2621 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2622
2623 /*
2624 * Unmap PM I/O ports, will remap it with the actual base after state
2625 * successfully loaded.
2626 */
2627 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2628 AssertRCReturn(rc, rc);
2629
2630 /*
2631 * Unregister SMBus handlers, will register with actual base after state
2632 * successfully loaded.
2633 */
2634 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2635 AssertRCReturn(rc, rc);
2636 acpiR3SMBusResetDevice(pThis);
2637
2638 switch (uVersion)
2639 {
2640 case 4:
2641 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2642 break;
2643 case 5:
2644 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2645 break;
2646 case 6:
2647 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2648 break;
2649 case 7:
2650 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2651 break;
2652 case 8:
2653 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2654 break;
2655 default:
2656 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2657 break;
2658 }
2659 if (RT_SUCCESS(rc))
2660 {
2661 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2662 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2663 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2664 AssertRCReturn(rc, rc);
2665 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2666 AssertRCReturn(rc, rc);
2667 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2668 AssertRCReturn(rc, rc);
2669 rc = acpiR3FetchBatteryInfo(pThis);
2670 AssertRCReturn(rc, rc);
2671
2672 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2673 DEVACPI_LOCK_R3(pDevIns, pThis);
2674 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2675 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2676 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2677 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2678 DEVACPI_UNLOCK(pDevIns, pThis);
2679 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2680 }
2681 return rc;
2682}
2683
2684/**
2685 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2686 */
2687static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2688{
2689 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2690 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2691 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2692 return NULL;
2693}
2694
2695/**
2696 * Calculate the check sum for some ACPI data before planting it.
2697 *
2698 * All the bytes must add up to 0.
2699 *
2700 * @returns check sum.
2701 * @param pvSrc What to check sum.
2702 * @param cbData The amount of data to checksum.
2703 */
2704static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2705{
2706 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2707 uint8_t uSum = 0;
2708 for (size_t i = 0; i < cbData; ++i)
2709 uSum += pbSrc[i];
2710 return -uSum;
2711}
2712
2713/**
2714 * Prepare a ACPI table header.
2715 */
2716static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2717 const char au8Signature[4],
2718 uint32_t u32Length, uint8_t u8Revision)
2719{
2720 memcpy(header->au8Signature, au8Signature, 4);
2721 header->u32Length = RT_H2LE_U32(u32Length);
2722 header->u8Revision = u8Revision;
2723 memcpy(header->au8OemId, pThis->au8OemId, 6);
2724 memcpy(header->au8OemTabId, "VBOX", 4);
2725 memcpy(header->au8OemTabId+4, au8Signature, 4);
2726 header->u32OemRevision = RT_H2LE_U32(1);
2727 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2728 header->u32CreatorRev = pThis->u32CreatorRev;
2729}
2730
2731/**
2732 * Initialize a generic address structure (ACPIGENADDR).
2733 */
2734static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2735 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2736 uint8_t u8AccessSize, uint64_t u64Address)
2737{
2738 g->u8AddressSpaceId = u8AddressSpaceId;
2739 g->u8RegisterBitWidth = u8RegisterBitWidth;
2740 g->u8RegisterBitOffset = u8RegisterBitOffset;
2741 g->u8AccessSize = u8AccessSize;
2742 g->u64Address = RT_H2LE_U64(u64Address);
2743}
2744
2745/**
2746 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2747 */
2748DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2749{
2750 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2751}
2752
2753/**
2754 * Plant the Differentiated System Description Table (DSDT).
2755 */
2756static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2757{
2758 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2759}
2760
2761/**
2762 * Plant the Secondary System Description Table (SSDT).
2763 */
2764static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2765{
2766 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2767}
2768
2769/**
2770 * Plant the Firmware ACPI Control Structure (FACS).
2771 */
2772static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2773{
2774 ACPITBLFACS facs;
2775
2776 memset(&facs, 0, sizeof(facs));
2777 memcpy(facs.au8Signature, "FACS", 4);
2778 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2779 facs.u32HWSignature = RT_H2LE_U32(0);
2780 facs.u32FWVector = RT_H2LE_U32(0);
2781 facs.u32GlobalLock = RT_H2LE_U32(0);
2782 facs.u32Flags = RT_H2LE_U32(0);
2783 facs.u64X_FWVector = RT_H2LE_U64(0);
2784 facs.u8Version = 1;
2785
2786 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2787}
2788
2789/**
2790 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2791 */
2792static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2793 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2794{
2795 ACPITBLFADT fadt;
2796
2797 /* First the ACPI version 2+ version of the structure. */
2798 memset(&fadt, 0, sizeof(fadt));
2799 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2800 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2801 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2802 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2803 fadt.u8PreferredPMProfile = 0; /* unspecified */
2804 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2805 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2806 fadt.u8AcpiEnable = ACPI_ENABLE;
2807 fadt.u8AcpiDisable = ACPI_DISABLE;
2808 fadt.u8S4BIOSReq = 0;
2809 fadt.u8PStateCnt = 0;
2810 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2811 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2812 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2813 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2814 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2815 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2816 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2817 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2818 fadt.u8PM1EVTLEN = 4;
2819 fadt.u8PM1CTLLEN = 2;
2820 fadt.u8PM2CTLLEN = 0;
2821 fadt.u8PMTMLEN = 4;
2822 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2823 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2824 fadt.u8GPE1BASE = GPE1_BASE;
2825 fadt.u8CSTCNT = 0;
2826 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2827 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2828 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2829 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2830 fadt.u8DutyOffset = 0;
2831 fadt.u8DutyWidth = 0;
2832 fadt.u8DayAlarm = 0;
2833 fadt.u8MonAlarm = 0;
2834 fadt.u8Century = 0;
2835 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2836 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2837 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2838 | FADT_FL_FIX_RTC
2839 | FADT_FL_TMR_VAL_EXT
2840 | FADT_FL_RESET_REG_SUP);
2841
2842 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2843 if (pThis->fCpuHotPlug)
2844 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2845
2846 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2847 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2848 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2849 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2850 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2851 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2852 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2853 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2854 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2855 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2856 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2857 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2858 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2859 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2860
2861 /* Now the ACPI 1.0 version. */
2862 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2863 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2864 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2865 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2866 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2867}
2868
2869/**
2870 * Plant the root System Description Table.
2871 *
2872 * The RSDT and XSDT tables are basically identical. The only difference is 32
2873 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2874 * ACPI 2.0 and up.
2875 */
2876static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2877{
2878 ACPITBLRSDT *rsdt;
2879 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2880
2881 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2882 if (!rsdt)
2883 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2884
2885 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2886 for (unsigned int i = 0; i < nb_entries; ++i)
2887 {
2888 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2889 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2890 }
2891 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2892 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2893 RTMemFree(rsdt);
2894 return VINF_SUCCESS;
2895}
2896
2897/**
2898 * Plant the Extended System Description Table.
2899 */
2900static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2901{
2902 ACPITBLXSDT *xsdt;
2903 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2904 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
2905 if (!xsdt)
2906 return VERR_NO_TMP_MEMORY;
2907
2908 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
2909
2910 if (pThis->cCustTbls > 0)
2911 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2912
2913 for (unsigned int i = 0; i < nb_entries; ++i)
2914 {
2915 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2916 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2917 }
2918 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
2919 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
2920
2921 RTMemFree(xsdt);
2922 return VINF_SUCCESS;
2923}
2924
2925/**
2926 * Plant the Root System Description Pointer (RSDP).
2927 */
2928static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2929{
2930 memset(rsdp, 0, sizeof(*rsdp));
2931
2932 /* ACPI 1.0 part (RSDT) */
2933 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2934 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2935 rsdp->u8Revision = ACPI_REVISION;
2936 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2937 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2938
2939 /* ACPI 2.0 part (XSDT) */
2940 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2941 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2942 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2943}
2944
2945/**
2946 * Multiple APIC Description Table.
2947 *
2948 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2949 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2950 * use regular C structure and proxy to raw memory instead.
2951 */
2952class AcpiTableMadt
2953{
2954 /**
2955 * All actual data stored in dynamically allocated memory pointed by this field.
2956 */
2957 uint8_t *m_pbData;
2958 /**
2959 * Number of CPU entries in this MADT.
2960 */
2961 uint32_t m_cCpus;
2962
2963 /**
2964 * Number of interrupt overrides.
2965 */
2966 uint32_t m_cIsos;
2967
2968public:
2969 /**
2970 * Address of ACPI header
2971 */
2972 inline ACPITBLHEADER *header_addr(void) const
2973 {
2974 return (ACPITBLHEADER *)m_pbData;
2975 }
2976
2977 /**
2978 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2979 * although address is the same for all of them.
2980 */
2981 inline uint32_t *u32LAPIC_addr(void) const
2982 {
2983 return (uint32_t *)(header_addr() + 1);
2984 }
2985
2986 /**
2987 * Address of APIC flags
2988 */
2989 inline uint32_t *u32Flags_addr(void) const
2990 {
2991 return (uint32_t *)(u32LAPIC_addr() + 1);
2992 }
2993
2994 /**
2995 * Address of ISO description
2996 */
2997 inline ACPITBLISO *ISO_addr(void) const
2998 {
2999 return (ACPITBLISO *)(u32Flags_addr() + 1);
3000 }
3001
3002 /**
3003 * Address of per-CPU LAPIC descriptions
3004 */
3005 inline ACPITBLLAPIC *LApics_addr(void) const
3006 {
3007 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3008 }
3009
3010 /**
3011 * Address of IO APIC description
3012 */
3013 inline ACPITBLIOAPIC *IOApic_addr(void) const
3014 {
3015 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3016 }
3017
3018 /**
3019 * Size of MADT.
3020 * Note that this function assumes IOApic to be the last field in structure.
3021 */
3022 inline uint32_t size(void) const
3023 {
3024 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3025 }
3026
3027 /**
3028 * Raw data of MADT.
3029 */
3030 inline const uint8_t *data(void) const
3031 {
3032 return m_pbData;
3033 }
3034
3035 /**
3036 * Size of MADT for given ACPI config, useful to compute layout.
3037 */
3038 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3039 {
3040 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3041 }
3042
3043 /*
3044 * Constructor, only works in Ring 3, doesn't look like a big deal.
3045 */
3046 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3047 {
3048 m_cCpus = cCpus;
3049 m_cIsos = cIsos;
3050 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3051 uint32_t cb = size();
3052 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3053 }
3054
3055 ~AcpiTableMadt()
3056 {
3057 RTMemFree(m_pbData);
3058 }
3059};
3060
3061
3062/**
3063 * Plant the Multiple APIC Description Table (MADT).
3064 *
3065 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3066 *
3067 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3068 */
3069static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3070{
3071 uint16_t cpus = pThis->cCpus;
3072 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3073
3074 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3075
3076 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3077 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3078
3079 /* LAPICs records */
3080 ACPITBLLAPIC* lapic = madt.LApics_addr();
3081 for (uint16_t i = 0; i < cpus; i++)
3082 {
3083 lapic->u8Type = 0;
3084 lapic->u8Length = sizeof(ACPITBLLAPIC);
3085 lapic->u8ProcId = i;
3086 /** Must match numbering convention in MPTABLES */
3087 lapic->u8ApicId = i;
3088 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3089 lapic++;
3090 }
3091
3092 /* IO-APIC record */
3093 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3094 ioapic->u8Type = 1;
3095 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3096 /** Must match MP tables ID */
3097 ioapic->u8IOApicId = cpus;
3098 ioapic->u8Reserved = 0;
3099 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3100 ioapic->u32GSIB = RT_H2LE_U32(0);
3101
3102 /* Interrupt Source Overrides */
3103 /* Flags:
3104 bits[3:2]:
3105 00 conforms to the bus
3106 01 edge-triggered
3107 10 reserved
3108 11 level-triggered
3109 bits[1:0]
3110 00 conforms to the bus
3111 01 active-high
3112 10 reserved
3113 11 active-low */
3114 /* If changing, also update PDMIsaSetIrq() and MPS */
3115 ACPITBLISO* isos = madt.ISO_addr();
3116 /* Timer interrupt rule IRQ0 to GSI2 */
3117 isos[0].u8Type = 2;
3118 isos[0].u8Length = sizeof(ACPITBLISO);
3119 isos[0].u8Bus = 0; /* Must be 0 */
3120 isos[0].u8Source = 0; /* IRQ0 */
3121 isos[0].u32GSI = 2; /* connected to pin 2 */
3122 isos[0].u16Flags = 0; /* conform to the bus */
3123
3124 /* ACPI interrupt rule - IRQ9 to GSI9 */
3125 isos[1].u8Type = 2;
3126 isos[1].u8Length = sizeof(ACPITBLISO);
3127 isos[1].u8Bus = 0; /* Must be 0 */
3128 isos[1].u8Source = 9; /* IRQ9 */
3129 isos[1].u32GSI = 9; /* connected to pin 9 */
3130 isos[1].u16Flags = 0xf; /* active low, level triggered */
3131 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3132
3133 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3134 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3135}
3136
3137/**
3138 * Plant the High Performance Event Timer (HPET) descriptor.
3139 */
3140static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3141{
3142 ACPITBLHPET hpet;
3143
3144 memset(&hpet, 0, sizeof(hpet));
3145
3146 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3147 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3148 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3149 0 /* Memory address space */,
3150 64 /* Register bit width */,
3151 0 /* Bit offset */,
3152 0, /* Register access size, is it correct? */
3153 0xfed00000 /* Address */);
3154
3155 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3156 hpet.u32Number = 0;
3157 hpet.u32MinTick = 4096;
3158 hpet.u8Attributes = 0;
3159
3160 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3161
3162 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3163}
3164
3165
3166#ifdef VBOX_WITH_IOMMU_AMD
3167/**
3168 * Plant the AMD IOMMU descriptor.
3169 */
3170static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3171{
3172 ACPITBLIOMMU Ivrs;
3173 RT_ZERO(Ivrs);
3174
3175 uint16_t const uIommuBus = 0;
3176 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuAmdPciAddress);
3177 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuAmdPciAddress);
3178
3179 /* IVRS header. */
3180 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3181 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3182 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3183 | RT_BF_MAKE(ACPI_IVINFO_BF_DMA_REMAP_SUP, 0) /* Pre-boot DMA remap support not supported. */
3184 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3185 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3186 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64) /* Virt. Addr size (64 bits) */
3187 | RT_BF_MAKE(ACPI_IVINFO_BF_HT_ATS_RESV, 0); /* ATS response range reserved (only applicable for HT) */
3188
3189 /* IVHD type 10 definition block. */
3190 Ivrs.IvhdType10.u8Type = 0x10;
3191 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3192 + sizeof(Ivrs.IvhdType10Start)
3193 + sizeof(Ivrs.IvhdType10End)
3194 + sizeof(Ivrs.IvhdType10Rsvd0)
3195 + sizeof(Ivrs.IvhdType10Rsvd1)
3196 + sizeof(Ivrs.IvhdType10IoApic)
3197 + sizeof(Ivrs.IvhdType10Hpet);
3198 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3199 Ivrs.IvhdType10.u16CapOffset = IOMMU_PCI_OFF_CAP_HDR;
3200 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR;
3201 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3202 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3203 Ivrs.IvhdType10.u8Flags = ACPI_IVHD_10H_F_COHERENT; /* Remote IOTLB etc. not supported. */
3204 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3205 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3206 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3207 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3208 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3209 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3210 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3211 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3212 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3213 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3214 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3215 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3216 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3217 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3218 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3219 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3);
3220 /* Start range from BDF (00:01:00). */
3221 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3222 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3223 Ivrs.IvhdType10Start.u8DteSetting = 0;
3224 /* End range at BDF (ff:1f:7). */
3225 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3226 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3227 Ivrs.IvhdType10End.u8DteSetting = 0;
3228
3229 /* Southbridge I/O APIC special device entry. */
3230 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3231 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3232 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3233 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3234 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3235 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3236 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3237 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3238 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3239 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3240
3241 /* HPET special device entry. */
3242 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3243 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3244 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3245 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3246 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3247 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3248
3249 /* IVHD type 11 definition block. */
3250 Ivrs.IvhdType11.u8Type = 0x11;
3251 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3252 + sizeof(Ivrs.IvhdType11Start)
3253 + sizeof(Ivrs.IvhdType11End)
3254 + sizeof(Ivrs.IvhdType11Rsvd0)
3255 + sizeof(Ivrs.IvhdType11Rsvd1)
3256 + sizeof(Ivrs.IvhdType11IoApic)
3257 + sizeof(Ivrs.IvhdType11Hpet);
3258 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3259 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3260 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3261 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3262 Ivrs.IvhdType11.u8Flags = ACPI_IVHD_11H_F_COHERENT;
3263 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3264 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3265 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3266 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3267 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3268 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3269 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3270 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3271 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3272 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3273 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 1)
3274 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3275 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3276 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3277 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3)
3278 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3279 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3280 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3281 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3282 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3283 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3284 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3285 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3286 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3287 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS)
3288 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3289 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3290 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3291 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3292 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3293 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3294 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3295 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3296 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3297 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3298 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3299 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3300 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3301 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3302
3303 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3304 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3305 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3306 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3307 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3308 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3309 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3310
3311 /* Finally, Compute checksum. */
3312 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3313
3314 /* Plant the ACPI table. */
3315 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3316}
3317#endif
3318
3319
3320/**
3321 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3322 * descriptor.
3323 *
3324 * @param pDevIns The device instance.
3325 * @param pThis The ACPI shared instance data.
3326 * @param GCPhysDst Where to plant it.
3327 */
3328static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3329{
3330 struct
3331 {
3332 ACPITBLMCFG hdr;
3333 ACPITBLMCFGENTRY entry;
3334 } tbl;
3335 uint8_t u8StartBus = 0;
3336 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3337
3338 RT_ZERO(tbl);
3339
3340 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3341 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3342 tbl.entry.u8StartBus = u8StartBus;
3343 tbl.entry.u8EndBus = u8EndBus;
3344 // u16PciSegmentGroup must match _SEG in ACPI table
3345
3346 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3347
3348 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3349}
3350
3351/**
3352 * Used by acpiR3PlantTables and acpiConstruct.
3353 *
3354 * @returns Guest memory address.
3355 */
3356static uint32_t apicR3FindRsdpSpace(void)
3357{
3358 return 0xe0000;
3359}
3360
3361/**
3362 * Called by acpiR3Construct to read and allocate a custom ACPI table
3363 *
3364 * @param pDevIns The device instance.
3365 * @param ppu8CustBin Address to receive the address of the table
3366 * @param pcbCustBin Address to receive the size of the the table.
3367 * @param pszCustBinFile
3368 * @param cbBufAvail Maximum space in bytes available for the custom
3369 * table (including header).
3370 */
3371static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3372 char *pszCustBinFile, uint32_t cbBufAvail)
3373{
3374 RTFILE FileCUSTBin;
3375 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3376 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3377 if (RT_SUCCESS(rc))
3378 {
3379 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3380 if (RT_SUCCESS(rc))
3381 {
3382 /* The following checks should be in sync the AssertReleaseMsg's below. */
3383 if ( *pcbCustBin > cbBufAvail
3384 || *pcbCustBin < sizeof(ACPITBLHEADER))
3385 rc = VERR_TOO_MUCH_DATA;
3386
3387 /*
3388 * Allocate buffer for the custom table binary data.
3389 */
3390 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3391 if (*ppu8CustBin)
3392 {
3393 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3394 if (RT_FAILURE(rc))
3395 {
3396 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3397 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3398 *ppu8CustBin = NULL;
3399 }
3400 }
3401 else
3402 {
3403 rc = VERR_NO_MEMORY;
3404 }
3405 RTFileClose(FileCUSTBin);
3406 }
3407 }
3408 return rc;
3409}
3410
3411/**
3412 * Create the ACPI tables in guest memory.
3413 */
3414static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3415{
3416 int rc;
3417 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3418 RTGCPHYS32 GCPhysHpet = 0;
3419#ifdef VBOX_WITH_IOMMU_AMD
3420 RTGCPHYS32 GCPhysIommuAmd = 0;
3421#endif
3422 RTGCPHYS32 GCPhysApic = 0;
3423 RTGCPHYS32 GCPhysSsdt = 0;
3424 RTGCPHYS32 GCPhysMcfg = 0;
3425 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3426 uint32_t addend = 0;
3427#ifdef VBOX_WITH_IOMMU_AMD
3428 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3429 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3430#else
3431 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3432 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3433#endif
3434 uint32_t cAddr;
3435 uint32_t iMadt = 0;
3436 uint32_t iHpet = 0;
3437#ifdef VBOX_WITH_IOMMU_AMD
3438 uint32_t iIommuAmd = 0;
3439#endif
3440 uint32_t iSsdt = 0;
3441 uint32_t iMcfg = 0;
3442 uint32_t iCust = 0;
3443 size_t cbRsdt = sizeof(ACPITBLHEADER);
3444 size_t cbXsdt = sizeof(ACPITBLHEADER);
3445
3446 cAddr = 1; /* FADT */
3447 if (pThis->u8UseIOApic)
3448 iMadt = cAddr++; /* MADT */
3449
3450 if (pThis->fUseHpet)
3451 iHpet = cAddr++; /* HPET */
3452
3453#ifdef VBOX_WITH_IOMMU_AMD
3454 if (pThis->u32IommuAmdPciAddress)
3455 iIommuAmd = cAddr++; /* IOMMU (AMD) */
3456#endif
3457
3458 if (pThis->fUseMcfg)
3459 iMcfg = cAddr++; /* MCFG */
3460
3461 if (pThis->cCustTbls > 0)
3462 {
3463 iCust = cAddr; /* CUST */
3464 cAddr += pThis->cCustTbls;
3465 }
3466
3467 iSsdt = cAddr++; /* SSDT */
3468
3469 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3470 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3471
3472 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3473 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3474
3475 /*
3476 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3477 * The latter starts never below 4G.
3478 */
3479 PVM pVM = PDMDevHlpGetVM(pDevIns);
3480 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3481 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3482
3483 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3484 if (pThis->fPciPref64Enabled)
3485 {
3486 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3487 if (pThis->u64PciPref64Max > u64PciPref64Min)
3488 {
3489 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3490 pThis->u64PciPref64Min = u64PciPref64Min;
3491 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3492 u64PciPref64Min, pThis->u64PciPref64Max-1));
3493 }
3494 else
3495 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3496 u64PciPref64Min, pThis->u64PciPref64Max-1));
3497 }
3498 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3499 {
3500 /* Note: This is also enforced by DevPcBios.cpp. */
3501 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3502 cbBelow4GB = UINT32_C(0xfe000000);
3503 }
3504 pThis->cbRamLow = cbBelow4GB;
3505
3506 GCPhysCur = 0;
3507 GCPhysRsdt = GCPhysCur;
3508
3509 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3510 GCPhysXsdt = GCPhysCur;
3511
3512 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3513 GCPhysFadtAcpi1 = GCPhysCur;
3514
3515 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3516 GCPhysFadtAcpi2 = GCPhysCur;
3517
3518 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3519 GCPhysFacs = GCPhysCur;
3520
3521 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3522 if (pThis->u8UseIOApic)
3523 {
3524 GCPhysApic = GCPhysCur;
3525 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3526 }
3527 if (pThis->fUseHpet)
3528 {
3529 GCPhysHpet = GCPhysCur;
3530 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3531 }
3532#ifdef VBOX_WITH_IOMMU_AMD
3533 if (pThis->u32IommuAmdPciAddress)
3534 {
3535 GCPhysIommuAmd = GCPhysCur;
3536 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3537 }
3538#endif
3539 if (pThis->fUseMcfg)
3540 {
3541 GCPhysMcfg = GCPhysCur;
3542 /* Assume one entry */
3543 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3544 }
3545
3546 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3547 {
3548 aGCPhysCust[i] = GCPhysCur;
3549 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3550 }
3551
3552 void *pvSsdtCode = NULL;
3553 size_t cbSsdt = 0;
3554 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3555 if (RT_FAILURE(rc))
3556 return rc;
3557
3558 GCPhysSsdt = GCPhysCur;
3559 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3560
3561 GCPhysDsdt = GCPhysCur;
3562
3563 void *pvDsdtCode = NULL;
3564 size_t cbDsdt = 0;
3565 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3566 if (RT_FAILURE(rc))
3567 return rc;
3568
3569 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3570
3571 if (GCPhysCur > 0x10000)
3572 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3573 N_("Error: ACPI tables bigger than 64KB"));
3574
3575 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3576 addend = pThis->cbRamLow - 0x10000;
3577 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3578 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3579 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3580 if (pThis->u8UseIOApic)
3581 Log((" MADT 0x%08X", GCPhysApic + addend));
3582 if (pThis->fUseHpet)
3583 Log((" HPET 0x%08X", GCPhysHpet + addend));
3584 if (pThis->fUseMcfg)
3585 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3586 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3587 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3588 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3589 Log(("\n"));
3590
3591 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3592 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3593 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3594 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3595 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3596
3597 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3598 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3599 if (pThis->u8UseIOApic)
3600 {
3601 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3602 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3603 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3604 }
3605 if (pThis->fUseHpet)
3606 {
3607 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3608 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3609 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3610 }
3611#ifdef VBOX_WITH_IOMMU_AMD
3612 if (pThis->u32IommuAmdPciAddress)
3613 {
3614 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommuAmd + addend);
3615 aGCPhysRsdt[iIommuAmd] = GCPhysIommuAmd + addend;
3616 aGCPhysXsdt[iIommuAmd] = GCPhysIommuAmd + addend;
3617 }
3618#endif
3619 if (pThis->fUseMcfg)
3620 {
3621 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3622 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3623 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3624 }
3625 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3626 {
3627 Assert(i < MAX_CUST_TABLES);
3628 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3629 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3630 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3631 uint8_t* pSig = pThisCC->apu8CustBin[i];
3632 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3633 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3634 }
3635
3636 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3637 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3638 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3639 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3640
3641 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3642 if (RT_FAILURE(rc))
3643 return rc;
3644 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3645}
3646
3647/**
3648 * @callback_method_impl{FNPCICONFIGREAD}
3649 */
3650static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3651 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3652{
3653 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3654 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3655 return rcStrict;
3656}
3657
3658/**
3659 * @callback_method_impl{FNPCICONFIGWRITE}
3660 */
3661static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3662 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3663{
3664 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3665 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3666
3667 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3668 DEVACPI_LOCK_R3(pDevIns, pThis);
3669
3670 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3671 {
3672 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3673 u32Value = SCI_INT;
3674 }
3675
3676 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3677
3678 /* Assume that the base address is only changed when the corresponding
3679 * hardware functionality is disabled. The IO region is mapped when the
3680 * functionality is enabled by the guest. */
3681
3682 if (uAddress == PMREGMISC)
3683 {
3684 RTIOPORT NewIoPortBase = 0;
3685 /* Check Power Management IO Space Enable (PMIOSE) bit */
3686 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3687 {
3688 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3689 NewIoPortBase &= 0xffc0;
3690 }
3691
3692 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
3693 AssertRC(rc);
3694 }
3695
3696 if (uAddress == SMBHSTCFG)
3697 {
3698 RTIOPORT NewIoPortBase = 0;
3699 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3700 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3701 {
3702 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3703 NewIoPortBase &= 0xfff0;
3704 }
3705
3706 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3707 AssertRC(rc);
3708 }
3709
3710 DEVACPI_UNLOCK(pDevIns, pThis);
3711 return rcStrict;
3712}
3713
3714/**
3715 * Attach a new CPU.
3716 *
3717 * @returns VBox status code.
3718 * @param pDevIns The device instance.
3719 * @param iLUN The logical unit which is being attached.
3720 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3721 *
3722 * @remarks This code path is not used during construction.
3723 */
3724static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3725{
3726 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3727 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3728 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3729
3730 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3731 ("Hot-plug flag is not set\n"),
3732 VERR_NOT_SUPPORTED);
3733 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3734
3735 /* Check if it was already attached */
3736 int rc = VINF_SUCCESS;
3737 DEVACPI_LOCK_R3(pDevIns, pThis);
3738 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3739 {
3740 PPDMIBASE IBaseTmp;
3741 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3742 if (RT_SUCCESS(rc))
3743 {
3744 /* Enable the CPU */
3745 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3746
3747 /*
3748 * Lock the CPU because we don't know if the guest will use it or not.
3749 * Prevents ejection while the CPU is still used
3750 */
3751 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3752 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3753 pThis->u32CpuEvent = iLUN;
3754
3755 /* Notify the guest */
3756 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3757 }
3758 }
3759 DEVACPI_UNLOCK(pDevIns, pThis);
3760 return rc;
3761}
3762
3763/**
3764 * Detach notification.
3765 *
3766 * @param pDevIns The device instance.
3767 * @param iLUN The logical unit which is being detached.
3768 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3769 */
3770static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3771{
3772 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3773
3774 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3775
3776 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3777 ("Hot-plug flag is not set\n"));
3778
3779 /* Check if it was already detached */
3780 DEVACPI_LOCK_R3(pDevIns, pThis);
3781 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3782 {
3783 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3784 {
3785 /* Disable the CPU */
3786 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3787 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3788 pThis->u32CpuEvent = iLUN;
3789
3790 /* Notify the guest */
3791 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3792 }
3793 else
3794 AssertMsgFailed(("CPU is still locked by the guest\n"));
3795 }
3796 DEVACPI_UNLOCK(pDevIns, pThis);
3797}
3798
3799/**
3800 * @interface_method_impl{PDMDEVREG,pfnResume}
3801 */
3802static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3803{
3804 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3805 if (pThis->fSetWakeupOnResume)
3806 {
3807 Log(("acpiResume: setting WAK_STS\n"));
3808 pThis->fSetWakeupOnResume = false;
3809 pThis->pm1a_sts |= WAK_STS;
3810 }
3811}
3812
3813/**
3814 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3815 */
3816static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3817{
3818 RT_NOREF(enmCtx);
3819 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3820 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3821 acpiR3PlantTables(pDevIns, pThis, pThisCC);
3822}
3823
3824/**
3825 * @interface_method_impl{PDMDEVREG,pfnReset}
3826 */
3827static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3828{
3829 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3830 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3831
3832 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3833 acpiSetIrq(pDevIns, 0);
3834
3835 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3836 pThis->pm1a_en = 0;
3837 pThis->pm1a_sts = 0;
3838 pThis->pm1a_ctl = 0;
3839 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3840 pThis->uPmTimerVal = 0;
3841 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3842 pThis->uPmTimeOld = pThis->uPmTimerVal;
3843 pThis->uBatteryIndex = 0;
3844 pThis->uSystemInfoIndex = 0;
3845 pThis->gpe0_en = 0;
3846 pThis->gpe0_sts = 0;
3847 pThis->uSleepState = 0;
3848 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
3849
3850 /* Real device behavior is resetting only the PM controller state,
3851 * but we're additionally doing the job of the BIOS. */
3852 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
3853 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3854
3855 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3856 * state. Real device behavior is only the SMBus controller state reset,
3857 * but we're additionally doing the job of the BIOS. */
3858 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3859 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3860 acpiR3SMBusResetDevice(pThis);
3861}
3862
3863/**
3864 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3865 */
3866static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3867{
3868 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3869 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3870 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3871
3872 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3873 {
3874 if (pThisCC->apu8CustBin[i])
3875 {
3876 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
3877 pThisCC->apu8CustBin[i] = NULL;
3878 }
3879 }
3880 return VINF_SUCCESS;
3881}
3882
3883/**
3884 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3885 */
3886static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3887{
3888 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3889 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3890 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3891 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3892
3893 /*
3894 * Init data and set defaults.
3895 */
3896 /** @todo move more of the code up! */
3897
3898 pThisCC->pDevIns = pDevIns;
3899 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3900 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3901 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3902 pThis->u32CpuEventType = 0;
3903 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3904
3905 /* The first CPU can't be attached/detached */
3906 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3907 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3908
3909 /* IBase */
3910 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
3911 /* IACPIPort */
3912 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3913 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3914 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3915 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3916 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3917 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3918 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3919
3920 /*
3921 * Set the default critical section to NOP (related to the PM timer).
3922 */
3923 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3924 AssertRCReturn(rc, rc);
3925
3926 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3927 AssertRCReturn(rc, rc);
3928
3929 /*
3930 * Validate and read the configuration.
3931 */
3932 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
3933 "IOAPIC"
3934 "|NumCPUs"
3935 "|HpetEnabled"
3936 "|McfgEnabled"
3937 "|McfgBase"
3938 "|McfgLength"
3939 "|PciPref64Enabled"
3940 "|PciPref64LimitGB"
3941 "|SmcEnabled"
3942 "|FdcEnabled"
3943 "|ShowRtc"
3944 "|ShowCpu"
3945 "|NicPciAddress"
3946 "|AudioPciAddress"
3947 "|NvmePciAddress"
3948 "|IocPciAddress"
3949 "|HostBusPciAddress"
3950 "|EnableSuspendToDisk"
3951 "|PowerS1Enabled"
3952 "|PowerS4Enabled"
3953 "|CpuHotPlug"
3954 "|AmlFilePath"
3955 "|Serial0IoPortBase"
3956 "|Serial1IoPortBase"
3957 "|Serial2IoPortBase"
3958 "|Serial3IoPortBase"
3959 "|Serial0Irq"
3960 "|Serial1Irq"
3961 "|Serial2Irq"
3962 "|Serial3Irq"
3963 "|AcpiOemId"
3964 "|AcpiCreatorId"
3965 "|AcpiCreatorRev"
3966 "|CustomTable"
3967 "|CustomTable0"
3968 "|CustomTable1"
3969 "|CustomTable2"
3970 "|CustomTable3"
3971 "|Parallel0IoPortBase"
3972 "|Parallel1IoPortBase"
3973 "|Parallel0Irq"
3974 "|Parallel1Irq"
3975 "|IommuAmdPciAddress"
3976 "|SbIoApicPciAddress"
3977 , "");
3978
3979 /* query whether we are supposed to present an IOAPIC */
3980 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3981 if (RT_FAILURE(rc))
3982 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
3983
3984 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3985 if (RT_FAILURE(rc))
3986 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3987
3988 /* query whether we are supposed to present an FDC controller */
3989 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3990 if (RT_FAILURE(rc))
3991 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
3992
3993 /* query whether we are supposed to present HPET */
3994 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
3995 if (RT_FAILURE(rc))
3996 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
3997 /* query MCFG configuration */
3998 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
3999 if (RT_FAILURE(rc))
4000 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4001 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4002 if (RT_FAILURE(rc))
4003 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4004 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4005
4006 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4007 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4008 if (RT_FAILURE(rc))
4009 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4010
4011 /* query the limit of the the 64-bit prefetchable memory window */
4012 uint64_t u64PciPref64MaxGB;
4013 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4014 if (RT_FAILURE(rc))
4015 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4016 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4017
4018 /* query whether we are supposed to present SMC */
4019 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4020 if (RT_FAILURE(rc))
4021 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4022
4023 /* query whether we are supposed to present RTC object */
4024 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4025 if (RT_FAILURE(rc))
4026 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4027
4028 /* query whether we are supposed to present CPU objects */
4029 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4030 if (RT_FAILURE(rc))
4031 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4032
4033 /* query primary NIC PCI address (GIGE) */
4034 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4035 if (RT_FAILURE(rc))
4036 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4037
4038 /* query HD Audio PCI address (HDAA) */
4039 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4040 if (RT_FAILURE(rc))
4041 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4042
4043 /* query NVMe PCI address (NVMA) */
4044 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4045 if (RT_FAILURE(rc))
4046 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4047
4048 /* query IO controller (southbridge) PCI address */
4049 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4050 if (RT_FAILURE(rc))
4051 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4052
4053 /* query host bus controller PCI address */
4054 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4055 if (RT_FAILURE(rc))
4056 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4057
4058 /* query whether S1 power state should be exposed */
4059 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4060 if (RT_FAILURE(rc))
4061 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4062
4063 /* query whether S4 power state should be exposed */
4064 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4065 if (RT_FAILURE(rc))
4066 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4067
4068 /* query whether S1 power state should save the VM state */
4069 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4070 if (RT_FAILURE(rc))
4071 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4072
4073 /* query whether we are allow CPU hot plugging */
4074 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4075 if (RT_FAILURE(rc))
4076 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4077
4078 /* query serial info */
4079 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4080 if (RT_FAILURE(rc))
4081 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4082
4083 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4084 if (RT_FAILURE(rc))
4085 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4086
4087 /* Serial 1 is enabled, get config data */
4088 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4089 if (RT_FAILURE(rc))
4090 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4091
4092 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4093 if (RT_FAILURE(rc))
4094 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4095
4096 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4097 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4098 if (RT_FAILURE(rc))
4099 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4100
4101 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4102 if (RT_FAILURE(rc))
4103 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4104
4105 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4106 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4107 if (RT_FAILURE(rc))
4108 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4109
4110 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4111 if (RT_FAILURE(rc))
4112 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4113 /*
4114 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4115 * the corresponding parallel port is not enabled.
4116 */
4117 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4118 if (RT_FAILURE(rc))
4119 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4120
4121 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4122 if (RT_FAILURE(rc))
4123 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4124
4125 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4126 if (RT_FAILURE(rc))
4127 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4128
4129 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4130 if (RT_FAILURE(rc))
4131 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4132
4133#ifdef VBOX_WITH_IOMMU_AMD
4134 /* Query IOMMU AMD address (IOMA). */
4135 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuAmdPciAddress", &pThis->u32IommuAmdPciAddress, 0);
4136 if (RT_FAILURE(rc))
4137 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdAddress\""));
4138
4139 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4140 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress, 0);
4141 if (RT_FAILURE(rc))
4142 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4143
4144 /* Warn if the SB IOAPIC is not at the required address if an AMD IOMMU is configured. */
4145 if ( pThis->u32IommuAmdPciAddress
4146 && pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4147 {
4148 /** @todo Maybe make this a VM startup failure later. */
4149 LogRel(("ACPI: Warning! Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4150 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4151 }
4152#endif
4153
4154 /* Try to attach the other CPUs */
4155 for (unsigned i = 1; i < pThis->cCpus; i++)
4156 {
4157 if (pThis->fCpuHotPlug)
4158 {
4159 PPDMIBASE IBaseTmp;
4160 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4161
4162 if (RT_SUCCESS(rc))
4163 {
4164 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4165 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4166 Log(("acpi: Attached CPU %u\n", i));
4167 }
4168 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4169 Log(("acpi: CPU %u not attached yet\n", i));
4170 else
4171 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4172 }
4173 else
4174 {
4175 /* CPU is always attached if hot-plug is not enabled. */
4176 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4177 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4178 }
4179 }
4180
4181 char szOemId[16];
4182 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4183 if (RT_FAILURE(rc))
4184 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4185 size_t cchOemId = strlen(szOemId);
4186 if (cchOemId > 6)
4187 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4188 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4189 memcpy(pThis->au8OemId, szOemId, cchOemId);
4190
4191 char szCreatorId[16];
4192 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4193 if (RT_FAILURE(rc))
4194 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4195 size_t cchCreatorId = strlen(szCreatorId);
4196 if (cchCreatorId > 4)
4197 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4198 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4199 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4200
4201 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4202 if (RT_FAILURE(rc))
4203 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4204
4205 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4206
4207 /*
4208 * Load custom ACPI tables.
4209 */
4210 /* Total space available for custom ACPI tables */
4211 /** @todo define as appropriate, remove as a magic number, and document
4212 * limitation in product manual */
4213 uint32_t cbBufAvail = 3072;
4214 pThis->cCustTbls = 0;
4215
4216 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4217 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4218 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4219 {
4220 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4221
4222 /*
4223 * Get the custom table binary file name.
4224 */
4225 char *pszCustBinFile = NULL;
4226 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4227 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4228 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4229 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4230 {
4231 rc = VINF_SUCCESS;
4232 pszCustBinFile = NULL;
4233 }
4234 else if (RT_FAILURE(rc))
4235 return PDMDEV_SET_ERROR(pDevIns, rc,
4236 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4237 else if (!*pszCustBinFile)
4238 {
4239 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4240 pszCustBinFile = NULL;
4241 }
4242
4243 /*
4244 * Determine the custom table binary size, open specified file in the process.
4245 */
4246 if (pszCustBinFile)
4247 {
4248 uint32_t idxCust = pThis->cCustTbls;
4249 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4250 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4251 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4252 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4253 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4254 if (RT_FAILURE(rc))
4255 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4256 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4257
4258 /* Update custom OEM attributes based on custom table */
4259 /** @todo is it intended for custom tables to overwrite user provided values above? */
4260 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4261 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4262 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4263 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4264 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4265 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4266
4267 pThis->cCustTbls++;
4268 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
4269 }
4270 }
4271
4272 /* Set default PM port base */
4273 pThis->uPmIoPortBase = PM_PORT_BASE;
4274
4275 /* Set default SMBus port base */
4276 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4277
4278 /*
4279 * FDC and SMC try to use the same non-shareable interrupt (6),
4280 * enable only one device.
4281 */
4282 if (pThis->fUseSmc)
4283 pThis->fUseFdc = false;
4284
4285 /*
4286 * Plant ACPI tables.
4287 */
4288 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4289 * au8RSDPPage here. However, there should be no harm in doing it
4290 * twice, so the lazy bird is taking the quick way out for now. */
4291 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4292 if (!GCPhysRsdp)
4293 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4294
4295 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4296 AssertRCReturn(rc, rc);
4297
4298 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4299 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4300 AssertRCReturn(rc, rc);
4301
4302 /*
4303 * Create the PM I/O ports. These can be unmapped and remapped.
4304 */
4305 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4306 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4307 AssertRCReturn(rc, rc);
4308 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4309 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4310 AssertRCReturn(rc, rc);
4311 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4312 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4313 AssertRCReturn(rc, rc);
4314 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4315 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4316 AssertRCReturn(rc, rc);
4317 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4318 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4319 AssertRCReturn(rc, rc);
4320 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4321 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4322 AssertRCReturn(rc, rc);
4323 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4324 AssertRCReturn(rc, rc);
4325
4326 /*
4327 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4328 */
4329 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4330 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4331 AssertRCReturn(rc, rc);
4332 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4333 AssertRCReturn(rc, rc);
4334
4335 /*
4336 * Create and map the fixed I/O ports.
4337 */
4338 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4339 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4340 AssertRCReturn(rc, rc);
4341#ifdef DEBUG_ACPI
4342 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4343 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4344 AssertRCReturn(rc, rc);
4345 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4346 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4347 AssertRCReturn(rc, rc);
4348#endif
4349 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4350 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4351 AssertRCReturn(rc, rc);
4352 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4353 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4354 AssertRCReturn(rc, rc);
4355 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4356 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4357 AssertRCReturn(rc, rc);
4358 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4359 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4360 AssertRCReturn(rc, rc);
4361 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4362 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4363 AssertRCReturn(rc, rc);
4364
4365 /*
4366 * Create the PM timer.
4367 */
4368 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4369 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pThis->hPmTimer);
4370 AssertRCReturn(rc, rc);
4371
4372 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4373 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4374 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4375 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4376
4377 /*
4378 * Set up the PCI device.
4379 */
4380 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4381 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4382
4383 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4384 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4385
4386 /* See p. 50 of PIIX4 manual */
4387 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4388 PDMPciDevSetStatus(pPciDev, 0x0280);
4389
4390 PDMPciDevSetRevisionId(pPciDev, 0x08);
4391
4392 PDMPciDevSetClassProg(pPciDev, 0x00);
4393 PDMPciDevSetClassSub(pPciDev, 0x80);
4394 PDMPciDevSetClassBase(pPciDev, 0x06);
4395
4396 PDMPciDevSetHeaderType(pPciDev, 0x80);
4397
4398 PDMPciDevSetBIST(pPciDev, 0x00);
4399
4400 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4401 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4402
4403 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4404 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4405
4406 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4407 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4408 acpiR3SMBusResetDevice(pThis);
4409
4410 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4411 AssertRCReturn(rc, rc);
4412
4413 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4414 AssertRCReturn(rc, rc);
4415
4416 /*
4417 * Register the saved state.
4418 */
4419 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4420 AssertRCReturn(rc, rc);
4421
4422 /*
4423 * Get the corresponding connector interface
4424 */
4425 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4426 if (RT_SUCCESS(rc))
4427 {
4428 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4429 if (!pThisCC->pDrv)
4430 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4431 }
4432 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4433 {
4434 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4435 rc = VINF_SUCCESS;
4436 }
4437 else
4438 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4439
4440 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4441
4442 return rc;
4443}
4444
4445#else /* !IN_RING3 */
4446
4447/**
4448 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4449 */
4450static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4451{
4452 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4453 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4454
4455 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4456 AssertRCReturn(rc, rc);
4457
4458 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4459 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4460 AssertRCReturn(rc, rc);
4461
4462 return VINF_SUCCESS;
4463}
4464
4465#endif /* !IN_RING3 */
4466
4467/**
4468 * The device registration structure.
4469 */
4470const PDMDEVREG g_DeviceACPI =
4471{
4472 /* .u32Version = */ PDM_DEVREG_VERSION,
4473 /* .uReserved0 = */ 0,
4474 /* .szName = */ "acpi",
4475 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4476 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4477 /* .cMaxInstances = */ ~0U,
4478 /* .uSharedVersion = */ 42,
4479 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4480 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4481 /* .cbInstanceRC = */ 0,
4482 /* .cMaxPciDevices = */ 1,
4483 /* .cMaxMsixVectors = */ 0,
4484 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4485#if defined(IN_RING3)
4486 /* .pszRCMod = */ "VBoxDDRC.rc",
4487 /* .pszR0Mod = */ "VBoxDDR0.r0",
4488 /* .pfnConstruct = */ acpiR3Construct,
4489 /* .pfnDestruct = */ acpiR3Destruct,
4490 /* .pfnRelocate = */ NULL,
4491 /* .pfnMemSetup = */ acpiR3MemSetup,
4492 /* .pfnPowerOn = */ NULL,
4493 /* .pfnReset = */ acpiR3Reset,
4494 /* .pfnSuspend = */ NULL,
4495 /* .pfnResume = */ acpiR3Resume,
4496 /* .pfnAttach = */ acpiR3Attach,
4497 /* .pfnDetach = */ acpiR3Detach,
4498 /* .pfnQueryInterface = */ NULL,
4499 /* .pfnInitComplete = */ NULL,
4500 /* .pfnPowerOff = */ NULL,
4501 /* .pfnSoftReset = */ NULL,
4502 /* .pfnReserved0 = */ NULL,
4503 /* .pfnReserved1 = */ NULL,
4504 /* .pfnReserved2 = */ NULL,
4505 /* .pfnReserved3 = */ NULL,
4506 /* .pfnReserved4 = */ NULL,
4507 /* .pfnReserved5 = */ NULL,
4508 /* .pfnReserved6 = */ NULL,
4509 /* .pfnReserved7 = */ NULL,
4510#elif defined(IN_RING0)
4511 /* .pfnEarlyConstruct = */ NULL,
4512 /* .pfnConstruct = */ acpiRZConstruct,
4513 /* .pfnDestruct = */ NULL,
4514 /* .pfnFinalDestruct = */ NULL,
4515 /* .pfnRequest = */ NULL,
4516 /* .pfnReserved0 = */ NULL,
4517 /* .pfnReserved1 = */ NULL,
4518 /* .pfnReserved2 = */ NULL,
4519 /* .pfnReserved3 = */ NULL,
4520 /* .pfnReserved4 = */ NULL,
4521 /* .pfnReserved5 = */ NULL,
4522 /* .pfnReserved6 = */ NULL,
4523 /* .pfnReserved7 = */ NULL,
4524#elif defined(IN_RC)
4525 /* .pfnConstruct = */ acpiRZConstruct,
4526 /* .pfnReserved0 = */ NULL,
4527 /* .pfnReserved1 = */ NULL,
4528 /* .pfnReserved2 = */ NULL,
4529 /* .pfnReserved3 = */ NULL,
4530 /* .pfnReserved4 = */ NULL,
4531 /* .pfnReserved5 = */ NULL,
4532 /* .pfnReserved6 = */ NULL,
4533 /* .pfnReserved7 = */ NULL,
4534#else
4535# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4536#endif
4537 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4538};
4539
4540#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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