VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 87937

Last change on this file since 87937 was 87773, checked in by vboxsync, 4 years ago

VMM/TM,Devices: Store the timer name in the TMTIMER structure and limit it to 31 characters. Shortened most timer names. bugref:9943
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File size: 175.4 KB
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1/* $Id: DevACPI.cpp 87773 2021-02-16 23:36:15Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <VBox/pci.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#include <iprt/asm-math.h>
33#include <iprt/file.h>
34#ifdef IN_RING3
35# include <iprt/alloc.h>
36# include <iprt/string.h>
37# include <iprt/uuid.h>
38#endif /* IN_RING3 */
39#ifdef VBOX_WITH_IOMMU_AMD
40# include <VBox/iommu-amd.h>
41#endif
42
43#include "VBoxDD.h"
44#ifdef VBOX_WITH_IOMMU_AMD
45# include "../Bus/DevIommuAmd.h"
46#endif
47
48#ifdef LOG_ENABLED
49# define DEBUG_ACPI
50#endif
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56#ifdef IN_RING3
57/** Locks the device state, ring-3 only. */
58# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
59 do { \
60 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
61 AssertRC(rcLock); \
62 } while (0)
63#endif
64/** Unlocks the device state (all contexts). */
65#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
66 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
67
68
69#define DEBUG_HEX 0x3000
70#define DEBUG_CHR 0x3001
71
72/** PM Base Address PCI config space offset */
73#define PMBA 0x40
74/** PM Miscellaneous Power Management PCI config space offset */
75#define PMREGMISC 0x80
76
77#define PM_TMR_FREQ 3579545
78/** Default base for PM PIIX4 device */
79#define PM_PORT_BASE 0x4000
80/* Port offsets in PM device */
81enum
82{
83 PM1a_EVT_OFFSET = 0x00,
84 PM1b_EVT_OFFSET = -1, /**< not supported */
85 PM1a_CTL_OFFSET = 0x04,
86 PM1b_CTL_OFFSET = -1, /**< not supported */
87 PM2_CTL_OFFSET = -1, /**< not supported */
88 PM_TMR_OFFSET = 0x08,
89 GPE0_OFFSET = 0x20,
90 GPE1_OFFSET = -1 /**< not supported */
91};
92
93/* Maximum supported number of custom ACPI tables */
94#define MAX_CUST_TABLES 4
95
96/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
97#define PM_TMR_32BIT
98
99#define BAT_INDEX 0x00004040
100#define BAT_DATA 0x00004044
101#define SYSI_INDEX 0x00004048
102#define SYSI_DATA 0x0000404c
103#define ACPI_RESET_BLK 0x00004050
104
105/* PM1x status register bits */
106#define TMR_STS RT_BIT(0)
107#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
108#define BM_STS RT_BIT(4)
109#define GBL_STS RT_BIT(5)
110#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
111#define PWRBTN_STS RT_BIT(8)
112#define SLPBTN_STS RT_BIT(9)
113#define RTC_STS RT_BIT(10)
114#define IGN_STS RT_BIT(11)
115#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
116#define WAK_STS RT_BIT(15)
117#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
118
119/* PM1x enable register bits */
120#define TMR_EN RT_BIT(0)
121#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
122#define GBL_EN RT_BIT(5)
123#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
124#define PWRBTN_EN RT_BIT(8)
125#define SLPBTN_EN RT_BIT(9)
126#define RTC_EN RT_BIT(10)
127#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
128#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
129#define IGN_EN 0
130
131/* PM1x control register bits */
132#define SCI_EN RT_BIT(0)
133#define BM_RLD RT_BIT(1)
134#define GBL_RLS RT_BIT(2)
135#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
136#define IGN_CNT RT_BIT(9)
137#define SLP_TYPx_SHIFT 10
138#define SLP_TYPx_MASK 7
139#define SLP_EN RT_BIT(13)
140#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
141#define RSR_CNT (RSR1_CNT | RSR2_CNT)
142
143#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
144
145enum
146{
147 BAT_STATUS_STATE = 0x00, /**< BST battery state */
148 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
149 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
150 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
151 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
152 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
153 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
154 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
155 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
156 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
157 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
158 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
159 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
160 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
161 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
162 BAT_INDEX_LAST
163};
164
165enum
166{
167 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
168 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
169};
170
171enum
172{
173 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
174 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
175 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
176 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
177 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
178 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
179 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
180 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
181 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
182 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
183 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
184 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
185 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
186 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
187 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
188 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
189 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
190 SYSTEM_INFO_INDEX_POWER_STATES = 17,
191 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
192 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
193 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
194 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
195 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
196 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
197 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
198 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
199 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
200 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
201 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
202 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
203 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
204 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
205 SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS = 32, /**< AMD IOMMU PCI address, or 0 */
206 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
207 SYSTEM_INFO_INDEX_END = 34,
208 SYSTEM_INFO_INDEX_INVALID = 0x80,
209 SYSTEM_INFO_INDEX_VALID = 0x200
210};
211
212#define AC_OFFLINE 0
213#define AC_ONLINE 1
214
215#define BAT_TECH_PRIMARY 1
216#define BAT_TECH_SECONDARY 2
217
218#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
219#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
220#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
221#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
222#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
223
224/** SMBus Base Address PCI config space offset */
225#define SMBBA 0x90
226/** SMBus Host Configuration PCI config space offset */
227#define SMBHSTCFG 0xd2
228/** SMBus Slave Command PCI config space offset */
229#define SMBSLVC 0xd3
230/** SMBus Slave Shadow Port 1 PCI config space offset */
231#define SMBSHDW1 0xd4
232/** SMBus Slave Shadow Port 2 PCI config space offset */
233#define SMBSHDW2 0xd5
234/** SMBus Revision Identification PCI config space offset */
235#define SMBREV 0xd6
236
237#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
238#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
239#define SMBHSTCFG_INTRSEL_SMI 0
240#define SMBHSTCFG_INTRSEL_IRQ9 4
241#define SMBHSTCFG_INTRSEL_SHIFT 1
242
243/** Default base for SMBus PIIX4 device */
244#define SMB_PORT_BASE 0x4100
245
246/** SMBus Host Status Register I/O offset */
247#define SMBHSTSTS_OFF 0x0000
248/** SMBus Slave Status Register I/O offset */
249#define SMBSLVSTS_OFF 0x0001
250/** SMBus Host Count Register I/O offset */
251#define SMBHSTCNT_OFF 0x0002
252/** SMBus Host Command Register I/O offset */
253#define SMBHSTCMD_OFF 0x0003
254/** SMBus Host Address Register I/O offset */
255#define SMBHSTADD_OFF 0x0004
256/** SMBus Host Data 0 Register I/O offset */
257#define SMBHSTDAT0_OFF 0x0005
258/** SMBus Host Data 1 Register I/O offset */
259#define SMBHSTDAT1_OFF 0x0006
260/** SMBus Block Data Register I/O offset */
261#define SMBBLKDAT_OFF 0x0007
262/** SMBus Slave Control Register I/O offset */
263#define SMBSLVCNT_OFF 0x0008
264/** SMBus Shadow Command Register I/O offset */
265#define SMBSHDWCMD_OFF 0x0009
266/** SMBus Slave Event Register I/O offset */
267#define SMBSLVEVT_OFF 0x000a
268/** SMBus Slave Data Register I/O offset */
269#define SMBSLVDAT_OFF 0x000c
270
271#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
272#define SMBHSTSTS_INTER RT_BIT(1)
273#define SMBHSTSTS_DEV_ERR RT_BIT(2)
274#define SMBHSTSTS_BUS_ERR RT_BIT(3)
275#define SMBHSTSTS_FAILED RT_BIT(4)
276#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
277
278#define SMBSLVSTS_WRITE_MASK 0x3c
279
280#define SMBHSTCNT_INTEREN RT_BIT(0)
281#define SMBHSTCNT_KILL RT_BIT(1)
282#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
283#define SMBHSTCNT_START RT_BIT(6)
284#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
285
286#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
287
288
289/*********************************************************************************************************************************
290* Structures and Typedefs *
291*********************************************************************************************************************************/
292/**
293 * The shared ACPI device state.
294 */
295typedef struct ACPISTATE
296{
297 /** Critical section protecting the ACPI state. */
298 PDMCRITSECT CritSect;
299
300 uint16_t pm1a_en;
301 uint16_t pm1a_sts;
302 uint16_t pm1a_ctl;
303 /** Number of logical CPUs in guest */
304 uint16_t cCpus;
305
306 uint64_t u64PmTimerInitial;
307 /** The PM timer. */
308 TMTIMERHANDLE hPmTimer;
309 /* PM Timer last calculated value */
310 uint32_t uPmTimerVal;
311 uint32_t Alignment0;
312
313 uint32_t gpe0_en;
314 uint32_t gpe0_sts;
315
316 uint32_t uBatteryIndex;
317 uint32_t au8BatteryInfo[13];
318
319 uint32_t uSystemInfoIndex;
320 uint32_t u32Alignment0;
321 uint64_t u64RamSize;
322 /** Offset of the 64-bit prefetchable memory window. */
323 uint64_t u64PciPref64Min;
324 /** Limit of the 64-bit prefetchable memory window. */
325 uint64_t u64PciPref64Max;
326 /** The number of bytes below 4GB. */
327 uint32_t cbRamLow;
328
329 /** Current ACPI S* state. We support S0 and S5. */
330 uint32_t uSleepState;
331 uint8_t au8RSDPPage[0x1000];
332 /** This is a workaround for incorrect index field handling by Intels ACPICA.
333 * The system info _INI method writes to offset 0x200. We either observe a
334 * write request to index 0x80 (in that case we don't change the index) or a
335 * write request to offset 0x200 (in that case we divide the index value by
336 * 4. Note that the _STA method is sometimes called prior to the _INI method
337 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
338 * acpiR3BatIndexWrite() for handling this. */
339 uint8_t u8IndexShift;
340 /** provide an I/O-APIC */
341 uint8_t u8UseIOApic;
342 /** provide a floppy controller */
343 bool fUseFdc;
344 /** If High Precision Event Timer device should be supported */
345 bool fUseHpet;
346 /** If System Management Controller device should be supported */
347 bool fUseSmc;
348 /** the guest handled the last power button event */
349 bool fPowerButtonHandled;
350 /** If ACPI CPU device should be shown */
351 bool fShowCpu;
352 /** If Real Time Clock ACPI object to be shown */
353 bool fShowRtc;
354 /** I/O port address of PM device. */
355 RTIOPORT uPmIoPortBase;
356 /** I/O port address of SMBus device. */
357 RTIOPORT uSMBusIoPortBase;
358 /** Which CPU to check for the locked status. */
359 uint32_t idCpuLockCheck;
360 /** Array of flags of attached CPUs */
361 VMCPUSET CpuSetAttached;
362 /** Mask of locked CPUs (used by the guest). */
363 VMCPUSET CpuSetLocked;
364 /** The CPU event type. */
365 uint32_t u32CpuEventType;
366 /** The CPU id affected. */
367 uint32_t u32CpuEvent;
368 /** Flag whether CPU hot plugging is enabled. */
369 bool fCpuHotPlug;
370 /** If MCFG ACPI table shown to the guest */
371 bool fUseMcfg;
372 /** if the 64-bit prefetchable memory window is shown to the guest */
373 bool fPciPref64Enabled;
374 /** If the IOMMU device should be enabled */
375 bool fUseIommu;
376 /** Primary NIC PCI address. */
377 uint32_t u32NicPciAddress;
378 /** HD Audio PCI address. */
379 uint32_t u32AudioPciAddress;
380 /** Primary NVMe controller PCI address. */
381 uint32_t u32NvmePciAddress;
382 /** Flag whether S1 power state is enabled. */
383 bool fS1Enabled;
384 /** Flag whether S4 power state is enabled. */
385 bool fS4Enabled;
386 /** Flag whether S1 triggers a state save. */
387 bool fSuspendToSavedState;
388 /** Flag whether to set WAK_STS on resume (restore included). */
389 bool fSetWakeupOnResume;
390 /** PCI address of the IO controller device. */
391 uint32_t u32IocPciAddress;
392 /** PCI address of the host bus controller device. */
393 uint32_t u32HbcPciAddress;
394 /** PCI address of the AMD IOMMU device. */
395 uint32_t u32IommuAmdPciAddress;
396 /** PCI address of the southbridge I/O APIC device. */
397 uint32_t u32SbIoApicPciAddress;
398
399 /** Physical address of PCI config space MMIO region */
400 uint64_t u64PciConfigMMioAddress;
401 /** Length of PCI config space MMIO region */
402 uint64_t u64PciConfigMMioLength;
403 /** Serial 0 IRQ number */
404 uint8_t uSerial0Irq;
405 /** Serial 1 IRQ number */
406 uint8_t uSerial1Irq;
407 /** Serial 2 IRQ number */
408 uint8_t uSerial2Irq;
409 /** Serial 3 IRQ number */
410 uint8_t uSerial3Irq;
411 /** Serial 0 IO port base */
412 RTIOPORT uSerial0IoPortBase;
413 /** Serial 1 IO port base */
414 RTIOPORT uSerial1IoPortBase;
415 /** Serial 2 IO port base */
416 RTIOPORT uSerial2IoPortBase;
417 /** Serial 3 IO port base */
418 RTIOPORT uSerial3IoPortBase;
419
420 /** @name Parallel port config bits
421 * @{ */
422 /** Parallel 0 IO port base */
423 RTIOPORT uParallel0IoPortBase;
424 /** Parallel 1 IO port base */
425 RTIOPORT uParallel1IoPortBase;
426 /** Parallel 0 IRQ number */
427 uint8_t uParallel0Irq;
428 /** Parallel 1 IRQ number */
429 uint8_t uParallel1Irq;
430 /** @} */
431
432 /** Number of custom ACPI tables */
433 uint8_t cCustTbls;
434 /** ACPI OEM ID */
435 uint8_t au8OemId[6];
436 /** ACPI Crator ID */
437 uint8_t au8CreatorId[4];
438 uint8_t abAlignment2[3];
439 /** ACPI Crator Rev */
440 uint32_t u32CreatorRev;
441 /** ACPI custom OEM Tab ID */
442 uint8_t au8OemTabId[8];
443 /** ACPI custom OEM Rev */
444 uint32_t u32OemRevision;
445
446 /** SMBus Host Status Register */
447 uint8_t u8SMBusHstSts;
448 /** SMBus Slave Status Register */
449 uint8_t u8SMBusSlvSts;
450 /** SMBus Host Control Register */
451 uint8_t u8SMBusHstCnt;
452 /** SMBus Host Command Register */
453 uint8_t u8SMBusHstCmd;
454 /** SMBus Host Address Register */
455 uint8_t u8SMBusHstAdd;
456 /** SMBus Host Data 0 Register */
457 uint8_t u8SMBusHstDat0;
458 /** SMBus Host Data 1 Register */
459 uint8_t u8SMBusHstDat1;
460 /** SMBus Slave Control Register */
461 uint8_t u8SMBusSlvCnt;
462 /** SMBus Slave Event Register */
463 uint16_t u16SMBusSlvEvt;
464 /** SMBus Slave Data Register */
465 uint16_t u16SMBusSlvDat;
466 /** SMBus Shadow Command Register */
467 uint8_t u8SMBusShdwCmd;
468 /** SMBus Host Block Index */
469 uint8_t u8SMBusBlkIdx;
470 uint8_t abAlignment3[2];
471 /** SMBus Host Block Data Buffer */
472 uint8_t au8SMBusBlkDat[32];
473
474 /** @todo DEBUGGING */
475 uint32_t uPmTimeOld;
476 uint32_t uPmTimeA;
477 uint32_t uPmTimeB;
478 uint32_t Alignment5;
479
480 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
481 * @{ */
482 IOMIOPORTHANDLE hIoPortPm1aEn;
483 IOMIOPORTHANDLE hIoPortPm1aSts;
484 IOMIOPORTHANDLE hIoPortPm1aCtl;
485 IOMIOPORTHANDLE hIoPortPmTimer;
486 IOMIOPORTHANDLE hIoPortGpe0En;
487 IOMIOPORTHANDLE hIoPortGpe0Sts;
488 /** @} */
489
490 /** SMBus I/O ports (mapped/unmapped). */
491 IOMIOPORTHANDLE hIoPortSMBus;
492
493 /** @name Fixed I/O ports
494 * @{ */
495 /** ACPI SMI I/O port. */
496 IOMIOPORTHANDLE hIoPortSmi;
497 /** ACPI Debug hex I/O port. */
498 IOMIOPORTHANDLE hIoPortDebugHex;
499 /** ACPI Debug char I/O port. */
500 IOMIOPORTHANDLE hIoPortDebugChar;
501 /** ACPI Battery status index I/O port. */
502 IOMIOPORTHANDLE hIoPortBatteryIndex;
503 /** ACPI Battery status data I/O port. */
504 IOMIOPORTHANDLE hIoPortBatteryData;
505 /** ACPI system info index I/O port. */
506 IOMIOPORTHANDLE hIoPortSysInfoIndex;
507 /** ACPI system info data I/O port. */
508 IOMIOPORTHANDLE hIoPortSysInfoData;
509 /** ACPI Reset I/O port. */
510 IOMIOPORTHANDLE hIoPortReset;
511 /** @} */
512
513} ACPISTATE;
514/** Pointer to the shared ACPI device state. */
515typedef ACPISTATE *PACPISTATE;
516
517
518
519/**
520 * The ring-3 ACPI device state.
521 */
522typedef struct ACPISTATER3
523{
524 /** ACPI port base interface. */
525 PDMIBASE IBase;
526 /** ACPI port interface. */
527 PDMIACPIPORT IACPIPort;
528 /** Pointer to the device instance so we can get our bearings from
529 * interface functions. */
530 PPDMDEVINSR3 pDevIns;
531
532 /** Pointer to the driver base interface. */
533 R3PTRTYPE(PPDMIBASE) pDrvBase;
534 /** Pointer to the driver connector interface. */
535 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
536
537 /** Custom ACPI tables binary data. */
538 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
539 /** The size of the custom table binary. */
540 uint64_t acbCustBin[MAX_CUST_TABLES];
541} ACPISTATER3;
542/** Pointer to the ring-3 ACPI device state. */
543typedef ACPISTATER3 *PACPISTATER3;
544
545
546#pragma pack(1)
547
548/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
549struct ACPIGENADDR
550{
551 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
552 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
553 uint8_t u8RegisterBitOffset; /**< bit offset of register */
554 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
555 uint64_t u64Address; /**< 64-bit address of register */
556};
557AssertCompileSize(ACPIGENADDR, 12);
558
559/** Root System Description Pointer */
560struct ACPITBLRSDP
561{
562 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
563 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
564 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
565 uint8_t u8Revision; /**< revision number, currently 2 */
566#define ACPI_REVISION 2 /**< ACPI 3.0 */
567 uint32_t u32RSDT; /**< phys addr of RSDT */
568 uint32_t u32Length; /**< bytes of this table */
569 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
570 uint8_t u8ExtChecksum; /**< checksum of entire table */
571 uint8_t u8Reserved[3]; /**< reserved */
572};
573AssertCompileSize(ACPITBLRSDP, 36);
574
575/** System Description Table Header */
576struct ACPITBLHEADER
577{
578 uint8_t au8Signature[4]; /**< table identifier */
579 uint32_t u32Length; /**< length of the table including header */
580 uint8_t u8Revision; /**< revision number */
581 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
582 uint8_t au8OemId[6]; /**< OEM-supplied string */
583 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
584 uint32_t u32OemRevision; /**< OEM-supplied revision number */
585 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
586 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
587};
588AssertCompileSize(ACPITBLHEADER, 36);
589
590/** Root System Description Table */
591struct ACPITBLRSDT
592{
593 ACPITBLHEADER header;
594 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
595};
596AssertCompileSize(ACPITBLRSDT, 40);
597
598/** Extended System Description Table */
599struct ACPITBLXSDT
600{
601 ACPITBLHEADER header;
602 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
603};
604AssertCompileSize(ACPITBLXSDT, 44);
605
606/** Fixed ACPI Description Table */
607struct ACPITBLFADT
608{
609 ACPITBLHEADER header;
610 uint32_t u32FACS; /**< phys. address of FACS */
611 uint32_t u32DSDT; /**< phys. address of DSDT */
612 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
613#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
614#define INT_MODEL_MULTIPLE_APIC 2
615 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
616 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
617#define SCI_INT 9
618 uint32_t u32SMICmd; /**< system port address of SMI command port */
619#define SMI_CMD 0x0000442e
620 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
621#define ACPI_ENABLE 0xa1
622 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
623#define ACPI_DISABLE 0xa0
624 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
625 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
626 state control responsibility */
627 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
628 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
629 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
630 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
631 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
632 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
633 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
634 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
635 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
636 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
637 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
638 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
639 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
640#define GPE0_BLK_LEN 2
641 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
642#define GPE1_BLK_LEN 0
643 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
644#define GPE1_BASE 0
645 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
646 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
647#define P_LVL2_LAT 101 /**< C2 state not supported */
648 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
649#define P_LVL3_LAT 1001 /**< C3 state not supported */
650 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
651 lines from any processors memory caches */
652#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
653 uint16_t u16FlushStride; /**< cache line width */
654#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
655 uint8_t u8DutyOffset;
656 uint8_t u8DutyWidth;
657 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
658 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
659 uint8_t u8Century; /**< RTC CMOS RAM index of century */
660 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
661#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
662 (COM too?) */
663#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
664#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
665#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
666#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
667 uint8_t u8Must0_0; /**< must be 0 */
668 uint32_t u32Flags; /**< fixed feature flags */
669#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
670#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
671#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
672#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
673#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
674#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
675#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
676#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
677#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
678#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
679#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
680#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
681#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
682#define FADT_FL_CPU_SW_SLP RT_BIT(13)
683#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
684#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
685#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
686#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
687#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
688#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
689
690/* PM Timer mask and msb */
691#ifndef PM_TMR_32BIT
692#define TMR_VAL_MSB 0x800000
693#define TMR_VAL_MASK 0xffffff
694#undef FADT_FL_TMR_VAL_EXT
695#define FADT_FL_TMR_VAL_EXT 0
696#else
697#define TMR_VAL_MSB 0x80000000
698#define TMR_VAL_MASK 0xffffffff
699#endif
700
701 /** Start of the ACPI 2.0 extension. */
702 ACPIGENADDR ResetReg; /**< ext addr of reset register */
703 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
704#define ACPI_RESET_REG_VAL 0x10
705 uint8_t au8Must0_1[3]; /**< must be 0 */
706 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
707 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
708 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
709 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
710 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
711 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
712 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
713 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
714 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
715 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
716};
717AssertCompileSize(ACPITBLFADT, 244);
718#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
719
720/** Firmware ACPI Control Structure */
721struct ACPITBLFACS
722{
723 uint8_t au8Signature[4]; /**< 'FACS' */
724 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
725 uint32_t u32HWSignature; /**< systems HW signature at last boot */
726 uint32_t u32FWVector; /**< address of waking vector */
727 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
728 uint32_t u32Flags; /**< FACS flags */
729 uint64_t u64X_FWVector; /**< 64-bit waking vector */
730 uint8_t u8Version; /**< version of this table */
731 uint8_t au8Reserved[31]; /**< zero */
732};
733AssertCompileSize(ACPITBLFACS, 64);
734
735/** Processor Local APIC Structure */
736struct ACPITBLLAPIC
737{
738 uint8_t u8Type; /**< 0 = LAPIC */
739 uint8_t u8Length; /**< 8 */
740 uint8_t u8ProcId; /**< processor ID */
741 uint8_t u8ApicId; /**< local APIC ID */
742 uint32_t u32Flags; /**< Flags */
743#define LAPIC_ENABLED 0x1
744};
745AssertCompileSize(ACPITBLLAPIC, 8);
746
747/** I/O APIC Structure */
748struct ACPITBLIOAPIC
749{
750 uint8_t u8Type; /**< 1 == I/O APIC */
751 uint8_t u8Length; /**< 12 */
752 uint8_t u8IOApicId; /**< I/O APIC ID */
753 uint8_t u8Reserved; /**< 0 */
754 uint32_t u32Address; /**< phys address to access I/O APIC */
755 uint32_t u32GSIB; /**< global system interrupt number to start */
756};
757AssertCompileSize(ACPITBLIOAPIC, 12);
758
759/** Interrupt Source Override Structure */
760struct ACPITBLISO
761{
762 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
763 uint8_t u8Length; /**< 10 */
764 uint8_t u8Bus; /**< Bus */
765 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
766 uint32_t u32GSI; /**< Global System Interrupt */
767 uint16_t u16Flags; /**< MPS INTI flags Global */
768};
769AssertCompileSize(ACPITBLISO, 10);
770#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
771
772/** HPET Descriptor Structure */
773struct ACPITBLHPET
774{
775 ACPITBLHEADER aHeader;
776 uint32_t u32Id; /**< hardware ID of event timer block
777 [31:16] PCI vendor ID of first timer block
778 [15] legacy replacement IRQ routing capable
779 [14] reserved
780 [13] COUNT_SIZE_CAP counter size
781 [12:8] number of comparators in first timer block
782 [7:0] hardware rev ID */
783 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
784 uint8_t u32Number; /**< sequence number starting at 0 */
785 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
786 lost interrupts while the counter is programmed
787 to operate in periodic mode. Unit: clock tick. */
788 uint8_t u8Attributes; /**< page protection and OEM attribute. */
789};
790AssertCompileSize(ACPITBLHPET, 56);
791
792#ifdef VBOX_WITH_IOMMU_AMD
793/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
794 * In accordance with the AMD spec. */
795typedef struct ACPIIVRS
796{
797 ACPITBLHEADER header;
798 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
799 uint64_t u64Rsvd; /**< Reserved (MBZ). */
800 /* IVHD type block follows. */
801} ACPIIVRS;
802AssertCompileSize(ACPIIVRS, 48);
803AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
804
805/**
806 * AMD IOMMU: The ACPI table.
807 */
808typedef struct ACPITBLIOMMU
809{
810 ACPIIVRS Hdr;
811 ACPIIVHDTYPE10 IvhdType10;
812 ACPIIVHDDEVENTRY4 IvhdType10Start;
813 ACPIIVHDDEVENTRY4 IvhdType10End;
814 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
815 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
816 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
817 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
818
819 ACPIIVHDTYPE11 IvhdType11;
820 ACPIIVHDDEVENTRY4 IvhdType11Start;
821 ACPIIVHDDEVENTRY4 IvhdType11End;
822 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
823 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
824 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
825 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
826} ACPITBLIOMMU;
827AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
828AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
829AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
830AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
831#endif
832
833/** MCFG Descriptor Structure */
834typedef struct ACPITBLMCFG
835{
836 ACPITBLHEADER aHeader;
837 uint64_t u64Reserved;
838} ACPITBLMCFG;
839AssertCompileSize(ACPITBLMCFG, 44);
840
841/** Number of such entries can be computed from the whole table length in header */
842typedef struct ACPITBLMCFGENTRY
843{
844 uint64_t u64BaseAddress;
845 uint16_t u16PciSegmentGroup;
846 uint8_t u8StartBus;
847 uint8_t u8EndBus;
848 uint32_t u32Reserved;
849} ACPITBLMCFGENTRY;
850AssertCompileSize(ACPITBLMCFGENTRY, 16);
851
852#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
853
854/** Custom Description Table */
855struct ACPITBLCUST
856{
857 ACPITBLHEADER header;
858 uint8_t au8Data[476];
859};
860AssertCompileSize(ACPITBLCUST, 512);
861
862
863#pragma pack()
864
865
866#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
867
868
869/*********************************************************************************************************************************
870* Internal Functions *
871*********************************************************************************************************************************/
872#ifdef IN_RING3
873static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
874#endif
875
876/* SCI, usually IRQ9 */
877DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
878{
879 PDMDevHlpPCISetIrq(pDevIns, 0, level);
880}
881
882DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
883{
884 return (pThis->pm1a_ctl & SCI_EN)
885 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
886}
887
888DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
889{
890 return !!(pThis->gpe0_en & pThis->gpe0_sts);
891}
892
893DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
894{
895 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
896 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
897 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
898 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
899 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
900}
901
902DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
903{
904 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
905}
906
907/**
908 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
909 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
910 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
911 * registers and trigger IRQs.
912 *
913 * Caller must hold the state lock.
914 *
915 * @param pDevIns The PDM device instance.
916 * @param pThis The ACPI shared instance data.
917 * @param sts The new PM1a.STS value.
918 * @param en The new PM1a.EN value.
919 */
920static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
921{
922 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
923
924 const bool old_level = acpiSCILevel(pDevIns, pThis);
925 pThis->pm1a_en = en;
926 pThis->pm1a_sts = sts;
927 const bool new_level = acpiSCILevel(pDevIns, pThis);
928
929 LogFunc(("old=%x new=%x\n", old_level, new_level));
930
931 if (new_level != old_level)
932 acpiSetIrq(pDevIns, new_level);
933}
934
935#ifdef IN_RING3
936
937/**
938 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
939 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
940 *
941 * Caller must hold the state lock.
942 *
943 * @param pDevIns The PDM device instance.
944 * @param pThis The ACPI shared instance data.
945 * @param sts The new GPE0.STS value.
946 * @param en The new GPE0.EN value.
947 */
948static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
949{
950 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
951
952 const bool old_level = acpiSCILevel(pDevIns, pThis);
953 pThis->gpe0_en = en;
954 pThis->gpe0_sts = sts;
955 const bool new_level = acpiSCILevel(pDevIns, pThis);
956
957 LogFunc(("old=%x new=%x\n", old_level, new_level));
958
959 if (new_level != old_level)
960 acpiSetIrq(pDevIns, new_level);
961}
962
963/**
964 * Used by acpiR3PM1aCtlWrite to power off the VM.
965 *
966 * @param pDevIns The device instance.
967 * @returns Strict VBox status code.
968 */
969static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
970{
971 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
972 AssertRC(VBOXSTRICTRC_VAL(rc));
973 return rc;
974}
975
976/**
977 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
978 *
979 * @param pDevIns The device instance.
980 * @param pThis The ACPI shared instance data.
981 * @returns Strict VBox status code.
982 */
983static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
984{
985 /* We must set WAK_STS on resume (includes restore) so the guest knows that
986 we've woken up and can continue executing code. The guest is probably
987 reading the PMSTS register in a loop to check this. */
988 VBOXSTRICTRC rc;
989 pThis->fSetWakeupOnResume = true;
990 if (pThis->fSuspendToSavedState)
991 {
992 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
993 if (rc != VERR_NOT_SUPPORTED)
994 AssertRC(VBOXSTRICTRC_VAL(rc));
995 else
996 {
997 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
998 rc = PDMDevHlpVMSuspend(pDevIns);
999 AssertRC(VBOXSTRICTRC_VAL(rc));
1000 }
1001 }
1002 else
1003 {
1004 rc = PDMDevHlpVMSuspend(pDevIns);
1005 AssertRC(VBOXSTRICTRC_VAL(rc));
1006 }
1007 return rc;
1008}
1009
1010
1011/**
1012 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
1013 */
1014static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
1015{
1016 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1017 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1018 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1019 DEVACPI_LOCK_R3(pDevIns, pThis);
1020
1021 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1022 pThis->fPowerButtonHandled = false;
1023 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1024
1025 DEVACPI_UNLOCK(pDevIns, pThis);
1026 return VINF_SUCCESS;
1027}
1028
1029/**
1030 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
1031 */
1032static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1033{
1034 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1035 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1036 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1037 DEVACPI_LOCK_R3(pDevIns, pThis);
1038
1039 *pfHandled = pThis->fPowerButtonHandled;
1040
1041 DEVACPI_UNLOCK(pDevIns, pThis);
1042 return VINF_SUCCESS;
1043}
1044
1045/**
1046 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1047 * Guest entered into G0 (working) or G1 (sleeping)}
1048 */
1049static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1050{
1051 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1052 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1053 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1054 DEVACPI_LOCK_R3(pDevIns, pThis);
1055
1056 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1057
1058 DEVACPI_UNLOCK(pDevIns, pThis);
1059 return VINF_SUCCESS;
1060}
1061
1062/**
1063 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1064 */
1065static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1066{
1067 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1068 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1069 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1070 DEVACPI_LOCK_R3(pDevIns, pThis);
1071
1072 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1073
1074 DEVACPI_UNLOCK(pDevIns, pThis);
1075 return VINF_SUCCESS;
1076}
1077
1078/**
1079 * Send an ACPI sleep button event.
1080 *
1081 * @returns VBox status code
1082 * @param pInterface Pointer to the interface structure containing the called function pointer.
1083 */
1084static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1085{
1086 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1087 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1088 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1089 DEVACPI_LOCK_R3(pDevIns, pThis);
1090
1091 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1092
1093 DEVACPI_UNLOCK(pDevIns, pThis);
1094 return VINF_SUCCESS;
1095}
1096
1097/**
1098 * Send an ACPI monitor hot-plug event.
1099 *
1100 * @returns VBox status code
1101 * @param pInterface Pointer to the interface structure containing the
1102 * called function pointer.
1103 */
1104static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1105{
1106 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1107 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1108 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1109 DEVACPI_LOCK_R3(pDevIns, pThis);
1110
1111 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1112
1113 DEVACPI_UNLOCK(pDevIns, pThis);
1114 return VINF_SUCCESS;
1115}
1116
1117/**
1118 * Send an ACPI battery status change event.
1119 *
1120 * @returns VBox status code
1121 * @param pInterface Pointer to the interface structure containing the
1122 * called function pointer.
1123 */
1124static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1125{
1126 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1127 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1128 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1129 DEVACPI_LOCK_R3(pDevIns, pThis);
1130
1131 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1132
1133 DEVACPI_UNLOCK(pDevIns, pThis);
1134 return VINF_SUCCESS;
1135}
1136
1137/**
1138 * Used by acpiR3PmTimer to re-arm the PM timer.
1139 *
1140 * The caller is expected to either hold the clock lock or to have made sure
1141 * the VM is resetting or loading state.
1142 *
1143 * @param pDevIns The device instance.
1144 * @param pThis The ACPI shared instance data.
1145 * @param uNow The current time.
1146 */
1147static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1148{
1149 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1150 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1151 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1152 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1153 Log(("acpi: uInterval = %RU64\n", uInterval));
1154}
1155
1156#endif /* IN_RING3 */
1157
1158/**
1159 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1160 *
1161 * The caller is expected to either hold the clock lock or to have made sure
1162 * the VM is resetting or loading state.
1163 *
1164 * @param pDevIns The PDM device instance.
1165 * @param pThis The ACPI instance
1166 * @param u64Now The current time
1167 */
1168static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1169{
1170 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1171 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1172 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1173
1174 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1175 & TMR_VAL_MASK;
1176
1177 if ((pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1178 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1179}
1180
1181#ifdef IN_RING3
1182
1183/**
1184 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1185 */
1186static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1187{
1188 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1189 Assert(pThis->hPmTimer == hTimer);
1190 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
1191 RT_NOREF(pvUser);
1192
1193 DEVACPI_LOCK_R3(pDevIns, pThis);
1194 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1195 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1196 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1197 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, hTimer);
1198 acpiPmTimerUpdate(pDevIns, pThis, tsNow);
1199 DEVACPI_UNLOCK(pDevIns, pThis);
1200
1201 acpiR3PmTimerReset(pDevIns, pThis, tsNow);
1202}
1203
1204/**
1205 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1206 * acpiR3LoadState.
1207 *
1208 * @returns VINF_SUCCESS.
1209 * @param pThis The ACPI shared instance data.
1210 * @param pThisCC The ACPI instance data for ring-3.
1211 */
1212static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1213{
1214 uint32_t *p = pThis->au8BatteryInfo;
1215 bool fPresent; /* battery present? */
1216 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1217 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1218 uint32_t hostPresentRate; /* 0..1000 */
1219 int rc;
1220
1221 if (!pThisCC->pDrv)
1222 return VINF_SUCCESS;
1223 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1224 &hostBatteryState, &hostPresentRate);
1225 AssertRC(rc);
1226
1227 /* default values */
1228 p[BAT_STATUS_STATE] = hostBatteryState;
1229 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1230 : hostPresentRate * 50; /* mW */
1231 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1232 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1233
1234 /* did we get a valid battery state? */
1235 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1236 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1237 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1238 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1239
1240 return VINF_SUCCESS;
1241}
1242
1243/**
1244 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1245 * acpiR3LoadState.
1246 *
1247 * @returns VINF_SUCCESS.
1248 * @param pThis The ACPI shared instance data.
1249 */
1250static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1251{
1252 uint32_t *p = pThis->au8BatteryInfo;
1253
1254 p[BAT_INFO_UNITS] = 0; /* mWh */
1255 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1256 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1257 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1258 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1259 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1260 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1261 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1262 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1263
1264 return VINF_SUCCESS;
1265}
1266
1267/**
1268 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1269 *
1270 * @returns status mask or 0.
1271 * @param pThisCC The ACPI instance data for ring-3.
1272 */
1273static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1274{
1275 bool fPresent; /* battery present? */
1276 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1277 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1278 uint32_t hostPresentRate; /* 0..1000 */
1279 int rc;
1280
1281 if (!pThisCC->pDrv)
1282 return 0;
1283 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1284 &hostBatteryState, &hostPresentRate);
1285 AssertRC(rc);
1286
1287 return fPresent
1288 ? STA_DEVICE_PRESENT_MASK /* present */
1289 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1290 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1291 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1292 | STA_BATTERY_PRESENT_MASK /* battery is present */
1293 : 0; /* device not present */
1294}
1295
1296/**
1297 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1298 *
1299 * @returns status.
1300 * @param pThisCC The ACPI instance data for ring-3.
1301 */
1302static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1303{
1304 /* query the current power source from the host driver */
1305 if (!pThisCC->pDrv)
1306 return AC_ONLINE;
1307
1308 PDMACPIPOWERSOURCE ps;
1309 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1310 AssertRC(rc);
1311 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1312}
1313
1314/**
1315 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1316 */
1317static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1318{
1319 RT_NOREF(pvUser, offPort);
1320 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1321 if (cb != 4)
1322 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1323
1324 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1325 DEVACPI_LOCK_R3(pDevIns, pThis);
1326
1327 u32 >>= pThis->u8IndexShift;
1328 /* see comment at the declaration of u8IndexShift */
1329 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1330 {
1331 pThis->u8IndexShift = 2;
1332 u32 >>= 2;
1333 }
1334 Assert(u32 < BAT_INDEX_LAST);
1335 pThis->uBatteryIndex = u32;
1336
1337 DEVACPI_UNLOCK(pDevIns, pThis);
1338 return VINF_SUCCESS;
1339}
1340
1341/**
1342 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1343 */
1344static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1345{
1346 RT_NOREF(pvUser, offPort);
1347 if (cb != 4)
1348 return VERR_IOM_IOPORT_UNUSED;
1349
1350 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1351 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1352 DEVACPI_LOCK_R3(pDevIns, pThis);
1353
1354 VBOXSTRICTRC rc = VINF_SUCCESS;
1355 switch (pThis->uBatteryIndex)
1356 {
1357 case BAT_STATUS_STATE:
1358 acpiR3FetchBatteryStatus(pThis, pThisCC);
1359 RT_FALL_THRU();
1360 case BAT_STATUS_PRESENT_RATE:
1361 case BAT_STATUS_REMAINING_CAPACITY:
1362 case BAT_STATUS_PRESENT_VOLTAGE:
1363 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1364 break;
1365
1366 case BAT_INFO_UNITS:
1367 acpiR3FetchBatteryInfo(pThis);
1368 RT_FALL_THRU();
1369 case BAT_INFO_DESIGN_CAPACITY:
1370 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1371 case BAT_INFO_TECHNOLOGY:
1372 case BAT_INFO_DESIGN_VOLTAGE:
1373 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1374 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1375 case BAT_INFO_CAPACITY_GRANULARITY_1:
1376 case BAT_INFO_CAPACITY_GRANULARITY_2:
1377 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1378 break;
1379
1380 case BAT_DEVICE_STATUS:
1381 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1382 break;
1383
1384 case BAT_POWER_SOURCE:
1385 *pu32 = acpiR3GetPowerSource(pThisCC);
1386 break;
1387
1388 default:
1389 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1390 *pu32 = UINT32_MAX;
1391 break;
1392 }
1393
1394 DEVACPI_UNLOCK(pDevIns, pThis);
1395 return rc;
1396}
1397
1398/**
1399 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1400 */
1401static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1402{
1403 RT_NOREF(pvUser, offPort);
1404 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1405 if (cb != 4)
1406 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1407
1408 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1409 DEVACPI_LOCK_R3(pDevIns, pThis);
1410
1411 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1412 pThis->uSystemInfoIndex = u32;
1413 else
1414 {
1415 /* see comment at the declaration of u8IndexShift */
1416 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1417 {
1418 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1419 pThis->u8IndexShift = 2;
1420 }
1421
1422 u32 >>= pThis->u8IndexShift;
1423
1424 /* If the index exceeds 31 (which is all we can fit within offset 0x80), we need to divide the index again
1425 for indices > 31 and < SYSTEM_INFO_INDEX_END. */
1426 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 2 && (u32 >> 2) < SYSTEM_INFO_INDEX_END)
1427 u32 >>= 2;
1428
1429 AssertMsg(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1430 pThis->uSystemInfoIndex = u32;
1431 }
1432
1433 DEVACPI_UNLOCK(pDevIns, pThis);
1434 return VINF_SUCCESS;
1435}
1436
1437/**
1438 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1439 */
1440static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1441{
1442 RT_NOREF(pvUser, offPort);
1443 if (cb != 4)
1444 return VERR_IOM_IOPORT_UNUSED;
1445
1446 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1447 DEVACPI_LOCK_R3(pDevIns, pThis);
1448
1449 VBOXSTRICTRC rc = VINF_SUCCESS;
1450 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1451 switch (uSystemInfoIndex)
1452 {
1453 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1454 *pu32 = pThis->cbRamLow;
1455 break;
1456
1457 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1458 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1459 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1460 break;
1461
1462 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1463 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1464 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1465 break;
1466
1467 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1468 *pu32 = pThis->u8UseIOApic;
1469 break;
1470
1471 case SYSTEM_INFO_INDEX_HPET_STATUS:
1472 *pu32 = pThis->fUseHpet
1473 ? ( STA_DEVICE_PRESENT_MASK
1474 | STA_DEVICE_ENABLED_MASK
1475 | STA_DEVICE_SHOW_IN_UI_MASK
1476 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1477 : 0;
1478 break;
1479
1480 case SYSTEM_INFO_INDEX_SMC_STATUS:
1481 *pu32 = pThis->fUseSmc
1482 ? ( STA_DEVICE_PRESENT_MASK
1483 | STA_DEVICE_ENABLED_MASK
1484 /* no need to show this device in the UI */
1485 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1486 : 0;
1487 break;
1488
1489 case SYSTEM_INFO_INDEX_FDC_STATUS:
1490 *pu32 = pThis->fUseFdc
1491 ? ( STA_DEVICE_PRESENT_MASK
1492 | STA_DEVICE_ENABLED_MASK
1493 | STA_DEVICE_SHOW_IN_UI_MASK
1494 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1495 : 0;
1496 break;
1497
1498 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1499 *pu32 = pThis->u32NicPciAddress;
1500 break;
1501
1502 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1503 *pu32 = pThis->u32AudioPciAddress;
1504 break;
1505
1506 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1507 *pu32 = pThis->u32NvmePciAddress;
1508 break;
1509
1510 case SYSTEM_INFO_INDEX_POWER_STATES:
1511 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1512 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1513 *pu32 |= RT_BIT(1);
1514 if (pThis->fS4Enabled)
1515 *pu32 |= RT_BIT(4);
1516 break;
1517
1518 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1519 *pu32 = pThis->u32IocPciAddress;
1520 break;
1521
1522 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1523 *pu32 = pThis->u32HbcPciAddress;
1524 break;
1525
1526 case SYSTEM_INFO_INDEX_PCI_BASE:
1527 /** @todo couldn't MCFG be in 64-bit range? */
1528 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1529 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1530 break;
1531
1532 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1533 /** @todo couldn't MCFG be in 64-bit range? */
1534 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1535 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1536 break;
1537
1538 case SYSTEM_INFO_INDEX_RTC_STATUS:
1539 *pu32 = pThis->fShowRtc
1540 ? ( STA_DEVICE_PRESENT_MASK
1541 | STA_DEVICE_ENABLED_MASK
1542 | STA_DEVICE_SHOW_IN_UI_MASK
1543 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1544 : 0;
1545 break;
1546
1547 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1548 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1549 {
1550 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1551 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1552 }
1553 else
1554 {
1555 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1556 pThis->idCpuLockCheck);
1557 /* Always return locked status just to be safe */
1558 *pu32 = 1;
1559 }
1560 break;
1561
1562 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1563 *pu32 = pThis->u32CpuEventType;
1564 break;
1565
1566 case SYSTEM_INFO_INDEX_CPU_EVENT:
1567 *pu32 = pThis->u32CpuEvent;
1568 break;
1569
1570 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1571 *pu32 = pThis->uSerial0IoPortBase;
1572 break;
1573
1574 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1575 *pu32 = pThis->uSerial0Irq;
1576 break;
1577
1578 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1579 *pu32 = pThis->uSerial1IoPortBase;
1580 break;
1581
1582 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1583 *pu32 = pThis->uSerial1Irq;
1584 break;
1585
1586 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1587 *pu32 = pThis->uSerial2IoPortBase;
1588 break;
1589
1590 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1591 *pu32 = pThis->uSerial2Irq;
1592 break;
1593
1594 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1595 *pu32 = pThis->uSerial3IoPortBase;
1596 break;
1597
1598 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1599 *pu32 = pThis->uSerial3Irq;
1600 break;
1601
1602 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1603 *pu32 = pThis->uParallel0IoPortBase;
1604 break;
1605
1606 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1607 *pu32 = pThis->uParallel0Irq;
1608 break;
1609
1610 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1611 *pu32 = pThis->uParallel1IoPortBase;
1612 break;
1613
1614 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1615 *pu32 = pThis->uParallel1Irq;
1616 break;
1617
1618 case SYSTEM_INFO_INDEX_IOMMU_AMD_ADDRESS:
1619 *pu32 = pThis->u32IommuAmdPciAddress;
1620 break;
1621
1622 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
1623 *pu32 = pThis->u32SbIoApicPciAddress;
1624 break;
1625
1626 case SYSTEM_INFO_INDEX_END:
1627 /** @todo why isn't this setting any output value? */
1628 break;
1629
1630 /* Solaris 9 tries to read from this index */
1631 case SYSTEM_INFO_INDEX_INVALID:
1632 *pu32 = 0;
1633 break;
1634
1635 default:
1636 *pu32 = UINT32_MAX;
1637 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1638 break;
1639 }
1640
1641 DEVACPI_UNLOCK(pDevIns, pThis);
1642 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1643 return rc;
1644}
1645
1646/**
1647 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1648 */
1649static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1650{
1651 RT_NOREF(pvUser, offPort);
1652 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1653 if (cb != 4)
1654 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1655
1656 DEVACPI_LOCK_R3(pDevIns, pThis);
1657 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1658
1659 VBOXSTRICTRC rc = VINF_SUCCESS;
1660 switch (pThis->uSystemInfoIndex)
1661 {
1662 case SYSTEM_INFO_INDEX_INVALID:
1663 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1664 pThis->u8IndexShift = 0;
1665 break;
1666
1667 case SYSTEM_INFO_INDEX_VALID:
1668 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1669 pThis->u8IndexShift = 2;
1670 break;
1671
1672 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1673 pThis->idCpuLockCheck = u32;
1674 break;
1675
1676 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1677 if (u32 < pThis->cCpus)
1678 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1679 else
1680 LogRel(("ACPI: CPU %u does not exist\n", u32));
1681 break;
1682
1683 default:
1684 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1685 break;
1686 }
1687
1688 DEVACPI_UNLOCK(pDevIns, pThis);
1689 return rc;
1690}
1691
1692/**
1693 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1694 */
1695static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1696{
1697 RT_NOREF(offPort, pvUser);
1698 if (cb != 2)
1699 return VERR_IOM_IOPORT_UNUSED;
1700
1701 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1702 DEVACPI_LOCK_R3(pDevIns, pThis);
1703
1704 *pu32 = pThis->pm1a_en;
1705
1706 DEVACPI_UNLOCK(pDevIns, pThis);
1707 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1708 return VINF_SUCCESS;
1709}
1710
1711/**
1712 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1713 */
1714static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1715{
1716 RT_NOREF(offPort, pvUser);
1717 if (cb != 2 && cb != 4)
1718 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1719
1720 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1721 DEVACPI_LOCK_R3(pDevIns, pThis);
1722
1723 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1724 u32 &= ~(RSR_EN | IGN_EN);
1725 u32 &= 0xffff;
1726 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1727
1728 DEVACPI_UNLOCK(pDevIns, pThis);
1729 return VINF_SUCCESS;
1730}
1731
1732/**
1733 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1734 */
1735static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1736{
1737 RT_NOREF(offPort, pvUser);
1738 if (cb != 2)
1739 {
1740 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1741 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1742 }
1743
1744 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1745 DEVACPI_LOCK_R3(pDevIns, pThis);
1746
1747 *pu32 = pThis->pm1a_sts;
1748
1749 DEVACPI_UNLOCK(pDevIns, pThis);
1750 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1751 return VINF_SUCCESS;
1752}
1753
1754/**
1755 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1756 */
1757static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1758{
1759 RT_NOREF(offPort, pvUser);
1760 if (cb != 2 && cb != 4)
1761 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1762
1763 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1764 DEVACPI_LOCK_R3(pDevIns, pThis);
1765
1766 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1767 u32 &= 0xffff;
1768 if (u32 & PWRBTN_STS)
1769 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1770 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1771 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1772
1773 DEVACPI_UNLOCK(pDevIns, pThis);
1774 return VINF_SUCCESS;
1775}
1776
1777/**
1778 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1779 */
1780static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1781{
1782 RT_NOREF(offPort, pvUser);
1783 if (cb != 2)
1784 {
1785 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1786 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1787 }
1788
1789 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1790 DEVACPI_LOCK_R3(pDevIns, pThis);
1791
1792 *pu32 = pThis->pm1a_ctl;
1793
1794 DEVACPI_UNLOCK(pDevIns, pThis);
1795 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1796 return VINF_SUCCESS;
1797}
1798
1799/**
1800 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1801 */
1802static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1803{
1804 RT_NOREF(offPort, pvUser);
1805 if (cb != 2 && cb != 4)
1806 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1807
1808 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1809 DEVACPI_LOCK_R3(pDevIns, pThis);
1810
1811 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1812 u32 &= 0xffff;
1813 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1814
1815 VBOXSTRICTRC rc = VINF_SUCCESS;
1816 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1817 if (uSleepState != pThis->uSleepState)
1818 {
1819 pThis->uSleepState = uSleepState;
1820 switch (uSleepState)
1821 {
1822 case 0x00: /* S0 */
1823 break;
1824
1825 case 0x01: /* S1 */
1826 if (pThis->fS1Enabled)
1827 {
1828 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1829 rc = acpiR3DoSleep(pDevIns, pThis);
1830 break;
1831 }
1832 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1833 RT_FALL_THRU();
1834
1835 case 0x04: /* S4 */
1836 if (pThis->fS4Enabled)
1837 {
1838 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1839 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1840 break;
1841 }
1842 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1843 RT_FALL_THRU();
1844
1845 case 0x05: /* S5 */
1846 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1847 rc = acpiR3DoPowerOff(pDevIns);
1848 break;
1849
1850 default:
1851 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1852 break;
1853 }
1854 }
1855
1856 DEVACPI_UNLOCK(pDevIns, pThis);
1857 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1858 return rc;
1859}
1860
1861#endif /* IN_RING3 */
1862
1863/**
1864 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1865 *
1866 * @remarks The only I/O port currently implemented in all contexts.
1867 */
1868static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1869{
1870 RT_NOREF(offPort, pvUser);
1871 if (cb != 4)
1872 return VERR_IOM_IOPORT_UNUSED;
1873
1874 /*
1875 * We use the clock lock to serialize access to u64PmTimerInitial and to
1876 * make sure we get a reliable time from the clock
1877 * as well as and to prevent uPmTimerVal from being updated during read.
1878 */
1879 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1880 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1881 if (rc == VINF_SUCCESS)
1882 {
1883 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1884 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1885 *pu32 = pThis->uPmTimerVal;
1886
1887 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
1888
1889 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1890 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1891
1892#if 0
1893 /** @todo temporary: sanity check against running backwards */
1894 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1895 if (*pu32 - uOld >= 0x10000000)
1896 {
1897# if defined(IN_RING0)
1898 pThis->uPmTimeA = uOld;
1899 pThis->uPmTimeB = *pu32;
1900 return VERR_TM_TIMER_BAD_CLOCK;
1901# elif defined(IN_RING3)
1902 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1903# endif
1904 }
1905#endif
1906 }
1907 return rc;
1908}
1909
1910#ifdef IN_RING3
1911
1912/**
1913 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
1914 */
1915static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1916{
1917 RT_NOREF(offPort, pvUser);
1918 if (cb != 1)
1919 {
1920 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1921 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1922 }
1923
1924 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1925 DEVACPI_LOCK_R3(pDevIns, pThis);
1926
1927 *pu32 = pThis->gpe0_sts & 0xff;
1928
1929 DEVACPI_UNLOCK(pDevIns, pThis);
1930 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1931 return VINF_SUCCESS;
1932}
1933
1934/**
1935 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
1936 */
1937static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1938{
1939 RT_NOREF(offPort, pvUser);
1940 if (cb != 1)
1941 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1942
1943 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1944 DEVACPI_LOCK_R3(pDevIns, pThis);
1945
1946 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1947 u32 = pThis->gpe0_sts & ~u32;
1948 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1949
1950 DEVACPI_UNLOCK(pDevIns, pThis);
1951 return VINF_SUCCESS;
1952}
1953
1954/**
1955 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
1956 */
1957static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1958{
1959 RT_NOREF(offPort, pvUser);
1960 if (cb != 1)
1961 {
1962 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1963 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1964 }
1965
1966 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1967 DEVACPI_LOCK_R3(pDevIns, pThis);
1968
1969 *pu32 = pThis->gpe0_en & 0xff;
1970
1971 DEVACPI_UNLOCK(pDevIns, pThis);
1972 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1973 return VINF_SUCCESS;
1974}
1975
1976/**
1977 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
1978 */
1979static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1980{
1981 RT_NOREF(offPort, pvUser);
1982 if (cb != 1)
1983 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1984
1985 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1986 DEVACPI_LOCK_R3(pDevIns, pThis);
1987
1988 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1989 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
1990
1991 DEVACPI_UNLOCK(pDevIns, pThis);
1992 return VINF_SUCCESS;
1993}
1994
1995/**
1996 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
1997 */
1998static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1999{
2000 RT_NOREF(offPort, pvUser);
2001 Log(("acpiR3SmiWrite %#x\n", u32));
2002 if (cb != 1)
2003 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2004
2005 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2006 DEVACPI_LOCK_R3(pDevIns, pThis);
2007
2008 if (u32 == ACPI_ENABLE)
2009 pThis->pm1a_ctl |= SCI_EN;
2010 else if (u32 == ACPI_DISABLE)
2011 pThis->pm1a_ctl &= ~SCI_EN;
2012 else
2013 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2014
2015 DEVACPI_UNLOCK(pDevIns, pThis);
2016 return VINF_SUCCESS;
2017}
2018
2019/**
2020 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2021 */
2022static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2023{
2024 RT_NOREF(offPort, pvUser);
2025 Log(("acpiR3ResetWrite: %#x\n", u32));
2026 NOREF(pvUser);
2027 if (cb != 1)
2028 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2029
2030 /* No state locking required. */
2031 VBOXSTRICTRC rc;
2032 if (u32 == ACPI_RESET_REG_VAL)
2033 {
2034 LogRel(("ACPI: Reset initiated by ACPI\n"));
2035 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2036 }
2037 else
2038 {
2039 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2040 rc = VINF_SUCCESS;
2041 }
2042
2043 return rc;
2044}
2045
2046# ifdef DEBUG_ACPI
2047
2048/**
2049 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2050 */
2051static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2052{
2053 NOREF(pvUser);
2054 switch (cb)
2055 {
2056 case 1:
2057 Log(("%#x\n", u32 & 0xff));
2058 break;
2059 case 2:
2060 Log(("%#6x\n", u32 & 0xffff));
2061 break;
2062 case 4:
2063 Log(("%#10x\n", u32));
2064 break;
2065 default:
2066 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2067 }
2068 return VINF_SUCCESS;
2069}
2070
2071/**
2072 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2073 */
2074static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2075{
2076 NOREF(pvUser);
2077 switch (cb)
2078 {
2079 case 1:
2080 Log(("%c", u32 & 0xff));
2081 break;
2082 default:
2083 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2084 }
2085 return VINF_SUCCESS;
2086}
2087
2088# endif /* DEBUG_ACPI */
2089
2090/**
2091 * @callback_method_impl{FNDBGFHANDLERDEV}
2092 */
2093static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2094{
2095 RT_NOREF(pszArgs);
2096 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2097 pHlp->pfnPrintf(pHlp,
2098 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2099}
2100
2101/**
2102 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2103 *
2104 * @param pDevIns The PDM device instance.
2105 * @param pThis The ACPI shared instance data.
2106 */
2107static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2108{
2109 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2110 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2111 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2112 pPciDev->abConfig[PMBA + 2] = 0x00;
2113 pPciDev->abConfig[PMBA + 3] = 0x00;
2114}
2115
2116/**
2117 * Used to calculate the value of a PM I/O port.
2118 *
2119 * @returns The actual I/O port value.
2120 * @param pThis The ACPI shared instance data.
2121 * @param offset The offset into the I/O space, or -1 if invalid.
2122 */
2123static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2124{
2125 Assert(pThis->uPmIoPortBase != 0);
2126
2127 if (offset == -1)
2128 return 0;
2129
2130 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2131}
2132
2133/**
2134 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2135 * timer and GPE0 I/O ports.
2136 *
2137 * @returns VBox status code.
2138 * @param pDevIns The device instance.
2139 * @param pThis The ACPI shared instance data.
2140 */
2141static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2142{
2143 if (pThis->uPmIoPortBase == 0)
2144 return VINF_SUCCESS;
2145
2146 int rc;
2147 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2148 AssertRCReturn(rc, rc);
2149 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2150 AssertRCReturn(rc, rc);
2151 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2152 AssertRCReturn(rc, rc);
2153 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2154 AssertRCReturn(rc, rc);
2155 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2156 AssertRCReturn(rc, rc);
2157 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2158
2159 return VINF_SUCCESS;
2160}
2161
2162/**
2163 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2164 * timer and GPE0 I/O ports.
2165 *
2166 * @returns VBox status code.
2167 * @param pDevIns The device instance.
2168 * @param pThis The ACPI shared instance data.
2169 */
2170static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2171{
2172 if (pThis->uPmIoPortBase != 0)
2173 {
2174 int rc;
2175 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2176 AssertRCReturn(rc, rc);
2177 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2178 AssertRCReturn(rc, rc);
2179 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2180 AssertRCReturn(rc, rc);
2181 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2182 AssertRCReturn(rc, rc);
2183 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2184 AssertRCReturn(rc, rc);
2185 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2186 AssertRCReturn(rc, rc);
2187 }
2188 return VINF_SUCCESS;
2189}
2190
2191/**
2192 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2193 * PM1a, PM timer and GPE0 ports.
2194 *
2195 * @returns VBox status code.
2196 *
2197 * @param pDevIns The device instance.
2198 * @param pThis The ACPI shared instance data.
2199 * @param pThisCC The ACPI instance data for ring-3.
2200 * @param NewIoPortBase The new base address of the I/O ports.
2201 */
2202static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2203{
2204 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2205 if (NewIoPortBase != pThis->uPmIoPortBase)
2206 {
2207 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2208 if (RT_FAILURE(rc))
2209 return rc;
2210
2211 pThis->uPmIoPortBase = NewIoPortBase;
2212
2213 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2214 if (RT_FAILURE(rc))
2215 return rc;
2216
2217 /* We have to update FADT table acccording to the new base */
2218 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2219 AssertRC(rc);
2220 if (RT_FAILURE(rc))
2221 return rc;
2222 }
2223
2224 return VINF_SUCCESS;
2225}
2226
2227/**
2228 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2229 */
2230static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2231{
2232 RT_NOREF(pvUser);
2233 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2234
2235 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2236 uint8_t off = offPort & 0x000f;
2237 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2238 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2239 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2240
2241 DEVACPI_LOCK_R3(pDevIns, pThis);
2242 switch (off)
2243 {
2244 case SMBHSTSTS_OFF:
2245 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2246 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2247 break;
2248 case SMBSLVSTS_OFF:
2249 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2250 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2251 break;
2252 case SMBHSTCNT_OFF:
2253 {
2254 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2255
2256 const bool old_level = acpiSCILevel(pDevIns, pThis);
2257 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2258 if (u32 & SMBHSTCNT_START)
2259 {
2260 /* Start, trigger error as this is a dummy implementation */
2261 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2262 }
2263 if (u32 & SMBHSTCNT_KILL)
2264 {
2265 /* Kill */
2266 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2267 }
2268 const bool new_level = acpiSCILevel(pDevIns, pThis);
2269
2270 LogFunc(("old=%x new=%x\n", old_level, new_level));
2271
2272 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2273 * needs to be implemented later if it ever becomes relevant. */
2274 if (new_level != old_level)
2275 acpiSetIrq(pDevIns, new_level);
2276 break;
2277 }
2278 case SMBHSTCMD_OFF:
2279 pThis->u8SMBusHstCmd = u32;
2280 break;
2281 case SMBHSTADD_OFF:
2282 pThis->u8SMBusHstAdd = u32;
2283 break;
2284 case SMBHSTDAT0_OFF:
2285 pThis->u8SMBusHstDat0 = u32;
2286 break;
2287 case SMBHSTDAT1_OFF:
2288 pThis->u8SMBusHstDat1 = u32;
2289 break;
2290 case SMBBLKDAT_OFF:
2291 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2292 pThis->u8SMBusBlkIdx++;
2293 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2294 break;
2295 case SMBSLVCNT_OFF:
2296 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2297 break;
2298 case SMBSHDWCMD_OFF:
2299 /* readonly register */
2300 break;
2301 case SMBSLVEVT_OFF:
2302 pThis->u16SMBusSlvEvt = u32;
2303 break;
2304 case SMBSLVDAT_OFF:
2305 /* readonly register */
2306 break;
2307 default:
2308 /* caught by the sanity check above */
2309 ;
2310 }
2311
2312 DEVACPI_UNLOCK(pDevIns, pThis);
2313 return VINF_SUCCESS;
2314}
2315
2316/**
2317 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2318 */
2319static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2320{
2321 RT_NOREF(pvUser);
2322 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2323
2324 VBOXSTRICTRC rc = VINF_SUCCESS;
2325 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2326 uint8_t const off = offPort & 0x000f;
2327 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2328 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2329 return VERR_IOM_IOPORT_UNUSED;
2330
2331 DEVACPI_LOCK_R3(pDevIns, pThis);
2332 switch (off)
2333 {
2334 case SMBHSTSTS_OFF:
2335 *pu32 = pThis->u8SMBusHstSts;
2336 break;
2337 case SMBSLVSTS_OFF:
2338 *pu32 = pThis->u8SMBusSlvSts;
2339 break;
2340 case SMBHSTCNT_OFF:
2341 pThis->u8SMBusBlkIdx = 0;
2342 *pu32 = pThis->u8SMBusHstCnt;
2343 break;
2344 case SMBHSTCMD_OFF:
2345 *pu32 = pThis->u8SMBusHstCmd;
2346 break;
2347 case SMBHSTADD_OFF:
2348 *pu32 = pThis->u8SMBusHstAdd;
2349 break;
2350 case SMBHSTDAT0_OFF:
2351 *pu32 = pThis->u8SMBusHstDat0;
2352 break;
2353 case SMBHSTDAT1_OFF:
2354 *pu32 = pThis->u8SMBusHstDat1;
2355 break;
2356 case SMBBLKDAT_OFF:
2357 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2358 pThis->u8SMBusBlkIdx++;
2359 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2360 break;
2361 case SMBSLVCNT_OFF:
2362 *pu32 = pThis->u8SMBusSlvCnt;
2363 break;
2364 case SMBSHDWCMD_OFF:
2365 *pu32 = pThis->u8SMBusShdwCmd;
2366 break;
2367 case SMBSLVEVT_OFF:
2368 *pu32 = pThis->u16SMBusSlvEvt;
2369 break;
2370 case SMBSLVDAT_OFF:
2371 *pu32 = pThis->u16SMBusSlvDat;
2372 break;
2373 default:
2374 /* caught by the sanity check above */
2375 rc = VERR_IOM_IOPORT_UNUSED;
2376 }
2377 DEVACPI_UNLOCK(pDevIns, pThis);
2378
2379 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2380 return rc;
2381}
2382
2383/**
2384 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2385 *
2386 * @param pDevIns The PDM device instance.
2387 * @param pThis The ACPI shared instance data.
2388 */
2389static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2390{
2391 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2392 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2393 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2394 pPciDev->abConfig[SMBBA+2] = 0x00;
2395 pPciDev->abConfig[SMBBA+3] = 0x00;
2396 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2397 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2398 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2399 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2400 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2401}
2402
2403/**
2404 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2405 *
2406 * @param pThis The ACPI shared instance data.
2407 */
2408static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2409{
2410 pThis->u8SMBusHstSts = 0x00;
2411 pThis->u8SMBusSlvSts = 0x00;
2412 pThis->u8SMBusHstCnt = 0x00;
2413 pThis->u8SMBusHstCmd = 0x00;
2414 pThis->u8SMBusHstAdd = 0x00;
2415 pThis->u8SMBusHstDat0 = 0x00;
2416 pThis->u8SMBusHstDat1 = 0x00;
2417 pThis->u8SMBusSlvCnt = 0x00;
2418 pThis->u8SMBusShdwCmd = 0x00;
2419 pThis->u16SMBusSlvEvt = 0x0000;
2420 pThis->u16SMBusSlvDat = 0x0000;
2421 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2422 pThis->u8SMBusBlkIdx = 0;
2423}
2424
2425/**
2426 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2427 *
2428 * @returns VBox status code.
2429 * @param pDevIns The device instance.
2430 * @param pThis The ACPI shared instance data.
2431 */
2432static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2433{
2434 if (pThis->uSMBusIoPortBase != 0)
2435 {
2436 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2437 AssertRCReturn(rc, rc);
2438 }
2439 return VINF_SUCCESS;
2440}
2441
2442/**
2443 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2444 *
2445 * @returns VBox status code.
2446 * @param pDevIns The device instance.
2447 * @param pThis The ACPI shared instance data.
2448 */
2449static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2450{
2451 if (pThis->uSMBusIoPortBase != 0)
2452 {
2453 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2454 AssertRCReturn(rc, rc);
2455 }
2456 return VINF_SUCCESS;
2457}
2458
2459/**
2460 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2461 * SMBus ports.
2462 *
2463 * @returns VBox status code.
2464 *
2465 * @param pDevIns The device instance.
2466 * @param pThis The ACPI shared instance data.
2467 * @param NewIoPortBase The new base address of the I/O ports.
2468 */
2469static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2470{
2471 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2472 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2473 {
2474 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2475 AssertRCReturn(rc, rc);
2476
2477 pThis->uSMBusIoPortBase = NewIoPortBase;
2478
2479 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2480 AssertRCReturn(rc, rc);
2481
2482#if 0 /* is there an FADT table entry for the SMBus base? */
2483 /* We have to update FADT table acccording to the new base */
2484 rc = acpiR3PlantTables(pThis);
2485 AssertRC(rc);
2486 if (RT_FAILURE(rc))
2487 return rc;
2488#endif
2489 }
2490
2491 return VINF_SUCCESS;
2492}
2493
2494
2495/**
2496 * Saved state structure description, version 4.
2497 */
2498static const SSMFIELD g_AcpiSavedStateFields4[] =
2499{
2500 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2501 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2502 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2503 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2504 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2505 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2506 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2507 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2508 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2509 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2510 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2511 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2512 SSMFIELD_ENTRY_TERM()
2513};
2514
2515/**
2516 * Saved state structure description, version 5.
2517 */
2518static const SSMFIELD g_AcpiSavedStateFields5[] =
2519{
2520 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2521 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2522 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2523 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2524 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2525 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2526 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2527 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2528 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2529 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2530 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2531 SSMFIELD_ENTRY_TERM()
2532};
2533
2534/**
2535 * Saved state structure description, version 6.
2536 */
2537static const SSMFIELD g_AcpiSavedStateFields6[] =
2538{
2539 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2540 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2541 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2542 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2543 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2544 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2545 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2546 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2547 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2548 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2549 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2550 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2551 SSMFIELD_ENTRY_TERM()
2552};
2553
2554/**
2555 * Saved state structure description, version 7.
2556 */
2557static const SSMFIELD g_AcpiSavedStateFields7[] =
2558{
2559 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2560 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2561 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2562 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2563 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2564 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2565 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2566 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2567 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2568 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2569 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2570 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2571 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2572 SSMFIELD_ENTRY_TERM()
2573};
2574
2575/**
2576 * Saved state structure description, version 8.
2577 */
2578static const SSMFIELD g_AcpiSavedStateFields8[] =
2579{
2580 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2581 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2582 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2583 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2584 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2585 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2586 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2587 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2588 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2589 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2590 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2591 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2592 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2593 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2594 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2595 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2596 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2597 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2598 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2599 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2600 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2601 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2602 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2603 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2604 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2605 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2606 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2607 SSMFIELD_ENTRY_TERM()
2608};
2609
2610/**
2611 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2612 */
2613static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2614{
2615 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2616 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2617 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2618}
2619
2620/**
2621 * @callback_method_impl{FNSSMDEVLOADEXEC}
2622 */
2623static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2624{
2625 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2626 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2627 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2628 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2629
2630 /*
2631 * Unmap PM I/O ports, will remap it with the actual base after state
2632 * successfully loaded.
2633 */
2634 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2635 AssertRCReturn(rc, rc);
2636
2637 /*
2638 * Unregister SMBus handlers, will register with actual base after state
2639 * successfully loaded.
2640 */
2641 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2642 AssertRCReturn(rc, rc);
2643 acpiR3SMBusResetDevice(pThis);
2644
2645 switch (uVersion)
2646 {
2647 case 4:
2648 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2649 break;
2650 case 5:
2651 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2652 break;
2653 case 6:
2654 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2655 break;
2656 case 7:
2657 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2658 break;
2659 case 8:
2660 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2661 break;
2662 default:
2663 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2664 break;
2665 }
2666 if (RT_SUCCESS(rc))
2667 {
2668 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2669 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2670 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2671 AssertRCReturn(rc, rc);
2672 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2673 AssertRCReturn(rc, rc);
2674 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2675 AssertRCReturn(rc, rc);
2676 rc = acpiR3FetchBatteryInfo(pThis);
2677 AssertRCReturn(rc, rc);
2678
2679 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2680 DEVACPI_LOCK_R3(pDevIns, pThis);
2681 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2682 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2683 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2684 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2685 DEVACPI_UNLOCK(pDevIns, pThis);
2686 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2687 }
2688 return rc;
2689}
2690
2691/**
2692 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2693 */
2694static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2695{
2696 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2697 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2698 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2699 return NULL;
2700}
2701
2702/**
2703 * Calculate the check sum for some ACPI data before planting it.
2704 *
2705 * All the bytes must add up to 0.
2706 *
2707 * @returns check sum.
2708 * @param pvSrc What to check sum.
2709 * @param cbData The amount of data to checksum.
2710 */
2711static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2712{
2713 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2714 uint8_t uSum = 0;
2715 for (size_t i = 0; i < cbData; ++i)
2716 uSum += pbSrc[i];
2717 return -uSum;
2718}
2719
2720/**
2721 * Prepare a ACPI table header.
2722 */
2723static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2724 const char au8Signature[4],
2725 uint32_t u32Length, uint8_t u8Revision)
2726{
2727 memcpy(header->au8Signature, au8Signature, 4);
2728 header->u32Length = RT_H2LE_U32(u32Length);
2729 header->u8Revision = u8Revision;
2730 memcpy(header->au8OemId, pThis->au8OemId, 6);
2731 memcpy(header->au8OemTabId, "VBOX", 4);
2732 memcpy(header->au8OemTabId+4, au8Signature, 4);
2733 header->u32OemRevision = RT_H2LE_U32(1);
2734 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2735 header->u32CreatorRev = pThis->u32CreatorRev;
2736}
2737
2738/**
2739 * Initialize a generic address structure (ACPIGENADDR).
2740 */
2741static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2742 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2743 uint8_t u8AccessSize, uint64_t u64Address)
2744{
2745 g->u8AddressSpaceId = u8AddressSpaceId;
2746 g->u8RegisterBitWidth = u8RegisterBitWidth;
2747 g->u8RegisterBitOffset = u8RegisterBitOffset;
2748 g->u8AccessSize = u8AccessSize;
2749 g->u64Address = RT_H2LE_U64(u64Address);
2750}
2751
2752/**
2753 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2754 */
2755DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2756{
2757 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2758}
2759
2760/**
2761 * Plant the Differentiated System Description Table (DSDT).
2762 */
2763static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2764{
2765 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2766}
2767
2768/**
2769 * Plant the Secondary System Description Table (SSDT).
2770 */
2771static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2772{
2773 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2774}
2775
2776/**
2777 * Plant the Firmware ACPI Control Structure (FACS).
2778 */
2779static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2780{
2781 ACPITBLFACS facs;
2782
2783 memset(&facs, 0, sizeof(facs));
2784 memcpy(facs.au8Signature, "FACS", 4);
2785 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2786 facs.u32HWSignature = RT_H2LE_U32(0);
2787 facs.u32FWVector = RT_H2LE_U32(0);
2788 facs.u32GlobalLock = RT_H2LE_U32(0);
2789 facs.u32Flags = RT_H2LE_U32(0);
2790 facs.u64X_FWVector = RT_H2LE_U64(0);
2791 facs.u8Version = 1;
2792
2793 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2794}
2795
2796/**
2797 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2798 */
2799static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2800 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2801{
2802 ACPITBLFADT fadt;
2803
2804 /* First the ACPI version 2+ version of the structure. */
2805 memset(&fadt, 0, sizeof(fadt));
2806 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2807 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2808 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2809 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2810 fadt.u8PreferredPMProfile = 0; /* unspecified */
2811 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2812 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2813 fadt.u8AcpiEnable = ACPI_ENABLE;
2814 fadt.u8AcpiDisable = ACPI_DISABLE;
2815 fadt.u8S4BIOSReq = 0;
2816 fadt.u8PStateCnt = 0;
2817 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2818 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2819 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2820 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2821 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2822 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2823 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2824 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2825 fadt.u8PM1EVTLEN = 4;
2826 fadt.u8PM1CTLLEN = 2;
2827 fadt.u8PM2CTLLEN = 0;
2828 fadt.u8PMTMLEN = 4;
2829 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2830 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2831 fadt.u8GPE1BASE = GPE1_BASE;
2832 fadt.u8CSTCNT = 0;
2833 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2834 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2835 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2836 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2837 fadt.u8DutyOffset = 0;
2838 fadt.u8DutyWidth = 0;
2839 fadt.u8DayAlarm = 0;
2840 fadt.u8MonAlarm = 0;
2841 fadt.u8Century = 0;
2842 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2843 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2844 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2845 | FADT_FL_FIX_RTC
2846 | FADT_FL_TMR_VAL_EXT
2847 | FADT_FL_RESET_REG_SUP);
2848
2849 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2850 if (pThis->fCpuHotPlug)
2851 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2852
2853 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2854 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2855 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2856 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2857 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2858 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2859 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2860 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2861 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2862 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2863 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2864 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2865 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2866 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2867
2868 /* Now the ACPI 1.0 version. */
2869 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2870 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2871 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2872 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2873 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2874}
2875
2876/**
2877 * Plant the root System Description Table.
2878 *
2879 * The RSDT and XSDT tables are basically identical. The only difference is 32
2880 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2881 * ACPI 2.0 and up.
2882 */
2883static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2884{
2885 ACPITBLRSDT *rsdt;
2886 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2887
2888 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2889 if (!rsdt)
2890 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2891
2892 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2893 for (unsigned int i = 0; i < nb_entries; ++i)
2894 {
2895 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2896 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2897 }
2898 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2899 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2900 RTMemFree(rsdt);
2901 return VINF_SUCCESS;
2902}
2903
2904/**
2905 * Plant the Extended System Description Table.
2906 */
2907static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2908{
2909 ACPITBLXSDT *xsdt;
2910 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2911 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
2912 if (!xsdt)
2913 return VERR_NO_TMP_MEMORY;
2914
2915 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
2916
2917 if (pThis->cCustTbls > 0)
2918 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2919
2920 for (unsigned int i = 0; i < nb_entries; ++i)
2921 {
2922 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2923 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2924 }
2925 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
2926 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
2927
2928 RTMemFree(xsdt);
2929 return VINF_SUCCESS;
2930}
2931
2932/**
2933 * Plant the Root System Description Pointer (RSDP).
2934 */
2935static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2936{
2937 memset(rsdp, 0, sizeof(*rsdp));
2938
2939 /* ACPI 1.0 part (RSDT) */
2940 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2941 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2942 rsdp->u8Revision = ACPI_REVISION;
2943 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2944 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2945
2946 /* ACPI 2.0 part (XSDT) */
2947 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2948 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2949 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2950}
2951
2952/**
2953 * Multiple APIC Description Table.
2954 *
2955 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2956 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2957 * use regular C structure and proxy to raw memory instead.
2958 */
2959class AcpiTableMadt
2960{
2961 /**
2962 * All actual data stored in dynamically allocated memory pointed by this field.
2963 */
2964 uint8_t *m_pbData;
2965 /**
2966 * Number of CPU entries in this MADT.
2967 */
2968 uint32_t m_cCpus;
2969
2970 /**
2971 * Number of interrupt overrides.
2972 */
2973 uint32_t m_cIsos;
2974
2975public:
2976 /**
2977 * Address of ACPI header
2978 */
2979 inline ACPITBLHEADER *header_addr(void) const
2980 {
2981 return (ACPITBLHEADER *)m_pbData;
2982 }
2983
2984 /**
2985 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2986 * although address is the same for all of them.
2987 */
2988 inline uint32_t *u32LAPIC_addr(void) const
2989 {
2990 return (uint32_t *)(header_addr() + 1);
2991 }
2992
2993 /**
2994 * Address of APIC flags
2995 */
2996 inline uint32_t *u32Flags_addr(void) const
2997 {
2998 return (uint32_t *)(u32LAPIC_addr() + 1);
2999 }
3000
3001 /**
3002 * Address of ISO description
3003 */
3004 inline ACPITBLISO *ISO_addr(void) const
3005 {
3006 return (ACPITBLISO *)(u32Flags_addr() + 1);
3007 }
3008
3009 /**
3010 * Address of per-CPU LAPIC descriptions
3011 */
3012 inline ACPITBLLAPIC *LApics_addr(void) const
3013 {
3014 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3015 }
3016
3017 /**
3018 * Address of IO APIC description
3019 */
3020 inline ACPITBLIOAPIC *IOApic_addr(void) const
3021 {
3022 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3023 }
3024
3025 /**
3026 * Size of MADT.
3027 * Note that this function assumes IOApic to be the last field in structure.
3028 */
3029 inline uint32_t size(void) const
3030 {
3031 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3032 }
3033
3034 /**
3035 * Raw data of MADT.
3036 */
3037 inline const uint8_t *data(void) const
3038 {
3039 return m_pbData;
3040 }
3041
3042 /**
3043 * Size of MADT for given ACPI config, useful to compute layout.
3044 */
3045 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3046 {
3047 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3048 }
3049
3050 /*
3051 * Constructor, only works in Ring 3, doesn't look like a big deal.
3052 */
3053 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3054 {
3055 m_cCpus = cCpus;
3056 m_cIsos = cIsos;
3057 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3058 uint32_t cb = size();
3059 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3060 }
3061
3062 ~AcpiTableMadt()
3063 {
3064 RTMemFree(m_pbData);
3065 }
3066};
3067
3068
3069/**
3070 * Plant the Multiple APIC Description Table (MADT).
3071 *
3072 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3073 *
3074 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3075 */
3076static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3077{
3078 uint16_t cpus = pThis->cCpus;
3079 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3080
3081 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3082
3083 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3084 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3085
3086 /* LAPICs records */
3087 ACPITBLLAPIC* lapic = madt.LApics_addr();
3088 for (uint16_t i = 0; i < cpus; i++)
3089 {
3090 lapic->u8Type = 0;
3091 lapic->u8Length = sizeof(ACPITBLLAPIC);
3092 lapic->u8ProcId = i;
3093 /** Must match numbering convention in MPTABLES */
3094 lapic->u8ApicId = i;
3095 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3096 lapic++;
3097 }
3098
3099 /* IO-APIC record */
3100 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3101 ioapic->u8Type = 1;
3102 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3103 /** Must match MP tables ID */
3104 ioapic->u8IOApicId = cpus;
3105 ioapic->u8Reserved = 0;
3106 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3107 ioapic->u32GSIB = RT_H2LE_U32(0);
3108
3109 /* Interrupt Source Overrides */
3110 /* Flags:
3111 bits[3:2]:
3112 00 conforms to the bus
3113 01 edge-triggered
3114 10 reserved
3115 11 level-triggered
3116 bits[1:0]
3117 00 conforms to the bus
3118 01 active-high
3119 10 reserved
3120 11 active-low */
3121 /* If changing, also update PDMIsaSetIrq() and MPS */
3122 ACPITBLISO* isos = madt.ISO_addr();
3123 /* Timer interrupt rule IRQ0 to GSI2 */
3124 isos[0].u8Type = 2;
3125 isos[0].u8Length = sizeof(ACPITBLISO);
3126 isos[0].u8Bus = 0; /* Must be 0 */
3127 isos[0].u8Source = 0; /* IRQ0 */
3128 isos[0].u32GSI = 2; /* connected to pin 2 */
3129 isos[0].u16Flags = 0; /* conform to the bus */
3130
3131 /* ACPI interrupt rule - IRQ9 to GSI9 */
3132 isos[1].u8Type = 2;
3133 isos[1].u8Length = sizeof(ACPITBLISO);
3134 isos[1].u8Bus = 0; /* Must be 0 */
3135 isos[1].u8Source = 9; /* IRQ9 */
3136 isos[1].u32GSI = 9; /* connected to pin 9 */
3137 isos[1].u16Flags = 0xf; /* active low, level triggered */
3138 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3139
3140 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3141 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3142}
3143
3144/**
3145 * Plant the High Performance Event Timer (HPET) descriptor.
3146 */
3147static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3148{
3149 ACPITBLHPET hpet;
3150
3151 memset(&hpet, 0, sizeof(hpet));
3152
3153 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3154 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3155 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3156 0 /* Memory address space */,
3157 64 /* Register bit width */,
3158 0 /* Bit offset */,
3159 0, /* Register access size, is it correct? */
3160 0xfed00000 /* Address */);
3161
3162 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3163 hpet.u32Number = 0;
3164 hpet.u32MinTick = 4096;
3165 hpet.u8Attributes = 0;
3166
3167 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3168
3169 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3170}
3171
3172
3173#ifdef VBOX_WITH_IOMMU_AMD
3174/**
3175 * Plant the AMD IOMMU descriptor.
3176 */
3177static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3178{
3179 ACPITBLIOMMU Ivrs;
3180 RT_ZERO(Ivrs);
3181
3182 uint16_t const uIommuBus = 0;
3183 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuAmdPciAddress);
3184 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuAmdPciAddress);
3185
3186 /* IVRS header. */
3187 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3188 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3189 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3190 | RT_BF_MAKE(ACPI_IVINFO_BF_DMA_REMAP_SUP, 0) /* Pre-boot DMA remap support not supported. */
3191 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3192 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3193 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64) /* Virt. Addr size (64 bits) */
3194 | RT_BF_MAKE(ACPI_IVINFO_BF_HT_ATS_RESV, 0); /* ATS response range reserved (only applicable for HT) */
3195
3196 /* IVHD type 10 definition block. */
3197 Ivrs.IvhdType10.u8Type = 0x10;
3198 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3199 + sizeof(Ivrs.IvhdType10Start)
3200 + sizeof(Ivrs.IvhdType10End)
3201 + sizeof(Ivrs.IvhdType10Rsvd0)
3202 + sizeof(Ivrs.IvhdType10Rsvd1)
3203 + sizeof(Ivrs.IvhdType10IoApic)
3204 + sizeof(Ivrs.IvhdType10Hpet);
3205 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3206 Ivrs.IvhdType10.u16CapOffset = IOMMU_PCI_OFF_CAP_HDR;
3207 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR;
3208 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3209 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3210 Ivrs.IvhdType10.u8Flags = ACPI_IVHD_10H_F_COHERENT; /* Remote IOTLB etc. not supported. */
3211 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3212 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3213 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3214 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3215 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3216 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3217 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3218 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3219 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3220 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3221 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3222 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3223 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3224 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3225 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3226 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3);
3227 /* Start range from BDF (00:01:00). */
3228 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3229 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3230 Ivrs.IvhdType10Start.u8DteSetting = 0;
3231 /* End range at BDF (ff:1f:7). */
3232 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3233 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3234 Ivrs.IvhdType10End.u8DteSetting = 0;
3235
3236 /* Southbridge I/O APIC special device entry. */
3237 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3238 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3239 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3240 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3241 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3242 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3243 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3244 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3245 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3246 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3247
3248 /* HPET special device entry. */
3249 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3250 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3251 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3252 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3253 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3254 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3255
3256 /* IVHD type 11 definition block. */
3257 Ivrs.IvhdType11.u8Type = 0x11;
3258 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3259 + sizeof(Ivrs.IvhdType11Start)
3260 + sizeof(Ivrs.IvhdType11End)
3261 + sizeof(Ivrs.IvhdType11Rsvd0)
3262 + sizeof(Ivrs.IvhdType11Rsvd1)
3263 + sizeof(Ivrs.IvhdType11IoApic)
3264 + sizeof(Ivrs.IvhdType11Hpet);
3265 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3266 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3267 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3268 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3269 Ivrs.IvhdType11.u8Flags = ACPI_IVHD_11H_F_COHERENT;
3270 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3271 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3272 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3273 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3274 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3275 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3276 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3277 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3278 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3279 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3280 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 1)
3281 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3282 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3283 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3284 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3)
3285 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3286 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3287 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3288 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3289 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3290 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3291 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3292 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3293 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3294 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS)
3295 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3296 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3297 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3298 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3299 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3300 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3301 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3302 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3303 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3304 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3305 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3306 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3307 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3308 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3309
3310 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3311 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3312 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3313 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3314 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3315 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3316 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3317
3318 /* Finally, Compute checksum. */
3319 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3320
3321 /* Plant the ACPI table. */
3322 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3323}
3324#endif
3325
3326
3327/**
3328 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3329 * descriptor.
3330 *
3331 * @param pDevIns The device instance.
3332 * @param pThis The ACPI shared instance data.
3333 * @param GCPhysDst Where to plant it.
3334 */
3335static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3336{
3337 struct
3338 {
3339 ACPITBLMCFG hdr;
3340 ACPITBLMCFGENTRY entry;
3341 } tbl;
3342 uint8_t u8StartBus = 0;
3343 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3344
3345 RT_ZERO(tbl);
3346
3347 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3348 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3349 tbl.entry.u8StartBus = u8StartBus;
3350 tbl.entry.u8EndBus = u8EndBus;
3351 // u16PciSegmentGroup must match _SEG in ACPI table
3352
3353 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3354
3355 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3356}
3357
3358/**
3359 * Used by acpiR3PlantTables and acpiConstruct.
3360 *
3361 * @returns Guest memory address.
3362 */
3363static uint32_t apicR3FindRsdpSpace(void)
3364{
3365 return 0xe0000;
3366}
3367
3368/**
3369 * Called by acpiR3Construct to read and allocate a custom ACPI table
3370 *
3371 * @param pDevIns The device instance.
3372 * @param ppu8CustBin Address to receive the address of the table
3373 * @param pcbCustBin Address to receive the size of the the table.
3374 * @param pszCustBinFile
3375 * @param cbBufAvail Maximum space in bytes available for the custom
3376 * table (including header).
3377 */
3378static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3379 char *pszCustBinFile, uint32_t cbBufAvail)
3380{
3381 RTFILE FileCUSTBin;
3382 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3383 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3384 if (RT_SUCCESS(rc))
3385 {
3386 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3387 if (RT_SUCCESS(rc))
3388 {
3389 /* The following checks should be in sync the AssertReleaseMsg's below. */
3390 if ( *pcbCustBin > cbBufAvail
3391 || *pcbCustBin < sizeof(ACPITBLHEADER))
3392 rc = VERR_TOO_MUCH_DATA;
3393
3394 /*
3395 * Allocate buffer for the custom table binary data.
3396 */
3397 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3398 if (*ppu8CustBin)
3399 {
3400 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3401 if (RT_FAILURE(rc))
3402 {
3403 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3404 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3405 *ppu8CustBin = NULL;
3406 }
3407 }
3408 else
3409 {
3410 rc = VERR_NO_MEMORY;
3411 }
3412 RTFileClose(FileCUSTBin);
3413 }
3414 }
3415 return rc;
3416}
3417
3418/**
3419 * Create the ACPI tables in guest memory.
3420 */
3421static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3422{
3423 int rc;
3424 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3425 RTGCPHYS32 GCPhysHpet = 0;
3426#ifdef VBOX_WITH_IOMMU_AMD
3427 RTGCPHYS32 GCPhysIommuAmd = 0;
3428#endif
3429 RTGCPHYS32 GCPhysApic = 0;
3430 RTGCPHYS32 GCPhysSsdt = 0;
3431 RTGCPHYS32 GCPhysMcfg = 0;
3432 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3433 uint32_t addend = 0;
3434#ifdef VBOX_WITH_IOMMU_AMD
3435 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3436 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3437#else
3438 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3439 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3440#endif
3441 uint32_t cAddr;
3442 uint32_t iMadt = 0;
3443 uint32_t iHpet = 0;
3444#ifdef VBOX_WITH_IOMMU_AMD
3445 uint32_t iIommuAmd = 0;
3446#endif
3447 uint32_t iSsdt = 0;
3448 uint32_t iMcfg = 0;
3449 uint32_t iCust = 0;
3450 size_t cbRsdt = sizeof(ACPITBLHEADER);
3451 size_t cbXsdt = sizeof(ACPITBLHEADER);
3452
3453 cAddr = 1; /* FADT */
3454 if (pThis->u8UseIOApic)
3455 iMadt = cAddr++; /* MADT */
3456
3457 if (pThis->fUseHpet)
3458 iHpet = cAddr++; /* HPET */
3459
3460#ifdef VBOX_WITH_IOMMU_AMD
3461 if (pThis->fUseIommu)
3462 iIommuAmd = cAddr++; /* IOMMU (AMD) */
3463#endif
3464
3465 if (pThis->fUseMcfg)
3466 iMcfg = cAddr++; /* MCFG */
3467
3468 if (pThis->cCustTbls > 0)
3469 {
3470 iCust = cAddr; /* CUST */
3471 cAddr += pThis->cCustTbls;
3472 }
3473
3474 iSsdt = cAddr++; /* SSDT */
3475
3476 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3477 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3478
3479 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3480 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3481
3482 /*
3483 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3484 * The latter starts never below 4G.
3485 */
3486 PVM pVM = PDMDevHlpGetVM(pDevIns);
3487 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3488 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3489
3490 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3491 if (pThis->fPciPref64Enabled)
3492 {
3493 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3494 if (pThis->u64PciPref64Max > u64PciPref64Min)
3495 {
3496 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3497 pThis->u64PciPref64Min = u64PciPref64Min;
3498 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3499 u64PciPref64Min, pThis->u64PciPref64Max-1));
3500 }
3501 else
3502 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3503 u64PciPref64Min, pThis->u64PciPref64Max-1));
3504 }
3505 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3506 {
3507 /* Note: This is also enforced by DevPcBios.cpp. */
3508 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3509 cbBelow4GB = UINT32_C(0xfe000000);
3510 }
3511 pThis->cbRamLow = cbBelow4GB;
3512
3513 GCPhysCur = 0;
3514 GCPhysRsdt = GCPhysCur;
3515
3516 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3517 GCPhysXsdt = GCPhysCur;
3518
3519 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3520 GCPhysFadtAcpi1 = GCPhysCur;
3521
3522 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3523 GCPhysFadtAcpi2 = GCPhysCur;
3524
3525 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3526 GCPhysFacs = GCPhysCur;
3527
3528 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3529 if (pThis->u8UseIOApic)
3530 {
3531 GCPhysApic = GCPhysCur;
3532 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3533 }
3534 if (pThis->fUseHpet)
3535 {
3536 GCPhysHpet = GCPhysCur;
3537 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3538 }
3539#ifdef VBOX_WITH_IOMMU_AMD
3540 if (pThis->fUseIommu)
3541 {
3542 GCPhysIommuAmd = GCPhysCur;
3543 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3544 }
3545#endif
3546 if (pThis->fUseMcfg)
3547 {
3548 GCPhysMcfg = GCPhysCur;
3549 /* Assume one entry */
3550 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3551 }
3552
3553 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3554 {
3555 aGCPhysCust[i] = GCPhysCur;
3556 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3557 }
3558
3559 void *pvSsdtCode = NULL;
3560 size_t cbSsdt = 0;
3561 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3562 if (RT_FAILURE(rc))
3563 return rc;
3564
3565 GCPhysSsdt = GCPhysCur;
3566 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3567
3568 GCPhysDsdt = GCPhysCur;
3569
3570 void *pvDsdtCode = NULL;
3571 size_t cbDsdt = 0;
3572 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3573 if (RT_FAILURE(rc))
3574 return rc;
3575
3576 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3577
3578 if (GCPhysCur > 0x10000)
3579 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3580 N_("Error: ACPI tables bigger than 64KB"));
3581
3582 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3583 addend = pThis->cbRamLow - 0x10000;
3584 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3585 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3586 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3587 if (pThis->u8UseIOApic)
3588 Log((" MADT 0x%08X", GCPhysApic + addend));
3589 if (pThis->fUseHpet)
3590 Log((" HPET 0x%08X", GCPhysHpet + addend));
3591 if (pThis->fUseMcfg)
3592 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3593 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3594 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3595 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3596 Log(("\n"));
3597
3598 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3599 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3600 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3601 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3602 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3603
3604 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3605 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3606 if (pThis->u8UseIOApic)
3607 {
3608 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3609 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3610 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3611 }
3612 if (pThis->fUseHpet)
3613 {
3614 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3615 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3616 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3617 }
3618#ifdef VBOX_WITH_IOMMU_AMD
3619 if (pThis->fUseIommu)
3620 {
3621 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommuAmd + addend);
3622 aGCPhysRsdt[iIommuAmd] = GCPhysIommuAmd + addend;
3623 aGCPhysXsdt[iIommuAmd] = GCPhysIommuAmd + addend;
3624 }
3625#endif
3626 if (pThis->fUseMcfg)
3627 {
3628 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3629 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3630 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3631 }
3632 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3633 {
3634 Assert(i < MAX_CUST_TABLES);
3635 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3636 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3637 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3638 uint8_t* pSig = pThisCC->apu8CustBin[i];
3639 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3640 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3641 }
3642
3643 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3644 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3645 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3646 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3647
3648 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3649 if (RT_FAILURE(rc))
3650 return rc;
3651 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3652}
3653
3654/**
3655 * @callback_method_impl{FNPCICONFIGREAD}
3656 */
3657static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3658 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3659{
3660 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3661 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3662 return rcStrict;
3663}
3664
3665/**
3666 * @callback_method_impl{FNPCICONFIGWRITE}
3667 */
3668static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3669 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3670{
3671 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3672 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3673
3674 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3675 DEVACPI_LOCK_R3(pDevIns, pThis);
3676
3677 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3678 {
3679 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3680 u32Value = SCI_INT;
3681 }
3682
3683 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3684
3685 /* Assume that the base address is only changed when the corresponding
3686 * hardware functionality is disabled. The IO region is mapped when the
3687 * functionality is enabled by the guest. */
3688
3689 if (uAddress == PMREGMISC)
3690 {
3691 RTIOPORT NewIoPortBase = 0;
3692 /* Check Power Management IO Space Enable (PMIOSE) bit */
3693 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3694 {
3695 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3696 NewIoPortBase &= 0xffc0;
3697 }
3698
3699 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
3700 AssertRC(rc);
3701 }
3702
3703 if (uAddress == SMBHSTCFG)
3704 {
3705 RTIOPORT NewIoPortBase = 0;
3706 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3707 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3708 {
3709 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3710 NewIoPortBase &= 0xfff0;
3711 }
3712
3713 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3714 AssertRC(rc);
3715 }
3716
3717 DEVACPI_UNLOCK(pDevIns, pThis);
3718 return rcStrict;
3719}
3720
3721/**
3722 * Attach a new CPU.
3723 *
3724 * @returns VBox status code.
3725 * @param pDevIns The device instance.
3726 * @param iLUN The logical unit which is being attached.
3727 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3728 *
3729 * @remarks This code path is not used during construction.
3730 */
3731static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3732{
3733 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3734 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3735 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3736
3737 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3738 ("Hot-plug flag is not set\n"),
3739 VERR_NOT_SUPPORTED);
3740 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3741
3742 /* Check if it was already attached */
3743 int rc = VINF_SUCCESS;
3744 DEVACPI_LOCK_R3(pDevIns, pThis);
3745 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3746 {
3747 PPDMIBASE IBaseTmp;
3748 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3749 if (RT_SUCCESS(rc))
3750 {
3751 /* Enable the CPU */
3752 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3753
3754 /*
3755 * Lock the CPU because we don't know if the guest will use it or not.
3756 * Prevents ejection while the CPU is still used
3757 */
3758 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3759 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3760 pThis->u32CpuEvent = iLUN;
3761
3762 /* Notify the guest */
3763 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3764 }
3765 }
3766 DEVACPI_UNLOCK(pDevIns, pThis);
3767 return rc;
3768}
3769
3770/**
3771 * Detach notification.
3772 *
3773 * @param pDevIns The device instance.
3774 * @param iLUN The logical unit which is being detached.
3775 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3776 */
3777static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3778{
3779 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3780
3781 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3782
3783 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3784 ("Hot-plug flag is not set\n"));
3785
3786 /* Check if it was already detached */
3787 DEVACPI_LOCK_R3(pDevIns, pThis);
3788 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3789 {
3790 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3791 {
3792 /* Disable the CPU */
3793 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3794 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3795 pThis->u32CpuEvent = iLUN;
3796
3797 /* Notify the guest */
3798 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3799 }
3800 else
3801 AssertMsgFailed(("CPU is still locked by the guest\n"));
3802 }
3803 DEVACPI_UNLOCK(pDevIns, pThis);
3804}
3805
3806/**
3807 * @interface_method_impl{PDMDEVREG,pfnResume}
3808 */
3809static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3810{
3811 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3812 if (pThis->fSetWakeupOnResume)
3813 {
3814 Log(("acpiResume: setting WAK_STS\n"));
3815 pThis->fSetWakeupOnResume = false;
3816 pThis->pm1a_sts |= WAK_STS;
3817 }
3818}
3819
3820/**
3821 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3822 */
3823static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3824{
3825 RT_NOREF(enmCtx);
3826 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3827 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3828 acpiR3PlantTables(pDevIns, pThis, pThisCC);
3829}
3830
3831/**
3832 * @interface_method_impl{PDMDEVREG,pfnReset}
3833 */
3834static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3835{
3836 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3837 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3838
3839 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3840 acpiSetIrq(pDevIns, 0);
3841
3842 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3843 pThis->pm1a_en = 0;
3844 pThis->pm1a_sts = 0;
3845 pThis->pm1a_ctl = 0;
3846 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3847 pThis->uPmTimerVal = 0;
3848 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3849 pThis->uPmTimeOld = pThis->uPmTimerVal;
3850 pThis->uBatteryIndex = 0;
3851 pThis->uSystemInfoIndex = 0;
3852 pThis->gpe0_en = 0;
3853 pThis->gpe0_sts = 0;
3854 pThis->uSleepState = 0;
3855 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
3856
3857 /* Real device behavior is resetting only the PM controller state,
3858 * but we're additionally doing the job of the BIOS. */
3859 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
3860 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3861
3862 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3863 * state. Real device behavior is only the SMBus controller state reset,
3864 * but we're additionally doing the job of the BIOS. */
3865 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3866 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3867 acpiR3SMBusResetDevice(pThis);
3868}
3869
3870/**
3871 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3872 */
3873static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3874{
3875 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3876 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3877 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3878
3879 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3880 {
3881 if (pThisCC->apu8CustBin[i])
3882 {
3883 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
3884 pThisCC->apu8CustBin[i] = NULL;
3885 }
3886 }
3887 return VINF_SUCCESS;
3888}
3889
3890/**
3891 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3892 */
3893static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3894{
3895 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3896 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3897 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3898 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3899
3900 /*
3901 * Init data and set defaults.
3902 */
3903 /** @todo move more of the code up! */
3904
3905 pThisCC->pDevIns = pDevIns;
3906 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
3907 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
3908 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
3909 pThis->u32CpuEventType = 0;
3910 pThis->u32CpuEvent = UINT32_C(0xffffffff);
3911
3912 /* The first CPU can't be attached/detached */
3913 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
3914 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
3915
3916 /* IBase */
3917 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
3918 /* IACPIPort */
3919 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
3920 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
3921 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
3922 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
3923 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
3924 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
3925 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
3926
3927 /*
3928 * Set the default critical section to NOP (related to the PM timer).
3929 */
3930 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3931 AssertRCReturn(rc, rc);
3932
3933 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
3934 AssertRCReturn(rc, rc);
3935
3936 /*
3937 * Validate and read the configuration.
3938 */
3939 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
3940 "IOAPIC"
3941 "|NumCPUs"
3942 "|HpetEnabled"
3943 "|McfgEnabled"
3944 "|McfgBase"
3945 "|McfgLength"
3946 "|PciPref64Enabled"
3947 "|PciPref64LimitGB"
3948 "|SmcEnabled"
3949 "|FdcEnabled"
3950 "|ShowRtc"
3951 "|ShowCpu"
3952 "|NicPciAddress"
3953 "|AudioPciAddress"
3954 "|NvmePciAddress"
3955 "|IocPciAddress"
3956 "|HostBusPciAddress"
3957 "|EnableSuspendToDisk"
3958 "|PowerS1Enabled"
3959 "|PowerS4Enabled"
3960 "|CpuHotPlug"
3961 "|AmlFilePath"
3962 "|Serial0IoPortBase"
3963 "|Serial1IoPortBase"
3964 "|Serial2IoPortBase"
3965 "|Serial3IoPortBase"
3966 "|Serial0Irq"
3967 "|Serial1Irq"
3968 "|Serial2Irq"
3969 "|Serial3Irq"
3970 "|AcpiOemId"
3971 "|AcpiCreatorId"
3972 "|AcpiCreatorRev"
3973 "|CustomTable"
3974 "|CustomTable0"
3975 "|CustomTable1"
3976 "|CustomTable2"
3977 "|CustomTable3"
3978 "|Parallel0IoPortBase"
3979 "|Parallel1IoPortBase"
3980 "|Parallel0Irq"
3981 "|Parallel1Irq"
3982 "|IommuAmdEnabled"
3983 "|IommuAmdPciAddress"
3984 "|SbIoApicPciAddress"
3985 , "");
3986
3987 /* query whether we are supposed to present an IOAPIC */
3988 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
3989 if (RT_FAILURE(rc))
3990 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
3991
3992 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
3993 if (RT_FAILURE(rc))
3994 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
3995
3996 /* query whether we are supposed to present an FDC controller */
3997 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
3998 if (RT_FAILURE(rc))
3999 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
4000
4001 /* query whether we are supposed to present HPET */
4002 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
4003 if (RT_FAILURE(rc))
4004 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
4005 /* query MCFG configuration */
4006 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
4007 if (RT_FAILURE(rc))
4008 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4009 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4010 if (RT_FAILURE(rc))
4011 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4012 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4013
4014 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4015 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4016 if (RT_FAILURE(rc))
4017 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4018
4019 /* query the limit of the the 64-bit prefetchable memory window */
4020 uint64_t u64PciPref64MaxGB;
4021 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4022 if (RT_FAILURE(rc))
4023 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4024 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4025
4026 /* query whether we are supposed to present SMC */
4027 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4028 if (RT_FAILURE(rc))
4029 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4030
4031 /* query whether we are supposed to present RTC object */
4032 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4033 if (RT_FAILURE(rc))
4034 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4035
4036 /* query whether we are supposed to present CPU objects */
4037 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4038 if (RT_FAILURE(rc))
4039 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4040
4041 /* query primary NIC PCI address (GIGE) */
4042 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4043 if (RT_FAILURE(rc))
4044 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4045
4046 /* query HD Audio PCI address (HDAA) */
4047 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4048 if (RT_FAILURE(rc))
4049 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4050
4051 /* query NVMe PCI address (NVMA) */
4052 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4053 if (RT_FAILURE(rc))
4054 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4055
4056 /* query IO controller (southbridge) PCI address */
4057 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4058 if (RT_FAILURE(rc))
4059 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4060
4061 /* query host bus controller PCI address */
4062 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4063 if (RT_FAILURE(rc))
4064 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4065
4066 /* query whether S1 power state should be exposed */
4067 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4068 if (RT_FAILURE(rc))
4069 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4070
4071 /* query whether S4 power state should be exposed */
4072 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4073 if (RT_FAILURE(rc))
4074 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4075
4076 /* query whether S1 power state should save the VM state */
4077 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4078 if (RT_FAILURE(rc))
4079 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4080
4081 /* query whether we are allow CPU hot plugging */
4082 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4083 if (RT_FAILURE(rc))
4084 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4085
4086 /* query serial info */
4087 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4088 if (RT_FAILURE(rc))
4089 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4090
4091 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4092 if (RT_FAILURE(rc))
4093 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4094
4095 /* Serial 1 is enabled, get config data */
4096 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4097 if (RT_FAILURE(rc))
4098 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4099
4100 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4101 if (RT_FAILURE(rc))
4102 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4103
4104 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4105 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4106 if (RT_FAILURE(rc))
4107 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4108
4109 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4110 if (RT_FAILURE(rc))
4111 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4112
4113 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4114 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4115 if (RT_FAILURE(rc))
4116 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4117
4118 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4119 if (RT_FAILURE(rc))
4120 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4121 /*
4122 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4123 * the corresponding parallel port is not enabled.
4124 */
4125 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4126 if (RT_FAILURE(rc))
4127 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4128
4129 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4130 if (RT_FAILURE(rc))
4131 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4132
4133 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4134 if (RT_FAILURE(rc))
4135 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4136
4137 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4138 if (RT_FAILURE(rc))
4139 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4140
4141#ifdef VBOX_WITH_IOMMU_AMD
4142 /* Query whether an IOMMU AMD is enabled. */
4143 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommu, false);
4144 if (RT_FAILURE(rc))
4145 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuEnabled\""));
4146
4147 if (pThis->fUseIommu)
4148 {
4149 /* Query IOMMU AMD address (IOMA). */
4150 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuAmdPciAddress", &pThis->u32IommuAmdPciAddress, 0);
4151 if (RT_FAILURE(rc))
4152 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdAddress\""));
4153
4154 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4155 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress, 0);
4156 if (RT_FAILURE(rc))
4157 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4158
4159 /* Warn if the IOMMU Address is at the PCI host-bridge address. */
4160 /** @todo We should eventually not assign the IOMMU at this address, see
4161 * @bugref{9654#c53}. */
4162 if (!pThis->u32IommuAmdPciAddress)
4163 LogRel(("ACPI: Warning! AMD IOMMU assigned the PCI host bridge address.\n"));
4164
4165 /* Warn if the SB IOAPIC is not at the required address if an AMD IOMMU is configured. */
4166 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4167 {
4168 /** @todo Maybe make this a VM startup failure later. */
4169 LogRel(("ACPI: Warning! Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4170 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4171 }
4172 }
4173#endif
4174
4175 /* Try to attach the other CPUs */
4176 for (unsigned i = 1; i < pThis->cCpus; i++)
4177 {
4178 if (pThis->fCpuHotPlug)
4179 {
4180 PPDMIBASE IBaseTmp;
4181 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4182
4183 if (RT_SUCCESS(rc))
4184 {
4185 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4186 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4187 Log(("acpi: Attached CPU %u\n", i));
4188 }
4189 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4190 Log(("acpi: CPU %u not attached yet\n", i));
4191 else
4192 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4193 }
4194 else
4195 {
4196 /* CPU is always attached if hot-plug is not enabled. */
4197 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4198 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4199 }
4200 }
4201
4202 char szOemId[16];
4203 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4204 if (RT_FAILURE(rc))
4205 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4206 size_t cchOemId = strlen(szOemId);
4207 if (cchOemId > 6)
4208 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4209 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4210 memcpy(pThis->au8OemId, szOemId, cchOemId);
4211
4212 char szCreatorId[16];
4213 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4214 if (RT_FAILURE(rc))
4215 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4216 size_t cchCreatorId = strlen(szCreatorId);
4217 if (cchCreatorId > 4)
4218 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4219 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4220 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4221
4222 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4223 if (RT_FAILURE(rc))
4224 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4225
4226 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4227
4228 /*
4229 * Load custom ACPI tables.
4230 */
4231 /* Total space available for custom ACPI tables */
4232 /** @todo define as appropriate, remove as a magic number, and document
4233 * limitation in product manual */
4234 uint32_t cbBufAvail = 3072;
4235 pThis->cCustTbls = 0;
4236
4237 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4238 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4239 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4240 {
4241 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4242
4243 /*
4244 * Get the custom table binary file name.
4245 */
4246 char *pszCustBinFile = NULL;
4247 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4248 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4249 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4250 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4251 {
4252 rc = VINF_SUCCESS;
4253 pszCustBinFile = NULL;
4254 }
4255 else if (RT_FAILURE(rc))
4256 return PDMDEV_SET_ERROR(pDevIns, rc,
4257 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4258 else if (!*pszCustBinFile)
4259 {
4260 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4261 pszCustBinFile = NULL;
4262 }
4263
4264 /*
4265 * Determine the custom table binary size, open specified file in the process.
4266 */
4267 if (pszCustBinFile)
4268 {
4269 uint32_t idxCust = pThis->cCustTbls;
4270 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4271 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4272 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4273 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4274 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4275 if (RT_FAILURE(rc))
4276 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4277 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4278
4279 /* Update custom OEM attributes based on custom table */
4280 /** @todo is it intended for custom tables to overwrite user provided values above? */
4281 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4282 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4283 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4284 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4285 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4286 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4287
4288 pThis->cCustTbls++;
4289 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
4290 }
4291 }
4292
4293 /* Set default PM port base */
4294 pThis->uPmIoPortBase = PM_PORT_BASE;
4295
4296 /* Set default SMBus port base */
4297 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4298
4299 /*
4300 * FDC and SMC try to use the same non-shareable interrupt (6),
4301 * enable only one device.
4302 */
4303 if (pThis->fUseSmc)
4304 pThis->fUseFdc = false;
4305
4306 /*
4307 * Plant ACPI tables.
4308 */
4309 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4310 * au8RSDPPage here. However, there should be no harm in doing it
4311 * twice, so the lazy bird is taking the quick way out for now. */
4312 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4313 if (!GCPhysRsdp)
4314 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4315
4316 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4317 AssertRCReturn(rc, rc);
4318
4319 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4320 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4321 AssertRCReturn(rc, rc);
4322
4323 /*
4324 * Create the PM I/O ports. These can be unmapped and remapped.
4325 */
4326 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4327 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4328 AssertRCReturn(rc, rc);
4329 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4330 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4331 AssertRCReturn(rc, rc);
4332 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4333 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4334 AssertRCReturn(rc, rc);
4335 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4336 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4337 AssertRCReturn(rc, rc);
4338 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4339 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4340 AssertRCReturn(rc, rc);
4341 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4342 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4343 AssertRCReturn(rc, rc);
4344 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4345 AssertRCReturn(rc, rc);
4346
4347 /*
4348 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4349 */
4350 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4351 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4352 AssertRCReturn(rc, rc);
4353 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4354 AssertRCReturn(rc, rc);
4355
4356 /*
4357 * Create and map the fixed I/O ports.
4358 */
4359 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4360 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4361 AssertRCReturn(rc, rc);
4362#ifdef DEBUG_ACPI
4363 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4364 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4365 AssertRCReturn(rc, rc);
4366 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4367 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4368 AssertRCReturn(rc, rc);
4369#endif
4370 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4371 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4372 AssertRCReturn(rc, rc);
4373 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4374 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4375 AssertRCReturn(rc, rc);
4376 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4377 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4378 AssertRCReturn(rc, rc);
4379 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4380 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4381 AssertRCReturn(rc, rc);
4382 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4383 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4384 AssertRCReturn(rc, rc);
4385
4386 /*
4387 * Create the PM timer.
4388 */
4389 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4390 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "ACPI PM", &pThis->hPmTimer);
4391 AssertRCReturn(rc, rc);
4392
4393 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4394 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4395 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4396 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4397
4398 /*
4399 * Set up the PCI device.
4400 */
4401 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4402 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4403
4404 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4405 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4406
4407 /* See p. 50 of PIIX4 manual */
4408 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4409 PDMPciDevSetStatus(pPciDev, 0x0280);
4410
4411 PDMPciDevSetRevisionId(pPciDev, 0x08);
4412
4413 PDMPciDevSetClassProg(pPciDev, 0x00);
4414 PDMPciDevSetClassSub(pPciDev, 0x80);
4415 PDMPciDevSetClassBase(pPciDev, 0x06);
4416
4417 PDMPciDevSetHeaderType(pPciDev, 0x80);
4418
4419 PDMPciDevSetBIST(pPciDev, 0x00);
4420
4421 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4422 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4423
4424 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4425 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4426
4427 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4428 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4429 acpiR3SMBusResetDevice(pThis);
4430
4431 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4432 AssertRCReturn(rc, rc);
4433
4434 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4435 AssertRCReturn(rc, rc);
4436
4437 /*
4438 * Register the saved state.
4439 */
4440 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4441 AssertRCReturn(rc, rc);
4442
4443 /*
4444 * Get the corresponding connector interface
4445 */
4446 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4447 if (RT_SUCCESS(rc))
4448 {
4449 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4450 if (!pThisCC->pDrv)
4451 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4452 }
4453 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4454 {
4455 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4456 rc = VINF_SUCCESS;
4457 }
4458 else
4459 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4460
4461 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4462
4463 return rc;
4464}
4465
4466#else /* !IN_RING3 */
4467
4468/**
4469 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4470 */
4471static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4472{
4473 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4474 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4475
4476 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4477 AssertRCReturn(rc, rc);
4478
4479 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4480 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4481 AssertRCReturn(rc, rc);
4482
4483 return VINF_SUCCESS;
4484}
4485
4486#endif /* !IN_RING3 */
4487
4488/**
4489 * The device registration structure.
4490 */
4491const PDMDEVREG g_DeviceACPI =
4492{
4493 /* .u32Version = */ PDM_DEVREG_VERSION,
4494 /* .uReserved0 = */ 0,
4495 /* .szName = */ "acpi",
4496 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4497 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4498 /* .cMaxInstances = */ ~0U,
4499 /* .uSharedVersion = */ 42,
4500 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4501 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4502 /* .cbInstanceRC = */ 0,
4503 /* .cMaxPciDevices = */ 1,
4504 /* .cMaxMsixVectors = */ 0,
4505 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4506#if defined(IN_RING3)
4507 /* .pszRCMod = */ "VBoxDDRC.rc",
4508 /* .pszR0Mod = */ "VBoxDDR0.r0",
4509 /* .pfnConstruct = */ acpiR3Construct,
4510 /* .pfnDestruct = */ acpiR3Destruct,
4511 /* .pfnRelocate = */ NULL,
4512 /* .pfnMemSetup = */ acpiR3MemSetup,
4513 /* .pfnPowerOn = */ NULL,
4514 /* .pfnReset = */ acpiR3Reset,
4515 /* .pfnSuspend = */ NULL,
4516 /* .pfnResume = */ acpiR3Resume,
4517 /* .pfnAttach = */ acpiR3Attach,
4518 /* .pfnDetach = */ acpiR3Detach,
4519 /* .pfnQueryInterface = */ NULL,
4520 /* .pfnInitComplete = */ NULL,
4521 /* .pfnPowerOff = */ NULL,
4522 /* .pfnSoftReset = */ NULL,
4523 /* .pfnReserved0 = */ NULL,
4524 /* .pfnReserved1 = */ NULL,
4525 /* .pfnReserved2 = */ NULL,
4526 /* .pfnReserved3 = */ NULL,
4527 /* .pfnReserved4 = */ NULL,
4528 /* .pfnReserved5 = */ NULL,
4529 /* .pfnReserved6 = */ NULL,
4530 /* .pfnReserved7 = */ NULL,
4531#elif defined(IN_RING0)
4532 /* .pfnEarlyConstruct = */ NULL,
4533 /* .pfnConstruct = */ acpiRZConstruct,
4534 /* .pfnDestruct = */ NULL,
4535 /* .pfnFinalDestruct = */ NULL,
4536 /* .pfnRequest = */ NULL,
4537 /* .pfnReserved0 = */ NULL,
4538 /* .pfnReserved1 = */ NULL,
4539 /* .pfnReserved2 = */ NULL,
4540 /* .pfnReserved3 = */ NULL,
4541 /* .pfnReserved4 = */ NULL,
4542 /* .pfnReserved5 = */ NULL,
4543 /* .pfnReserved6 = */ NULL,
4544 /* .pfnReserved7 = */ NULL,
4545#elif defined(IN_RC)
4546 /* .pfnConstruct = */ acpiRZConstruct,
4547 /* .pfnReserved0 = */ NULL,
4548 /* .pfnReserved1 = */ NULL,
4549 /* .pfnReserved2 = */ NULL,
4550 /* .pfnReserved3 = */ NULL,
4551 /* .pfnReserved4 = */ NULL,
4552 /* .pfnReserved5 = */ NULL,
4553 /* .pfnReserved6 = */ NULL,
4554 /* .pfnReserved7 = */ NULL,
4555#else
4556# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4557#endif
4558 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4559};
4560
4561#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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