VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 88340

Last change on this file since 88340 was 88340, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 WIP.
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1/* $Id: DevACPI.cpp 88340 2021-04-01 04:03:48Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <VBox/pci.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#include <iprt/asm-math.h>
33#include <iprt/file.h>
34#ifdef IN_RING3
35# include <iprt/alloc.h>
36# include <iprt/string.h>
37# include <iprt/uuid.h>
38#endif /* IN_RING3 */
39#ifdef VBOX_WITH_IOMMU_AMD
40# include <VBox/iommu-amd.h>
41#endif
42#ifdef VBOX_WITH_IOMMU_INTEL
43# include <VBox/iommu-intel.h>
44#endif
45
46#include "VBoxDD.h"
47#ifdef VBOX_WITH_IOMMU_AMD
48# include "../Bus/DevIommuAmd.h"
49#endif
50#ifdef VBOX_WITH_IOMMU_INTEL
51# include "../Bus/DevIommuIntel.h"
52#endif
53
54#ifdef LOG_ENABLED
55# define DEBUG_ACPI
56#endif
57
58
59/*********************************************************************************************************************************
60* Defined Constants And Macros *
61*********************************************************************************************************************************/
62#ifdef IN_RING3
63/** Locks the device state, ring-3 only. */
64# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
65 do { \
66 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
67 AssertRC(rcLock); \
68 } while (0)
69#endif
70/** Unlocks the device state (all contexts). */
71#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
72 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
73
74
75#define DEBUG_HEX 0x3000
76#define DEBUG_CHR 0x3001
77
78/** PM Base Address PCI config space offset */
79#define PMBA 0x40
80/** PM Miscellaneous Power Management PCI config space offset */
81#define PMREGMISC 0x80
82
83#define PM_TMR_FREQ 3579545
84/** Default base for PM PIIX4 device */
85#define PM_PORT_BASE 0x4000
86/* Port offsets in PM device */
87enum
88{
89 PM1a_EVT_OFFSET = 0x00,
90 PM1b_EVT_OFFSET = -1, /**< not supported */
91 PM1a_CTL_OFFSET = 0x04,
92 PM1b_CTL_OFFSET = -1, /**< not supported */
93 PM2_CTL_OFFSET = -1, /**< not supported */
94 PM_TMR_OFFSET = 0x08,
95 GPE0_OFFSET = 0x20,
96 GPE1_OFFSET = -1 /**< not supported */
97};
98
99/* Maximum supported number of custom ACPI tables */
100#define MAX_CUST_TABLES 4
101
102/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
103#define PM_TMR_32BIT
104
105#define BAT_INDEX 0x00004040
106#define BAT_DATA 0x00004044
107#define SYSI_INDEX 0x00004048
108#define SYSI_DATA 0x0000404c
109#define ACPI_RESET_BLK 0x00004050
110
111/* PM1x status register bits */
112#define TMR_STS RT_BIT(0)
113#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
114#define BM_STS RT_BIT(4)
115#define GBL_STS RT_BIT(5)
116#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
117#define PWRBTN_STS RT_BIT(8)
118#define SLPBTN_STS RT_BIT(9)
119#define RTC_STS RT_BIT(10)
120#define IGN_STS RT_BIT(11)
121#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
122#define WAK_STS RT_BIT(15)
123#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
124
125/* PM1x enable register bits */
126#define TMR_EN RT_BIT(0)
127#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
128#define GBL_EN RT_BIT(5)
129#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
130#define PWRBTN_EN RT_BIT(8)
131#define SLPBTN_EN RT_BIT(9)
132#define RTC_EN RT_BIT(10)
133#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
134#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
135#define IGN_EN 0
136
137/* PM1x control register bits */
138#define SCI_EN RT_BIT(0)
139#define BM_RLD RT_BIT(1)
140#define GBL_RLS RT_BIT(2)
141#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
142#define IGN_CNT RT_BIT(9)
143#define SLP_TYPx_SHIFT 10
144#define SLP_TYPx_MASK 7
145#define SLP_EN RT_BIT(13)
146#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
147#define RSR_CNT (RSR1_CNT | RSR2_CNT)
148
149#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
150
151enum
152{
153 BAT_STATUS_STATE = 0x00, /**< BST battery state */
154 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
155 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
156 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
157 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
158 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
159 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
160 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
161 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
162 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
163 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
164 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
165 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
166 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
167 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
168 BAT_INDEX_LAST
169};
170
171enum
172{
173 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
174 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
175};
176
177enum
178{
179 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
180 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
181 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
182 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
183 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
184 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
185 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
186 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
187 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
188 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
189 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
190 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
191 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
192 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
193 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
194 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
195 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
196 SYSTEM_INFO_INDEX_POWER_STATES = 17,
197 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
198 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
199 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
200 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
201 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
202 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
203 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
204 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
205 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
206 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
207 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
208 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
209 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
210 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
211 SYSTEM_INFO_INDEX_IOMMU_ADDRESS = 32, /**< IOMMU PCI address, or 0 */
212 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
213 SYSTEM_INFO_INDEX_END = 34,
214 SYSTEM_INFO_INDEX_INVALID = 0x80,
215 SYSTEM_INFO_INDEX_VALID = 0x200
216};
217
218#define AC_OFFLINE 0
219#define AC_ONLINE 1
220
221#define BAT_TECH_PRIMARY 1
222#define BAT_TECH_SECONDARY 2
223
224#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
225#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
226#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
227#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
228#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
229
230/** SMBus Base Address PCI config space offset */
231#define SMBBA 0x90
232/** SMBus Host Configuration PCI config space offset */
233#define SMBHSTCFG 0xd2
234/** SMBus Slave Command PCI config space offset */
235#define SMBSLVC 0xd3
236/** SMBus Slave Shadow Port 1 PCI config space offset */
237#define SMBSHDW1 0xd4
238/** SMBus Slave Shadow Port 2 PCI config space offset */
239#define SMBSHDW2 0xd5
240/** SMBus Revision Identification PCI config space offset */
241#define SMBREV 0xd6
242
243#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
244#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
245#define SMBHSTCFG_INTRSEL_SMI 0
246#define SMBHSTCFG_INTRSEL_IRQ9 4
247#define SMBHSTCFG_INTRSEL_SHIFT 1
248
249/** Default base for SMBus PIIX4 device */
250#define SMB_PORT_BASE 0x4100
251
252/** SMBus Host Status Register I/O offset */
253#define SMBHSTSTS_OFF 0x0000
254/** SMBus Slave Status Register I/O offset */
255#define SMBSLVSTS_OFF 0x0001
256/** SMBus Host Count Register I/O offset */
257#define SMBHSTCNT_OFF 0x0002
258/** SMBus Host Command Register I/O offset */
259#define SMBHSTCMD_OFF 0x0003
260/** SMBus Host Address Register I/O offset */
261#define SMBHSTADD_OFF 0x0004
262/** SMBus Host Data 0 Register I/O offset */
263#define SMBHSTDAT0_OFF 0x0005
264/** SMBus Host Data 1 Register I/O offset */
265#define SMBHSTDAT1_OFF 0x0006
266/** SMBus Block Data Register I/O offset */
267#define SMBBLKDAT_OFF 0x0007
268/** SMBus Slave Control Register I/O offset */
269#define SMBSLVCNT_OFF 0x0008
270/** SMBus Shadow Command Register I/O offset */
271#define SMBSHDWCMD_OFF 0x0009
272/** SMBus Slave Event Register I/O offset */
273#define SMBSLVEVT_OFF 0x000a
274/** SMBus Slave Data Register I/O offset */
275#define SMBSLVDAT_OFF 0x000c
276
277#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
278#define SMBHSTSTS_INTER RT_BIT(1)
279#define SMBHSTSTS_DEV_ERR RT_BIT(2)
280#define SMBHSTSTS_BUS_ERR RT_BIT(3)
281#define SMBHSTSTS_FAILED RT_BIT(4)
282#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
283
284#define SMBSLVSTS_WRITE_MASK 0x3c
285
286#define SMBHSTCNT_INTEREN RT_BIT(0)
287#define SMBHSTCNT_KILL RT_BIT(1)
288#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
289#define SMBHSTCNT_START RT_BIT(6)
290#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
291
292#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
293
294
295/*********************************************************************************************************************************
296* Structures and Typedefs *
297*********************************************************************************************************************************/
298/**
299 * The shared ACPI device state.
300 */
301typedef struct ACPISTATE
302{
303 /** Critical section protecting the ACPI state. */
304 PDMCRITSECT CritSect;
305
306 uint16_t pm1a_en;
307 uint16_t pm1a_sts;
308 uint16_t pm1a_ctl;
309 /** Number of logical CPUs in guest */
310 uint16_t cCpus;
311
312 uint64_t u64PmTimerInitial;
313 /** The PM timer. */
314 TMTIMERHANDLE hPmTimer;
315 /* PM Timer last calculated value */
316 uint32_t uPmTimerVal;
317 uint32_t Alignment0;
318
319 uint32_t gpe0_en;
320 uint32_t gpe0_sts;
321
322 uint32_t uBatteryIndex;
323 uint32_t au8BatteryInfo[13];
324
325 uint32_t uSystemInfoIndex;
326 uint32_t u32Alignment0;
327 uint64_t u64RamSize;
328 /** Offset of the 64-bit prefetchable memory window. */
329 uint64_t u64PciPref64Min;
330 /** Limit of the 64-bit prefetchable memory window. */
331 uint64_t u64PciPref64Max;
332 /** The number of bytes below 4GB. */
333 uint32_t cbRamLow;
334
335 /** Current ACPI S* state. We support S0 and S5. */
336 uint32_t uSleepState;
337 uint8_t au8RSDPPage[0x1000];
338 /** This is a workaround for incorrect index field handling by Intels ACPICA.
339 * The system info _INI method writes to offset 0x200. We either observe a
340 * write request to index 0x80 (in that case we don't change the index) or a
341 * write request to offset 0x200 (in that case we divide the index value by
342 * 4. Note that the _STA method is sometimes called prior to the _INI method
343 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
344 * acpiR3BatIndexWrite() for handling this. */
345 uint8_t u8IndexShift;
346 /** provide an I/O-APIC */
347 uint8_t u8UseIOApic;
348 /** provide a floppy controller */
349 bool fUseFdc;
350 /** If High Precision Event Timer device should be supported */
351 bool fUseHpet;
352 /** If System Management Controller device should be supported */
353 bool fUseSmc;
354 /** the guest handled the last power button event */
355 bool fPowerButtonHandled;
356 /** If ACPI CPU device should be shown */
357 bool fShowCpu;
358 /** If Real Time Clock ACPI object to be shown */
359 bool fShowRtc;
360 /** I/O port address of PM device. */
361 RTIOPORT uPmIoPortBase;
362 /** I/O port address of SMBus device. */
363 RTIOPORT uSMBusIoPortBase;
364 /** Which CPU to check for the locked status. */
365 uint32_t idCpuLockCheck;
366 /** Array of flags of attached CPUs */
367 VMCPUSET CpuSetAttached;
368 /** Mask of locked CPUs (used by the guest). */
369 VMCPUSET CpuSetLocked;
370 /** The CPU event type. */
371 uint32_t u32CpuEventType;
372 /** The CPU id affected. */
373 uint32_t u32CpuEvent;
374 /** Flag whether CPU hot plugging is enabled. */
375 bool fCpuHotPlug;
376 /** If MCFG ACPI table shown to the guest */
377 bool fUseMcfg;
378 /** if the 64-bit prefetchable memory window is shown to the guest */
379 bool fPciPref64Enabled;
380 /** If the IOMMU (AMD) device should be enabled */
381 bool fUseIommuAmd;
382 /** If the IOMMU (Intel) device should be enabled */
383 bool fUseIommuIntel;
384 /** Padding. */
385 bool afPadding0[3];
386 /** Primary NIC PCI address. */
387 uint32_t u32NicPciAddress;
388 /** HD Audio PCI address. */
389 uint32_t u32AudioPciAddress;
390 /** Primary NVMe controller PCI address. */
391 uint32_t u32NvmePciAddress;
392 /** Flag whether S1 power state is enabled. */
393 bool fS1Enabled;
394 /** Flag whether S4 power state is enabled. */
395 bool fS4Enabled;
396 /** Flag whether S1 triggers a state save. */
397 bool fSuspendToSavedState;
398 /** Flag whether to set WAK_STS on resume (restore included). */
399 bool fSetWakeupOnResume;
400 /** PCI address of the IO controller device. */
401 uint32_t u32IocPciAddress;
402 /** PCI address of the host bus controller device. */
403 uint32_t u32HbcPciAddress;
404 /** PCI address of the IOMMU device. */
405 uint32_t u32IommuPciAddress;
406 /** PCI address of the southbridge I/O APIC device. */
407 uint32_t u32SbIoApicPciAddress;
408
409 /** Physical address of PCI config space MMIO region */
410 uint64_t u64PciConfigMMioAddress;
411 /** Length of PCI config space MMIO region */
412 uint64_t u64PciConfigMMioLength;
413 /** Serial 0 IRQ number */
414 uint8_t uSerial0Irq;
415 /** Serial 1 IRQ number */
416 uint8_t uSerial1Irq;
417 /** Serial 2 IRQ number */
418 uint8_t uSerial2Irq;
419 /** Serial 3 IRQ number */
420 uint8_t uSerial3Irq;
421 /** Serial 0 IO port base */
422 RTIOPORT uSerial0IoPortBase;
423 /** Serial 1 IO port base */
424 RTIOPORT uSerial1IoPortBase;
425 /** Serial 2 IO port base */
426 RTIOPORT uSerial2IoPortBase;
427 /** Serial 3 IO port base */
428 RTIOPORT uSerial3IoPortBase;
429
430 /** @name Parallel port config bits
431 * @{ */
432 /** Parallel 0 IO port base */
433 RTIOPORT uParallel0IoPortBase;
434 /** Parallel 1 IO port base */
435 RTIOPORT uParallel1IoPortBase;
436 /** Parallel 0 IRQ number */
437 uint8_t uParallel0Irq;
438 /** Parallel 1 IRQ number */
439 uint8_t uParallel1Irq;
440 /** @} */
441
442 /** Number of custom ACPI tables */
443 uint8_t cCustTbls;
444 /** ACPI OEM ID */
445 uint8_t au8OemId[6];
446 /** ACPI Crator ID */
447 uint8_t au8CreatorId[4];
448 uint8_t abAlignment2[3];
449 /** ACPI Crator Rev */
450 uint32_t u32CreatorRev;
451 /** ACPI custom OEM Tab ID */
452 uint8_t au8OemTabId[8];
453 /** ACPI custom OEM Rev */
454 uint32_t u32OemRevision;
455
456 /** SMBus Host Status Register */
457 uint8_t u8SMBusHstSts;
458 /** SMBus Slave Status Register */
459 uint8_t u8SMBusSlvSts;
460 /** SMBus Host Control Register */
461 uint8_t u8SMBusHstCnt;
462 /** SMBus Host Command Register */
463 uint8_t u8SMBusHstCmd;
464 /** SMBus Host Address Register */
465 uint8_t u8SMBusHstAdd;
466 /** SMBus Host Data 0 Register */
467 uint8_t u8SMBusHstDat0;
468 /** SMBus Host Data 1 Register */
469 uint8_t u8SMBusHstDat1;
470 /** SMBus Slave Control Register */
471 uint8_t u8SMBusSlvCnt;
472 /** SMBus Slave Event Register */
473 uint16_t u16SMBusSlvEvt;
474 /** SMBus Slave Data Register */
475 uint16_t u16SMBusSlvDat;
476 /** SMBus Shadow Command Register */
477 uint8_t u8SMBusShdwCmd;
478 /** SMBus Host Block Index */
479 uint8_t u8SMBusBlkIdx;
480 uint8_t abAlignment3[2];
481 /** SMBus Host Block Data Buffer */
482 uint8_t au8SMBusBlkDat[32];
483
484 /** @todo DEBUGGING */
485 uint32_t uPmTimeOld;
486 uint32_t uPmTimeA;
487 uint32_t uPmTimeB;
488 uint32_t Alignment5;
489
490 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
491 * @{ */
492 IOMIOPORTHANDLE hIoPortPm1aEn;
493 IOMIOPORTHANDLE hIoPortPm1aSts;
494 IOMIOPORTHANDLE hIoPortPm1aCtl;
495 IOMIOPORTHANDLE hIoPortPmTimer;
496 IOMIOPORTHANDLE hIoPortGpe0En;
497 IOMIOPORTHANDLE hIoPortGpe0Sts;
498 /** @} */
499
500 /** SMBus I/O ports (mapped/unmapped). */
501 IOMIOPORTHANDLE hIoPortSMBus;
502
503 /** @name Fixed I/O ports
504 * @{ */
505 /** ACPI SMI I/O port. */
506 IOMIOPORTHANDLE hIoPortSmi;
507 /** ACPI Debug hex I/O port. */
508 IOMIOPORTHANDLE hIoPortDebugHex;
509 /** ACPI Debug char I/O port. */
510 IOMIOPORTHANDLE hIoPortDebugChar;
511 /** ACPI Battery status index I/O port. */
512 IOMIOPORTHANDLE hIoPortBatteryIndex;
513 /** ACPI Battery status data I/O port. */
514 IOMIOPORTHANDLE hIoPortBatteryData;
515 /** ACPI system info index I/O port. */
516 IOMIOPORTHANDLE hIoPortSysInfoIndex;
517 /** ACPI system info data I/O port. */
518 IOMIOPORTHANDLE hIoPortSysInfoData;
519 /** ACPI Reset I/O port. */
520 IOMIOPORTHANDLE hIoPortReset;
521 /** @} */
522
523} ACPISTATE;
524/** Pointer to the shared ACPI device state. */
525typedef ACPISTATE *PACPISTATE;
526
527
528
529/**
530 * The ring-3 ACPI device state.
531 */
532typedef struct ACPISTATER3
533{
534 /** ACPI port base interface. */
535 PDMIBASE IBase;
536 /** ACPI port interface. */
537 PDMIACPIPORT IACPIPort;
538 /** Pointer to the device instance so we can get our bearings from
539 * interface functions. */
540 PPDMDEVINSR3 pDevIns;
541
542 /** Pointer to the driver base interface. */
543 R3PTRTYPE(PPDMIBASE) pDrvBase;
544 /** Pointer to the driver connector interface. */
545 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
546
547 /** Custom ACPI tables binary data. */
548 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
549 /** The size of the custom table binary. */
550 uint64_t acbCustBin[MAX_CUST_TABLES];
551} ACPISTATER3;
552/** Pointer to the ring-3 ACPI device state. */
553typedef ACPISTATER3 *PACPISTATER3;
554
555
556#pragma pack(1)
557
558/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
559struct ACPIGENADDR
560{
561 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
562 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
563 uint8_t u8RegisterBitOffset; /**< bit offset of register */
564 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
565 uint64_t u64Address; /**< 64-bit address of register */
566};
567AssertCompileSize(ACPIGENADDR, 12);
568
569/** Root System Description Pointer */
570struct ACPITBLRSDP
571{
572 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
573 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
574 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
575 uint8_t u8Revision; /**< revision number, currently 2 */
576#define ACPI_REVISION 2 /**< ACPI 3.0 */
577 uint32_t u32RSDT; /**< phys addr of RSDT */
578 uint32_t u32Length; /**< bytes of this table */
579 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
580 uint8_t u8ExtChecksum; /**< checksum of entire table */
581 uint8_t u8Reserved[3]; /**< reserved */
582};
583AssertCompileSize(ACPITBLRSDP, 36);
584
585/** System Description Table Header */
586struct ACPITBLHEADER
587{
588 uint8_t au8Signature[4]; /**< table identifier */
589 uint32_t u32Length; /**< length of the table including header */
590 uint8_t u8Revision; /**< revision number */
591 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
592 uint8_t au8OemId[6]; /**< OEM-supplied string */
593 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
594 uint32_t u32OemRevision; /**< OEM-supplied revision number */
595 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
596 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
597};
598AssertCompileSize(ACPITBLHEADER, 36);
599
600/** Root System Description Table */
601struct ACPITBLRSDT
602{
603 ACPITBLHEADER header;
604 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
605};
606AssertCompileSize(ACPITBLRSDT, 40);
607
608/** Extended System Description Table */
609struct ACPITBLXSDT
610{
611 ACPITBLHEADER header;
612 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
613};
614AssertCompileSize(ACPITBLXSDT, 44);
615
616/** Fixed ACPI Description Table */
617struct ACPITBLFADT
618{
619 ACPITBLHEADER header;
620 uint32_t u32FACS; /**< phys. address of FACS */
621 uint32_t u32DSDT; /**< phys. address of DSDT */
622 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
623#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
624#define INT_MODEL_MULTIPLE_APIC 2
625 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
626 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
627#define SCI_INT 9
628 uint32_t u32SMICmd; /**< system port address of SMI command port */
629#define SMI_CMD 0x0000442e
630 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
631#define ACPI_ENABLE 0xa1
632 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
633#define ACPI_DISABLE 0xa0
634 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
635 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
636 state control responsibility */
637 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
638 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
639 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
640 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
641 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
642 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
643 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
644 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
645 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
646 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
647 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
648 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
649 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
650#define GPE0_BLK_LEN 2
651 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
652#define GPE1_BLK_LEN 0
653 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
654#define GPE1_BASE 0
655 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
656 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
657#define P_LVL2_LAT 101 /**< C2 state not supported */
658 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
659#define P_LVL3_LAT 1001 /**< C3 state not supported */
660 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
661 lines from any processors memory caches */
662#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
663 uint16_t u16FlushStride; /**< cache line width */
664#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
665 uint8_t u8DutyOffset;
666 uint8_t u8DutyWidth;
667 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
668 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
669 uint8_t u8Century; /**< RTC CMOS RAM index of century */
670 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
671#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
672 (COM too?) */
673#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
674#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
675#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
676#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
677 uint8_t u8Must0_0; /**< must be 0 */
678 uint32_t u32Flags; /**< fixed feature flags */
679#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
680#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
681#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
682#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
683#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
684#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
685#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
686#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
687#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
688#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
689#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
690#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
691#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
692#define FADT_FL_CPU_SW_SLP RT_BIT(13)
693#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
694#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
695#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
696#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
697#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
698#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
699
700/* PM Timer mask and msb */
701#ifndef PM_TMR_32BIT
702#define TMR_VAL_MSB 0x800000
703#define TMR_VAL_MASK 0xffffff
704#undef FADT_FL_TMR_VAL_EXT
705#define FADT_FL_TMR_VAL_EXT 0
706#else
707#define TMR_VAL_MSB 0x80000000
708#define TMR_VAL_MASK 0xffffffff
709#endif
710
711 /** Start of the ACPI 2.0 extension. */
712 ACPIGENADDR ResetReg; /**< ext addr of reset register */
713 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
714#define ACPI_RESET_REG_VAL 0x10
715 uint8_t au8Must0_1[3]; /**< must be 0 */
716 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
717 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
718 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
719 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
720 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
721 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
722 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
723 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
724 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
725 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
726};
727AssertCompileSize(ACPITBLFADT, 244);
728#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
729
730/** Firmware ACPI Control Structure */
731struct ACPITBLFACS
732{
733 uint8_t au8Signature[4]; /**< 'FACS' */
734 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
735 uint32_t u32HWSignature; /**< systems HW signature at last boot */
736 uint32_t u32FWVector; /**< address of waking vector */
737 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
738 uint32_t u32Flags; /**< FACS flags */
739 uint64_t u64X_FWVector; /**< 64-bit waking vector */
740 uint8_t u8Version; /**< version of this table */
741 uint8_t au8Reserved[31]; /**< zero */
742};
743AssertCompileSize(ACPITBLFACS, 64);
744
745/** Processor Local APIC Structure */
746struct ACPITBLLAPIC
747{
748 uint8_t u8Type; /**< 0 = LAPIC */
749 uint8_t u8Length; /**< 8 */
750 uint8_t u8ProcId; /**< processor ID */
751 uint8_t u8ApicId; /**< local APIC ID */
752 uint32_t u32Flags; /**< Flags */
753#define LAPIC_ENABLED 0x1
754};
755AssertCompileSize(ACPITBLLAPIC, 8);
756
757/** I/O APIC Structure */
758struct ACPITBLIOAPIC
759{
760 uint8_t u8Type; /**< 1 == I/O APIC */
761 uint8_t u8Length; /**< 12 */
762 uint8_t u8IOApicId; /**< I/O APIC ID */
763 uint8_t u8Reserved; /**< 0 */
764 uint32_t u32Address; /**< phys address to access I/O APIC */
765 uint32_t u32GSIB; /**< global system interrupt number to start */
766};
767AssertCompileSize(ACPITBLIOAPIC, 12);
768
769/** Interrupt Source Override Structure */
770struct ACPITBLISO
771{
772 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
773 uint8_t u8Length; /**< 10 */
774 uint8_t u8Bus; /**< Bus */
775 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
776 uint32_t u32GSI; /**< Global System Interrupt */
777 uint16_t u16Flags; /**< MPS INTI flags Global */
778};
779AssertCompileSize(ACPITBLISO, 10);
780#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
781
782/** HPET Descriptor Structure */
783struct ACPITBLHPET
784{
785 ACPITBLHEADER aHeader;
786 uint32_t u32Id; /**< hardware ID of event timer block
787 [31:16] PCI vendor ID of first timer block
788 [15] legacy replacement IRQ routing capable
789 [14] reserved
790 [13] COUNT_SIZE_CAP counter size
791 [12:8] number of comparators in first timer block
792 [7:0] hardware rev ID */
793 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
794 uint8_t u32Number; /**< sequence number starting at 0 */
795 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
796 lost interrupts while the counter is programmed
797 to operate in periodic mode. Unit: clock tick. */
798 uint8_t u8Attributes; /**< page protection and OEM attribute. */
799};
800AssertCompileSize(ACPITBLHPET, 56);
801
802#ifdef VBOX_WITH_IOMMU_AMD
803/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
804 * In accordance with the AMD spec. */
805typedef struct ACPIIVRS
806{
807 ACPITBLHEADER header;
808 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
809 uint64_t u64Rsvd; /**< Reserved (MBZ). */
810 /* IVHD type block follows. */
811} ACPIIVRS;
812AssertCompileSize(ACPIIVRS, 48);
813AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
814
815/**
816 * AMD IOMMU: The ACPI table.
817 */
818typedef struct ACPITBLIOMMU
819{
820 ACPIIVRS Hdr;
821 ACPIIVHDTYPE10 IvhdType10;
822 ACPIIVHDDEVENTRY4 IvhdType10Start;
823 ACPIIVHDDEVENTRY4 IvhdType10End;
824 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
825 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
826 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
827 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
828
829 ACPIIVHDTYPE11 IvhdType11;
830 ACPIIVHDDEVENTRY4 IvhdType11Start;
831 ACPIIVHDDEVENTRY4 IvhdType11End;
832 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
833 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
834 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
835 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
836} ACPITBLIOMMU;
837AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
838AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
839AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
840AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
841#endif /* VBOX_WITH_IOMMU_AMD */
842
843#ifdef VBOX_WITH_IOMMU_INTEL
844/** Intel IOMMU: DMAR (DMA Remapping) Reporting Structure.
845 * In accordance with the AMD spec. */
846typedef struct ACPIDMAR
847{
848 ACPITBLHEADER Hdr;
849 /** Host-address Width (N+1 physical bits addressable). */
850 uint8_t uHostAddrWidth;
851 /** Flags, see ACPI_DMAR_F_XXX. */
852 uint8_t fFlags;
853 /** Reserved. */
854 uint8_t abRsvd[10];
855 /* Remapping Structures[] follows. */
856} ACPIDMAR;
857AssertCompileSize(ACPIDMAR, 48);
858AssertCompileMemberOffset(ACPIDMAR, uHostAddrWidth, 36);
859AssertCompileMemberOffset(ACPIDMAR, fFlags, 37);
860
861/**
862 * Intel VT-d: The ACPI table.
863 */
864typedef struct ACPITBLVTD
865{
866 ACPIDMAR Dmar;
867 ACPIDRHD Drhd;
868 /* ACPIDMARDEVSCOPE DevScope; */
869} ACPITBLVTD;
870#endif /* VBOX_WITH_IOMMU_INTEL */
871
872/** MCFG Descriptor Structure */
873typedef struct ACPITBLMCFG
874{
875 ACPITBLHEADER aHeader;
876 uint64_t u64Reserved;
877} ACPITBLMCFG;
878AssertCompileSize(ACPITBLMCFG, 44);
879
880/** Number of such entries can be computed from the whole table length in header */
881typedef struct ACPITBLMCFGENTRY
882{
883 uint64_t u64BaseAddress;
884 uint16_t u16PciSegmentGroup;
885 uint8_t u8StartBus;
886 uint8_t u8EndBus;
887 uint32_t u32Reserved;
888} ACPITBLMCFGENTRY;
889AssertCompileSize(ACPITBLMCFGENTRY, 16);
890
891#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
892
893/** Custom Description Table */
894struct ACPITBLCUST
895{
896 ACPITBLHEADER header;
897 uint8_t au8Data[476];
898};
899AssertCompileSize(ACPITBLCUST, 512);
900
901
902#pragma pack()
903
904
905#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
906
907
908/*********************************************************************************************************************************
909* Internal Functions *
910*********************************************************************************************************************************/
911#ifdef IN_RING3
912static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
913#endif
914
915/* SCI, usually IRQ9 */
916DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
917{
918 PDMDevHlpPCISetIrq(pDevIns, 0, level);
919}
920
921DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
922{
923 return (pThis->pm1a_ctl & SCI_EN)
924 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
925}
926
927DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
928{
929 return !!(pThis->gpe0_en & pThis->gpe0_sts);
930}
931
932DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
933{
934 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
935 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
936 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
937 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
938 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
939}
940
941DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
942{
943 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
944}
945
946/**
947 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
948 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
949 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
950 * registers and trigger IRQs.
951 *
952 * Caller must hold the state lock.
953 *
954 * @param pDevIns The PDM device instance.
955 * @param pThis The ACPI shared instance data.
956 * @param sts The new PM1a.STS value.
957 * @param en The new PM1a.EN value.
958 */
959static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
960{
961 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
962
963 const bool old_level = acpiSCILevel(pDevIns, pThis);
964 pThis->pm1a_en = en;
965 pThis->pm1a_sts = sts;
966 const bool new_level = acpiSCILevel(pDevIns, pThis);
967
968 LogFunc(("old=%x new=%x\n", old_level, new_level));
969
970 if (new_level != old_level)
971 acpiSetIrq(pDevIns, new_level);
972}
973
974#ifdef IN_RING3
975
976/**
977 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
978 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
979 *
980 * Caller must hold the state lock.
981 *
982 * @param pDevIns The PDM device instance.
983 * @param pThis The ACPI shared instance data.
984 * @param sts The new GPE0.STS value.
985 * @param en The new GPE0.EN value.
986 */
987static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
988{
989 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
990
991 const bool old_level = acpiSCILevel(pDevIns, pThis);
992 pThis->gpe0_en = en;
993 pThis->gpe0_sts = sts;
994 const bool new_level = acpiSCILevel(pDevIns, pThis);
995
996 LogFunc(("old=%x new=%x\n", old_level, new_level));
997
998 if (new_level != old_level)
999 acpiSetIrq(pDevIns, new_level);
1000}
1001
1002/**
1003 * Used by acpiR3PM1aCtlWrite to power off the VM.
1004 *
1005 * @param pDevIns The device instance.
1006 * @returns Strict VBox status code.
1007 */
1008static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
1009{
1010 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
1011 AssertRC(VBOXSTRICTRC_VAL(rc));
1012 return rc;
1013}
1014
1015/**
1016 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
1017 *
1018 * @param pDevIns The device instance.
1019 * @param pThis The ACPI shared instance data.
1020 * @returns Strict VBox status code.
1021 */
1022static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
1023{
1024 /* We must set WAK_STS on resume (includes restore) so the guest knows that
1025 we've woken up and can continue executing code. The guest is probably
1026 reading the PMSTS register in a loop to check this. */
1027 VBOXSTRICTRC rc;
1028 pThis->fSetWakeupOnResume = true;
1029 if (pThis->fSuspendToSavedState)
1030 {
1031 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
1032 if (rc != VERR_NOT_SUPPORTED)
1033 AssertRC(VBOXSTRICTRC_VAL(rc));
1034 else
1035 {
1036 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
1037 rc = PDMDevHlpVMSuspend(pDevIns);
1038 AssertRC(VBOXSTRICTRC_VAL(rc));
1039 }
1040 }
1041 else
1042 {
1043 rc = PDMDevHlpVMSuspend(pDevIns);
1044 AssertRC(VBOXSTRICTRC_VAL(rc));
1045 }
1046 return rc;
1047}
1048
1049
1050/**
1051 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
1052 */
1053static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
1054{
1055 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1056 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1057 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1058 DEVACPI_LOCK_R3(pDevIns, pThis);
1059
1060 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1061 pThis->fPowerButtonHandled = false;
1062 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1063
1064 DEVACPI_UNLOCK(pDevIns, pThis);
1065 return VINF_SUCCESS;
1066}
1067
1068/**
1069 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
1070 */
1071static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1072{
1073 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1074 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1075 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1076 DEVACPI_LOCK_R3(pDevIns, pThis);
1077
1078 *pfHandled = pThis->fPowerButtonHandled;
1079
1080 DEVACPI_UNLOCK(pDevIns, pThis);
1081 return VINF_SUCCESS;
1082}
1083
1084/**
1085 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1086 * Guest entered into G0 (working) or G1 (sleeping)}
1087 */
1088static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1089{
1090 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1091 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1092 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1093 DEVACPI_LOCK_R3(pDevIns, pThis);
1094
1095 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1096
1097 DEVACPI_UNLOCK(pDevIns, pThis);
1098 return VINF_SUCCESS;
1099}
1100
1101/**
1102 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1103 */
1104static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1105{
1106 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1107 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1108 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1109 DEVACPI_LOCK_R3(pDevIns, pThis);
1110
1111 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1112
1113 DEVACPI_UNLOCK(pDevIns, pThis);
1114 return VINF_SUCCESS;
1115}
1116
1117/**
1118 * Send an ACPI sleep button event.
1119 *
1120 * @returns VBox status code
1121 * @param pInterface Pointer to the interface structure containing the called function pointer.
1122 */
1123static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1124{
1125 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1126 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1127 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1128 DEVACPI_LOCK_R3(pDevIns, pThis);
1129
1130 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1131
1132 DEVACPI_UNLOCK(pDevIns, pThis);
1133 return VINF_SUCCESS;
1134}
1135
1136/**
1137 * Send an ACPI monitor hot-plug event.
1138 *
1139 * @returns VBox status code
1140 * @param pInterface Pointer to the interface structure containing the
1141 * called function pointer.
1142 */
1143static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1144{
1145 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1146 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1147 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1148 DEVACPI_LOCK_R3(pDevIns, pThis);
1149
1150 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1151
1152 DEVACPI_UNLOCK(pDevIns, pThis);
1153 return VINF_SUCCESS;
1154}
1155
1156/**
1157 * Send an ACPI battery status change event.
1158 *
1159 * @returns VBox status code
1160 * @param pInterface Pointer to the interface structure containing the
1161 * called function pointer.
1162 */
1163static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1164{
1165 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1166 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1167 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1168 DEVACPI_LOCK_R3(pDevIns, pThis);
1169
1170 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1171
1172 DEVACPI_UNLOCK(pDevIns, pThis);
1173 return VINF_SUCCESS;
1174}
1175
1176/**
1177 * Used by acpiR3PmTimer to re-arm the PM timer.
1178 *
1179 * The caller is expected to either hold the clock lock or to have made sure
1180 * the VM is resetting or loading state.
1181 *
1182 * @param pDevIns The device instance.
1183 * @param pThis The ACPI shared instance data.
1184 * @param uNow The current time.
1185 */
1186static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1187{
1188 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1189 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1190 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1191 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1192 Log(("acpi: uInterval = %RU64\n", uInterval));
1193}
1194
1195#endif /* IN_RING3 */
1196
1197/**
1198 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1199 *
1200 * The caller is expected to either hold the clock lock or to have made sure
1201 * the VM is resetting or loading state.
1202 *
1203 * @param pDevIns The PDM device instance.
1204 * @param pThis The ACPI instance
1205 * @param u64Now The current time
1206 */
1207static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1208{
1209 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1210 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1211 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1212
1213 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1214 & TMR_VAL_MASK;
1215
1216 if ((pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1217 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1218}
1219
1220#ifdef IN_RING3
1221
1222/**
1223 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1224 */
1225static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1226{
1227 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1228 Assert(pThis->hPmTimer == hTimer);
1229 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
1230 RT_NOREF(pvUser);
1231
1232 DEVACPI_LOCK_R3(pDevIns, pThis);
1233 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1234 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1235 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1236 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, hTimer);
1237 acpiPmTimerUpdate(pDevIns, pThis, tsNow);
1238 DEVACPI_UNLOCK(pDevIns, pThis);
1239
1240 acpiR3PmTimerReset(pDevIns, pThis, tsNow);
1241}
1242
1243/**
1244 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1245 * acpiR3LoadState.
1246 *
1247 * @returns VINF_SUCCESS.
1248 * @param pThis The ACPI shared instance data.
1249 * @param pThisCC The ACPI instance data for ring-3.
1250 */
1251static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1252{
1253 uint32_t *p = pThis->au8BatteryInfo;
1254 bool fPresent; /* battery present? */
1255 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1256 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1257 uint32_t hostPresentRate; /* 0..1000 */
1258 int rc;
1259
1260 if (!pThisCC->pDrv)
1261 return VINF_SUCCESS;
1262 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1263 &hostBatteryState, &hostPresentRate);
1264 AssertRC(rc);
1265
1266 /* default values */
1267 p[BAT_STATUS_STATE] = hostBatteryState;
1268 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1269 : hostPresentRate * 50; /* mW */
1270 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1271 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1272
1273 /* did we get a valid battery state? */
1274 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1275 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1276 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1277 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1278
1279 return VINF_SUCCESS;
1280}
1281
1282/**
1283 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1284 * acpiR3LoadState.
1285 *
1286 * @returns VINF_SUCCESS.
1287 * @param pThis The ACPI shared instance data.
1288 */
1289static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1290{
1291 uint32_t *p = pThis->au8BatteryInfo;
1292
1293 p[BAT_INFO_UNITS] = 0; /* mWh */
1294 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1295 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1296 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1297 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1298 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1299 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1300 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1301 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1302
1303 return VINF_SUCCESS;
1304}
1305
1306/**
1307 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1308 *
1309 * @returns status mask or 0.
1310 * @param pThisCC The ACPI instance data for ring-3.
1311 */
1312static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1313{
1314 bool fPresent; /* battery present? */
1315 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1316 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1317 uint32_t hostPresentRate; /* 0..1000 */
1318 int rc;
1319
1320 if (!pThisCC->pDrv)
1321 return 0;
1322 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1323 &hostBatteryState, &hostPresentRate);
1324 AssertRC(rc);
1325
1326 return fPresent
1327 ? STA_DEVICE_PRESENT_MASK /* present */
1328 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1329 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1330 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1331 | STA_BATTERY_PRESENT_MASK /* battery is present */
1332 : 0; /* device not present */
1333}
1334
1335/**
1336 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1337 *
1338 * @returns status.
1339 * @param pThisCC The ACPI instance data for ring-3.
1340 */
1341static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1342{
1343 /* query the current power source from the host driver */
1344 if (!pThisCC->pDrv)
1345 return AC_ONLINE;
1346
1347 PDMACPIPOWERSOURCE ps;
1348 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1349 AssertRC(rc);
1350 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1351}
1352
1353/**
1354 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1355 */
1356static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1357{
1358 RT_NOREF(pvUser, offPort);
1359 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1360 if (cb != 4)
1361 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1362
1363 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1364 DEVACPI_LOCK_R3(pDevIns, pThis);
1365
1366 u32 >>= pThis->u8IndexShift;
1367 /* see comment at the declaration of u8IndexShift */
1368 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1369 {
1370 pThis->u8IndexShift = 2;
1371 u32 >>= 2;
1372 }
1373 Assert(u32 < BAT_INDEX_LAST);
1374 pThis->uBatteryIndex = u32;
1375
1376 DEVACPI_UNLOCK(pDevIns, pThis);
1377 return VINF_SUCCESS;
1378}
1379
1380/**
1381 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1382 */
1383static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1384{
1385 RT_NOREF(pvUser, offPort);
1386 if (cb != 4)
1387 return VERR_IOM_IOPORT_UNUSED;
1388
1389 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1390 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1391 DEVACPI_LOCK_R3(pDevIns, pThis);
1392
1393 VBOXSTRICTRC rc = VINF_SUCCESS;
1394 switch (pThis->uBatteryIndex)
1395 {
1396 case BAT_STATUS_STATE:
1397 acpiR3FetchBatteryStatus(pThis, pThisCC);
1398 RT_FALL_THRU();
1399 case BAT_STATUS_PRESENT_RATE:
1400 case BAT_STATUS_REMAINING_CAPACITY:
1401 case BAT_STATUS_PRESENT_VOLTAGE:
1402 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1403 break;
1404
1405 case BAT_INFO_UNITS:
1406 acpiR3FetchBatteryInfo(pThis);
1407 RT_FALL_THRU();
1408 case BAT_INFO_DESIGN_CAPACITY:
1409 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1410 case BAT_INFO_TECHNOLOGY:
1411 case BAT_INFO_DESIGN_VOLTAGE:
1412 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1413 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1414 case BAT_INFO_CAPACITY_GRANULARITY_1:
1415 case BAT_INFO_CAPACITY_GRANULARITY_2:
1416 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1417 break;
1418
1419 case BAT_DEVICE_STATUS:
1420 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1421 break;
1422
1423 case BAT_POWER_SOURCE:
1424 *pu32 = acpiR3GetPowerSource(pThisCC);
1425 break;
1426
1427 default:
1428 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1429 *pu32 = UINT32_MAX;
1430 break;
1431 }
1432
1433 DEVACPI_UNLOCK(pDevIns, pThis);
1434 return rc;
1435}
1436
1437/**
1438 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1439 */
1440static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1441{
1442 RT_NOREF(pvUser, offPort);
1443 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1444 if (cb != 4)
1445 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1446
1447 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1448 DEVACPI_LOCK_R3(pDevIns, pThis);
1449
1450 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1451 pThis->uSystemInfoIndex = u32;
1452 else
1453 {
1454 /* see comment at the declaration of u8IndexShift */
1455 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1456 {
1457 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1458 pThis->u8IndexShift = 2;
1459 }
1460
1461 u32 >>= pThis->u8IndexShift;
1462
1463 /* If the index exceeds 31 (which is all we can fit within offset 0x80), we need to divide the index again
1464 for indices > 31 and < SYSTEM_INFO_INDEX_END. */
1465 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 2 && (u32 >> 2) < SYSTEM_INFO_INDEX_END)
1466 u32 >>= 2;
1467
1468 AssertMsg(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1469 pThis->uSystemInfoIndex = u32;
1470 }
1471
1472 DEVACPI_UNLOCK(pDevIns, pThis);
1473 return VINF_SUCCESS;
1474}
1475
1476/**
1477 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1478 */
1479static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1480{
1481 RT_NOREF(pvUser, offPort);
1482 if (cb != 4)
1483 return VERR_IOM_IOPORT_UNUSED;
1484
1485 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1486 DEVACPI_LOCK_R3(pDevIns, pThis);
1487
1488 VBOXSTRICTRC rc = VINF_SUCCESS;
1489 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1490 switch (uSystemInfoIndex)
1491 {
1492 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1493 *pu32 = pThis->cbRamLow;
1494 break;
1495
1496 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1497 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1498 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1499 break;
1500
1501 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1502 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1503 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1504 break;
1505
1506 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1507 *pu32 = pThis->u8UseIOApic;
1508 break;
1509
1510 case SYSTEM_INFO_INDEX_HPET_STATUS:
1511 *pu32 = pThis->fUseHpet
1512 ? ( STA_DEVICE_PRESENT_MASK
1513 | STA_DEVICE_ENABLED_MASK
1514 | STA_DEVICE_SHOW_IN_UI_MASK
1515 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1516 : 0;
1517 break;
1518
1519 case SYSTEM_INFO_INDEX_SMC_STATUS:
1520 *pu32 = pThis->fUseSmc
1521 ? ( STA_DEVICE_PRESENT_MASK
1522 | STA_DEVICE_ENABLED_MASK
1523 /* no need to show this device in the UI */
1524 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1525 : 0;
1526 break;
1527
1528 case SYSTEM_INFO_INDEX_FDC_STATUS:
1529 *pu32 = pThis->fUseFdc
1530 ? ( STA_DEVICE_PRESENT_MASK
1531 | STA_DEVICE_ENABLED_MASK
1532 | STA_DEVICE_SHOW_IN_UI_MASK
1533 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1534 : 0;
1535 break;
1536
1537 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1538 *pu32 = pThis->u32NicPciAddress;
1539 break;
1540
1541 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1542 *pu32 = pThis->u32AudioPciAddress;
1543 break;
1544
1545 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1546 *pu32 = pThis->u32NvmePciAddress;
1547 break;
1548
1549 case SYSTEM_INFO_INDEX_POWER_STATES:
1550 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1551 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1552 *pu32 |= RT_BIT(1);
1553 if (pThis->fS4Enabled)
1554 *pu32 |= RT_BIT(4);
1555 break;
1556
1557 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1558 *pu32 = pThis->u32IocPciAddress;
1559 break;
1560
1561 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1562 *pu32 = pThis->u32HbcPciAddress;
1563 break;
1564
1565 case SYSTEM_INFO_INDEX_PCI_BASE:
1566 /** @todo couldn't MCFG be in 64-bit range? */
1567 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1568 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1569 break;
1570
1571 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1572 /** @todo couldn't MCFG be in 64-bit range? */
1573 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1574 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1575 break;
1576
1577 case SYSTEM_INFO_INDEX_RTC_STATUS:
1578 *pu32 = pThis->fShowRtc
1579 ? ( STA_DEVICE_PRESENT_MASK
1580 | STA_DEVICE_ENABLED_MASK
1581 | STA_DEVICE_SHOW_IN_UI_MASK
1582 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1583 : 0;
1584 break;
1585
1586 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1587 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1588 {
1589 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1590 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1591 }
1592 else
1593 {
1594 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1595 pThis->idCpuLockCheck);
1596 /* Always return locked status just to be safe */
1597 *pu32 = 1;
1598 }
1599 break;
1600
1601 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1602 *pu32 = pThis->u32CpuEventType;
1603 break;
1604
1605 case SYSTEM_INFO_INDEX_CPU_EVENT:
1606 *pu32 = pThis->u32CpuEvent;
1607 break;
1608
1609 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1610 *pu32 = pThis->uSerial0IoPortBase;
1611 break;
1612
1613 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1614 *pu32 = pThis->uSerial0Irq;
1615 break;
1616
1617 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1618 *pu32 = pThis->uSerial1IoPortBase;
1619 break;
1620
1621 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1622 *pu32 = pThis->uSerial1Irq;
1623 break;
1624
1625 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1626 *pu32 = pThis->uSerial2IoPortBase;
1627 break;
1628
1629 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1630 *pu32 = pThis->uSerial2Irq;
1631 break;
1632
1633 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1634 *pu32 = pThis->uSerial3IoPortBase;
1635 break;
1636
1637 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1638 *pu32 = pThis->uSerial3Irq;
1639 break;
1640
1641 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1642 *pu32 = pThis->uParallel0IoPortBase;
1643 break;
1644
1645 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1646 *pu32 = pThis->uParallel0Irq;
1647 break;
1648
1649 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1650 *pu32 = pThis->uParallel1IoPortBase;
1651 break;
1652
1653 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1654 *pu32 = pThis->uParallel1Irq;
1655 break;
1656
1657 case SYSTEM_INFO_INDEX_IOMMU_ADDRESS:
1658 *pu32 = pThis->u32IommuPciAddress;
1659 break;
1660
1661 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
1662 *pu32 = pThis->u32SbIoApicPciAddress;
1663 break;
1664
1665 case SYSTEM_INFO_INDEX_END:
1666 /** @todo why isn't this setting any output value? */
1667 break;
1668
1669 /* Solaris 9 tries to read from this index */
1670 case SYSTEM_INFO_INDEX_INVALID:
1671 *pu32 = 0;
1672 break;
1673
1674 default:
1675 *pu32 = UINT32_MAX;
1676 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1677 break;
1678 }
1679
1680 DEVACPI_UNLOCK(pDevIns, pThis);
1681 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1682 return rc;
1683}
1684
1685/**
1686 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1687 */
1688static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1689{
1690 RT_NOREF(pvUser, offPort);
1691 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1692 if (cb != 4)
1693 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1694
1695 DEVACPI_LOCK_R3(pDevIns, pThis);
1696 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1697
1698 VBOXSTRICTRC rc = VINF_SUCCESS;
1699 switch (pThis->uSystemInfoIndex)
1700 {
1701 case SYSTEM_INFO_INDEX_INVALID:
1702 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1703 pThis->u8IndexShift = 0;
1704 break;
1705
1706 case SYSTEM_INFO_INDEX_VALID:
1707 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1708 pThis->u8IndexShift = 2;
1709 break;
1710
1711 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1712 pThis->idCpuLockCheck = u32;
1713 break;
1714
1715 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1716 if (u32 < pThis->cCpus)
1717 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1718 else
1719 LogRel(("ACPI: CPU %u does not exist\n", u32));
1720 break;
1721
1722 default:
1723 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1724 break;
1725 }
1726
1727 DEVACPI_UNLOCK(pDevIns, pThis);
1728 return rc;
1729}
1730
1731/**
1732 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1733 */
1734static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1735{
1736 RT_NOREF(offPort, pvUser);
1737 if (cb != 2)
1738 return VERR_IOM_IOPORT_UNUSED;
1739
1740 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1741 DEVACPI_LOCK_R3(pDevIns, pThis);
1742
1743 *pu32 = pThis->pm1a_en;
1744
1745 DEVACPI_UNLOCK(pDevIns, pThis);
1746 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1747 return VINF_SUCCESS;
1748}
1749
1750/**
1751 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1752 */
1753static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1754{
1755 RT_NOREF(offPort, pvUser);
1756 if (cb != 2 && cb != 4)
1757 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1758
1759 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1760 DEVACPI_LOCK_R3(pDevIns, pThis);
1761
1762 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1763 u32 &= ~(RSR_EN | IGN_EN);
1764 u32 &= 0xffff;
1765 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1766
1767 DEVACPI_UNLOCK(pDevIns, pThis);
1768 return VINF_SUCCESS;
1769}
1770
1771/**
1772 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1773 */
1774static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1775{
1776 RT_NOREF(offPort, pvUser);
1777 if (cb != 2)
1778 {
1779 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1780 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1781 }
1782
1783 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1784 DEVACPI_LOCK_R3(pDevIns, pThis);
1785
1786 *pu32 = pThis->pm1a_sts;
1787
1788 DEVACPI_UNLOCK(pDevIns, pThis);
1789 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1790 return VINF_SUCCESS;
1791}
1792
1793/**
1794 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1795 */
1796static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1797{
1798 RT_NOREF(offPort, pvUser);
1799 if (cb != 2 && cb != 4)
1800 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1801
1802 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1803 DEVACPI_LOCK_R3(pDevIns, pThis);
1804
1805 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1806 u32 &= 0xffff;
1807 if (u32 & PWRBTN_STS)
1808 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1809 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1810 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1811
1812 DEVACPI_UNLOCK(pDevIns, pThis);
1813 return VINF_SUCCESS;
1814}
1815
1816/**
1817 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1818 */
1819static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1820{
1821 RT_NOREF(offPort, pvUser);
1822 if (cb != 2)
1823 {
1824 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1825 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1826 }
1827
1828 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1829 DEVACPI_LOCK_R3(pDevIns, pThis);
1830
1831 *pu32 = pThis->pm1a_ctl;
1832
1833 DEVACPI_UNLOCK(pDevIns, pThis);
1834 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1835 return VINF_SUCCESS;
1836}
1837
1838/**
1839 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1840 */
1841static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1842{
1843 RT_NOREF(offPort, pvUser);
1844 if (cb != 2 && cb != 4)
1845 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1846
1847 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1848 DEVACPI_LOCK_R3(pDevIns, pThis);
1849
1850 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1851 u32 &= 0xffff;
1852 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1853
1854 VBOXSTRICTRC rc = VINF_SUCCESS;
1855 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1856 if (uSleepState != pThis->uSleepState)
1857 {
1858 pThis->uSleepState = uSleepState;
1859 switch (uSleepState)
1860 {
1861 case 0x00: /* S0 */
1862 break;
1863
1864 case 0x01: /* S1 */
1865 if (pThis->fS1Enabled)
1866 {
1867 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1868 rc = acpiR3DoSleep(pDevIns, pThis);
1869 break;
1870 }
1871 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1872 RT_FALL_THRU();
1873
1874 case 0x04: /* S4 */
1875 if (pThis->fS4Enabled)
1876 {
1877 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1878 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1879 break;
1880 }
1881 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1882 RT_FALL_THRU();
1883
1884 case 0x05: /* S5 */
1885 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1886 rc = acpiR3DoPowerOff(pDevIns);
1887 break;
1888
1889 default:
1890 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1891 break;
1892 }
1893 }
1894
1895 DEVACPI_UNLOCK(pDevIns, pThis);
1896 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1897 return rc;
1898}
1899
1900#endif /* IN_RING3 */
1901
1902/**
1903 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1904 *
1905 * @remarks The only I/O port currently implemented in all contexts.
1906 */
1907static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1908{
1909 RT_NOREF(offPort, pvUser);
1910 if (cb != 4)
1911 return VERR_IOM_IOPORT_UNUSED;
1912
1913 /*
1914 * We use the clock lock to serialize access to u64PmTimerInitial and to
1915 * make sure we get a reliable time from the clock
1916 * as well as and to prevent uPmTimerVal from being updated during read.
1917 */
1918 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1919 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1920 if (rc == VINF_SUCCESS)
1921 {
1922 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1923 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1924 *pu32 = pThis->uPmTimerVal;
1925
1926 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
1927
1928 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1929 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1930
1931#if 0
1932 /** @todo temporary: sanity check against running backwards */
1933 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
1934 if (*pu32 - uOld >= 0x10000000)
1935 {
1936# if defined(IN_RING0)
1937 pThis->uPmTimeA = uOld;
1938 pThis->uPmTimeB = *pu32;
1939 return VERR_TM_TIMER_BAD_CLOCK;
1940# elif defined(IN_RING3)
1941 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
1942# endif
1943 }
1944#endif
1945 }
1946 return rc;
1947}
1948
1949#ifdef IN_RING3
1950
1951/**
1952 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
1953 */
1954static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1955{
1956 RT_NOREF(offPort, pvUser);
1957 if (cb != 1)
1958 {
1959 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1960 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1961 }
1962
1963 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1964 DEVACPI_LOCK_R3(pDevIns, pThis);
1965
1966 *pu32 = pThis->gpe0_sts & 0xff;
1967
1968 DEVACPI_UNLOCK(pDevIns, pThis);
1969 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1970 return VINF_SUCCESS;
1971}
1972
1973/**
1974 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
1975 */
1976static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1977{
1978 RT_NOREF(offPort, pvUser);
1979 if (cb != 1)
1980 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1981
1982 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1983 DEVACPI_LOCK_R3(pDevIns, pThis);
1984
1985 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1986 u32 = pThis->gpe0_sts & ~u32;
1987 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
1988
1989 DEVACPI_UNLOCK(pDevIns, pThis);
1990 return VINF_SUCCESS;
1991}
1992
1993/**
1994 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
1995 */
1996static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1997{
1998 RT_NOREF(offPort, pvUser);
1999 if (cb != 1)
2000 {
2001 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2002 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2003 }
2004
2005 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2006 DEVACPI_LOCK_R3(pDevIns, pThis);
2007
2008 *pu32 = pThis->gpe0_en & 0xff;
2009
2010 DEVACPI_UNLOCK(pDevIns, pThis);
2011 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
2012 return VINF_SUCCESS;
2013}
2014
2015/**
2016 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
2017 */
2018static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2019{
2020 RT_NOREF(offPort, pvUser);
2021 if (cb != 1)
2022 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2023
2024 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2025 DEVACPI_LOCK_R3(pDevIns, pThis);
2026
2027 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
2028 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
2029
2030 DEVACPI_UNLOCK(pDevIns, pThis);
2031 return VINF_SUCCESS;
2032}
2033
2034/**
2035 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
2036 */
2037static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2038{
2039 RT_NOREF(offPort, pvUser);
2040 Log(("acpiR3SmiWrite %#x\n", u32));
2041 if (cb != 1)
2042 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2043
2044 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2045 DEVACPI_LOCK_R3(pDevIns, pThis);
2046
2047 if (u32 == ACPI_ENABLE)
2048 pThis->pm1a_ctl |= SCI_EN;
2049 else if (u32 == ACPI_DISABLE)
2050 pThis->pm1a_ctl &= ~SCI_EN;
2051 else
2052 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2053
2054 DEVACPI_UNLOCK(pDevIns, pThis);
2055 return VINF_SUCCESS;
2056}
2057
2058/**
2059 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2060 */
2061static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2062{
2063 RT_NOREF(offPort, pvUser);
2064 Log(("acpiR3ResetWrite: %#x\n", u32));
2065 NOREF(pvUser);
2066 if (cb != 1)
2067 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2068
2069 /* No state locking required. */
2070 VBOXSTRICTRC rc;
2071 if (u32 == ACPI_RESET_REG_VAL)
2072 {
2073 LogRel(("ACPI: Reset initiated by ACPI\n"));
2074 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2075 }
2076 else
2077 {
2078 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2079 rc = VINF_SUCCESS;
2080 }
2081
2082 return rc;
2083}
2084
2085# ifdef DEBUG_ACPI
2086
2087/**
2088 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2089 */
2090static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2091{
2092 NOREF(pvUser);
2093 switch (cb)
2094 {
2095 case 1:
2096 Log(("%#x\n", u32 & 0xff));
2097 break;
2098 case 2:
2099 Log(("%#6x\n", u32 & 0xffff));
2100 break;
2101 case 4:
2102 Log(("%#10x\n", u32));
2103 break;
2104 default:
2105 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2106 }
2107 return VINF_SUCCESS;
2108}
2109
2110/**
2111 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2112 */
2113static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2114{
2115 NOREF(pvUser);
2116 switch (cb)
2117 {
2118 case 1:
2119 Log(("%c", u32 & 0xff));
2120 break;
2121 default:
2122 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2123 }
2124 return VINF_SUCCESS;
2125}
2126
2127# endif /* DEBUG_ACPI */
2128
2129/**
2130 * @callback_method_impl{FNDBGFHANDLERDEV}
2131 */
2132static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2133{
2134 RT_NOREF(pszArgs);
2135 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2136 pHlp->pfnPrintf(pHlp,
2137 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2138}
2139
2140/**
2141 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2142 *
2143 * @param pDevIns The PDM device instance.
2144 * @param pThis The ACPI shared instance data.
2145 */
2146static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2147{
2148 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2149 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2150 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2151 pPciDev->abConfig[PMBA + 2] = 0x00;
2152 pPciDev->abConfig[PMBA + 3] = 0x00;
2153}
2154
2155/**
2156 * Used to calculate the value of a PM I/O port.
2157 *
2158 * @returns The actual I/O port value.
2159 * @param pThis The ACPI shared instance data.
2160 * @param offset The offset into the I/O space, or -1 if invalid.
2161 */
2162static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2163{
2164 Assert(pThis->uPmIoPortBase != 0);
2165
2166 if (offset == -1)
2167 return 0;
2168
2169 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2170}
2171
2172/**
2173 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2174 * timer and GPE0 I/O ports.
2175 *
2176 * @returns VBox status code.
2177 * @param pDevIns The device instance.
2178 * @param pThis The ACPI shared instance data.
2179 */
2180static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2181{
2182 if (pThis->uPmIoPortBase == 0)
2183 return VINF_SUCCESS;
2184
2185 int rc;
2186 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2187 AssertRCReturn(rc, rc);
2188 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2189 AssertRCReturn(rc, rc);
2190 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2191 AssertRCReturn(rc, rc);
2192 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2193 AssertRCReturn(rc, rc);
2194 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2195 AssertRCReturn(rc, rc);
2196 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2197
2198 return VINF_SUCCESS;
2199}
2200
2201/**
2202 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2203 * timer and GPE0 I/O ports.
2204 *
2205 * @returns VBox status code.
2206 * @param pDevIns The device instance.
2207 * @param pThis The ACPI shared instance data.
2208 */
2209static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2210{
2211 if (pThis->uPmIoPortBase != 0)
2212 {
2213 int rc;
2214 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2215 AssertRCReturn(rc, rc);
2216 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2217 AssertRCReturn(rc, rc);
2218 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2219 AssertRCReturn(rc, rc);
2220 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2221 AssertRCReturn(rc, rc);
2222 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2223 AssertRCReturn(rc, rc);
2224 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2225 AssertRCReturn(rc, rc);
2226 }
2227 return VINF_SUCCESS;
2228}
2229
2230/**
2231 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2232 * PM1a, PM timer and GPE0 ports.
2233 *
2234 * @returns VBox status code.
2235 *
2236 * @param pDevIns The device instance.
2237 * @param pThis The ACPI shared instance data.
2238 * @param pThisCC The ACPI instance data for ring-3.
2239 * @param NewIoPortBase The new base address of the I/O ports.
2240 */
2241static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2242{
2243 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2244 if (NewIoPortBase != pThis->uPmIoPortBase)
2245 {
2246 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2247 if (RT_FAILURE(rc))
2248 return rc;
2249
2250 pThis->uPmIoPortBase = NewIoPortBase;
2251
2252 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2253 if (RT_FAILURE(rc))
2254 return rc;
2255
2256 /* We have to update FADT table acccording to the new base */
2257 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2258 AssertRC(rc);
2259 if (RT_FAILURE(rc))
2260 return rc;
2261 }
2262
2263 return VINF_SUCCESS;
2264}
2265
2266/**
2267 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2268 */
2269static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2270{
2271 RT_NOREF(pvUser);
2272 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2273
2274 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2275 uint8_t off = offPort & 0x000f;
2276 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2277 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2278 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2279
2280 DEVACPI_LOCK_R3(pDevIns, pThis);
2281 switch (off)
2282 {
2283 case SMBHSTSTS_OFF:
2284 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2285 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2286 break;
2287 case SMBSLVSTS_OFF:
2288 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2289 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2290 break;
2291 case SMBHSTCNT_OFF:
2292 {
2293 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2294
2295 const bool old_level = acpiSCILevel(pDevIns, pThis);
2296 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2297 if (u32 & SMBHSTCNT_START)
2298 {
2299 /* Start, trigger error as this is a dummy implementation */
2300 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2301 }
2302 if (u32 & SMBHSTCNT_KILL)
2303 {
2304 /* Kill */
2305 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2306 }
2307 const bool new_level = acpiSCILevel(pDevIns, pThis);
2308
2309 LogFunc(("old=%x new=%x\n", old_level, new_level));
2310
2311 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2312 * needs to be implemented later if it ever becomes relevant. */
2313 if (new_level != old_level)
2314 acpiSetIrq(pDevIns, new_level);
2315 break;
2316 }
2317 case SMBHSTCMD_OFF:
2318 pThis->u8SMBusHstCmd = u32;
2319 break;
2320 case SMBHSTADD_OFF:
2321 pThis->u8SMBusHstAdd = u32;
2322 break;
2323 case SMBHSTDAT0_OFF:
2324 pThis->u8SMBusHstDat0 = u32;
2325 break;
2326 case SMBHSTDAT1_OFF:
2327 pThis->u8SMBusHstDat1 = u32;
2328 break;
2329 case SMBBLKDAT_OFF:
2330 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2331 pThis->u8SMBusBlkIdx++;
2332 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2333 break;
2334 case SMBSLVCNT_OFF:
2335 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2336 break;
2337 case SMBSHDWCMD_OFF:
2338 /* readonly register */
2339 break;
2340 case SMBSLVEVT_OFF:
2341 pThis->u16SMBusSlvEvt = u32;
2342 break;
2343 case SMBSLVDAT_OFF:
2344 /* readonly register */
2345 break;
2346 default:
2347 /* caught by the sanity check above */
2348 ;
2349 }
2350
2351 DEVACPI_UNLOCK(pDevIns, pThis);
2352 return VINF_SUCCESS;
2353}
2354
2355/**
2356 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2357 */
2358static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2359{
2360 RT_NOREF(pvUser);
2361 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2362
2363 VBOXSTRICTRC rc = VINF_SUCCESS;
2364 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2365 uint8_t const off = offPort & 0x000f;
2366 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2367 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2368 return VERR_IOM_IOPORT_UNUSED;
2369
2370 DEVACPI_LOCK_R3(pDevIns, pThis);
2371 switch (off)
2372 {
2373 case SMBHSTSTS_OFF:
2374 *pu32 = pThis->u8SMBusHstSts;
2375 break;
2376 case SMBSLVSTS_OFF:
2377 *pu32 = pThis->u8SMBusSlvSts;
2378 break;
2379 case SMBHSTCNT_OFF:
2380 pThis->u8SMBusBlkIdx = 0;
2381 *pu32 = pThis->u8SMBusHstCnt;
2382 break;
2383 case SMBHSTCMD_OFF:
2384 *pu32 = pThis->u8SMBusHstCmd;
2385 break;
2386 case SMBHSTADD_OFF:
2387 *pu32 = pThis->u8SMBusHstAdd;
2388 break;
2389 case SMBHSTDAT0_OFF:
2390 *pu32 = pThis->u8SMBusHstDat0;
2391 break;
2392 case SMBHSTDAT1_OFF:
2393 *pu32 = pThis->u8SMBusHstDat1;
2394 break;
2395 case SMBBLKDAT_OFF:
2396 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2397 pThis->u8SMBusBlkIdx++;
2398 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2399 break;
2400 case SMBSLVCNT_OFF:
2401 *pu32 = pThis->u8SMBusSlvCnt;
2402 break;
2403 case SMBSHDWCMD_OFF:
2404 *pu32 = pThis->u8SMBusShdwCmd;
2405 break;
2406 case SMBSLVEVT_OFF:
2407 *pu32 = pThis->u16SMBusSlvEvt;
2408 break;
2409 case SMBSLVDAT_OFF:
2410 *pu32 = pThis->u16SMBusSlvDat;
2411 break;
2412 default:
2413 /* caught by the sanity check above */
2414 rc = VERR_IOM_IOPORT_UNUSED;
2415 }
2416 DEVACPI_UNLOCK(pDevIns, pThis);
2417
2418 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2419 return rc;
2420}
2421
2422/**
2423 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2424 *
2425 * @param pDevIns The PDM device instance.
2426 * @param pThis The ACPI shared instance data.
2427 */
2428static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2429{
2430 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2431 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2432 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2433 pPciDev->abConfig[SMBBA+2] = 0x00;
2434 pPciDev->abConfig[SMBBA+3] = 0x00;
2435 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2436 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2437 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2438 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2439 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2440}
2441
2442/**
2443 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2444 *
2445 * @param pThis The ACPI shared instance data.
2446 */
2447static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2448{
2449 pThis->u8SMBusHstSts = 0x00;
2450 pThis->u8SMBusSlvSts = 0x00;
2451 pThis->u8SMBusHstCnt = 0x00;
2452 pThis->u8SMBusHstCmd = 0x00;
2453 pThis->u8SMBusHstAdd = 0x00;
2454 pThis->u8SMBusHstDat0 = 0x00;
2455 pThis->u8SMBusHstDat1 = 0x00;
2456 pThis->u8SMBusSlvCnt = 0x00;
2457 pThis->u8SMBusShdwCmd = 0x00;
2458 pThis->u16SMBusSlvEvt = 0x0000;
2459 pThis->u16SMBusSlvDat = 0x0000;
2460 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2461 pThis->u8SMBusBlkIdx = 0;
2462}
2463
2464/**
2465 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2466 *
2467 * @returns VBox status code.
2468 * @param pDevIns The device instance.
2469 * @param pThis The ACPI shared instance data.
2470 */
2471static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2472{
2473 if (pThis->uSMBusIoPortBase != 0)
2474 {
2475 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2476 AssertRCReturn(rc, rc);
2477 }
2478 return VINF_SUCCESS;
2479}
2480
2481/**
2482 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2483 *
2484 * @returns VBox status code.
2485 * @param pDevIns The device instance.
2486 * @param pThis The ACPI shared instance data.
2487 */
2488static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2489{
2490 if (pThis->uSMBusIoPortBase != 0)
2491 {
2492 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2493 AssertRCReturn(rc, rc);
2494 }
2495 return VINF_SUCCESS;
2496}
2497
2498/**
2499 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2500 * SMBus ports.
2501 *
2502 * @returns VBox status code.
2503 *
2504 * @param pDevIns The device instance.
2505 * @param pThis The ACPI shared instance data.
2506 * @param NewIoPortBase The new base address of the I/O ports.
2507 */
2508static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2509{
2510 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2511 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2512 {
2513 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2514 AssertRCReturn(rc, rc);
2515
2516 pThis->uSMBusIoPortBase = NewIoPortBase;
2517
2518 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2519 AssertRCReturn(rc, rc);
2520
2521#if 0 /* is there an FADT table entry for the SMBus base? */
2522 /* We have to update FADT table acccording to the new base */
2523 rc = acpiR3PlantTables(pThis);
2524 AssertRC(rc);
2525 if (RT_FAILURE(rc))
2526 return rc;
2527#endif
2528 }
2529
2530 return VINF_SUCCESS;
2531}
2532
2533
2534/**
2535 * Saved state structure description, version 4.
2536 */
2537static const SSMFIELD g_AcpiSavedStateFields4[] =
2538{
2539 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2540 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2541 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2542 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2543 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2544 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2545 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2546 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2547 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2548 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2549 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2550 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2551 SSMFIELD_ENTRY_TERM()
2552};
2553
2554/**
2555 * Saved state structure description, version 5.
2556 */
2557static const SSMFIELD g_AcpiSavedStateFields5[] =
2558{
2559 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2560 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2561 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2562 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2563 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2564 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2565 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2566 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2567 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2568 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2569 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2570 SSMFIELD_ENTRY_TERM()
2571};
2572
2573/**
2574 * Saved state structure description, version 6.
2575 */
2576static const SSMFIELD g_AcpiSavedStateFields6[] =
2577{
2578 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2579 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2580 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2581 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2582 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2583 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2584 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2585 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2586 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2587 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2588 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2589 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2590 SSMFIELD_ENTRY_TERM()
2591};
2592
2593/**
2594 * Saved state structure description, version 7.
2595 */
2596static const SSMFIELD g_AcpiSavedStateFields7[] =
2597{
2598 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2599 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2600 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2601 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2602 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2603 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2604 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2605 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2606 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2607 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2608 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2609 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2610 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2611 SSMFIELD_ENTRY_TERM()
2612};
2613
2614/**
2615 * Saved state structure description, version 8.
2616 */
2617static const SSMFIELD g_AcpiSavedStateFields8[] =
2618{
2619 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2620 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2621 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2622 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2623 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2624 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2625 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2626 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2627 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2628 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2629 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2630 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2631 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2632 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2633 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2634 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2635 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2636 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2637 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2638 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2639 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2640 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2641 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2642 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2643 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2644 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2645 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2646 SSMFIELD_ENTRY_TERM()
2647};
2648
2649/**
2650 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2651 */
2652static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2653{
2654 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2655 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2656 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2657}
2658
2659/**
2660 * @callback_method_impl{FNSSMDEVLOADEXEC}
2661 */
2662static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2663{
2664 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2665 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2666 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2667 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2668
2669 /*
2670 * Unmap PM I/O ports, will remap it with the actual base after state
2671 * successfully loaded.
2672 */
2673 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2674 AssertRCReturn(rc, rc);
2675
2676 /*
2677 * Unregister SMBus handlers, will register with actual base after state
2678 * successfully loaded.
2679 */
2680 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2681 AssertRCReturn(rc, rc);
2682 acpiR3SMBusResetDevice(pThis);
2683
2684 switch (uVersion)
2685 {
2686 case 4:
2687 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2688 break;
2689 case 5:
2690 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2691 break;
2692 case 6:
2693 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2694 break;
2695 case 7:
2696 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2697 break;
2698 case 8:
2699 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2700 break;
2701 default:
2702 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2703 break;
2704 }
2705 if (RT_SUCCESS(rc))
2706 {
2707 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2708 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2709 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2710 AssertRCReturn(rc, rc);
2711 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2712 AssertRCReturn(rc, rc);
2713 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2714 AssertRCReturn(rc, rc);
2715 rc = acpiR3FetchBatteryInfo(pThis);
2716 AssertRCReturn(rc, rc);
2717
2718 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2719 DEVACPI_LOCK_R3(pDevIns, pThis);
2720 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2721 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2722 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2723 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2724 DEVACPI_UNLOCK(pDevIns, pThis);
2725 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2726 }
2727 return rc;
2728}
2729
2730/**
2731 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2732 */
2733static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2734{
2735 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2736 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2737 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2738 return NULL;
2739}
2740
2741/**
2742 * Calculate the check sum for some ACPI data before planting it.
2743 *
2744 * All the bytes must add up to 0.
2745 *
2746 * @returns check sum.
2747 * @param pvSrc What to check sum.
2748 * @param cbData The amount of data to checksum.
2749 */
2750static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2751{
2752 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2753 uint8_t uSum = 0;
2754 for (size_t i = 0; i < cbData; ++i)
2755 uSum += pbSrc[i];
2756 return -uSum;
2757}
2758
2759/**
2760 * Prepare a ACPI table header.
2761 */
2762static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2763 const char au8Signature[4],
2764 uint32_t u32Length, uint8_t u8Revision)
2765{
2766 memcpy(header->au8Signature, au8Signature, 4);
2767 header->u32Length = RT_H2LE_U32(u32Length);
2768 header->u8Revision = u8Revision;
2769 memcpy(header->au8OemId, pThis->au8OemId, 6);
2770 memcpy(header->au8OemTabId, "VBOX", 4);
2771 memcpy(header->au8OemTabId+4, au8Signature, 4);
2772 header->u32OemRevision = RT_H2LE_U32(1);
2773 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2774 header->u32CreatorRev = pThis->u32CreatorRev;
2775}
2776
2777/**
2778 * Initialize a generic address structure (ACPIGENADDR).
2779 */
2780static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2781 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2782 uint8_t u8AccessSize, uint64_t u64Address)
2783{
2784 g->u8AddressSpaceId = u8AddressSpaceId;
2785 g->u8RegisterBitWidth = u8RegisterBitWidth;
2786 g->u8RegisterBitOffset = u8RegisterBitOffset;
2787 g->u8AccessSize = u8AccessSize;
2788 g->u64Address = RT_H2LE_U64(u64Address);
2789}
2790
2791/**
2792 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2793 */
2794DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2795{
2796 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2797}
2798
2799/**
2800 * Plant the Differentiated System Description Table (DSDT).
2801 */
2802static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2803{
2804 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2805}
2806
2807/**
2808 * Plant the Secondary System Description Table (SSDT).
2809 */
2810static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2811{
2812 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2813}
2814
2815/**
2816 * Plant the Firmware ACPI Control Structure (FACS).
2817 */
2818static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2819{
2820 ACPITBLFACS facs;
2821
2822 memset(&facs, 0, sizeof(facs));
2823 memcpy(facs.au8Signature, "FACS", 4);
2824 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2825 facs.u32HWSignature = RT_H2LE_U32(0);
2826 facs.u32FWVector = RT_H2LE_U32(0);
2827 facs.u32GlobalLock = RT_H2LE_U32(0);
2828 facs.u32Flags = RT_H2LE_U32(0);
2829 facs.u64X_FWVector = RT_H2LE_U64(0);
2830 facs.u8Version = 1;
2831
2832 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2833}
2834
2835/**
2836 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2837 */
2838static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2839 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2840{
2841 ACPITBLFADT fadt;
2842
2843 /* First the ACPI version 2+ version of the structure. */
2844 memset(&fadt, 0, sizeof(fadt));
2845 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2846 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2847 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2848 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2849 fadt.u8PreferredPMProfile = 0; /* unspecified */
2850 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2851 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2852 fadt.u8AcpiEnable = ACPI_ENABLE;
2853 fadt.u8AcpiDisable = ACPI_DISABLE;
2854 fadt.u8S4BIOSReq = 0;
2855 fadt.u8PStateCnt = 0;
2856 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2857 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2858 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2859 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2860 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2861 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2862 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2863 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2864 fadt.u8PM1EVTLEN = 4;
2865 fadt.u8PM1CTLLEN = 2;
2866 fadt.u8PM2CTLLEN = 0;
2867 fadt.u8PMTMLEN = 4;
2868 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2869 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2870 fadt.u8GPE1BASE = GPE1_BASE;
2871 fadt.u8CSTCNT = 0;
2872 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2873 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2874 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2875 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2876 fadt.u8DutyOffset = 0;
2877 fadt.u8DutyWidth = 0;
2878 fadt.u8DayAlarm = 0;
2879 fadt.u8MonAlarm = 0;
2880 fadt.u8Century = 0;
2881 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2882 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2883 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2884 | FADT_FL_FIX_RTC
2885 | FADT_FL_TMR_VAL_EXT
2886 | FADT_FL_RESET_REG_SUP);
2887
2888 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2889 if (pThis->fCpuHotPlug)
2890 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2891
2892 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2893 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2894 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2895 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2896 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2897 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2898 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2899 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2900 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2901 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2902 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2903 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2904 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2905 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2906
2907 /* Now the ACPI 1.0 version. */
2908 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2909 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2910 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2911 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2912 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2913}
2914
2915/**
2916 * Plant the root System Description Table.
2917 *
2918 * The RSDT and XSDT tables are basically identical. The only difference is 32
2919 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2920 * ACPI 2.0 and up.
2921 */
2922static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2923{
2924 ACPITBLRSDT *rsdt;
2925 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2926
2927 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2928 if (!rsdt)
2929 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2930
2931 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2932 for (unsigned int i = 0; i < nb_entries; ++i)
2933 {
2934 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2935 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2936 }
2937 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2938 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
2939 RTMemFree(rsdt);
2940 return VINF_SUCCESS;
2941}
2942
2943/**
2944 * Plant the Extended System Description Table.
2945 */
2946static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2947{
2948 ACPITBLXSDT *xsdt;
2949 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2950 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
2951 if (!xsdt)
2952 return VERR_NO_TMP_MEMORY;
2953
2954 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
2955
2956 if (pThis->cCustTbls > 0)
2957 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2958
2959 for (unsigned int i = 0; i < nb_entries; ++i)
2960 {
2961 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2962 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2963 }
2964 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
2965 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
2966
2967 RTMemFree(xsdt);
2968 return VINF_SUCCESS;
2969}
2970
2971/**
2972 * Plant the Root System Description Pointer (RSDP).
2973 */
2974static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2975{
2976 memset(rsdp, 0, sizeof(*rsdp));
2977
2978 /* ACPI 1.0 part (RSDT) */
2979 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2980 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2981 rsdp->u8Revision = ACPI_REVISION;
2982 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2983 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2984
2985 /* ACPI 2.0 part (XSDT) */
2986 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2987 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2988 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2989}
2990
2991/**
2992 * Multiple APIC Description Table.
2993 *
2994 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2995 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2996 * use regular C structure and proxy to raw memory instead.
2997 */
2998class AcpiTableMadt
2999{
3000 /**
3001 * All actual data stored in dynamically allocated memory pointed by this field.
3002 */
3003 uint8_t *m_pbData;
3004 /**
3005 * Number of CPU entries in this MADT.
3006 */
3007 uint32_t m_cCpus;
3008
3009 /**
3010 * Number of interrupt overrides.
3011 */
3012 uint32_t m_cIsos;
3013
3014public:
3015 /**
3016 * Address of ACPI header
3017 */
3018 inline ACPITBLHEADER *header_addr(void) const
3019 {
3020 return (ACPITBLHEADER *)m_pbData;
3021 }
3022
3023 /**
3024 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
3025 * although address is the same for all of them.
3026 */
3027 inline uint32_t *u32LAPIC_addr(void) const
3028 {
3029 return (uint32_t *)(header_addr() + 1);
3030 }
3031
3032 /**
3033 * Address of APIC flags
3034 */
3035 inline uint32_t *u32Flags_addr(void) const
3036 {
3037 return (uint32_t *)(u32LAPIC_addr() + 1);
3038 }
3039
3040 /**
3041 * Address of ISO description
3042 */
3043 inline ACPITBLISO *ISO_addr(void) const
3044 {
3045 return (ACPITBLISO *)(u32Flags_addr() + 1);
3046 }
3047
3048 /**
3049 * Address of per-CPU LAPIC descriptions
3050 */
3051 inline ACPITBLLAPIC *LApics_addr(void) const
3052 {
3053 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3054 }
3055
3056 /**
3057 * Address of IO APIC description
3058 */
3059 inline ACPITBLIOAPIC *IOApic_addr(void) const
3060 {
3061 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3062 }
3063
3064 /**
3065 * Size of MADT.
3066 * Note that this function assumes IOApic to be the last field in structure.
3067 */
3068 inline uint32_t size(void) const
3069 {
3070 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3071 }
3072
3073 /**
3074 * Raw data of MADT.
3075 */
3076 inline const uint8_t *data(void) const
3077 {
3078 return m_pbData;
3079 }
3080
3081 /**
3082 * Size of MADT for given ACPI config, useful to compute layout.
3083 */
3084 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3085 {
3086 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3087 }
3088
3089 /*
3090 * Constructor, only works in Ring 3, doesn't look like a big deal.
3091 */
3092 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3093 {
3094 m_cCpus = cCpus;
3095 m_cIsos = cIsos;
3096 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3097 uint32_t cb = size();
3098 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3099 }
3100
3101 ~AcpiTableMadt()
3102 {
3103 RTMemFree(m_pbData);
3104 }
3105};
3106
3107
3108/**
3109 * Plant the Multiple APIC Description Table (MADT).
3110 *
3111 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3112 *
3113 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3114 */
3115static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3116{
3117 uint16_t cpus = pThis->cCpus;
3118 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3119
3120 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3121
3122 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3123 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3124
3125 /* LAPICs records */
3126 ACPITBLLAPIC* lapic = madt.LApics_addr();
3127 for (uint16_t i = 0; i < cpus; i++)
3128 {
3129 lapic->u8Type = 0;
3130 lapic->u8Length = sizeof(ACPITBLLAPIC);
3131 lapic->u8ProcId = i;
3132 /** Must match numbering convention in MPTABLES */
3133 lapic->u8ApicId = i;
3134 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3135 lapic++;
3136 }
3137
3138 /* IO-APIC record */
3139 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3140 ioapic->u8Type = 1;
3141 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3142 /** Must match MP tables ID */
3143 ioapic->u8IOApicId = cpus;
3144 ioapic->u8Reserved = 0;
3145 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3146 ioapic->u32GSIB = RT_H2LE_U32(0);
3147
3148 /* Interrupt Source Overrides */
3149 /* Flags:
3150 bits[3:2]:
3151 00 conforms to the bus
3152 01 edge-triggered
3153 10 reserved
3154 11 level-triggered
3155 bits[1:0]
3156 00 conforms to the bus
3157 01 active-high
3158 10 reserved
3159 11 active-low */
3160 /* If changing, also update PDMIsaSetIrq() and MPS */
3161 ACPITBLISO* isos = madt.ISO_addr();
3162 /* Timer interrupt rule IRQ0 to GSI2 */
3163 isos[0].u8Type = 2;
3164 isos[0].u8Length = sizeof(ACPITBLISO);
3165 isos[0].u8Bus = 0; /* Must be 0 */
3166 isos[0].u8Source = 0; /* IRQ0 */
3167 isos[0].u32GSI = 2; /* connected to pin 2 */
3168 isos[0].u16Flags = 0; /* conform to the bus */
3169
3170 /* ACPI interrupt rule - IRQ9 to GSI9 */
3171 isos[1].u8Type = 2;
3172 isos[1].u8Length = sizeof(ACPITBLISO);
3173 isos[1].u8Bus = 0; /* Must be 0 */
3174 isos[1].u8Source = 9; /* IRQ9 */
3175 isos[1].u32GSI = 9; /* connected to pin 9 */
3176 isos[1].u16Flags = 0xf; /* active low, level triggered */
3177 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3178
3179 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3180 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3181}
3182
3183/**
3184 * Plant the High Performance Event Timer (HPET) descriptor.
3185 */
3186static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3187{
3188 ACPITBLHPET hpet;
3189
3190 memset(&hpet, 0, sizeof(hpet));
3191
3192 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3193 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3194 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3195 0 /* Memory address space */,
3196 64 /* Register bit width */,
3197 0 /* Bit offset */,
3198 0, /* Register access size, is it correct? */
3199 0xfed00000 /* Address */);
3200
3201 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3202 hpet.u32Number = 0;
3203 hpet.u32MinTick = 4096;
3204 hpet.u8Attributes = 0;
3205
3206 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3207
3208 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3209}
3210
3211
3212#ifdef VBOX_WITH_IOMMU_AMD
3213/**
3214 * Plant the AMD IOMMU descriptor.
3215 */
3216static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3217{
3218 ACPITBLIOMMU Ivrs;
3219 RT_ZERO(Ivrs);
3220
3221 uint16_t const uIommuBus = 0;
3222 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuPciAddress);
3223 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuPciAddress);
3224
3225 /* IVRS header. */
3226 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3227 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3228 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3229 | RT_BF_MAKE(ACPI_IVINFO_BF_DMA_REMAP_SUP, 0) /* Pre-boot DMA remap support not supported. */
3230 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3231 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3232 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64) /* Virt. Addr size (64 bits) */
3233 | RT_BF_MAKE(ACPI_IVINFO_BF_HT_ATS_RESV, 0); /* ATS response range reserved (only applicable for HT) */
3234
3235 /* IVHD type 10 definition block. */
3236 Ivrs.IvhdType10.u8Type = 0x10;
3237 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3238 + sizeof(Ivrs.IvhdType10Start)
3239 + sizeof(Ivrs.IvhdType10End)
3240 + sizeof(Ivrs.IvhdType10Rsvd0)
3241 + sizeof(Ivrs.IvhdType10Rsvd1)
3242 + sizeof(Ivrs.IvhdType10IoApic)
3243 + sizeof(Ivrs.IvhdType10Hpet);
3244 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3245 Ivrs.IvhdType10.u16CapOffset = IOMMU_PCI_OFF_CAP_HDR;
3246 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR;
3247 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3248 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3249 Ivrs.IvhdType10.u8Flags = ACPI_IVHD_10H_F_COHERENT; /* Remote IOTLB etc. not supported. */
3250 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3251 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3252 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3253 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3254 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3255 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3256 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3257 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3258 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3259 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3260 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3261 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3262 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3263 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3264 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3265 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3);
3266 /* Start range from BDF (00:01:00). */
3267 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3268 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3269 Ivrs.IvhdType10Start.u8DteSetting = 0;
3270 /* End range at BDF (ff:1f:7). */
3271 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3272 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3273 Ivrs.IvhdType10End.u8DteSetting = 0;
3274
3275 /* Southbridge I/O APIC special device entry. */
3276 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3277 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3278 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3279 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3280 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3281 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3282 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3283 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3284 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3285 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3286
3287 /* HPET special device entry. */
3288 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3289 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3290 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3291 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3292 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3293 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3294
3295 /* IVHD type 11 definition block. */
3296 Ivrs.IvhdType11.u8Type = 0x11;
3297 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3298 + sizeof(Ivrs.IvhdType11Start)
3299 + sizeof(Ivrs.IvhdType11End)
3300 + sizeof(Ivrs.IvhdType11Rsvd0)
3301 + sizeof(Ivrs.IvhdType11Rsvd1)
3302 + sizeof(Ivrs.IvhdType11IoApic)
3303 + sizeof(Ivrs.IvhdType11Hpet);
3304 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3305 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3306 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3307 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3308 Ivrs.IvhdType11.u8Flags = ACPI_IVHD_11H_F_COHERENT;
3309 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3310 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3311 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3312 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3313 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3314 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3315 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3316 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3317 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3318 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3319 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 1)
3320 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3321 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3322 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3323 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3)
3324 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3325 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3326 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3327 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3328 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3329 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3330 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3331 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3332 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3333 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS)
3334 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3335 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3336 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3337 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3338 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3339 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3340 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3341 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3342 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3343 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3344 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3345 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3346 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3347 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3348
3349 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3350 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3351 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3352 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3353 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3354 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3355 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3356
3357 /* Finally, compute checksum. */
3358 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3359
3360 /* Plant the ACPI table. */
3361 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3362}
3363#endif /* VBOX_WITH_IOMMU_AMD */
3364
3365
3366#ifdef VBOX_WITH_IOMMU_INTEL
3367/**
3368 * Plant the Intel IOMMU (VT-d) descriptor.
3369 */
3370static void acpiR3SetupIommuIntel(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3371{
3372 ACPITBLVTD VtdTable;
3373 RT_ZERO(VtdTable);
3374
3375 /* VT-d Table. */
3376 acpiR3PrepareHeader(pThis, &VtdTable.Dmar.Hdr, "DMAR", sizeof(ACPITBLVTD), ACPI_DMAR_REVISION);
3377
3378 /* DMAR. */
3379 uint8_t cPhysAddrBits;
3380 uint8_t cLinearAddrBits;
3381 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cPhysAddrBits, &cLinearAddrBits);
3382 Assert(cPhysAddrBits > 0); NOREF(cLinearAddrBits);
3383 VtdTable.Dmar.uHostAddrWidth = cPhysAddrBits - 1;
3384 VtdTable.Dmar.fFlags = VTD_ACPI_DMAR_FLAGS;
3385
3386 /* DRHD. */
3387 VtdTable.Drhd.cbLength = sizeof(ACPIDRHD) /* + sizeof(VtdTable.DevScope) */;
3388 VtdTable.Drhd.fFlags = ACPI_DRHD_F_INCLUDE_PCI_ALL;
3389 VtdTable.Drhd.uRegBaseAddr = VTD_MMIO_BASE_PHYSADDR;
3390
3391 /* Finally, compute checksum. */
3392 VtdTable.Dmar.Hdr.u8Checksum = acpiR3Checksum(&VtdTable, sizeof(VtdTable));
3393
3394 /* Plant the ACPI table. */
3395 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&VtdTable, sizeof(VtdTable));
3396}
3397#endif /* VBOX_WITH_IOMMU_INTEL */
3398
3399
3400/**
3401 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3402 * descriptor.
3403 *
3404 * @param pDevIns The device instance.
3405 * @param pThis The ACPI shared instance data.
3406 * @param GCPhysDst Where to plant it.
3407 */
3408static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3409{
3410 struct
3411 {
3412 ACPITBLMCFG hdr;
3413 ACPITBLMCFGENTRY entry;
3414 } tbl;
3415 uint8_t u8StartBus = 0;
3416 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3417
3418 RT_ZERO(tbl);
3419
3420 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3421 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3422 tbl.entry.u8StartBus = u8StartBus;
3423 tbl.entry.u8EndBus = u8EndBus;
3424 // u16PciSegmentGroup must match _SEG in ACPI table
3425
3426 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3427
3428 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3429}
3430
3431/**
3432 * Used by acpiR3PlantTables and acpiConstruct.
3433 *
3434 * @returns Guest memory address.
3435 */
3436static uint32_t apicR3FindRsdpSpace(void)
3437{
3438 return 0xe0000;
3439}
3440
3441/**
3442 * Called by acpiR3Construct to read and allocate a custom ACPI table
3443 *
3444 * @param pDevIns The device instance.
3445 * @param ppu8CustBin Address to receive the address of the table
3446 * @param pcbCustBin Address to receive the size of the the table.
3447 * @param pszCustBinFile
3448 * @param cbBufAvail Maximum space in bytes available for the custom
3449 * table (including header).
3450 */
3451static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3452 char *pszCustBinFile, uint32_t cbBufAvail)
3453{
3454 RTFILE FileCUSTBin;
3455 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3456 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3457 if (RT_SUCCESS(rc))
3458 {
3459 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3460 if (RT_SUCCESS(rc))
3461 {
3462 /* The following checks should be in sync the AssertReleaseMsg's below. */
3463 if ( *pcbCustBin > cbBufAvail
3464 || *pcbCustBin < sizeof(ACPITBLHEADER))
3465 rc = VERR_TOO_MUCH_DATA;
3466
3467 /*
3468 * Allocate buffer for the custom table binary data.
3469 */
3470 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3471 if (*ppu8CustBin)
3472 {
3473 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3474 if (RT_FAILURE(rc))
3475 {
3476 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3477 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3478 *ppu8CustBin = NULL;
3479 }
3480 }
3481 else
3482 {
3483 rc = VERR_NO_MEMORY;
3484 }
3485 RTFileClose(FileCUSTBin);
3486 }
3487 }
3488 return rc;
3489}
3490
3491/**
3492 * Create the ACPI tables in guest memory.
3493 */
3494static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3495{
3496 int rc;
3497 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3498 RTGCPHYS32 GCPhysHpet = 0;
3499#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3500 RTGCPHYS32 GCPhysIommu = 0;
3501#endif
3502 RTGCPHYS32 GCPhysApic = 0;
3503 RTGCPHYS32 GCPhysSsdt = 0;
3504 RTGCPHYS32 GCPhysMcfg = 0;
3505 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3506 uint32_t addend = 0;
3507#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3508 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3509 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3510#else
3511 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3512 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3513#endif
3514 uint32_t cAddr;
3515 uint32_t iMadt = 0;
3516 uint32_t iHpet = 0;
3517#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3518 uint32_t iIommu = 0;
3519#endif
3520 uint32_t iSsdt = 0;
3521 uint32_t iMcfg = 0;
3522 uint32_t iCust = 0;
3523 size_t cbRsdt = sizeof(ACPITBLHEADER);
3524 size_t cbXsdt = sizeof(ACPITBLHEADER);
3525
3526 cAddr = 1; /* FADT */
3527 if (pThis->u8UseIOApic)
3528 iMadt = cAddr++; /* MADT */
3529
3530 if (pThis->fUseHpet)
3531 iHpet = cAddr++; /* HPET */
3532
3533#ifdef VBOX_WITH_IOMMU_AMD
3534 if (pThis->fUseIommuAmd)
3535 iIommu = cAddr++; /* IOMMU (AMD) */
3536#endif
3537
3538#ifdef VBOX_WITH_IOMMU_INTEL
3539 if (pThis->fUseIommuIntel)
3540 iIommu = cAddr++; /* IOMMU (AMD) */
3541#endif
3542
3543 if (pThis->fUseMcfg)
3544 iMcfg = cAddr++; /* MCFG */
3545
3546 if (pThis->cCustTbls > 0)
3547 {
3548 iCust = cAddr; /* CUST */
3549 cAddr += pThis->cCustTbls;
3550 }
3551
3552 iSsdt = cAddr++; /* SSDT */
3553
3554 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3555 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3556
3557 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3558 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3559
3560 /*
3561 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3562 * The latter starts never below 4G.
3563 */
3564 PVM pVM = PDMDevHlpGetVM(pDevIns);
3565 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3566 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3567
3568 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3569 if (pThis->fPciPref64Enabled)
3570 {
3571 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3572 if (pThis->u64PciPref64Max > u64PciPref64Min)
3573 {
3574 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3575 pThis->u64PciPref64Min = u64PciPref64Min;
3576 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3577 u64PciPref64Min, pThis->u64PciPref64Max-1));
3578 }
3579 else
3580 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3581 u64PciPref64Min, pThis->u64PciPref64Max-1));
3582 }
3583 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3584 {
3585 /* Note: This is also enforced by DevPcBios.cpp. */
3586 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3587 cbBelow4GB = UINT32_C(0xfe000000);
3588 }
3589 pThis->cbRamLow = cbBelow4GB;
3590
3591 GCPhysCur = 0;
3592 GCPhysRsdt = GCPhysCur;
3593
3594 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3595 GCPhysXsdt = GCPhysCur;
3596
3597 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3598 GCPhysFadtAcpi1 = GCPhysCur;
3599
3600 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3601 GCPhysFadtAcpi2 = GCPhysCur;
3602
3603 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3604 GCPhysFacs = GCPhysCur;
3605
3606 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3607 if (pThis->u8UseIOApic)
3608 {
3609 GCPhysApic = GCPhysCur;
3610 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3611 }
3612 if (pThis->fUseHpet)
3613 {
3614 GCPhysHpet = GCPhysCur;
3615 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3616 }
3617#ifdef VBOX_WITH_IOMMU_AMD
3618 if (pThis->fUseIommuAmd)
3619 {
3620 GCPhysIommu = GCPhysCur;
3621 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3622 }
3623#endif
3624#ifdef VBOX_WITH_IOMMU_INTEL
3625 if (pThis->fUseIommuIntel)
3626 {
3627 GCPhysIommu = GCPhysCur;
3628 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLVTD), 16);
3629 }
3630#endif
3631
3632 if (pThis->fUseMcfg)
3633 {
3634 GCPhysMcfg = GCPhysCur;
3635 /* Assume one entry */
3636 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3637 }
3638
3639 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3640 {
3641 aGCPhysCust[i] = GCPhysCur;
3642 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3643 }
3644
3645 void *pvSsdtCode = NULL;
3646 size_t cbSsdt = 0;
3647 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3648 if (RT_FAILURE(rc))
3649 return rc;
3650
3651 GCPhysSsdt = GCPhysCur;
3652 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3653
3654 GCPhysDsdt = GCPhysCur;
3655
3656 void *pvDsdtCode = NULL;
3657 size_t cbDsdt = 0;
3658 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3659 if (RT_FAILURE(rc))
3660 return rc;
3661
3662 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3663
3664 if (GCPhysCur > 0x10000)
3665 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3666 N_("Error: ACPI tables bigger than 64KB"));
3667
3668 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3669 addend = pThis->cbRamLow - 0x10000;
3670 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3671 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3672 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3673 if (pThis->u8UseIOApic)
3674 Log((" MADT 0x%08X", GCPhysApic + addend));
3675 if (pThis->fUseHpet)
3676 Log((" HPET 0x%08X", GCPhysHpet + addend));
3677 if (pThis->fUseMcfg)
3678 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3679 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3680 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3681 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3682 Log(("\n"));
3683
3684 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3685 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3686 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3687 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3688 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3689
3690 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3691 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3692 if (pThis->u8UseIOApic)
3693 {
3694 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3695 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3696 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3697 }
3698 if (pThis->fUseHpet)
3699 {
3700 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3701 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3702 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3703 }
3704#ifdef VBOX_WITH_IOMMU_AMD
3705 if (pThis->fUseIommuAmd)
3706 {
3707 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommu + addend);
3708 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3709 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3710 }
3711#endif
3712#ifdef VBOX_WITH_IOMMU_INTEL
3713 if (pThis->fUseIommuIntel)
3714 {
3715 acpiR3SetupIommuIntel(pDevIns, pThis, GCPhysIommu + addend);
3716 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3717 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3718 }
3719#endif
3720 if (pThis->fUseMcfg)
3721 {
3722 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3723 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3724 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3725 }
3726 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3727 {
3728 Assert(i < MAX_CUST_TABLES);
3729 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3730 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3731 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3732 uint8_t* pSig = pThisCC->apu8CustBin[i];
3733 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3734 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3735 }
3736
3737 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3738 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3739 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3740 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3741
3742 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3743 if (RT_FAILURE(rc))
3744 return rc;
3745 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3746}
3747
3748/**
3749 * @callback_method_impl{FNPCICONFIGREAD}
3750 */
3751static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3752 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3753{
3754 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3755 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3756 return rcStrict;
3757}
3758
3759/**
3760 * @callback_method_impl{FNPCICONFIGWRITE}
3761 */
3762static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3763 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3764{
3765 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3766 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3767
3768 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3769 DEVACPI_LOCK_R3(pDevIns, pThis);
3770
3771 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3772 {
3773 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3774 u32Value = SCI_INT;
3775 }
3776
3777 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3778
3779 /* Assume that the base address is only changed when the corresponding
3780 * hardware functionality is disabled. The IO region is mapped when the
3781 * functionality is enabled by the guest. */
3782
3783 if (uAddress == PMREGMISC)
3784 {
3785 RTIOPORT NewIoPortBase = 0;
3786 /* Check Power Management IO Space Enable (PMIOSE) bit */
3787 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3788 {
3789 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3790 NewIoPortBase &= 0xffc0;
3791 }
3792
3793 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
3794 AssertRC(rc);
3795 }
3796
3797 if (uAddress == SMBHSTCFG)
3798 {
3799 RTIOPORT NewIoPortBase = 0;
3800 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3801 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3802 {
3803 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3804 NewIoPortBase &= 0xfff0;
3805 }
3806
3807 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
3808 AssertRC(rc);
3809 }
3810
3811 DEVACPI_UNLOCK(pDevIns, pThis);
3812 return rcStrict;
3813}
3814
3815/**
3816 * Attach a new CPU.
3817 *
3818 * @returns VBox status code.
3819 * @param pDevIns The device instance.
3820 * @param iLUN The logical unit which is being attached.
3821 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3822 *
3823 * @remarks This code path is not used during construction.
3824 */
3825static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3826{
3827 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3828 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3829 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3830
3831 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3832 ("Hot-plug flag is not set\n"),
3833 VERR_NOT_SUPPORTED);
3834 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
3835
3836 /* Check if it was already attached */
3837 int rc = VINF_SUCCESS;
3838 DEVACPI_LOCK_R3(pDevIns, pThis);
3839 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3840 {
3841 PPDMIBASE IBaseTmp;
3842 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
3843 if (RT_SUCCESS(rc))
3844 {
3845 /* Enable the CPU */
3846 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
3847
3848 /*
3849 * Lock the CPU because we don't know if the guest will use it or not.
3850 * Prevents ejection while the CPU is still used
3851 */
3852 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
3853 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
3854 pThis->u32CpuEvent = iLUN;
3855
3856 /* Notify the guest */
3857 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3858 }
3859 }
3860 DEVACPI_UNLOCK(pDevIns, pThis);
3861 return rc;
3862}
3863
3864/**
3865 * Detach notification.
3866 *
3867 * @param pDevIns The device instance.
3868 * @param iLUN The logical unit which is being detached.
3869 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
3870 */
3871static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
3872{
3873 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3874
3875 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
3876
3877 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
3878 ("Hot-plug flag is not set\n"));
3879
3880 /* Check if it was already detached */
3881 DEVACPI_LOCK_R3(pDevIns, pThis);
3882 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
3883 {
3884 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
3885 {
3886 /* Disable the CPU */
3887 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
3888 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
3889 pThis->u32CpuEvent = iLUN;
3890
3891 /* Notify the guest */
3892 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
3893 }
3894 else
3895 AssertMsgFailed(("CPU is still locked by the guest\n"));
3896 }
3897 DEVACPI_UNLOCK(pDevIns, pThis);
3898}
3899
3900/**
3901 * @interface_method_impl{PDMDEVREG,pfnResume}
3902 */
3903static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
3904{
3905 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3906 if (pThis->fSetWakeupOnResume)
3907 {
3908 Log(("acpiResume: setting WAK_STS\n"));
3909 pThis->fSetWakeupOnResume = false;
3910 pThis->pm1a_sts |= WAK_STS;
3911 }
3912}
3913
3914/**
3915 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
3916 */
3917static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
3918{
3919 RT_NOREF(enmCtx);
3920 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3921 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3922 acpiR3PlantTables(pDevIns, pThis, pThisCC);
3923}
3924
3925/**
3926 * @interface_method_impl{PDMDEVREG,pfnReset}
3927 */
3928static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
3929{
3930 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3931 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3932
3933 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
3934 acpiSetIrq(pDevIns, 0);
3935
3936 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
3937 pThis->pm1a_en = 0;
3938 pThis->pm1a_sts = 0;
3939 pThis->pm1a_ctl = 0;
3940 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
3941 pThis->uPmTimerVal = 0;
3942 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
3943 pThis->uPmTimeOld = pThis->uPmTimerVal;
3944 pThis->uBatteryIndex = 0;
3945 pThis->uSystemInfoIndex = 0;
3946 pThis->gpe0_en = 0;
3947 pThis->gpe0_sts = 0;
3948 pThis->uSleepState = 0;
3949 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
3950
3951 /* Real device behavior is resetting only the PM controller state,
3952 * but we're additionally doing the job of the BIOS. */
3953 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
3954 acpiR3PmPCIBIOSFake(pDevIns, pThis);
3955
3956 /* Reset SMBus base and PCI config space in addition to the SMBus controller
3957 * state. Real device behavior is only the SMBus controller state reset,
3958 * but we're additionally doing the job of the BIOS. */
3959 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
3960 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
3961 acpiR3SMBusResetDevice(pThis);
3962}
3963
3964/**
3965 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3966 */
3967static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
3968{
3969 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3970 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3971 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3972
3973 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3974 {
3975 if (pThisCC->apu8CustBin[i])
3976 {
3977 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
3978 pThisCC->apu8CustBin[i] = NULL;
3979 }
3980 }
3981 return VINF_SUCCESS;
3982}
3983
3984/**
3985 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3986 */
3987static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3988{
3989 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3990 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3991 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3992 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3993
3994 /*
3995 * Init data and set defaults.
3996 */
3997 /** @todo move more of the code up! */
3998
3999 pThisCC->pDevIns = pDevIns;
4000 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
4001 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
4002 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
4003 pThis->u32CpuEventType = 0;
4004 pThis->u32CpuEvent = UINT32_C(0xffffffff);
4005
4006 /* The first CPU can't be attached/detached */
4007 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
4008 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
4009
4010 /* IBase */
4011 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
4012 /* IACPIPort */
4013 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
4014 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
4015 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
4016 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
4017 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
4018 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
4019 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
4020
4021 /*
4022 * Set the default critical section to NOP (related to the PM timer).
4023 */
4024 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4025 AssertRCReturn(rc, rc);
4026
4027 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
4028 AssertRCReturn(rc, rc);
4029
4030 /*
4031 * Validate and read the configuration.
4032 */
4033 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
4034 "IOAPIC"
4035 "|NumCPUs"
4036 "|HpetEnabled"
4037 "|McfgEnabled"
4038 "|McfgBase"
4039 "|McfgLength"
4040 "|PciPref64Enabled"
4041 "|PciPref64LimitGB"
4042 "|SmcEnabled"
4043 "|FdcEnabled"
4044 "|ShowRtc"
4045 "|ShowCpu"
4046 "|NicPciAddress"
4047 "|AudioPciAddress"
4048 "|NvmePciAddress"
4049 "|IocPciAddress"
4050 "|HostBusPciAddress"
4051 "|EnableSuspendToDisk"
4052 "|PowerS1Enabled"
4053 "|PowerS4Enabled"
4054 "|CpuHotPlug"
4055 "|AmlFilePath"
4056 "|Serial0IoPortBase"
4057 "|Serial1IoPortBase"
4058 "|Serial2IoPortBase"
4059 "|Serial3IoPortBase"
4060 "|Serial0Irq"
4061 "|Serial1Irq"
4062 "|Serial2Irq"
4063 "|Serial3Irq"
4064 "|AcpiOemId"
4065 "|AcpiCreatorId"
4066 "|AcpiCreatorRev"
4067 "|CustomTable"
4068 "|CustomTable0"
4069 "|CustomTable1"
4070 "|CustomTable2"
4071 "|CustomTable3"
4072 "|Parallel0IoPortBase"
4073 "|Parallel1IoPortBase"
4074 "|Parallel0Irq"
4075 "|Parallel1Irq"
4076 "|IommuIntelEnabled"
4077 "|IommuAmdEnabled"
4078 "|IommuPciAddress"
4079 "|SbIoApicPciAddress"
4080 , "");
4081
4082 /* query whether we are supposed to present an IOAPIC */
4083 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
4084 if (RT_FAILURE(rc))
4085 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
4086
4087 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
4088 if (RT_FAILURE(rc))
4089 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
4090
4091 /* query whether we are supposed to present an FDC controller */
4092 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
4093 if (RT_FAILURE(rc))
4094 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
4095
4096 /* query whether we are supposed to present HPET */
4097 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
4098 if (RT_FAILURE(rc))
4099 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
4100 /* query MCFG configuration */
4101 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
4102 if (RT_FAILURE(rc))
4103 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4104 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4105 if (RT_FAILURE(rc))
4106 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4107 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4108
4109 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4110 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4111 if (RT_FAILURE(rc))
4112 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4113
4114 /* query the limit of the the 64-bit prefetchable memory window */
4115 uint64_t u64PciPref64MaxGB;
4116 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4117 if (RT_FAILURE(rc))
4118 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4119 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4120
4121 /* query whether we are supposed to present SMC */
4122 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4123 if (RT_FAILURE(rc))
4124 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4125
4126 /* query whether we are supposed to present RTC object */
4127 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4128 if (RT_FAILURE(rc))
4129 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4130
4131 /* query whether we are supposed to present CPU objects */
4132 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4133 if (RT_FAILURE(rc))
4134 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4135
4136 /* query primary NIC PCI address (GIGE) */
4137 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4138 if (RT_FAILURE(rc))
4139 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4140
4141 /* query HD Audio PCI address (HDAA) */
4142 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4143 if (RT_FAILURE(rc))
4144 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4145
4146 /* query NVMe PCI address (NVMA) */
4147 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4148 if (RT_FAILURE(rc))
4149 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4150
4151 /* query IO controller (southbridge) PCI address */
4152 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4153 if (RT_FAILURE(rc))
4154 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4155
4156 /* query host bus controller PCI address */
4157 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4158 if (RT_FAILURE(rc))
4159 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4160
4161 /* query whether S1 power state should be exposed */
4162 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4163 if (RT_FAILURE(rc))
4164 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4165
4166 /* query whether S4 power state should be exposed */
4167 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4168 if (RT_FAILURE(rc))
4169 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4170
4171 /* query whether S1 power state should save the VM state */
4172 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4173 if (RT_FAILURE(rc))
4174 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4175
4176 /* query whether we are allow CPU hot plugging */
4177 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4178 if (RT_FAILURE(rc))
4179 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4180
4181 /* query serial info */
4182 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4183 if (RT_FAILURE(rc))
4184 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4185
4186 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4187 if (RT_FAILURE(rc))
4188 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4189
4190 /* Serial 1 is enabled, get config data */
4191 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4192 if (RT_FAILURE(rc))
4193 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4194
4195 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4196 if (RT_FAILURE(rc))
4197 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4198
4199 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4200 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4201 if (RT_FAILURE(rc))
4202 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4203
4204 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4205 if (RT_FAILURE(rc))
4206 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4207
4208 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4209 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4210 if (RT_FAILURE(rc))
4211 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4212
4213 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4214 if (RT_FAILURE(rc))
4215 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4216 /*
4217 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4218 * the corresponding parallel port is not enabled.
4219 */
4220 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4221 if (RT_FAILURE(rc))
4222 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4223
4224 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4225 if (RT_FAILURE(rc))
4226 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4227
4228 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4229 if (RT_FAILURE(rc))
4230 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4231
4232 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4233 if (RT_FAILURE(rc))
4234 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4235
4236#ifdef VBOX_WITH_IOMMU_AMD
4237 /* Query whether an IOMMU (AMD) is enabled. */
4238 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommuAmd, false);
4239 if (RT_FAILURE(rc))
4240 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdEnabled\""));
4241
4242 if (pThis->fUseIommuAmd)
4243 {
4244 /* Query IOMMU AMD address (IOMA). */
4245 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress, 0);
4246 if (RT_FAILURE(rc))
4247 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4248
4249 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4250 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress, 0);
4251 if (RT_FAILURE(rc))
4252 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4253
4254 /* Warn if the IOMMU Address is at the PCI host-bridge address. */
4255 /** @todo We should eventually not assign the IOMMU at this address, see
4256 * @bugref{9654#c53}. */
4257 if (!pThis->u32IommuPciAddress)
4258 LogRel(("ACPI: Warning! AMD IOMMU assigned the PCI host bridge address.\n"));
4259
4260 /* Warn if the SB IOAPIC is not at the required address if an AMD IOMMU is configured. */
4261 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4262 {
4263 /** @todo Maybe make this a VM startup failure later. */
4264 LogRel(("ACPI: Warning! Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4265 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4266 }
4267 }
4268#endif
4269
4270#ifdef VBOX_WITH_IOMMU_INTEL
4271 /* Query whether an IOMMU (Intel) is enabled. */
4272 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuIntelEnabled", &pThis->fUseIommuIntel, false);
4273 if (RT_FAILURE(rc))
4274 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuIntelEnabled\""));
4275
4276 if (pThis->fUseIommuIntel)
4277 {
4278 /* Query IOMMU Intel address. */
4279 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress, 0);
4280 if (RT_FAILURE(rc))
4281 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4282 }
4283#endif
4284
4285 /* Don't even think about enabling an Intel and an AMD IOMMU at the same time! */
4286 if ( pThis->fUseIommuAmd
4287 && pThis->fUseIommuIntel)
4288 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Cannot enable Intel and AMD IOMMU simultaneously!"));
4289
4290 /* Try to attach the other CPUs */
4291 for (unsigned i = 1; i < pThis->cCpus; i++)
4292 {
4293 if (pThis->fCpuHotPlug)
4294 {
4295 PPDMIBASE IBaseTmp;
4296 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4297
4298 if (RT_SUCCESS(rc))
4299 {
4300 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4301 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4302 Log(("acpi: Attached CPU %u\n", i));
4303 }
4304 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4305 Log(("acpi: CPU %u not attached yet\n", i));
4306 else
4307 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4308 }
4309 else
4310 {
4311 /* CPU is always attached if hot-plug is not enabled. */
4312 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4313 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4314 }
4315 }
4316
4317 char szOemId[16];
4318 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4319 if (RT_FAILURE(rc))
4320 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4321 size_t cchOemId = strlen(szOemId);
4322 if (cchOemId > 6)
4323 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4324 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4325 memcpy(pThis->au8OemId, szOemId, cchOemId);
4326
4327 char szCreatorId[16];
4328 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4329 if (RT_FAILURE(rc))
4330 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4331 size_t cchCreatorId = strlen(szCreatorId);
4332 if (cchCreatorId > 4)
4333 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4334 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4335 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4336
4337 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4338 if (RT_FAILURE(rc))
4339 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4340
4341 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4342
4343 /*
4344 * Load custom ACPI tables.
4345 */
4346 /* Total space available for custom ACPI tables */
4347 /** @todo define as appropriate, remove as a magic number, and document
4348 * limitation in product manual */
4349 uint32_t cbBufAvail = 3072;
4350 pThis->cCustTbls = 0;
4351
4352 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4353 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4354 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4355 {
4356 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4357
4358 /*
4359 * Get the custom table binary file name.
4360 */
4361 char *pszCustBinFile = NULL;
4362 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4363 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4364 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4365 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4366 {
4367 rc = VINF_SUCCESS;
4368 pszCustBinFile = NULL;
4369 }
4370 else if (RT_FAILURE(rc))
4371 return PDMDEV_SET_ERROR(pDevIns, rc,
4372 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4373 else if (!*pszCustBinFile)
4374 {
4375 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4376 pszCustBinFile = NULL;
4377 }
4378
4379 /*
4380 * Determine the custom table binary size, open specified file in the process.
4381 */
4382 if (pszCustBinFile)
4383 {
4384 uint32_t idxCust = pThis->cCustTbls;
4385 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4386 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4387 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4388 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4389 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4390 if (RT_FAILURE(rc))
4391 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4392 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4393
4394 /* Update custom OEM attributes based on custom table */
4395 /** @todo is it intended for custom tables to overwrite user provided values above? */
4396 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4397 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4398 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4399 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4400 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4401 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4402
4403 pThis->cCustTbls++;
4404 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
4405 }
4406 }
4407
4408 /* Set default PM port base */
4409 pThis->uPmIoPortBase = PM_PORT_BASE;
4410
4411 /* Set default SMBus port base */
4412 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4413
4414 /*
4415 * FDC and SMC try to use the same non-shareable interrupt (6),
4416 * enable only one device.
4417 */
4418 if (pThis->fUseSmc)
4419 pThis->fUseFdc = false;
4420
4421 /*
4422 * Plant ACPI tables.
4423 */
4424 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4425 * au8RSDPPage here. However, there should be no harm in doing it
4426 * twice, so the lazy bird is taking the quick way out for now. */
4427 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4428 if (!GCPhysRsdp)
4429 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4430
4431 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4432 AssertRCReturn(rc, rc);
4433
4434 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4435 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4436 AssertRCReturn(rc, rc);
4437
4438 /*
4439 * Create the PM I/O ports. These can be unmapped and remapped.
4440 */
4441 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4442 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4443 AssertRCReturn(rc, rc);
4444 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4445 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4446 AssertRCReturn(rc, rc);
4447 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4448 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4449 AssertRCReturn(rc, rc);
4450 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4451 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4452 AssertRCReturn(rc, rc);
4453 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4454 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4455 AssertRCReturn(rc, rc);
4456 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4457 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4458 AssertRCReturn(rc, rc);
4459 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4460 AssertRCReturn(rc, rc);
4461
4462 /*
4463 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4464 */
4465 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4466 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4467 AssertRCReturn(rc, rc);
4468 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4469 AssertRCReturn(rc, rc);
4470
4471 /*
4472 * Create and map the fixed I/O ports.
4473 */
4474 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4475 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4476 AssertRCReturn(rc, rc);
4477#ifdef DEBUG_ACPI
4478 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4479 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4480 AssertRCReturn(rc, rc);
4481 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4482 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4483 AssertRCReturn(rc, rc);
4484#endif
4485 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4486 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4487 AssertRCReturn(rc, rc);
4488 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4489 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4490 AssertRCReturn(rc, rc);
4491 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4492 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4493 AssertRCReturn(rc, rc);
4494 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4495 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4496 AssertRCReturn(rc, rc);
4497 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4498 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4499 AssertRCReturn(rc, rc);
4500
4501 /*
4502 * Create the PM timer.
4503 */
4504 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4505 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "ACPI PM", &pThis->hPmTimer);
4506 AssertRCReturn(rc, rc);
4507
4508 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4509 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4510 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4511 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4512
4513 /*
4514 * Set up the PCI device.
4515 */
4516 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4517 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4518
4519 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4520 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4521
4522 /* See p. 50 of PIIX4 manual */
4523 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4524 PDMPciDevSetStatus(pPciDev, 0x0280);
4525
4526 PDMPciDevSetRevisionId(pPciDev, 0x08);
4527
4528 PDMPciDevSetClassProg(pPciDev, 0x00);
4529 PDMPciDevSetClassSub(pPciDev, 0x80);
4530 PDMPciDevSetClassBase(pPciDev, 0x06);
4531
4532 PDMPciDevSetHeaderType(pPciDev, 0x80);
4533
4534 PDMPciDevSetBIST(pPciDev, 0x00);
4535
4536 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4537 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4538
4539 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4540 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4541
4542 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4543 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4544 acpiR3SMBusResetDevice(pThis);
4545
4546 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4547 AssertRCReturn(rc, rc);
4548
4549 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4550 AssertRCReturn(rc, rc);
4551
4552 /*
4553 * Register the saved state.
4554 */
4555 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4556 AssertRCReturn(rc, rc);
4557
4558 /*
4559 * Get the corresponding connector interface
4560 */
4561 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4562 if (RT_SUCCESS(rc))
4563 {
4564 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4565 if (!pThisCC->pDrv)
4566 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4567 }
4568 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4569 {
4570 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4571 rc = VINF_SUCCESS;
4572 }
4573 else
4574 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4575
4576 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4577
4578 return rc;
4579}
4580
4581#else /* !IN_RING3 */
4582
4583/**
4584 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4585 */
4586static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4587{
4588 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4589 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4590
4591 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4592 AssertRCReturn(rc, rc);
4593
4594 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4595 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4596 AssertRCReturn(rc, rc);
4597
4598 return VINF_SUCCESS;
4599}
4600
4601#endif /* !IN_RING3 */
4602
4603/**
4604 * The device registration structure.
4605 */
4606const PDMDEVREG g_DeviceACPI =
4607{
4608 /* .u32Version = */ PDM_DEVREG_VERSION,
4609 /* .uReserved0 = */ 0,
4610 /* .szName = */ "acpi",
4611 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4612 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4613 /* .cMaxInstances = */ ~0U,
4614 /* .uSharedVersion = */ 42,
4615 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4616 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4617 /* .cbInstanceRC = */ 0,
4618 /* .cMaxPciDevices = */ 1,
4619 /* .cMaxMsixVectors = */ 0,
4620 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4621#if defined(IN_RING3)
4622 /* .pszRCMod = */ "VBoxDDRC.rc",
4623 /* .pszR0Mod = */ "VBoxDDR0.r0",
4624 /* .pfnConstruct = */ acpiR3Construct,
4625 /* .pfnDestruct = */ acpiR3Destruct,
4626 /* .pfnRelocate = */ NULL,
4627 /* .pfnMemSetup = */ acpiR3MemSetup,
4628 /* .pfnPowerOn = */ NULL,
4629 /* .pfnReset = */ acpiR3Reset,
4630 /* .pfnSuspend = */ NULL,
4631 /* .pfnResume = */ acpiR3Resume,
4632 /* .pfnAttach = */ acpiR3Attach,
4633 /* .pfnDetach = */ acpiR3Detach,
4634 /* .pfnQueryInterface = */ NULL,
4635 /* .pfnInitComplete = */ NULL,
4636 /* .pfnPowerOff = */ NULL,
4637 /* .pfnSoftReset = */ NULL,
4638 /* .pfnReserved0 = */ NULL,
4639 /* .pfnReserved1 = */ NULL,
4640 /* .pfnReserved2 = */ NULL,
4641 /* .pfnReserved3 = */ NULL,
4642 /* .pfnReserved4 = */ NULL,
4643 /* .pfnReserved5 = */ NULL,
4644 /* .pfnReserved6 = */ NULL,
4645 /* .pfnReserved7 = */ NULL,
4646#elif defined(IN_RING0)
4647 /* .pfnEarlyConstruct = */ NULL,
4648 /* .pfnConstruct = */ acpiRZConstruct,
4649 /* .pfnDestruct = */ NULL,
4650 /* .pfnFinalDestruct = */ NULL,
4651 /* .pfnRequest = */ NULL,
4652 /* .pfnReserved0 = */ NULL,
4653 /* .pfnReserved1 = */ NULL,
4654 /* .pfnReserved2 = */ NULL,
4655 /* .pfnReserved3 = */ NULL,
4656 /* .pfnReserved4 = */ NULL,
4657 /* .pfnReserved5 = */ NULL,
4658 /* .pfnReserved6 = */ NULL,
4659 /* .pfnReserved7 = */ NULL,
4660#elif defined(IN_RC)
4661 /* .pfnConstruct = */ acpiRZConstruct,
4662 /* .pfnReserved0 = */ NULL,
4663 /* .pfnReserved1 = */ NULL,
4664 /* .pfnReserved2 = */ NULL,
4665 /* .pfnReserved3 = */ NULL,
4666 /* .pfnReserved4 = */ NULL,
4667 /* .pfnReserved5 = */ NULL,
4668 /* .pfnReserved6 = */ NULL,
4669 /* .pfnReserved7 = */ NULL,
4670#else
4671# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4672#endif
4673 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4674};
4675
4676#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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