VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 90993

Last change on this file since 90993 was 90908, checked in by vboxsync, 4 years ago

Devices/ACPI: Preliminary TPM support (disabled), bugref:10075
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1/* $Id: DevACPI.cpp 90908 2021-08-26 10:27:04Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/log.h>
28#include <VBox/param.h>
29#include <VBox/pci.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#include <iprt/asm-math.h>
33#include <iprt/file.h>
34#ifdef IN_RING3
35# include <iprt/alloc.h>
36# include <iprt/string.h>
37# include <iprt/uuid.h>
38#endif /* IN_RING3 */
39#ifdef VBOX_WITH_IOMMU_AMD
40# include <VBox/iommu-amd.h>
41#endif
42#ifdef VBOX_WITH_IOMMU_INTEL
43# include <VBox/iommu-intel.h>
44#endif
45
46#include "VBoxDD.h"
47#ifdef VBOX_WITH_IOMMU_AMD
48# include "../Bus/DevIommuAmd.h"
49#endif
50#ifdef VBOX_WITH_IOMMU_INTEL
51# include "../Bus/DevIommuIntel.h"
52#endif
53
54#ifdef LOG_ENABLED
55# define DEBUG_ACPI
56#endif
57
58
59/*********************************************************************************************************************************
60* Defined Constants And Macros *
61*********************************************************************************************************************************/
62#ifdef IN_RING3
63/** Locks the device state, ring-3 only. */
64# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
65 do { \
66 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
67 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSect, rcLock); \
68 } while (0)
69#endif
70/** Unlocks the device state (all contexts). */
71#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
72 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
73
74
75#define DEBUG_HEX 0x3000
76#define DEBUG_CHR 0x3001
77
78/** PM Base Address PCI config space offset */
79#define PMBA 0x40
80/** PM Miscellaneous Power Management PCI config space offset */
81#define PMREGMISC 0x80
82
83#define PM_TMR_FREQ 3579545
84/** Default base for PM PIIX4 device */
85#define PM_PORT_BASE 0x4000
86/* Port offsets in PM device */
87enum
88{
89 PM1a_EVT_OFFSET = 0x00,
90 PM1b_EVT_OFFSET = -1, /**< not supported */
91 PM1a_CTL_OFFSET = 0x04,
92 PM1b_CTL_OFFSET = -1, /**< not supported */
93 PM2_CTL_OFFSET = -1, /**< not supported */
94 PM_TMR_OFFSET = 0x08,
95 GPE0_OFFSET = 0x20,
96 GPE1_OFFSET = -1 /**< not supported */
97};
98
99/* Maximum supported number of custom ACPI tables */
100#define MAX_CUST_TABLES 4
101
102/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
103#define PM_TMR_32BIT
104
105#define BAT_INDEX 0x00004040
106#define BAT_DATA 0x00004044
107#define SYSI_INDEX 0x00004048
108#define SYSI_DATA 0x0000404c
109#define ACPI_RESET_BLK 0x00004050
110
111/* PM1x status register bits */
112#define TMR_STS RT_BIT(0)
113#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
114#define BM_STS RT_BIT(4)
115#define GBL_STS RT_BIT(5)
116#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
117#define PWRBTN_STS RT_BIT(8)
118#define SLPBTN_STS RT_BIT(9)
119#define RTC_STS RT_BIT(10)
120#define IGN_STS RT_BIT(11)
121#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
122#define WAK_STS RT_BIT(15)
123#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
124
125/* PM1x enable register bits */
126#define TMR_EN RT_BIT(0)
127#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
128#define GBL_EN RT_BIT(5)
129#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
130#define PWRBTN_EN RT_BIT(8)
131#define SLPBTN_EN RT_BIT(9)
132#define RTC_EN RT_BIT(10)
133#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
134#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
135#define IGN_EN 0
136
137/* PM1x control register bits */
138#define SCI_EN RT_BIT(0)
139#define BM_RLD RT_BIT(1)
140#define GBL_RLS RT_BIT(2)
141#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
142#define IGN_CNT RT_BIT(9)
143#define SLP_TYPx_SHIFT 10
144#define SLP_TYPx_MASK 7
145#define SLP_EN RT_BIT(13)
146#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
147#define RSR_CNT (RSR1_CNT | RSR2_CNT)
148
149#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
150
151enum
152{
153 BAT_STATUS_STATE = 0x00, /**< BST battery state */
154 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
155 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
156 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
157 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
158 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
159 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
160 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
161 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
162 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
163 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
164 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
165 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
166 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
167 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
168 BAT_INDEX_LAST
169};
170
171enum
172{
173 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
174 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
175};
176
177enum
178{
179 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
180 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
181 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
182 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
183 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
184 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
185 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
186 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
187 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
188 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
189 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
190 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
191 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
192 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
193 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
194 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
195 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
196 SYSTEM_INFO_INDEX_POWER_STATES = 17,
197 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
198 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
199 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
200 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
201 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
202 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
203 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
204 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
205 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
206 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
207 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
208 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
209 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
210 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
211 SYSTEM_INFO_INDEX_IOMMU_ADDRESS = 32, /**< IOMMU PCI address, or 0 */
212 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
213 SYSTEM_INFO_INDEX_END = 34,
214 SYSTEM_INFO_INDEX_INVALID = 0x80,
215 SYSTEM_INFO_INDEX_VALID = 0x200
216};
217
218#define AC_OFFLINE 0
219#define AC_ONLINE 1
220
221#define BAT_TECH_PRIMARY 1
222#define BAT_TECH_SECONDARY 2
223
224#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
225#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
226#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
227#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
228#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
229
230/** SMBus Base Address PCI config space offset */
231#define SMBBA 0x90
232/** SMBus Host Configuration PCI config space offset */
233#define SMBHSTCFG 0xd2
234/** SMBus Slave Command PCI config space offset */
235#define SMBSLVC 0xd3
236/** SMBus Slave Shadow Port 1 PCI config space offset */
237#define SMBSHDW1 0xd4
238/** SMBus Slave Shadow Port 2 PCI config space offset */
239#define SMBSHDW2 0xd5
240/** SMBus Revision Identification PCI config space offset */
241#define SMBREV 0xd6
242
243#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
244#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
245#define SMBHSTCFG_INTRSEL_SMI 0
246#define SMBHSTCFG_INTRSEL_IRQ9 4
247#define SMBHSTCFG_INTRSEL_SHIFT 1
248
249/** Default base for SMBus PIIX4 device */
250#define SMB_PORT_BASE 0x4100
251
252/** SMBus Host Status Register I/O offset */
253#define SMBHSTSTS_OFF 0x0000
254/** SMBus Slave Status Register I/O offset */
255#define SMBSLVSTS_OFF 0x0001
256/** SMBus Host Count Register I/O offset */
257#define SMBHSTCNT_OFF 0x0002
258/** SMBus Host Command Register I/O offset */
259#define SMBHSTCMD_OFF 0x0003
260/** SMBus Host Address Register I/O offset */
261#define SMBHSTADD_OFF 0x0004
262/** SMBus Host Data 0 Register I/O offset */
263#define SMBHSTDAT0_OFF 0x0005
264/** SMBus Host Data 1 Register I/O offset */
265#define SMBHSTDAT1_OFF 0x0006
266/** SMBus Block Data Register I/O offset */
267#define SMBBLKDAT_OFF 0x0007
268/** SMBus Slave Control Register I/O offset */
269#define SMBSLVCNT_OFF 0x0008
270/** SMBus Shadow Command Register I/O offset */
271#define SMBSHDWCMD_OFF 0x0009
272/** SMBus Slave Event Register I/O offset */
273#define SMBSLVEVT_OFF 0x000a
274/** SMBus Slave Data Register I/O offset */
275#define SMBSLVDAT_OFF 0x000c
276
277#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
278#define SMBHSTSTS_INTER RT_BIT(1)
279#define SMBHSTSTS_DEV_ERR RT_BIT(2)
280#define SMBHSTSTS_BUS_ERR RT_BIT(3)
281#define SMBHSTSTS_FAILED RT_BIT(4)
282#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
283
284#define SMBSLVSTS_WRITE_MASK 0x3c
285
286#define SMBHSTCNT_INTEREN RT_BIT(0)
287#define SMBHSTCNT_KILL RT_BIT(1)
288#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
289#define SMBHSTCNT_START RT_BIT(6)
290#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
291
292#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
293
294
295/*********************************************************************************************************************************
296* Structures and Typedefs *
297*********************************************************************************************************************************/
298/**
299 * The TPM mode configured.
300 */
301typedef enum ACPITPMMODE
302{
303 ACPITPMMODE_INVALID = 0,
304 ACPITPMMODE_DISABLED,
305 ACPITPMMODE_TIS_1_2,
306 ACPITPMMODE_CRB_2_0,
307 ACPITPMMODE_FIFO_2_0,
308 ACPITPMMODE_32BIT_HACK = 0x7fffffff
309} ACPITPMMODE;
310
311
312/**
313 * The shared ACPI device state.
314 */
315typedef struct ACPISTATE
316{
317 /** Critical section protecting the ACPI state. */
318 PDMCRITSECT CritSect;
319
320 uint16_t pm1a_en;
321 uint16_t pm1a_sts;
322 uint16_t pm1a_ctl;
323 /** Number of logical CPUs in guest */
324 uint16_t cCpus;
325
326 uint64_t u64PmTimerInitial;
327 /** The PM timer. */
328 TMTIMERHANDLE hPmTimer;
329 /* PM Timer last calculated value */
330 uint32_t uPmTimerVal;
331 uint32_t Alignment0;
332
333 uint32_t gpe0_en;
334 uint32_t gpe0_sts;
335
336 uint32_t uBatteryIndex;
337 uint32_t au8BatteryInfo[13];
338
339 uint32_t uSystemInfoIndex;
340 uint32_t u32Alignment0;
341 uint64_t u64RamSize;
342 /** Offset of the 64-bit prefetchable memory window. */
343 uint64_t u64PciPref64Min;
344 /** Limit of the 64-bit prefetchable memory window. */
345 uint64_t u64PciPref64Max;
346 /** The number of bytes below 4GB. */
347 uint32_t cbRamLow;
348
349 /** Current ACPI S* state. We support S0 and S5. */
350 uint32_t uSleepState;
351 uint8_t au8RSDPPage[0x1000];
352 /** This is a workaround for incorrect index field handling by Intels ACPICA.
353 * The system info _INI method writes to offset 0x200. We either observe a
354 * write request to index 0x80 (in that case we don't change the index) or a
355 * write request to offset 0x200 (in that case we divide the index value by
356 * 4. Note that the _STA method is sometimes called prior to the _INI method
357 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
358 * acpiR3BatIndexWrite() for handling this. */
359 uint8_t u8IndexShift;
360 /** provide an I/O-APIC */
361 uint8_t u8UseIOApic;
362 /** provide a floppy controller */
363 bool fUseFdc;
364 /** If High Precision Event Timer device should be supported */
365 bool fUseHpet;
366 /** If System Management Controller device should be supported */
367 bool fUseSmc;
368 /** the guest handled the last power button event */
369 bool fPowerButtonHandled;
370 /** If ACPI CPU device should be shown */
371 bool fShowCpu;
372 /** If Real Time Clock ACPI object to be shown */
373 bool fShowRtc;
374 /** I/O port address of PM device. */
375 RTIOPORT uPmIoPortBase;
376 /** I/O port address of SMBus device. */
377 RTIOPORT uSMBusIoPortBase;
378 /** Which CPU to check for the locked status. */
379 uint32_t idCpuLockCheck;
380 /** Array of flags of attached CPUs */
381 VMCPUSET CpuSetAttached;
382 /** Mask of locked CPUs (used by the guest). */
383 VMCPUSET CpuSetLocked;
384 /** The CPU event type. */
385 uint32_t u32CpuEventType;
386 /** The CPU id affected. */
387 uint32_t u32CpuEvent;
388 /** Flag whether CPU hot plugging is enabled. */
389 bool fCpuHotPlug;
390 /** If MCFG ACPI table shown to the guest */
391 bool fUseMcfg;
392 /** if the 64-bit prefetchable memory window is shown to the guest */
393 bool fPciPref64Enabled;
394 /** If the IOMMU (AMD) device should be enabled */
395 bool fUseIommuAmd;
396 /** If the IOMMU (Intel) device should be enabled */
397 bool fUseIommuIntel;
398 /** Padding. */
399 bool afPadding0[3];
400 /** Primary NIC PCI address. */
401 uint32_t u32NicPciAddress;
402 /** HD Audio PCI address. */
403 uint32_t u32AudioPciAddress;
404 /** Primary NVMe controller PCI address. */
405 uint32_t u32NvmePciAddress;
406 /** Flag whether S1 power state is enabled. */
407 bool fS1Enabled;
408 /** Flag whether S4 power state is enabled. */
409 bool fS4Enabled;
410 /** Flag whether S1 triggers a state save. */
411 bool fSuspendToSavedState;
412 /** Flag whether to set WAK_STS on resume (restore included). */
413 bool fSetWakeupOnResume;
414 /** PCI address of the IO controller device. */
415 uint32_t u32IocPciAddress;
416 /** PCI address of the host bus controller device. */
417 uint32_t u32HbcPciAddress;
418 /** PCI address of the IOMMU device. */
419 uint32_t u32IommuPciAddress;
420 /** PCI address of the southbridge I/O APIC device. */
421 uint32_t u32SbIoApicPciAddress;
422
423 /** Physical address of PCI config space MMIO region */
424 uint64_t u64PciConfigMMioAddress;
425 /** Length of PCI config space MMIO region */
426 uint64_t u64PciConfigMMioLength;
427 /** Serial 0 IRQ number */
428 uint8_t uSerial0Irq;
429 /** Serial 1 IRQ number */
430 uint8_t uSerial1Irq;
431 /** Serial 2 IRQ number */
432 uint8_t uSerial2Irq;
433 /** Serial 3 IRQ number */
434 uint8_t uSerial3Irq;
435 /** Serial 0 IO port base */
436 RTIOPORT uSerial0IoPortBase;
437 /** Serial 1 IO port base */
438 RTIOPORT uSerial1IoPortBase;
439 /** Serial 2 IO port base */
440 RTIOPORT uSerial2IoPortBase;
441 /** Serial 3 IO port base */
442 RTIOPORT uSerial3IoPortBase;
443
444 /** @name Parallel port config bits
445 * @{ */
446 /** Parallel 0 IO port base */
447 RTIOPORT uParallel0IoPortBase;
448 /** Parallel 1 IO port base */
449 RTIOPORT uParallel1IoPortBase;
450 /** Parallel 0 IRQ number */
451 uint8_t uParallel0Irq;
452 /** Parallel 1 IRQ number */
453 uint8_t uParallel1Irq;
454 /** @} */
455
456#ifdef VBOX_WITH_TPM
457 /** @name TPM config bits
458 * @{ */
459 /** The ACPI TPM mode configured. */
460 ACPITPMMODE enmTpmMode;
461 /** The MMIO register area base address. */
462 RTGCPHYS GCPhysTpmMmio;
463 /** @} */
464#endif
465
466 /** Number of custom ACPI tables */
467 uint8_t cCustTbls;
468 /** ACPI OEM ID */
469 uint8_t au8OemId[6];
470 /** ACPI Crator ID */
471 uint8_t au8CreatorId[4];
472 uint8_t abAlignment2[3];
473 /** ACPI Crator Rev */
474 uint32_t u32CreatorRev;
475 /** ACPI custom OEM Tab ID */
476 uint8_t au8OemTabId[8];
477 /** ACPI custom OEM Rev */
478 uint32_t u32OemRevision;
479
480 /** SMBus Host Status Register */
481 uint8_t u8SMBusHstSts;
482 /** SMBus Slave Status Register */
483 uint8_t u8SMBusSlvSts;
484 /** SMBus Host Control Register */
485 uint8_t u8SMBusHstCnt;
486 /** SMBus Host Command Register */
487 uint8_t u8SMBusHstCmd;
488 /** SMBus Host Address Register */
489 uint8_t u8SMBusHstAdd;
490 /** SMBus Host Data 0 Register */
491 uint8_t u8SMBusHstDat0;
492 /** SMBus Host Data 1 Register */
493 uint8_t u8SMBusHstDat1;
494 /** SMBus Slave Control Register */
495 uint8_t u8SMBusSlvCnt;
496 /** SMBus Slave Event Register */
497 uint16_t u16SMBusSlvEvt;
498 /** SMBus Slave Data Register */
499 uint16_t u16SMBusSlvDat;
500 /** SMBus Shadow Command Register */
501 uint8_t u8SMBusShdwCmd;
502 /** SMBus Host Block Index */
503 uint8_t u8SMBusBlkIdx;
504 uint8_t abAlignment3[2];
505 /** SMBus Host Block Data Buffer */
506 uint8_t au8SMBusBlkDat[32];
507
508 /** @todo DEBUGGING */
509 uint32_t uPmTimeOld;
510 uint32_t uPmTimeA;
511 uint32_t uPmTimeB;
512 uint32_t Alignment5;
513
514 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
515 * @{ */
516 IOMIOPORTHANDLE hIoPortPm1aEn;
517 IOMIOPORTHANDLE hIoPortPm1aSts;
518 IOMIOPORTHANDLE hIoPortPm1aCtl;
519 IOMIOPORTHANDLE hIoPortPmTimer;
520 IOMIOPORTHANDLE hIoPortGpe0En;
521 IOMIOPORTHANDLE hIoPortGpe0Sts;
522 /** @} */
523
524 /** SMBus I/O ports (mapped/unmapped). */
525 IOMIOPORTHANDLE hIoPortSMBus;
526
527 /** @name Fixed I/O ports
528 * @{ */
529 /** ACPI SMI I/O port. */
530 IOMIOPORTHANDLE hIoPortSmi;
531 /** ACPI Debug hex I/O port. */
532 IOMIOPORTHANDLE hIoPortDebugHex;
533 /** ACPI Debug char I/O port. */
534 IOMIOPORTHANDLE hIoPortDebugChar;
535 /** ACPI Battery status index I/O port. */
536 IOMIOPORTHANDLE hIoPortBatteryIndex;
537 /** ACPI Battery status data I/O port. */
538 IOMIOPORTHANDLE hIoPortBatteryData;
539 /** ACPI system info index I/O port. */
540 IOMIOPORTHANDLE hIoPortSysInfoIndex;
541 /** ACPI system info data I/O port. */
542 IOMIOPORTHANDLE hIoPortSysInfoData;
543 /** ACPI Reset I/O port. */
544 IOMIOPORTHANDLE hIoPortReset;
545 /** @} */
546
547} ACPISTATE;
548/** Pointer to the shared ACPI device state. */
549typedef ACPISTATE *PACPISTATE;
550
551
552
553/**
554 * The ring-3 ACPI device state.
555 */
556typedef struct ACPISTATER3
557{
558 /** ACPI port base interface. */
559 PDMIBASE IBase;
560 /** ACPI port interface. */
561 PDMIACPIPORT IACPIPort;
562 /** Pointer to the device instance so we can get our bearings from
563 * interface functions. */
564 PPDMDEVINSR3 pDevIns;
565
566 /** Pointer to the driver base interface. */
567 R3PTRTYPE(PPDMIBASE) pDrvBase;
568 /** Pointer to the driver connector interface. */
569 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
570
571 /** Custom ACPI tables binary data. */
572 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
573 /** The size of the custom table binary. */
574 uint64_t acbCustBin[MAX_CUST_TABLES];
575} ACPISTATER3;
576/** Pointer to the ring-3 ACPI device state. */
577typedef ACPISTATER3 *PACPISTATER3;
578
579
580#pragma pack(1)
581
582/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
583struct ACPIGENADDR
584{
585 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
586 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
587 uint8_t u8RegisterBitOffset; /**< bit offset of register */
588 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
589 uint64_t u64Address; /**< 64-bit address of register */
590};
591AssertCompileSize(ACPIGENADDR, 12);
592
593/** Root System Description Pointer */
594struct ACPITBLRSDP
595{
596 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
597 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
598 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
599 uint8_t u8Revision; /**< revision number, currently 2 */
600#define ACPI_REVISION 2 /**< ACPI 3.0 */
601 uint32_t u32RSDT; /**< phys addr of RSDT */
602 uint32_t u32Length; /**< bytes of this table */
603 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
604 uint8_t u8ExtChecksum; /**< checksum of entire table */
605 uint8_t u8Reserved[3]; /**< reserved */
606};
607AssertCompileSize(ACPITBLRSDP, 36);
608
609/** System Description Table Header */
610struct ACPITBLHEADER
611{
612 uint8_t au8Signature[4]; /**< table identifier */
613 uint32_t u32Length; /**< length of the table including header */
614 uint8_t u8Revision; /**< revision number */
615 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
616 uint8_t au8OemId[6]; /**< OEM-supplied string */
617 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
618 uint32_t u32OemRevision; /**< OEM-supplied revision number */
619 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
620 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
621};
622AssertCompileSize(ACPITBLHEADER, 36);
623
624/** Root System Description Table */
625struct ACPITBLRSDT
626{
627 ACPITBLHEADER header;
628 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
629};
630AssertCompileSize(ACPITBLRSDT, 40);
631
632/** Extended System Description Table */
633struct ACPITBLXSDT
634{
635 ACPITBLHEADER header;
636 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
637};
638AssertCompileSize(ACPITBLXSDT, 44);
639
640/** Fixed ACPI Description Table */
641struct ACPITBLFADT
642{
643 ACPITBLHEADER header;
644 uint32_t u32FACS; /**< phys. address of FACS */
645 uint32_t u32DSDT; /**< phys. address of DSDT */
646 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
647#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
648#define INT_MODEL_MULTIPLE_APIC 2
649 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
650 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
651#define SCI_INT 9
652 uint32_t u32SMICmd; /**< system port address of SMI command port */
653#define SMI_CMD 0x0000442e
654 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
655#define ACPI_ENABLE 0xa1
656 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
657#define ACPI_DISABLE 0xa0
658 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
659 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
660 state control responsibility */
661 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
662 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
663 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
664 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
665 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
666 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
667 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
668 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
669 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
670 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
671 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
672 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
673 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
674#define GPE0_BLK_LEN 2
675 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
676#define GPE1_BLK_LEN 0
677 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
678#define GPE1_BASE 0
679 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
680 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
681#define P_LVL2_LAT 101 /**< C2 state not supported */
682 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
683#define P_LVL3_LAT 1001 /**< C3 state not supported */
684 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
685 lines from any processors memory caches */
686#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
687 uint16_t u16FlushStride; /**< cache line width */
688#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
689 uint8_t u8DutyOffset;
690 uint8_t u8DutyWidth;
691 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
692 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
693 uint8_t u8Century; /**< RTC CMOS RAM index of century */
694 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
695#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
696 (COM too?) */
697#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
698#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
699#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
700#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
701 uint8_t u8Must0_0; /**< must be 0 */
702 uint32_t u32Flags; /**< fixed feature flags */
703#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
704#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
705#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
706#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
707#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
708#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
709#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
710#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
711#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
712#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
713#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
714#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
715#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
716#define FADT_FL_CPU_SW_SLP RT_BIT(13)
717#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
718#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
719#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
720#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
721#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
722#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
723
724/* PM Timer mask and msb */
725#ifndef PM_TMR_32BIT
726#define TMR_VAL_MSB 0x800000
727#define TMR_VAL_MASK 0xffffff
728#undef FADT_FL_TMR_VAL_EXT
729#define FADT_FL_TMR_VAL_EXT 0
730#else
731#define TMR_VAL_MSB 0x80000000
732#define TMR_VAL_MASK 0xffffffff
733#endif
734
735 /** Start of the ACPI 2.0 extension. */
736 ACPIGENADDR ResetReg; /**< ext addr of reset register */
737 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
738#define ACPI_RESET_REG_VAL 0x10
739 uint8_t au8Must0_1[3]; /**< must be 0 */
740 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
741 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
742 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
743 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
744 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
745 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
746 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
747 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
748 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
749 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
750};
751AssertCompileSize(ACPITBLFADT, 244);
752#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
753
754/** Firmware ACPI Control Structure */
755struct ACPITBLFACS
756{
757 uint8_t au8Signature[4]; /**< 'FACS' */
758 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
759 uint32_t u32HWSignature; /**< systems HW signature at last boot */
760 uint32_t u32FWVector; /**< address of waking vector */
761 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
762 uint32_t u32Flags; /**< FACS flags */
763 uint64_t u64X_FWVector; /**< 64-bit waking vector */
764 uint8_t u8Version; /**< version of this table */
765 uint8_t au8Reserved[31]; /**< zero */
766};
767AssertCompileSize(ACPITBLFACS, 64);
768
769/** Processor Local APIC Structure */
770struct ACPITBLLAPIC
771{
772 uint8_t u8Type; /**< 0 = LAPIC */
773 uint8_t u8Length; /**< 8 */
774 uint8_t u8ProcId; /**< processor ID */
775 uint8_t u8ApicId; /**< local APIC ID */
776 uint32_t u32Flags; /**< Flags */
777#define LAPIC_ENABLED 0x1
778};
779AssertCompileSize(ACPITBLLAPIC, 8);
780
781/** I/O APIC Structure */
782struct ACPITBLIOAPIC
783{
784 uint8_t u8Type; /**< 1 == I/O APIC */
785 uint8_t u8Length; /**< 12 */
786 uint8_t u8IOApicId; /**< I/O APIC ID */
787 uint8_t u8Reserved; /**< 0 */
788 uint32_t u32Address; /**< phys address to access I/O APIC */
789 uint32_t u32GSIB; /**< global system interrupt number to start */
790};
791AssertCompileSize(ACPITBLIOAPIC, 12);
792
793/** Interrupt Source Override Structure */
794struct ACPITBLISO
795{
796 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
797 uint8_t u8Length; /**< 10 */
798 uint8_t u8Bus; /**< Bus */
799 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
800 uint32_t u32GSI; /**< Global System Interrupt */
801 uint16_t u16Flags; /**< MPS INTI flags Global */
802};
803AssertCompileSize(ACPITBLISO, 10);
804#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
805
806/** HPET Descriptor Structure */
807struct ACPITBLHPET
808{
809 ACPITBLHEADER aHeader;
810 uint32_t u32Id; /**< hardware ID of event timer block
811 [31:16] PCI vendor ID of first timer block
812 [15] legacy replacement IRQ routing capable
813 [14] reserved
814 [13] COUNT_SIZE_CAP counter size
815 [12:8] number of comparators in first timer block
816 [7:0] hardware rev ID */
817 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
818 uint8_t u32Number; /**< sequence number starting at 0 */
819 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
820 lost interrupts while the counter is programmed
821 to operate in periodic mode. Unit: clock tick. */
822 uint8_t u8Attributes; /**< page protection and OEM attribute. */
823};
824AssertCompileSize(ACPITBLHPET, 56);
825
826#ifdef VBOX_WITH_IOMMU_AMD
827/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
828 * In accordance with the AMD spec. */
829typedef struct ACPIIVRS
830{
831 ACPITBLHEADER header;
832 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
833 uint64_t u64Rsvd; /**< Reserved (MBZ). */
834 /* IVHD type block follows. */
835} ACPIIVRS;
836AssertCompileSize(ACPIIVRS, 48);
837AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
838
839/**
840 * AMD IOMMU: The ACPI table.
841 */
842typedef struct ACPITBLIOMMU
843{
844 ACPIIVRS Hdr;
845 ACPIIVHDTYPE10 IvhdType10;
846 ACPIIVHDDEVENTRY4 IvhdType10Start;
847 ACPIIVHDDEVENTRY4 IvhdType10End;
848 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
849 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
850 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
851 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
852
853 ACPIIVHDTYPE11 IvhdType11;
854 ACPIIVHDDEVENTRY4 IvhdType11Start;
855 ACPIIVHDDEVENTRY4 IvhdType11End;
856 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
857 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
858 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
859 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
860} ACPITBLIOMMU;
861AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
862AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
863AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
864AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
865#endif /* VBOX_WITH_IOMMU_AMD */
866
867#ifdef VBOX_WITH_IOMMU_INTEL
868/** Intel IOMMU: DMAR (DMA Remapping) Reporting Structure.
869 * In accordance with the AMD spec. */
870typedef struct ACPIDMAR
871{
872 ACPITBLHEADER Hdr;
873 /** Host-address Width (N+1 physical bits addressable). */
874 uint8_t uHostAddrWidth;
875 /** Flags, see ACPI_DMAR_F_XXX. */
876 uint8_t fFlags;
877 /** Reserved. */
878 uint8_t abRsvd[10];
879 /* Remapping Structures[] follows. */
880} ACPIDMAR;
881AssertCompileSize(ACPIDMAR, 48);
882AssertCompileMemberOffset(ACPIDMAR, uHostAddrWidth, 36);
883AssertCompileMemberOffset(ACPIDMAR, fFlags, 37);
884
885/**
886 * Intel VT-d: The ACPI table.
887 */
888typedef struct ACPITBLVTD
889{
890 ACPIDMAR Dmar;
891 ACPIDRHD Drhd;
892 ACPIDMARDEVSCOPE DevScopeIoApic;
893} ACPITBLVTD;
894#endif /* VBOX_WITH_IOMMU_INTEL */
895
896/** MCFG Descriptor Structure */
897typedef struct ACPITBLMCFG
898{
899 ACPITBLHEADER aHeader;
900 uint64_t u64Reserved;
901} ACPITBLMCFG;
902AssertCompileSize(ACPITBLMCFG, 44);
903
904/** Number of such entries can be computed from the whole table length in header */
905typedef struct ACPITBLMCFGENTRY
906{
907 uint64_t u64BaseAddress;
908 uint16_t u16PciSegmentGroup;
909 uint8_t u8StartBus;
910 uint8_t u8EndBus;
911 uint32_t u32Reserved;
912} ACPITBLMCFGENTRY;
913AssertCompileSize(ACPITBLMCFGENTRY, 16);
914
915#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
916
917/** Custom Description Table */
918struct ACPITBLCUST
919{
920 ACPITBLHEADER header;
921 uint8_t au8Data[476];
922};
923AssertCompileSize(ACPITBLCUST, 512);
924
925
926#ifdef VBOX_WITH_TPM
927/**
928 * TPM: The ACPI table for a TPM 2.0 device
929 * (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpec_v1p3_r8_pub.pdf).
930 */
931typedef struct ACPITBLTPM20
932{
933 /** The common ACPI table header. */
934 ACPITBLHEADER Hdr;
935 /** The platform class. */
936 uint16_t u16PlatCls;
937 /** Reserved. */
938 uint16_t u16Rsvd0;
939 /** Address of the CRB control area or FIFO base address. */
940 uint64_t u64BaseAddrCrbOrFifo;
941 /** The start method selector. */
942 uint32_t u32StartMethod;
943 /** Following are start method specific parameters and optional LAML and LASA fields we don't implement right now. */
944 /** @todo */
945} ACPITBLTPM20;
946AssertCompileSize(ACPITBLTPM20, 52);
947
948/** Revision of the TPM2.0 ACPI table. */
949#define ACPI_TPM20_REVISION 4
950/** The default MMIO base address of the TPM. */
951#define ACPI_TPM_MMIO_BASE_DEFAULT 0xfed40000
952
953
954/** @name Possible values for the ACPITBLTPM20::u16PlatCls member.
955 * @{ */
956/** Client platform. */
957#define ACPITBL_TPM20_PLAT_CLS_CLIENT UINT16_C(0)
958/** Server platform. */
959#define ACPITBL_TPM20_PLAT_CLS_SERVER UINT16_C(1)
960/** @} */
961
962
963/** @name Possible values for the ACPITBLTPM20::u32StartMethod member.
964 * @{ */
965/** MMIO interface (TIS1.2+Cancel). */
966#define ACPITBL_TPM20_START_METHOD_TIS12 UINT16_C(6)
967/** CRB interface. */
968#define ACPITBL_TPM20_START_METHOD_CRB UINT16_C(7)
969/** @} */
970#endif
971
972
973#pragma pack()
974
975
976#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
977
978
979/*********************************************************************************************************************************
980* Internal Functions *
981*********************************************************************************************************************************/
982#ifdef IN_RING3
983static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
984#endif
985
986/* SCI, usually IRQ9 */
987DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
988{
989 PDMDevHlpPCISetIrq(pDevIns, 0, level);
990}
991
992DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
993{
994 return (pThis->pm1a_ctl & SCI_EN)
995 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
996}
997
998DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
999{
1000 return !!(pThis->gpe0_en & pThis->gpe0_sts);
1001}
1002
1003DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
1004{
1005 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1006 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
1007 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
1008 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
1009 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
1010}
1011
1012DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
1013{
1014 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
1015}
1016
1017/**
1018 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
1019 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
1020 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
1021 * registers and trigger IRQs.
1022 *
1023 * Caller must hold the state lock.
1024 *
1025 * @param pDevIns The PDM device instance.
1026 * @param pThis The ACPI shared instance data.
1027 * @param sts The new PM1a.STS value.
1028 * @param en The new PM1a.EN value.
1029 */
1030static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1031{
1032 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1033
1034 const bool old_level = acpiSCILevel(pDevIns, pThis);
1035 pThis->pm1a_en = en;
1036 pThis->pm1a_sts = sts;
1037 const bool new_level = acpiSCILevel(pDevIns, pThis);
1038
1039 LogFunc(("old=%x new=%x\n", old_level, new_level));
1040
1041 if (new_level != old_level)
1042 acpiSetIrq(pDevIns, new_level);
1043}
1044
1045#ifdef IN_RING3
1046
1047/**
1048 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
1049 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
1050 *
1051 * Caller must hold the state lock.
1052 *
1053 * @param pDevIns The PDM device instance.
1054 * @param pThis The ACPI shared instance data.
1055 * @param sts The new GPE0.STS value.
1056 * @param en The new GPE0.EN value.
1057 */
1058static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1059{
1060 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1061
1062 const bool old_level = acpiSCILevel(pDevIns, pThis);
1063 pThis->gpe0_en = en;
1064 pThis->gpe0_sts = sts;
1065 const bool new_level = acpiSCILevel(pDevIns, pThis);
1066
1067 LogFunc(("old=%x new=%x\n", old_level, new_level));
1068
1069 if (new_level != old_level)
1070 acpiSetIrq(pDevIns, new_level);
1071}
1072
1073/**
1074 * Used by acpiR3PM1aCtlWrite to power off the VM.
1075 *
1076 * @param pDevIns The device instance.
1077 * @returns Strict VBox status code.
1078 */
1079static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
1080{
1081 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
1082 AssertRC(VBOXSTRICTRC_VAL(rc));
1083 return rc;
1084}
1085
1086/**
1087 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
1088 *
1089 * @param pDevIns The device instance.
1090 * @param pThis The ACPI shared instance data.
1091 * @returns Strict VBox status code.
1092 */
1093static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
1094{
1095 /* We must set WAK_STS on resume (includes restore) so the guest knows that
1096 we've woken up and can continue executing code. The guest is probably
1097 reading the PMSTS register in a loop to check this. */
1098 VBOXSTRICTRC rc;
1099 pThis->fSetWakeupOnResume = true;
1100 if (pThis->fSuspendToSavedState)
1101 {
1102 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
1103 if (rc != VERR_NOT_SUPPORTED)
1104 AssertRC(VBOXSTRICTRC_VAL(rc));
1105 else
1106 {
1107 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
1108 rc = PDMDevHlpVMSuspend(pDevIns);
1109 AssertRC(VBOXSTRICTRC_VAL(rc));
1110 }
1111 }
1112 else
1113 {
1114 rc = PDMDevHlpVMSuspend(pDevIns);
1115 AssertRC(VBOXSTRICTRC_VAL(rc));
1116 }
1117 return rc;
1118}
1119
1120
1121/**
1122 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
1123 */
1124static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
1125{
1126 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1127 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1128 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1129 DEVACPI_LOCK_R3(pDevIns, pThis);
1130
1131 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1132 pThis->fPowerButtonHandled = false;
1133 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1134
1135 DEVACPI_UNLOCK(pDevIns, pThis);
1136 return VINF_SUCCESS;
1137}
1138
1139/**
1140 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
1141 */
1142static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1143{
1144 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1145 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1146 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1147 DEVACPI_LOCK_R3(pDevIns, pThis);
1148
1149 *pfHandled = pThis->fPowerButtonHandled;
1150
1151 DEVACPI_UNLOCK(pDevIns, pThis);
1152 return VINF_SUCCESS;
1153}
1154
1155/**
1156 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1157 * Guest entered into G0 (working) or G1 (sleeping)}
1158 */
1159static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1160{
1161 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1162 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1163 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1164 DEVACPI_LOCK_R3(pDevIns, pThis);
1165
1166 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1167
1168 DEVACPI_UNLOCK(pDevIns, pThis);
1169 return VINF_SUCCESS;
1170}
1171
1172/**
1173 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1174 */
1175static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1176{
1177 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1178 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1179 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1180 DEVACPI_LOCK_R3(pDevIns, pThis);
1181
1182 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1183
1184 DEVACPI_UNLOCK(pDevIns, pThis);
1185 return VINF_SUCCESS;
1186}
1187
1188/**
1189 * Send an ACPI sleep button event.
1190 *
1191 * @returns VBox status code
1192 * @param pInterface Pointer to the interface structure containing the called function pointer.
1193 */
1194static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1195{
1196 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1197 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1198 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1199 DEVACPI_LOCK_R3(pDevIns, pThis);
1200
1201 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1202
1203 DEVACPI_UNLOCK(pDevIns, pThis);
1204 return VINF_SUCCESS;
1205}
1206
1207/**
1208 * Send an ACPI monitor hot-plug event.
1209 *
1210 * @returns VBox status code
1211 * @param pInterface Pointer to the interface structure containing the
1212 * called function pointer.
1213 */
1214static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1215{
1216 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1217 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1218 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1219 DEVACPI_LOCK_R3(pDevIns, pThis);
1220
1221 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1222
1223 DEVACPI_UNLOCK(pDevIns, pThis);
1224 return VINF_SUCCESS;
1225}
1226
1227/**
1228 * Send an ACPI battery status change event.
1229 *
1230 * @returns VBox status code
1231 * @param pInterface Pointer to the interface structure containing the
1232 * called function pointer.
1233 */
1234static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1235{
1236 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1237 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1238 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1239 DEVACPI_LOCK_R3(pDevIns, pThis);
1240
1241 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1242
1243 DEVACPI_UNLOCK(pDevIns, pThis);
1244 return VINF_SUCCESS;
1245}
1246
1247/**
1248 * Used by acpiR3PmTimer to re-arm the PM timer.
1249 *
1250 * The caller is expected to either hold the clock lock or to have made sure
1251 * the VM is resetting or loading state.
1252 *
1253 * @param pDevIns The device instance.
1254 * @param pThis The ACPI shared instance data.
1255 * @param uNow The current time.
1256 */
1257static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1258{
1259 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1260 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1261 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1262 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1263 Log(("acpi: uInterval = %RU64\n", uInterval));
1264}
1265
1266#endif /* IN_RING3 */
1267
1268/**
1269 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1270 *
1271 * The caller is expected to either hold the clock lock or to have made sure
1272 * the VM is resetting or loading state.
1273 *
1274 * @param pDevIns The PDM device instance.
1275 * @param pThis The ACPI instance
1276 * @param u64Now The current time
1277 */
1278static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1279{
1280 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1281 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1282 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1283
1284 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1285 & TMR_VAL_MASK;
1286
1287 if ((pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1288 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1289}
1290
1291#ifdef IN_RING3
1292
1293/**
1294 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1295 */
1296static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1297{
1298 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1299 Assert(pThis->hPmTimer == hTimer);
1300 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
1301 RT_NOREF(pvUser);
1302
1303 DEVACPI_LOCK_R3(pDevIns, pThis);
1304 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1305 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1306 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1307 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, hTimer);
1308 acpiPmTimerUpdate(pDevIns, pThis, tsNow);
1309 DEVACPI_UNLOCK(pDevIns, pThis);
1310
1311 acpiR3PmTimerReset(pDevIns, pThis, tsNow);
1312}
1313
1314/**
1315 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1316 * acpiR3LoadState.
1317 *
1318 * @returns VINF_SUCCESS.
1319 * @param pThis The ACPI shared instance data.
1320 * @param pThisCC The ACPI instance data for ring-3.
1321 */
1322static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1323{
1324 uint32_t *p = pThis->au8BatteryInfo;
1325 bool fPresent; /* battery present? */
1326 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1327 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1328 uint32_t hostPresentRate; /* 0..1000 */
1329 int rc;
1330
1331 if (!pThisCC->pDrv)
1332 return VINF_SUCCESS;
1333 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1334 &hostBatteryState, &hostPresentRate);
1335 AssertRC(rc);
1336
1337 /* default values */
1338 p[BAT_STATUS_STATE] = hostBatteryState;
1339 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1340 : hostPresentRate * 50; /* mW */
1341 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1342 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1343
1344 /* did we get a valid battery state? */
1345 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1346 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1347 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1348 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1349
1350 return VINF_SUCCESS;
1351}
1352
1353/**
1354 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1355 * acpiR3LoadState.
1356 *
1357 * @returns VINF_SUCCESS.
1358 * @param pThis The ACPI shared instance data.
1359 */
1360static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1361{
1362 uint32_t *p = pThis->au8BatteryInfo;
1363
1364 p[BAT_INFO_UNITS] = 0; /* mWh */
1365 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1366 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1367 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1368 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1369 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1370 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1371 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1372 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1373
1374 return VINF_SUCCESS;
1375}
1376
1377/**
1378 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1379 *
1380 * @returns status mask or 0.
1381 * @param pThisCC The ACPI instance data for ring-3.
1382 */
1383static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1384{
1385 bool fPresent; /* battery present? */
1386 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1387 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1388 uint32_t hostPresentRate; /* 0..1000 */
1389 int rc;
1390
1391 if (!pThisCC->pDrv)
1392 return 0;
1393 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1394 &hostBatteryState, &hostPresentRate);
1395 AssertRC(rc);
1396
1397 return fPresent
1398 ? STA_DEVICE_PRESENT_MASK /* present */
1399 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1400 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1401 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1402 | STA_BATTERY_PRESENT_MASK /* battery is present */
1403 : 0; /* device not present */
1404}
1405
1406/**
1407 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1408 *
1409 * @returns status.
1410 * @param pThisCC The ACPI instance data for ring-3.
1411 */
1412static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1413{
1414 /* query the current power source from the host driver */
1415 if (!pThisCC->pDrv)
1416 return AC_ONLINE;
1417
1418 PDMACPIPOWERSOURCE ps;
1419 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1420 AssertRC(rc);
1421 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1422}
1423
1424/**
1425 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1426 */
1427static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1428{
1429 RT_NOREF(pvUser, offPort);
1430 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1431 if (cb != 4)
1432 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1433
1434 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1435 DEVACPI_LOCK_R3(pDevIns, pThis);
1436
1437 u32 >>= pThis->u8IndexShift;
1438 /* see comment at the declaration of u8IndexShift */
1439 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1440 {
1441 pThis->u8IndexShift = 2;
1442 u32 >>= 2;
1443 }
1444 Assert(u32 < BAT_INDEX_LAST);
1445 pThis->uBatteryIndex = u32;
1446
1447 DEVACPI_UNLOCK(pDevIns, pThis);
1448 return VINF_SUCCESS;
1449}
1450
1451/**
1452 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1453 */
1454static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1455{
1456 RT_NOREF(pvUser, offPort);
1457 if (cb != 4)
1458 return VERR_IOM_IOPORT_UNUSED;
1459
1460 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1461 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1462 DEVACPI_LOCK_R3(pDevIns, pThis);
1463
1464 VBOXSTRICTRC rc = VINF_SUCCESS;
1465 switch (pThis->uBatteryIndex)
1466 {
1467 case BAT_STATUS_STATE:
1468 acpiR3FetchBatteryStatus(pThis, pThisCC);
1469 RT_FALL_THRU();
1470 case BAT_STATUS_PRESENT_RATE:
1471 case BAT_STATUS_REMAINING_CAPACITY:
1472 case BAT_STATUS_PRESENT_VOLTAGE:
1473 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1474 break;
1475
1476 case BAT_INFO_UNITS:
1477 acpiR3FetchBatteryInfo(pThis);
1478 RT_FALL_THRU();
1479 case BAT_INFO_DESIGN_CAPACITY:
1480 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1481 case BAT_INFO_TECHNOLOGY:
1482 case BAT_INFO_DESIGN_VOLTAGE:
1483 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1484 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1485 case BAT_INFO_CAPACITY_GRANULARITY_1:
1486 case BAT_INFO_CAPACITY_GRANULARITY_2:
1487 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1488 break;
1489
1490 case BAT_DEVICE_STATUS:
1491 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1492 break;
1493
1494 case BAT_POWER_SOURCE:
1495 *pu32 = acpiR3GetPowerSource(pThisCC);
1496 break;
1497
1498 default:
1499 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1500 *pu32 = UINT32_MAX;
1501 break;
1502 }
1503
1504 DEVACPI_UNLOCK(pDevIns, pThis);
1505 return rc;
1506}
1507
1508/**
1509 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1510 */
1511static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1512{
1513 RT_NOREF(pvUser, offPort);
1514 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1515 if (cb != 4)
1516 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1517
1518 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1519 DEVACPI_LOCK_R3(pDevIns, pThis);
1520
1521 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1522 pThis->uSystemInfoIndex = u32;
1523 else
1524 {
1525 /* see comment at the declaration of u8IndexShift */
1526 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1527 {
1528 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1529 pThis->u8IndexShift = 2;
1530 }
1531
1532 u32 >>= pThis->u8IndexShift;
1533
1534 /* If the index exceeds 31 (which is all we can fit within offset 0x80), we need to divide the index again
1535 for indices > 31 and < SYSTEM_INFO_INDEX_END. */
1536 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 2 && (u32 >> 2) < SYSTEM_INFO_INDEX_END)
1537 u32 >>= 2;
1538
1539 AssertMsg(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1540 pThis->uSystemInfoIndex = u32;
1541 }
1542
1543 DEVACPI_UNLOCK(pDevIns, pThis);
1544 return VINF_SUCCESS;
1545}
1546
1547/**
1548 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1549 */
1550static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1551{
1552 RT_NOREF(pvUser, offPort);
1553 if (cb != 4)
1554 return VERR_IOM_IOPORT_UNUSED;
1555
1556 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1557 DEVACPI_LOCK_R3(pDevIns, pThis);
1558
1559 VBOXSTRICTRC rc = VINF_SUCCESS;
1560 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1561 switch (uSystemInfoIndex)
1562 {
1563 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1564 *pu32 = pThis->cbRamLow;
1565 break;
1566
1567 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1568 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1569 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1570 break;
1571
1572 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1573 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1574 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1575 break;
1576
1577 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1578 *pu32 = pThis->u8UseIOApic;
1579 break;
1580
1581 case SYSTEM_INFO_INDEX_HPET_STATUS:
1582 *pu32 = pThis->fUseHpet
1583 ? ( STA_DEVICE_PRESENT_MASK
1584 | STA_DEVICE_ENABLED_MASK
1585 | STA_DEVICE_SHOW_IN_UI_MASK
1586 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1587 : 0;
1588 break;
1589
1590 case SYSTEM_INFO_INDEX_SMC_STATUS:
1591 *pu32 = pThis->fUseSmc
1592 ? ( STA_DEVICE_PRESENT_MASK
1593 | STA_DEVICE_ENABLED_MASK
1594 /* no need to show this device in the UI */
1595 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1596 : 0;
1597 break;
1598
1599 case SYSTEM_INFO_INDEX_FDC_STATUS:
1600 *pu32 = pThis->fUseFdc
1601 ? ( STA_DEVICE_PRESENT_MASK
1602 | STA_DEVICE_ENABLED_MASK
1603 | STA_DEVICE_SHOW_IN_UI_MASK
1604 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1605 : 0;
1606 break;
1607
1608 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1609 *pu32 = pThis->u32NicPciAddress;
1610 break;
1611
1612 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1613 *pu32 = pThis->u32AudioPciAddress;
1614 break;
1615
1616 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1617 *pu32 = pThis->u32NvmePciAddress;
1618 break;
1619
1620 case SYSTEM_INFO_INDEX_POWER_STATES:
1621 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1622 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1623 *pu32 |= RT_BIT(1);
1624 if (pThis->fS4Enabled)
1625 *pu32 |= RT_BIT(4);
1626 break;
1627
1628 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1629 *pu32 = pThis->u32IocPciAddress;
1630 break;
1631
1632 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1633 *pu32 = pThis->u32HbcPciAddress;
1634 break;
1635
1636 case SYSTEM_INFO_INDEX_PCI_BASE:
1637 /** @todo couldn't MCFG be in 64-bit range? */
1638 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1639 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1640 break;
1641
1642 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1643 /** @todo couldn't MCFG be in 64-bit range? */
1644 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1645 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1646 break;
1647
1648 case SYSTEM_INFO_INDEX_RTC_STATUS:
1649 *pu32 = pThis->fShowRtc
1650 ? ( STA_DEVICE_PRESENT_MASK
1651 | STA_DEVICE_ENABLED_MASK
1652 | STA_DEVICE_SHOW_IN_UI_MASK
1653 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1654 : 0;
1655 break;
1656
1657 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1658 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1659 {
1660 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1661 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1662 }
1663 else
1664 {
1665 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1666 pThis->idCpuLockCheck);
1667 /* Always return locked status just to be safe */
1668 *pu32 = 1;
1669 }
1670 break;
1671
1672 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1673 *pu32 = pThis->u32CpuEventType;
1674 break;
1675
1676 case SYSTEM_INFO_INDEX_CPU_EVENT:
1677 *pu32 = pThis->u32CpuEvent;
1678 break;
1679
1680 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1681 *pu32 = pThis->uSerial0IoPortBase;
1682 break;
1683
1684 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1685 *pu32 = pThis->uSerial0Irq;
1686 break;
1687
1688 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1689 *pu32 = pThis->uSerial1IoPortBase;
1690 break;
1691
1692 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1693 *pu32 = pThis->uSerial1Irq;
1694 break;
1695
1696 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1697 *pu32 = pThis->uSerial2IoPortBase;
1698 break;
1699
1700 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1701 *pu32 = pThis->uSerial2Irq;
1702 break;
1703
1704 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1705 *pu32 = pThis->uSerial3IoPortBase;
1706 break;
1707
1708 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1709 *pu32 = pThis->uSerial3Irq;
1710 break;
1711
1712 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1713 *pu32 = pThis->uParallel0IoPortBase;
1714 break;
1715
1716 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1717 *pu32 = pThis->uParallel0Irq;
1718 break;
1719
1720 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1721 *pu32 = pThis->uParallel1IoPortBase;
1722 break;
1723
1724 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1725 *pu32 = pThis->uParallel1Irq;
1726 break;
1727
1728 case SYSTEM_INFO_INDEX_IOMMU_ADDRESS:
1729 *pu32 = pThis->u32IommuPciAddress;
1730 break;
1731
1732 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
1733 *pu32 = pThis->u32SbIoApicPciAddress;
1734 break;
1735
1736 case SYSTEM_INFO_INDEX_END:
1737 /** @todo why isn't this setting any output value? */
1738 break;
1739
1740 /* Solaris 9 tries to read from this index */
1741 case SYSTEM_INFO_INDEX_INVALID:
1742 *pu32 = 0;
1743 break;
1744
1745 default:
1746 *pu32 = UINT32_MAX;
1747 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1748 break;
1749 }
1750
1751 DEVACPI_UNLOCK(pDevIns, pThis);
1752 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1753 return rc;
1754}
1755
1756/**
1757 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1758 */
1759static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1760{
1761 RT_NOREF(pvUser, offPort);
1762 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1763 if (cb != 4)
1764 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1765
1766 DEVACPI_LOCK_R3(pDevIns, pThis);
1767 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1768
1769 VBOXSTRICTRC rc = VINF_SUCCESS;
1770 switch (pThis->uSystemInfoIndex)
1771 {
1772 case SYSTEM_INFO_INDEX_INVALID:
1773 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1774 pThis->u8IndexShift = 0;
1775 break;
1776
1777 case SYSTEM_INFO_INDEX_VALID:
1778 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1779 pThis->u8IndexShift = 2;
1780 break;
1781
1782 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1783 pThis->idCpuLockCheck = u32;
1784 break;
1785
1786 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1787 if (u32 < pThis->cCpus)
1788 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1789 else
1790 LogRel(("ACPI: CPU %u does not exist\n", u32));
1791 break;
1792
1793 default:
1794 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1795 break;
1796 }
1797
1798 DEVACPI_UNLOCK(pDevIns, pThis);
1799 return rc;
1800}
1801
1802/**
1803 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1804 */
1805static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1806{
1807 RT_NOREF(offPort, pvUser);
1808 if (cb != 2)
1809 return VERR_IOM_IOPORT_UNUSED;
1810
1811 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1812 DEVACPI_LOCK_R3(pDevIns, pThis);
1813
1814 *pu32 = pThis->pm1a_en;
1815
1816 DEVACPI_UNLOCK(pDevIns, pThis);
1817 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1818 return VINF_SUCCESS;
1819}
1820
1821/**
1822 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1823 */
1824static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1825{
1826 RT_NOREF(offPort, pvUser);
1827 if (cb != 2 && cb != 4)
1828 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1829
1830 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1831 DEVACPI_LOCK_R3(pDevIns, pThis);
1832
1833 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1834 u32 &= ~(RSR_EN | IGN_EN);
1835 u32 &= 0xffff;
1836 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1837
1838 DEVACPI_UNLOCK(pDevIns, pThis);
1839 return VINF_SUCCESS;
1840}
1841
1842/**
1843 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1844 */
1845static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1846{
1847 RT_NOREF(offPort, pvUser);
1848 if (cb != 2)
1849 {
1850 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1851 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1852 }
1853
1854 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1855 DEVACPI_LOCK_R3(pDevIns, pThis);
1856
1857 *pu32 = pThis->pm1a_sts;
1858
1859 DEVACPI_UNLOCK(pDevIns, pThis);
1860 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1861 return VINF_SUCCESS;
1862}
1863
1864/**
1865 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1866 */
1867static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1868{
1869 RT_NOREF(offPort, pvUser);
1870 if (cb != 2 && cb != 4)
1871 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1872
1873 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1874 DEVACPI_LOCK_R3(pDevIns, pThis);
1875
1876 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1877 u32 &= 0xffff;
1878 if (u32 & PWRBTN_STS)
1879 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1880 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1881 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1882
1883 DEVACPI_UNLOCK(pDevIns, pThis);
1884 return VINF_SUCCESS;
1885}
1886
1887/**
1888 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1889 */
1890static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1891{
1892 RT_NOREF(offPort, pvUser);
1893 if (cb != 2)
1894 {
1895 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1896 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1897 }
1898
1899 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1900 DEVACPI_LOCK_R3(pDevIns, pThis);
1901
1902 *pu32 = pThis->pm1a_ctl;
1903
1904 DEVACPI_UNLOCK(pDevIns, pThis);
1905 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1906 return VINF_SUCCESS;
1907}
1908
1909/**
1910 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1911 */
1912static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1913{
1914 RT_NOREF(offPort, pvUser);
1915 if (cb != 2 && cb != 4)
1916 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1917
1918 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1919 DEVACPI_LOCK_R3(pDevIns, pThis);
1920
1921 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1922 u32 &= 0xffff;
1923 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1924
1925 VBOXSTRICTRC rc = VINF_SUCCESS;
1926 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1927 if (uSleepState != pThis->uSleepState)
1928 {
1929 pThis->uSleepState = uSleepState;
1930 switch (uSleepState)
1931 {
1932 case 0x00: /* S0 */
1933 break;
1934
1935 case 0x01: /* S1 */
1936 if (pThis->fS1Enabled)
1937 {
1938 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1939 rc = acpiR3DoSleep(pDevIns, pThis);
1940 break;
1941 }
1942 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1943 RT_FALL_THRU();
1944
1945 case 0x04: /* S4 */
1946 if (pThis->fS4Enabled)
1947 {
1948 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1949 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1950 break;
1951 }
1952 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1953 RT_FALL_THRU();
1954
1955 case 0x05: /* S5 */
1956 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1957 rc = acpiR3DoPowerOff(pDevIns);
1958 break;
1959
1960 default:
1961 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1962 break;
1963 }
1964 }
1965
1966 DEVACPI_UNLOCK(pDevIns, pThis);
1967 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1968 return rc;
1969}
1970
1971#endif /* IN_RING3 */
1972
1973/**
1974 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
1975 *
1976 * @remarks The only I/O port currently implemented in all contexts.
1977 */
1978static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1979{
1980 RT_NOREF(offPort, pvUser);
1981 if (cb != 4)
1982 return VERR_IOM_IOPORT_UNUSED;
1983
1984 /*
1985 * We use the clock lock to serialize access to u64PmTimerInitial and to
1986 * make sure we get a reliable time from the clock
1987 * as well as and to prevent uPmTimerVal from being updated during read.
1988 */
1989 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1990 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1991 if (rc == VINF_SUCCESS)
1992 {
1993 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
1994 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
1995 *pu32 = pThis->uPmTimerVal;
1996
1997 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
1998
1999 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
2000 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
2001
2002#if 0
2003 /** @todo temporary: sanity check against running backwards */
2004 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
2005 if (*pu32 - uOld >= 0x10000000)
2006 {
2007# if defined(IN_RING0)
2008 pThis->uPmTimeA = uOld;
2009 pThis->uPmTimeB = *pu32;
2010 return VERR_TM_TIMER_BAD_CLOCK;
2011# elif defined(IN_RING3)
2012 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
2013# endif
2014 }
2015#endif
2016 }
2017 return rc;
2018}
2019
2020#ifdef IN_RING3
2021
2022/**
2023 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
2024 */
2025static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2026{
2027 RT_NOREF(offPort, pvUser);
2028 if (cb != 1)
2029 {
2030 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2031 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2032 }
2033
2034 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2035 DEVACPI_LOCK_R3(pDevIns, pThis);
2036
2037 *pu32 = pThis->gpe0_sts & 0xff;
2038
2039 DEVACPI_UNLOCK(pDevIns, pThis);
2040 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
2041 return VINF_SUCCESS;
2042}
2043
2044/**
2045 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
2046 */
2047static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2048{
2049 RT_NOREF(offPort, pvUser);
2050 if (cb != 1)
2051 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2052
2053 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2054 DEVACPI_LOCK_R3(pDevIns, pThis);
2055
2056 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
2057 u32 = pThis->gpe0_sts & ~u32;
2058 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
2059
2060 DEVACPI_UNLOCK(pDevIns, pThis);
2061 return VINF_SUCCESS;
2062}
2063
2064/**
2065 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
2066 */
2067static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2068{
2069 RT_NOREF(offPort, pvUser);
2070 if (cb != 1)
2071 {
2072 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2073 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2074 }
2075
2076 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2077 DEVACPI_LOCK_R3(pDevIns, pThis);
2078
2079 *pu32 = pThis->gpe0_en & 0xff;
2080
2081 DEVACPI_UNLOCK(pDevIns, pThis);
2082 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
2083 return VINF_SUCCESS;
2084}
2085
2086/**
2087 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
2088 */
2089static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2090{
2091 RT_NOREF(offPort, pvUser);
2092 if (cb != 1)
2093 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2094
2095 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2096 DEVACPI_LOCK_R3(pDevIns, pThis);
2097
2098 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
2099 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
2100
2101 DEVACPI_UNLOCK(pDevIns, pThis);
2102 return VINF_SUCCESS;
2103}
2104
2105/**
2106 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
2107 */
2108static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2109{
2110 RT_NOREF(offPort, pvUser);
2111 Log(("acpiR3SmiWrite %#x\n", u32));
2112 if (cb != 1)
2113 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2114
2115 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2116 DEVACPI_LOCK_R3(pDevIns, pThis);
2117
2118 if (u32 == ACPI_ENABLE)
2119 pThis->pm1a_ctl |= SCI_EN;
2120 else if (u32 == ACPI_DISABLE)
2121 pThis->pm1a_ctl &= ~SCI_EN;
2122 else
2123 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2124
2125 DEVACPI_UNLOCK(pDevIns, pThis);
2126 return VINF_SUCCESS;
2127}
2128
2129/**
2130 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2131 */
2132static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2133{
2134 RT_NOREF(offPort, pvUser);
2135 Log(("acpiR3ResetWrite: %#x\n", u32));
2136 NOREF(pvUser);
2137 if (cb != 1)
2138 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2139
2140 /* No state locking required. */
2141 VBOXSTRICTRC rc;
2142 if (u32 == ACPI_RESET_REG_VAL)
2143 {
2144 LogRel(("ACPI: Reset initiated by ACPI\n"));
2145 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2146 }
2147 else
2148 {
2149 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2150 rc = VINF_SUCCESS;
2151 }
2152
2153 return rc;
2154}
2155
2156# ifdef DEBUG_ACPI
2157
2158/**
2159 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2160 */
2161static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2162{
2163 NOREF(pvUser);
2164 switch (cb)
2165 {
2166 case 1:
2167 Log(("%#x\n", u32 & 0xff));
2168 break;
2169 case 2:
2170 Log(("%#6x\n", u32 & 0xffff));
2171 break;
2172 case 4:
2173 Log(("%#10x\n", u32));
2174 break;
2175 default:
2176 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2177 }
2178 return VINF_SUCCESS;
2179}
2180
2181/**
2182 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2183 */
2184static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2185{
2186 NOREF(pvUser);
2187 switch (cb)
2188 {
2189 case 1:
2190 Log(("%c", u32 & 0xff));
2191 break;
2192 default:
2193 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2194 }
2195 return VINF_SUCCESS;
2196}
2197
2198# endif /* DEBUG_ACPI */
2199
2200/**
2201 * @callback_method_impl{FNDBGFHANDLERDEV}
2202 */
2203static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2204{
2205 RT_NOREF(pszArgs);
2206 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2207 pHlp->pfnPrintf(pHlp,
2208 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2209}
2210
2211/**
2212 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2213 *
2214 * @param pDevIns The PDM device instance.
2215 * @param pThis The ACPI shared instance data.
2216 */
2217static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2218{
2219 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2220 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2221 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2222 pPciDev->abConfig[PMBA + 2] = 0x00;
2223 pPciDev->abConfig[PMBA + 3] = 0x00;
2224}
2225
2226/**
2227 * Used to calculate the value of a PM I/O port.
2228 *
2229 * @returns The actual I/O port value.
2230 * @param pThis The ACPI shared instance data.
2231 * @param offset The offset into the I/O space, or -1 if invalid.
2232 */
2233static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2234{
2235 Assert(pThis->uPmIoPortBase != 0);
2236
2237 if (offset == -1)
2238 return 0;
2239
2240 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2241}
2242
2243/**
2244 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2245 * timer and GPE0 I/O ports.
2246 *
2247 * @returns VBox status code.
2248 * @param pDevIns The device instance.
2249 * @param pThis The ACPI shared instance data.
2250 */
2251static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2252{
2253 if (pThis->uPmIoPortBase == 0)
2254 return VINF_SUCCESS;
2255
2256 int rc;
2257 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2258 AssertRCReturn(rc, rc);
2259 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2260 AssertRCReturn(rc, rc);
2261 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2262 AssertRCReturn(rc, rc);
2263 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2264 AssertRCReturn(rc, rc);
2265 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2266 AssertRCReturn(rc, rc);
2267 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2268
2269 return VINF_SUCCESS;
2270}
2271
2272/**
2273 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2274 * timer and GPE0 I/O ports.
2275 *
2276 * @returns VBox status code.
2277 * @param pDevIns The device instance.
2278 * @param pThis The ACPI shared instance data.
2279 */
2280static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2281{
2282 if (pThis->uPmIoPortBase != 0)
2283 {
2284 int rc;
2285 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2286 AssertRCReturn(rc, rc);
2287 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2288 AssertRCReturn(rc, rc);
2289 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2290 AssertRCReturn(rc, rc);
2291 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2292 AssertRCReturn(rc, rc);
2293 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2294 AssertRCReturn(rc, rc);
2295 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2296 AssertRCReturn(rc, rc);
2297 }
2298 return VINF_SUCCESS;
2299}
2300
2301/**
2302 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2303 * PM1a, PM timer and GPE0 ports.
2304 *
2305 * @returns VBox status code.
2306 *
2307 * @param pDevIns The device instance.
2308 * @param pThis The ACPI shared instance data.
2309 * @param pThisCC The ACPI instance data for ring-3.
2310 * @param NewIoPortBase The new base address of the I/O ports.
2311 */
2312static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2313{
2314 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2315 if (NewIoPortBase != pThis->uPmIoPortBase)
2316 {
2317 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2318 if (RT_FAILURE(rc))
2319 return rc;
2320
2321 pThis->uPmIoPortBase = NewIoPortBase;
2322
2323 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2324 if (RT_FAILURE(rc))
2325 return rc;
2326
2327 /* We have to update FADT table acccording to the new base */
2328 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2329 AssertRC(rc);
2330 if (RT_FAILURE(rc))
2331 return rc;
2332 }
2333
2334 return VINF_SUCCESS;
2335}
2336
2337/**
2338 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2339 */
2340static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2341{
2342 RT_NOREF(pvUser);
2343 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2344
2345 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2346 uint8_t off = offPort & 0x000f;
2347 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2348 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2349 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2350
2351 DEVACPI_LOCK_R3(pDevIns, pThis);
2352 switch (off)
2353 {
2354 case SMBHSTSTS_OFF:
2355 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2356 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2357 break;
2358 case SMBSLVSTS_OFF:
2359 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2360 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2361 break;
2362 case SMBHSTCNT_OFF:
2363 {
2364 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2365
2366 const bool old_level = acpiSCILevel(pDevIns, pThis);
2367 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2368 if (u32 & SMBHSTCNT_START)
2369 {
2370 /* Start, trigger error as this is a dummy implementation */
2371 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2372 }
2373 if (u32 & SMBHSTCNT_KILL)
2374 {
2375 /* Kill */
2376 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2377 }
2378 const bool new_level = acpiSCILevel(pDevIns, pThis);
2379
2380 LogFunc(("old=%x new=%x\n", old_level, new_level));
2381
2382 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2383 * needs to be implemented later if it ever becomes relevant. */
2384 if (new_level != old_level)
2385 acpiSetIrq(pDevIns, new_level);
2386 break;
2387 }
2388 case SMBHSTCMD_OFF:
2389 pThis->u8SMBusHstCmd = u32;
2390 break;
2391 case SMBHSTADD_OFF:
2392 pThis->u8SMBusHstAdd = u32;
2393 break;
2394 case SMBHSTDAT0_OFF:
2395 pThis->u8SMBusHstDat0 = u32;
2396 break;
2397 case SMBHSTDAT1_OFF:
2398 pThis->u8SMBusHstDat1 = u32;
2399 break;
2400 case SMBBLKDAT_OFF:
2401 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2402 pThis->u8SMBusBlkIdx++;
2403 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2404 break;
2405 case SMBSLVCNT_OFF:
2406 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2407 break;
2408 case SMBSHDWCMD_OFF:
2409 /* readonly register */
2410 break;
2411 case SMBSLVEVT_OFF:
2412 pThis->u16SMBusSlvEvt = u32;
2413 break;
2414 case SMBSLVDAT_OFF:
2415 /* readonly register */
2416 break;
2417 default:
2418 /* caught by the sanity check above */
2419 ;
2420 }
2421
2422 DEVACPI_UNLOCK(pDevIns, pThis);
2423 return VINF_SUCCESS;
2424}
2425
2426/**
2427 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2428 */
2429static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2430{
2431 RT_NOREF(pvUser);
2432 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2433
2434 VBOXSTRICTRC rc = VINF_SUCCESS;
2435 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2436 uint8_t const off = offPort & 0x000f;
2437 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2438 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2439 return VERR_IOM_IOPORT_UNUSED;
2440
2441 DEVACPI_LOCK_R3(pDevIns, pThis);
2442 switch (off)
2443 {
2444 case SMBHSTSTS_OFF:
2445 *pu32 = pThis->u8SMBusHstSts;
2446 break;
2447 case SMBSLVSTS_OFF:
2448 *pu32 = pThis->u8SMBusSlvSts;
2449 break;
2450 case SMBHSTCNT_OFF:
2451 pThis->u8SMBusBlkIdx = 0;
2452 *pu32 = pThis->u8SMBusHstCnt;
2453 break;
2454 case SMBHSTCMD_OFF:
2455 *pu32 = pThis->u8SMBusHstCmd;
2456 break;
2457 case SMBHSTADD_OFF:
2458 *pu32 = pThis->u8SMBusHstAdd;
2459 break;
2460 case SMBHSTDAT0_OFF:
2461 *pu32 = pThis->u8SMBusHstDat0;
2462 break;
2463 case SMBHSTDAT1_OFF:
2464 *pu32 = pThis->u8SMBusHstDat1;
2465 break;
2466 case SMBBLKDAT_OFF:
2467 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2468 pThis->u8SMBusBlkIdx++;
2469 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2470 break;
2471 case SMBSLVCNT_OFF:
2472 *pu32 = pThis->u8SMBusSlvCnt;
2473 break;
2474 case SMBSHDWCMD_OFF:
2475 *pu32 = pThis->u8SMBusShdwCmd;
2476 break;
2477 case SMBSLVEVT_OFF:
2478 *pu32 = pThis->u16SMBusSlvEvt;
2479 break;
2480 case SMBSLVDAT_OFF:
2481 *pu32 = pThis->u16SMBusSlvDat;
2482 break;
2483 default:
2484 /* caught by the sanity check above */
2485 rc = VERR_IOM_IOPORT_UNUSED;
2486 }
2487 DEVACPI_UNLOCK(pDevIns, pThis);
2488
2489 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2490 return rc;
2491}
2492
2493/**
2494 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2495 *
2496 * @param pDevIns The PDM device instance.
2497 * @param pThis The ACPI shared instance data.
2498 */
2499static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2500{
2501 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2502 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2503 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2504 pPciDev->abConfig[SMBBA+2] = 0x00;
2505 pPciDev->abConfig[SMBBA+3] = 0x00;
2506 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2507 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2508 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2509 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2510 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2511}
2512
2513/**
2514 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2515 *
2516 * @param pThis The ACPI shared instance data.
2517 */
2518static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2519{
2520 pThis->u8SMBusHstSts = 0x00;
2521 pThis->u8SMBusSlvSts = 0x00;
2522 pThis->u8SMBusHstCnt = 0x00;
2523 pThis->u8SMBusHstCmd = 0x00;
2524 pThis->u8SMBusHstAdd = 0x00;
2525 pThis->u8SMBusHstDat0 = 0x00;
2526 pThis->u8SMBusHstDat1 = 0x00;
2527 pThis->u8SMBusSlvCnt = 0x00;
2528 pThis->u8SMBusShdwCmd = 0x00;
2529 pThis->u16SMBusSlvEvt = 0x0000;
2530 pThis->u16SMBusSlvDat = 0x0000;
2531 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2532 pThis->u8SMBusBlkIdx = 0;
2533}
2534
2535/**
2536 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2537 *
2538 * @returns VBox status code.
2539 * @param pDevIns The device instance.
2540 * @param pThis The ACPI shared instance data.
2541 */
2542static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2543{
2544 if (pThis->uSMBusIoPortBase != 0)
2545 {
2546 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2547 AssertRCReturn(rc, rc);
2548 }
2549 return VINF_SUCCESS;
2550}
2551
2552/**
2553 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2554 *
2555 * @returns VBox status code.
2556 * @param pDevIns The device instance.
2557 * @param pThis The ACPI shared instance data.
2558 */
2559static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2560{
2561 if (pThis->uSMBusIoPortBase != 0)
2562 {
2563 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2564 AssertRCReturn(rc, rc);
2565 }
2566 return VINF_SUCCESS;
2567}
2568
2569/**
2570 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2571 * SMBus ports.
2572 *
2573 * @returns VBox status code.
2574 *
2575 * @param pDevIns The device instance.
2576 * @param pThis The ACPI shared instance data.
2577 * @param NewIoPortBase The new base address of the I/O ports.
2578 */
2579static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2580{
2581 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2582 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2583 {
2584 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2585 AssertRCReturn(rc, rc);
2586
2587 pThis->uSMBusIoPortBase = NewIoPortBase;
2588
2589 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2590 AssertRCReturn(rc, rc);
2591
2592#if 0 /* is there an FADT table entry for the SMBus base? */
2593 /* We have to update FADT table acccording to the new base */
2594 rc = acpiR3PlantTables(pThis);
2595 AssertRC(rc);
2596 if (RT_FAILURE(rc))
2597 return rc;
2598#endif
2599 }
2600
2601 return VINF_SUCCESS;
2602}
2603
2604
2605/**
2606 * Saved state structure description, version 4.
2607 */
2608static const SSMFIELD g_AcpiSavedStateFields4[] =
2609{
2610 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2611 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2612 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2613 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2614 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2615 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2616 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2617 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2618 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2619 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2620 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2621 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2622 SSMFIELD_ENTRY_TERM()
2623};
2624
2625/**
2626 * Saved state structure description, version 5.
2627 */
2628static const SSMFIELD g_AcpiSavedStateFields5[] =
2629{
2630 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2631 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2632 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2633 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2634 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2635 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2636 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2637 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2638 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2639 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2640 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2641 SSMFIELD_ENTRY_TERM()
2642};
2643
2644/**
2645 * Saved state structure description, version 6.
2646 */
2647static const SSMFIELD g_AcpiSavedStateFields6[] =
2648{
2649 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2650 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2651 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2652 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2653 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2654 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2655 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2656 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2657 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2658 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2659 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2660 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2661 SSMFIELD_ENTRY_TERM()
2662};
2663
2664/**
2665 * Saved state structure description, version 7.
2666 */
2667static const SSMFIELD g_AcpiSavedStateFields7[] =
2668{
2669 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2670 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2671 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2672 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2673 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2674 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2675 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2676 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2677 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2678 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2679 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2680 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2681 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2682 SSMFIELD_ENTRY_TERM()
2683};
2684
2685/**
2686 * Saved state structure description, version 8.
2687 */
2688static const SSMFIELD g_AcpiSavedStateFields8[] =
2689{
2690 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2691 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2692 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2693 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2694 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2695 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2696 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2697 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2698 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2699 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2700 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2701 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2702 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2703 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2704 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2705 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2706 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2707 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2708 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2709 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2710 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2711 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2712 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2713 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2714 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2715 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2716 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2717 SSMFIELD_ENTRY_TERM()
2718};
2719
2720/**
2721 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2722 */
2723static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2724{
2725 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2726 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2727 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2728}
2729
2730/**
2731 * @callback_method_impl{FNSSMDEVLOADEXEC}
2732 */
2733static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2734{
2735 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2736 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2737 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2738 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2739
2740 /*
2741 * Unmap PM I/O ports, will remap it with the actual base after state
2742 * successfully loaded.
2743 */
2744 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2745 AssertRCReturn(rc, rc);
2746
2747 /*
2748 * Unregister SMBus handlers, will register with actual base after state
2749 * successfully loaded.
2750 */
2751 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2752 AssertRCReturn(rc, rc);
2753 acpiR3SMBusResetDevice(pThis);
2754
2755 switch (uVersion)
2756 {
2757 case 4:
2758 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2759 break;
2760 case 5:
2761 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2762 break;
2763 case 6:
2764 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2765 break;
2766 case 7:
2767 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2768 break;
2769 case 8:
2770 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2771 break;
2772 default:
2773 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2774 break;
2775 }
2776 if (RT_SUCCESS(rc))
2777 {
2778 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2779 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2780 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2781 AssertRCReturn(rc, rc);
2782 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2783 AssertRCReturn(rc, rc);
2784 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2785 AssertRCReturn(rc, rc);
2786 rc = acpiR3FetchBatteryInfo(pThis);
2787 AssertRCReturn(rc, rc);
2788
2789 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2790 DEVACPI_LOCK_R3(pDevIns, pThis);
2791 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2792 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2793 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2794 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2795 DEVACPI_UNLOCK(pDevIns, pThis);
2796 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2797 }
2798 return rc;
2799}
2800
2801/**
2802 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2803 */
2804static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2805{
2806 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2807 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2808 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2809 return NULL;
2810}
2811
2812/**
2813 * Calculate the check sum for some ACPI data before planting it.
2814 *
2815 * All the bytes must add up to 0.
2816 *
2817 * @returns check sum.
2818 * @param pvSrc What to check sum.
2819 * @param cbData The amount of data to checksum.
2820 */
2821static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2822{
2823 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2824 uint8_t uSum = 0;
2825 for (size_t i = 0; i < cbData; ++i)
2826 uSum += pbSrc[i];
2827 return -uSum;
2828}
2829
2830/**
2831 * Prepare a ACPI table header.
2832 */
2833static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2834 const char au8Signature[4],
2835 uint32_t u32Length, uint8_t u8Revision)
2836{
2837 memcpy(header->au8Signature, au8Signature, 4);
2838 header->u32Length = RT_H2LE_U32(u32Length);
2839 header->u8Revision = u8Revision;
2840 memcpy(header->au8OemId, pThis->au8OemId, 6);
2841 memcpy(header->au8OemTabId, "VBOX", 4);
2842 memcpy(header->au8OemTabId+4, au8Signature, 4);
2843 header->u32OemRevision = RT_H2LE_U32(1);
2844 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2845 header->u32CreatorRev = pThis->u32CreatorRev;
2846}
2847
2848/**
2849 * Initialize a generic address structure (ACPIGENADDR).
2850 */
2851static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2852 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2853 uint8_t u8AccessSize, uint64_t u64Address)
2854{
2855 g->u8AddressSpaceId = u8AddressSpaceId;
2856 g->u8RegisterBitWidth = u8RegisterBitWidth;
2857 g->u8RegisterBitOffset = u8RegisterBitOffset;
2858 g->u8AccessSize = u8AccessSize;
2859 g->u64Address = RT_H2LE_U64(u64Address);
2860}
2861
2862/**
2863 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2864 */
2865DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2866{
2867 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2868}
2869
2870/**
2871 * Plant the Differentiated System Description Table (DSDT).
2872 */
2873static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2874{
2875 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2876}
2877
2878/**
2879 * Plant the Secondary System Description Table (SSDT).
2880 */
2881static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2882{
2883 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2884}
2885
2886#ifdef VBOX_WITH_TPM
2887/**
2888 * Plant the Secondary System Description Table (SSDT).
2889 */
2890static void acpiR3SetupTpmSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2891{
2892 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2893}
2894#endif
2895
2896/**
2897 * Plant the Firmware ACPI Control Structure (FACS).
2898 */
2899static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2900{
2901 ACPITBLFACS facs;
2902
2903 memset(&facs, 0, sizeof(facs));
2904 memcpy(facs.au8Signature, "FACS", 4);
2905 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2906 facs.u32HWSignature = RT_H2LE_U32(0);
2907 facs.u32FWVector = RT_H2LE_U32(0);
2908 facs.u32GlobalLock = RT_H2LE_U32(0);
2909 facs.u32Flags = RT_H2LE_U32(0);
2910 facs.u64X_FWVector = RT_H2LE_U64(0);
2911 facs.u8Version = 1;
2912
2913 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2914}
2915
2916/**
2917 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2918 */
2919static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2920 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2921{
2922 ACPITBLFADT fadt;
2923
2924 /* First the ACPI version 2+ version of the structure. */
2925 memset(&fadt, 0, sizeof(fadt));
2926 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2927 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2928 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2929 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2930 fadt.u8PreferredPMProfile = 0; /* unspecified */
2931 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2932 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2933 fadt.u8AcpiEnable = ACPI_ENABLE;
2934 fadt.u8AcpiDisable = ACPI_DISABLE;
2935 fadt.u8S4BIOSReq = 0;
2936 fadt.u8PStateCnt = 0;
2937 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2938 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2939 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2940 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2941 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2942 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2943 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2944 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2945 fadt.u8PM1EVTLEN = 4;
2946 fadt.u8PM1CTLLEN = 2;
2947 fadt.u8PM2CTLLEN = 0;
2948 fadt.u8PMTMLEN = 4;
2949 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2950 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2951 fadt.u8GPE1BASE = GPE1_BASE;
2952 fadt.u8CSTCNT = 0;
2953 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2954 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2955 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2956 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2957 fadt.u8DutyOffset = 0;
2958 fadt.u8DutyWidth = 0;
2959 fadt.u8DayAlarm = 0;
2960 fadt.u8MonAlarm = 0;
2961 fadt.u8Century = 0;
2962 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2963 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2964 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2965 | FADT_FL_FIX_RTC
2966 | FADT_FL_TMR_VAL_EXT
2967 | FADT_FL_RESET_REG_SUP);
2968
2969 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2970 if (pThis->fCpuHotPlug)
2971 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2972
2973 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2974 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2975 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2976 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2977 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2978 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2979 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2980 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2981 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2982 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2983 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2984 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2985 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2986 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
2987
2988 /* Now the ACPI 1.0 version. */
2989 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2990 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2991 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2992 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2993 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2994}
2995
2996/**
2997 * Plant the root System Description Table.
2998 *
2999 * The RSDT and XSDT tables are basically identical. The only difference is 32
3000 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
3001 * ACPI 2.0 and up.
3002 */
3003static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3004{
3005 ACPITBLRSDT *rsdt;
3006 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
3007
3008 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
3009 if (!rsdt)
3010 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
3011
3012 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
3013 for (unsigned int i = 0; i < nb_entries; ++i)
3014 {
3015 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
3016 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
3017 }
3018 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
3019 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
3020 RTMemFree(rsdt);
3021 return VINF_SUCCESS;
3022}
3023
3024/**
3025 * Plant the Extended System Description Table.
3026 */
3027static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3028{
3029 ACPITBLXSDT *xsdt;
3030 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
3031 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
3032 if (!xsdt)
3033 return VERR_NO_TMP_MEMORY;
3034
3035 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
3036
3037 if (pThis->cCustTbls > 0)
3038 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
3039
3040 for (unsigned int i = 0; i < nb_entries; ++i)
3041 {
3042 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
3043 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
3044 }
3045 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
3046 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
3047
3048 RTMemFree(xsdt);
3049 return VINF_SUCCESS;
3050}
3051
3052/**
3053 * Plant the Root System Description Pointer (RSDP).
3054 */
3055static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
3056{
3057 memset(rsdp, 0, sizeof(*rsdp));
3058
3059 /* ACPI 1.0 part (RSDT) */
3060 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
3061 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
3062 rsdp->u8Revision = ACPI_REVISION;
3063 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
3064 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
3065
3066 /* ACPI 2.0 part (XSDT) */
3067 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
3068 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
3069 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
3070}
3071
3072/**
3073 * Multiple APIC Description Table.
3074 *
3075 * This structure looks somewhat convoluted due layout of MADT table in MP case.
3076 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
3077 * use regular C structure and proxy to raw memory instead.
3078 */
3079class AcpiTableMadt
3080{
3081 /**
3082 * All actual data stored in dynamically allocated memory pointed by this field.
3083 */
3084 uint8_t *m_pbData;
3085 /**
3086 * Number of CPU entries in this MADT.
3087 */
3088 uint32_t m_cCpus;
3089
3090 /**
3091 * Number of interrupt overrides.
3092 */
3093 uint32_t m_cIsos;
3094
3095public:
3096 /**
3097 * Address of ACPI header
3098 */
3099 inline ACPITBLHEADER *header_addr(void) const
3100 {
3101 return (ACPITBLHEADER *)m_pbData;
3102 }
3103
3104 /**
3105 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
3106 * although address is the same for all of them.
3107 */
3108 inline uint32_t *u32LAPIC_addr(void) const
3109 {
3110 return (uint32_t *)(header_addr() + 1);
3111 }
3112
3113 /**
3114 * Address of APIC flags
3115 */
3116 inline uint32_t *u32Flags_addr(void) const
3117 {
3118 return (uint32_t *)(u32LAPIC_addr() + 1);
3119 }
3120
3121 /**
3122 * Address of ISO description
3123 */
3124 inline ACPITBLISO *ISO_addr(void) const
3125 {
3126 return (ACPITBLISO *)(u32Flags_addr() + 1);
3127 }
3128
3129 /**
3130 * Address of per-CPU LAPIC descriptions
3131 */
3132 inline ACPITBLLAPIC *LApics_addr(void) const
3133 {
3134 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3135 }
3136
3137 /**
3138 * Address of IO APIC description
3139 */
3140 inline ACPITBLIOAPIC *IOApic_addr(void) const
3141 {
3142 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3143 }
3144
3145 /**
3146 * Size of MADT.
3147 * Note that this function assumes IOApic to be the last field in structure.
3148 */
3149 inline uint32_t size(void) const
3150 {
3151 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3152 }
3153
3154 /**
3155 * Raw data of MADT.
3156 */
3157 inline const uint8_t *data(void) const
3158 {
3159 return m_pbData;
3160 }
3161
3162 /**
3163 * Size of MADT for given ACPI config, useful to compute layout.
3164 */
3165 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3166 {
3167 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3168 }
3169
3170 /*
3171 * Constructor, only works in Ring 3, doesn't look like a big deal.
3172 */
3173 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3174 {
3175 m_cCpus = cCpus;
3176 m_cIsos = cIsos;
3177 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3178 uint32_t cb = size();
3179 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3180 }
3181
3182 ~AcpiTableMadt()
3183 {
3184 RTMemFree(m_pbData);
3185 }
3186};
3187
3188
3189/**
3190 * Plant the Multiple APIC Description Table (MADT).
3191 *
3192 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3193 *
3194 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3195 */
3196static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3197{
3198 uint16_t cpus = pThis->cCpus;
3199 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3200
3201 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3202
3203 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3204 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3205
3206 /* LAPICs records */
3207 ACPITBLLAPIC* lapic = madt.LApics_addr();
3208 for (uint16_t i = 0; i < cpus; i++)
3209 {
3210 lapic->u8Type = 0;
3211 lapic->u8Length = sizeof(ACPITBLLAPIC);
3212 lapic->u8ProcId = i;
3213 /** Must match numbering convention in MPTABLES */
3214 lapic->u8ApicId = i;
3215 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3216 lapic++;
3217 }
3218
3219 /* IO-APIC record */
3220 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3221 ioapic->u8Type = 1;
3222 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3223 /** Must match MP tables ID */
3224 ioapic->u8IOApicId = cpus;
3225 ioapic->u8Reserved = 0;
3226 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3227 ioapic->u32GSIB = RT_H2LE_U32(0);
3228
3229 /* Interrupt Source Overrides */
3230 /* Flags:
3231 bits[3:2]:
3232 00 conforms to the bus
3233 01 edge-triggered
3234 10 reserved
3235 11 level-triggered
3236 bits[1:0]
3237 00 conforms to the bus
3238 01 active-high
3239 10 reserved
3240 11 active-low */
3241 /* If changing, also update PDMIsaSetIrq() and MPS */
3242 ACPITBLISO* isos = madt.ISO_addr();
3243 /* Timer interrupt rule IRQ0 to GSI2 */
3244 isos[0].u8Type = 2;
3245 isos[0].u8Length = sizeof(ACPITBLISO);
3246 isos[0].u8Bus = 0; /* Must be 0 */
3247 isos[0].u8Source = 0; /* IRQ0 */
3248 isos[0].u32GSI = 2; /* connected to pin 2 */
3249 isos[0].u16Flags = 0; /* conform to the bus */
3250
3251 /* ACPI interrupt rule - IRQ9 to GSI9 */
3252 isos[1].u8Type = 2;
3253 isos[1].u8Length = sizeof(ACPITBLISO);
3254 isos[1].u8Bus = 0; /* Must be 0 */
3255 isos[1].u8Source = 9; /* IRQ9 */
3256 isos[1].u32GSI = 9; /* connected to pin 9 */
3257 isos[1].u16Flags = 0xf; /* active low, level triggered */
3258 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3259
3260 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3261 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3262}
3263
3264/**
3265 * Plant the High Performance Event Timer (HPET) descriptor.
3266 */
3267static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3268{
3269 ACPITBLHPET hpet;
3270
3271 memset(&hpet, 0, sizeof(hpet));
3272
3273 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3274 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3275 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3276 0 /* Memory address space */,
3277 64 /* Register bit width */,
3278 0 /* Bit offset */,
3279 0, /* Register access size, is it correct? */
3280 0xfed00000 /* Address */);
3281
3282 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3283 hpet.u32Number = 0;
3284 hpet.u32MinTick = 4096;
3285 hpet.u8Attributes = 0;
3286
3287 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3288
3289 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3290}
3291
3292
3293#ifdef VBOX_WITH_IOMMU_AMD
3294/**
3295 * Plant the AMD IOMMU descriptor.
3296 */
3297static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3298{
3299 ACPITBLIOMMU Ivrs;
3300 RT_ZERO(Ivrs);
3301
3302 uint16_t const uIommuBus = 0;
3303 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuPciAddress);
3304 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuPciAddress);
3305
3306 /* IVRS header. */
3307 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3308 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3309 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3310 | RT_BF_MAKE(ACPI_IVINFO_BF_DMA_REMAP_SUP, 0) /* Pre-boot DMA remap support not supported. */
3311 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3312 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3313 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64) /* Virt. Addr size (64 bits) */
3314 | RT_BF_MAKE(ACPI_IVINFO_BF_HT_ATS_RESV, 0); /* ATS response range reserved (only applicable for HT) */
3315
3316 /* IVHD type 10 definition block. */
3317 Ivrs.IvhdType10.u8Type = 0x10;
3318 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3319 + sizeof(Ivrs.IvhdType10Start)
3320 + sizeof(Ivrs.IvhdType10End)
3321 + sizeof(Ivrs.IvhdType10Rsvd0)
3322 + sizeof(Ivrs.IvhdType10Rsvd1)
3323 + sizeof(Ivrs.IvhdType10IoApic)
3324 + sizeof(Ivrs.IvhdType10Hpet);
3325 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3326 Ivrs.IvhdType10.u16CapOffset = IOMMU_PCI_OFF_CAP_HDR;
3327 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR;
3328 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3329 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3330 Ivrs.IvhdType10.u8Flags = ACPI_IVHD_10H_F_COHERENT; /* Remote IOTLB etc. not supported. */
3331 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3332 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3333 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3334 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3335 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3336 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3337 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3338 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3339 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3340 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3341 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3342 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3343 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3344 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3345 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3346 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3);
3347 /* Start range from BDF (00:01:00). */
3348 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3349 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3350 Ivrs.IvhdType10Start.u8DteSetting = 0;
3351 /* End range at BDF (ff:1f:7). */
3352 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3353 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3354 Ivrs.IvhdType10End.u8DteSetting = 0;
3355
3356 /* Southbridge I/O APIC special device entry. */
3357 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3358 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3359 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3360 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3361 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3362 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3363 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3364 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3365 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3366 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3367
3368 /* HPET special device entry. */
3369 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3370 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3371 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3372 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3373 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3374 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3375
3376 /* IVHD type 11 definition block. */
3377 Ivrs.IvhdType11.u8Type = 0x11;
3378 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3379 + sizeof(Ivrs.IvhdType11Start)
3380 + sizeof(Ivrs.IvhdType11End)
3381 + sizeof(Ivrs.IvhdType11Rsvd0)
3382 + sizeof(Ivrs.IvhdType11Rsvd1)
3383 + sizeof(Ivrs.IvhdType11IoApic)
3384 + sizeof(Ivrs.IvhdType11Hpet);
3385 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3386 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3387 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3388 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3389 Ivrs.IvhdType11.u8Flags = ACPI_IVHD_11H_F_COHERENT;
3390 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3391 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3392 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3393 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3394 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3395 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3396 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3397 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3398 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3399 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3400 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 1)
3401 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3402 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3403 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3404 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3)
3405 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3406 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3407 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3408 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3409 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3410 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3411 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3412 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3413 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3414 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS)
3415 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3416 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3417 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3418 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3419 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3420 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3421 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3422 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3423 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3424 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3425 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3426 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3427 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3428 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3429
3430 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3431 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3432 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3433 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3434 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3435 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3436 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3437
3438 /* Finally, compute checksum. */
3439 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3440
3441 /* Plant the ACPI table. */
3442 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3443}
3444#endif /* VBOX_WITH_IOMMU_AMD */
3445
3446
3447#ifdef VBOX_WITH_IOMMU_INTEL
3448/**
3449 * Plant the Intel IOMMU (VT-d) descriptor.
3450 */
3451static void acpiR3SetupIommuIntel(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3452{
3453 ACPITBLVTD VtdTable;
3454 RT_ZERO(VtdTable);
3455
3456 /* VT-d Table. */
3457 acpiR3PrepareHeader(pThis, &VtdTable.Dmar.Hdr, "DMAR", sizeof(ACPITBLVTD), ACPI_DMAR_REVISION);
3458
3459 /* DMAR. */
3460 uint8_t cPhysAddrBits;
3461 uint8_t cLinearAddrBits;
3462 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cPhysAddrBits, &cLinearAddrBits);
3463 Assert(cPhysAddrBits > 0); NOREF(cLinearAddrBits);
3464 VtdTable.Dmar.uHostAddrWidth = cPhysAddrBits - 1;
3465 VtdTable.Dmar.fFlags = DMAR_ACPI_DMAR_FLAGS;
3466
3467 /* DRHD. */
3468 VtdTable.Drhd.cbLength = sizeof(ACPIDRHD);
3469 VtdTable.Drhd.fFlags = ACPI_DRHD_F_INCLUDE_PCI_ALL;
3470 VtdTable.Drhd.uRegBaseAddr = DMAR_MMIO_BASE_PHYSADDR;
3471
3472 /* Device Scopes: I/O APIC. */
3473 if (pThis->u8UseIOApic)
3474 {
3475 uint8_t const uIoApicBus = 0;
3476 uint8_t const uIoApicDev = RT_HI_U16(pThis->u32SbIoApicPciAddress);
3477 uint8_t const uIoApicFn = RT_LO_U16(pThis->u32SbIoApicPciAddress);
3478
3479 VtdTable.DevScopeIoApic.uType = ACPIDMARDEVSCOPE_TYPE_IOAPIC;
3480 VtdTable.DevScopeIoApic.cbLength = sizeof(ACPIDMARDEVSCOPE);
3481 VtdTable.DevScopeIoApic.idEnum = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3482 VtdTable.DevScopeIoApic.uStartBusNum = uIoApicBus;
3483 VtdTable.DevScopeIoApic.Path.uDevice = uIoApicDev;
3484 VtdTable.DevScopeIoApic.Path.uFunction = uIoApicFn;
3485
3486 VtdTable.Drhd.cbLength += sizeof(VtdTable.DevScopeIoApic);
3487 }
3488
3489 /* Finally, compute checksum. */
3490 VtdTable.Dmar.Hdr.u8Checksum = acpiR3Checksum(&VtdTable, sizeof(VtdTable));
3491
3492 /* Plant the ACPI table. */
3493 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&VtdTable, sizeof(VtdTable));
3494}
3495#endif /* VBOX_WITH_IOMMU_INTEL */
3496
3497
3498#ifdef VBOX_WITH_TPM
3499/**
3500 * Plant the TPM 2.0 ACPI descriptor.
3501 */
3502static void acpiR3SetupTpm(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3503{
3504 ACPITBLTPM20 Tpm2Tbl;
3505 RT_ZERO(Tpm2Tbl);
3506
3507 acpiR3PrepareHeader(pThis, &Tpm2Tbl.Hdr, "TPM2", sizeof(ACPITBLTPM20), ACPI_TPM20_REVISION);
3508
3509 switch (pThis->enmTpmMode)
3510 {
3511 case ACPITPMMODE_CRB_2_0:
3512 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_CRB;
3513 Tpm2Tbl.u64BaseAddrCrbOrFifo = pThis->GCPhysTpmMmio;
3514 break;
3515 case ACPITPMMODE_TIS_1_2:
3516 case ACPITPMMODE_FIFO_2_0:
3517 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_TIS12;
3518 break;
3519 case ACPITPMMODE_DISABLED: /* Should never be called with the TPM disabled. */
3520 default:
3521 AssertFailed();
3522 }
3523
3524 Tpm2Tbl.u16PlatCls = ACPITBL_TPM20_PLAT_CLS_CLIENT;
3525
3526 /* Finally, compute checksum. */
3527 Tpm2Tbl.Hdr.u8Checksum = acpiR3Checksum(&Tpm2Tbl, sizeof(Tpm2Tbl));
3528
3529 /* Plant the ACPI table. */
3530 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Tpm2Tbl, sizeof(Tpm2Tbl));
3531}
3532#endif
3533
3534
3535/**
3536 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3537 * descriptor.
3538 *
3539 * @param pDevIns The device instance.
3540 * @param pThis The ACPI shared instance data.
3541 * @param GCPhysDst Where to plant it.
3542 */
3543static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3544{
3545 struct
3546 {
3547 ACPITBLMCFG hdr;
3548 ACPITBLMCFGENTRY entry;
3549 } tbl;
3550 uint8_t u8StartBus = 0;
3551 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3552
3553 RT_ZERO(tbl);
3554
3555 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3556 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3557 tbl.entry.u8StartBus = u8StartBus;
3558 tbl.entry.u8EndBus = u8EndBus;
3559 // u16PciSegmentGroup must match _SEG in ACPI table
3560
3561 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3562
3563 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3564}
3565
3566/**
3567 * Used by acpiR3PlantTables and acpiConstruct.
3568 *
3569 * @returns Guest memory address.
3570 */
3571static uint32_t apicR3FindRsdpSpace(void)
3572{
3573 return 0xe0000;
3574}
3575
3576/**
3577 * Called by acpiR3Construct to read and allocate a custom ACPI table
3578 *
3579 * @param pDevIns The device instance.
3580 * @param ppu8CustBin Address to receive the address of the table
3581 * @param pcbCustBin Address to receive the size of the the table.
3582 * @param pszCustBinFile
3583 * @param cbBufAvail Maximum space in bytes available for the custom
3584 * table (including header).
3585 */
3586static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3587 char *pszCustBinFile, uint32_t cbBufAvail)
3588{
3589 RTFILE FileCUSTBin;
3590 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3591 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3592 if (RT_SUCCESS(rc))
3593 {
3594 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3595 if (RT_SUCCESS(rc))
3596 {
3597 /* The following checks should be in sync the AssertReleaseMsg's below. */
3598 if ( *pcbCustBin > cbBufAvail
3599 || *pcbCustBin < sizeof(ACPITBLHEADER))
3600 rc = VERR_TOO_MUCH_DATA;
3601
3602 /*
3603 * Allocate buffer for the custom table binary data.
3604 */
3605 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3606 if (*ppu8CustBin)
3607 {
3608 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3609 if (RT_FAILURE(rc))
3610 {
3611 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3612 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3613 *ppu8CustBin = NULL;
3614 }
3615 }
3616 else
3617 {
3618 rc = VERR_NO_MEMORY;
3619 }
3620 RTFileClose(FileCUSTBin);
3621 }
3622 }
3623 return rc;
3624}
3625
3626/**
3627 * Create the ACPI tables in guest memory.
3628 */
3629static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3630{
3631 int rc;
3632 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3633 RTGCPHYS32 GCPhysHpet = 0;
3634#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3635 RTGCPHYS32 GCPhysIommu = 0;
3636#endif
3637#ifdef VBOX_WITH_TPM
3638 RTGCPHYS32 GCPhysTpm = 0;
3639 RTGCPHYS32 GCPhysSsdtTpm = 0;
3640#endif
3641 RTGCPHYS32 GCPhysApic = 0;
3642 RTGCPHYS32 GCPhysSsdt = 0;
3643 RTGCPHYS32 GCPhysMcfg = 0;
3644 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3645 uint32_t addend = 0;
3646#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3647# ifdef VBOX_WITH_TPM
3648 RTGCPHYS32 aGCPhysRsdt[10 + MAX_CUST_TABLES];
3649 RTGCPHYS32 aGCPhysXsdt[10 + MAX_CUST_TABLES];
3650# else
3651 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3652 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3653# endif
3654#else
3655# ifdef VBOX_WITH_TPM
3656 RTGCPHYS32 aGCPhysRsdt[9 + MAX_CUST_TABLES];
3657 RTGCPHYS32 aGCPhysXsdt[9 + MAX_CUST_TABLES];
3658# else
3659 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3660 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3661# endif
3662#endif
3663 uint32_t cAddr;
3664 uint32_t iMadt = 0;
3665 uint32_t iHpet = 0;
3666#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3667 uint32_t iIommu = 0;
3668#endif
3669#ifdef VBOX_WITH_TPM
3670 uint32_t iTpm = 0;
3671 uint32_t iSsdtTpm = 0;
3672#endif
3673 uint32_t iSsdt = 0;
3674 uint32_t iMcfg = 0;
3675 uint32_t iCust = 0;
3676 size_t cbRsdt = sizeof(ACPITBLHEADER);
3677 size_t cbXsdt = sizeof(ACPITBLHEADER);
3678
3679 cAddr = 1; /* FADT */
3680 if (pThis->u8UseIOApic)
3681 iMadt = cAddr++; /* MADT */
3682
3683 if (pThis->fUseHpet)
3684 iHpet = cAddr++; /* HPET */
3685
3686#ifdef VBOX_WITH_IOMMU_AMD
3687 if (pThis->fUseIommuAmd)
3688 iIommu = cAddr++; /* IOMMU (AMD) */
3689#endif
3690
3691#ifdef VBOX_WITH_IOMMU_INTEL
3692 if (pThis->fUseIommuIntel)
3693 iIommu = cAddr++; /* IOMMU (Intel) */
3694#endif
3695
3696#ifdef VBOX_WITH_TPM
3697 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3698 {
3699 iTpm = cAddr++; /* TPM device */
3700 iSsdtTpm = cAddr++;
3701 }
3702#endif
3703
3704 if (pThis->fUseMcfg)
3705 iMcfg = cAddr++; /* MCFG */
3706
3707 if (pThis->cCustTbls > 0)
3708 {
3709 iCust = cAddr; /* CUST */
3710 cAddr += pThis->cCustTbls;
3711 }
3712
3713 iSsdt = cAddr++; /* SSDT */
3714
3715 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3716 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3717
3718 cbRsdt += cAddr * sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3719 cbXsdt += cAddr * sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3720
3721 /*
3722 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3723 * The latter starts never below 4G.
3724 */
3725 PVM pVM = PDMDevHlpGetVM(pDevIns);
3726 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3727 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3728
3729 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3730 if (pThis->fPciPref64Enabled)
3731 {
3732 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3733 if (pThis->u64PciPref64Max > u64PciPref64Min)
3734 {
3735 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3736 pThis->u64PciPref64Min = u64PciPref64Min;
3737 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3738 u64PciPref64Min, pThis->u64PciPref64Max-1));
3739 }
3740 else
3741 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3742 u64PciPref64Min, pThis->u64PciPref64Max-1));
3743 }
3744 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3745 {
3746 /* Note: This is also enforced by DevPcBios.cpp. */
3747 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3748 cbBelow4GB = UINT32_C(0xfe000000);
3749 }
3750 pThis->cbRamLow = cbBelow4GB;
3751
3752 GCPhysCur = 0;
3753 GCPhysRsdt = GCPhysCur;
3754
3755 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3756 GCPhysXsdt = GCPhysCur;
3757
3758 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3759 GCPhysFadtAcpi1 = GCPhysCur;
3760
3761 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3762 GCPhysFadtAcpi2 = GCPhysCur;
3763
3764 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3765 GCPhysFacs = GCPhysCur;
3766
3767 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3768 if (pThis->u8UseIOApic)
3769 {
3770 GCPhysApic = GCPhysCur;
3771 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3772 }
3773 if (pThis->fUseHpet)
3774 {
3775 GCPhysHpet = GCPhysCur;
3776 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3777 }
3778#ifdef VBOX_WITH_IOMMU_AMD
3779 if (pThis->fUseIommuAmd)
3780 {
3781 GCPhysIommu = GCPhysCur;
3782 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3783 }
3784#endif
3785#ifdef VBOX_WITH_IOMMU_INTEL
3786 if (pThis->fUseIommuIntel)
3787 {
3788 GCPhysIommu = GCPhysCur;
3789 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLVTD), 16);
3790 }
3791#endif
3792#ifdef VBOX_WITH_TPM
3793 void *pvSsdtTpmCode = NULL;
3794 size_t cbSsdtTpm = 0;
3795
3796 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3797 {
3798 GCPhysTpm = GCPhysCur;
3799 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLTPM20), 16); /** @todo TPM1.2 */
3800
3801 rc = acpiPrepareTpmSsdt(pDevIns, &pvSsdtTpmCode, &cbSsdtTpm);
3802 if (RT_FAILURE(rc))
3803 return rc;
3804
3805 GCPhysSsdtTpm = GCPhysCur;
3806 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdtTpm, 16);
3807 }
3808#endif
3809
3810 if (pThis->fUseMcfg)
3811 {
3812 GCPhysMcfg = GCPhysCur;
3813 /* Assume one entry */
3814 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3815 }
3816
3817 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3818 {
3819 aGCPhysCust[i] = GCPhysCur;
3820 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3821 }
3822
3823 void *pvSsdtCode = NULL;
3824 size_t cbSsdt = 0;
3825 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3826 if (RT_FAILURE(rc))
3827 return rc;
3828
3829 GCPhysSsdt = GCPhysCur;
3830 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3831
3832 GCPhysDsdt = GCPhysCur;
3833
3834 void *pvDsdtCode = NULL;
3835 size_t cbDsdt = 0;
3836 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3837 if (RT_FAILURE(rc))
3838 return rc;
3839
3840 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3841
3842 if (GCPhysCur > 0x10000)
3843 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3844 N_("Error: ACPI tables bigger than 64KB"));
3845
3846 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3847 addend = pThis->cbRamLow - 0x10000;
3848 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3849 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3850 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3851 if (pThis->u8UseIOApic)
3852 Log((" MADT 0x%08X", GCPhysApic + addend));
3853 if (pThis->fUseHpet)
3854 Log((" HPET 0x%08X", GCPhysHpet + addend));
3855 if (pThis->fUseMcfg)
3856 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3857 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3858 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3859 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3860 Log(("\n"));
3861
3862 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3863 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3864 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3865 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3866 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3867
3868 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3869 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3870 if (pThis->u8UseIOApic)
3871 {
3872 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3873 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3874 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3875 }
3876 if (pThis->fUseHpet)
3877 {
3878 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3879 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3880 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3881 }
3882#ifdef VBOX_WITH_IOMMU_AMD
3883 if (pThis->fUseIommuAmd)
3884 {
3885 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommu + addend);
3886 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3887 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3888 }
3889#endif
3890#ifdef VBOX_WITH_IOMMU_INTEL
3891 if (pThis->fUseIommuIntel)
3892 {
3893 acpiR3SetupIommuIntel(pDevIns, pThis, GCPhysIommu + addend);
3894 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3895 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3896 }
3897#endif
3898#ifdef VBOX_WITH_TPM
3899 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3900 {
3901 acpiR3SetupTpm(pDevIns, pThis, GCPhysTpm + addend);
3902 aGCPhysRsdt[iTpm] = GCPhysTpm + addend;
3903 aGCPhysXsdt[iTpm] = GCPhysTpm + addend;
3904
3905 acpiR3SetupTpmSsdt(pDevIns, GCPhysSsdtTpm + addend, pvSsdtTpmCode, cbSsdtTpm);
3906 acpiCleanupTpmSsdt(pDevIns, pvSsdtTpmCode);
3907 aGCPhysRsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3908 aGCPhysXsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3909 }
3910#endif
3911
3912 if (pThis->fUseMcfg)
3913 {
3914 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3915 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3916 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3917 }
3918 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3919 {
3920 Assert(i < MAX_CUST_TABLES);
3921 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3922 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3923 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3924 uint8_t* pSig = pThisCC->apu8CustBin[i];
3925 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3926 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3927 }
3928
3929 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3930 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3931 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3932 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3933
3934 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3935 if (RT_FAILURE(rc))
3936 return rc;
3937 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3938}
3939
3940/**
3941 * @callback_method_impl{FNPCICONFIGREAD}
3942 */
3943static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3944 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
3945{
3946 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3947 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3948 return rcStrict;
3949}
3950
3951/**
3952 * @callback_method_impl{FNPCICONFIGWRITE}
3953 */
3954static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3955 uint32_t uAddress, unsigned cb, uint32_t u32Value)
3956{
3957 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
3958 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
3959
3960 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
3961 DEVACPI_LOCK_R3(pDevIns, pThis);
3962
3963 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
3964 {
3965 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
3966 u32Value = SCI_INT;
3967 }
3968
3969 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3970
3971 /* Assume that the base address is only changed when the corresponding
3972 * hardware functionality is disabled. The IO region is mapped when the
3973 * functionality is enabled by the guest. */
3974
3975 if (uAddress == PMREGMISC)
3976 {
3977 RTIOPORT NewIoPortBase = 0;
3978 /* Check Power Management IO Space Enable (PMIOSE) bit */
3979 if (pPciDev->abConfig[PMREGMISC] & 0x01)
3980 {
3981 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
3982 NewIoPortBase &= 0xffc0;
3983 }
3984
3985 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
3986 AssertRC(rc);
3987 }
3988
3989 if (uAddress == SMBHSTCFG)
3990 {
3991 RTIOPORT NewIoPortBase = 0;
3992 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
3993 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
3994 {
3995 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
3996 NewIoPortBase &= 0xfff0;
3997 }
3998
3999 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
4000 AssertRC(rc);
4001 }
4002
4003 DEVACPI_UNLOCK(pDevIns, pThis);
4004 return rcStrict;
4005}
4006
4007/**
4008 * Attach a new CPU.
4009 *
4010 * @returns VBox status code.
4011 * @param pDevIns The device instance.
4012 * @param iLUN The logical unit which is being attached.
4013 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4014 *
4015 * @remarks This code path is not used during construction.
4016 */
4017static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4018{
4019 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4020 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4021 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4022
4023 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4024 ("Hot-plug flag is not set\n"),
4025 VERR_NOT_SUPPORTED);
4026 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
4027
4028 /* Check if it was already attached */
4029 int rc = VINF_SUCCESS;
4030 DEVACPI_LOCK_R3(pDevIns, pThis);
4031 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4032 {
4033 PPDMIBASE IBaseTmp;
4034 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4035 if (RT_SUCCESS(rc))
4036 {
4037 /* Enable the CPU */
4038 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
4039
4040 /*
4041 * Lock the CPU because we don't know if the guest will use it or not.
4042 * Prevents ejection while the CPU is still used
4043 */
4044 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
4045 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
4046 pThis->u32CpuEvent = iLUN;
4047
4048 /* Notify the guest */
4049 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4050 }
4051 }
4052 DEVACPI_UNLOCK(pDevIns, pThis);
4053 return rc;
4054}
4055
4056/**
4057 * Detach notification.
4058 *
4059 * @param pDevIns The device instance.
4060 * @param iLUN The logical unit which is being detached.
4061 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4062 */
4063static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4064{
4065 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4066
4067 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4068
4069 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4070 ("Hot-plug flag is not set\n"));
4071
4072 /* Check if it was already detached */
4073 DEVACPI_LOCK_R3(pDevIns, pThis);
4074 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4075 {
4076 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
4077 {
4078 /* Disable the CPU */
4079 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
4080 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
4081 pThis->u32CpuEvent = iLUN;
4082
4083 /* Notify the guest */
4084 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4085 }
4086 else
4087 AssertMsgFailed(("CPU is still locked by the guest\n"));
4088 }
4089 DEVACPI_UNLOCK(pDevIns, pThis);
4090}
4091
4092/**
4093 * @interface_method_impl{PDMDEVREG,pfnResume}
4094 */
4095static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
4096{
4097 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4098 if (pThis->fSetWakeupOnResume)
4099 {
4100 Log(("acpiResume: setting WAK_STS\n"));
4101 pThis->fSetWakeupOnResume = false;
4102 pThis->pm1a_sts |= WAK_STS;
4103 }
4104}
4105
4106/**
4107 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
4108 */
4109static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
4110{
4111 RT_NOREF(enmCtx);
4112 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4113 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4114 acpiR3PlantTables(pDevIns, pThis, pThisCC);
4115}
4116
4117/**
4118 * @interface_method_impl{PDMDEVREG,pfnReset}
4119 */
4120static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
4121{
4122 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4123 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4124
4125 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
4126 acpiSetIrq(pDevIns, 0);
4127
4128 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4129 pThis->pm1a_en = 0;
4130 pThis->pm1a_sts = 0;
4131 pThis->pm1a_ctl = 0;
4132 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4133 pThis->uPmTimerVal = 0;
4134 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4135 pThis->uPmTimeOld = pThis->uPmTimerVal;
4136 pThis->uBatteryIndex = 0;
4137 pThis->uSystemInfoIndex = 0;
4138 pThis->gpe0_en = 0;
4139 pThis->gpe0_sts = 0;
4140 pThis->uSleepState = 0;
4141 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4142
4143 /* Real device behavior is resetting only the PM controller state,
4144 * but we're additionally doing the job of the BIOS. */
4145 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
4146 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4147
4148 /* Reset SMBus base and PCI config space in addition to the SMBus controller
4149 * state. Real device behavior is only the SMBus controller state reset,
4150 * but we're additionally doing the job of the BIOS. */
4151 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
4152 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4153 acpiR3SMBusResetDevice(pThis);
4154}
4155
4156/**
4157 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4158 */
4159static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
4160{
4161 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4162 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4163 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4164
4165 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4166 {
4167 if (pThisCC->apu8CustBin[i])
4168 {
4169 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
4170 pThisCC->apu8CustBin[i] = NULL;
4171 }
4172 }
4173 return VINF_SUCCESS;
4174}
4175
4176/**
4177 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4178 */
4179static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4180{
4181 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4182 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4183 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4184 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4185
4186 /*
4187 * Init data and set defaults.
4188 */
4189 /** @todo move more of the code up! */
4190
4191 pThisCC->pDevIns = pDevIns;
4192 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
4193 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
4194 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
4195 pThis->u32CpuEventType = 0;
4196 pThis->u32CpuEvent = UINT32_C(0xffffffff);
4197
4198 /* The first CPU can't be attached/detached */
4199 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
4200 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
4201
4202 /* IBase */
4203 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
4204 /* IACPIPort */
4205 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
4206 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
4207 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
4208 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
4209 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
4210 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
4211 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
4212
4213 /*
4214 * Set the default critical section to NOP (related to the PM timer).
4215 */
4216 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4217 AssertRCReturn(rc, rc);
4218
4219 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
4220 AssertRCReturn(rc, rc);
4221
4222 /*
4223 * Validate and read the configuration.
4224 */
4225 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
4226 "IOAPIC"
4227 "|NumCPUs"
4228 "|HpetEnabled"
4229 "|McfgEnabled"
4230 "|McfgBase"
4231 "|McfgLength"
4232 "|PciPref64Enabled"
4233 "|PciPref64LimitGB"
4234 "|SmcEnabled"
4235 "|FdcEnabled"
4236 "|ShowRtc"
4237 "|ShowCpu"
4238 "|NicPciAddress"
4239 "|AudioPciAddress"
4240 "|NvmePciAddress"
4241 "|IocPciAddress"
4242 "|HostBusPciAddress"
4243 "|EnableSuspendToDisk"
4244 "|PowerS1Enabled"
4245 "|PowerS4Enabled"
4246 "|CpuHotPlug"
4247 "|AmlFilePath"
4248 "|Serial0IoPortBase"
4249 "|Serial1IoPortBase"
4250 "|Serial2IoPortBase"
4251 "|Serial3IoPortBase"
4252 "|Serial0Irq"
4253 "|Serial1Irq"
4254 "|Serial2Irq"
4255 "|Serial3Irq"
4256 "|AcpiOemId"
4257 "|AcpiCreatorId"
4258 "|AcpiCreatorRev"
4259 "|CustomTable"
4260 "|CustomTable0"
4261 "|CustomTable1"
4262 "|CustomTable2"
4263 "|CustomTable3"
4264 "|Parallel0IoPortBase"
4265 "|Parallel1IoPortBase"
4266 "|Parallel0Irq"
4267 "|Parallel1Irq"
4268 "|IommuIntelEnabled"
4269 "|IommuAmdEnabled"
4270 "|IommuPciAddress"
4271 "|SbIoApicPciAddress"
4272 "|TpmMode"
4273 "|TpmMmioAddress"
4274 "|SsdtTpmFilePath"
4275 , "");
4276
4277 /* query whether we are supposed to present an IOAPIC */
4278 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
4279 if (RT_FAILURE(rc))
4280 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
4281
4282 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
4283 if (RT_FAILURE(rc))
4284 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
4285
4286 /* query whether we are supposed to present an FDC controller */
4287 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
4288 if (RT_FAILURE(rc))
4289 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
4290
4291 /* query whether we are supposed to present HPET */
4292 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
4293 if (RT_FAILURE(rc))
4294 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
4295 /* query MCFG configuration */
4296 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
4297 if (RT_FAILURE(rc))
4298 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4299 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4300 if (RT_FAILURE(rc))
4301 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4302 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4303
4304 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4305 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4306 if (RT_FAILURE(rc))
4307 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4308
4309 /* query the limit of the the 64-bit prefetchable memory window */
4310 uint64_t u64PciPref64MaxGB;
4311 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4312 if (RT_FAILURE(rc))
4313 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4314 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4315
4316 /* query whether we are supposed to present SMC */
4317 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4318 if (RT_FAILURE(rc))
4319 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4320
4321 /* query whether we are supposed to present RTC object */
4322 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4323 if (RT_FAILURE(rc))
4324 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4325
4326 /* query whether we are supposed to present CPU objects */
4327 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4328 if (RT_FAILURE(rc))
4329 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4330
4331 /* query primary NIC PCI address (GIGE) */
4332 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4333 if (RT_FAILURE(rc))
4334 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4335
4336 /* query HD Audio PCI address (HDAA) */
4337 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4338 if (RT_FAILURE(rc))
4339 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4340
4341 /* query NVMe PCI address (NVMA) */
4342 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4343 if (RT_FAILURE(rc))
4344 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4345
4346 /* query IO controller (southbridge) PCI address */
4347 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4348 if (RT_FAILURE(rc))
4349 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4350
4351 /* query host bus controller PCI address */
4352 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4353 if (RT_FAILURE(rc))
4354 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4355
4356 /* query whether S1 power state should be exposed */
4357 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4358 if (RT_FAILURE(rc))
4359 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4360
4361 /* query whether S4 power state should be exposed */
4362 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4363 if (RT_FAILURE(rc))
4364 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4365
4366 /* query whether S1 power state should save the VM state */
4367 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4368 if (RT_FAILURE(rc))
4369 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4370
4371 /* query whether we are allow CPU hot plugging */
4372 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4373 if (RT_FAILURE(rc))
4374 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4375
4376 /* query serial info */
4377 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4378 if (RT_FAILURE(rc))
4379 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4380
4381 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4382 if (RT_FAILURE(rc))
4383 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4384
4385 /* Serial 1 is enabled, get config data */
4386 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4387 if (RT_FAILURE(rc))
4388 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4389
4390 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4391 if (RT_FAILURE(rc))
4392 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4393
4394 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4395 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4396 if (RT_FAILURE(rc))
4397 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4398
4399 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4400 if (RT_FAILURE(rc))
4401 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4402
4403 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4404 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4405 if (RT_FAILURE(rc))
4406 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4407
4408 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4409 if (RT_FAILURE(rc))
4410 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4411 /*
4412 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4413 * the corresponding parallel port is not enabled.
4414 */
4415 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4416 if (RT_FAILURE(rc))
4417 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4418
4419 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4420 if (RT_FAILURE(rc))
4421 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4422
4423 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4424 if (RT_FAILURE(rc))
4425 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4426
4427 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4428 if (RT_FAILURE(rc))
4429 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4430
4431#ifdef VBOX_WITH_IOMMU_AMD
4432 /* Query whether an IOMMU (AMD) is enabled. */
4433 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommuAmd, false);
4434 if (RT_FAILURE(rc))
4435 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdEnabled\""));
4436
4437 if (pThis->fUseIommuAmd)
4438 {
4439 /* Query IOMMU AMD address (IOMA). */
4440 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4441 if (RT_FAILURE(rc))
4442 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4443
4444 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4445 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4446 if (RT_FAILURE(rc))
4447 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4448
4449 /* Warn if the IOMMU Address is at the PCI host-bridge address. */
4450 /** @todo We should eventually not assign the IOMMU at this address, see
4451 * @bugref{9654#c53}. */
4452 if (!pThis->u32IommuPciAddress)
4453 LogRel(("ACPI: Warning! AMD IOMMU assigned the PCI host bridge address.\n"));
4454
4455 /* Warn if the IOAPIC is not at the expected address. */
4456 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4457 {
4458 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4459 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4460 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4461 }
4462 }
4463#endif
4464
4465#ifdef VBOX_WITH_IOMMU_INTEL
4466 /* Query whether an IOMMU (Intel) is enabled. */
4467 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuIntelEnabled", &pThis->fUseIommuIntel, false);
4468 if (RT_FAILURE(rc))
4469 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuIntelEnabled\""));
4470
4471 if (pThis->fUseIommuIntel)
4472 {
4473 /* Query IOMMU Intel address. */
4474 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4475 if (RT_FAILURE(rc))
4476 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4477
4478 /* Get the reserved I/O APIC PCI address (required when an Intel IOMMU is configured). */
4479 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4480 if (RT_FAILURE(rc))
4481 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4482
4483 /* Warn if the IOAPIC is not at the expected address. */
4484 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4485 {
4486 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an Intel IOMMU is present.\n",
4487 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4488 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4489 }
4490 }
4491#endif
4492
4493 /* Don't even think about enabling an Intel and an AMD IOMMU at the same time! */
4494 if ( pThis->fUseIommuAmd
4495 && pThis->fUseIommuIntel)
4496 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Cannot enable Intel and AMD IOMMU simultaneously!"));
4497
4498#ifdef VBOX_WITH_TPM
4499 char szTpmMode[64]; RT_ZERO(szTpmMode);
4500
4501 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "TpmMode", &szTpmMode[0], RT_ELEMENTS(szTpmMode) - 1, "disabled");
4502 if (RT_FAILURE(rc))
4503 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMode\""));
4504
4505 if (!RTStrICmp(szTpmMode, "disabled"))
4506 pThis->enmTpmMode = ACPITPMMODE_DISABLED;
4507 else if (!RTStrICmp(szTpmMode, "tis1.2"))
4508 pThis->enmTpmMode = ACPITPMMODE_TIS_1_2;
4509 else if (!RTStrICmp(szTpmMode, "crb2.0"))
4510 pThis->enmTpmMode = ACPITPMMODE_CRB_2_0;
4511 else if (!RTStrICmp(szTpmMode, "fifo2.0"))
4512 pThis->enmTpmMode = ACPITPMMODE_FIFO_2_0;
4513 else
4514 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER, N_("Configuration error: Value of \"TpmMode\" is not known"));
4515
4516 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "TpmMmioAddress", (uint64_t *)&pThis->GCPhysTpmMmio, ACPI_TPM_MMIO_BASE_DEFAULT);
4517 if (RT_FAILURE(rc))
4518 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMmioAddress\""));
4519#endif
4520
4521 /* Try to attach the other CPUs */
4522 for (unsigned i = 1; i < pThis->cCpus; i++)
4523 {
4524 if (pThis->fCpuHotPlug)
4525 {
4526 PPDMIBASE IBaseTmp;
4527 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4528
4529 if (RT_SUCCESS(rc))
4530 {
4531 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4532 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4533 Log(("acpi: Attached CPU %u\n", i));
4534 }
4535 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4536 Log(("acpi: CPU %u not attached yet\n", i));
4537 else
4538 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4539 }
4540 else
4541 {
4542 /* CPU is always attached if hot-plug is not enabled. */
4543 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4544 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4545 }
4546 }
4547
4548 char szOemId[16];
4549 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4550 if (RT_FAILURE(rc))
4551 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4552 size_t cchOemId = strlen(szOemId);
4553 if (cchOemId > 6)
4554 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4555 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4556 memcpy(pThis->au8OemId, szOemId, cchOemId);
4557
4558 char szCreatorId[16];
4559 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4560 if (RT_FAILURE(rc))
4561 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4562 size_t cchCreatorId = strlen(szCreatorId);
4563 if (cchCreatorId > 4)
4564 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4565 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4566 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4567
4568 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4569 if (RT_FAILURE(rc))
4570 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4571
4572 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4573
4574 /*
4575 * Load custom ACPI tables.
4576 */
4577 /* Total space available for custom ACPI tables */
4578 /** @todo define as appropriate, remove as a magic number, and document
4579 * limitation in product manual */
4580 uint32_t cbBufAvail = 3072;
4581 pThis->cCustTbls = 0;
4582
4583 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4584 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4585 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4586 {
4587 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4588
4589 /*
4590 * Get the custom table binary file name.
4591 */
4592 char *pszCustBinFile = NULL;
4593 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4594 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4595 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4596 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4597 {
4598 rc = VINF_SUCCESS;
4599 pszCustBinFile = NULL;
4600 }
4601 else if (RT_FAILURE(rc))
4602 return PDMDEV_SET_ERROR(pDevIns, rc,
4603 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4604 else if (!*pszCustBinFile)
4605 {
4606 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4607 pszCustBinFile = NULL;
4608 }
4609
4610 /*
4611 * Determine the custom table binary size, open specified file in the process.
4612 */
4613 if (pszCustBinFile)
4614 {
4615 uint32_t idxCust = pThis->cCustTbls;
4616 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4617 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4618 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4619 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4620 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4621 if (RT_FAILURE(rc))
4622 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4623 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4624
4625 /* Update custom OEM attributes based on custom table */
4626 /** @todo is it intended for custom tables to overwrite user provided values above? */
4627 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4628 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4629 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4630 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4631 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4632 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4633
4634 pThis->cCustTbls++;
4635 Assert(pThis->cCustTbls <= MAX_CUST_TABLES);
4636 }
4637 }
4638
4639 /* Set default PM port base */
4640 pThis->uPmIoPortBase = PM_PORT_BASE;
4641
4642 /* Set default SMBus port base */
4643 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4644
4645 /*
4646 * FDC and SMC try to use the same non-shareable interrupt (6),
4647 * enable only one device.
4648 */
4649 if (pThis->fUseSmc)
4650 pThis->fUseFdc = false;
4651
4652 /*
4653 * Plant ACPI tables.
4654 */
4655 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4656 * au8RSDPPage here. However, there should be no harm in doing it
4657 * twice, so the lazy bird is taking the quick way out for now. */
4658 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4659 if (!GCPhysRsdp)
4660 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4661
4662 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4663 AssertRCReturn(rc, rc);
4664
4665 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4666 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4667 AssertRCReturn(rc, rc);
4668
4669 /*
4670 * Create the PM I/O ports. These can be unmapped and remapped.
4671 */
4672 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4673 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4674 AssertRCReturn(rc, rc);
4675 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4676 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4677 AssertRCReturn(rc, rc);
4678 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4679 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4680 AssertRCReturn(rc, rc);
4681 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4682 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4683 AssertRCReturn(rc, rc);
4684 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4685 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4686 AssertRCReturn(rc, rc);
4687 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4688 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4689 AssertRCReturn(rc, rc);
4690 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4691 AssertRCReturn(rc, rc);
4692
4693 /*
4694 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4695 */
4696 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4697 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4698 AssertRCReturn(rc, rc);
4699 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4700 AssertRCReturn(rc, rc);
4701
4702 /*
4703 * Create and map the fixed I/O ports.
4704 */
4705 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4706 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4707 AssertRCReturn(rc, rc);
4708#ifdef DEBUG_ACPI
4709 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4710 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4711 AssertRCReturn(rc, rc);
4712 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4713 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4714 AssertRCReturn(rc, rc);
4715#endif
4716 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4717 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4718 AssertRCReturn(rc, rc);
4719 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4720 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4721 AssertRCReturn(rc, rc);
4722 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4723 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4724 AssertRCReturn(rc, rc);
4725 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4726 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4727 AssertRCReturn(rc, rc);
4728 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4729 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4730 AssertRCReturn(rc, rc);
4731
4732 /*
4733 * Create the PM timer.
4734 */
4735 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4736 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "ACPI PM", &pThis->hPmTimer);
4737 AssertRCReturn(rc, rc);
4738
4739 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4740 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4741 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4742 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4743
4744 /*
4745 * Set up the PCI device.
4746 */
4747 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4748 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4749
4750 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4751 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4752
4753 /* See p. 50 of PIIX4 manual */
4754 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4755 PDMPciDevSetStatus(pPciDev, 0x0280);
4756
4757 PDMPciDevSetRevisionId(pPciDev, 0x08);
4758
4759 PDMPciDevSetClassProg(pPciDev, 0x00);
4760 PDMPciDevSetClassSub(pPciDev, 0x80);
4761 PDMPciDevSetClassBase(pPciDev, 0x06);
4762
4763 PDMPciDevSetHeaderType(pPciDev, 0x80);
4764
4765 PDMPciDevSetBIST(pPciDev, 0x00);
4766
4767 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4768 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4769
4770 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4771 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4772
4773 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4774 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4775 acpiR3SMBusResetDevice(pThis);
4776
4777 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4778 AssertRCReturn(rc, rc);
4779
4780 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4781 AssertRCReturn(rc, rc);
4782
4783 /*
4784 * Register the saved state.
4785 */
4786 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4787 AssertRCReturn(rc, rc);
4788
4789 /*
4790 * Get the corresponding connector interface
4791 */
4792 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4793 if (RT_SUCCESS(rc))
4794 {
4795 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4796 if (!pThisCC->pDrv)
4797 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4798 }
4799 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4800 {
4801 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4802 rc = VINF_SUCCESS;
4803 }
4804 else
4805 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4806
4807 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4808
4809 return rc;
4810}
4811
4812#else /* !IN_RING3 */
4813
4814/**
4815 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4816 */
4817static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4818{
4819 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4820 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4821
4822 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4823 AssertRCReturn(rc, rc);
4824
4825 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4826 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4827 AssertRCReturn(rc, rc);
4828
4829 return VINF_SUCCESS;
4830}
4831
4832#endif /* !IN_RING3 */
4833
4834/**
4835 * The device registration structure.
4836 */
4837const PDMDEVREG g_DeviceACPI =
4838{
4839 /* .u32Version = */ PDM_DEVREG_VERSION,
4840 /* .uReserved0 = */ 0,
4841 /* .szName = */ "acpi",
4842 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4843 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4844 /* .cMaxInstances = */ ~0U,
4845 /* .uSharedVersion = */ 42,
4846 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4847 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4848 /* .cbInstanceRC = */ 0,
4849 /* .cMaxPciDevices = */ 1,
4850 /* .cMaxMsixVectors = */ 0,
4851 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4852#if defined(IN_RING3)
4853 /* .pszRCMod = */ "VBoxDDRC.rc",
4854 /* .pszR0Mod = */ "VBoxDDR0.r0",
4855 /* .pfnConstruct = */ acpiR3Construct,
4856 /* .pfnDestruct = */ acpiR3Destruct,
4857 /* .pfnRelocate = */ NULL,
4858 /* .pfnMemSetup = */ acpiR3MemSetup,
4859 /* .pfnPowerOn = */ NULL,
4860 /* .pfnReset = */ acpiR3Reset,
4861 /* .pfnSuspend = */ NULL,
4862 /* .pfnResume = */ acpiR3Resume,
4863 /* .pfnAttach = */ acpiR3Attach,
4864 /* .pfnDetach = */ acpiR3Detach,
4865 /* .pfnQueryInterface = */ NULL,
4866 /* .pfnInitComplete = */ NULL,
4867 /* .pfnPowerOff = */ NULL,
4868 /* .pfnSoftReset = */ NULL,
4869 /* .pfnReserved0 = */ NULL,
4870 /* .pfnReserved1 = */ NULL,
4871 /* .pfnReserved2 = */ NULL,
4872 /* .pfnReserved3 = */ NULL,
4873 /* .pfnReserved4 = */ NULL,
4874 /* .pfnReserved5 = */ NULL,
4875 /* .pfnReserved6 = */ NULL,
4876 /* .pfnReserved7 = */ NULL,
4877#elif defined(IN_RING0)
4878 /* .pfnEarlyConstruct = */ NULL,
4879 /* .pfnConstruct = */ acpiRZConstruct,
4880 /* .pfnDestruct = */ NULL,
4881 /* .pfnFinalDestruct = */ NULL,
4882 /* .pfnRequest = */ NULL,
4883 /* .pfnReserved0 = */ NULL,
4884 /* .pfnReserved1 = */ NULL,
4885 /* .pfnReserved2 = */ NULL,
4886 /* .pfnReserved3 = */ NULL,
4887 /* .pfnReserved4 = */ NULL,
4888 /* .pfnReserved5 = */ NULL,
4889 /* .pfnReserved6 = */ NULL,
4890 /* .pfnReserved7 = */ NULL,
4891#elif defined(IN_RC)
4892 /* .pfnConstruct = */ acpiRZConstruct,
4893 /* .pfnReserved0 = */ NULL,
4894 /* .pfnReserved1 = */ NULL,
4895 /* .pfnReserved2 = */ NULL,
4896 /* .pfnReserved3 = */ NULL,
4897 /* .pfnReserved4 = */ NULL,
4898 /* .pfnReserved5 = */ NULL,
4899 /* .pfnReserved6 = */ NULL,
4900 /* .pfnReserved7 = */ NULL,
4901#else
4902# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4903#endif
4904 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4905};
4906
4907#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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