VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 91375

Last change on this file since 91375 was 91238, checked in by vboxsync, 3 years ago

DevACPI: Use ASSERT_GUEST instead of Assert in a couple of place; fixed a PDMDevHlpDBGFStop.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 188.7 KB
Line 
1/* $Id: DevACPI.cpp 91238 2021-09-14 20:45:35Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/dbgftrace.h>
26#include <VBox/vmm/vmcpuset.h>
27#include <VBox/AssertGuest.h>
28#include <VBox/log.h>
29#include <VBox/param.h>
30#include <VBox/pci.h>
31#include <iprt/assert.h>
32#include <iprt/asm.h>
33#include <iprt/asm-math.h>
34#include <iprt/file.h>
35#ifdef IN_RING3
36# include <iprt/alloc.h>
37# include <iprt/string.h>
38# include <iprt/uuid.h>
39#endif /* IN_RING3 */
40#ifdef VBOX_WITH_IOMMU_AMD
41# include <VBox/iommu-amd.h>
42#endif
43#ifdef VBOX_WITH_IOMMU_INTEL
44# include <VBox/iommu-intel.h>
45#endif
46
47#include "VBoxDD.h"
48#ifdef VBOX_WITH_IOMMU_AMD
49# include "../Bus/DevIommuAmd.h"
50#endif
51#ifdef VBOX_WITH_IOMMU_INTEL
52# include "../Bus/DevIommuIntel.h"
53#endif
54
55#ifdef LOG_ENABLED
56# define DEBUG_ACPI
57#endif
58
59
60/*********************************************************************************************************************************
61* Defined Constants And Macros *
62*********************************************************************************************************************************/
63#ifdef IN_RING3
64/** Locks the device state, ring-3 only. */
65# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
66 do { \
67 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
68 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSect, rcLock); \
69 } while (0)
70#endif
71/** Unlocks the device state (all contexts). */
72#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
73 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
74
75
76#define DEBUG_HEX 0x3000
77#define DEBUG_CHR 0x3001
78
79/** PM Base Address PCI config space offset */
80#define PMBA 0x40
81/** PM Miscellaneous Power Management PCI config space offset */
82#define PMREGMISC 0x80
83
84#define PM_TMR_FREQ 3579545
85/** Default base for PM PIIX4 device */
86#define PM_PORT_BASE 0x4000
87/* Port offsets in PM device */
88enum
89{
90 PM1a_EVT_OFFSET = 0x00,
91 PM1b_EVT_OFFSET = -1, /**< not supported */
92 PM1a_CTL_OFFSET = 0x04,
93 PM1b_CTL_OFFSET = -1, /**< not supported */
94 PM2_CTL_OFFSET = -1, /**< not supported */
95 PM_TMR_OFFSET = 0x08,
96 GPE0_OFFSET = 0x20,
97 GPE1_OFFSET = -1 /**< not supported */
98};
99
100/* Maximum supported number of custom ACPI tables */
101#define MAX_CUST_TABLES 4
102
103/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
104#define PM_TMR_32BIT
105
106#define BAT_INDEX 0x00004040
107#define BAT_DATA 0x00004044
108#define SYSI_INDEX 0x00004048
109#define SYSI_DATA 0x0000404c
110#define ACPI_RESET_BLK 0x00004050
111
112/* PM1x status register bits */
113#define TMR_STS RT_BIT(0)
114#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
115#define BM_STS RT_BIT(4)
116#define GBL_STS RT_BIT(5)
117#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
118#define PWRBTN_STS RT_BIT(8)
119#define SLPBTN_STS RT_BIT(9)
120#define RTC_STS RT_BIT(10)
121#define IGN_STS RT_BIT(11)
122#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
123#define WAK_STS RT_BIT(15)
124#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
125
126/* PM1x enable register bits */
127#define TMR_EN RT_BIT(0)
128#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
129#define GBL_EN RT_BIT(5)
130#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
131#define PWRBTN_EN RT_BIT(8)
132#define SLPBTN_EN RT_BIT(9)
133#define RTC_EN RT_BIT(10)
134#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
135#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
136#define IGN_EN 0
137
138/* PM1x control register bits */
139#define SCI_EN RT_BIT(0)
140#define BM_RLD RT_BIT(1)
141#define GBL_RLS RT_BIT(2)
142#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
143#define IGN_CNT RT_BIT(9)
144#define SLP_TYPx_SHIFT 10
145#define SLP_TYPx_MASK 7
146#define SLP_EN RT_BIT(13)
147#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
148#define RSR_CNT (RSR1_CNT | RSR2_CNT)
149
150#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
151
152enum
153{
154 BAT_STATUS_STATE = 0x00, /**< BST battery state */
155 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
156 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
157 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
158 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
159 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
160 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
161 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
162 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
163 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
164 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
165 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
166 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
167 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
168 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
169 BAT_INDEX_LAST
170};
171
172enum
173{
174 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
175 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
176};
177
178enum
179{
180 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
181 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
182 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
183 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
184 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
185 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
186 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
187 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
188 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
189 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
190 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
191 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
192 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
193 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
194 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
195 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
196 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
197 SYSTEM_INFO_INDEX_POWER_STATES = 17,
198 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
199 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
200 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
201 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
202 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
203 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
204 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
205 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
206 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
207 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
208 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
209 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
210 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
211 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
212 SYSTEM_INFO_INDEX_IOMMU_ADDRESS = 32, /**< IOMMU PCI address, or 0 */
213 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
214 SYSTEM_INFO_INDEX_END = 34,
215 SYSTEM_INFO_INDEX_INVALID = 0x80,
216 SYSTEM_INFO_INDEX_VALID = 0x200
217};
218
219#define AC_OFFLINE 0
220#define AC_ONLINE 1
221
222#define BAT_TECH_PRIMARY 1
223#define BAT_TECH_SECONDARY 2
224
225#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
226#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
227#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
228#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
229#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
230
231/** SMBus Base Address PCI config space offset */
232#define SMBBA 0x90
233/** SMBus Host Configuration PCI config space offset */
234#define SMBHSTCFG 0xd2
235/** SMBus Slave Command PCI config space offset */
236#define SMBSLVC 0xd3
237/** SMBus Slave Shadow Port 1 PCI config space offset */
238#define SMBSHDW1 0xd4
239/** SMBus Slave Shadow Port 2 PCI config space offset */
240#define SMBSHDW2 0xd5
241/** SMBus Revision Identification PCI config space offset */
242#define SMBREV 0xd6
243
244#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
245#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
246#define SMBHSTCFG_INTRSEL_SMI 0
247#define SMBHSTCFG_INTRSEL_IRQ9 4
248#define SMBHSTCFG_INTRSEL_SHIFT 1
249
250/** Default base for SMBus PIIX4 device */
251#define SMB_PORT_BASE 0x4100
252
253/** SMBus Host Status Register I/O offset */
254#define SMBHSTSTS_OFF 0x0000
255/** SMBus Slave Status Register I/O offset */
256#define SMBSLVSTS_OFF 0x0001
257/** SMBus Host Count Register I/O offset */
258#define SMBHSTCNT_OFF 0x0002
259/** SMBus Host Command Register I/O offset */
260#define SMBHSTCMD_OFF 0x0003
261/** SMBus Host Address Register I/O offset */
262#define SMBHSTADD_OFF 0x0004
263/** SMBus Host Data 0 Register I/O offset */
264#define SMBHSTDAT0_OFF 0x0005
265/** SMBus Host Data 1 Register I/O offset */
266#define SMBHSTDAT1_OFF 0x0006
267/** SMBus Block Data Register I/O offset */
268#define SMBBLKDAT_OFF 0x0007
269/** SMBus Slave Control Register I/O offset */
270#define SMBSLVCNT_OFF 0x0008
271/** SMBus Shadow Command Register I/O offset */
272#define SMBSHDWCMD_OFF 0x0009
273/** SMBus Slave Event Register I/O offset */
274#define SMBSLVEVT_OFF 0x000a
275/** SMBus Slave Data Register I/O offset */
276#define SMBSLVDAT_OFF 0x000c
277
278#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
279#define SMBHSTSTS_INTER RT_BIT(1)
280#define SMBHSTSTS_DEV_ERR RT_BIT(2)
281#define SMBHSTSTS_BUS_ERR RT_BIT(3)
282#define SMBHSTSTS_FAILED RT_BIT(4)
283#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
284
285#define SMBSLVSTS_WRITE_MASK 0x3c
286
287#define SMBHSTCNT_INTEREN RT_BIT(0)
288#define SMBHSTCNT_KILL RT_BIT(1)
289#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
290#define SMBHSTCNT_START RT_BIT(6)
291#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
292
293#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
294
295
296/*********************************************************************************************************************************
297* Structures and Typedefs *
298*********************************************************************************************************************************/
299/**
300 * The TPM mode configured.
301 */
302typedef enum ACPITPMMODE
303{
304 ACPITPMMODE_INVALID = 0,
305 ACPITPMMODE_DISABLED,
306 ACPITPMMODE_TIS_1_2,
307 ACPITPMMODE_CRB_2_0,
308 ACPITPMMODE_FIFO_2_0,
309 ACPITPMMODE_32BIT_HACK = 0x7fffffff
310} ACPITPMMODE;
311
312
313/**
314 * The shared ACPI device state.
315 */
316typedef struct ACPISTATE
317{
318 /** Critical section protecting the ACPI state. */
319 PDMCRITSECT CritSect;
320
321 uint16_t pm1a_en;
322 uint16_t pm1a_sts;
323 uint16_t pm1a_ctl;
324 /** Number of logical CPUs in guest */
325 uint16_t cCpus;
326
327 uint64_t u64PmTimerInitial;
328 /** The PM timer. */
329 TMTIMERHANDLE hPmTimer;
330 /* PM Timer last calculated value */
331 uint32_t uPmTimerVal;
332 uint32_t Alignment0;
333
334 uint32_t gpe0_en;
335 uint32_t gpe0_sts;
336
337 uint32_t uBatteryIndex;
338 uint32_t au8BatteryInfo[13];
339
340 uint32_t uSystemInfoIndex;
341 uint32_t u32Alignment0;
342 uint64_t u64RamSize;
343 /** Offset of the 64-bit prefetchable memory window. */
344 uint64_t u64PciPref64Min;
345 /** Limit of the 64-bit prefetchable memory window. */
346 uint64_t u64PciPref64Max;
347 /** The number of bytes below 4GB. */
348 uint32_t cbRamLow;
349
350 /** Current ACPI S* state. We support S0 and S5. */
351 uint32_t uSleepState;
352 uint8_t au8RSDPPage[0x1000];
353 /** This is a workaround for incorrect index field handling by Intels ACPICA.
354 * The system info _INI method writes to offset 0x200. We either observe a
355 * write request to index 0x80 (in that case we don't change the index) or a
356 * write request to offset 0x200 (in that case we divide the index value by
357 * 4. Note that the _STA method is sometimes called prior to the _INI method
358 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
359 * acpiR3BatIndexWrite() for handling this. */
360 uint8_t u8IndexShift;
361 /** provide an I/O-APIC */
362 uint8_t u8UseIOApic;
363 /** provide a floppy controller */
364 bool fUseFdc;
365 /** If High Precision Event Timer device should be supported */
366 bool fUseHpet;
367 /** If System Management Controller device should be supported */
368 bool fUseSmc;
369 /** the guest handled the last power button event */
370 bool fPowerButtonHandled;
371 /** If ACPI CPU device should be shown */
372 bool fShowCpu;
373 /** If Real Time Clock ACPI object to be shown */
374 bool fShowRtc;
375 /** I/O port address of PM device. */
376 RTIOPORT uPmIoPortBase;
377 /** I/O port address of SMBus device. */
378 RTIOPORT uSMBusIoPortBase;
379 /** Which CPU to check for the locked status. */
380 uint32_t idCpuLockCheck;
381 /** Array of flags of attached CPUs */
382 VMCPUSET CpuSetAttached;
383 /** Mask of locked CPUs (used by the guest). */
384 VMCPUSET CpuSetLocked;
385 /** The CPU event type. */
386 uint32_t u32CpuEventType;
387 /** The CPU id affected. */
388 uint32_t u32CpuEvent;
389 /** Flag whether CPU hot plugging is enabled. */
390 bool fCpuHotPlug;
391 /** If MCFG ACPI table shown to the guest */
392 bool fUseMcfg;
393 /** if the 64-bit prefetchable memory window is shown to the guest */
394 bool fPciPref64Enabled;
395 /** If the IOMMU (AMD) device should be enabled */
396 bool fUseIommuAmd;
397 /** If the IOMMU (Intel) device should be enabled */
398 bool fUseIommuIntel;
399 /** Padding. */
400 bool afPadding0[3];
401 /** Primary NIC PCI address. */
402 uint32_t u32NicPciAddress;
403 /** HD Audio PCI address. */
404 uint32_t u32AudioPciAddress;
405 /** Primary NVMe controller PCI address. */
406 uint32_t u32NvmePciAddress;
407 /** Flag whether S1 power state is enabled. */
408 bool fS1Enabled;
409 /** Flag whether S4 power state is enabled. */
410 bool fS4Enabled;
411 /** Flag whether S1 triggers a state save. */
412 bool fSuspendToSavedState;
413 /** Flag whether to set WAK_STS on resume (restore included). */
414 bool fSetWakeupOnResume;
415 /** PCI address of the IO controller device. */
416 uint32_t u32IocPciAddress;
417 /** PCI address of the host bus controller device. */
418 uint32_t u32HbcPciAddress;
419 /** PCI address of the IOMMU device. */
420 uint32_t u32IommuPciAddress;
421 /** PCI address of the southbridge I/O APIC device. */
422 uint32_t u32SbIoApicPciAddress;
423
424 /** Physical address of PCI config space MMIO region */
425 uint64_t u64PciConfigMMioAddress;
426 /** Length of PCI config space MMIO region */
427 uint64_t u64PciConfigMMioLength;
428 /** Serial 0 IRQ number */
429 uint8_t uSerial0Irq;
430 /** Serial 1 IRQ number */
431 uint8_t uSerial1Irq;
432 /** Serial 2 IRQ number */
433 uint8_t uSerial2Irq;
434 /** Serial 3 IRQ number */
435 uint8_t uSerial3Irq;
436 /** Serial 0 IO port base */
437 RTIOPORT uSerial0IoPortBase;
438 /** Serial 1 IO port base */
439 RTIOPORT uSerial1IoPortBase;
440 /** Serial 2 IO port base */
441 RTIOPORT uSerial2IoPortBase;
442 /** Serial 3 IO port base */
443 RTIOPORT uSerial3IoPortBase;
444
445 /** @name Parallel port config bits
446 * @{ */
447 /** Parallel 0 IO port base */
448 RTIOPORT uParallel0IoPortBase;
449 /** Parallel 1 IO port base */
450 RTIOPORT uParallel1IoPortBase;
451 /** Parallel 0 IRQ number */
452 uint8_t uParallel0Irq;
453 /** Parallel 1 IRQ number */
454 uint8_t uParallel1Irq;
455 /** @} */
456
457#ifdef VBOX_WITH_TPM
458 /** @name TPM config bits
459 * @{ */
460 /** The ACPI TPM mode configured. */
461 ACPITPMMODE enmTpmMode;
462 /** The MMIO register area base address. */
463 RTGCPHYS GCPhysTpmMmio;
464 /** @} */
465#endif
466
467 /** Number of custom ACPI tables */
468 uint8_t cCustTbls;
469 /** ACPI OEM ID */
470 uint8_t au8OemId[6];
471 /** ACPI Crator ID */
472 uint8_t au8CreatorId[4];
473 uint8_t abAlignment2[3];
474 /** ACPI Crator Rev */
475 uint32_t u32CreatorRev;
476 /** ACPI custom OEM Tab ID */
477 uint8_t au8OemTabId[8];
478 /** ACPI custom OEM Rev */
479 uint32_t u32OemRevision;
480
481 /** SMBus Host Status Register */
482 uint8_t u8SMBusHstSts;
483 /** SMBus Slave Status Register */
484 uint8_t u8SMBusSlvSts;
485 /** SMBus Host Control Register */
486 uint8_t u8SMBusHstCnt;
487 /** SMBus Host Command Register */
488 uint8_t u8SMBusHstCmd;
489 /** SMBus Host Address Register */
490 uint8_t u8SMBusHstAdd;
491 /** SMBus Host Data 0 Register */
492 uint8_t u8SMBusHstDat0;
493 /** SMBus Host Data 1 Register */
494 uint8_t u8SMBusHstDat1;
495 /** SMBus Slave Control Register */
496 uint8_t u8SMBusSlvCnt;
497 /** SMBus Slave Event Register */
498 uint16_t u16SMBusSlvEvt;
499 /** SMBus Slave Data Register */
500 uint16_t u16SMBusSlvDat;
501 /** SMBus Shadow Command Register */
502 uint8_t u8SMBusShdwCmd;
503 /** SMBus Host Block Index */
504 uint8_t u8SMBusBlkIdx;
505 uint8_t abAlignment3[2];
506 /** SMBus Host Block Data Buffer */
507 uint8_t au8SMBusBlkDat[32];
508
509 /** @todo DEBUGGING */
510 uint32_t uPmTimeOld;
511 uint32_t uPmTimeA;
512 uint32_t uPmTimeB;
513 uint32_t Alignment5;
514
515 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
516 * @{ */
517 IOMIOPORTHANDLE hIoPortPm1aEn;
518 IOMIOPORTHANDLE hIoPortPm1aSts;
519 IOMIOPORTHANDLE hIoPortPm1aCtl;
520 IOMIOPORTHANDLE hIoPortPmTimer;
521 IOMIOPORTHANDLE hIoPortGpe0En;
522 IOMIOPORTHANDLE hIoPortGpe0Sts;
523 /** @} */
524
525 /** SMBus I/O ports (mapped/unmapped). */
526 IOMIOPORTHANDLE hIoPortSMBus;
527
528 /** @name Fixed I/O ports
529 * @{ */
530 /** ACPI SMI I/O port. */
531 IOMIOPORTHANDLE hIoPortSmi;
532 /** ACPI Debug hex I/O port. */
533 IOMIOPORTHANDLE hIoPortDebugHex;
534 /** ACPI Debug char I/O port. */
535 IOMIOPORTHANDLE hIoPortDebugChar;
536 /** ACPI Battery status index I/O port. */
537 IOMIOPORTHANDLE hIoPortBatteryIndex;
538 /** ACPI Battery status data I/O port. */
539 IOMIOPORTHANDLE hIoPortBatteryData;
540 /** ACPI system info index I/O port. */
541 IOMIOPORTHANDLE hIoPortSysInfoIndex;
542 /** ACPI system info data I/O port. */
543 IOMIOPORTHANDLE hIoPortSysInfoData;
544 /** ACPI Reset I/O port. */
545 IOMIOPORTHANDLE hIoPortReset;
546 /** @} */
547
548} ACPISTATE;
549/** Pointer to the shared ACPI device state. */
550typedef ACPISTATE *PACPISTATE;
551
552
553
554/**
555 * The ring-3 ACPI device state.
556 */
557typedef struct ACPISTATER3
558{
559 /** ACPI port base interface. */
560 PDMIBASE IBase;
561 /** ACPI port interface. */
562 PDMIACPIPORT IACPIPort;
563 /** Pointer to the device instance so we can get our bearings from
564 * interface functions. */
565 PPDMDEVINSR3 pDevIns;
566
567 /** Pointer to the driver base interface. */
568 R3PTRTYPE(PPDMIBASE) pDrvBase;
569 /** Pointer to the driver connector interface. */
570 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
571
572 /** Custom ACPI tables binary data. */
573 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
574 /** The size of the custom table binary. */
575 uint64_t acbCustBin[MAX_CUST_TABLES];
576} ACPISTATER3;
577/** Pointer to the ring-3 ACPI device state. */
578typedef ACPISTATER3 *PACPISTATER3;
579
580
581#pragma pack(1)
582
583/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
584struct ACPIGENADDR
585{
586 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
587 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
588 uint8_t u8RegisterBitOffset; /**< bit offset of register */
589 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
590 uint64_t u64Address; /**< 64-bit address of register */
591};
592AssertCompileSize(ACPIGENADDR, 12);
593
594/** Root System Description Pointer */
595struct ACPITBLRSDP
596{
597 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
598 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
599 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
600 uint8_t u8Revision; /**< revision number, currently 2 */
601#define ACPI_REVISION 2 /**< ACPI 3.0 */
602 uint32_t u32RSDT; /**< phys addr of RSDT */
603 uint32_t u32Length; /**< bytes of this table */
604 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
605 uint8_t u8ExtChecksum; /**< checksum of entire table */
606 uint8_t u8Reserved[3]; /**< reserved */
607};
608AssertCompileSize(ACPITBLRSDP, 36);
609
610/** System Description Table Header */
611struct ACPITBLHEADER
612{
613 uint8_t au8Signature[4]; /**< table identifier */
614 uint32_t u32Length; /**< length of the table including header */
615 uint8_t u8Revision; /**< revision number */
616 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
617 uint8_t au8OemId[6]; /**< OEM-supplied string */
618 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
619 uint32_t u32OemRevision; /**< OEM-supplied revision number */
620 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
621 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
622};
623AssertCompileSize(ACPITBLHEADER, 36);
624
625/** Root System Description Table */
626struct ACPITBLRSDT
627{
628 ACPITBLHEADER header;
629 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
630};
631AssertCompileSize(ACPITBLRSDT, 40);
632
633/** Extended System Description Table */
634struct ACPITBLXSDT
635{
636 ACPITBLHEADER header;
637 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
638};
639AssertCompileSize(ACPITBLXSDT, 44);
640
641/** Fixed ACPI Description Table */
642struct ACPITBLFADT
643{
644 ACPITBLHEADER header;
645 uint32_t u32FACS; /**< phys. address of FACS */
646 uint32_t u32DSDT; /**< phys. address of DSDT */
647 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
648#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
649#define INT_MODEL_MULTIPLE_APIC 2
650 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
651 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
652#define SCI_INT 9
653 uint32_t u32SMICmd; /**< system port address of SMI command port */
654#define SMI_CMD 0x0000442e
655 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
656#define ACPI_ENABLE 0xa1
657 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
658#define ACPI_DISABLE 0xa0
659 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
660 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
661 state control responsibility */
662 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
663 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
664 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
665 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
666 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
667 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
668 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
669 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
670 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
671 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
672 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
673 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
674 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
675#define GPE0_BLK_LEN 2
676 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
677#define GPE1_BLK_LEN 0
678 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
679#define GPE1_BASE 0
680 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
681 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
682#define P_LVL2_LAT 101 /**< C2 state not supported */
683 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
684#define P_LVL3_LAT 1001 /**< C3 state not supported */
685 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
686 lines from any processors memory caches */
687#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
688 uint16_t u16FlushStride; /**< cache line width */
689#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
690 uint8_t u8DutyOffset;
691 uint8_t u8DutyWidth;
692 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
693 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
694 uint8_t u8Century; /**< RTC CMOS RAM index of century */
695 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
696#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
697 (COM too?) */
698#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
699#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
700#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
701#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
702 uint8_t u8Must0_0; /**< must be 0 */
703 uint32_t u32Flags; /**< fixed feature flags */
704#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
705#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
706#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
707#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
708#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
709#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
710#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
711#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
712#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
713#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
714#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
715#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
716#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
717#define FADT_FL_CPU_SW_SLP RT_BIT(13)
718#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
719#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
720#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
721#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
722#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
723#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
724
725/* PM Timer mask and msb */
726#ifndef PM_TMR_32BIT
727#define TMR_VAL_MSB 0x800000
728#define TMR_VAL_MASK 0xffffff
729#undef FADT_FL_TMR_VAL_EXT
730#define FADT_FL_TMR_VAL_EXT 0
731#else
732#define TMR_VAL_MSB 0x80000000
733#define TMR_VAL_MASK 0xffffffff
734#endif
735
736 /** Start of the ACPI 2.0 extension. */
737 ACPIGENADDR ResetReg; /**< ext addr of reset register */
738 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
739#define ACPI_RESET_REG_VAL 0x10
740 uint8_t au8Must0_1[3]; /**< must be 0 */
741 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
742 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
743 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
744 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
745 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
746 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
747 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
748 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
749 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
750 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
751};
752AssertCompileSize(ACPITBLFADT, 244);
753#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
754
755/** Firmware ACPI Control Structure */
756struct ACPITBLFACS
757{
758 uint8_t au8Signature[4]; /**< 'FACS' */
759 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
760 uint32_t u32HWSignature; /**< systems HW signature at last boot */
761 uint32_t u32FWVector; /**< address of waking vector */
762 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
763 uint32_t u32Flags; /**< FACS flags */
764 uint64_t u64X_FWVector; /**< 64-bit waking vector */
765 uint8_t u8Version; /**< version of this table */
766 uint8_t au8Reserved[31]; /**< zero */
767};
768AssertCompileSize(ACPITBLFACS, 64);
769
770/** Processor Local APIC Structure */
771struct ACPITBLLAPIC
772{
773 uint8_t u8Type; /**< 0 = LAPIC */
774 uint8_t u8Length; /**< 8 */
775 uint8_t u8ProcId; /**< processor ID */
776 uint8_t u8ApicId; /**< local APIC ID */
777 uint32_t u32Flags; /**< Flags */
778#define LAPIC_ENABLED 0x1
779};
780AssertCompileSize(ACPITBLLAPIC, 8);
781
782/** I/O APIC Structure */
783struct ACPITBLIOAPIC
784{
785 uint8_t u8Type; /**< 1 == I/O APIC */
786 uint8_t u8Length; /**< 12 */
787 uint8_t u8IOApicId; /**< I/O APIC ID */
788 uint8_t u8Reserved; /**< 0 */
789 uint32_t u32Address; /**< phys address to access I/O APIC */
790 uint32_t u32GSIB; /**< global system interrupt number to start */
791};
792AssertCompileSize(ACPITBLIOAPIC, 12);
793
794/** Interrupt Source Override Structure */
795struct ACPITBLISO
796{
797 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
798 uint8_t u8Length; /**< 10 */
799 uint8_t u8Bus; /**< Bus */
800 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
801 uint32_t u32GSI; /**< Global System Interrupt */
802 uint16_t u16Flags; /**< MPS INTI flags Global */
803};
804AssertCompileSize(ACPITBLISO, 10);
805#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
806
807/** HPET Descriptor Structure */
808struct ACPITBLHPET
809{
810 ACPITBLHEADER aHeader;
811 uint32_t u32Id; /**< hardware ID of event timer block
812 [31:16] PCI vendor ID of first timer block
813 [15] legacy replacement IRQ routing capable
814 [14] reserved
815 [13] COUNT_SIZE_CAP counter size
816 [12:8] number of comparators in first timer block
817 [7:0] hardware rev ID */
818 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
819 uint8_t u32Number; /**< sequence number starting at 0 */
820 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
821 lost interrupts while the counter is programmed
822 to operate in periodic mode. Unit: clock tick. */
823 uint8_t u8Attributes; /**< page protection and OEM attribute. */
824};
825AssertCompileSize(ACPITBLHPET, 56);
826
827#ifdef VBOX_WITH_IOMMU_AMD
828/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
829 * In accordance with the AMD spec. */
830typedef struct ACPIIVRS
831{
832 ACPITBLHEADER header;
833 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
834 uint64_t u64Rsvd; /**< Reserved (MBZ). */
835 /* IVHD type block follows. */
836} ACPIIVRS;
837AssertCompileSize(ACPIIVRS, 48);
838AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
839
840/**
841 * AMD IOMMU: The ACPI table.
842 */
843typedef struct ACPITBLIOMMU
844{
845 ACPIIVRS Hdr;
846 ACPIIVHDTYPE10 IvhdType10;
847 ACPIIVHDDEVENTRY4 IvhdType10Start;
848 ACPIIVHDDEVENTRY4 IvhdType10End;
849 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
850 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
851 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
852 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
853
854 ACPIIVHDTYPE11 IvhdType11;
855 ACPIIVHDDEVENTRY4 IvhdType11Start;
856 ACPIIVHDDEVENTRY4 IvhdType11End;
857 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
858 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
859 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
860 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
861} ACPITBLIOMMU;
862AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
863AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
864AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
865AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
866#endif /* VBOX_WITH_IOMMU_AMD */
867
868#ifdef VBOX_WITH_IOMMU_INTEL
869/** Intel IOMMU: DMAR (DMA Remapping) Reporting Structure.
870 * In accordance with the AMD spec. */
871typedef struct ACPIDMAR
872{
873 ACPITBLHEADER Hdr;
874 /** Host-address Width (N+1 physical bits addressable). */
875 uint8_t uHostAddrWidth;
876 /** Flags, see ACPI_DMAR_F_XXX. */
877 uint8_t fFlags;
878 /** Reserved. */
879 uint8_t abRsvd[10];
880 /* Remapping Structures[] follows. */
881} ACPIDMAR;
882AssertCompileSize(ACPIDMAR, 48);
883AssertCompileMemberOffset(ACPIDMAR, uHostAddrWidth, 36);
884AssertCompileMemberOffset(ACPIDMAR, fFlags, 37);
885
886/**
887 * Intel VT-d: The ACPI table.
888 */
889typedef struct ACPITBLVTD
890{
891 ACPIDMAR Dmar;
892 ACPIDRHD Drhd;
893 ACPIDMARDEVSCOPE DevScopeIoApic;
894} ACPITBLVTD;
895#endif /* VBOX_WITH_IOMMU_INTEL */
896
897/** MCFG Descriptor Structure */
898typedef struct ACPITBLMCFG
899{
900 ACPITBLHEADER aHeader;
901 uint64_t u64Reserved;
902} ACPITBLMCFG;
903AssertCompileSize(ACPITBLMCFG, 44);
904
905/** Number of such entries can be computed from the whole table length in header */
906typedef struct ACPITBLMCFGENTRY
907{
908 uint64_t u64BaseAddress;
909 uint16_t u16PciSegmentGroup;
910 uint8_t u8StartBus;
911 uint8_t u8EndBus;
912 uint32_t u32Reserved;
913} ACPITBLMCFGENTRY;
914AssertCompileSize(ACPITBLMCFGENTRY, 16);
915
916#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
917
918/** Custom Description Table */
919struct ACPITBLCUST
920{
921 ACPITBLHEADER header;
922 uint8_t au8Data[476];
923};
924AssertCompileSize(ACPITBLCUST, 512);
925
926
927#ifdef VBOX_WITH_TPM
928/**
929 * TPM: The ACPI table for a TPM 2.0 device
930 * (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpec_v1p3_r8_pub.pdf).
931 */
932typedef struct ACPITBLTPM20
933{
934 /** The common ACPI table header. */
935 ACPITBLHEADER Hdr;
936 /** The platform class. */
937 uint16_t u16PlatCls;
938 /** Reserved. */
939 uint16_t u16Rsvd0;
940 /** Address of the CRB control area or FIFO base address. */
941 uint64_t u64BaseAddrCrbOrFifo;
942 /** The start method selector. */
943 uint32_t u32StartMethod;
944 /** Following are start method specific parameters and optional LAML and LASA fields we don't implement right now. */
945 /** @todo */
946} ACPITBLTPM20;
947AssertCompileSize(ACPITBLTPM20, 52);
948
949/** Revision of the TPM2.0 ACPI table. */
950#define ACPI_TPM20_REVISION 4
951/** The default MMIO base address of the TPM. */
952#define ACPI_TPM_MMIO_BASE_DEFAULT 0xfed40000
953
954
955/** @name Possible values for the ACPITBLTPM20::u16PlatCls member.
956 * @{ */
957/** Client platform. */
958#define ACPITBL_TPM20_PLAT_CLS_CLIENT UINT16_C(0)
959/** Server platform. */
960#define ACPITBL_TPM20_PLAT_CLS_SERVER UINT16_C(1)
961/** @} */
962
963
964/** @name Possible values for the ACPITBLTPM20::u32StartMethod member.
965 * @{ */
966/** MMIO interface (TIS1.2+Cancel). */
967#define ACPITBL_TPM20_START_METHOD_TIS12 UINT16_C(6)
968/** CRB interface. */
969#define ACPITBL_TPM20_START_METHOD_CRB UINT16_C(7)
970/** @} */
971
972
973/**
974 * TPM: The ACPI table for a TPM 1.2 device
975 * (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpecification_v1.20_r8.pdf).
976 */
977typedef struct ACPITBLTCPA
978{
979 /** The common ACPI table header. */
980 ACPITBLHEADER Hdr;
981 /** The platform class. */
982 uint16_t u16PlatCls;
983 /** Log Area Minimum Length. */
984 uint32_t u32Laml;
985 /** Log Area Start Address. */
986 uint64_t u64Lasa;
987} ACPITBLTCPA;
988AssertCompileSize(ACPITBLTCPA, 50);
989
990/** Revision of the TPM1.2 ACPI table. */
991#define ACPI_TCPA_REVISION 2
992/** LAML region size. */
993#define ACPI_TCPA_LAML_SZ _16K
994
995
996/** @name Possible values for the ACPITBLTCPA::u16PlatCls member.
997 * @{ */
998/** Client platform. */
999#define ACPI_TCPA_PLAT_CLS_CLIENT UINT16_C(0)
1000/** @} */
1001#endif
1002
1003
1004#pragma pack()
1005
1006
1007#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
1008
1009
1010/*********************************************************************************************************************************
1011* Internal Functions *
1012*********************************************************************************************************************************/
1013#ifdef IN_RING3
1014static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
1015#endif
1016
1017/* SCI, usually IRQ9 */
1018DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
1019{
1020 PDMDevHlpPCISetIrq(pDevIns, 0, level);
1021}
1022
1023DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
1024{
1025 return (pThis->pm1a_ctl & SCI_EN)
1026 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
1027}
1028
1029DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
1030{
1031 return !!(pThis->gpe0_en & pThis->gpe0_sts);
1032}
1033
1034DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
1035{
1036 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1037 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
1038 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
1039 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
1040 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
1041}
1042
1043DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
1044{
1045 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
1046}
1047
1048/**
1049 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
1050 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
1051 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
1052 * registers and trigger IRQs.
1053 *
1054 * Caller must hold the state lock.
1055 *
1056 * @param pDevIns The PDM device instance.
1057 * @param pThis The ACPI shared instance data.
1058 * @param sts The new PM1a.STS value.
1059 * @param en The new PM1a.EN value.
1060 */
1061static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1062{
1063 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1064
1065 const bool old_level = acpiSCILevel(pDevIns, pThis);
1066 pThis->pm1a_en = en;
1067 pThis->pm1a_sts = sts;
1068 const bool new_level = acpiSCILevel(pDevIns, pThis);
1069
1070 LogFunc(("old=%x new=%x\n", old_level, new_level));
1071
1072 if (new_level != old_level)
1073 acpiSetIrq(pDevIns, new_level);
1074}
1075
1076#ifdef IN_RING3
1077
1078/**
1079 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
1080 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
1081 *
1082 * Caller must hold the state lock.
1083 *
1084 * @param pDevIns The PDM device instance.
1085 * @param pThis The ACPI shared instance data.
1086 * @param sts The new GPE0.STS value.
1087 * @param en The new GPE0.EN value.
1088 */
1089static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1090{
1091 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1092
1093 const bool old_level = acpiSCILevel(pDevIns, pThis);
1094 pThis->gpe0_en = en;
1095 pThis->gpe0_sts = sts;
1096 const bool new_level = acpiSCILevel(pDevIns, pThis);
1097
1098 LogFunc(("old=%x new=%x\n", old_level, new_level));
1099
1100 if (new_level != old_level)
1101 acpiSetIrq(pDevIns, new_level);
1102}
1103
1104/**
1105 * Used by acpiR3PM1aCtlWrite to power off the VM.
1106 *
1107 * @param pDevIns The device instance.
1108 * @returns Strict VBox status code.
1109 */
1110static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
1111{
1112 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
1113 AssertRC(VBOXSTRICTRC_VAL(rc));
1114 return rc;
1115}
1116
1117/**
1118 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
1119 *
1120 * @param pDevIns The device instance.
1121 * @param pThis The ACPI shared instance data.
1122 * @returns Strict VBox status code.
1123 */
1124static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
1125{
1126 /* We must set WAK_STS on resume (includes restore) so the guest knows that
1127 we've woken up and can continue executing code. The guest is probably
1128 reading the PMSTS register in a loop to check this. */
1129 VBOXSTRICTRC rc;
1130 pThis->fSetWakeupOnResume = true;
1131 if (pThis->fSuspendToSavedState)
1132 {
1133 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
1134 if (rc != VERR_NOT_SUPPORTED)
1135 AssertRC(VBOXSTRICTRC_VAL(rc));
1136 else
1137 {
1138 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
1139 rc = PDMDevHlpVMSuspend(pDevIns);
1140 AssertRC(VBOXSTRICTRC_VAL(rc));
1141 }
1142 }
1143 else
1144 {
1145 rc = PDMDevHlpVMSuspend(pDevIns);
1146 AssertRC(VBOXSTRICTRC_VAL(rc));
1147 }
1148 return rc;
1149}
1150
1151
1152/**
1153 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
1154 */
1155static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
1156{
1157 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1158 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1159 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1160 DEVACPI_LOCK_R3(pDevIns, pThis);
1161
1162 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1163 pThis->fPowerButtonHandled = false;
1164 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1165
1166 DEVACPI_UNLOCK(pDevIns, pThis);
1167 return VINF_SUCCESS;
1168}
1169
1170/**
1171 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
1172 */
1173static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1174{
1175 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1176 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1177 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1178 DEVACPI_LOCK_R3(pDevIns, pThis);
1179
1180 *pfHandled = pThis->fPowerButtonHandled;
1181
1182 DEVACPI_UNLOCK(pDevIns, pThis);
1183 return VINF_SUCCESS;
1184}
1185
1186/**
1187 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1188 * Guest entered into G0 (working) or G1 (sleeping)}
1189 */
1190static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1191{
1192 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1193 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1194 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1195 DEVACPI_LOCK_R3(pDevIns, pThis);
1196
1197 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1198
1199 DEVACPI_UNLOCK(pDevIns, pThis);
1200 return VINF_SUCCESS;
1201}
1202
1203/**
1204 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1205 */
1206static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1207{
1208 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1209 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1210 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1211 DEVACPI_LOCK_R3(pDevIns, pThis);
1212
1213 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1214
1215 DEVACPI_UNLOCK(pDevIns, pThis);
1216 return VINF_SUCCESS;
1217}
1218
1219/**
1220 * Send an ACPI sleep button event.
1221 *
1222 * @returns VBox status code
1223 * @param pInterface Pointer to the interface structure containing the called function pointer.
1224 */
1225static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1226{
1227 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1228 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1229 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1230 DEVACPI_LOCK_R3(pDevIns, pThis);
1231
1232 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1233
1234 DEVACPI_UNLOCK(pDevIns, pThis);
1235 return VINF_SUCCESS;
1236}
1237
1238/**
1239 * Send an ACPI monitor hot-plug event.
1240 *
1241 * @returns VBox status code
1242 * @param pInterface Pointer to the interface structure containing the
1243 * called function pointer.
1244 */
1245static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1246{
1247 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1248 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1249 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1250 DEVACPI_LOCK_R3(pDevIns, pThis);
1251
1252 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1253
1254 DEVACPI_UNLOCK(pDevIns, pThis);
1255 return VINF_SUCCESS;
1256}
1257
1258/**
1259 * Send an ACPI battery status change event.
1260 *
1261 * @returns VBox status code
1262 * @param pInterface Pointer to the interface structure containing the
1263 * called function pointer.
1264 */
1265static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1266{
1267 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1268 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1269 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1270 DEVACPI_LOCK_R3(pDevIns, pThis);
1271
1272 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1273
1274 DEVACPI_UNLOCK(pDevIns, pThis);
1275 return VINF_SUCCESS;
1276}
1277
1278/**
1279 * Used by acpiR3PmTimer to re-arm the PM timer.
1280 *
1281 * The caller is expected to either hold the clock lock or to have made sure
1282 * the VM is resetting or loading state.
1283 *
1284 * @param pDevIns The device instance.
1285 * @param pThis The ACPI shared instance data.
1286 * @param uNow The current time.
1287 */
1288static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1289{
1290 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1291 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1292 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1293 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1294 Log(("acpi: uInterval = %RU64\n", uInterval));
1295}
1296
1297#endif /* IN_RING3 */
1298
1299/**
1300 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1301 *
1302 * The caller is expected to either hold the clock lock or to have made sure
1303 * the VM is resetting or loading state.
1304 *
1305 * @param pDevIns The PDM device instance.
1306 * @param pThis The ACPI instance
1307 * @param u64Now The current time
1308 */
1309static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1310{
1311 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1312 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1313 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1314
1315 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1316 & TMR_VAL_MASK;
1317
1318 if ((pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1319 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1320}
1321
1322#ifdef IN_RING3
1323
1324/**
1325 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1326 */
1327static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1328{
1329 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1330 Assert(pThis->hPmTimer == hTimer);
1331 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
1332 RT_NOREF(pvUser);
1333
1334 DEVACPI_LOCK_R3(pDevIns, pThis);
1335 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1336 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1337 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1338 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, hTimer);
1339 acpiPmTimerUpdate(pDevIns, pThis, tsNow);
1340 DEVACPI_UNLOCK(pDevIns, pThis);
1341
1342 acpiR3PmTimerReset(pDevIns, pThis, tsNow);
1343}
1344
1345/**
1346 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1347 * acpiR3LoadState.
1348 *
1349 * @returns VINF_SUCCESS.
1350 * @param pThis The ACPI shared instance data.
1351 * @param pThisCC The ACPI instance data for ring-3.
1352 */
1353static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1354{
1355 uint32_t *p = pThis->au8BatteryInfo;
1356 bool fPresent; /* battery present? */
1357 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1358 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1359 uint32_t hostPresentRate; /* 0..1000 */
1360 int rc;
1361
1362 if (!pThisCC->pDrv)
1363 return VINF_SUCCESS;
1364 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1365 &hostBatteryState, &hostPresentRate);
1366 AssertRC(rc);
1367
1368 /* default values */
1369 p[BAT_STATUS_STATE] = hostBatteryState;
1370 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1371 : hostPresentRate * 50; /* mW */
1372 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1373 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1374
1375 /* did we get a valid battery state? */
1376 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1377 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1378 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1379 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1380
1381 return VINF_SUCCESS;
1382}
1383
1384/**
1385 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1386 * acpiR3LoadState.
1387 *
1388 * @returns VINF_SUCCESS.
1389 * @param pThis The ACPI shared instance data.
1390 */
1391static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1392{
1393 uint32_t *p = pThis->au8BatteryInfo;
1394
1395 p[BAT_INFO_UNITS] = 0; /* mWh */
1396 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1397 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1398 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1399 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1400 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1401 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1402 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1403 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1404
1405 return VINF_SUCCESS;
1406}
1407
1408/**
1409 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1410 *
1411 * @returns status mask or 0.
1412 * @param pThisCC The ACPI instance data for ring-3.
1413 */
1414static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1415{
1416 bool fPresent; /* battery present? */
1417 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1418 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1419 uint32_t hostPresentRate; /* 0..1000 */
1420 int rc;
1421
1422 if (!pThisCC->pDrv)
1423 return 0;
1424 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1425 &hostBatteryState, &hostPresentRate);
1426 AssertRC(rc);
1427
1428 return fPresent
1429 ? STA_DEVICE_PRESENT_MASK /* present */
1430 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1431 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1432 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1433 | STA_BATTERY_PRESENT_MASK /* battery is present */
1434 : 0; /* device not present */
1435}
1436
1437/**
1438 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1439 *
1440 * @returns status.
1441 * @param pThisCC The ACPI instance data for ring-3.
1442 */
1443static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1444{
1445 /* query the current power source from the host driver */
1446 if (!pThisCC->pDrv)
1447 return AC_ONLINE;
1448
1449 PDMACPIPOWERSOURCE ps;
1450 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1451 AssertRC(rc);
1452 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1453}
1454
1455/**
1456 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1457 */
1458static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1459{
1460 RT_NOREF(pvUser, offPort);
1461 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1462 if (cb != 4)
1463 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1464
1465 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1466 DEVACPI_LOCK_R3(pDevIns, pThis);
1467
1468 u32 >>= pThis->u8IndexShift;
1469 /* see comment at the declaration of u8IndexShift */
1470 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1471 {
1472 pThis->u8IndexShift = 2;
1473 u32 >>= 2;
1474 }
1475 ASSERT_GUEST_MSG(u32 < BAT_INDEX_LAST, ("%#x\n", u32));
1476 pThis->uBatteryIndex = u32;
1477
1478 DEVACPI_UNLOCK(pDevIns, pThis);
1479 return VINF_SUCCESS;
1480}
1481
1482/**
1483 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1484 */
1485static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1486{
1487 RT_NOREF(pvUser, offPort);
1488 if (cb != 4)
1489 return VERR_IOM_IOPORT_UNUSED;
1490
1491 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1492 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1493 DEVACPI_LOCK_R3(pDevIns, pThis);
1494
1495 VBOXSTRICTRC rc = VINF_SUCCESS;
1496 switch (pThis->uBatteryIndex)
1497 {
1498 case BAT_STATUS_STATE:
1499 acpiR3FetchBatteryStatus(pThis, pThisCC);
1500 RT_FALL_THRU();
1501 case BAT_STATUS_PRESENT_RATE:
1502 case BAT_STATUS_REMAINING_CAPACITY:
1503 case BAT_STATUS_PRESENT_VOLTAGE:
1504 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1505 break;
1506
1507 case BAT_INFO_UNITS:
1508 acpiR3FetchBatteryInfo(pThis);
1509 RT_FALL_THRU();
1510 case BAT_INFO_DESIGN_CAPACITY:
1511 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1512 case BAT_INFO_TECHNOLOGY:
1513 case BAT_INFO_DESIGN_VOLTAGE:
1514 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1515 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1516 case BAT_INFO_CAPACITY_GRANULARITY_1:
1517 case BAT_INFO_CAPACITY_GRANULARITY_2:
1518 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1519 break;
1520
1521 case BAT_DEVICE_STATUS:
1522 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1523 break;
1524
1525 case BAT_POWER_SOURCE:
1526 *pu32 = acpiR3GetPowerSource(pThisCC);
1527 break;
1528
1529 default:
1530 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1531 *pu32 = UINT32_MAX;
1532 break;
1533 }
1534
1535 DEVACPI_UNLOCK(pDevIns, pThis);
1536 return rc;
1537}
1538
1539/**
1540 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1541 */
1542static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1543{
1544 RT_NOREF(pvUser, offPort);
1545 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1546 if (cb != 4)
1547 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1548
1549 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1550 DEVACPI_LOCK_R3(pDevIns, pThis);
1551
1552 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1553 pThis->uSystemInfoIndex = u32;
1554 else
1555 {
1556 /* see comment at the declaration of u8IndexShift */
1557 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1558 {
1559 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1560 pThis->u8IndexShift = 2;
1561 }
1562
1563 u32 >>= pThis->u8IndexShift;
1564
1565 /* If the index exceeds 31 (which is all we can fit within offset 0x80), we need to divide the index again
1566 for indices > 31 and < SYSTEM_INFO_INDEX_END. */
1567 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 2 && (u32 >> 2) < SYSTEM_INFO_INDEX_END)
1568 u32 >>= 2;
1569
1570 ASSERT_GUEST_MSG(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1571 pThis->uSystemInfoIndex = u32;
1572 }
1573
1574 DEVACPI_UNLOCK(pDevIns, pThis);
1575 return VINF_SUCCESS;
1576}
1577
1578/**
1579 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1580 */
1581static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1582{
1583 RT_NOREF(pvUser, offPort);
1584 if (cb != 4)
1585 return VERR_IOM_IOPORT_UNUSED;
1586
1587 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1588 DEVACPI_LOCK_R3(pDevIns, pThis);
1589
1590 VBOXSTRICTRC rc = VINF_SUCCESS;
1591 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1592 switch (uSystemInfoIndex)
1593 {
1594 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1595 *pu32 = pThis->cbRamLow;
1596 break;
1597
1598 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1599 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1600 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1601 break;
1602
1603 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1604 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1605 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1606 break;
1607
1608 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1609 *pu32 = pThis->u8UseIOApic;
1610 break;
1611
1612 case SYSTEM_INFO_INDEX_HPET_STATUS:
1613 *pu32 = pThis->fUseHpet
1614 ? ( STA_DEVICE_PRESENT_MASK
1615 | STA_DEVICE_ENABLED_MASK
1616 | STA_DEVICE_SHOW_IN_UI_MASK
1617 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1618 : 0;
1619 break;
1620
1621 case SYSTEM_INFO_INDEX_SMC_STATUS:
1622 *pu32 = pThis->fUseSmc
1623 ? ( STA_DEVICE_PRESENT_MASK
1624 | STA_DEVICE_ENABLED_MASK
1625 /* no need to show this device in the UI */
1626 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1627 : 0;
1628 break;
1629
1630 case SYSTEM_INFO_INDEX_FDC_STATUS:
1631 *pu32 = pThis->fUseFdc
1632 ? ( STA_DEVICE_PRESENT_MASK
1633 | STA_DEVICE_ENABLED_MASK
1634 | STA_DEVICE_SHOW_IN_UI_MASK
1635 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1636 : 0;
1637 break;
1638
1639 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1640 *pu32 = pThis->u32NicPciAddress;
1641 break;
1642
1643 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1644 *pu32 = pThis->u32AudioPciAddress;
1645 break;
1646
1647 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1648 *pu32 = pThis->u32NvmePciAddress;
1649 break;
1650
1651 case SYSTEM_INFO_INDEX_POWER_STATES:
1652 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1653 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1654 *pu32 |= RT_BIT(1);
1655 if (pThis->fS4Enabled)
1656 *pu32 |= RT_BIT(4);
1657 break;
1658
1659 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1660 *pu32 = pThis->u32IocPciAddress;
1661 break;
1662
1663 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1664 *pu32 = pThis->u32HbcPciAddress;
1665 break;
1666
1667 case SYSTEM_INFO_INDEX_PCI_BASE:
1668 /** @todo couldn't MCFG be in 64-bit range? */
1669 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1670 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1671 break;
1672
1673 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1674 /** @todo couldn't MCFG be in 64-bit range? */
1675 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1676 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1677 break;
1678
1679 case SYSTEM_INFO_INDEX_RTC_STATUS:
1680 *pu32 = pThis->fShowRtc
1681 ? ( STA_DEVICE_PRESENT_MASK
1682 | STA_DEVICE_ENABLED_MASK
1683 | STA_DEVICE_SHOW_IN_UI_MASK
1684 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1685 : 0;
1686 break;
1687
1688 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1689 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1690 {
1691 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1692 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1693 }
1694 else
1695 {
1696 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1697 pThis->idCpuLockCheck);
1698 /* Always return locked status just to be safe */
1699 *pu32 = 1;
1700 }
1701 break;
1702
1703 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1704 *pu32 = pThis->u32CpuEventType;
1705 break;
1706
1707 case SYSTEM_INFO_INDEX_CPU_EVENT:
1708 *pu32 = pThis->u32CpuEvent;
1709 break;
1710
1711 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1712 *pu32 = pThis->uSerial0IoPortBase;
1713 break;
1714
1715 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1716 *pu32 = pThis->uSerial0Irq;
1717 break;
1718
1719 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1720 *pu32 = pThis->uSerial1IoPortBase;
1721 break;
1722
1723 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1724 *pu32 = pThis->uSerial1Irq;
1725 break;
1726
1727 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1728 *pu32 = pThis->uSerial2IoPortBase;
1729 break;
1730
1731 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1732 *pu32 = pThis->uSerial2Irq;
1733 break;
1734
1735 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1736 *pu32 = pThis->uSerial3IoPortBase;
1737 break;
1738
1739 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1740 *pu32 = pThis->uSerial3Irq;
1741 break;
1742
1743 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1744 *pu32 = pThis->uParallel0IoPortBase;
1745 break;
1746
1747 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1748 *pu32 = pThis->uParallel0Irq;
1749 break;
1750
1751 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1752 *pu32 = pThis->uParallel1IoPortBase;
1753 break;
1754
1755 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1756 *pu32 = pThis->uParallel1Irq;
1757 break;
1758
1759 case SYSTEM_INFO_INDEX_IOMMU_ADDRESS:
1760 *pu32 = pThis->u32IommuPciAddress;
1761 break;
1762
1763 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
1764 *pu32 = pThis->u32SbIoApicPciAddress;
1765 break;
1766
1767 case SYSTEM_INFO_INDEX_END:
1768 /** @todo why isn't this setting any output value? */
1769 break;
1770
1771 /* Solaris 9 tries to read from this index */
1772 case SYSTEM_INFO_INDEX_INVALID:
1773 *pu32 = 0;
1774 break;
1775
1776 default:
1777 *pu32 = UINT32_MAX;
1778 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, uSystemInfoIndex);
1779 break;
1780 }
1781
1782 DEVACPI_UNLOCK(pDevIns, pThis);
1783 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1784 return rc;
1785}
1786
1787/**
1788 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1789 */
1790static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1791{
1792 RT_NOREF(pvUser, offPort);
1793 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1794 if (cb != 4)
1795 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1796
1797 DEVACPI_LOCK_R3(pDevIns, pThis);
1798 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1799
1800 VBOXSTRICTRC rc = VINF_SUCCESS;
1801 switch (pThis->uSystemInfoIndex)
1802 {
1803 case SYSTEM_INFO_INDEX_INVALID:
1804 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1805 pThis->u8IndexShift = 0;
1806 break;
1807
1808 case SYSTEM_INFO_INDEX_VALID:
1809 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1810 pThis->u8IndexShift = 2;
1811 break;
1812
1813 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1814 pThis->idCpuLockCheck = u32;
1815 break;
1816
1817 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1818 if (u32 < pThis->cCpus)
1819 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1820 else
1821 LogRel(("ACPI: CPU %u does not exist\n", u32));
1822 break;
1823
1824 default:
1825 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1826 break;
1827 }
1828
1829 DEVACPI_UNLOCK(pDevIns, pThis);
1830 return rc;
1831}
1832
1833/**
1834 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1835 */
1836static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1837{
1838 RT_NOREF(offPort, pvUser);
1839 if (cb != 2)
1840 return VERR_IOM_IOPORT_UNUSED;
1841
1842 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1843 DEVACPI_LOCK_R3(pDevIns, pThis);
1844
1845 *pu32 = pThis->pm1a_en;
1846
1847 DEVACPI_UNLOCK(pDevIns, pThis);
1848 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1849 return VINF_SUCCESS;
1850}
1851
1852/**
1853 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1854 */
1855static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1856{
1857 RT_NOREF(offPort, pvUser);
1858 if (cb != 2 && cb != 4)
1859 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1860
1861 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1862 DEVACPI_LOCK_R3(pDevIns, pThis);
1863
1864 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1865 u32 &= ~(RSR_EN | IGN_EN);
1866 u32 &= 0xffff;
1867 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1868
1869 DEVACPI_UNLOCK(pDevIns, pThis);
1870 return VINF_SUCCESS;
1871}
1872
1873/**
1874 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1875 */
1876static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1877{
1878 RT_NOREF(offPort, pvUser);
1879 if (cb != 2)
1880 {
1881 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1882 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1883 }
1884
1885 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1886 DEVACPI_LOCK_R3(pDevIns, pThis);
1887
1888 *pu32 = pThis->pm1a_sts;
1889
1890 DEVACPI_UNLOCK(pDevIns, pThis);
1891 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1892 return VINF_SUCCESS;
1893}
1894
1895/**
1896 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1897 */
1898static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1899{
1900 RT_NOREF(offPort, pvUser);
1901 if (cb != 2 && cb != 4)
1902 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1903
1904 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1905 DEVACPI_LOCK_R3(pDevIns, pThis);
1906
1907 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1908 u32 &= 0xffff;
1909 if (u32 & PWRBTN_STS)
1910 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1911 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1912 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1913
1914 DEVACPI_UNLOCK(pDevIns, pThis);
1915 return VINF_SUCCESS;
1916}
1917
1918/**
1919 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1920 */
1921static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1922{
1923 RT_NOREF(offPort, pvUser);
1924 if (cb != 2)
1925 {
1926 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1927 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1928 }
1929
1930 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1931 DEVACPI_LOCK_R3(pDevIns, pThis);
1932
1933 *pu32 = pThis->pm1a_ctl;
1934
1935 DEVACPI_UNLOCK(pDevIns, pThis);
1936 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1937 return VINF_SUCCESS;
1938}
1939
1940/**
1941 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1942 */
1943static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1944{
1945 RT_NOREF(offPort, pvUser);
1946 if (cb != 2 && cb != 4)
1947 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1948
1949 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1950 DEVACPI_LOCK_R3(pDevIns, pThis);
1951
1952 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1953 u32 &= 0xffff;
1954 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1955
1956 VBOXSTRICTRC rc = VINF_SUCCESS;
1957 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1958 if (uSleepState != pThis->uSleepState)
1959 {
1960 pThis->uSleepState = uSleepState;
1961 switch (uSleepState)
1962 {
1963 case 0x00: /* S0 */
1964 break;
1965
1966 case 0x01: /* S1 */
1967 if (pThis->fS1Enabled)
1968 {
1969 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1970 rc = acpiR3DoSleep(pDevIns, pThis);
1971 break;
1972 }
1973 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1974 RT_FALL_THRU();
1975
1976 case 0x04: /* S4 */
1977 if (pThis->fS4Enabled)
1978 {
1979 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1980 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1981 break;
1982 }
1983 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1984 RT_FALL_THRU();
1985
1986 case 0x05: /* S5 */
1987 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1988 rc = acpiR3DoPowerOff(pDevIns);
1989 break;
1990
1991 default:
1992 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1993 break;
1994 }
1995 }
1996
1997 DEVACPI_UNLOCK(pDevIns, pThis);
1998 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
1999 return rc;
2000}
2001
2002#endif /* IN_RING3 */
2003
2004/**
2005 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
2006 *
2007 * @remarks The only I/O port currently implemented in all contexts.
2008 */
2009static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2010{
2011 RT_NOREF(offPort, pvUser);
2012 if (cb != 4)
2013 return VERR_IOM_IOPORT_UNUSED;
2014
2015 /*
2016 * We use the clock lock to serialize access to u64PmTimerInitial and to
2017 * make sure we get a reliable time from the clock
2018 * as well as and to prevent uPmTimerVal from being updated during read.
2019 */
2020 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2021 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
2022 if (rc == VINF_SUCCESS)
2023 {
2024 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2025 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2026 *pu32 = pThis->uPmTimerVal;
2027
2028 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
2029
2030 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
2031 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
2032
2033#if 0
2034 /** @todo temporary: sanity check against running backwards */
2035 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
2036 if (*pu32 - uOld >= 0x10000000)
2037 {
2038# if defined(IN_RING0)
2039 pThis->uPmTimeA = uOld;
2040 pThis->uPmTimeB = *pu32;
2041 return VERR_TM_TIMER_BAD_CLOCK;
2042# elif defined(IN_RING3)
2043 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
2044# endif
2045 }
2046#endif
2047 }
2048 return rc;
2049}
2050
2051#ifdef IN_RING3
2052
2053/**
2054 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
2055 */
2056static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2057{
2058 RT_NOREF(offPort, pvUser);
2059 if (cb != 1)
2060 {
2061 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2062 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2063 }
2064
2065 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2066 DEVACPI_LOCK_R3(pDevIns, pThis);
2067
2068 *pu32 = pThis->gpe0_sts & 0xff;
2069
2070 DEVACPI_UNLOCK(pDevIns, pThis);
2071 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
2072 return VINF_SUCCESS;
2073}
2074
2075/**
2076 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
2077 */
2078static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2079{
2080 RT_NOREF(offPort, pvUser);
2081 if (cb != 1)
2082 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2083
2084 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2085 DEVACPI_LOCK_R3(pDevIns, pThis);
2086
2087 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
2088 u32 = pThis->gpe0_sts & ~u32;
2089 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
2090
2091 DEVACPI_UNLOCK(pDevIns, pThis);
2092 return VINF_SUCCESS;
2093}
2094
2095/**
2096 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
2097 */
2098static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2099{
2100 RT_NOREF(offPort, pvUser);
2101 if (cb != 1)
2102 {
2103 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2104 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2105 }
2106
2107 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2108 DEVACPI_LOCK_R3(pDevIns, pThis);
2109
2110 *pu32 = pThis->gpe0_en & 0xff;
2111
2112 DEVACPI_UNLOCK(pDevIns, pThis);
2113 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
2114 return VINF_SUCCESS;
2115}
2116
2117/**
2118 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
2119 */
2120static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2121{
2122 RT_NOREF(offPort, pvUser);
2123 if (cb != 1)
2124 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2125
2126 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2127 DEVACPI_LOCK_R3(pDevIns, pThis);
2128
2129 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
2130 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
2131
2132 DEVACPI_UNLOCK(pDevIns, pThis);
2133 return VINF_SUCCESS;
2134}
2135
2136/**
2137 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
2138 */
2139static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2140{
2141 RT_NOREF(offPort, pvUser);
2142 Log(("acpiR3SmiWrite %#x\n", u32));
2143 if (cb != 1)
2144 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2145
2146 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2147 DEVACPI_LOCK_R3(pDevIns, pThis);
2148
2149 if (u32 == ACPI_ENABLE)
2150 pThis->pm1a_ctl |= SCI_EN;
2151 else if (u32 == ACPI_DISABLE)
2152 pThis->pm1a_ctl &= ~SCI_EN;
2153 else
2154 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2155
2156 DEVACPI_UNLOCK(pDevIns, pThis);
2157 return VINF_SUCCESS;
2158}
2159
2160/**
2161 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2162 */
2163static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2164{
2165 RT_NOREF(offPort, pvUser);
2166 Log(("acpiR3ResetWrite: %#x\n", u32));
2167 NOREF(pvUser);
2168 if (cb != 1)
2169 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2170
2171 /* No state locking required. */
2172 VBOXSTRICTRC rc;
2173 if (u32 == ACPI_RESET_REG_VAL)
2174 {
2175 LogRel(("ACPI: Reset initiated by ACPI\n"));
2176 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2177 }
2178 else
2179 {
2180 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2181 rc = VINF_SUCCESS;
2182 }
2183
2184 return rc;
2185}
2186
2187# ifdef DEBUG_ACPI
2188
2189/**
2190 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2191 */
2192static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2193{
2194 NOREF(pvUser);
2195 switch (cb)
2196 {
2197 case 1:
2198 Log(("%#x\n", u32 & 0xff));
2199 break;
2200 case 2:
2201 Log(("%#6x\n", u32 & 0xffff));
2202 break;
2203 case 4:
2204 Log(("%#10x\n", u32));
2205 break;
2206 default:
2207 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2208 }
2209 return VINF_SUCCESS;
2210}
2211
2212/**
2213 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2214 */
2215static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2216{
2217 NOREF(pvUser);
2218 switch (cb)
2219 {
2220 case 1:
2221 Log(("%c", u32 & 0xff));
2222 break;
2223 default:
2224 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2225 }
2226 return VINF_SUCCESS;
2227}
2228
2229# endif /* DEBUG_ACPI */
2230
2231/**
2232 * @callback_method_impl{FNDBGFHANDLERDEV}
2233 */
2234static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2235{
2236 RT_NOREF(pszArgs);
2237 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2238 pHlp->pfnPrintf(pHlp,
2239 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2240}
2241
2242/**
2243 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2244 *
2245 * @param pDevIns The PDM device instance.
2246 * @param pThis The ACPI shared instance data.
2247 */
2248static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2249{
2250 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2251 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2252 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2253 pPciDev->abConfig[PMBA + 2] = 0x00;
2254 pPciDev->abConfig[PMBA + 3] = 0x00;
2255}
2256
2257/**
2258 * Used to calculate the value of a PM I/O port.
2259 *
2260 * @returns The actual I/O port value.
2261 * @param pThis The ACPI shared instance data.
2262 * @param offset The offset into the I/O space, or -1 if invalid.
2263 */
2264static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2265{
2266 Assert(pThis->uPmIoPortBase != 0);
2267
2268 if (offset == -1)
2269 return 0;
2270
2271 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2272}
2273
2274/**
2275 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2276 * timer and GPE0 I/O ports.
2277 *
2278 * @returns VBox status code.
2279 * @param pDevIns The device instance.
2280 * @param pThis The ACPI shared instance data.
2281 */
2282static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2283{
2284 if (pThis->uPmIoPortBase == 0)
2285 return VINF_SUCCESS;
2286
2287 int rc;
2288 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2289 AssertRCReturn(rc, rc);
2290 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2291 AssertRCReturn(rc, rc);
2292 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2293 AssertRCReturn(rc, rc);
2294 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2295 AssertRCReturn(rc, rc);
2296 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2297 AssertRCReturn(rc, rc);
2298 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2299
2300 return VINF_SUCCESS;
2301}
2302
2303/**
2304 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2305 * timer and GPE0 I/O ports.
2306 *
2307 * @returns VBox status code.
2308 * @param pDevIns The device instance.
2309 * @param pThis The ACPI shared instance data.
2310 */
2311static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2312{
2313 if (pThis->uPmIoPortBase != 0)
2314 {
2315 int rc;
2316 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2317 AssertRCReturn(rc, rc);
2318 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2319 AssertRCReturn(rc, rc);
2320 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2321 AssertRCReturn(rc, rc);
2322 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2323 AssertRCReturn(rc, rc);
2324 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2325 AssertRCReturn(rc, rc);
2326 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2327 AssertRCReturn(rc, rc);
2328 }
2329 return VINF_SUCCESS;
2330}
2331
2332/**
2333 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2334 * PM1a, PM timer and GPE0 ports.
2335 *
2336 * @returns VBox status code.
2337 *
2338 * @param pDevIns The device instance.
2339 * @param pThis The ACPI shared instance data.
2340 * @param pThisCC The ACPI instance data for ring-3.
2341 * @param NewIoPortBase The new base address of the I/O ports.
2342 */
2343static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2344{
2345 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2346 if (NewIoPortBase != pThis->uPmIoPortBase)
2347 {
2348 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2349 if (RT_FAILURE(rc))
2350 return rc;
2351
2352 pThis->uPmIoPortBase = NewIoPortBase;
2353
2354 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2355 if (RT_FAILURE(rc))
2356 return rc;
2357
2358 /* We have to update FADT table acccording to the new base */
2359 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2360 AssertRC(rc);
2361 if (RT_FAILURE(rc))
2362 return rc;
2363 }
2364
2365 return VINF_SUCCESS;
2366}
2367
2368/**
2369 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2370 */
2371static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2372{
2373 RT_NOREF(pvUser);
2374 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2375
2376 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2377 uint8_t off = offPort & 0x000f;
2378 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2379 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2380 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2381
2382 DEVACPI_LOCK_R3(pDevIns, pThis);
2383 switch (off)
2384 {
2385 case SMBHSTSTS_OFF:
2386 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2387 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2388 break;
2389 case SMBSLVSTS_OFF:
2390 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2391 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2392 break;
2393 case SMBHSTCNT_OFF:
2394 {
2395 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2396
2397 const bool old_level = acpiSCILevel(pDevIns, pThis);
2398 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2399 if (u32 & SMBHSTCNT_START)
2400 {
2401 /* Start, trigger error as this is a dummy implementation */
2402 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2403 }
2404 if (u32 & SMBHSTCNT_KILL)
2405 {
2406 /* Kill */
2407 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2408 }
2409 const bool new_level = acpiSCILevel(pDevIns, pThis);
2410
2411 LogFunc(("old=%x new=%x\n", old_level, new_level));
2412
2413 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2414 * needs to be implemented later if it ever becomes relevant. */
2415 if (new_level != old_level)
2416 acpiSetIrq(pDevIns, new_level);
2417 break;
2418 }
2419 case SMBHSTCMD_OFF:
2420 pThis->u8SMBusHstCmd = u32;
2421 break;
2422 case SMBHSTADD_OFF:
2423 pThis->u8SMBusHstAdd = u32;
2424 break;
2425 case SMBHSTDAT0_OFF:
2426 pThis->u8SMBusHstDat0 = u32;
2427 break;
2428 case SMBHSTDAT1_OFF:
2429 pThis->u8SMBusHstDat1 = u32;
2430 break;
2431 case SMBBLKDAT_OFF:
2432 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2433 pThis->u8SMBusBlkIdx++;
2434 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2435 break;
2436 case SMBSLVCNT_OFF:
2437 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2438 break;
2439 case SMBSHDWCMD_OFF:
2440 /* readonly register */
2441 break;
2442 case SMBSLVEVT_OFF:
2443 pThis->u16SMBusSlvEvt = u32;
2444 break;
2445 case SMBSLVDAT_OFF:
2446 /* readonly register */
2447 break;
2448 default:
2449 /* caught by the sanity check above */
2450 ;
2451 }
2452
2453 DEVACPI_UNLOCK(pDevIns, pThis);
2454 return VINF_SUCCESS;
2455}
2456
2457/**
2458 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2459 */
2460static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2461{
2462 RT_NOREF(pvUser);
2463 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2464
2465 VBOXSTRICTRC rc = VINF_SUCCESS;
2466 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2467 uint8_t const off = offPort & 0x000f;
2468 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2469 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2470 return VERR_IOM_IOPORT_UNUSED;
2471
2472 DEVACPI_LOCK_R3(pDevIns, pThis);
2473 switch (off)
2474 {
2475 case SMBHSTSTS_OFF:
2476 *pu32 = pThis->u8SMBusHstSts;
2477 break;
2478 case SMBSLVSTS_OFF:
2479 *pu32 = pThis->u8SMBusSlvSts;
2480 break;
2481 case SMBHSTCNT_OFF:
2482 pThis->u8SMBusBlkIdx = 0;
2483 *pu32 = pThis->u8SMBusHstCnt;
2484 break;
2485 case SMBHSTCMD_OFF:
2486 *pu32 = pThis->u8SMBusHstCmd;
2487 break;
2488 case SMBHSTADD_OFF:
2489 *pu32 = pThis->u8SMBusHstAdd;
2490 break;
2491 case SMBHSTDAT0_OFF:
2492 *pu32 = pThis->u8SMBusHstDat0;
2493 break;
2494 case SMBHSTDAT1_OFF:
2495 *pu32 = pThis->u8SMBusHstDat1;
2496 break;
2497 case SMBBLKDAT_OFF:
2498 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2499 pThis->u8SMBusBlkIdx++;
2500 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2501 break;
2502 case SMBSLVCNT_OFF:
2503 *pu32 = pThis->u8SMBusSlvCnt;
2504 break;
2505 case SMBSHDWCMD_OFF:
2506 *pu32 = pThis->u8SMBusShdwCmd;
2507 break;
2508 case SMBSLVEVT_OFF:
2509 *pu32 = pThis->u16SMBusSlvEvt;
2510 break;
2511 case SMBSLVDAT_OFF:
2512 *pu32 = pThis->u16SMBusSlvDat;
2513 break;
2514 default:
2515 /* caught by the sanity check above */
2516 rc = VERR_IOM_IOPORT_UNUSED;
2517 }
2518 DEVACPI_UNLOCK(pDevIns, pThis);
2519
2520 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2521 return rc;
2522}
2523
2524/**
2525 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2526 *
2527 * @param pDevIns The PDM device instance.
2528 * @param pThis The ACPI shared instance data.
2529 */
2530static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2531{
2532 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2533 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2534 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2535 pPciDev->abConfig[SMBBA+2] = 0x00;
2536 pPciDev->abConfig[SMBBA+3] = 0x00;
2537 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2538 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2539 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2540 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2541 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2542}
2543
2544/**
2545 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2546 *
2547 * @param pThis The ACPI shared instance data.
2548 */
2549static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2550{
2551 pThis->u8SMBusHstSts = 0x00;
2552 pThis->u8SMBusSlvSts = 0x00;
2553 pThis->u8SMBusHstCnt = 0x00;
2554 pThis->u8SMBusHstCmd = 0x00;
2555 pThis->u8SMBusHstAdd = 0x00;
2556 pThis->u8SMBusHstDat0 = 0x00;
2557 pThis->u8SMBusHstDat1 = 0x00;
2558 pThis->u8SMBusSlvCnt = 0x00;
2559 pThis->u8SMBusShdwCmd = 0x00;
2560 pThis->u16SMBusSlvEvt = 0x0000;
2561 pThis->u16SMBusSlvDat = 0x0000;
2562 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2563 pThis->u8SMBusBlkIdx = 0;
2564}
2565
2566/**
2567 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2568 *
2569 * @returns VBox status code.
2570 * @param pDevIns The device instance.
2571 * @param pThis The ACPI shared instance data.
2572 */
2573static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2574{
2575 if (pThis->uSMBusIoPortBase != 0)
2576 {
2577 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2578 AssertRCReturn(rc, rc);
2579 }
2580 return VINF_SUCCESS;
2581}
2582
2583/**
2584 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2585 *
2586 * @returns VBox status code.
2587 * @param pDevIns The device instance.
2588 * @param pThis The ACPI shared instance data.
2589 */
2590static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2591{
2592 if (pThis->uSMBusIoPortBase != 0)
2593 {
2594 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2595 AssertRCReturn(rc, rc);
2596 }
2597 return VINF_SUCCESS;
2598}
2599
2600/**
2601 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2602 * SMBus ports.
2603 *
2604 * @returns VBox status code.
2605 *
2606 * @param pDevIns The device instance.
2607 * @param pThis The ACPI shared instance data.
2608 * @param NewIoPortBase The new base address of the I/O ports.
2609 */
2610static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2611{
2612 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2613 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2614 {
2615 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2616 AssertRCReturn(rc, rc);
2617
2618 pThis->uSMBusIoPortBase = NewIoPortBase;
2619
2620 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2621 AssertRCReturn(rc, rc);
2622
2623#if 0 /* is there an FADT table entry for the SMBus base? */
2624 /* We have to update FADT table acccording to the new base */
2625 rc = acpiR3PlantTables(pThis);
2626 AssertRC(rc);
2627 if (RT_FAILURE(rc))
2628 return rc;
2629#endif
2630 }
2631
2632 return VINF_SUCCESS;
2633}
2634
2635
2636/**
2637 * Saved state structure description, version 4.
2638 */
2639static const SSMFIELD g_AcpiSavedStateFields4[] =
2640{
2641 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2642 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2643 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2644 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2645 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2646 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2647 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2648 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2649 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2650 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2651 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2652 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2653 SSMFIELD_ENTRY_TERM()
2654};
2655
2656/**
2657 * Saved state structure description, version 5.
2658 */
2659static const SSMFIELD g_AcpiSavedStateFields5[] =
2660{
2661 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2662 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2663 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2664 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2665 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2666 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2667 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2668 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2669 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2670 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2671 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2672 SSMFIELD_ENTRY_TERM()
2673};
2674
2675/**
2676 * Saved state structure description, version 6.
2677 */
2678static const SSMFIELD g_AcpiSavedStateFields6[] =
2679{
2680 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2681 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2682 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2683 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2684 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2685 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2686 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2687 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2688 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2689 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2690 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2691 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2692 SSMFIELD_ENTRY_TERM()
2693};
2694
2695/**
2696 * Saved state structure description, version 7.
2697 */
2698static const SSMFIELD g_AcpiSavedStateFields7[] =
2699{
2700 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2701 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2702 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2703 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2704 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2705 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2706 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2707 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2708 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2709 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2710 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2711 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2712 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2713 SSMFIELD_ENTRY_TERM()
2714};
2715
2716/**
2717 * Saved state structure description, version 8.
2718 */
2719static const SSMFIELD g_AcpiSavedStateFields8[] =
2720{
2721 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2722 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2723 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2724 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2725 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2726 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2727 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2728 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2729 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2730 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2731 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2732 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2733 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2734 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2735 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2736 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2737 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2738 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2739 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2740 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2741 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2742 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2743 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2744 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2745 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2746 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2747 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2748 SSMFIELD_ENTRY_TERM()
2749};
2750
2751/**
2752 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2753 */
2754static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2755{
2756 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2757 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2758 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2759}
2760
2761/**
2762 * @callback_method_impl{FNSSMDEVLOADEXEC}
2763 */
2764static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2765{
2766 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2767 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2768 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2769 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2770
2771 /*
2772 * Unmap PM I/O ports, will remap it with the actual base after state
2773 * successfully loaded.
2774 */
2775 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2776 AssertRCReturn(rc, rc);
2777
2778 /*
2779 * Unregister SMBus handlers, will register with actual base after state
2780 * successfully loaded.
2781 */
2782 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2783 AssertRCReturn(rc, rc);
2784 acpiR3SMBusResetDevice(pThis);
2785
2786 switch (uVersion)
2787 {
2788 case 4:
2789 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2790 break;
2791 case 5:
2792 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2793 break;
2794 case 6:
2795 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2796 break;
2797 case 7:
2798 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2799 break;
2800 case 8:
2801 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2802 break;
2803 default:
2804 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2805 break;
2806 }
2807 if (RT_SUCCESS(rc))
2808 {
2809 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2810 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2811 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2812 AssertRCReturn(rc, rc);
2813 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2814 AssertRCReturn(rc, rc);
2815 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2816 AssertRCReturn(rc, rc);
2817 rc = acpiR3FetchBatteryInfo(pThis);
2818 AssertRCReturn(rc, rc);
2819
2820 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2821 DEVACPI_LOCK_R3(pDevIns, pThis);
2822 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2823 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2824 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2825 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2826 DEVACPI_UNLOCK(pDevIns, pThis);
2827 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2828 }
2829 return rc;
2830}
2831
2832/**
2833 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2834 */
2835static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2836{
2837 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2838 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2839 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2840 return NULL;
2841}
2842
2843/**
2844 * Calculate the check sum for some ACPI data before planting it.
2845 *
2846 * All the bytes must add up to 0.
2847 *
2848 * @returns check sum.
2849 * @param pvSrc What to check sum.
2850 * @param cbData The amount of data to checksum.
2851 */
2852static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2853{
2854 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2855 uint8_t uSum = 0;
2856 for (size_t i = 0; i < cbData; ++i)
2857 uSum += pbSrc[i];
2858 return -uSum;
2859}
2860
2861/**
2862 * Prepare a ACPI table header.
2863 */
2864static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2865 const char au8Signature[4],
2866 uint32_t u32Length, uint8_t u8Revision)
2867{
2868 memcpy(header->au8Signature, au8Signature, 4);
2869 header->u32Length = RT_H2LE_U32(u32Length);
2870 header->u8Revision = u8Revision;
2871 memcpy(header->au8OemId, pThis->au8OemId, 6);
2872 memcpy(header->au8OemTabId, "VBOX", 4);
2873 memcpy(header->au8OemTabId+4, au8Signature, 4);
2874 header->u32OemRevision = RT_H2LE_U32(1);
2875 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2876 header->u32CreatorRev = pThis->u32CreatorRev;
2877}
2878
2879/**
2880 * Initialize a generic address structure (ACPIGENADDR).
2881 */
2882static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2883 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2884 uint8_t u8AccessSize, uint64_t u64Address)
2885{
2886 g->u8AddressSpaceId = u8AddressSpaceId;
2887 g->u8RegisterBitWidth = u8RegisterBitWidth;
2888 g->u8RegisterBitOffset = u8RegisterBitOffset;
2889 g->u8AccessSize = u8AccessSize;
2890 g->u64Address = RT_H2LE_U64(u64Address);
2891}
2892
2893/**
2894 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2895 */
2896DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2897{
2898 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2899}
2900
2901/**
2902 * Plant the Differentiated System Description Table (DSDT).
2903 */
2904static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2905{
2906 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2907}
2908
2909/**
2910 * Plant the Secondary System Description Table (SSDT).
2911 */
2912static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2913{
2914 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2915}
2916
2917#ifdef VBOX_WITH_TPM
2918/**
2919 * Plant the Secondary System Description Table (SSDT).
2920 */
2921static void acpiR3SetupTpmSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2922{
2923 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2924}
2925#endif
2926
2927/**
2928 * Plant the Firmware ACPI Control Structure (FACS).
2929 */
2930static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2931{
2932 ACPITBLFACS facs;
2933
2934 memset(&facs, 0, sizeof(facs));
2935 memcpy(facs.au8Signature, "FACS", 4);
2936 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2937 facs.u32HWSignature = RT_H2LE_U32(0);
2938 facs.u32FWVector = RT_H2LE_U32(0);
2939 facs.u32GlobalLock = RT_H2LE_U32(0);
2940 facs.u32Flags = RT_H2LE_U32(0);
2941 facs.u64X_FWVector = RT_H2LE_U64(0);
2942 facs.u8Version = 1;
2943
2944 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2945}
2946
2947/**
2948 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2949 */
2950static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2951 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2952{
2953 ACPITBLFADT fadt;
2954
2955 /* First the ACPI version 2+ version of the structure. */
2956 memset(&fadt, 0, sizeof(fadt));
2957 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2958 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2959 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2960 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2961 fadt.u8PreferredPMProfile = 0; /* unspecified */
2962 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2963 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2964 fadt.u8AcpiEnable = ACPI_ENABLE;
2965 fadt.u8AcpiDisable = ACPI_DISABLE;
2966 fadt.u8S4BIOSReq = 0;
2967 fadt.u8PStateCnt = 0;
2968 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2969 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2970 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2971 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2972 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2973 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2974 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2975 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2976 fadt.u8PM1EVTLEN = 4;
2977 fadt.u8PM1CTLLEN = 2;
2978 fadt.u8PM2CTLLEN = 0;
2979 fadt.u8PMTMLEN = 4;
2980 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2981 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2982 fadt.u8GPE1BASE = GPE1_BASE;
2983 fadt.u8CSTCNT = 0;
2984 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2985 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2986 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2987 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2988 fadt.u8DutyOffset = 0;
2989 fadt.u8DutyWidth = 0;
2990 fadt.u8DayAlarm = 0;
2991 fadt.u8MonAlarm = 0;
2992 fadt.u8Century = 0;
2993 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2994 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2995 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2996 | FADT_FL_FIX_RTC
2997 | FADT_FL_TMR_VAL_EXT
2998 | FADT_FL_RESET_REG_SUP);
2999
3000 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
3001 if (pThis->fCpuHotPlug)
3002 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
3003
3004 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
3005 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
3006 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
3007 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
3008 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
3009 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
3010 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
3011 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
3012 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
3013 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
3014 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
3015 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
3016 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
3017 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
3018
3019 /* Now the ACPI 1.0 version. */
3020 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
3021 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
3022 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
3023 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
3024 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
3025}
3026
3027/**
3028 * Plant the root System Description Table.
3029 *
3030 * The RSDT and XSDT tables are basically identical. The only difference is 32
3031 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
3032 * ACPI 2.0 and up.
3033 */
3034static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3035{
3036 ACPITBLRSDT *rsdt;
3037 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
3038
3039 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
3040 if (!rsdt)
3041 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
3042
3043 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
3044 for (unsigned int i = 0; i < nb_entries; ++i)
3045 {
3046 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
3047 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
3048 }
3049 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
3050 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
3051 RTMemFree(rsdt);
3052 return VINF_SUCCESS;
3053}
3054
3055/**
3056 * Plant the Extended System Description Table.
3057 */
3058static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3059{
3060 ACPITBLXSDT *xsdt;
3061 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
3062 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
3063 if (!xsdt)
3064 return VERR_NO_TMP_MEMORY;
3065
3066 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
3067
3068 if (pThis->cCustTbls > 0)
3069 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
3070
3071 for (unsigned int i = 0; i < nb_entries; ++i)
3072 {
3073 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
3074 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
3075 }
3076 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
3077 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
3078
3079 RTMemFree(xsdt);
3080 return VINF_SUCCESS;
3081}
3082
3083/**
3084 * Plant the Root System Description Pointer (RSDP).
3085 */
3086static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
3087{
3088 memset(rsdp, 0, sizeof(*rsdp));
3089
3090 /* ACPI 1.0 part (RSDT) */
3091 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
3092 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
3093 rsdp->u8Revision = ACPI_REVISION;
3094 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
3095 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
3096
3097 /* ACPI 2.0 part (XSDT) */
3098 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
3099 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
3100 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
3101}
3102
3103/**
3104 * Multiple APIC Description Table.
3105 *
3106 * This structure looks somewhat convoluted due layout of MADT table in MP case.
3107 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
3108 * use regular C structure and proxy to raw memory instead.
3109 */
3110class AcpiTableMadt
3111{
3112 /**
3113 * All actual data stored in dynamically allocated memory pointed by this field.
3114 */
3115 uint8_t *m_pbData;
3116 /**
3117 * Number of CPU entries in this MADT.
3118 */
3119 uint32_t m_cCpus;
3120
3121 /**
3122 * Number of interrupt overrides.
3123 */
3124 uint32_t m_cIsos;
3125
3126public:
3127 /**
3128 * Address of ACPI header
3129 */
3130 inline ACPITBLHEADER *header_addr(void) const
3131 {
3132 return (ACPITBLHEADER *)m_pbData;
3133 }
3134
3135 /**
3136 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
3137 * although address is the same for all of them.
3138 */
3139 inline uint32_t *u32LAPIC_addr(void) const
3140 {
3141 return (uint32_t *)(header_addr() + 1);
3142 }
3143
3144 /**
3145 * Address of APIC flags
3146 */
3147 inline uint32_t *u32Flags_addr(void) const
3148 {
3149 return (uint32_t *)(u32LAPIC_addr() + 1);
3150 }
3151
3152 /**
3153 * Address of ISO description
3154 */
3155 inline ACPITBLISO *ISO_addr(void) const
3156 {
3157 return (ACPITBLISO *)(u32Flags_addr() + 1);
3158 }
3159
3160 /**
3161 * Address of per-CPU LAPIC descriptions
3162 */
3163 inline ACPITBLLAPIC *LApics_addr(void) const
3164 {
3165 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3166 }
3167
3168 /**
3169 * Address of IO APIC description
3170 */
3171 inline ACPITBLIOAPIC *IOApic_addr(void) const
3172 {
3173 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3174 }
3175
3176 /**
3177 * Size of MADT.
3178 * Note that this function assumes IOApic to be the last field in structure.
3179 */
3180 inline uint32_t size(void) const
3181 {
3182 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3183 }
3184
3185 /**
3186 * Raw data of MADT.
3187 */
3188 inline const uint8_t *data(void) const
3189 {
3190 return m_pbData;
3191 }
3192
3193 /**
3194 * Size of MADT for given ACPI config, useful to compute layout.
3195 */
3196 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3197 {
3198 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3199 }
3200
3201 /*
3202 * Constructor, only works in Ring 3, doesn't look like a big deal.
3203 */
3204 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3205 {
3206 m_cCpus = cCpus;
3207 m_cIsos = cIsos;
3208 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3209 uint32_t cb = size();
3210 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3211 }
3212
3213 ~AcpiTableMadt()
3214 {
3215 RTMemFree(m_pbData);
3216 }
3217};
3218
3219
3220/**
3221 * Plant the Multiple APIC Description Table (MADT).
3222 *
3223 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3224 *
3225 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3226 */
3227static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3228{
3229 uint16_t cpus = pThis->cCpus;
3230 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3231
3232 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3233
3234 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3235 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3236
3237 /* LAPICs records */
3238 ACPITBLLAPIC* lapic = madt.LApics_addr();
3239 for (uint16_t i = 0; i < cpus; i++)
3240 {
3241 lapic->u8Type = 0;
3242 lapic->u8Length = sizeof(ACPITBLLAPIC);
3243 lapic->u8ProcId = i;
3244 /** Must match numbering convention in MPTABLES */
3245 lapic->u8ApicId = i;
3246 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3247 lapic++;
3248 }
3249
3250 /* IO-APIC record */
3251 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3252 ioapic->u8Type = 1;
3253 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3254 /** Must match MP tables ID */
3255 ioapic->u8IOApicId = cpus;
3256 ioapic->u8Reserved = 0;
3257 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3258 ioapic->u32GSIB = RT_H2LE_U32(0);
3259
3260 /* Interrupt Source Overrides */
3261 /* Flags:
3262 bits[3:2]:
3263 00 conforms to the bus
3264 01 edge-triggered
3265 10 reserved
3266 11 level-triggered
3267 bits[1:0]
3268 00 conforms to the bus
3269 01 active-high
3270 10 reserved
3271 11 active-low */
3272 /* If changing, also update PDMIsaSetIrq() and MPS */
3273 ACPITBLISO* isos = madt.ISO_addr();
3274 /* Timer interrupt rule IRQ0 to GSI2 */
3275 isos[0].u8Type = 2;
3276 isos[0].u8Length = sizeof(ACPITBLISO);
3277 isos[0].u8Bus = 0; /* Must be 0 */
3278 isos[0].u8Source = 0; /* IRQ0 */
3279 isos[0].u32GSI = 2; /* connected to pin 2 */
3280 isos[0].u16Flags = 0; /* conform to the bus */
3281
3282 /* ACPI interrupt rule - IRQ9 to GSI9 */
3283 isos[1].u8Type = 2;
3284 isos[1].u8Length = sizeof(ACPITBLISO);
3285 isos[1].u8Bus = 0; /* Must be 0 */
3286 isos[1].u8Source = 9; /* IRQ9 */
3287 isos[1].u32GSI = 9; /* connected to pin 9 */
3288 isos[1].u16Flags = 0xf; /* active low, level triggered */
3289 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3290
3291 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3292 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3293}
3294
3295/**
3296 * Plant the High Performance Event Timer (HPET) descriptor.
3297 */
3298static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3299{
3300 ACPITBLHPET hpet;
3301
3302 memset(&hpet, 0, sizeof(hpet));
3303
3304 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3305 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3306 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3307 0 /* Memory address space */,
3308 64 /* Register bit width */,
3309 0 /* Bit offset */,
3310 0, /* Register access size, is it correct? */
3311 0xfed00000 /* Address */);
3312
3313 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3314 hpet.u32Number = 0;
3315 hpet.u32MinTick = 4096;
3316 hpet.u8Attributes = 0;
3317
3318 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3319
3320 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3321}
3322
3323
3324#ifdef VBOX_WITH_IOMMU_AMD
3325/**
3326 * Plant the AMD IOMMU descriptor.
3327 */
3328static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3329{
3330 ACPITBLIOMMU Ivrs;
3331 RT_ZERO(Ivrs);
3332
3333 uint16_t const uIommuBus = 0;
3334 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuPciAddress);
3335 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuPciAddress);
3336
3337 /* IVRS header. */
3338 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3339 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3340 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3341 | RT_BF_MAKE(ACPI_IVINFO_BF_DMA_REMAP_SUP, 0) /* Pre-boot DMA remap support not supported. */
3342 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3343 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3344 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64) /* Virt. Addr size (64 bits) */
3345 | RT_BF_MAKE(ACPI_IVINFO_BF_HT_ATS_RESV, 0); /* ATS response range reserved (only applicable for HT) */
3346
3347 /* IVHD type 10 definition block. */
3348 Ivrs.IvhdType10.u8Type = 0x10;
3349 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3350 + sizeof(Ivrs.IvhdType10Start)
3351 + sizeof(Ivrs.IvhdType10End)
3352 + sizeof(Ivrs.IvhdType10Rsvd0)
3353 + sizeof(Ivrs.IvhdType10Rsvd1)
3354 + sizeof(Ivrs.IvhdType10IoApic)
3355 + sizeof(Ivrs.IvhdType10Hpet);
3356 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3357 Ivrs.IvhdType10.u16CapOffset = IOMMU_PCI_OFF_CAP_HDR;
3358 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR;
3359 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3360 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3361 Ivrs.IvhdType10.u8Flags = ACPI_IVHD_10H_F_COHERENT; /* Remote IOTLB etc. not supported. */
3362 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3363 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3364 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3365 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3366 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3367 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3368 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3369 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3370 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3371 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3372 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3373 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3374 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3375 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3376 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3377 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3);
3378 /* Start range from BDF (00:01:00). */
3379 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3380 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3381 Ivrs.IvhdType10Start.u8DteSetting = 0;
3382 /* End range at BDF (ff:1f:7). */
3383 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3384 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3385 Ivrs.IvhdType10End.u8DteSetting = 0;
3386
3387 /* Southbridge I/O APIC special device entry. */
3388 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3389 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3390 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3391 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3392 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3393 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3394 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3395 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3396 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3397 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3398
3399 /* HPET special device entry. */
3400 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3401 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3402 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3403 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3404 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3405 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3406
3407 /* IVHD type 11 definition block. */
3408 Ivrs.IvhdType11.u8Type = 0x11;
3409 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3410 + sizeof(Ivrs.IvhdType11Start)
3411 + sizeof(Ivrs.IvhdType11End)
3412 + sizeof(Ivrs.IvhdType11Rsvd0)
3413 + sizeof(Ivrs.IvhdType11Rsvd1)
3414 + sizeof(Ivrs.IvhdType11IoApic)
3415 + sizeof(Ivrs.IvhdType11Hpet);
3416 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3417 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3418 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3419 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3420 Ivrs.IvhdType11.u8Flags = ACPI_IVHD_11H_F_COHERENT;
3421 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3422 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3423 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3424 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3425 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3426 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3427 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3428 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3429 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3430 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3431 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 1)
3432 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3433 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3434 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3435 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3)
3436 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3437 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3438 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3439 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3440 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3441 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3442 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3443 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3444 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3445 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS)
3446 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3447 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3448 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3449 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3450 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3451 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3452 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3453 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3454 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3455 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3456 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3457 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3458 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3459 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3460
3461 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3462 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3463 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3464 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3465 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3466 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3467 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3468
3469 /* Finally, compute checksum. */
3470 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3471
3472 /* Plant the ACPI table. */
3473 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3474}
3475#endif /* VBOX_WITH_IOMMU_AMD */
3476
3477
3478#ifdef VBOX_WITH_IOMMU_INTEL
3479/**
3480 * Plant the Intel IOMMU (VT-d) descriptor.
3481 */
3482static void acpiR3SetupIommuIntel(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3483{
3484 ACPITBLVTD VtdTable;
3485 RT_ZERO(VtdTable);
3486
3487 /* VT-d Table. */
3488 acpiR3PrepareHeader(pThis, &VtdTable.Dmar.Hdr, "DMAR", sizeof(ACPITBLVTD), ACPI_DMAR_REVISION);
3489
3490 /* DMAR. */
3491 uint8_t cPhysAddrBits;
3492 uint8_t cLinearAddrBits;
3493 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cPhysAddrBits, &cLinearAddrBits);
3494 Assert(cPhysAddrBits > 0); NOREF(cLinearAddrBits);
3495 VtdTable.Dmar.uHostAddrWidth = cPhysAddrBits - 1;
3496 VtdTable.Dmar.fFlags = DMAR_ACPI_DMAR_FLAGS;
3497
3498 /* DRHD. */
3499 VtdTable.Drhd.cbLength = sizeof(ACPIDRHD);
3500 VtdTable.Drhd.fFlags = ACPI_DRHD_F_INCLUDE_PCI_ALL;
3501 VtdTable.Drhd.uRegBaseAddr = DMAR_MMIO_BASE_PHYSADDR;
3502
3503 /* Device Scopes: I/O APIC. */
3504 if (pThis->u8UseIOApic)
3505 {
3506 uint8_t const uIoApicBus = 0;
3507 uint8_t const uIoApicDev = RT_HI_U16(pThis->u32SbIoApicPciAddress);
3508 uint8_t const uIoApicFn = RT_LO_U16(pThis->u32SbIoApicPciAddress);
3509
3510 VtdTable.DevScopeIoApic.uType = ACPIDMARDEVSCOPE_TYPE_IOAPIC;
3511 VtdTable.DevScopeIoApic.cbLength = sizeof(ACPIDMARDEVSCOPE);
3512 VtdTable.DevScopeIoApic.idEnum = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3513 VtdTable.DevScopeIoApic.uStartBusNum = uIoApicBus;
3514 VtdTable.DevScopeIoApic.Path.uDevice = uIoApicDev;
3515 VtdTable.DevScopeIoApic.Path.uFunction = uIoApicFn;
3516
3517 VtdTable.Drhd.cbLength += sizeof(VtdTable.DevScopeIoApic);
3518 }
3519
3520 /* Finally, compute checksum. */
3521 VtdTable.Dmar.Hdr.u8Checksum = acpiR3Checksum(&VtdTable, sizeof(VtdTable));
3522
3523 /* Plant the ACPI table. */
3524 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&VtdTable, sizeof(VtdTable));
3525}
3526#endif /* VBOX_WITH_IOMMU_INTEL */
3527
3528
3529#ifdef VBOX_WITH_TPM
3530/**
3531 * Plant the TPM 2.0 ACPI descriptor.
3532 */
3533static void acpiR3SetupTpm(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3534{
3535 if (pThis->enmTpmMode == ACPITPMMODE_TIS_1_2)
3536 {
3537 ACPITBLTCPA TcpaTbl;
3538 RT_ZERO(TcpaTbl);
3539
3540 acpiR3PrepareHeader(pThis, &TcpaTbl.Hdr, "TCPA", sizeof(TcpaTbl), ACPI_TCPA_REVISION);
3541
3542 TcpaTbl.u16PlatCls = ACPI_TCPA_PLAT_CLS_CLIENT;
3543 TcpaTbl.u32Laml = ACPI_TCPA_LAML_SZ;
3544 TcpaTbl.u64Lasa = addr + sizeof(TcpaTbl);
3545
3546 /* Finally, compute checksum. */
3547 TcpaTbl.Hdr.u8Checksum = acpiR3Checksum(&TcpaTbl, sizeof(TcpaTbl));
3548
3549 /* Plant the ACPI table. */
3550 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&TcpaTbl, sizeof(TcpaTbl));
3551 }
3552 else
3553 {
3554 ACPITBLTPM20 Tpm2Tbl;
3555 RT_ZERO(Tpm2Tbl);
3556
3557 acpiR3PrepareHeader(pThis, &Tpm2Tbl.Hdr, "TPM2", sizeof(ACPITBLTPM20), ACPI_TPM20_REVISION);
3558
3559 switch (pThis->enmTpmMode)
3560 {
3561 case ACPITPMMODE_CRB_2_0:
3562 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_CRB;
3563 Tpm2Tbl.u64BaseAddrCrbOrFifo = pThis->GCPhysTpmMmio;
3564 break;
3565 case ACPITPMMODE_FIFO_2_0:
3566 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_TIS12;
3567 break;
3568 case ACPITPMMODE_TIS_1_2: /* Handled above. */
3569 case ACPITPMMODE_DISABLED: /* Should never be called with the TPM disabled. */
3570 default:
3571 AssertFailed();
3572 }
3573
3574 Tpm2Tbl.u16PlatCls = ACPITBL_TPM20_PLAT_CLS_CLIENT;
3575
3576 /* Finally, compute checksum. */
3577 Tpm2Tbl.Hdr.u8Checksum = acpiR3Checksum(&Tpm2Tbl, sizeof(Tpm2Tbl));
3578
3579 /* Plant the ACPI table. */
3580 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Tpm2Tbl, sizeof(Tpm2Tbl));
3581 }
3582}
3583#endif
3584
3585
3586/**
3587 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3588 * descriptor.
3589 *
3590 * @param pDevIns The device instance.
3591 * @param pThis The ACPI shared instance data.
3592 * @param GCPhysDst Where to plant it.
3593 */
3594static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3595{
3596 struct
3597 {
3598 ACPITBLMCFG hdr;
3599 ACPITBLMCFGENTRY entry;
3600 } tbl;
3601 uint8_t u8StartBus = 0;
3602 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3603
3604 RT_ZERO(tbl);
3605
3606 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3607 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3608 tbl.entry.u8StartBus = u8StartBus;
3609 tbl.entry.u8EndBus = u8EndBus;
3610 // u16PciSegmentGroup must match _SEG in ACPI table
3611
3612 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3613
3614 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3615}
3616
3617/**
3618 * Used by acpiR3PlantTables and acpiConstruct.
3619 *
3620 * @returns Guest memory address.
3621 */
3622static uint32_t apicR3FindRsdpSpace(void)
3623{
3624 return 0xe0000;
3625}
3626
3627/**
3628 * Called by acpiR3Construct to read and allocate a custom ACPI table
3629 *
3630 * @param pDevIns The device instance.
3631 * @param ppu8CustBin Address to receive the address of the table
3632 * @param pcbCustBin Address to receive the size of the the table.
3633 * @param pszCustBinFile
3634 * @param cbBufAvail Maximum space in bytes available for the custom
3635 * table (including header).
3636 */
3637static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3638 char *pszCustBinFile, uint32_t cbBufAvail)
3639{
3640 RTFILE FileCUSTBin;
3641 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3642 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3643 if (RT_SUCCESS(rc))
3644 {
3645 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3646 if (RT_SUCCESS(rc))
3647 {
3648 /* The following checks should be in sync the AssertReleaseMsg's below. */
3649 if ( *pcbCustBin > cbBufAvail
3650 || *pcbCustBin < sizeof(ACPITBLHEADER))
3651 rc = VERR_TOO_MUCH_DATA;
3652
3653 /*
3654 * Allocate buffer for the custom table binary data.
3655 */
3656 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3657 if (*ppu8CustBin)
3658 {
3659 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3660 if (RT_FAILURE(rc))
3661 {
3662 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3663 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3664 *ppu8CustBin = NULL;
3665 }
3666 }
3667 else
3668 {
3669 rc = VERR_NO_MEMORY;
3670 }
3671 RTFileClose(FileCUSTBin);
3672 }
3673 }
3674 return rc;
3675}
3676
3677/**
3678 * Create the ACPI tables in guest memory.
3679 */
3680static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3681{
3682 int rc;
3683 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3684 RTGCPHYS32 GCPhysHpet = 0;
3685#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3686 RTGCPHYS32 GCPhysIommu = 0;
3687#endif
3688#ifdef VBOX_WITH_TPM
3689 RTGCPHYS32 GCPhysTpm = 0;
3690 RTGCPHYS32 GCPhysSsdtTpm = 0;
3691#endif
3692 RTGCPHYS32 GCPhysApic = 0;
3693 RTGCPHYS32 GCPhysSsdt = 0;
3694 RTGCPHYS32 GCPhysMcfg = 0;
3695 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3696 uint32_t addend = 0;
3697#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3698# ifdef VBOX_WITH_TPM
3699 RTGCPHYS32 aGCPhysRsdt[10 + MAX_CUST_TABLES];
3700 RTGCPHYS32 aGCPhysXsdt[10 + MAX_CUST_TABLES];
3701# else
3702 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3703 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3704# endif
3705#else
3706# ifdef VBOX_WITH_TPM
3707 RTGCPHYS32 aGCPhysRsdt[9 + MAX_CUST_TABLES];
3708 RTGCPHYS32 aGCPhysXsdt[9 + MAX_CUST_TABLES];
3709# else
3710 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3711 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3712# endif
3713#endif
3714 uint32_t cAddr;
3715 uint32_t iMadt = 0;
3716 uint32_t iHpet = 0;
3717#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3718 uint32_t iIommu = 0;
3719#endif
3720#ifdef VBOX_WITH_TPM
3721 uint32_t iTpm = 0;
3722 uint32_t iSsdtTpm = 0;
3723#endif
3724 uint32_t iSsdt = 0;
3725 uint32_t iMcfg = 0;
3726 uint32_t iCust = 0;
3727 size_t cbRsdt = sizeof(ACPITBLHEADER);
3728 size_t cbXsdt = sizeof(ACPITBLHEADER);
3729
3730 cAddr = 1; /* FADT */
3731 if (pThis->u8UseIOApic)
3732 iMadt = cAddr++; /* MADT */
3733
3734 if (pThis->fUseHpet)
3735 iHpet = cAddr++; /* HPET */
3736
3737#ifdef VBOX_WITH_IOMMU_AMD
3738 if (pThis->fUseIommuAmd)
3739 iIommu = cAddr++; /* IOMMU (AMD) */
3740#endif
3741
3742#ifdef VBOX_WITH_IOMMU_INTEL
3743 if (pThis->fUseIommuIntel)
3744 iIommu = cAddr++; /* IOMMU (Intel) */
3745#endif
3746
3747#ifdef VBOX_WITH_TPM
3748 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3749 {
3750 iTpm = cAddr++; /* TPM device */
3751 iSsdtTpm = cAddr++;
3752 }
3753#endif
3754
3755 if (pThis->fUseMcfg)
3756 iMcfg = cAddr++; /* MCFG */
3757
3758 if (pThis->cCustTbls > 0)
3759 {
3760 iCust = cAddr; /* CUST */
3761 cAddr += pThis->cCustTbls;
3762 }
3763
3764 iSsdt = cAddr++; /* SSDT */
3765
3766 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3767 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3768
3769 cbRsdt += cAddr * sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3770 cbXsdt += cAddr * sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3771
3772 /*
3773 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3774 * The latter starts never below 4G.
3775 */
3776 PVM pVM = PDMDevHlpGetVM(pDevIns);
3777 uint32_t cbBelow4GB = MMR3PhysGetRamSizeBelow4GB(pVM);
3778 uint64_t const cbAbove4GB = MMR3PhysGetRamSizeAbove4GB(pVM);
3779
3780 pThis->u64RamSize = MMR3PhysGetRamSize(pVM);
3781 if (pThis->fPciPref64Enabled)
3782 {
3783 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3784 if (pThis->u64PciPref64Max > u64PciPref64Min)
3785 {
3786 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3787 pThis->u64PciPref64Min = u64PciPref64Min;
3788 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3789 u64PciPref64Min, pThis->u64PciPref64Max-1));
3790 }
3791 else
3792 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3793 u64PciPref64Min, pThis->u64PciPref64Max-1));
3794 }
3795 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3796 {
3797 /* Note: This is also enforced by DevPcBios.cpp. */
3798 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3799 cbBelow4GB = UINT32_C(0xfe000000);
3800 }
3801 pThis->cbRamLow = cbBelow4GB;
3802
3803 GCPhysCur = 0;
3804 GCPhysRsdt = GCPhysCur;
3805
3806 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3807 GCPhysXsdt = GCPhysCur;
3808
3809 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3810 GCPhysFadtAcpi1 = GCPhysCur;
3811
3812 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3813 GCPhysFadtAcpi2 = GCPhysCur;
3814
3815 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3816 GCPhysFacs = GCPhysCur;
3817
3818 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3819 if (pThis->u8UseIOApic)
3820 {
3821 GCPhysApic = GCPhysCur;
3822 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3823 }
3824 if (pThis->fUseHpet)
3825 {
3826 GCPhysHpet = GCPhysCur;
3827 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3828 }
3829#ifdef VBOX_WITH_IOMMU_AMD
3830 if (pThis->fUseIommuAmd)
3831 {
3832 GCPhysIommu = GCPhysCur;
3833 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3834 }
3835#endif
3836#ifdef VBOX_WITH_IOMMU_INTEL
3837 if (pThis->fUseIommuIntel)
3838 {
3839 GCPhysIommu = GCPhysCur;
3840 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLVTD), 16);
3841 }
3842#endif
3843#ifdef VBOX_WITH_TPM
3844 void *pvSsdtTpmCode = NULL;
3845 size_t cbSsdtTpm = 0;
3846
3847 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3848 {
3849 GCPhysTpm = GCPhysCur;
3850
3851 if (pThis->enmTpmMode == ACPITPMMODE_TIS_1_2)
3852 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLTCPA) + ACPI_TCPA_LAML_SZ, 16);
3853 else
3854 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLTPM20), 16);
3855
3856 rc = acpiPrepareTpmSsdt(pDevIns, &pvSsdtTpmCode, &cbSsdtTpm);
3857 if (RT_FAILURE(rc))
3858 return rc;
3859
3860 GCPhysSsdtTpm = GCPhysCur;
3861 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdtTpm, 16);
3862 }
3863#endif
3864
3865 if (pThis->fUseMcfg)
3866 {
3867 GCPhysMcfg = GCPhysCur;
3868 /* Assume one entry */
3869 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3870 }
3871
3872 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3873 {
3874 aGCPhysCust[i] = GCPhysCur;
3875 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3876 }
3877
3878 void *pvSsdtCode = NULL;
3879 size_t cbSsdt = 0;
3880 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3881 if (RT_FAILURE(rc))
3882 return rc;
3883
3884 GCPhysSsdt = GCPhysCur;
3885 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3886
3887 GCPhysDsdt = GCPhysCur;
3888
3889 void *pvDsdtCode = NULL;
3890 size_t cbDsdt = 0;
3891 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3892 if (RT_FAILURE(rc))
3893 return rc;
3894
3895 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3896
3897 if (GCPhysCur > 0x10000)
3898 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3899 N_("Error: ACPI tables bigger than 64KB"));
3900
3901 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3902 addend = pThis->cbRamLow - 0x10000;
3903 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3904 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3905 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3906 if (pThis->u8UseIOApic)
3907 Log((" MADT 0x%08X", GCPhysApic + addend));
3908 if (pThis->fUseHpet)
3909 Log((" HPET 0x%08X", GCPhysHpet + addend));
3910 if (pThis->fUseMcfg)
3911 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3912 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3913 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3914 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3915 Log(("\n"));
3916
3917 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3918 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3919 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3920 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3921 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3922
3923 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3924 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3925 if (pThis->u8UseIOApic)
3926 {
3927 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3928 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3929 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3930 }
3931 if (pThis->fUseHpet)
3932 {
3933 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3934 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3935 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3936 }
3937#ifdef VBOX_WITH_IOMMU_AMD
3938 if (pThis->fUseIommuAmd)
3939 {
3940 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommu + addend);
3941 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3942 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3943 }
3944#endif
3945#ifdef VBOX_WITH_IOMMU_INTEL
3946 if (pThis->fUseIommuIntel)
3947 {
3948 acpiR3SetupIommuIntel(pDevIns, pThis, GCPhysIommu + addend);
3949 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3950 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3951 }
3952#endif
3953#ifdef VBOX_WITH_TPM
3954 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3955 {
3956 acpiR3SetupTpm(pDevIns, pThis, GCPhysTpm + addend);
3957 aGCPhysRsdt[iTpm] = GCPhysTpm + addend;
3958 aGCPhysXsdt[iTpm] = GCPhysTpm + addend;
3959
3960 acpiR3SetupTpmSsdt(pDevIns, GCPhysSsdtTpm + addend, pvSsdtTpmCode, cbSsdtTpm);
3961 acpiCleanupTpmSsdt(pDevIns, pvSsdtTpmCode);
3962 aGCPhysRsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3963 aGCPhysXsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3964 }
3965#endif
3966
3967 if (pThis->fUseMcfg)
3968 {
3969 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3970 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3971 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3972 }
3973 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3974 {
3975 AssertBreak(i < MAX_CUST_TABLES);
3976 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3977 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3978 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3979 uint8_t* pSig = pThisCC->apu8CustBin[i];
3980 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3981 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3982 }
3983
3984 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3985 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3986 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3987 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3988
3989 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3990 if (RT_FAILURE(rc))
3991 return rc;
3992 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
3993}
3994
3995/**
3996 * @callback_method_impl{FNPCICONFIGREAD}
3997 */
3998static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
3999 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
4000{
4001 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4002 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
4003 return rcStrict;
4004}
4005
4006/**
4007 * @callback_method_impl{FNPCICONFIGWRITE}
4008 */
4009static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
4010 uint32_t uAddress, unsigned cb, uint32_t u32Value)
4011{
4012 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4013 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4014
4015 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
4016 DEVACPI_LOCK_R3(pDevIns, pThis);
4017
4018 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
4019 {
4020 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
4021 u32Value = SCI_INT;
4022 }
4023
4024 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4025
4026 /* Assume that the base address is only changed when the corresponding
4027 * hardware functionality is disabled. The IO region is mapped when the
4028 * functionality is enabled by the guest. */
4029
4030 if (uAddress == PMREGMISC)
4031 {
4032 RTIOPORT NewIoPortBase = 0;
4033 /* Check Power Management IO Space Enable (PMIOSE) bit */
4034 if (pPciDev->abConfig[PMREGMISC] & 0x01)
4035 {
4036 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
4037 NewIoPortBase &= 0xffc0;
4038 }
4039
4040 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
4041 AssertRC(rc);
4042 }
4043
4044 if (uAddress == SMBHSTCFG)
4045 {
4046 RTIOPORT NewIoPortBase = 0;
4047 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
4048 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
4049 {
4050 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
4051 NewIoPortBase &= 0xfff0;
4052 }
4053
4054 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
4055 AssertRC(rc);
4056 }
4057
4058 DEVACPI_UNLOCK(pDevIns, pThis);
4059 return rcStrict;
4060}
4061
4062/**
4063 * Attach a new CPU.
4064 *
4065 * @returns VBox status code.
4066 * @param pDevIns The device instance.
4067 * @param iLUN The logical unit which is being attached.
4068 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4069 *
4070 * @remarks This code path is not used during construction.
4071 */
4072static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4073{
4074 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4075 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4076 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4077
4078 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4079 ("Hot-plug flag is not set\n"),
4080 VERR_NOT_SUPPORTED);
4081 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
4082
4083 /* Check if it was already attached */
4084 int rc = VINF_SUCCESS;
4085 DEVACPI_LOCK_R3(pDevIns, pThis);
4086 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4087 {
4088 PPDMIBASE IBaseTmp;
4089 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4090 if (RT_SUCCESS(rc))
4091 {
4092 /* Enable the CPU */
4093 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
4094
4095 /*
4096 * Lock the CPU because we don't know if the guest will use it or not.
4097 * Prevents ejection while the CPU is still used
4098 */
4099 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
4100 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
4101 pThis->u32CpuEvent = iLUN;
4102
4103 /* Notify the guest */
4104 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4105 }
4106 }
4107 DEVACPI_UNLOCK(pDevIns, pThis);
4108 return rc;
4109}
4110
4111/**
4112 * Detach notification.
4113 *
4114 * @param pDevIns The device instance.
4115 * @param iLUN The logical unit which is being detached.
4116 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4117 */
4118static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4119{
4120 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4121
4122 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4123
4124 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4125 ("Hot-plug flag is not set\n"));
4126
4127 /* Check if it was already detached */
4128 DEVACPI_LOCK_R3(pDevIns, pThis);
4129 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4130 {
4131 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
4132 {
4133 /* Disable the CPU */
4134 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
4135 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
4136 pThis->u32CpuEvent = iLUN;
4137
4138 /* Notify the guest */
4139 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4140 }
4141 else
4142 AssertMsgFailed(("CPU is still locked by the guest\n"));
4143 }
4144 DEVACPI_UNLOCK(pDevIns, pThis);
4145}
4146
4147/**
4148 * @interface_method_impl{PDMDEVREG,pfnResume}
4149 */
4150static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
4151{
4152 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4153 if (pThis->fSetWakeupOnResume)
4154 {
4155 Log(("acpiResume: setting WAK_STS\n"));
4156 pThis->fSetWakeupOnResume = false;
4157 pThis->pm1a_sts |= WAK_STS;
4158 }
4159}
4160
4161/**
4162 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
4163 */
4164static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
4165{
4166 RT_NOREF(enmCtx);
4167 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4168 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4169 acpiR3PlantTables(pDevIns, pThis, pThisCC);
4170}
4171
4172/**
4173 * @interface_method_impl{PDMDEVREG,pfnReset}
4174 */
4175static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
4176{
4177 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4178 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4179
4180 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
4181 acpiSetIrq(pDevIns, 0);
4182
4183 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4184 pThis->pm1a_en = 0;
4185 pThis->pm1a_sts = 0;
4186 pThis->pm1a_ctl = 0;
4187 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4188 pThis->uPmTimerVal = 0;
4189 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4190 pThis->uPmTimeOld = pThis->uPmTimerVal;
4191 pThis->uBatteryIndex = 0;
4192 pThis->uSystemInfoIndex = 0;
4193 pThis->gpe0_en = 0;
4194 pThis->gpe0_sts = 0;
4195 pThis->uSleepState = 0;
4196 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4197
4198 /* Real device behavior is resetting only the PM controller state,
4199 * but we're additionally doing the job of the BIOS. */
4200 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
4201 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4202
4203 /* Reset SMBus base and PCI config space in addition to the SMBus controller
4204 * state. Real device behavior is only the SMBus controller state reset,
4205 * but we're additionally doing the job of the BIOS. */
4206 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
4207 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4208 acpiR3SMBusResetDevice(pThis);
4209}
4210
4211/**
4212 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4213 */
4214static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
4215{
4216 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4217 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4218 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4219
4220 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4221 {
4222 if (pThisCC->apu8CustBin[i])
4223 {
4224 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
4225 pThisCC->apu8CustBin[i] = NULL;
4226 }
4227 }
4228 return VINF_SUCCESS;
4229}
4230
4231/**
4232 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4233 */
4234static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4235{
4236 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4237 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4238 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4239 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4240
4241 /*
4242 * Init data and set defaults.
4243 */
4244 /** @todo move more of the code up! */
4245
4246 pThisCC->pDevIns = pDevIns;
4247 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
4248 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
4249 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
4250 pThis->u32CpuEventType = 0;
4251 pThis->u32CpuEvent = UINT32_C(0xffffffff);
4252
4253 /* The first CPU can't be attached/detached */
4254 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
4255 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
4256
4257 /* IBase */
4258 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
4259 /* IACPIPort */
4260 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
4261 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
4262 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
4263 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
4264 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
4265 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
4266 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
4267
4268 /*
4269 * Set the default critical section to NOP (related to the PM timer).
4270 */
4271 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4272 AssertRCReturn(rc, rc);
4273
4274 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
4275 AssertRCReturn(rc, rc);
4276
4277 /*
4278 * Validate and read the configuration.
4279 */
4280 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
4281 "IOAPIC"
4282 "|NumCPUs"
4283 "|HpetEnabled"
4284 "|McfgEnabled"
4285 "|McfgBase"
4286 "|McfgLength"
4287 "|PciPref64Enabled"
4288 "|PciPref64LimitGB"
4289 "|SmcEnabled"
4290 "|FdcEnabled"
4291 "|ShowRtc"
4292 "|ShowCpu"
4293 "|NicPciAddress"
4294 "|AudioPciAddress"
4295 "|NvmePciAddress"
4296 "|IocPciAddress"
4297 "|HostBusPciAddress"
4298 "|EnableSuspendToDisk"
4299 "|PowerS1Enabled"
4300 "|PowerS4Enabled"
4301 "|CpuHotPlug"
4302 "|AmlFilePath"
4303 "|Serial0IoPortBase"
4304 "|Serial1IoPortBase"
4305 "|Serial2IoPortBase"
4306 "|Serial3IoPortBase"
4307 "|Serial0Irq"
4308 "|Serial1Irq"
4309 "|Serial2Irq"
4310 "|Serial3Irq"
4311 "|AcpiOemId"
4312 "|AcpiCreatorId"
4313 "|AcpiCreatorRev"
4314 "|CustomTable"
4315 "|CustomTable0"
4316 "|CustomTable1"
4317 "|CustomTable2"
4318 "|CustomTable3"
4319 "|Parallel0IoPortBase"
4320 "|Parallel1IoPortBase"
4321 "|Parallel0Irq"
4322 "|Parallel1Irq"
4323 "|IommuIntelEnabled"
4324 "|IommuAmdEnabled"
4325 "|IommuPciAddress"
4326 "|SbIoApicPciAddress"
4327 "|TpmMode"
4328 "|TpmMmioAddress"
4329 "|SsdtTpmFilePath"
4330 , "");
4331
4332 /* query whether we are supposed to present an IOAPIC */
4333 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
4334 if (RT_FAILURE(rc))
4335 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
4336
4337 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
4338 if (RT_FAILURE(rc))
4339 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
4340
4341 /* query whether we are supposed to present an FDC controller */
4342 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
4343 if (RT_FAILURE(rc))
4344 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
4345
4346 /* query whether we are supposed to present HPET */
4347 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
4348 if (RT_FAILURE(rc))
4349 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
4350 /* query MCFG configuration */
4351 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
4352 if (RT_FAILURE(rc))
4353 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4354 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4355 if (RT_FAILURE(rc))
4356 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4357 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4358
4359 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4360 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4361 if (RT_FAILURE(rc))
4362 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4363
4364 /* query the limit of the the 64-bit prefetchable memory window */
4365 uint64_t u64PciPref64MaxGB;
4366 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4367 if (RT_FAILURE(rc))
4368 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4369 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4370
4371 /* query whether we are supposed to present SMC */
4372 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4373 if (RT_FAILURE(rc))
4374 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4375
4376 /* query whether we are supposed to present RTC object */
4377 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4378 if (RT_FAILURE(rc))
4379 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4380
4381 /* query whether we are supposed to present CPU objects */
4382 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4383 if (RT_FAILURE(rc))
4384 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4385
4386 /* query primary NIC PCI address (GIGE) */
4387 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4388 if (RT_FAILURE(rc))
4389 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4390
4391 /* query HD Audio PCI address (HDAA) */
4392 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4393 if (RT_FAILURE(rc))
4394 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4395
4396 /* query NVMe PCI address (NVMA) */
4397 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4398 if (RT_FAILURE(rc))
4399 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4400
4401 /* query IO controller (southbridge) PCI address */
4402 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4403 if (RT_FAILURE(rc))
4404 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4405
4406 /* query host bus controller PCI address */
4407 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4408 if (RT_FAILURE(rc))
4409 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4410
4411 /* query whether S1 power state should be exposed */
4412 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4413 if (RT_FAILURE(rc))
4414 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4415
4416 /* query whether S4 power state should be exposed */
4417 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4418 if (RT_FAILURE(rc))
4419 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4420
4421 /* query whether S1 power state should save the VM state */
4422 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4423 if (RT_FAILURE(rc))
4424 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4425
4426 /* query whether we are allow CPU hot plugging */
4427 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4428 if (RT_FAILURE(rc))
4429 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4430
4431 /* query serial info */
4432 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4433 if (RT_FAILURE(rc))
4434 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4435
4436 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4437 if (RT_FAILURE(rc))
4438 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4439
4440 /* Serial 1 is enabled, get config data */
4441 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4442 if (RT_FAILURE(rc))
4443 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4444
4445 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4446 if (RT_FAILURE(rc))
4447 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4448
4449 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4450 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4451 if (RT_FAILURE(rc))
4452 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4453
4454 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4455 if (RT_FAILURE(rc))
4456 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4457
4458 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4459 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4460 if (RT_FAILURE(rc))
4461 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4462
4463 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4464 if (RT_FAILURE(rc))
4465 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4466 /*
4467 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4468 * the corresponding parallel port is not enabled.
4469 */
4470 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4471 if (RT_FAILURE(rc))
4472 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4473
4474 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4475 if (RT_FAILURE(rc))
4476 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4477
4478 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4479 if (RT_FAILURE(rc))
4480 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4481
4482 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4483 if (RT_FAILURE(rc))
4484 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4485
4486#ifdef VBOX_WITH_IOMMU_AMD
4487 /* Query whether an IOMMU (AMD) is enabled. */
4488 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommuAmd, false);
4489 if (RT_FAILURE(rc))
4490 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdEnabled\""));
4491
4492 if (pThis->fUseIommuAmd)
4493 {
4494 /* Query IOMMU AMD address (IOMA). */
4495 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4496 if (RT_FAILURE(rc))
4497 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4498
4499 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4500 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4501 if (RT_FAILURE(rc))
4502 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4503
4504 /* Warn if the IOMMU Address is at the PCI host-bridge address. */
4505 /** @todo We should eventually not assign the IOMMU at this address, see
4506 * @bugref{9654#c53}. */
4507 if (!pThis->u32IommuPciAddress)
4508 LogRel(("ACPI: Warning! AMD IOMMU assigned the PCI host bridge address.\n"));
4509
4510 /* Warn if the IOAPIC is not at the expected address. */
4511 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4512 {
4513 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4514 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4515 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4516 }
4517 }
4518#endif
4519
4520#ifdef VBOX_WITH_IOMMU_INTEL
4521 /* Query whether an IOMMU (Intel) is enabled. */
4522 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuIntelEnabled", &pThis->fUseIommuIntel, false);
4523 if (RT_FAILURE(rc))
4524 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuIntelEnabled\""));
4525
4526 if (pThis->fUseIommuIntel)
4527 {
4528 /* Query IOMMU Intel address. */
4529 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4530 if (RT_FAILURE(rc))
4531 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4532
4533 /* Get the reserved I/O APIC PCI address (required when an Intel IOMMU is configured). */
4534 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4535 if (RT_FAILURE(rc))
4536 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4537
4538 /* Warn if the IOAPIC is not at the expected address. */
4539 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4540 {
4541 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an Intel IOMMU is present.\n",
4542 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4543 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4544 }
4545 }
4546#endif
4547
4548 /* Don't even think about enabling an Intel and an AMD IOMMU at the same time! */
4549 if ( pThis->fUseIommuAmd
4550 && pThis->fUseIommuIntel)
4551 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Cannot enable Intel and AMD IOMMU simultaneously!"));
4552
4553#ifdef VBOX_WITH_TPM
4554 char szTpmMode[64]; RT_ZERO(szTpmMode);
4555
4556 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "TpmMode", &szTpmMode[0], RT_ELEMENTS(szTpmMode) - 1, "disabled");
4557 if (RT_FAILURE(rc))
4558 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMode\""));
4559
4560 if (!RTStrICmp(szTpmMode, "disabled"))
4561 pThis->enmTpmMode = ACPITPMMODE_DISABLED;
4562 else if (!RTStrICmp(szTpmMode, "tis1.2"))
4563 pThis->enmTpmMode = ACPITPMMODE_TIS_1_2;
4564 else if (!RTStrICmp(szTpmMode, "crb2.0"))
4565 pThis->enmTpmMode = ACPITPMMODE_CRB_2_0;
4566 else if (!RTStrICmp(szTpmMode, "fifo2.0"))
4567 pThis->enmTpmMode = ACPITPMMODE_FIFO_2_0;
4568 else
4569 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER, N_("Configuration error: Value of \"TpmMode\" is not known"));
4570
4571 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "TpmMmioAddress", (uint64_t *)&pThis->GCPhysTpmMmio, ACPI_TPM_MMIO_BASE_DEFAULT);
4572 if (RT_FAILURE(rc))
4573 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMmioAddress\""));
4574#endif
4575
4576 /* Try to attach the other CPUs */
4577 for (unsigned i = 1; i < pThis->cCpus; i++)
4578 {
4579 if (pThis->fCpuHotPlug)
4580 {
4581 PPDMIBASE IBaseTmp;
4582 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4583
4584 if (RT_SUCCESS(rc))
4585 {
4586 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4587 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4588 Log(("acpi: Attached CPU %u\n", i));
4589 }
4590 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4591 Log(("acpi: CPU %u not attached yet\n", i));
4592 else
4593 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4594 }
4595 else
4596 {
4597 /* CPU is always attached if hot-plug is not enabled. */
4598 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4599 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4600 }
4601 }
4602
4603 char szOemId[16];
4604 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4605 if (RT_FAILURE(rc))
4606 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4607 size_t cchOemId = strlen(szOemId);
4608 if (cchOemId > 6)
4609 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4610 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4611 memcpy(pThis->au8OemId, szOemId, cchOemId);
4612
4613 char szCreatorId[16];
4614 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4615 if (RT_FAILURE(rc))
4616 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4617 size_t cchCreatorId = strlen(szCreatorId);
4618 if (cchCreatorId > 4)
4619 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4620 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4621 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4622
4623 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4624 if (RT_FAILURE(rc))
4625 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4626
4627 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4628
4629 /*
4630 * Load custom ACPI tables.
4631 */
4632 /* Total space available for custom ACPI tables */
4633 /** @todo define as appropriate, remove as a magic number, and document
4634 * limitation in product manual */
4635 uint32_t cbBufAvail = 3072;
4636 pThis->cCustTbls = 0;
4637
4638 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4639 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4640 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4641 {
4642 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4643
4644 /*
4645 * Get the custom table binary file name.
4646 */
4647 char *pszCustBinFile = NULL;
4648 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4649 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4650 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4651 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4652 {
4653 rc = VINF_SUCCESS;
4654 pszCustBinFile = NULL;
4655 }
4656 else if (RT_FAILURE(rc))
4657 return PDMDEV_SET_ERROR(pDevIns, rc,
4658 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4659 else if (!*pszCustBinFile)
4660 {
4661 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4662 pszCustBinFile = NULL;
4663 }
4664
4665 /*
4666 * Determine the custom table binary size, open specified file in the process.
4667 */
4668 if (pszCustBinFile)
4669 {
4670 uint32_t idxCust = pThis->cCustTbls;
4671 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4672 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4673 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4674 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4675 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4676 if (RT_FAILURE(rc))
4677 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4678 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4679
4680 /* Update custom OEM attributes based on custom table */
4681 /** @todo is it intended for custom tables to overwrite user provided values above? */
4682 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4683 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4684 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4685 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4686 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4687 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4688
4689 pThis->cCustTbls++;
4690 AssertBreak(pThis->cCustTbls <= MAX_CUST_TABLES);
4691 }
4692 }
4693
4694 /* Set default PM port base */
4695 pThis->uPmIoPortBase = PM_PORT_BASE;
4696
4697 /* Set default SMBus port base */
4698 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4699
4700 /*
4701 * FDC and SMC try to use the same non-shareable interrupt (6),
4702 * enable only one device.
4703 */
4704 if (pThis->fUseSmc)
4705 pThis->fUseFdc = false;
4706
4707 /*
4708 * Plant ACPI tables.
4709 */
4710 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4711 * au8RSDPPage here. However, there should be no harm in doing it
4712 * twice, so the lazy bird is taking the quick way out for now. */
4713 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4714 if (!GCPhysRsdp)
4715 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4716
4717 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4718 AssertRCReturn(rc, rc);
4719
4720 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4721 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4722 AssertRCReturn(rc, rc);
4723
4724 /*
4725 * Create the PM I/O ports. These can be unmapped and remapped.
4726 */
4727 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4728 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4729 AssertRCReturn(rc, rc);
4730 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4731 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4732 AssertRCReturn(rc, rc);
4733 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4734 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4735 AssertRCReturn(rc, rc);
4736 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4737 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4738 AssertRCReturn(rc, rc);
4739 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4740 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4741 AssertRCReturn(rc, rc);
4742 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4743 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4744 AssertRCReturn(rc, rc);
4745 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4746 AssertRCReturn(rc, rc);
4747
4748 /*
4749 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4750 */
4751 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4752 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4753 AssertRCReturn(rc, rc);
4754 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4755 AssertRCReturn(rc, rc);
4756
4757 /*
4758 * Create and map the fixed I/O ports.
4759 */
4760 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4761 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4762 AssertRCReturn(rc, rc);
4763#ifdef DEBUG_ACPI
4764 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4765 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4766 AssertRCReturn(rc, rc);
4767 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4768 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4769 AssertRCReturn(rc, rc);
4770#endif
4771 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4772 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4773 AssertRCReturn(rc, rc);
4774 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4775 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4776 AssertRCReturn(rc, rc);
4777 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4778 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4779 AssertRCReturn(rc, rc);
4780 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4781 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4782 AssertRCReturn(rc, rc);
4783 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4784 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4785 AssertRCReturn(rc, rc);
4786
4787 /*
4788 * Create the PM timer.
4789 */
4790 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4791 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "ACPI PM", &pThis->hPmTimer);
4792 AssertRCReturn(rc, rc);
4793
4794 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4795 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4796 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4797 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4798
4799 /*
4800 * Set up the PCI device.
4801 */
4802 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4803 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4804
4805 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4806 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4807
4808 /* See p. 50 of PIIX4 manual */
4809 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4810 PDMPciDevSetStatus(pPciDev, 0x0280);
4811
4812 PDMPciDevSetRevisionId(pPciDev, 0x08);
4813
4814 PDMPciDevSetClassProg(pPciDev, 0x00);
4815 PDMPciDevSetClassSub(pPciDev, 0x80);
4816 PDMPciDevSetClassBase(pPciDev, 0x06);
4817
4818 PDMPciDevSetHeaderType(pPciDev, 0x80);
4819
4820 PDMPciDevSetBIST(pPciDev, 0x00);
4821
4822 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4823 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4824
4825 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4826 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4827
4828 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4829 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4830 acpiR3SMBusResetDevice(pThis);
4831
4832 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4833 AssertRCReturn(rc, rc);
4834
4835 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4836 AssertRCReturn(rc, rc);
4837
4838 /*
4839 * Register the saved state.
4840 */
4841 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4842 AssertRCReturn(rc, rc);
4843
4844 /*
4845 * Get the corresponding connector interface
4846 */
4847 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4848 if (RT_SUCCESS(rc))
4849 {
4850 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4851 if (!pThisCC->pDrv)
4852 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4853 }
4854 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4855 {
4856 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4857 rc = VINF_SUCCESS;
4858 }
4859 else
4860 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4861
4862 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4863
4864 return rc;
4865}
4866
4867#else /* !IN_RING3 */
4868
4869/**
4870 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4871 */
4872static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4873{
4874 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4875 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4876
4877 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4878 AssertRCReturn(rc, rc);
4879
4880 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4881 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4882 AssertRCReturn(rc, rc);
4883
4884 return VINF_SUCCESS;
4885}
4886
4887#endif /* !IN_RING3 */
4888
4889/**
4890 * The device registration structure.
4891 */
4892const PDMDEVREG g_DeviceACPI =
4893{
4894 /* .u32Version = */ PDM_DEVREG_VERSION,
4895 /* .uReserved0 = */ 0,
4896 /* .szName = */ "acpi",
4897 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4898 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4899 /* .cMaxInstances = */ ~0U,
4900 /* .uSharedVersion = */ 42,
4901 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4902 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4903 /* .cbInstanceRC = */ 0,
4904 /* .cMaxPciDevices = */ 1,
4905 /* .cMaxMsixVectors = */ 0,
4906 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4907#if defined(IN_RING3)
4908 /* .pszRCMod = */ "VBoxDDRC.rc",
4909 /* .pszR0Mod = */ "VBoxDDR0.r0",
4910 /* .pfnConstruct = */ acpiR3Construct,
4911 /* .pfnDestruct = */ acpiR3Destruct,
4912 /* .pfnRelocate = */ NULL,
4913 /* .pfnMemSetup = */ acpiR3MemSetup,
4914 /* .pfnPowerOn = */ NULL,
4915 /* .pfnReset = */ acpiR3Reset,
4916 /* .pfnSuspend = */ NULL,
4917 /* .pfnResume = */ acpiR3Resume,
4918 /* .pfnAttach = */ acpiR3Attach,
4919 /* .pfnDetach = */ acpiR3Detach,
4920 /* .pfnQueryInterface = */ NULL,
4921 /* .pfnInitComplete = */ NULL,
4922 /* .pfnPowerOff = */ NULL,
4923 /* .pfnSoftReset = */ NULL,
4924 /* .pfnReserved0 = */ NULL,
4925 /* .pfnReserved1 = */ NULL,
4926 /* .pfnReserved2 = */ NULL,
4927 /* .pfnReserved3 = */ NULL,
4928 /* .pfnReserved4 = */ NULL,
4929 /* .pfnReserved5 = */ NULL,
4930 /* .pfnReserved6 = */ NULL,
4931 /* .pfnReserved7 = */ NULL,
4932#elif defined(IN_RING0)
4933 /* .pfnEarlyConstruct = */ NULL,
4934 /* .pfnConstruct = */ acpiRZConstruct,
4935 /* .pfnDestruct = */ NULL,
4936 /* .pfnFinalDestruct = */ NULL,
4937 /* .pfnRequest = */ NULL,
4938 /* .pfnReserved0 = */ NULL,
4939 /* .pfnReserved1 = */ NULL,
4940 /* .pfnReserved2 = */ NULL,
4941 /* .pfnReserved3 = */ NULL,
4942 /* .pfnReserved4 = */ NULL,
4943 /* .pfnReserved5 = */ NULL,
4944 /* .pfnReserved6 = */ NULL,
4945 /* .pfnReserved7 = */ NULL,
4946#elif defined(IN_RC)
4947 /* .pfnConstruct = */ acpiRZConstruct,
4948 /* .pfnReserved0 = */ NULL,
4949 /* .pfnReserved1 = */ NULL,
4950 /* .pfnReserved2 = */ NULL,
4951 /* .pfnReserved3 = */ NULL,
4952 /* .pfnReserved4 = */ NULL,
4953 /* .pfnReserved5 = */ NULL,
4954 /* .pfnReserved6 = */ NULL,
4955 /* .pfnReserved7 = */ NULL,
4956#else
4957# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4958#endif
4959 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4960};
4961
4962#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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