DevAPIC.cpp@ 19602

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1	#ifdef VBOX
2	/* $Id: DevAPIC.cpp 19512 2009-05-08 08:08:49Z vboxsync $ */
3	/** @file
4	* Advanced Programmable Interrupt Controller (APIC) Device and
5	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* apic.c revision 1.5 @@OSETODO
27	*/
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/pdmdev.h>
34
35	#include <VBox/log.h>
36	#include <VBox/stam.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40	#include "Builtins2.h"
41	#include "vl_vbox.h"
42
43	#define MSR_IA32_APICBASE 0x1b
44	#define MSR_IA32_APICBASE_BSP (1<<8)
45	#define MSR_IA32_APICBASE_ENABLE (1<<11)
46	#ifdef VBOX
47	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48	#endif
49	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51	#ifndef EINVAL
52	# define EINVAL 1
53	#endif
54
55	#ifdef _MSC_VER
56	# pragma warning(disable:4244)
57	#endif
58
59	/** @def APIC_LOCK
60	* Acquires the PDM lock. */
61	#define APIC_LOCK(pThis, rc) \
62	do { \
63	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
64	if (rc2 != VINF_SUCCESS) \
65	return rc2; \
66	} while (0)
67
68	/** @def APIC_LOCK_VOID
69	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
70	#define APIC_LOCK_VOID(pThis, rc) \
71	do { \
72	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
73	AssertLogRelRCReturnVoid(rc2); \
74	} while (0)
75
76	/** @def APIC_UNLOCK
77	* Releases the PDM lock. */
78	#define APIC_UNLOCK(pThis) \
79	(pThis)->CTX_SUFF(pApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
80
81	/** @def IOAPIC_LOCK
82	* Acquires the PDM lock. */
83	#define IOAPIC_LOCK(pThis, rc) \
84	do { \
85	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
86	if (rc2 != VINF_SUCCESS) \
87	return rc2; \
88	} while (0)
89
90	/** @def IOAPIC_UNLOCK
91	* Releases the PDM lock. */
92	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
93
94	/** @def LAPIC_BASE
95	* Return address of first LAPIC state. */
96	#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
97
98	#define foreach_apic(dev, mask, code) \
99	do { \
100	uint32_t i; \
101	APICState* apic = LAPIC_BASE(dev); \
102	for (i = 0; i < dev->cCpus; i++) \
103	{ \
104	if (mask & (1 << (apic->id))) \
105	{ \
106	code; \
107	} \
108	apic++; \
109	} \
110	} while (0)
111
112	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
113	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
114	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
115	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
116
117	#endif /* VBOX */
118
119	/*
120	* APIC support
121	*
122	* Copyright (c) 2004-2005 Fabrice Bellard
123	*
124	* This library is free software; you can redistribute it and/or
125	* modify it under the terms of the GNU Lesser General Public
126	* License as published by the Free Software Foundation; either
127	* version 2 of the License, or (at your option) any later version.
128	*
129	* This library is distributed in the hope that it will be useful,
130	* but WITHOUT ANY WARRANTY; without even the implied warranty of
131	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
132	* Lesser General Public License for more details.
133	*
134	* You should have received a copy of the GNU Lesser General Public
135	* License along with this library; if not, write to the Free Software
136	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
137	*/
138	#ifndef VBOX
139	#include "vl.h"
140	#endif
141
142	#define DEBUG_APIC
143	#define DEBUG_IOAPIC
144
145	/* APIC Local Vector Table */
146	#define APIC_LVT_TIMER 0
147	#define APIC_LVT_THERMAL 1
148	#define APIC_LVT_PERFORM 2
149	#define APIC_LVT_LINT0 3
150	#define APIC_LVT_LINT1 4
151	#define APIC_LVT_ERROR 5
152	#define APIC_LVT_NB 6
153
154	/* APIC delivery modes */
155	#define APIC_DM_FIXED 0
156	#define APIC_DM_LOWPRI 1
157	#define APIC_DM_SMI 2
158	#define APIC_DM_NMI 4
159	#define APIC_DM_INIT 5
160	#define APIC_DM_SIPI 6
161	#define APIC_DM_EXTINT 7
162
163	/* APIC destination mode */
164	#define APIC_DESTMODE_FLAT 0xf
165	#define APIC_DESTMODE_CLUSTER 1
166
167	#define APIC_TRIGGER_EDGE 0
168	#define APIC_TRIGGER_LEVEL 1
169
170	#define APIC_LVT_TIMER_PERIODIC (1<<17)
171	#define APIC_LVT_MASKED (1<<16)
172	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
173	#define APIC_LVT_REMOTE_IRR (1<<14)
174	#define APIC_INPUT_POLARITY (1<<13)
175	#define APIC_SEND_PENDING (1<<12)
176
177	#define IOAPIC_NUM_PINS 0x18
178
179	#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181	#define APIC_SV_ENABLE (1 << 8)
182
183	#ifdef VBOX
184	#define APIC_MAX_PATCH_ATTEMPTS 100
185
186	typedef uint32_t PhysApicId;
187	typedef uint32_t LogApicId;
188	#endif
189
190	typedef struct APICState {
191	#ifndef VBOX
192	CPUState *cpu_env;
193	#endif /* !VBOX */
194	uint32_t apicbase;
195	#ifdef VBOX
196	/* Task priority register (interrupt level) */
197	uint32_t tpr;
198	/* Logical APIC id */
199	LogApicId id;
200	/* Physical APIC id */
201	PhysApicId phys_id;
202	/** @todo: is it logical or physical? Not really used anyway now. */
203	PhysApicId arb_id;
204	#else
205	uint8_t tpr;
206	uint8_t id;
207	uint8_t arb_id;
208	#endif
209	uint32_t spurious_vec;
210	uint8_t log_dest;
211	uint8_t dest_mode;
212	uint32_t isr[8]; /* in service register */
213	uint32_t tmr[8]; /* trigger mode register */
214	uint32_t irr[8]; /* interrupt request register */
215	uint32_t lvt[APIC_LVT_NB];
216	uint32_t esr; /* error register */
217	uint32_t icr[2];
218	uint32_t divide_conf;
219	int count_shift;
220	uint32_t initial_count;
221	#ifdef VBOX
222	uint32_t Alignment0;
223	#endif
224	int64_t initial_count_load_time, next_time;
225	#ifndef VBOX
226	QEMUTimer *timer;
227	struct APICState *next_apic;
228	#else
229	/** The APIC timer - R3 Ptr. */
230	PTMTIMERR3 pTimerR3;
231
232	/** The APIC timer - R0 Ptr. */
233	PTMTIMERR0 pTimerR0;
234
235	/** The APIC timer - RC Ptr. */
236	PTMTIMERRC pTimerRC;
237
238	/** Alignment */
239	uint32_t Alignment1;
240	#endif /* VBOX */
241	} APICState;
242
243	struct IOAPICState {
244	uint8_t id;
245	uint8_t ioregsel;
246
247	uint32_t irr;
248	uint64_t ioredtbl[IOAPIC_NUM_PINS];
249
250	#ifdef VBOX
251	/** The device instance - R3 Ptr. */
252	PPDMDEVINSR3 pDevInsR3;
253	/** The IOAPIC helpers - R3 Ptr. */
254	PCPDMIOAPICHLPR3 pIoApicHlpR3;
255
256	/** The device instance - R0 Ptr. */
257	PPDMDEVINSR0 pDevInsR0;
258	/** The IOAPIC helpers - R0 Ptr. */
259	PCPDMIOAPICHLPR0 pIoApicHlpR0;
260
261	/** The device instance - RC Ptr. */
262	PPDMDEVINSRC pDevInsRC;
263	/** The IOAPIC helpers - RC Ptr. */
264	PCPDMIOAPICHLPRC pIoApicHlpRC;
265
266	# ifdef VBOX_WITH_STATISTICS
267	STAMCOUNTER StatMMIOReadGC;
268	STAMCOUNTER StatMMIOReadHC;
269	STAMCOUNTER StatMMIOWriteGC;
270	STAMCOUNTER StatMMIOWriteHC;
271	STAMCOUNTER StatSetIrqGC;
272	STAMCOUNTER StatSetIrqHC;
273	# endif
274	#endif /* VBOX */
275	};
276
277	#ifdef VBOX
278	typedef struct IOAPICState IOAPICState;
279
280	typedef struct
281	{
282	/** The device instance - R3 Ptr. */
283	PPDMDEVINSR3 pDevInsR3;
284	/** The APIC helpers - R3 Ptr. */
285	PCPDMAPICHLPR3 pApicHlpR3;
286	/** LAPICs states - R3 Ptr */
287	RTR3PTR pLapicsR3;
288
289	/** The device instance - R0 Ptr. */
290	PPDMDEVINSR0 pDevInsR0;
291	/** The APIC helpers - R0 Ptr. */
292	PCPDMAPICHLPR0 pApicHlpR0;
293	/** LAPICs states - R0 Ptr */
294	RTR0PTR pLapicsR0;
295
296	/** The device instance - RC Ptr. */
297	PPDMDEVINSRC pDevInsRC;
298	/** The APIC helpers - RC Ptr. */
299	PCPDMAPICHLPRC pApicHlpRC;
300	/** LAPICs states - RC Ptr */
301	RTRCPTR pLapicsRC;
302
303	/** APIC specification version in this virtual hardware configuration. */
304	PDMAPICVERSION enmVersion;
305
306	/** Number of attempts made to optimize TPR accesses. */
307	uint32_t ulTPRPatchAttempts;
308
309	/** Number of CPUs on the system (same as LAPIC count). */
310	uint32_t cCpus;
311
312	# ifdef VBOX_WITH_STATISTICS
313	STAMCOUNTER StatMMIOReadGC;
314	STAMCOUNTER StatMMIOReadHC;
315	STAMCOUNTER StatMMIOWriteGC;
316	STAMCOUNTER StatMMIOWriteHC;
317	STAMCOUNTER StatClearedActiveIrq;
318	# endif
319	} APICDeviceInfo;
320
321	static void apic_eoi(APICDeviceInfo dev, APICState s);
322	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
323	uint8_t dest, uint8_t dest_mode,
324	uint8_t delivery_mode, uint8_t vector_num,
325	uint8_t polarity, uint8_t trigger_mode);
326	static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
327	int64_t current_time);
328	static int apic_get_arb_pri(APICState *s);
329	static int apic_get_ppr(APICState *s);
330	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
331
332
333	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
334	{
335	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
336	return LAPIC_BASE(dev) + id;
337	}
338
339	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
340	{
341	/* LAPIC's array is indexed by CPU id */
342	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
343	return getLapicById(dev, id);
344	}
345
346	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
347	{
348	/* for now we assume LAPIC physical id == CPU id */
349	return VMCPUID(s->phys_id);
350	}
351
352	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s)
353	{
354	Log2(("apic: setting interrupt flag\n"));
355	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns),
356	getCpuFromLapic(dev, s));
357	}
358
359	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
360	{
361	Log2(("apic: clear interrupt flag\n"));
362	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
363	getCpuFromLapic(dev, s));
364	}
365
366	#ifdef IN_RING3
367	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
368	{
369	Log2(("apic: send SIPI vector=%d\n", vector));
370
371	dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
372	getCpuFromLapic(dev, s),
373	vector);
374	}
375
376	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* dev, APICState *s)
377	{
378	Log2(("apic: send init IPI\n"));
379
380	dev->pApicHlpR3->pfnSendInitIpi(dev->pDevInsR3,
381	getCpuFromLapic(dev, s));
382	}
383	#endif
384
385	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
386	{
387	switch (dev->enmVersion)
388	{
389	case PDMAPICVERSION_NONE:
390	return 0;
391	case PDMAPICVERSION_APIC:
392	return MSR_IA32_APICBASE_ENABLE;
393	case PDMAPICVERSION_X2APIC:
394	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
395	default:
396	AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
397	return 0;
398	}
399	}
400
401	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
402	{
403	switch (((apic->apicbase) >> 10) & 0x3)
404	{
405	case 0:
406	return PDMAPICVERSION_NONE;
407	case 1:
408	default:
409	/* Invalid */
410	return PDMAPICVERSION_NONE;
411	case 2:
412	return PDMAPICVERSION_APIC;
413	case 3:
414	return PDMAPICVERSION_X2APIC;
415	}
416	}
417
418	#endif /* VBOX */
419
420	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
421	#ifndef VBOX
422	static int apic_io_memory;
423	static APICState *first_local_apic = NULL;
424	static int last_apic_id = 0;
425	#endif /* !VBOX */
426
427	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s);
428	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
429	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
430
431	#ifdef VBOX
432	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
433	__BEGIN_DECLS
434	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
435	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
436	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
437	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
438	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
439	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
440	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val);
441	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns);
442	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
443	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
444	uint8_t u8TriggerMode);
445	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
446	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
447	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
448	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
449	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
450
451	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
452	__END_DECLS
453	#endif /* VBOX */
454
455	#ifndef VBOX
456	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
457	uint8_t vector_num, uint8_t polarity,
458	uint8_t trigger_mode)
459	{
460	APICState *apic_iter;
461	#else /* VBOX */
462	static int apic_bus_deliver(APICDeviceInfo* dev,
463	uint32_t deliver_bitmask, uint8_t delivery_mode,
464	uint8_t vector_num, uint8_t polarity,
465	uint8_t trigger_mode)
466	{
467	#endif /* VBOX */
468
469	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
470	switch (delivery_mode) {
471	case APIC_DM_LOWPRI:
472	{
473	int d = -1;
474	if (deliver_bitmask)
475	d = ffs_bit(deliver_bitmask);
476	if (d >= 0)
477	{
478	APICState* apic = getLapicById(dev, d);
479	apic_set_irq(dev, apic, vector_num, trigger_mode);
480	}
481	return VINF_SUCCESS;
482	}
483	case APIC_DM_FIXED:
484	/* XXX: arbitration */
485	break;
486
487	case APIC_DM_SMI:
488	/** @todo: what do we really do with SMI */
489	foreach_apic(dev, deliver_bitmask,
490	cpuSetInterrupt(dev, apic));
491	return VINF_SUCCESS;
492
493	case APIC_DM_NMI:
494	/** @todo: what do we really do with NMI */
495	foreach_apic(dev, deliver_bitmask,
496	cpuSetInterrupt(dev, apic));
497	return VINF_SUCCESS;
498
499	case APIC_DM_INIT:
500	/* normal INIT IPI sent to processors */
501	#ifdef VBOX
502	#ifdef IN_RING3
503	foreach_apic(dev, deliver_bitmask,
504	apic_init_ipi(dev, apic));
505	return VINF_SUCCESS;
506	#else
507	/* We shall send init IPI only in R3, R0 calls should be
508	rescheduled to R3 */
509	return VINF_IOM_HC_MMIO_READ_WRITE;
510	#endif /* IN_RING3 */
511
512	#else
513	for (apic_iter = first_local_apic; apic_iter != NULL;
514	apic_iter = apic_iter->next_apic) {
515	apic_init_ipi(apic_iter);
516	}
517	#endif
518
519	case APIC_DM_EXTINT:
520	/* handled in I/O APIC code */
521	break;
522
523	default:
524	return VINF_SUCCESS;
525	}
526
527	#ifdef VBOX
528	foreach_apic(dev, deliver_bitmask,
529	apic_set_irq (dev, apic, vector_num, trigger_mode));
530	return VINF_SUCCESS;
531	#else /* VBOX */
532	for (apic_iter = first_local_apic; apic_iter != NULL;
533	apic_iter = apic_iter->next_apic) {
534	if (deliver_bitmask & (1 << apic_iter->id))
535	apic_set_irq(apic_iter, vector_num, trigger_mode);
536	}
537	#endif /* VBOX */
538	}
539
540	#ifndef VBOX
541	void cpu_set_apic_base(CPUState *env, uint64_t val)
542	{
543	APICState *s = env->apic_state;
544	#ifdef DEBUG_APIC
545	Log(("cpu_set_apic_base: %016llx\n", val));
546	#endif
547
548	s->apicbase = (val & 0xfffff000) \|
549	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
550	/* if disabled, cannot be enabled again */
551	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
552	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
553	env->cpuid_features &= ~CPUID_APIC;
554	s->spurious_vec &= ~APIC_SV_ENABLE;
555	}
556	}
557	#else /* VBOX */
558	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
559	{
560	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
561	APICState *s = getLapic(dev);
562	Log(("cpu_set_apic_base: %016RX64\n", val));
563
564	/** @todo: do we need to lock here ? */
565	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
566	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
567	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
568	PDMAPICVERSION oldMode = getApicMode(s);
569	s->apicbase =
570	(val & 0xfffff000) \| /* base */
571	(val & getApicEnableBits(dev)) \| /* mode */
572	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
573	PDMAPICVERSION newMode = getApicMode(s);
574
575	if (oldMode != newMode)
576	{
577	switch (newMode)
578	{
579	case PDMAPICVERSION_NONE:
580	{
581	s->spurious_vec &= ~APIC_SV_ENABLE;
582	/* Clear any pending APIC interrupt action flag. */
583	cpuClearInterrupt(dev, s);
584	/** @todo: why do we do that? */
585	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
586	break;
587	}
588	case PDMAPICVERSION_APIC:
589	/** @todo: map MMIO ranges, if needed */
590	break;
591	case PDMAPICVERSION_X2APIC:
592	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
593	break;
594	default:
595	break;
596	}
597	}
598	/* APIC_UNLOCK(dev); */
599	}
600	#endif /* VBOX */
601	#ifndef VBOX
602
603	uint64_t cpu_get_apic_base(CPUState *env)
604	{
605	APICState *s = env->apic_state;
606	#ifdef DEBUG_APIC
607	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
608	#endif
609	return s->apicbase;
610	}
611
612	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
613	{
614	APICState *s = env->apic_state;
615	s->tpr = (val & 0x0f) << 4;
616	apic_update_irq(s);
617	}
618
619	uint8_t cpu_get_apic_tpr(CPUX86State *env)
620	{
621	APICState *s = env->apic_state;
622	return s->tpr >> 4;
623	}
624
625	static int fls_bit(int value)
626	{
627	unsigned int ret = 0;
628
629	#ifdef HOST_I386
630	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
631	return ret;
632	#else
633	if (value > 0xffff)
634	value >>= 16, ret = 16;
635	if (value > 0xff)
636	value >>= 8, ret += 8;
637	if (value > 0xf)
638	value >>= 4, ret += 4;
639	if (value > 0x3)
640	value >>= 2, ret += 2;
641	return ret + (value >> 1);
642	#endif
643	}
644
645	static inline void set_bit(uint32_t *tab, int index)
646	{
647	int i, mask;
648	i = index >> 5;
649	mask = 1 << (index & 0x1f);
650	tab[i] \|= mask;
651	}
652
653	static inline void reset_bit(uint32_t *tab, int index)
654	{
655	int i, mask;
656	i = index >> 5;
657	mask = 1 << (index & 0x1f);
658	tab[i] &= ~mask;
659	}
660
661
662	#else /* VBOX */
663
664	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
665	{
666	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
667	APICState *s = getLapic(dev);
668	Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
669	return s->apicbase;
670	}
671
672	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
673	{
674	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
675	APICState *s = getLapic(dev);
676	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
677	apic_update_tpr(dev, s, (val & 0x0f) << 4);
678	}
679
680	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
681	{
682	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
683	APICState *s = getLapic(dev);
684	Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
685	return s->tpr >> 4;
686	}
687
688	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
689	{
690	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
691	int rc = VINF_SUCCESS;
692
693	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
694	return VERR_EM_INTERPRETER;
695
696	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
697
698	APICState* apic = getLapicById(dev, idCpu);
699
700	switch (index)
701	{
702	case 0x02:
703	apic->id = (u64Value >> 24);
704	break;
705	case 0x03:
706	break;
707	case 0x08:
708	apic_update_tpr(dev, apic, u64Value);
709	break;
710	case 0x09: case 0x0a:
711	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
712	break;
713	case 0x0b: /* EOI */
714	apic_eoi(dev, apic);
715	break;
716	case 0x0d:
717	apic->log_dest = u64Value >> 24;
718	break;
719	case 0x0e:
720	apic->dest_mode = u64Value >> 28;
721	break;
722	case 0x0f:
723	apic->spurious_vec = u64Value & 0x1ff;
724	apic_update_irq(dev, apic);
725	break;
726	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
727	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
728	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
729	case 0x28:
730	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
731	break;
732
733	case 0x30:
734	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
735	apic->icr[0] = (uint32_t)u64Value;
736	apic->icr[1] = (uint32_t)(u64Value >> 32);
737	rc = apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
738	(apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),
739	(apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
740	break;
741	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
742	{
743	int n = index - 0x32;
744	apic->lvt[n] = u64Value;
745	if (n == APIC_LVT_TIMER)
746	apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
747	}
748	break;
749	case 0x38:
750	apic->initial_count = u64Value;
751	apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
752	apic_timer_update(dev, apic, apic->initial_count_load_time);
753	break;
754	case 0x39:
755	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
756	break;
757	case 0x3e:
758	{
759	int v;
760	apic->divide_conf = u64Value & 0xb;
761	v = (apic->divide_conf & 3) \| ((apic->divide_conf >> 1) & 4);
762	apic->count_shift = (v + 1) & 7;
763	break;
764	}
765	case 0x3f:
766	{
767	/* Self IPI, see x2APIC book 2.4.5 */
768	int vector = u64Value & 0xff;
769	rc = apic_bus_deliver(dev,
770	1 << getLapicById(dev, idCpu)->id /* Self */,
771	0 /* Delivery mode - fixed */,
772	vector,
773	0 /* Polarity - conform to the bus */,
774	0 /* Trigger mode - edge */);
775	break;
776	}
777	default:
778	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
779	apic->esr \|= ESR_ILLEGAL_ADDRESS;
780	break;
781	}
782
783	return rc;
784	}
785	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
786	{
787	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
788
789	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
790	return VERR_EM_INTERPRETER;
791
792	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
793	APICState* apic = getLapicById(dev, idCpu);
794	uint64_t val = 0;
795
796	switch (index)
797	{
798	case 0x02: /* id */
799	val = apic->id << 24;
800	break;
801	case 0x03: /* version */
802	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
803	break;
804	case 0x08:
805	val = apic->tpr;
806	break;
807	case 0x09:
808	val = apic_get_arb_pri(apic);
809	break;
810	case 0x0a:
811	/* ppr */
812	val = apic_get_ppr(apic);
813	break;
814	case 0x0b:
815	val = 0;
816	break;
817	case 0x0d:
818	val = apic->log_dest << 24;
819	break;
820	case 0x0e:
821	/* Bottom 28 bits are always 1 */
822	val = (apic->dest_mode << 28) \| 0xfffffff;
823	break;
824	case 0x0f:
825	val = apic->spurious_vec;
826	break;
827	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
828	val = apic->isr[index & 7];
829	break;
830	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
831	val = apic->tmr[index & 7];
832	break;
833	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
834	val = apic->irr[index & 7];
835	break;
836	case 0x28:
837	val = apic->esr;
838	break;
839	case 0x30:
840	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
841	val = ((uint64_t)apic->icr[0x31] << 32) \| apic->icr[0x30];
842	break;
843	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
844	val = apic->lvt[index - 0x32];
845	break;
846	case 0x38:
847	val = apic->initial_count;
848	break;
849	case 0x39:
850	val = apic_get_current_count(dev, apic);
851	break;
852	case 0x3e:
853	val = apic->divide_conf;
854	break;
855	case 0x3f:
856	/* Self IPI register is write only */
857	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
858	break;
859	default:
860	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
861	apic->esr \|= ESR_ILLEGAL_ADDRESS;
862	val = 0;
863	break;
864	}
865	*pu64Value = val;
866	return VINF_SUCCESS;
867	}
868
869	/**
870	* More or less private interface between IOAPIC, only PDM is responsible
871	* for connecting the two devices.
872	*/
873	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
874	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
875	uint8_t u8TriggerMode)
876	{
877	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
878	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
879	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
880	return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
881	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
882	}
883
884	#endif /* VBOX */
885
886	/* return -1 if no bit is set */
887	static int get_highest_priority_int(uint32_t *tab)
888	{
889	int i;
890	for(i = 7; i >= 0; i--) {
891	if (tab[i] != 0) {
892	return i * 32 + fls_bit(tab[i]);
893	}
894	}
895	return -1;
896	}
897
898	static int apic_get_ppr(APICState *s)
899	{
900	int tpr, isrv, ppr;
901
902	tpr = (s->tpr >> 4);
903	isrv = get_highest_priority_int(s->isr);
904	if (isrv < 0)
905	isrv = 0;
906	isrv >>= 4;
907	if (tpr >= isrv)
908	ppr = s->tpr;
909	else
910	ppr = isrv << 4;
911	return ppr;
912	}
913
914	static int apic_get_ppr_zero_tpr(APICState *s)
915	{
916	int isrv;
917
918	isrv = get_highest_priority_int(s->isr);
919	if (isrv < 0)
920	isrv = 0;
921	return isrv;
922	}
923
924	static int apic_get_arb_pri(APICState *s)
925	{
926	/* XXX: arbitration */
927	return 0;
928	}
929
930	/* signal the CPU if an irq is pending */
931	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
932	{
933	int irrv, ppr;
934	if (!(s->spurious_vec & APIC_SV_ENABLE))
935	#ifdef VBOX
936	{
937	/* Clear any pending APIC interrupt action flag. */
938	cpuClearInterrupt(dev, s);
939	return false;
940	}
941	#else
942	return false;
943	#endif /* VBOX */
944	irrv = get_highest_priority_int(s->irr);
945	if (irrv < 0)
946	return false;
947	ppr = apic_get_ppr(s);
948	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
949	return false;
950	#ifndef VBOX
951	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
952	#else
953	cpuSetInterrupt(dev, s);
954	return true;
955	#endif
956	}
957
958	#ifdef VBOX
959
960	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
961	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
962	{
963	int irrv, ppr;
964	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
965	if (!dev)
966	return false;
967	APICState *s = getLapic(dev);
968
969	/*
970	* All our callbacks now come from single IOAPIC, thus locking
971	* seems to be excessive now (@todo: check)
972	*/
973	irrv = get_highest_priority_int(s->irr);
974	if (irrv < 0)
975	return false;
976
977	ppr = apic_get_ppr_zero_tpr(s);
978
979	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
980	return false;
981
982	return true;
983	}
984
985	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
986	{
987	bool fIrqIsActive = false;
988	bool fIrqWasActive = false;
989
990	fIrqWasActive = apic_update_irq(dev, s);
991	s->tpr = val;
992	fIrqIsActive = apic_update_irq(dev, s);
993
994	/* If an interrupt is pending and now masked, then clear the FF flag. */
995	if (fIrqWasActive && !fIrqIsActive)
996	{
997	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
998	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
999	cpuClearInterrupt(dev, s);
1000	}
1001	}
1002	#endif
1003
1004	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
1005	{
1006	LogFlow(("apic_set_irq vector=%x, trigger_mode=%x\n", vector_num, trigger_mode));
1007	set_bit(s->irr, vector_num);
1008	if (trigger_mode)
1009	set_bit(s->tmr, vector_num);
1010	else
1011	reset_bit(s->tmr, vector_num);
1012	apic_update_irq(dev, s);
1013	}
1014
1015	static void apic_eoi(APICDeviceInfo dev, APICState s)
1016	{
1017	int isrv;
1018	isrv = get_highest_priority_int(s->isr);
1019	if (isrv < 0)
1020	return;
1021	reset_bit(s->isr, isrv);
1022	LogFlow(("apic_eoi isrv=%x\n", isrv));
1023	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1024	set the remote IRR bit for level triggered interrupts. */
1025	apic_update_irq(dev, s);
1026	}
1027
1028	#ifndef VBOX
1029	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1030	#else /* VBOX */
1031	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1032	#endif /* VBOX */
1033	{
1034	uint32_t mask = 0;
1035
1036	if (dest_mode == 0)
1037	{
1038	if (dest == 0xff)
1039	mask = 0xff;
1040	else
1041	mask = 1 << dest;
1042	}
1043	else
1044	{
1045	APICState *apic = LAPIC_BASE(dev);
1046	uint32_t i;
1047
1048	/* XXX: cluster mode */
1049	for(i = 0; i < dev->cCpus; i++)
1050	{
1051	if (apic->dest_mode == 0xf)
1052	{
1053	if (dest & apic->log_dest)
1054	mask \|= (1 << apic->id);
1055	}
1056	else if (apic->dest_mode == 0x0)
1057	{
1058	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1059	&&
1060	(dest & apic->log_dest & 0x0f))
1061	{
1062	mask \|= (1 << i);
1063	}
1064	}
1065	}
1066	apic++;
1067	}
1068
1069	return mask;
1070	}
1071
1072	#ifdef IN_RING3
1073	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s)
1074	{
1075	int i;
1076
1077	for(i = 0; i < APIC_LVT_NB; i++)
1078	s->lvt[i] = 1 << 16; /* mask LVT */
1079	s->tpr = 0;
1080	s->spurious_vec = 0xff;
1081	s->log_dest = 0;
1082	s->dest_mode = 0xff;
1083	memset(s->isr, 0, sizeof(s->isr));
1084	memset(s->tmr, 0, sizeof(s->tmr));
1085	memset(s->irr, 0, sizeof(s->irr));
1086	s->esr = 0;
1087	memset(s->icr, 0, sizeof(s->icr));
1088	s->divide_conf = 0;
1089	s->count_shift = 0;
1090	s->initial_count = 0;
1091	s->initial_count_load_time = 0;
1092	s->next_time = 0;
1093
1094	#ifdef VBOX
1095	cpuSendInitIpi(dev, s);
1096	#endif
1097	}
1098
1099	/* send a SIPI message to the CPU to start it */
1100	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1101	{
1102	#ifndef VBOX
1103	CPUState *env = s->cpu_env;
1104	if (!env->halted)
1105	return;
1106	env->eip = 0;
1107	cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1108	0xffff, 0);
1109	env->halted = 0;
1110	#else
1111	/** @todo: init CPUs */
1112	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->id));
1113	cpuSendSipi(dev, s, vector_num);
1114	#endif
1115	}
1116	#endif /* IN_RING3 */
1117
1118	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1119	uint8_t dest, uint8_t dest_mode,
1120	uint8_t delivery_mode, uint8_t vector_num,
1121	uint8_t polarity, uint8_t trigger_mode)
1122	{
1123	uint32_t deliver_bitmask = 0;
1124	int dest_shorthand = (s->icr[0] >> 18) & 3;
1125	#ifndef VBOX
1126	APICState *apic_iter;
1127	#endif /* !VBOX */
1128
1129	LogFlow(("apic_deliver dest=%x dest_mode=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, delivery_mode, vector_num, polarity, trigger_mode));
1130
1131	switch (dest_shorthand) {
1132	case 0:
1133	#ifndef VBOX
1134	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1135	#else /* VBOX */
1136	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1137	#endif /* !VBOX */
1138	break;
1139	case 1:
1140	deliver_bitmask = (1 << s->id);
1141	break;
1142	case 2:
1143	deliver_bitmask = 0xffffffff;
1144	break;
1145	case 3:
1146	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1147	break;
1148	}
1149
1150	switch (delivery_mode) {
1151	case APIC_DM_LOWPRI:
1152	/* XXX: serch for focus processor, arbitration */
1153	dest = s->id;
1154
1155	case APIC_DM_INIT:
1156	{
1157	int trig_mode = (s->icr[0] >> 15) & 1;
1158	int level = (s->icr[0] >> 14) & 1;
1159	if (level == 0 && trig_mode == 1) {
1160	foreach_apic(dev, deliver_bitmask,
1161	apic->arb_id = apic->id);
1162	#ifndef VBOX
1163	return;
1164	#else
1165	return VINF_SUCCESS;
1166	#endif
1167	}
1168	}
1169	break;
1170
1171	case APIC_DM_SIPI:
1172	#ifndef VBOX
1173	for (apic_iter = first_local_apic; apic_iter != NULL;
1174	apic_iter = apic_iter->next_apic) {
1175	if (deliver_bitmask & (1 << apic_iter->id)) {
1176	/* XXX: SMP support */
1177	/* apic_startup(apic_iter); */
1178	}
1179	}
1180	return;
1181	#else
1182	# ifdef IN_RING3
1183	foreach_apic(dev, deliver_bitmask,
1184	apic_startup(dev, apic, vector_num));
1185	return VINF_SUCCESS;
1186	# else
1187	/* We shall send SIPI only in R3, R0 calls should be
1188	rescheduled to R3 */
1189	return VINF_IOM_HC_MMIO_WRITE;
1190	# endif
1191	#endif /* !VBOX */
1192	}
1193
1194	#ifndef VBOX
1195	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1196	trigger_mode);
1197	#else /* VBOX */
1198	return apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num,
1199	polarity, trigger_mode);
1200	#endif /* VBOX */
1201	}
1202
1203
1204	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1205	{
1206	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1207	/* if the APIC is not installed or enabled, we let the 8259 handle the
1208	IRQs */
1209	if (!dev)
1210	{
1211	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1212	return -1;
1213	}
1214
1215	APIC_LOCK(dev, VERR_INTERNAL_ERROR);
1216
1217	APICState *s = getLapic(dev);
1218	int intno;
1219
1220	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1221	Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
1222	intno = -1;
1223	goto done;
1224	}
1225
1226	/* XXX: spurious IRQ handling */
1227	intno = get_highest_priority_int(s->irr);
1228	if (intno < 0) {
1229	Log(("apic_get_interrupt: returns -1 (irr)\n"));
1230	intno = -1;
1231	goto done;
1232	}
1233	if (s->tpr && (uint32_t)intno <= s->tpr) {
1234	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1235	intno = s->spurious_vec & 0xff;
1236	goto done;
1237	}
1238	reset_bit(s->irr, intno);
1239	set_bit(s->isr, intno);
1240	apic_update_irq(dev, s);
1241	LogFlow(("apic_get_interrupt: returns %d\n", intno));
1242	done:
1243	APIC_UNLOCK(dev);
1244	return intno;
1245	}
1246
1247	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
1248	{
1249	int64_t d;
1250	uint32_t val;
1251	#ifndef VBOX
1252	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1253	s->count_shift;
1254	#else /* VBOX */
1255	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1256	s->count_shift;
1257	#endif /* VBOX */
1258	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1259	/* periodic */
1260	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1261	} else {
1262	if (d >= s->initial_count)
1263	val = 0;
1264	else
1265	val = s->initial_count - d;
1266	}
1267	return val;
1268	}
1269
1270	static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1271	{
1272	int64_t next_time, d;
1273
1274	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1275	d = (current_time - s->initial_count_load_time) >>
1276	s->count_shift;
1277	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1278	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1279	} else {
1280	if (d >= s->initial_count)
1281	goto no_timer;
1282	d = (uint64_t)s->initial_count + 1;
1283	}
1284	next_time = s->initial_count_load_time + (d << s->count_shift);
1285	#ifndef VBOX
1286	qemu_mod_timer(s->timer, next_time);
1287	#else
1288	TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1289	#endif
1290	s->next_time = next_time;
1291	} else {
1292	no_timer:
1293	#ifndef VBOX
1294	qemu_del_timer(s->timer);
1295	#else
1296	TMTimerStop(s->CTX_SUFF(pTimer));
1297	#endif
1298	}
1299	}
1300
1301	#ifdef IN_RING3
1302	#ifndef VBOX
1303	static void apic_timer(void *opaque)
1304	{
1305	APICState *s = opaque;
1306	#else /* VBOX */
1307	static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1308	{
1309	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1310	APICState *s = getLapic(dev);
1311
1312	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
1313	#endif /* VBOX */
1314
1315	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1316	LogFlow(("apic_timer: trigger irq\n"));
1317	apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1318	}
1319	apic_timer_update(dev, s, s->next_time);
1320
1321	#ifdef VBOX
1322	APIC_UNLOCK(dev);
1323	#endif
1324	}
1325	#endif /* IN_RING3 */
1326
1327	#ifndef VBOX
1328	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1329	{
1330	return 0;
1331	}
1332	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1333	{
1334	return 0;
1335	}
1336
1337	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1338	{
1339	}
1340
1341	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1342	{
1343	}
1344	#endif /* !VBOX */
1345
1346
1347	#ifndef VBOX
1348	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1349	{
1350	CPUState *env;
1351	APICState *s;
1352	#else /* VBOX */
1353	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1354	{
1355	#endif /* VBOX */
1356	uint32_t val;
1357	int index;
1358
1359	#ifndef VBOX
1360	env = cpu_single_env;
1361	if (!env)
1362	return 0;
1363	s = env->apic_state;
1364	#endif /* !VBOX */
1365
1366	index = (addr >> 4) & 0xff;
1367	switch(index) {
1368	case 0x02: /* id */
1369	val = s->id << 24;
1370	break;
1371	case 0x03: /* version */
1372	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1373	break;
1374	case 0x08:
1375	val = s->tpr;
1376	break;
1377	case 0x09:
1378	val = apic_get_arb_pri(s);
1379	break;
1380	case 0x0a:
1381	/* ppr */
1382	val = apic_get_ppr(s);
1383	break;
1384	case 0x0b:
1385	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1386	val = 0;
1387	break;
1388	case 0x0d:
1389	val = s->log_dest << 24;
1390	break;
1391	case 0x0e:
1392	#ifdef VBOX
1393	/* Bottom 28 bits are always 1 */
1394	val = (s->dest_mode << 28) \| 0xfffffff;
1395	#else
1396	val = s->dest_mode << 28;
1397	#endif
1398	break;
1399	case 0x0f:
1400	val = s->spurious_vec;
1401	break;
1402	#ifndef VBOX
1403	case 0x10 ... 0x17:
1404	#else /* VBOX */
1405	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1406	#endif /* VBOX */
1407	val = s->isr[index & 7];
1408	break;
1409	#ifndef VBOX
1410	case 0x18 ... 0x1f:
1411	#else /* VBOX */
1412	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1413	#endif /* VBOX */
1414	val = s->tmr[index & 7];
1415	break;
1416	#ifndef VBOX
1417	case 0x20 ... 0x27:
1418	#else /* VBOX */
1419	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1420	#endif /* VBOX */
1421	val = s->irr[index & 7];
1422	break;
1423	case 0x28:
1424	val = s->esr;
1425	break;
1426	case 0x30:
1427	case 0x31:
1428	val = s->icr[index & 1];
1429	break;
1430	#ifndef VBOX
1431	case 0x32 ... 0x37:
1432	#else /* VBOX */
1433	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1434	#endif /* VBOX */
1435	val = s->lvt[index - 0x32];
1436	break;
1437	case 0x38:
1438	val = s->initial_count;
1439	break;
1440	case 0x39:
1441	val = apic_get_current_count(dev, s);
1442	break;
1443	case 0x3e:
1444	val = s->divide_conf;
1445	break;
1446	default:
1447	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1448	s->esr \|= ESR_ILLEGAL_ADDRESS;
1449	val = 0;
1450	break;
1451	}
1452	#ifdef DEBUG_APIC
1453	Log(("APIC read: %08x = %08x\n", (uint32_t)addr, val));
1454	#endif
1455	return val;
1456	}
1457
1458	#ifndef VBOX
1459	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1460	{
1461	CPUState *env;
1462	APICState *s;
1463	#else /* VBOX */
1464	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1465	{
1466	int rc = VINF_SUCCESS;
1467	#endif /* VBOX */
1468	int index;
1469
1470	#ifndef VBOX
1471	env = cpu_single_env;
1472	if (!env)
1473	return;
1474	s = env->apic_state;
1475	#endif /* !VBOX */
1476
1477	#ifdef DEBUG_APIC
1478	Log(("APIC write: %08x = %08x\n", (uint32_t)addr, val));
1479	#endif
1480
1481	index = (addr >> 4) & 0xff;
1482	switch(index) {
1483	case 0x02:
1484	s->id = (val >> 24);
1485	break;
1486	case 0x03:
1487	Log(("apic_mem_writel: write to version register; ignored\n"));
1488	break;
1489	case 0x08:
1490	#ifdef VBOX
1491	apic_update_tpr(dev, s, val);
1492	#else
1493	s->tpr = val;
1494	apic_update_irq(s);
1495	#endif
1496	break;
1497	case 0x09:
1498	case 0x0a:
1499	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1500	break;
1501	case 0x0b: /* EOI */
1502	apic_eoi(dev, s);
1503	break;
1504	case 0x0d:
1505	s->log_dest = val >> 24;
1506	break;
1507	case 0x0e:
1508	s->dest_mode = val >> 28;
1509	break;
1510	case 0x0f:
1511	s->spurious_vec = val & 0x1ff;
1512	apic_update_irq(dev, s);
1513	break;
1514	#ifndef VBOX
1515	case 0x10 ... 0x17:
1516	case 0x18 ... 0x1f:
1517	case 0x20 ... 0x27:
1518	case 0x28:
1519	#else
1520	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1521	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1522	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1523	case 0x28:
1524	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1525	#endif
1526	break;
1527
1528	case 0x30:
1529	s->icr[0] = val;
1530	rc = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1531	(s->icr[0] >> 11) & 1,
1532	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1533	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1534	break;
1535	case 0x31:
1536	s->icr[1] = val;
1537	break;
1538	#ifndef VBOX
1539	case 0x32 ... 0x37:
1540	#else /* VBOX */
1541	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1542	#endif /* VBOX */
1543	{
1544	int n = index - 0x32;
1545	s->lvt[n] = val;
1546	if (n == APIC_LVT_TIMER)
1547	#ifndef VBOX
1548	apic_timer_update(s, qemu_get_clock(vm_clock));
1549	#else /* VBOX */
1550	apic_timer_update(dev, s, TMTimerGet(s->CTX_SUFF(pTimer)));
1551	#endif /* VBOX*/
1552	}
1553	break;
1554	case 0x38:
1555	s->initial_count = val;
1556	#ifndef VBOX
1557	s->initial_count_load_time = qemu_get_clock(vm_clock);
1558	#else /* VBOX */
1559	s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
1560	#endif /* VBOX*/
1561	apic_timer_update(dev, s, s->initial_count_load_time);
1562	break;
1563	case 0x39:
1564	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1565	break;
1566	case 0x3e:
1567	{
1568	int v;
1569	s->divide_conf = val & 0xb;
1570	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1571	s->count_shift = (v + 1) & 7;
1572	}
1573	break;
1574	default:
1575	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1576	s->esr \|= ESR_ILLEGAL_ADDRESS;
1577	break;
1578	}
1579	#ifdef VBOX
1580	return rc;
1581	#endif
1582	}
1583
1584	#ifdef IN_RING3
1585
1586	static void apic_save(QEMUFile f, void opaque)
1587	{
1588	APICState s = (APICState)opaque;
1589	int i;
1590
1591	qemu_put_be32s(f, &s->apicbase);
1592	#ifdef VBOX
1593	qemu_put_be32s(f, &s->id);
1594	qemu_put_be32s(f, &s->phys_id);
1595	qemu_put_be32s(f, &s->arb_id);
1596	qemu_put_be32s(f, &s->tpr);
1597	#else
1598	qemu_put_8s(f, &s->id);
1599	qemu_put_8s(f, &s->arb_id);
1600	qemu_put_8s(f, &s->tpr);
1601	#endif
1602	qemu_put_be32s(f, &s->spurious_vec);
1603	qemu_put_8s(f, &s->log_dest);
1604	qemu_put_8s(f, &s->dest_mode);
1605	for (i = 0; i < 8; i++) {
1606	qemu_put_be32s(f, &s->isr[i]);
1607	qemu_put_be32s(f, &s->tmr[i]);
1608	qemu_put_be32s(f, &s->irr[i]);
1609	}
1610	for (i = 0; i < APIC_LVT_NB; i++) {
1611	qemu_put_be32s(f, &s->lvt[i]);
1612	}
1613	qemu_put_be32s(f, &s->esr);
1614	qemu_put_be32s(f, &s->icr[0]);
1615	qemu_put_be32s(f, &s->icr[1]);
1616	qemu_put_be32s(f, &s->divide_conf);
1617	qemu_put_be32s(f, &s->count_shift);
1618	qemu_put_be32s(f, &s->initial_count);
1619	qemu_put_be64s(f, &s->initial_count_load_time);
1620	qemu_put_be64s(f, &s->next_time);
1621
1622	#ifdef VBOX
1623	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1624	#endif
1625	}
1626
1627	static int apic_load(QEMUFile f, void opaque, int version_id)
1628	{
1629	APICState s = (APICState)opaque;
1630	int i;
1631
1632	#ifdef VBOX
1633	if ((version_id < 1) \|\| (version_id > 2))
1634	return -EINVAL;
1635
1636	/* XXX: what if the base changes? (registered memory regions) */
1637	qemu_get_be32s(f, &s->apicbase);
1638
1639	switch (version_id)
1640	{
1641	case 1:
1642	{
1643	uint8_t val = 0;
1644	qemu_get_8s(f, &val);
1645	s->id = val;
1646	/* UP only in old saved states */
1647	s->phys_id = 0;
1648	qemu_get_8s(f, &val);
1649	s->arb_id = val;
1650	break;
1651	}
1652	case 2:
1653	qemu_get_be32s(f, &s->id);
1654	qemu_get_be32s(f, &s->phys_id);
1655	qemu_get_be32s(f, &s->arb_id);
1656	break;
1657	}
1658	qemu_get_be32s(f, &s->tpr);
1659	#else
1660	if (version_id != 1)
1661	return -EINVAL;
1662
1663	/* XXX: what if the base changes? (registered memory regions) */
1664	qemu_get_be32s(f, &s->apicbase);
1665	qemu_get_8s(f, &s->id);
1666	qemu_get_8s(f, &s->arb_id);
1667	qemu_get_8s(f, &s->tpr);
1668	#endif
1669	qemu_get_be32s(f, &s->spurious_vec);
1670	qemu_get_8s(f, &s->log_dest);
1671	qemu_get_8s(f, &s->dest_mode);
1672	for (i = 0; i < 8; i++) {
1673	qemu_get_be32s(f, &s->isr[i]);
1674	qemu_get_be32s(f, &s->tmr[i]);
1675	qemu_get_be32s(f, &s->irr[i]);
1676	}
1677	for (i = 0; i < APIC_LVT_NB; i++) {
1678	qemu_get_be32s(f, &s->lvt[i]);
1679	}
1680	qemu_get_be32s(f, &s->esr);
1681	qemu_get_be32s(f, &s->icr[0]);
1682	qemu_get_be32s(f, &s->icr[1]);
1683	qemu_get_be32s(f, &s->divide_conf);
1684	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1685	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1686	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1687	qemu_get_be64s(f, (uint64_t *)&s->next_time);
1688
1689	#ifdef VBOX
1690	TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1691	#endif
1692
1693	return VINF_SUCCESS;
1694	}
1695	#ifndef VBOX
1696	static void apic_reset(void *opaque)
1697	{
1698	APICState s = (APICState)opaque;
1699	apic_init_ipi(s);
1700	}
1701	#endif
1702
1703	#endif /* IN_RING3 */
1704
1705	#ifndef VBOX
1706	static CPUReadMemoryFunc *apic_mem_read[3] = {
1707	apic_mem_readb,
1708	apic_mem_readw,
1709	apic_mem_readl,
1710	};
1711
1712	static CPUWriteMemoryFunc *apic_mem_write[3] = {
1713	apic_mem_writeb,
1714	apic_mem_writew,
1715	apic_mem_writel,
1716	};
1717
1718	int apic_init(CPUState *env)
1719	{
1720	APICState *s;
1721
1722	s = qemu_mallocz(sizeof(APICState));
1723	if (!s)
1724	return -1;
1725	env->apic_state = s;
1726	apic_init_ipi(s);
1727	s->id = last_apic_id++;
1728	s->cpu_env = env;
1729	s->apicbase = 0xfee00000 \|
1730	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
1731
1732	/* XXX: mapping more APICs at the same memory location */
1733	if (apic_io_memory == 0) {
1734	/* NOTE: the APIC is directly connected to the CPU - it is not
1735	on the global memory bus. */
1736	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1737	apic_mem_write, NULL);
1738	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1739	apic_io_memory);
1740	}
1741	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1742
1743	register_savevm("apic", 0, 1, apic_save, apic_load, s);
1744	qemu_register_reset(apic_reset, s);
1745
1746	s->next_apic = first_local_apic;
1747	first_local_apic = s;
1748
1749	return 0;
1750	}
1751	#endif /* !VBOX */
1752
1753	static void ioapic_service(IOAPICState *s)
1754	{
1755	uint8_t i;
1756	uint8_t trig_mode;
1757	uint8_t vector;
1758	uint8_t delivery_mode;
1759	uint32_t mask;
1760	uint64_t entry;
1761	uint8_t dest;
1762	uint8_t dest_mode;
1763	uint8_t polarity;
1764
1765	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1766	mask = 1 << i;
1767	if (s->irr & mask) {
1768	entry = s->ioredtbl[i];
1769	if (!(entry & APIC_LVT_MASKED)) {
1770	trig_mode = ((entry >> 15) & 1);
1771	dest = entry >> 56;
1772	dest_mode = (entry >> 11) & 1;
1773	delivery_mode = (entry >> 8) & 7;
1774	polarity = (entry >> 13) & 1;
1775	if (trig_mode == APIC_TRIGGER_EDGE)
1776	s->irr &= ~mask;
1777	if (delivery_mode == APIC_DM_EXTINT)
1778	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1779	vector = pic_read_irq(isa_pic);
1780	#else /* VBOX */
1781	{
1782	AssertMsgFailed(("Delivery mode ExtINT"));
1783	vector = 0xff; /* incorrect but shuts up gcc. */
1784	}
1785	#endif /* VBOX */
1786	else
1787	vector = entry & 0xff;
1788
1789	#ifndef VBOX
1790	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1791	delivery_mode, vector, polarity, trig_mode);
1792	#else /* VBOX */
1793	int rc = s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1794	dest,
1795	dest_mode,
1796	delivery_mode,
1797	vector,
1798	polarity,
1799	trig_mode);
1800	/* We must be sure that attempts to reschedule in R3
1801	never get here */
1802	Assert(rc == VINF_SUCCESS);
1803	#endif /* VBOX */
1804	}
1805	}
1806	}
1807	}
1808
1809	#ifdef VBOX
1810	static
1811	#endif
1812	void ioapic_set_irq(void *opaque, int vector, int level)
1813	{
1814	IOAPICState s = (IOAPICState)opaque;
1815
1816	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1817	uint32_t mask = 1 << vector;
1818	uint64_t entry = s->ioredtbl[vector];
1819
1820	if ((entry >> 15) & 1) {
1821	/* level triggered */
1822	if (level) {
1823	s->irr \|= mask;
1824	ioapic_service(s);
1825	#ifdef VBOX
1826	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1827	s->irr &= ~mask;
1828	}
1829	#endif
1830	} else {
1831	s->irr &= ~mask;
1832	}
1833	} else {
1834	/* edge triggered */
1835	if (level) {
1836	s->irr \|= mask;
1837	ioapic_service(s);
1838	}
1839	}
1840	}
1841	}
1842
1843	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1844	{
1845	IOAPICState s = (IOAPICState)opaque;
1846	int index;
1847	uint32_t val = 0;
1848
1849	addr &= 0xff;
1850	if (addr == 0x00) {
1851	val = s->ioregsel;
1852	} else if (addr == 0x10) {
1853	switch (s->ioregsel) {
1854	case 0x00:
1855	val = s->id << 24;
1856	break;
1857	case 0x01:
1858	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1859	break;
1860	case 0x02:
1861	val = 0;
1862	break;
1863	default:
1864	index = (s->ioregsel - 0x10) >> 1;
1865	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1866	if (s->ioregsel & 1)
1867	val = s->ioredtbl[index] >> 32;
1868	else
1869	val = s->ioredtbl[index] & 0xffffffff;
1870	}
1871	}
1872	#ifdef DEBUG_IOAPIC
1873	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1874	#endif
1875	}
1876	return val;
1877	}
1878
1879	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1880	{
1881	IOAPICState s = (IOAPICState)opaque;
1882	int index;
1883
1884	addr &= 0xff;
1885	if (addr == 0x00) {
1886	s->ioregsel = val;
1887	return;
1888	} else if (addr == 0x10) {
1889	#ifdef DEBUG_IOAPIC
1890	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1891	#endif
1892	switch (s->ioregsel) {
1893	case 0x00:
1894	s->id = (val >> 24) & 0xff;
1895	return;
1896	case 0x01:
1897	case 0x02:
1898	return;
1899	default:
1900	index = (s->ioregsel - 0x10) >> 1;
1901	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1902	if (s->ioregsel & 1) {
1903	s->ioredtbl[index] &= 0xffffffff;
1904	s->ioredtbl[index] \|= (uint64_t)val << 32;
1905	} else {
1906	#ifdef VBOX
1907	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1908	uint8_t vec = val & 0xff;
1909	if ((val & APIC_LVT_MASKED) \|\|
1910	((vec >= 0x10) && (vec < 0xff)))
1911	{
1912	s->ioredtbl[index] &= ~0xffffffffULL;
1913	s->ioredtbl[index] \|= val;
1914	}
1915	else
1916	{
1917	/*
1918	* Linux 2.6 kernels has pretty strange function
1919	* unlock_ExtINT_logic() which writes
1920	* absolutely bogus (all 0) value into the vector
1921	* with pretty vague explanation why.
1922	* So we just ignore such writes.
1923	*/
1924	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1925	}
1926	}
1927	#else
1928	s->ioredtbl[index] &= ~0xffffffffULL;
1929	s->ioredtbl[index] \|= val;
1930	#endif
1931	ioapic_service(s);
1932	}
1933	}
1934	}
1935	}
1936
1937	#ifdef IN_RING3
1938
1939	static void ioapic_save(QEMUFile f, void opaque)
1940	{
1941	IOAPICState s = (IOAPICState)opaque;
1942	int i;
1943
1944	qemu_put_8s(f, &s->id);
1945	qemu_put_8s(f, &s->ioregsel);
1946	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1947	qemu_put_be64s(f, &s->ioredtbl[i]);
1948	}
1949	}
1950
1951	static int ioapic_load(QEMUFile f, void opaque, int version_id)
1952	{
1953	IOAPICState s = (IOAPICState)opaque;
1954	int i;
1955
1956	if (version_id != 1)
1957	return -EINVAL;
1958
1959	qemu_get_8s(f, &s->id);
1960	qemu_get_8s(f, &s->ioregsel);
1961	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1962	qemu_get_be64s(f, &s->ioredtbl[i]);
1963	}
1964	return 0;
1965	}
1966
1967	static void ioapic_reset(void *opaque)
1968	{
1969	IOAPICState s = (IOAPICState)opaque;
1970	#ifdef VBOX
1971	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1972	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1973	#endif
1974	int i;
1975
1976	memset(s, 0, sizeof(*s));
1977	for(i = 0; i < IOAPIC_NUM_PINS; i++)
1978	s->ioredtbl[i] = 1 << 16; /* mask LVT */
1979
1980	#ifdef VBOX
1981	if (pDevIns)
1982	{
1983	s->pDevInsR3 = pDevIns;
1984	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1985	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1986	}
1987	if (pIoApicHlp)
1988	{
1989	s->pIoApicHlpR3 = pIoApicHlp;
1990	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1991	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1992	}
1993	#endif
1994	}
1995
1996	#endif /* IN_RING3 */
1997
1998	#ifndef VBOX
1999	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
2000	ioapic_mem_readl,
2001	ioapic_mem_readl,
2002	ioapic_mem_readl,
2003	};
2004
2005	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
2006	ioapic_mem_writel,
2007	ioapic_mem_writel,
2008	ioapic_mem_writel,
2009	};
2010
2011	IOAPICState *ioapic_init(void)
2012	{
2013	IOAPICState *s;
2014	int io_memory;
2015
2016	s = qemu_mallocz(sizeof(IOAPICState));
2017	if (!s)
2018	return NULL;
2019	ioapic_reset(s);
2020	s->id = last_apic_id++;
2021
2022	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
2023	ioapic_mem_write, s);
2024	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2025
2026	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2027	qemu_register_reset(ioapic_reset, s);
2028
2029	return s;
2030	}
2031	#endif /* !VBOX */
2032
2033	/* LAPIC */
2034	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2035	{
2036	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2037	APICState *s = getLapic(dev);
2038
2039	Log(("[SMP] apicMMIORead at %llx\n", (uint64_t)GCPhysAddr));
2040
2041	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2042	different physical addresses, see #3092) */
2043
2044	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2045	switch (cb)
2046	{
2047	case 1:
2048	(uint8_t )pv = 0;
2049	break;
2050
2051	case 2:
2052	(uint16_t )pv = 0;
2053	break;
2054
2055	case 4:
2056	{
2057	#if 0 /** @note experimental */
2058	#ifndef IN_RING3
2059	uint32_t index = (GCPhysAddr >> 4) & 0xff;
2060
2061	if ( index == 0x08 /* TPR */
2062	&& ++s->ulTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2063	{
2064	#ifdef IN_RC
2065	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2066	#else
2067	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2068	pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2069	#endif
2070	return VINF_PATM_HC_MMIO_PATCH_READ;
2071	}
2072	#endif
2073	#endif /* experimental */
2074	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2075	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
2076	APIC_UNLOCK(dev);
2077	break;
2078	}
2079	default:
2080	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2081	return VERR_INTERNAL_ERROR;
2082	}
2083	return VINF_SUCCESS;
2084	}
2085
2086	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2087	{
2088	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2089	APICState *s = getLapic(dev);
2090
2091	Log(("[SMP] apicMMIOWrite at %llx\n", (uint64_t)GCPhysAddr));
2092
2093	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2094	different physical addresses, see #3092) */
2095
2096	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2097	switch (cb)
2098	{
2099	case 1:
2100	case 2:
2101	/* ignore */
2102	break;
2103
2104	case 4:
2105	{
2106	int rc;
2107	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2108	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2109	APIC_UNLOCK(dev);
2110	return rc;
2111	}
2112
2113	default:
2114	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2115	return VERR_INTERNAL_ERROR;
2116	}
2117	return VINF_SUCCESS;
2118	}
2119
2120	#ifdef IN_RING3
2121
2122	/**
2123	* @copydoc FNSSMDEVSAVEEXEC
2124	*/
2125	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2126	{
2127	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2128
2129	/* save all APICs data, @todo: is it correct? */
2130	foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
2131
2132	return VINF_SUCCESS;
2133	}
2134
2135	/**
2136	* @copydoc FNSSMDEVLOADEXEC
2137	*/
2138	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2139	{
2140	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2141	/* load all APICs data, @todo: is it correct? */
2142	foreach_apic(dev, 0xffffffff,
2143	if (apic_load(pSSMHandle, apic, u32Version))
2144	{
2145	AssertFailed();
2146	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2147	}
2148	);
2149	return VINF_SUCCESS;
2150	}
2151
2152	/**
2153	* @copydoc FNPDMDEVRESET
2154	*/
2155	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2156	{
2157	APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2158	APICState *s = getLapic(dev);
2159
2160	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2161
2162	TMTimerStop(s->CTX_SUFF(pTimer));
2163
2164	apic_init_ipi(dev, s);
2165	/* malc, I've removed the initing duplicated in apic_init_ipi(). This
2166	* arb_id was left over.. */
2167	s->arb_id = 0;
2168	/* Reset should re-enable the APIC. */
2169	s->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_ENABLE;
2170	if (s->phys_id == 0)
2171	s->apicbase \|= MSR_IA32_APICBASE_BSP;
2172	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2173	/* Clear any pending APIC interrupt action flag. */
2174	cpuClearInterrupt(dev, s);
2175	APIC_UNLOCK(dev);
2176	}
2177
2178	/**
2179	* @copydoc FNPDMDEVRELOCATE
2180	*/
2181	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2182	{
2183	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2184	dev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2185	dev->pApicHlpRC = dev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2186	dev->pLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), dev->pLapicsR3);
2187	foreach_apic(dev, 0xffffffff,
2188	apic->pTimerRC = TMTimerRCPtr(apic->CTX_SUFF(pTimer)));
2189	}
2190
2191	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2192	{
2193	int i;
2194	memset(apic, 0, sizeof(*apic));
2195	apic->apicbase = UINT32_C(0xfee00000) \| MSR_IA32_APICBASE_ENABLE;
2196	/* Mark first CPU as BSP */
2197	if (id == 0)
2198	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2199	for (i = 0; i < APIC_LVT_NB; i++)
2200	apic->lvt[i] = 1 << 16; /* mask LVT */
2201	apic->spurious_vec = 0xff;
2202	apic->phys_id = apic->id = id;
2203	}
2204
2205	/**
2206	* @copydoc FNPDMDEVCONSTRUCT
2207	*/
2208	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2209	{
2210	PDMAPICREG ApicReg;
2211	int rc;
2212	uint32_t i;
2213	bool fIOAPIC;
2214	bool fGCEnabled;
2215	bool fR0Enabled;
2216	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2217	uint32_t cCpus;
2218	APICState *apic;
2219
2220	/*
2221	* Only single device instance.
2222	*/
2223	Assert(iInstance == 0);
2224
2225	/*
2226	* Validate configuration.
2227	*/
2228	if (!CFGMR3AreValuesValid(pCfgHandle,
2229	"IOAPIC\0"
2230	"GCEnabled\0"
2231	"R0Enabled\0"
2232	"NumCPUs\0"))
2233	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2234
2235	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIOAPIC, true);
2236	if (RT_FAILURE(rc))
2237	return PDMDEV_SET_ERROR(pDevIns, rc,
2238	N_("Configuration error: Failed to read \"IOAPIC\""));
2239
2240	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2241	if (RT_FAILURE(rc))
2242	return PDMDEV_SET_ERROR(pDevIns, rc,
2243	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2244
2245	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2246	if (RT_FAILURE(rc))
2247	return PDMDEV_SET_ERROR(pDevIns, rc,
2248	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2249
2250	rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2251	if (RT_FAILURE(rc))
2252	return PDMDEV_SET_ERROR(pDevIns, rc,
2253	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2254
2255	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
2256
2257	/*
2258	* Init the data.
2259	*/
2260	pThis->pDevInsR3 = pDevIns;
2261	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2262	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2263	pThis->cCpus = cCpus;
2264	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2265	pThis->enmVersion = PDMAPICVERSION_APIC;
2266
2267	PVM pVM = PDMDevHlpGetVM(pDevIns);
2268	/*
2269	* We are not freeing this memory, as it's automatically released when guest exits.
2270	*/
2271	rc = MMHyperAlloc(pVM, cCpussizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void *)&pThis->pLapicsR3);
2272	if (RT_FAILURE(rc))
2273	return VERR_NO_MEMORY;
2274	pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
2275	pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
2276
2277	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2278	{
2279	initApicData(apic, i);
2280	apic++;
2281	}
2282
2283	/*
2284	* Register the APIC.
2285	*/
2286	ApicReg.u32Version = PDM_APICREG_VERSION;
2287	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2288	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2289	ApicReg.pfnSetBaseR3 = apicSetBase;
2290	ApicReg.pfnGetBaseR3 = apicGetBase;
2291	ApicReg.pfnSetTPRR3 = apicSetTPR;
2292	ApicReg.pfnGetTPRR3 = apicGetTPR;
2293	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2294	ApicReg.pfnReadMSRR3 = apicReadMSR;
2295	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2296	if (fGCEnabled) {
2297	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2298	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2299	ApicReg.pszSetBaseRC = "apicSetBase";
2300	ApicReg.pszGetBaseRC = "apicGetBase";
2301	ApicReg.pszSetTPRRC = "apicSetTPR";
2302	ApicReg.pszGetTPRRC = "apicGetTPR";
2303	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2304	ApicReg.pszReadMSRRC = "apicReadMSR";
2305	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2306	} else {
2307	ApicReg.pszGetInterruptRC = NULL;
2308	ApicReg.pszHasPendingIrqRC = NULL;
2309	ApicReg.pszSetBaseRC = NULL;
2310	ApicReg.pszGetBaseRC = NULL;
2311	ApicReg.pszSetTPRRC = NULL;
2312	ApicReg.pszGetTPRRC = NULL;
2313	ApicReg.pszWriteMSRRC = NULL;
2314	ApicReg.pszReadMSRRC = NULL;
2315	ApicReg.pszBusDeliverRC = NULL;
2316	}
2317	if (fR0Enabled) {
2318	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2319	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2320	ApicReg.pszSetBaseR0 = "apicSetBase";
2321	ApicReg.pszGetBaseR0 = "apicGetBase";
2322	ApicReg.pszSetTPRR0 = "apicSetTPR";
2323	ApicReg.pszGetTPRR0 = "apicGetTPR";
2324	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2325	ApicReg.pszReadMSRR0 = "apicReadMSR";
2326	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2327	} else {
2328	ApicReg.pszGetInterruptR0 = NULL;
2329	ApicReg.pszHasPendingIrqR0 = NULL;
2330	ApicReg.pszSetBaseR0 = NULL;
2331	ApicReg.pszGetBaseR0 = NULL;
2332	ApicReg.pszSetTPRR0 = NULL;
2333	ApicReg.pszGetTPRR0 = NULL;
2334	ApicReg.pszWriteMSRR0 = NULL;
2335	ApicReg.pszReadMSRR0 = NULL;
2336	ApicReg.pszBusDeliverR0 = NULL;
2337	}
2338
2339	Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2340	rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2341	if (RT_FAILURE(rc))
2342	{
2343	AssertLogRelMsgFailed(("APICRegister -> %Rrc\n", rc));
2344	return rc;
2345	}
2346
2347	/*
2348	* The the CPUID feature bit.
2349	*/
2350	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2351	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2352	if (u32Eax >= 1)
2353	{
2354	if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
2355	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2356	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2357	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2358	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2359	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2360	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2361	{
2362	LogRel(("Activating Local APIC\n"));
2363	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2364	}
2365	}
2366
2367	/*
2368	* Register the MMIO range.
2369	* @todo: may need to rethink for cases when different LAPICs mapped to different address
2370	* (see IA32_APIC_BASE_MSR)
2371	*/
2372	rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
2373	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2374	if (RT_FAILURE(rc))
2375	return rc;
2376
2377	if (fGCEnabled) {
2378	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2379
2380	rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2381	"apicMMIOWrite", "apicMMIORead", NULL);
2382	if (RT_FAILURE(rc))
2383	return rc;
2384	}
2385
2386	if (fR0Enabled) {
2387	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2388
2389	rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2390	"apicMMIOWrite", "apicMMIORead", NULL);
2391	if (RT_FAILURE(rc))
2392	return rc;
2393	}
2394
2395	/*
2396	* Create the APIC timers.
2397	*/
2398	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2399	{
2400	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer,
2401	"APIC Timer", &apic->pTimerR3);
2402	if (RT_FAILURE(rc))
2403	return rc;
2404	apic->pTimerR0 = TMTimerR0Ptr(apic->pTimerR3);
2405	apic->pTimerRC = TMTimerRCPtr(apic->pTimerR3);
2406	apic++;
2407	}
2408
2409	/*
2410	* Saved state.
2411	*/
2412	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
2413	sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
2414	if (RT_FAILURE(rc))
2415	return rc;
2416
2417	#ifdef VBOX_WITH_STATISTICS
2418	/*
2419	* Statistics.
2420	*/
2421	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2422	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2423	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2424	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2425	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq, STAMTYPE_COUNTER, "/PDM/APIC/Masked/ActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2426	#endif
2427
2428	return VINF_SUCCESS;
2429	}
2430
2431
2432	/**
2433	* APIC device registration structure.
2434	*/
2435	const PDMDEVREG g_DeviceAPIC =
2436	{
2437	/* u32Version */
2438	PDM_DEVREG_VERSION,
2439	/* szDeviceName */
2440	"apic",
2441	/* szRCMod */
2442	"VBoxDD2GC.gc",
2443	/* szR0Mod */
2444	"VBoxDD2R0.r0",
2445	/* pszDescription */
2446	"Advanced Programmable Interrupt Controller (APIC) Device",
2447	/* fFlags */
2448	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2449	/* fClass */
2450	PDM_DEVREG_CLASS_PIC,
2451	/* cMaxInstances */
2452	1,
2453	/* cbInstance */
2454	sizeof(APICState),
2455	/* pfnConstruct */
2456	apicConstruct,
2457	/* pfnDestruct */
2458	NULL,
2459	/* pfnRelocate */
2460	apicRelocate,
2461	/* pfnIOCtl */
2462	NULL,
2463	/* pfnPowerOn */
2464	NULL,
2465	/* pfnReset */
2466	apicReset,
2467	/* pfnSuspend */
2468	NULL,
2469	/* pfnResume */
2470	NULL,
2471	/* pfnAttach */
2472	NULL,
2473	/* pfnDetach */
2474	NULL,
2475	/* pfnQueryInterface. */
2476	NULL,
2477	/* pfnInitComplete */
2478	NULL,
2479	/* pfnPowerOff */
2480	NULL,
2481	/* pfnSoftReset */
2482	NULL,
2483	/* u32VersionEnd */
2484	PDM_DEVREG_VERSION
2485	};
2486
2487	#endif /* IN_RING3 */
2488
2489
2490	/* IOAPIC */
2491
2492	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2493	{
2494	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2495	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2496
2497	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2498	switch (cb)
2499	{
2500	case 1:
2501	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2502	break;
2503
2504	case 2:
2505	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2506	break;
2507
2508	case 4:
2509	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2510	break;
2511
2512	default:
2513	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2514	IOAPIC_UNLOCK(s);
2515	return VERR_INTERNAL_ERROR;
2516	}
2517	IOAPIC_UNLOCK(s);
2518	return VINF_SUCCESS;
2519	}
2520
2521	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2522	{
2523	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2524
2525	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2526	switch (cb)
2527	{
2528	case 1:
2529	case 2:
2530	case 4:
2531	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2532	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
2533	IOAPIC_UNLOCK(s);
2534	break;
2535
2536	default:
2537	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2538	return VERR_INTERNAL_ERROR;
2539	}
2540	return VINF_SUCCESS;
2541	}
2542
2543	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2544	{
2545	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
2546	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2547	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2548	ioapic_set_irq(pThis, iIrq, iLevel);
2549	}
2550
2551
2552	#ifdef IN_RING3
2553
2554	/**
2555	* @copydoc FNSSMDEVSAVEEXEC
2556	*/
2557	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2558	{
2559	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2560	ioapic_save(pSSMHandle, s);
2561	return VINF_SUCCESS;
2562	}
2563
2564	/**
2565	* @copydoc FNSSMDEVLOADEXEC
2566	*/
2567	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2568	{
2569	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2570
2571	if (ioapic_load(pSSMHandle, s, u32Version)) {
2572	AssertFailed();
2573	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2574	}
2575
2576	return VINF_SUCCESS;
2577	}
2578
2579	/**
2580	* @copydoc FNPDMDEVRESET
2581	*/
2582	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2583	{
2584	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2585	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2586	ioapic_reset(s);
2587	IOAPIC_UNLOCK(s);
2588	}
2589
2590	/**
2591	* @copydoc FNPDMDEVRELOCATE
2592	*/
2593	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2594	{
2595	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2596	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2597	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2598	}
2599
2600	/**
2601	* @copydoc FNPDMDEVCONSTRUCT
2602	*/
2603	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2604	{
2605	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2606	PDMIOAPICREG IoApicReg;
2607	bool fGCEnabled;
2608	bool fR0Enabled;
2609	int rc;
2610
2611	Assert(iInstance == 0);
2612
2613	/*
2614	* Validate and read the configuration.
2615	*/
2616	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2617	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2618
2619	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2620	if (RT_FAILURE(rc))
2621	return PDMDEV_SET_ERROR(pDevIns, rc,
2622	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2623
2624	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2625	if (RT_FAILURE(rc))
2626	return PDMDEV_SET_ERROR(pDevIns, rc,
2627	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2628	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2629
2630	/*
2631	* Initialize the state data.
2632	*/
2633	s->pDevInsR3 = pDevIns;
2634	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2635	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2636	ioapic_reset(s);
2637	s->id = 0;
2638
2639	/*
2640	* Register the IOAPIC and get helpers.
2641	*/
2642	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2643	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2644	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2645	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2646	rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2647	if (RT_FAILURE(rc))
2648	{
2649	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2650	return rc;
2651	}
2652
2653	/*
2654	* Register MMIO callbacks and saved state.
2655	*/
2656	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2657	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2658	if (RT_FAILURE(rc))
2659	return rc;
2660
2661	if (fGCEnabled) {
2662	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2663
2664	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2665	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2666	if (RT_FAILURE(rc))
2667	return rc;
2668	}
2669
2670	if (fR0Enabled) {
2671	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2672
2673	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2674	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2675	if (RT_FAILURE(rc))
2676	return rc;
2677	}
2678
2679	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2680	sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2681	if (RT_FAILURE(rc))
2682	return rc;
2683
2684	#ifdef VBOX_WITH_STATISTICS
2685	/*
2686	* Statistics.
2687	*/
2688	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2689	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2690	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2691	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2692	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2693	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2694	#endif
2695
2696	return VINF_SUCCESS;
2697	}
2698
2699	/**
2700	* IO APIC device registration structure.
2701	*/
2702	const PDMDEVREG g_DeviceIOAPIC =
2703	{
2704	/* u32Version */
2705	PDM_DEVREG_VERSION,
2706	/* szDeviceName */
2707	"ioapic",
2708	/* szRCMod */
2709	"VBoxDD2GC.gc",
2710	/* szR0Mod */
2711	"VBoxDD2R0.r0",
2712	/* pszDescription */
2713	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2714	/* fFlags */
2715	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2716	/* fClass */
2717	PDM_DEVREG_CLASS_PIC,
2718	/* cMaxInstances */
2719	1,
2720	/* cbInstance */
2721	sizeof(IOAPICState),
2722	/* pfnConstruct */
2723	ioapicConstruct,
2724	/* pfnDestruct */
2725	NULL,
2726	/* pfnRelocate */
2727	ioapicRelocate,
2728	/* pfnIOCtl */
2729	NULL,
2730	/* pfnPowerOn */
2731	NULL,
2732	/* pfnReset */
2733	ioapicReset,
2734	/* pfnSuspend */
2735	NULL,
2736	/* pfnResume */
2737	NULL,
2738	/* pfnAttach */
2739	NULL,
2740	/* pfnDetach */
2741	NULL,
2742	/* pfnQueryInterface. */
2743	NULL,
2744	/* pfnInitComplete */
2745	NULL,
2746	/* pfnPowerOff */
2747	NULL,
2748	/* pfnSoftReset */
2749	NULL,
2750	/* u32VersionEnd */
2751	PDM_DEVREG_VERSION
2752	};
2753
2754	#endif /* IN_RING3 */
2755	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 19602

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