VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 20131

Last change on this file since 20131 was 20092, checked in by vboxsync, 16 years ago

DevAPIC,PDM: timer critsect.
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File size: 82.3 KB
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1#ifdef VBOX
2/* $Id: DevAPIC.cpp 20092 2009-05-27 15:19:32Z vboxsync $ */
3/** @file
4 * Advanced Programmable Interrupt Controller (APIC) Device and
5 * I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6 */
7
8/*
9 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20 * Clara, CA 95054 USA or visit http://www.sun.com if you need
21 * additional information or have any questions.
22 * --------------------------------------------------------------------
23 *
24 * This code is based on:
25 *
26 * apic.c revision 1.5 @@OSETODO
27 */
28
29/*******************************************************************************
30* Header Files *
31*******************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/pdmdev.h>
34
35#include <VBox/log.h>
36#include <VBox/stam.h>
37#include <iprt/assert.h>
38#include <iprt/asm.h>
39
40#include "Builtins2.h"
41#include "vl_vbox.h"
42
43#define MSR_IA32_APICBASE 0x1b
44#define MSR_IA32_APICBASE_BSP (1<<8)
45#define MSR_IA32_APICBASE_ENABLE (1<<11)
46#ifdef VBOX
47#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48#endif
49#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51#ifndef EINVAL
52# define EINVAL 1
53#endif
54
55#ifdef _MSC_VER
56# pragma warning(disable:4244)
57#endif
58
59/** @def APIC_LOCK
60 * Acquires the PDM lock. */
61#define APIC_LOCK(pThis, rcBusy) \
62 do { \
63 int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
64 if (rc2 != VINF_SUCCESS) \
65 return rc2; \
66 } while (0)
67
68/** @def APIC_LOCK_VOID
69 * Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
70#define APIC_LOCK_VOID(pThis, rcBusy) \
71 do { \
72 int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
73 AssertLogRelRCReturnVoid(rc2); \
74 } while (0)
75
76/** @def APIC_UNLOCK
77 * Releases the PDM lock. */
78#define APIC_UNLOCK(pThis) \
79 PDMCritSectLeave((pThis)->CTX_SUFF(pCritSect))
80
81/** @def IOAPIC_LOCK
82 * Acquires the PDM lock. */
83#define IOAPIC_LOCK(pThis, rc) \
84 do { \
85 int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
86 if (rc2 != VINF_SUCCESS) \
87 return rc2; \
88 } while (0)
89
90/** @def IOAPIC_UNLOCK
91 * Releases the PDM lock. */
92#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
93
94/** @def LAPIC_BASE
95 * Return address of first LAPIC state. */
96#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
97
98#define foreach_apic(dev, mask, code) \
99 do { \
100 uint32_t i; \
101 APICState* apic = LAPIC_BASE(dev); \
102 for (i = 0; i < dev->cCpus; i++) \
103 { \
104 if (mask & (1 << (apic->id))) \
105 { \
106 code; \
107 } \
108 apic++; \
109 } \
110 } while (0)
111
112# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
113# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
114# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
115# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
116
117#endif /* VBOX */
118
119/*
120 * APIC support
121 *
122 * Copyright (c) 2004-2005 Fabrice Bellard
123 *
124 * This library is free software; you can redistribute it and/or
125 * modify it under the terms of the GNU Lesser General Public
126 * License as published by the Free Software Foundation; either
127 * version 2 of the License, or (at your option) any later version.
128 *
129 * This library is distributed in the hope that it will be useful,
130 * but WITHOUT ANY WARRANTY; without even the implied warranty of
131 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
132 * Lesser General Public License for more details.
133 *
134 * You should have received a copy of the GNU Lesser General Public
135 * License along with this library; if not, write to the Free Software
136 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
137 */
138#ifndef VBOX
139#include "vl.h"
140#endif
141
142#define DEBUG_APIC
143#define DEBUG_IOAPIC
144
145/* APIC Local Vector Table */
146#define APIC_LVT_TIMER 0
147#define APIC_LVT_THERMAL 1
148#define APIC_LVT_PERFORM 2
149#define APIC_LVT_LINT0 3
150#define APIC_LVT_LINT1 4
151#define APIC_LVT_ERROR 5
152#define APIC_LVT_NB 6
153
154/* APIC delivery modes */
155#define APIC_DM_FIXED 0
156#define APIC_DM_LOWPRI 1
157#define APIC_DM_SMI 2
158#define APIC_DM_NMI 4
159#define APIC_DM_INIT 5
160#define APIC_DM_SIPI 6
161#define APIC_DM_EXTINT 7
162
163/* APIC destination mode */
164#define APIC_DESTMODE_FLAT 0xf
165#define APIC_DESTMODE_CLUSTER 1
166
167#define APIC_TRIGGER_EDGE 0
168#define APIC_TRIGGER_LEVEL 1
169
170#define APIC_LVT_TIMER_PERIODIC (1<<17)
171#define APIC_LVT_MASKED (1<<16)
172#define APIC_LVT_LEVEL_TRIGGER (1<<15)
173#define APIC_LVT_REMOTE_IRR (1<<14)
174#define APIC_INPUT_POLARITY (1<<13)
175#define APIC_SEND_PENDING (1<<12)
176
177#define IOAPIC_NUM_PINS 0x18
178
179#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181#define APIC_SV_ENABLE (1 << 8)
182
183#ifdef VBOX
184#define APIC_MAX_PATCH_ATTEMPTS 100
185
186typedef uint32_t PhysApicId;
187typedef uint32_t LogApicId;
188#endif
189
190typedef struct APICState {
191#ifndef VBOX
192 CPUState *cpu_env;
193#endif /* !VBOX */
194 uint32_t apicbase;
195#ifdef VBOX
196 /* Task priority register (interrupt level) */
197 uint32_t tpr;
198 /* Logical APIC id */
199 LogApicId id;
200 /* Physical APIC id */
201 PhysApicId phys_id;
202 /** @todo: is it logical or physical? Not really used anyway now. */
203 PhysApicId arb_id;
204#else
205 uint8_t tpr;
206 uint8_t id;
207 uint8_t arb_id;
208#endif
209 uint32_t spurious_vec;
210 uint8_t log_dest;
211 uint8_t dest_mode;
212 uint32_t isr[8]; /* in service register */
213 uint32_t tmr[8]; /* trigger mode register */
214 uint32_t irr[8]; /* interrupt request register */
215 uint32_t lvt[APIC_LVT_NB];
216 uint32_t esr; /* error register */
217 uint32_t icr[2];
218 uint32_t divide_conf;
219 int count_shift;
220 uint32_t initial_count;
221#ifdef VBOX
222 uint32_t Alignment0;
223#endif
224 int64_t initial_count_load_time, next_time;
225#ifndef VBOX
226 QEMUTimer *timer;
227 struct APICState *next_apic;
228#else
229 /** The APIC timer - R3 Ptr. */
230 PTMTIMERR3 pTimerR3;
231
232 /** The APIC timer - R0 Ptr. */
233 PTMTIMERR0 pTimerR0;
234
235 /** The APIC timer - RC Ptr. */
236 PTMTIMERRC pTimerRC;
237
238 /** Alignment */
239 uint32_t Alignment1;
240#endif /* VBOX */
241} APICState;
242
243struct IOAPICState {
244 uint8_t id;
245 uint8_t ioregsel;
246
247 uint32_t irr;
248 uint64_t ioredtbl[IOAPIC_NUM_PINS];
249
250#ifdef VBOX
251 /** The device instance - R3 Ptr. */
252 PPDMDEVINSR3 pDevInsR3;
253 /** The IOAPIC helpers - R3 Ptr. */
254 PCPDMIOAPICHLPR3 pIoApicHlpR3;
255
256 /** The device instance - R0 Ptr. */
257 PPDMDEVINSR0 pDevInsR0;
258 /** The IOAPIC helpers - R0 Ptr. */
259 PCPDMIOAPICHLPR0 pIoApicHlpR0;
260
261 /** The device instance - RC Ptr. */
262 PPDMDEVINSRC pDevInsRC;
263 /** The IOAPIC helpers - RC Ptr. */
264 PCPDMIOAPICHLPRC pIoApicHlpRC;
265
266# ifdef VBOX_WITH_STATISTICS
267 STAMCOUNTER StatMMIOReadGC;
268 STAMCOUNTER StatMMIOReadHC;
269 STAMCOUNTER StatMMIOWriteGC;
270 STAMCOUNTER StatMMIOWriteHC;
271 STAMCOUNTER StatSetIrqGC;
272 STAMCOUNTER StatSetIrqHC;
273# endif
274#endif /* VBOX */
275};
276
277#ifdef VBOX
278typedef struct IOAPICState IOAPICState;
279
280typedef struct
281{
282 /** The device instance - R3 Ptr. */
283 PPDMDEVINSR3 pDevInsR3;
284 /** The APIC helpers - R3 Ptr. */
285 PCPDMAPICHLPR3 pApicHlpR3;
286 /** LAPICs states - R3 Ptr */
287 RTR3PTR pLapicsR3;
288 /** The critical section - R3 Ptr. */
289 R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
290
291 /** The device instance - R0 Ptr. */
292 PPDMDEVINSR0 pDevInsR0;
293 /** The APIC helpers - R0 Ptr. */
294 PCPDMAPICHLPR0 pApicHlpR0;
295 /** LAPICs states - R0 Ptr */
296 RTR0PTR pLapicsR0;
297 /** The critical section - R3 Ptr. */
298 R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
299
300 /** The device instance - RC Ptr. */
301 PPDMDEVINSRC pDevInsRC;
302 /** The APIC helpers - RC Ptr. */
303 PCPDMAPICHLPRC pApicHlpRC;
304 /** LAPICs states - RC Ptr */
305 RTRCPTR pLapicsRC;
306 /** The critical section - R3 Ptr. */
307 RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
308 RTRCPTR Padding0;
309
310 /** APIC specification version in this virtual hardware configuration. */
311 PDMAPICVERSION enmVersion;
312
313 /** Number of attempts made to optimize TPR accesses. */
314 uint32_t cTPRPatchAttempts;
315
316 /** Number of CPUs on the system (same as LAPIC count). */
317 uint32_t cCpus;
318
319# ifdef VBOX_WITH_STATISTICS
320 STAMCOUNTER StatMMIOReadGC;
321 STAMCOUNTER StatMMIOReadHC;
322 STAMCOUNTER StatMMIOWriteGC;
323 STAMCOUNTER StatMMIOWriteHC;
324 STAMCOUNTER StatClearedActiveIrq;
325# endif
326} APICDeviceInfo;
327
328static void apic_eoi(APICDeviceInfo *dev, APICState* s);
329static int apic_deliver(APICDeviceInfo* dev, APICState *s,
330 uint8_t dest, uint8_t dest_mode,
331 uint8_t delivery_mode, uint8_t vector_num,
332 uint8_t polarity, uint8_t trigger_mode);
333static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
334 int64_t current_time);
335static int apic_get_arb_pri(APICState *s);
336static int apic_get_ppr(APICState *s);
337static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
338
339
340DECLINLINE(APICState*) getLapicById(APICDeviceInfo* dev, VMCPUID id)
341{
342 AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
343 return LAPIC_BASE(dev) + id;
344}
345
346DECLINLINE(APICState*) getLapic(APICDeviceInfo* dev)
347{
348 /* LAPIC's array is indexed by CPU id */
349 VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
350 return getLapicById(dev, id);
351}
352
353DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
354{
355 /* for now we assume LAPIC physical id == CPU id */
356 return VMCPUID(s->phys_id);
357}
358
359DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s)
360{
361 Log2(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(dev, s)));
362 dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns),
363 getCpuFromLapic(dev, s));
364}
365
366DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
367{
368 Log2(("apic: clear interrupt flag\n"));
369 dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
370 getCpuFromLapic(dev, s));
371}
372
373#ifdef IN_RING3
374DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
375{
376 Log2(("apic: send SIPI vector=%d\n", vector));
377
378 dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
379 getCpuFromLapic(dev, s),
380 vector);
381}
382
383DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* dev, APICState *s)
384{
385 Log2(("apic: send init IPI\n"));
386
387 dev->pApicHlpR3->pfnSendInitIpi(dev->pDevInsR3,
388 getCpuFromLapic(dev, s));
389}
390#endif
391
392DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
393{
394 switch (dev->enmVersion)
395 {
396 case PDMAPICVERSION_NONE:
397 return 0;
398 case PDMAPICVERSION_APIC:
399 return MSR_IA32_APICBASE_ENABLE;
400 case PDMAPICVERSION_X2APIC:
401 return MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_X2ENABLE ;
402 default:
403 AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
404 return 0;
405 }
406}
407
408DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
409{
410 switch (((apic->apicbase) >> 10) & 0x3)
411 {
412 case 0:
413 return PDMAPICVERSION_NONE;
414 case 1:
415 default:
416 /* Invalid */
417 return PDMAPICVERSION_NONE;
418 case 2:
419 return PDMAPICVERSION_APIC;
420 case 3:
421 return PDMAPICVERSION_X2APIC;
422 }
423}
424
425#endif /* VBOX */
426
427#ifndef VBOX_DEVICE_STRUCT_TESTCASE
428#ifndef VBOX
429static int apic_io_memory;
430static APICState *first_local_apic = NULL;
431static int last_apic_id = 0;
432#endif /* !VBOX */
433
434static void apic_init_ipi(APICDeviceInfo* dev, APICState *s);
435static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
436static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
437
438#ifdef VBOX
439static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
440__BEGIN_DECLS
441PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
442PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
443PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
444PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
445PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
446PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
447PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val);
448PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu);
449PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
450 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
451 uint8_t u8TriggerMode);
452PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
453PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
454PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
455PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
456PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
457
458static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val);
459__END_DECLS
460#endif /* VBOX */
461
462#ifndef VBOX
463static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
464 uint8_t vector_num, uint8_t polarity,
465 uint8_t trigger_mode)
466{
467 APICState *apic_iter;
468#else /* VBOX */
469static int apic_bus_deliver(APICDeviceInfo* dev,
470 uint32_t deliver_bitmask, uint8_t delivery_mode,
471 uint8_t vector_num, uint8_t polarity,
472 uint8_t trigger_mode)
473{
474#endif /* VBOX */
475
476 LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
477 switch (delivery_mode) {
478 case APIC_DM_LOWPRI:
479 {
480 int d = -1;
481 if (deliver_bitmask)
482 d = ffs_bit(deliver_bitmask);
483 if (d >= 0)
484 {
485 APICState* apic = getLapicById(dev, d);
486 apic_set_irq(dev, apic, vector_num, trigger_mode);
487 }
488 return VINF_SUCCESS;
489 }
490 case APIC_DM_FIXED:
491 /* XXX: arbitration */
492 break;
493
494 case APIC_DM_SMI:
495 /** @todo: what do we really do with SMI */
496 foreach_apic(dev, deliver_bitmask,
497 cpuSetInterrupt(dev, apic));
498 return VINF_SUCCESS;
499
500 case APIC_DM_NMI:
501 /** @todo: what do we really do with NMI */
502 foreach_apic(dev, deliver_bitmask,
503 cpuSetInterrupt(dev, apic));
504 return VINF_SUCCESS;
505
506 case APIC_DM_INIT:
507 /* normal INIT IPI sent to processors */
508#ifdef VBOX
509#ifdef IN_RING3
510 foreach_apic(dev, deliver_bitmask,
511 apic_init_ipi(dev, apic));
512 return VINF_SUCCESS;
513#else
514 /* We shall send init IPI only in R3, R0 calls should be
515 rescheduled to R3 */
516 return VINF_IOM_HC_MMIO_READ_WRITE;
517#endif /* IN_RING3 */
518
519#else
520 for (apic_iter = first_local_apic; apic_iter != NULL;
521 apic_iter = apic_iter->next_apic) {
522 apic_init_ipi(apic_iter);
523 }
524#endif
525
526 case APIC_DM_EXTINT:
527 /* handled in I/O APIC code */
528 break;
529
530 default:
531 return VINF_SUCCESS;
532 }
533
534#ifdef VBOX
535 foreach_apic(dev, deliver_bitmask,
536 apic_set_irq (dev, apic, vector_num, trigger_mode));
537 return VINF_SUCCESS;
538#else /* VBOX */
539 for (apic_iter = first_local_apic; apic_iter != NULL;
540 apic_iter = apic_iter->next_apic) {
541 if (deliver_bitmask & (1 << apic_iter->id))
542 apic_set_irq(apic_iter, vector_num, trigger_mode);
543 }
544#endif /* VBOX */
545}
546
547#ifndef VBOX
548void cpu_set_apic_base(CPUState *env, uint64_t val)
549{
550 APICState *s = env->apic_state;
551#ifdef DEBUG_APIC
552 Log(("cpu_set_apic_base: %016llx\n", val));
553#endif
554
555 s->apicbase = (val & 0xfffff000) |
556 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
557 /* if disabled, cannot be enabled again */
558 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
559 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
560 env->cpuid_features &= ~CPUID_APIC;
561 s->spurious_vec &= ~APIC_SV_ENABLE;
562 }
563}
564#else /* VBOX */
565PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
566{
567 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
568 APICState *s = getLapic(dev);
569 Log(("cpu_set_apic_base: %016RX64\n", val));
570
571 /** @todo: do we need to lock here ? */
572 /* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
573 /** @todo If this change is valid immediately, then we should change the MMIO registration! */
574 /* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
575 PDMAPICVERSION oldMode = getApicMode(s);
576 s->apicbase =
577 (val & 0xfffff000) | /* base */
578 (val & getApicEnableBits(dev)) | /* mode */
579 (s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
580 PDMAPICVERSION newMode = getApicMode(s);
581
582 if (oldMode != newMode)
583 {
584 switch (newMode)
585 {
586 case PDMAPICVERSION_NONE:
587 {
588 s->spurious_vec &= ~APIC_SV_ENABLE;
589 /* Clear any pending APIC interrupt action flag. */
590 cpuClearInterrupt(dev, s);
591 /** @todo: why do we do that? */
592 dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
593 break;
594 }
595 case PDMAPICVERSION_APIC:
596 /** @todo: map MMIO ranges, if needed */
597 break;
598 case PDMAPICVERSION_X2APIC:
599 /** @todo: unmap MMIO ranges of this APIC, according to the spec */
600 break;
601 default:
602 break;
603 }
604 }
605 /* APIC_UNLOCK(dev); */
606}
607#endif /* VBOX */
608#ifndef VBOX
609
610uint64_t cpu_get_apic_base(CPUState *env)
611{
612 APICState *s = env->apic_state;
613#ifdef DEBUG_APIC
614 Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
615#endif
616 return s->apicbase;
617}
618
619void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
620{
621 APICState *s = env->apic_state;
622 s->tpr = (val & 0x0f) << 4;
623 apic_update_irq(s);
624}
625
626uint8_t cpu_get_apic_tpr(CPUX86State *env)
627{
628 APICState *s = env->apic_state;
629 return s->tpr >> 4;
630}
631
632static int fls_bit(int value)
633{
634 unsigned int ret = 0;
635
636#ifdef HOST_I386
637 __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
638 return ret;
639#else
640 if (value > 0xffff)
641 value >>= 16, ret = 16;
642 if (value > 0xff)
643 value >>= 8, ret += 8;
644 if (value > 0xf)
645 value >>= 4, ret += 4;
646 if (value > 0x3)
647 value >>= 2, ret += 2;
648 return ret + (value >> 1);
649#endif
650}
651
652static inline void set_bit(uint32_t *tab, int index)
653{
654 int i, mask;
655 i = index >> 5;
656 mask = 1 << (index & 0x1f);
657 tab[i] |= mask;
658}
659
660static inline void reset_bit(uint32_t *tab, int index)
661{
662 int i, mask;
663 i = index >> 5;
664 mask = 1 << (index & 0x1f);
665 tab[i] &= ~mask;
666}
667
668
669#else /* VBOX */
670
671PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
672{
673 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
674 APICState *s = getLapic(dev);
675 LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
676 return s->apicbase;
677}
678
679PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
680{
681 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
682 APICState *s = getLapicById(dev, idCpu);
683 LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
684 apic_update_tpr(dev, s, (val & 0x0f) << 4);
685}
686
687PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
688{
689 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
690 APICState *s = getLapicById(dev, idCpu);
691 Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
692 return s->tpr >> 4;
693}
694
695PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
696{
697 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
698 int rc = VINF_SUCCESS;
699
700 if (dev->enmVersion < PDMAPICVERSION_X2APIC)
701 return VERR_EM_INTERPRETER;
702
703 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
704
705 APICState* apic = getLapicById(dev, idCpu);
706
707 switch (index)
708 {
709 case 0x02:
710 apic->id = (u64Value >> 24);
711 break;
712 case 0x03:
713 break;
714 case 0x08:
715 apic_update_tpr(dev, apic, u64Value);
716 break;
717 case 0x09: case 0x0a:
718 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
719 break;
720 case 0x0b: /* EOI */
721 apic_eoi(dev, apic);
722 break;
723 case 0x0d:
724 apic->log_dest = u64Value >> 24;
725 break;
726 case 0x0e:
727 apic->dest_mode = u64Value >> 28;
728 break;
729 case 0x0f:
730 apic->spurious_vec = u64Value & 0x1ff;
731 apic_update_irq(dev, apic);
732 break;
733 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
734 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
735 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
736 case 0x28:
737 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
738 break;
739
740 case 0x30:
741 /* Here one of the differences with regular APIC: ICR is single 64-bit register */
742 apic->icr[0] = (uint32_t)u64Value;
743 apic->icr[1] = (uint32_t)(u64Value >> 32);
744 rc = apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
745 (apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),
746 (apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
747 break;
748 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
749 {
750 int n = index - 0x32;
751 apic->lvt[n] = u64Value;
752 if (n == APIC_LVT_TIMER)
753 apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
754 }
755 break;
756 case 0x38:
757 apic->initial_count = u64Value;
758 apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
759 apic_timer_update(dev, apic, apic->initial_count_load_time);
760 break;
761 case 0x39:
762 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
763 break;
764 case 0x3e:
765 {
766 int v;
767 apic->divide_conf = u64Value & 0xb;
768 v = (apic->divide_conf & 3) | ((apic->divide_conf >> 1) & 4);
769 apic->count_shift = (v + 1) & 7;
770 break;
771 }
772 case 0x3f:
773 {
774 /* Self IPI, see x2APIC book 2.4.5 */
775 int vector = u64Value & 0xff;
776 rc = apic_bus_deliver(dev,
777 1 << getLapicById(dev, idCpu)->id /* Self */,
778 0 /* Delivery mode - fixed */,
779 vector,
780 0 /* Polarity - conform to the bus */,
781 0 /* Trigger mode - edge */);
782 break;
783 }
784 default:
785 AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
786 apic->esr |= ESR_ILLEGAL_ADDRESS;
787 break;
788 }
789
790 return rc;
791}
792PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
793{
794 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
795
796 if (dev->enmVersion < PDMAPICVERSION_X2APIC)
797 return VERR_EM_INTERPRETER;
798
799 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
800 APICState* apic = getLapicById(dev, idCpu);
801 uint64_t val = 0;
802
803 switch (index)
804 {
805 case 0x02: /* id */
806 val = apic->id << 24;
807 break;
808 case 0x03: /* version */
809 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
810 break;
811 case 0x08:
812 val = apic->tpr;
813 break;
814 case 0x09:
815 val = apic_get_arb_pri(apic);
816 break;
817 case 0x0a:
818 /* ppr */
819 val = apic_get_ppr(apic);
820 break;
821 case 0x0b:
822 val = 0;
823 break;
824 case 0x0d:
825 val = apic->log_dest << 24;
826 break;
827 case 0x0e:
828 /* Bottom 28 bits are always 1 */
829 val = (apic->dest_mode << 28) | 0xfffffff;
830 break;
831 case 0x0f:
832 val = apic->spurious_vec;
833 break;
834 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
835 val = apic->isr[index & 7];
836 break;
837 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
838 val = apic->tmr[index & 7];
839 break;
840 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
841 val = apic->irr[index & 7];
842 break;
843 case 0x28:
844 val = apic->esr;
845 break;
846 case 0x30:
847 /* Here one of the differences with regular APIC: ICR is single 64-bit register */
848 val = ((uint64_t)apic->icr[0x31] << 32) | apic->icr[0x30];
849 break;
850 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
851 val = apic->lvt[index - 0x32];
852 break;
853 case 0x38:
854 val = apic->initial_count;
855 break;
856 case 0x39:
857 val = apic_get_current_count(dev, apic);
858 break;
859 case 0x3e:
860 val = apic->divide_conf;
861 break;
862 case 0x3f:
863 /* Self IPI register is write only */
864 Log(("apicReadMSR: read from write-only register %d ignored\n", index));
865 break;
866 default:
867 AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
868 apic->esr |= ESR_ILLEGAL_ADDRESS;
869 val = 0;
870 break;
871 }
872 *pu64Value = val;
873 return VINF_SUCCESS;
874}
875
876/**
877 * More or less private interface between IOAPIC, only PDM is responsible
878 * for connecting the two devices.
879 */
880PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
881 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
882 uint8_t u8TriggerMode)
883{
884 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
885 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
886 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
887 return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
888 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
889}
890
891#endif /* VBOX */
892
893/* return -1 if no bit is set */
894static int get_highest_priority_int(uint32_t *tab)
895{
896 int i;
897 for(i = 7; i >= 0; i--) {
898 if (tab[i] != 0) {
899 return i * 32 + fls_bit(tab[i]);
900 }
901 }
902 return -1;
903}
904
905static int apic_get_ppr(APICState *s)
906{
907 int tpr, isrv, ppr;
908
909 tpr = (s->tpr >> 4);
910 isrv = get_highest_priority_int(s->isr);
911 if (isrv < 0)
912 isrv = 0;
913 isrv >>= 4;
914 if (tpr >= isrv)
915 ppr = s->tpr;
916 else
917 ppr = isrv << 4;
918 return ppr;
919}
920
921static int apic_get_ppr_zero_tpr(APICState *s)
922{
923 int isrv;
924
925 isrv = get_highest_priority_int(s->isr);
926 if (isrv < 0)
927 isrv = 0;
928 return isrv;
929}
930
931static int apic_get_arb_pri(APICState *s)
932{
933 /* XXX: arbitration */
934 return 0;
935}
936
937/* signal the CPU if an irq is pending */
938static bool apic_update_irq(APICDeviceInfo *dev, APICState* s)
939{
940 int irrv, ppr;
941 if (!(s->spurious_vec & APIC_SV_ENABLE))
942#ifdef VBOX
943 {
944 /* Clear any pending APIC interrupt action flag. */
945 cpuClearInterrupt(dev, s);
946 return false;
947 }
948#else
949 return false;
950#endif /* VBOX */
951 irrv = get_highest_priority_int(s->irr);
952 if (irrv < 0)
953 return false;
954 ppr = apic_get_ppr(s);
955 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
956 return false;
957#ifndef VBOX
958 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
959#else
960 cpuSetInterrupt(dev, s);
961 return true;
962#endif
963}
964
965#ifdef VBOX
966
967/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
968PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
969{
970 int irrv, ppr;
971 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
972 if (!dev)
973 return false;
974 APICState *s = getLapic(dev);
975
976 /*
977 * All our callbacks now come from single IOAPIC, thus locking
978 * seems to be excessive now (@todo: check)
979 */
980 irrv = get_highest_priority_int(s->irr);
981 if (irrv < 0)
982 return false;
983
984 ppr = apic_get_ppr_zero_tpr(s);
985
986 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
987 return false;
988
989 return true;
990}
991
992static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val)
993{
994 bool fIrqIsActive = false;
995 bool fIrqWasActive = false;
996
997 fIrqWasActive = apic_update_irq(dev, s);
998 s->tpr = val;
999 fIrqIsActive = apic_update_irq(dev, s);
1000
1001 /* If an interrupt is pending and now masked, then clear the FF flag. */
1002 if (fIrqWasActive && !fIrqIsActive)
1003 {
1004 Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1005 STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
1006 cpuClearInterrupt(dev, s);
1007 }
1008}
1009#endif
1010
1011static void apic_set_irq(APICDeviceInfo *dev, APICState* s, int vector_num, int trigger_mode)
1012{
1013 LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode));
1014 set_bit(s->irr, vector_num);
1015 if (trigger_mode)
1016 set_bit(s->tmr, vector_num);
1017 else
1018 reset_bit(s->tmr, vector_num);
1019 apic_update_irq(dev, s);
1020}
1021
1022static void apic_eoi(APICDeviceInfo *dev, APICState* s)
1023{
1024 int isrv;
1025 isrv = get_highest_priority_int(s->isr);
1026 if (isrv < 0)
1027 return;
1028 reset_bit(s->isr, isrv);
1029 LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1030 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1031 set the remote IRR bit for level triggered interrupts. */
1032 apic_update_irq(dev, s);
1033}
1034
1035#ifndef VBOX
1036static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1037#else /* VBOX */
1038static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1039#endif /* VBOX */
1040{
1041 uint32_t mask = 0;
1042
1043 if (dest_mode == 0)
1044 {
1045 if (dest == 0xff)
1046 mask = 0xff;
1047 else
1048 mask = 1 << dest;
1049 }
1050 else
1051 {
1052 APICState *apic = LAPIC_BASE(dev);
1053 uint32_t i;
1054
1055 /* XXX: cluster mode */
1056 for(i = 0; i < dev->cCpus; i++)
1057 {
1058 if (apic->dest_mode == 0xf)
1059 {
1060 if (dest & apic->log_dest)
1061 mask |= (1 << apic->id);
1062 }
1063 else if (apic->dest_mode == 0x0)
1064 {
1065 if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1066 &&
1067 (dest & apic->log_dest & 0x0f))
1068 {
1069 mask |= (1 << i);
1070 }
1071 }
1072 apic++;
1073 }
1074 }
1075
1076 return mask;
1077}
1078
1079#ifdef IN_RING3
1080static void apic_init_ipi(APICDeviceInfo* dev, APICState *s)
1081{
1082 int i;
1083
1084 for(i = 0; i < APIC_LVT_NB; i++)
1085 s->lvt[i] = 1 << 16; /* mask LVT */
1086 s->tpr = 0;
1087 s->spurious_vec = 0xff;
1088 s->log_dest = 0;
1089 s->dest_mode = 0xff;
1090 memset(s->isr, 0, sizeof(s->isr));
1091 memset(s->tmr, 0, sizeof(s->tmr));
1092 memset(s->irr, 0, sizeof(s->irr));
1093 s->esr = 0;
1094 memset(s->icr, 0, sizeof(s->icr));
1095 s->divide_conf = 0;
1096 s->count_shift = 0;
1097 s->initial_count = 0;
1098 s->initial_count_load_time = 0;
1099 s->next_time = 0;
1100
1101#ifdef VBOX
1102 cpuSendInitIpi(dev, s);
1103#endif
1104}
1105
1106/* send a SIPI message to the CPU to start it */
1107static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1108{
1109#ifndef VBOX
1110 CPUState *env = s->cpu_env;
1111 if (!env->halted)
1112 return;
1113 env->eip = 0;
1114 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1115 0xffff, 0);
1116 env->halted = 0;
1117#else
1118 Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1119 cpuSendSipi(dev, s, vector_num);
1120#endif
1121}
1122#endif /* IN_RING3 */
1123
1124static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1125 uint8_t dest, uint8_t dest_mode,
1126 uint8_t delivery_mode, uint8_t vector_num,
1127 uint8_t polarity, uint8_t trigger_mode)
1128{
1129 uint32_t deliver_bitmask = 0;
1130 int dest_shorthand = (s->icr[0] >> 18) & 3;
1131#ifndef VBOX
1132 APICState *apic_iter;
1133#endif /* !VBOX */
1134
1135 LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1136
1137 switch (dest_shorthand) {
1138 case 0:
1139#ifndef VBOX
1140 deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1141#else /* VBOX */
1142 deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1143#endif /* !VBOX */
1144 break;
1145 case 1:
1146 deliver_bitmask = (1 << s->id);
1147 break;
1148 case 2:
1149 deliver_bitmask = 0xffffffff;
1150 break;
1151 case 3:
1152 deliver_bitmask = 0xffffffff & ~(1 << s->id);
1153 break;
1154 }
1155
1156 switch (delivery_mode) {
1157 case APIC_DM_INIT:
1158 {
1159 int trig_mode = (s->icr[0] >> 15) & 1;
1160 int level = (s->icr[0] >> 14) & 1;
1161 if (level == 0 && trig_mode == 1) {
1162 foreach_apic(dev, deliver_bitmask,
1163 apic->arb_id = apic->id);
1164#ifndef VBOX
1165 return;
1166#else
1167 Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1168 return VINF_SUCCESS;
1169#endif
1170 }
1171 }
1172 break;
1173
1174 case APIC_DM_SIPI:
1175#ifndef VBOX
1176 for (apic_iter = first_local_apic; apic_iter != NULL;
1177 apic_iter = apic_iter->next_apic) {
1178 if (deliver_bitmask & (1 << apic_iter->id)) {
1179 /* XXX: SMP support */
1180 /* apic_startup(apic_iter); */
1181 }
1182 }
1183 return;
1184#else
1185# ifdef IN_RING3
1186 foreach_apic(dev, deliver_bitmask,
1187 apic_startup(dev, apic, vector_num));
1188 return VINF_SUCCESS;
1189# else
1190 /* We shall send SIPI only in R3, R0 calls should be
1191 rescheduled to R3 */
1192 return VINF_IOM_HC_MMIO_WRITE;
1193# endif
1194#endif /* !VBOX */
1195 }
1196
1197#ifndef VBOX
1198 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1199 trigger_mode);
1200#else /* VBOX */
1201 return apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num,
1202 polarity, trigger_mode);
1203#endif /* VBOX */
1204}
1205
1206
1207PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1208{
1209 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1210 /* if the APIC is not installed or enabled, we let the 8259 handle the
1211 IRQs */
1212 if (!dev)
1213 {
1214 Log(("apic_get_interrupt: returns -1 (!s)\n"));
1215 return -1;
1216 }
1217
1218 APIC_LOCK(dev, VERR_INTERNAL_ERROR);
1219
1220 APICState *s = getLapic(dev);
1221 int intno;
1222
1223 if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1224 Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
1225 intno = -1;
1226 goto done;
1227 }
1228
1229 /* XXX: spurious IRQ handling */
1230 intno = get_highest_priority_int(s->irr);
1231 if (intno < 0) {
1232 Log(("apic_get_interrupt: returns -1 (irr)\n"));
1233 intno = -1;
1234 goto done;
1235 }
1236 if (s->tpr && (uint32_t)intno <= s->tpr) {
1237 Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1238 intno = s->spurious_vec & 0xff;
1239 goto done;
1240 }
1241 reset_bit(s->irr, intno);
1242 set_bit(s->isr, intno);
1243 apic_update_irq(dev, s);
1244 LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno));
1245 done:
1246 APIC_UNLOCK(dev);
1247 return intno;
1248}
1249
1250static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
1251{
1252 int64_t d;
1253 uint32_t val;
1254#ifndef VBOX
1255 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1256 s->count_shift;
1257#else /* VBOX */
1258 d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1259 s->count_shift;
1260#endif /* VBOX */
1261 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1262 /* periodic */
1263 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1264 } else {
1265 if (d >= s->initial_count)
1266 val = 0;
1267 else
1268 val = s->initial_count - d;
1269 }
1270 return val;
1271}
1272
1273static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1274{
1275 int64_t next_time, d;
1276
1277 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1278 d = (current_time - s->initial_count_load_time) >>
1279 s->count_shift;
1280 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1281 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1282 } else {
1283 if (d >= s->initial_count)
1284 goto no_timer;
1285 d = (uint64_t)s->initial_count + 1;
1286 }
1287 next_time = s->initial_count_load_time + (d << s->count_shift);
1288#ifndef VBOX
1289 qemu_mod_timer(s->timer, next_time);
1290#else
1291 TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1292#endif
1293 s->next_time = next_time;
1294 } else {
1295 no_timer:
1296#ifndef VBOX
1297 qemu_del_timer(s->timer);
1298#else
1299 TMTimerStop(s->CTX_SUFF(pTimer));
1300#endif
1301 }
1302}
1303
1304#ifdef IN_RING3
1305# ifndef VBOX
1306static void apic_timer(void *opaque)
1307{
1308 APICState *s = opaque;
1309# else /* VBOX */
1310static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1311{
1312 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1313 APICState *s = (APICState *)pvUser;
1314 Assert(s->pTimerR3 == pTimer);
1315# endif /* VBOX */
1316
1317 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1318 LogFlow(("apic_timer: trigger irq\n"));
1319 apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1320 }
1321 apic_timer_update(dev, s, s->next_time);
1322}
1323#endif /* IN_RING3 */
1324
1325#ifndef VBOX
1326static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1327{
1328 return 0;
1329}
1330static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1331{
1332 return 0;
1333}
1334
1335static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1336{
1337}
1338
1339static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1340{
1341}
1342#endif /* !VBOX */
1343
1344
1345#ifndef VBOX
1346static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1347{
1348 CPUState *env;
1349 APICState *s;
1350#else /* VBOX */
1351static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1352{
1353#endif /* VBOX */
1354 uint32_t val;
1355 int index;
1356
1357#ifndef VBOX
1358 env = cpu_single_env;
1359 if (!env)
1360 return 0;
1361 s = env->apic_state;
1362#endif /* !VBOX */
1363
1364 index = (addr >> 4) & 0xff;
1365 switch(index) {
1366 case 0x02: /* id */
1367 val = s->id << 24;
1368 break;
1369 case 0x03: /* version */
1370 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1371 break;
1372 case 0x08:
1373 val = s->tpr;
1374 break;
1375 case 0x09:
1376 val = apic_get_arb_pri(s);
1377 break;
1378 case 0x0a:
1379 /* ppr */
1380 val = apic_get_ppr(s);
1381 break;
1382 case 0x0b:
1383 Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1384 val = 0;
1385 break;
1386 case 0x0d:
1387 val = s->log_dest << 24;
1388 break;
1389 case 0x0e:
1390#ifdef VBOX
1391 /* Bottom 28 bits are always 1 */
1392 val = (s->dest_mode << 28) | 0xfffffff;
1393#else
1394 val = s->dest_mode << 28;
1395#endif
1396 break;
1397 case 0x0f:
1398 val = s->spurious_vec;
1399 break;
1400#ifndef VBOX
1401 case 0x10 ... 0x17:
1402#else /* VBOX */
1403 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1404#endif /* VBOX */
1405 val = s->isr[index & 7];
1406 break;
1407#ifndef VBOX
1408 case 0x18 ... 0x1f:
1409#else /* VBOX */
1410 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1411#endif /* VBOX */
1412 val = s->tmr[index & 7];
1413 break;
1414#ifndef VBOX
1415 case 0x20 ... 0x27:
1416#else /* VBOX */
1417 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1418#endif /* VBOX */
1419 val = s->irr[index & 7];
1420 break;
1421 case 0x28:
1422 val = s->esr;
1423 break;
1424 case 0x30:
1425 case 0x31:
1426 val = s->icr[index & 1];
1427 break;
1428#ifndef VBOX
1429 case 0x32 ... 0x37:
1430#else /* VBOX */
1431 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1432#endif /* VBOX */
1433 val = s->lvt[index - 0x32];
1434 break;
1435 case 0x38:
1436 val = s->initial_count;
1437 break;
1438 case 0x39:
1439 val = apic_get_current_count(dev, s);
1440 break;
1441 case 0x3e:
1442 val = s->divide_conf;
1443 break;
1444 default:
1445 AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1446 s->esr |= ESR_ILLEGAL_ADDRESS;
1447 val = 0;
1448 break;
1449 }
1450#ifdef DEBUG_APIC
1451 Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1452#endif
1453 return val;
1454}
1455
1456#ifndef VBOX
1457static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1458{
1459 CPUState *env;
1460 APICState *s;
1461#else /* VBOX */
1462static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1463{
1464 int rc = VINF_SUCCESS;
1465#endif /* VBOX */
1466 int index;
1467
1468#ifndef VBOX
1469 env = cpu_single_env;
1470 if (!env)
1471 return;
1472 s = env->apic_state;
1473#endif /* !VBOX */
1474
1475#ifdef DEBUG_APIC
1476 Log(("CPU%d: APIC write: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1477#endif
1478
1479 index = (addr >> 4) & 0xff;
1480 switch(index) {
1481 case 0x02:
1482 s->id = (val >> 24);
1483 break;
1484 case 0x03:
1485 Log(("apic_mem_writel: write to version register; ignored\n"));
1486 break;
1487 case 0x08:
1488#ifdef VBOX
1489 apic_update_tpr(dev, s, val);
1490#else
1491 s->tpr = val;
1492 apic_update_irq(s);
1493#endif
1494 break;
1495 case 0x09:
1496 case 0x0a:
1497 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1498 break;
1499 case 0x0b: /* EOI */
1500 apic_eoi(dev, s);
1501 break;
1502 case 0x0d:
1503 s->log_dest = val >> 24;
1504 break;
1505 case 0x0e:
1506 s->dest_mode = val >> 28;
1507 break;
1508 case 0x0f:
1509 s->spurious_vec = val & 0x1ff;
1510 apic_update_irq(dev, s);
1511 break;
1512#ifndef VBOX
1513 case 0x10 ... 0x17:
1514 case 0x18 ... 0x1f:
1515 case 0x20 ... 0x27:
1516 case 0x28:
1517#else
1518 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1519 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1520 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1521 case 0x28:
1522 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1523#endif
1524 break;
1525
1526 case 0x30:
1527 s->icr[0] = val;
1528 rc = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1529 (s->icr[0] >> 11) & 1,
1530 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1531 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1532 break;
1533 case 0x31:
1534 s->icr[1] = val;
1535 break;
1536#ifndef VBOX
1537 case 0x32 ... 0x37:
1538#else /* VBOX */
1539 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1540#endif /* VBOX */
1541 {
1542 int n = index - 0x32;
1543 s->lvt[n] = val;
1544 if (n == APIC_LVT_TIMER)
1545#ifndef VBOX
1546 apic_timer_update(s, qemu_get_clock(vm_clock));
1547#else /* VBOX */
1548 apic_timer_update(dev, s, TMTimerGet(s->CTX_SUFF(pTimer)));
1549#endif /* VBOX*/
1550 }
1551 break;
1552 case 0x38:
1553 s->initial_count = val;
1554#ifndef VBOX
1555 s->initial_count_load_time = qemu_get_clock(vm_clock);
1556#else /* VBOX */
1557 s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
1558#endif /* VBOX*/
1559 apic_timer_update(dev, s, s->initial_count_load_time);
1560 break;
1561 case 0x39:
1562 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1563 break;
1564 case 0x3e:
1565 {
1566 int v;
1567 s->divide_conf = val & 0xb;
1568 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
1569 s->count_shift = (v + 1) & 7;
1570 }
1571 break;
1572 default:
1573 AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1574 s->esr |= ESR_ILLEGAL_ADDRESS;
1575 break;
1576 }
1577#ifdef VBOX
1578 return rc;
1579#endif
1580}
1581
1582#ifdef IN_RING3
1583
1584static void apic_save(QEMUFile *f, void *opaque)
1585{
1586 APICState *s = (APICState*)opaque;
1587 int i;
1588
1589 qemu_put_be32s(f, &s->apicbase);
1590#ifdef VBOX
1591 qemu_put_be32s(f, &s->id);
1592 qemu_put_be32s(f, &s->phys_id);
1593 qemu_put_be32s(f, &s->arb_id);
1594 qemu_put_be32s(f, &s->tpr);
1595#else
1596 qemu_put_8s(f, &s->id);
1597 qemu_put_8s(f, &s->arb_id);
1598 qemu_put_8s(f, &s->tpr);
1599#endif
1600 qemu_put_be32s(f, &s->spurious_vec);
1601 qemu_put_8s(f, &s->log_dest);
1602 qemu_put_8s(f, &s->dest_mode);
1603 for (i = 0; i < 8; i++) {
1604 qemu_put_be32s(f, &s->isr[i]);
1605 qemu_put_be32s(f, &s->tmr[i]);
1606 qemu_put_be32s(f, &s->irr[i]);
1607 }
1608 for (i = 0; i < APIC_LVT_NB; i++) {
1609 qemu_put_be32s(f, &s->lvt[i]);
1610 }
1611 qemu_put_be32s(f, &s->esr);
1612 qemu_put_be32s(f, &s->icr[0]);
1613 qemu_put_be32s(f, &s->icr[1]);
1614 qemu_put_be32s(f, &s->divide_conf);
1615 qemu_put_be32s(f, &s->count_shift);
1616 qemu_put_be32s(f, &s->initial_count);
1617 qemu_put_be64s(f, &s->initial_count_load_time);
1618 qemu_put_be64s(f, &s->next_time);
1619
1620#ifdef VBOX
1621 TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1622#endif
1623}
1624
1625static int apic_load(QEMUFile *f, void *opaque, int version_id)
1626{
1627 APICState *s = (APICState*)opaque;
1628 int i;
1629
1630#ifdef VBOX
1631 if ((version_id < 1) || (version_id > 2))
1632 return -EINVAL;
1633
1634 /* XXX: what if the base changes? (registered memory regions) */
1635 qemu_get_be32s(f, &s->apicbase);
1636
1637 switch (version_id)
1638 {
1639 case 1:
1640 {
1641 uint8_t val = 0;
1642 qemu_get_8s(f, &val);
1643 s->id = val;
1644 /* UP only in old saved states */
1645 s->phys_id = 0;
1646 qemu_get_8s(f, &val);
1647 s->arb_id = val;
1648 break;
1649 }
1650 case 2:
1651 qemu_get_be32s(f, &s->id);
1652 qemu_get_be32s(f, &s->phys_id);
1653 qemu_get_be32s(f, &s->arb_id);
1654 break;
1655 }
1656 qemu_get_be32s(f, &s->tpr);
1657#else
1658 if (version_id != 1)
1659 return -EINVAL;
1660
1661 /* XXX: what if the base changes? (registered memory regions) */
1662 qemu_get_be32s(f, &s->apicbase);
1663 qemu_get_8s(f, &s->id);
1664 qemu_get_8s(f, &s->arb_id);
1665 qemu_get_8s(f, &s->tpr);
1666#endif
1667 qemu_get_be32s(f, &s->spurious_vec);
1668 qemu_get_8s(f, &s->log_dest);
1669 qemu_get_8s(f, &s->dest_mode);
1670 for (i = 0; i < 8; i++) {
1671 qemu_get_be32s(f, &s->isr[i]);
1672 qemu_get_be32s(f, &s->tmr[i]);
1673 qemu_get_be32s(f, &s->irr[i]);
1674 }
1675 for (i = 0; i < APIC_LVT_NB; i++) {
1676 qemu_get_be32s(f, &s->lvt[i]);
1677 }
1678 qemu_get_be32s(f, &s->esr);
1679 qemu_get_be32s(f, &s->icr[0]);
1680 qemu_get_be32s(f, &s->icr[1]);
1681 qemu_get_be32s(f, &s->divide_conf);
1682 qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1683 qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1684 qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1685 qemu_get_be64s(f, (uint64_t *)&s->next_time);
1686
1687#ifdef VBOX
1688 TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1689#endif
1690
1691 return VINF_SUCCESS;
1692}
1693#ifndef VBOX
1694static void apic_reset(void *opaque)
1695{
1696 APICState *s = (APICState*)opaque;
1697 apic_init_ipi(s);
1698}
1699#endif
1700
1701#endif /* IN_RING3 */
1702
1703#ifndef VBOX
1704static CPUReadMemoryFunc *apic_mem_read[3] = {
1705 apic_mem_readb,
1706 apic_mem_readw,
1707 apic_mem_readl,
1708};
1709
1710static CPUWriteMemoryFunc *apic_mem_write[3] = {
1711 apic_mem_writeb,
1712 apic_mem_writew,
1713 apic_mem_writel,
1714};
1715
1716int apic_init(CPUState *env)
1717{
1718 APICState *s;
1719
1720 s = qemu_mallocz(sizeof(APICState));
1721 if (!s)
1722 return -1;
1723 env->apic_state = s;
1724 apic_init_ipi(s);
1725 s->id = last_apic_id++;
1726 s->cpu_env = env;
1727 s->apicbase = 0xfee00000 |
1728 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
1729
1730 /* XXX: mapping more APICs at the same memory location */
1731 if (apic_io_memory == 0) {
1732 /* NOTE: the APIC is directly connected to the CPU - it is not
1733 on the global memory bus. */
1734 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1735 apic_mem_write, NULL);
1736 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1737 apic_io_memory);
1738 }
1739 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1740
1741 register_savevm("apic", 0, 1, apic_save, apic_load, s);
1742 qemu_register_reset(apic_reset, s);
1743
1744 s->next_apic = first_local_apic;
1745 first_local_apic = s;
1746
1747 return 0;
1748}
1749#endif /* !VBOX */
1750
1751static void ioapic_service(IOAPICState *s)
1752{
1753 uint8_t i;
1754 uint8_t trig_mode;
1755 uint8_t vector;
1756 uint8_t delivery_mode;
1757 uint32_t mask;
1758 uint64_t entry;
1759 uint8_t dest;
1760 uint8_t dest_mode;
1761 uint8_t polarity;
1762
1763 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1764 mask = 1 << i;
1765 if (s->irr & mask) {
1766 entry = s->ioredtbl[i];
1767 if (!(entry & APIC_LVT_MASKED)) {
1768 trig_mode = ((entry >> 15) & 1);
1769 dest = entry >> 56;
1770 dest_mode = (entry >> 11) & 1;
1771 delivery_mode = (entry >> 8) & 7;
1772 polarity = (entry >> 13) & 1;
1773 if (trig_mode == APIC_TRIGGER_EDGE)
1774 s->irr &= ~mask;
1775 if (delivery_mode == APIC_DM_EXTINT)
1776#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1777 vector = pic_read_irq(isa_pic);
1778#else /* VBOX */
1779 {
1780 AssertMsgFailed(("Delivery mode ExtINT"));
1781 vector = 0xff; /* incorrect but shuts up gcc. */
1782 }
1783#endif /* VBOX */
1784 else
1785 vector = entry & 0xff;
1786
1787#ifndef VBOX
1788 apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1789 delivery_mode, vector, polarity, trig_mode);
1790#else /* VBOX */
1791 int rc = s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1792 dest,
1793 dest_mode,
1794 delivery_mode,
1795 vector,
1796 polarity,
1797 trig_mode);
1798 /* We must be sure that attempts to reschedule in R3
1799 never get here */
1800 Assert(rc == VINF_SUCCESS);
1801#endif /* VBOX */
1802 }
1803 }
1804 }
1805}
1806
1807#ifdef VBOX
1808static
1809#endif
1810void ioapic_set_irq(void *opaque, int vector, int level)
1811{
1812 IOAPICState *s = (IOAPICState*)opaque;
1813
1814 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1815 uint32_t mask = 1 << vector;
1816 uint64_t entry = s->ioredtbl[vector];
1817
1818 if ((entry >> 15) & 1) {
1819 /* level triggered */
1820 if (level) {
1821 s->irr |= mask;
1822 ioapic_service(s);
1823#ifdef VBOX
1824 if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1825 s->irr &= ~mask;
1826 }
1827#endif
1828 } else {
1829 s->irr &= ~mask;
1830 }
1831 } else {
1832 /* edge triggered */
1833 if (level) {
1834 s->irr |= mask;
1835 ioapic_service(s);
1836 }
1837 }
1838 }
1839}
1840
1841static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1842{
1843 IOAPICState *s = (IOAPICState*)opaque;
1844 int index;
1845 uint32_t val = 0;
1846
1847 addr &= 0xff;
1848 if (addr == 0x00) {
1849 val = s->ioregsel;
1850 } else if (addr == 0x10) {
1851 switch (s->ioregsel) {
1852 case 0x00:
1853 val = s->id << 24;
1854 break;
1855 case 0x01:
1856 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1857 break;
1858 case 0x02:
1859 val = 0;
1860 break;
1861 default:
1862 index = (s->ioregsel - 0x10) >> 1;
1863 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1864 if (s->ioregsel & 1)
1865 val = s->ioredtbl[index] >> 32;
1866 else
1867 val = s->ioredtbl[index] & 0xffffffff;
1868 }
1869 }
1870#ifdef DEBUG_IOAPIC
1871 Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1872#endif
1873 }
1874 return val;
1875}
1876
1877static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1878{
1879 IOAPICState *s = (IOAPICState*)opaque;
1880 int index;
1881
1882 addr &= 0xff;
1883 if (addr == 0x00) {
1884 s->ioregsel = val;
1885 return;
1886 } else if (addr == 0x10) {
1887#ifdef DEBUG_IOAPIC
1888 Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1889#endif
1890 switch (s->ioregsel) {
1891 case 0x00:
1892 s->id = (val >> 24) & 0xff;
1893 return;
1894 case 0x01:
1895 case 0x02:
1896 return;
1897 default:
1898 index = (s->ioregsel - 0x10) >> 1;
1899 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1900 if (s->ioregsel & 1) {
1901 s->ioredtbl[index] &= 0xffffffff;
1902 s->ioredtbl[index] |= (uint64_t)val << 32;
1903 } else {
1904#ifdef VBOX
1905 /* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1906 uint8_t vec = val & 0xff;
1907 if ((val & APIC_LVT_MASKED) ||
1908 ((vec >= 0x10) && (vec < 0xff)))
1909 {
1910 s->ioredtbl[index] &= ~0xffffffffULL;
1911 s->ioredtbl[index] |= val;
1912 }
1913 else
1914 {
1915 /*
1916 * Linux 2.6 kernels has pretty strange function
1917 * unlock_ExtINT_logic() which writes
1918 * absolutely bogus (all 0) value into the vector
1919 * with pretty vague explanation why.
1920 * So we just ignore such writes.
1921 */
1922 LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1923 }
1924 }
1925#else
1926 s->ioredtbl[index] &= ~0xffffffffULL;
1927 s->ioredtbl[index] |= val;
1928#endif
1929 ioapic_service(s);
1930 }
1931 }
1932 }
1933}
1934
1935#ifdef IN_RING3
1936
1937static void ioapic_save(QEMUFile *f, void *opaque)
1938{
1939 IOAPICState *s = (IOAPICState*)opaque;
1940 int i;
1941
1942 qemu_put_8s(f, &s->id);
1943 qemu_put_8s(f, &s->ioregsel);
1944 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1945 qemu_put_be64s(f, &s->ioredtbl[i]);
1946 }
1947}
1948
1949static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1950{
1951 IOAPICState *s = (IOAPICState*)opaque;
1952 int i;
1953
1954 if (version_id != 1)
1955 return -EINVAL;
1956
1957 qemu_get_8s(f, &s->id);
1958 qemu_get_8s(f, &s->ioregsel);
1959 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1960 qemu_get_be64s(f, &s->ioredtbl[i]);
1961 }
1962 return 0;
1963}
1964
1965static void ioapic_reset(void *opaque)
1966{
1967 IOAPICState *s = (IOAPICState*)opaque;
1968#ifdef VBOX
1969 PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1970 PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1971#endif
1972 int i;
1973
1974 memset(s, 0, sizeof(*s));
1975 for(i = 0; i < IOAPIC_NUM_PINS; i++)
1976 s->ioredtbl[i] = 1 << 16; /* mask LVT */
1977
1978#ifdef VBOX
1979 if (pDevIns)
1980 {
1981 s->pDevInsR3 = pDevIns;
1982 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1983 s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1984 }
1985 if (pIoApicHlp)
1986 {
1987 s->pIoApicHlpR3 = pIoApicHlp;
1988 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1989 s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1990 }
1991#endif
1992}
1993
1994#endif /* IN_RING3 */
1995
1996#ifndef VBOX
1997static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1998 ioapic_mem_readl,
1999 ioapic_mem_readl,
2000 ioapic_mem_readl,
2001};
2002
2003static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
2004 ioapic_mem_writel,
2005 ioapic_mem_writel,
2006 ioapic_mem_writel,
2007};
2008
2009IOAPICState *ioapic_init(void)
2010{
2011 IOAPICState *s;
2012 int io_memory;
2013
2014 s = qemu_mallocz(sizeof(IOAPICState));
2015 if (!s)
2016 return NULL;
2017 ioapic_reset(s);
2018 s->id = last_apic_id++;
2019
2020 io_memory = cpu_register_io_memory(0, ioapic_mem_read,
2021 ioapic_mem_write, s);
2022 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2023
2024 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2025 qemu_register_reset(ioapic_reset, s);
2026
2027 return s;
2028}
2029#endif /* !VBOX */
2030
2031/* LAPIC */
2032PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2033{
2034 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2035 APICState *s = getLapic(dev);
2036
2037 Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2038
2039 /** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2040 different physical addresses, see #3092) */
2041
2042 STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2043 switch (cb)
2044 {
2045 case 1:
2046 *(uint8_t *)pv = 0;
2047 break;
2048
2049 case 2:
2050 *(uint16_t *)pv = 0;
2051 break;
2052
2053 case 4:
2054 {
2055#if 0 /** @note experimental */
2056#ifndef IN_RING3
2057 uint32_t index = (GCPhysAddr >> 4) & 0xff;
2058
2059 if ( index == 0x08 /* TPR */
2060 && ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2061 {
2062#ifdef IN_RC
2063 pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2064#else
2065 RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2066 pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2067#endif
2068 return VINF_PATM_HC_MMIO_PATCH_READ;
2069 }
2070#endif
2071#endif /* experimental */
2072 APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2073 *(uint32_t *)pv = apic_mem_readl(dev, s, GCPhysAddr);
2074 APIC_UNLOCK(dev);
2075 break;
2076 }
2077 default:
2078 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2079 return VERR_INTERNAL_ERROR;
2080 }
2081 return VINF_SUCCESS;
2082}
2083
2084PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2085{
2086 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2087 APICState *s = getLapic(dev);
2088
2089 Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2090
2091 /** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2092 different physical addresses, see #3092) */
2093
2094 STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2095 switch (cb)
2096 {
2097 case 1:
2098 case 2:
2099 /* ignore */
2100 break;
2101
2102 case 4:
2103 {
2104 int rc;
2105 APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2106 rc = apic_mem_writel(dev, s, GCPhysAddr, *(uint32_t *)pv);
2107 APIC_UNLOCK(dev);
2108 return rc;
2109 }
2110
2111 default:
2112 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2113 return VERR_INTERNAL_ERROR;
2114 }
2115 return VINF_SUCCESS;
2116}
2117
2118#ifdef IN_RING3
2119
2120/**
2121 * @copydoc FNSSMDEVSAVEEXEC
2122 */
2123static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2124{
2125 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2126
2127 /* save all APICs data, @todo: is it correct? */
2128 foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
2129
2130 return VINF_SUCCESS;
2131}
2132
2133/**
2134 * @copydoc FNSSMDEVLOADEXEC
2135 */
2136static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2137{
2138 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2139 /* load all APICs data, @todo: is it correct? */
2140 foreach_apic(dev, 0xffffffff,
2141 if (apic_load(pSSMHandle, apic, u32Version))
2142 {
2143 AssertFailed();
2144 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2145 }
2146 );
2147 return VINF_SUCCESS;
2148}
2149
2150/**
2151 * @copydoc FNPDMDEVRESET
2152 */
2153static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2154{
2155 APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2156 APICState *s = getLapic(dev);
2157
2158 APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2159
2160 TMTimerStop(s->CTX_SUFF(pTimer));
2161
2162 apic_init_ipi(dev, s);
2163 /* malc, I've removed the initing duplicated in apic_init_ipi(). This
2164 * arb_id was left over.. */
2165 s->arb_id = 0;
2166 /* Reset should re-enable the APIC. */
2167 s->apicbase = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2168 if (s->phys_id == 0)
2169 s->apicbase |= MSR_IA32_APICBASE_BSP;
2170 dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2171 /* Clear any pending APIC interrupt action flag. */
2172 cpuClearInterrupt(dev, s);
2173 APIC_UNLOCK(dev);
2174}
2175
2176/**
2177 * @copydoc FNPDMDEVRELOCATE
2178 */
2179static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2180{
2181 APICDeviceInfo *pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2182 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2183 pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2184 pThis->pLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pThis->pLapicsR3);
2185 pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2186 foreach_apic(pThis, 0xffffffff,
2187 apic->pTimerRC = TMTimerRCPtr(apic->CTX_SUFF(pTimer)));
2188}
2189
2190DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2191{
2192 int i;
2193 memset(apic, 0, sizeof(*apic));
2194 apic->apicbase = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_ENABLE;
2195 /* Mark first CPU as BSP */
2196 if (id == 0)
2197 apic->apicbase |= MSR_IA32_APICBASE_BSP;
2198 for (i = 0; i < APIC_LVT_NB; i++)
2199 apic->lvt[i] = 1 << 16; /* mask LVT */
2200 apic->spurious_vec = 0xff;
2201 apic->phys_id = apic->id = id;
2202}
2203
2204/**
2205 * @copydoc FNPDMDEVCONSTRUCT
2206 */
2207static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2208{
2209 PDMAPICREG ApicReg;
2210 int rc;
2211 uint32_t i;
2212 bool fIOAPIC;
2213 bool fGCEnabled;
2214 bool fR0Enabled;
2215 APICDeviceInfo *pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2216 uint32_t cCpus;
2217 APICState *apic;
2218
2219 /*
2220 * Only single device instance.
2221 */
2222 Assert(iInstance == 0);
2223
2224 /*
2225 * Validate configuration.
2226 */
2227 if (!CFGMR3AreValuesValid(pCfgHandle,
2228 "IOAPIC\0"
2229 "GCEnabled\0"
2230 "R0Enabled\0"
2231 "NumCPUs\0"))
2232 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2233
2234 rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIOAPIC, true);
2235 if (RT_FAILURE(rc))
2236 return PDMDEV_SET_ERROR(pDevIns, rc,
2237 N_("Configuration error: Failed to read \"IOAPIC\""));
2238
2239 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2240 if (RT_FAILURE(rc))
2241 return PDMDEV_SET_ERROR(pDevIns, rc,
2242 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2243
2244 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2245 if (RT_FAILURE(rc))
2246 return PDMDEV_SET_ERROR(pDevIns, rc,
2247 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2248
2249 rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2250 if (RT_FAILURE(rc))
2251 return PDMDEV_SET_ERROR(pDevIns, rc,
2252 N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2253
2254 Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
2255
2256 /* TODO: Current implementation is limited to 32 CPUs due to the use of 32 bits bitmasks. */
2257 if (cCpus > 32)
2258 return PDMDEV_SET_ERROR(pDevIns, rc,
2259 N_("Configuration error: Invalid value for \"NumCPUs\""));
2260
2261 /*
2262 * Init the data.
2263 */
2264 pThis->pDevInsR3 = pDevIns;
2265 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2266 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2267 pThis->cCpus = cCpus;
2268 /* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2269 pThis->enmVersion = PDMAPICVERSION_APIC;
2270
2271 PVM pVM = PDMDevHlpGetVM(pDevIns);
2272 /*
2273 * We are not freeing this memory, as it's automatically released when guest exits.
2274 */
2275 rc = MMHyperAlloc(pVM, cCpus*sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->pLapicsR3);
2276 if (RT_FAILURE(rc))
2277 return VERR_NO_MEMORY;
2278 pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
2279 pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
2280
2281 for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2282 {
2283 initApicData(apic, i);
2284 apic++;
2285 }
2286
2287 /*
2288 * Register the APIC.
2289 */
2290 ApicReg.u32Version = PDM_APICREG_VERSION;
2291 ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2292 ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2293 ApicReg.pfnSetBaseR3 = apicSetBase;
2294 ApicReg.pfnGetBaseR3 = apicGetBase;
2295 ApicReg.pfnSetTPRR3 = apicSetTPR;
2296 ApicReg.pfnGetTPRR3 = apicGetTPR;
2297 ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2298 ApicReg.pfnReadMSRR3 = apicReadMSR;
2299 ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2300 if (fGCEnabled) {
2301 ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2302 ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2303 ApicReg.pszSetBaseRC = "apicSetBase";
2304 ApicReg.pszGetBaseRC = "apicGetBase";
2305 ApicReg.pszSetTPRRC = "apicSetTPR";
2306 ApicReg.pszGetTPRRC = "apicGetTPR";
2307 ApicReg.pszWriteMSRRC = "apicWriteMSR";
2308 ApicReg.pszReadMSRRC = "apicReadMSR";
2309 ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2310 } else {
2311 ApicReg.pszGetInterruptRC = NULL;
2312 ApicReg.pszHasPendingIrqRC = NULL;
2313 ApicReg.pszSetBaseRC = NULL;
2314 ApicReg.pszGetBaseRC = NULL;
2315 ApicReg.pszSetTPRRC = NULL;
2316 ApicReg.pszGetTPRRC = NULL;
2317 ApicReg.pszWriteMSRRC = NULL;
2318 ApicReg.pszReadMSRRC = NULL;
2319 ApicReg.pszBusDeliverRC = NULL;
2320 }
2321 if (fR0Enabled) {
2322 ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2323 ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2324 ApicReg.pszSetBaseR0 = "apicSetBase";
2325 ApicReg.pszGetBaseR0 = "apicGetBase";
2326 ApicReg.pszSetTPRR0 = "apicSetTPR";
2327 ApicReg.pszGetTPRR0 = "apicGetTPR";
2328 ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2329 ApicReg.pszReadMSRR0 = "apicReadMSR";
2330 ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2331 } else {
2332 ApicReg.pszGetInterruptR0 = NULL;
2333 ApicReg.pszHasPendingIrqR0 = NULL;
2334 ApicReg.pszSetBaseR0 = NULL;
2335 ApicReg.pszGetBaseR0 = NULL;
2336 ApicReg.pszSetTPRR0 = NULL;
2337 ApicReg.pszGetTPRR0 = NULL;
2338 ApicReg.pszWriteMSRR0 = NULL;
2339 ApicReg.pszReadMSRR0 = NULL;
2340 ApicReg.pszBusDeliverR0 = NULL;
2341 }
2342
2343 Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2344 rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2345 if (RT_FAILURE(rc))
2346 {
2347 AssertLogRelMsgFailed(("APICRegister -> %Rrc\n", rc));
2348 return rc;
2349 }
2350 pThis->pCritSectR3 = pThis->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2351
2352 /*
2353 * The the CPUID feature bit.
2354 */
2355 uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2356 PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2357 if (u32Eax >= 1)
2358 {
2359 if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
2360 || ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2361 && u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2362 && u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2363 || ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2364 && u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2365 && u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2366 {
2367 LogRel(("Activating Local APIC\n"));
2368 pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2369 }
2370 }
2371
2372 /*
2373 * Register the MMIO range.
2374 */
2375 rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
2376 apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2377 if (RT_FAILURE(rc))
2378 return rc;
2379
2380 if (fGCEnabled) {
2381 pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2382 pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2383
2384 rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2385 "apicMMIOWrite", "apicMMIORead", NULL);
2386 if (RT_FAILURE(rc))
2387 return rc;
2388 }
2389
2390 if (fR0Enabled) {
2391 pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2392 pThis->pCritSectR0 = pThis->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2393
2394 rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2395 "apicMMIOWrite", "apicMMIORead", NULL);
2396 if (RT_FAILURE(rc))
2397 return rc;
2398 }
2399
2400 /*
2401 * Create the APIC timers.
2402 */
2403 for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2404 {
2405 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer, apic,
2406 TMTIMER_FLAGS_NO_CRIT_SECT, "APIC Timer", &apic->pTimerR3);
2407 if (RT_FAILURE(rc))
2408 return rc;
2409 apic->pTimerR0 = TMTimerR0Ptr(apic->pTimerR3);
2410 apic->pTimerRC = TMTimerRCPtr(apic->pTimerR3);
2411 TMR3TimerSetCritSect(apic->pTimerR3, pThis->pCritSectR3);
2412 apic++;
2413 }
2414
2415 /*
2416 * Saved state.
2417 */
2418 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
2419 sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
2420 if (RT_FAILURE(rc))
2421 return rc;
2422
2423#ifdef VBOX_WITH_STATISTICS
2424 /*
2425 * Statistics.
2426 */
2427 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2428 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2429 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2430 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2431 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq, STAMTYPE_COUNTER, "/PDM/APIC/Masked/ActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2432#endif
2433
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/**
2439 * APIC device registration structure.
2440 */
2441const PDMDEVREG g_DeviceAPIC =
2442{
2443 /* u32Version */
2444 PDM_DEVREG_VERSION,
2445 /* szDeviceName */
2446 "apic",
2447 /* szRCMod */
2448 "VBoxDD2GC.gc",
2449 /* szR0Mod */
2450 "VBoxDD2R0.r0",
2451 /* pszDescription */
2452 "Advanced Programmable Interrupt Controller (APIC) Device",
2453 /* fFlags */
2454 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2455 /* fClass */
2456 PDM_DEVREG_CLASS_PIC,
2457 /* cMaxInstances */
2458 1,
2459 /* cbInstance */
2460 sizeof(APICState),
2461 /* pfnConstruct */
2462 apicConstruct,
2463 /* pfnDestruct */
2464 NULL,
2465 /* pfnRelocate */
2466 apicRelocate,
2467 /* pfnIOCtl */
2468 NULL,
2469 /* pfnPowerOn */
2470 NULL,
2471 /* pfnReset */
2472 apicReset,
2473 /* pfnSuspend */
2474 NULL,
2475 /* pfnResume */
2476 NULL,
2477 /* pfnAttach */
2478 NULL,
2479 /* pfnDetach */
2480 NULL,
2481 /* pfnQueryInterface. */
2482 NULL,
2483 /* pfnInitComplete */
2484 NULL,
2485 /* pfnPowerOff */
2486 NULL,
2487 /* pfnSoftReset */
2488 NULL,
2489 /* u32VersionEnd */
2490 PDM_DEVREG_VERSION
2491};
2492
2493#endif /* IN_RING3 */
2494
2495
2496/* IOAPIC */
2497
2498PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2499{
2500 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2501 IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2502
2503 STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2504 switch (cb)
2505 {
2506 case 1:
2507 *(uint8_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2508 break;
2509
2510 case 2:
2511 *(uint16_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2512 break;
2513
2514 case 4:
2515 *(uint32_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2516 break;
2517
2518 default:
2519 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2520 IOAPIC_UNLOCK(s);
2521 return VERR_INTERNAL_ERROR;
2522 }
2523 IOAPIC_UNLOCK(s);
2524 return VINF_SUCCESS;
2525}
2526
2527PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2528{
2529 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2530
2531 STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2532 switch (cb)
2533 {
2534 case 1:
2535 case 2:
2536 case 4:
2537 IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2538 ioapic_mem_writel(s, GCPhysAddr, *(uint32_t *)pv);
2539 IOAPIC_UNLOCK(s);
2540 break;
2541
2542 default:
2543 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2544 return VERR_INTERNAL_ERROR;
2545 }
2546 return VINF_SUCCESS;
2547}
2548
2549PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2550{
2551 IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *);
2552 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2553 LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2554 ioapic_set_irq(pThis, iIrq, iLevel);
2555}
2556
2557
2558#ifdef IN_RING3
2559
2560/**
2561 * @copydoc FNSSMDEVSAVEEXEC
2562 */
2563static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2564{
2565 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2566 ioapic_save(pSSMHandle, s);
2567 return VINF_SUCCESS;
2568}
2569
2570/**
2571 * @copydoc FNSSMDEVLOADEXEC
2572 */
2573static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2574{
2575 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2576
2577 if (ioapic_load(pSSMHandle, s, u32Version)) {
2578 AssertFailed();
2579 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2580 }
2581
2582 return VINF_SUCCESS;
2583}
2584
2585/**
2586 * @copydoc FNPDMDEVRESET
2587 */
2588static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2589{
2590 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2591 s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2592 ioapic_reset(s);
2593 IOAPIC_UNLOCK(s);
2594}
2595
2596/**
2597 * @copydoc FNPDMDEVRELOCATE
2598 */
2599static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2600{
2601 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2602 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2603 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2604}
2605
2606/**
2607 * @copydoc FNPDMDEVCONSTRUCT
2608 */
2609static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2610{
2611 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2612 PDMIOAPICREG IoApicReg;
2613 bool fGCEnabled;
2614 bool fR0Enabled;
2615 int rc;
2616
2617 Assert(iInstance == 0);
2618
2619 /*
2620 * Validate and read the configuration.
2621 */
2622 if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2623 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2624
2625 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2626 if (RT_FAILURE(rc))
2627 return PDMDEV_SET_ERROR(pDevIns, rc,
2628 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2629
2630 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2631 if (RT_FAILURE(rc))
2632 return PDMDEV_SET_ERROR(pDevIns, rc,
2633 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2634 Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2635
2636 /*
2637 * Initialize the state data.
2638 */
2639 s->pDevInsR3 = pDevIns;
2640 s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2641 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2642 ioapic_reset(s);
2643 s->id = 0;
2644
2645 /*
2646 * Register the IOAPIC and get helpers.
2647 */
2648 IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2649 IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2650 IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2651 IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2652 rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2653 if (RT_FAILURE(rc))
2654 {
2655 AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2656 return rc;
2657 }
2658
2659 /*
2660 * Register MMIO callbacks and saved state.
2661 */
2662 rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2663 ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2664 if (RT_FAILURE(rc))
2665 return rc;
2666
2667 if (fGCEnabled) {
2668 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2669
2670 rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2671 "ioapicMMIOWrite", "ioapicMMIORead", NULL);
2672 if (RT_FAILURE(rc))
2673 return rc;
2674 }
2675
2676 if (fR0Enabled) {
2677 s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2678
2679 rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2680 "ioapicMMIOWrite", "ioapicMMIORead", NULL);
2681 if (RT_FAILURE(rc))
2682 return rc;
2683 }
2684
2685 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2686 sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2687 if (RT_FAILURE(rc))
2688 return rc;
2689
2690#ifdef VBOX_WITH_STATISTICS
2691 /*
2692 * Statistics.
2693 */
2694 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2695 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2696 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2697 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2698 PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2699 PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2700#endif
2701
2702 return VINF_SUCCESS;
2703}
2704
2705/**
2706 * IO APIC device registration structure.
2707 */
2708const PDMDEVREG g_DeviceIOAPIC =
2709{
2710 /* u32Version */
2711 PDM_DEVREG_VERSION,
2712 /* szDeviceName */
2713 "ioapic",
2714 /* szRCMod */
2715 "VBoxDD2GC.gc",
2716 /* szR0Mod */
2717 "VBoxDD2R0.r0",
2718 /* pszDescription */
2719 "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2720 /* fFlags */
2721 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2722 /* fClass */
2723 PDM_DEVREG_CLASS_PIC,
2724 /* cMaxInstances */
2725 1,
2726 /* cbInstance */
2727 sizeof(IOAPICState),
2728 /* pfnConstruct */
2729 ioapicConstruct,
2730 /* pfnDestruct */
2731 NULL,
2732 /* pfnRelocate */
2733 ioapicRelocate,
2734 /* pfnIOCtl */
2735 NULL,
2736 /* pfnPowerOn */
2737 NULL,
2738 /* pfnReset */
2739 ioapicReset,
2740 /* pfnSuspend */
2741 NULL,
2742 /* pfnResume */
2743 NULL,
2744 /* pfnAttach */
2745 NULL,
2746 /* pfnDetach */
2747 NULL,
2748 /* pfnQueryInterface. */
2749 NULL,
2750 /* pfnInitComplete */
2751 NULL,
2752 /* pfnPowerOff */
2753 NULL,
2754 /* pfnSoftReset */
2755 NULL,
2756 /* u32VersionEnd */
2757 PDM_DEVREG_VERSION
2758};
2759
2760#endif /* IN_RING3 */
2761#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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