DevAPIC.cpp@ 2685

Last change on this file since 2685 was 2640, checked in by vboxsync, 18 years ago
fixed typo
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File size: 59.0 KB

Line
1	#ifdef VBOX
2	/** @file
3	*
4	* VBox basic PC devices:
5	* Advanced Programmable Interrupt Controller (APIC) device
6	*/
7
8	/*
9	* Copyright (C) 2006 InnoTek Systemberatung GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License as published by the Free Software Foundation,
15	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
16	* distribution. VirtualBox OSE is distributed in the hope that it will
17	* be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* If you received this file as part of a commercial VirtualBox
20	* distribution, then only the terms of your commercial VirtualBox
21	* license agreement apply instead of the previous paragraph.
22	*
23	* --------------------------------------------------------------------
24	*
25	* This code is based on:
26	*
27	* apic.c revision 1.5 @@OSETODO
28	*/
29
30	/*******************************************************************************
31	* Header Files *
32	*******************************************************************************/
33	#define LOG_GROUP LOG_GROUP_DEV_APIC
34	#include <VBox/pdm.h>
35
36	#include <VBox/log.h>
37	#include <VBox/stam.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40
41	#include "Builtins2.h"
42	#include "vl_vbox.h"
43
44	#define MSR_IA32_APICBASE 0x1b
45	#define MSR_IA32_APICBASE_BSP (1<<8)
46	#define MSR_IA32_APICBASE_ENABLE (1<<11)
47	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
48
49	#ifndef EINVAL
50	# define EINVAL 1
51	#endif
52
53	#ifdef _MSC_VER
54	# pragma warning(disable:4244)
55	#endif
56
57	/** @def APIC_LOCK
58	* Acquires the PDM lock. This is a NOP if locking is disabled. */
59	/** @def APIC_UNLOCK
60	* Releases the PDM lock. This is a NOP if locking is disabled. */
61	/** @def IOAPIC_LOCK
62	* Acquires the PDM lock. This is a NOP if locking is disabled. */
63	/** @def IOAPIC_UNLOCK
64	* Releases the PDM lock. This is a NOP if locking is disabled. */
65	#ifdef VBOX_WITH_PDM_LOCK
66	# define APIC_LOCK(pThis, rc) \
67	do { \
68	int rc2 = (pThis)->CTXALLSUFF(pApicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
69	if (rc2 != VINF_SUCCESS) \
70	return rc2; \
71	} while (0)
72	# define APIC_UNLOCK(pThis) \
73	(pThis)->CTXALLSUFF(pApicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
74	# define IOAPIC_LOCK(pThis, rc) \
75	do { \
76	int rc2 = (pThis)->CTXALLSUFF(pIoApicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
77	if (rc2 != VINF_SUCCESS) \
78	return rc2; \
79	} while (0)
80	# define IOAPIC_UNLOCK(pThis) (pThis)->CTXALLSUFF(pIoApicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
81	#else /* !VBOX_WITH_PDM_LOCK */
82	# define APIC_LOCK(pThis, rc) do { } while (0)
83	# define APIC_UNLOCK(pThis) do { } while (0)
84	# define IOAPIC_LOCK(pThis, rc) do { } while (0)
85	# define IOAPIC_UNLOCK(pThis) do { } while (0)
86	#endif /* !VBOX_WITH_PDM_LOCK */
87
88
89	#endif /* VBOX */
90
91	/*
92	* APIC support
93	*
94	* Copyright (c) 2004-2005 Fabrice Bellard
95	*
96	* This library is free software; you can redistribute it and/or
97	* modify it under the terms of the GNU Lesser General Public
98	* License as published by the Free Software Foundation; either
99	* version 2 of the License, or (at your option) any later version.
100	*
101	* This library is distributed in the hope that it will be useful,
102	* but WITHOUT ANY WARRANTY; without even the implied warranty of
103	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
104	* Lesser General Public License for more details.
105	*
106	* You should have received a copy of the GNU Lesser General Public
107	* License along with this library; if not, write to the Free Software
108	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
109	*/
110	#ifndef VBOX
111	#include "vl.h"
112	#endif
113
114	#define DEBUG_APIC
115	#define DEBUG_IOAPIC
116
117	/* APIC Local Vector Table */
118	#define APIC_LVT_TIMER 0
119	#define APIC_LVT_THERMAL 1
120	#define APIC_LVT_PERFORM 2
121	#define APIC_LVT_LINT0 3
122	#define APIC_LVT_LINT1 4
123	#define APIC_LVT_ERROR 5
124	#define APIC_LVT_NB 6
125
126	/* APIC delivery modes */
127	#define APIC_DM_FIXED 0
128	#define APIC_DM_LOWPRI 1
129	#define APIC_DM_SMI 2
130	#define APIC_DM_NMI 4
131	#define APIC_DM_INIT 5
132	#define APIC_DM_SIPI 6
133	#define APIC_DM_EXTINT 7
134
135	/* APIC destination mode */
136	#define APIC_DESTMODE_FLAT 0xf
137	#define APIC_DESTMODE_CLUSTER 1
138
139	#define APIC_TRIGGER_EDGE 0
140	#define APIC_TRIGGER_LEVEL 1
141
142	#define APIC_LVT_TIMER_PERIODIC (1<<17)
143	#define APIC_LVT_MASKED (1<<16)
144	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
145	#define APIC_LVT_REMOTE_IRR (1<<14)
146	#define APIC_INPUT_POLARITY (1<<13)
147	#define APIC_SEND_PENDING (1<<12)
148
149	#define IOAPIC_NUM_PINS 0x18
150
151	#define ESR_ILLEGAL_ADDRESS (1 << 7)
152
153	#define APIC_SV_ENABLE (1 << 8)
154
155	#ifdef VBOX
156	#define APIC_MAX_PATCH_ATTEMPTS 100
157	#endif
158
159	typedef struct APICState {
160	#ifndef VBOX
161	CPUState *cpu_env;
162	#endif /* !VBOX */
163	uint32_t apicbase;
164	uint8_t id;
165	uint8_t arb_id;
166	#ifdef VBOX
167	uint32_t tpr;
168	#else
169	uint8_t tpr;
170	#endif
171	uint32_t spurious_vec;
172	uint8_t log_dest;
173	uint8_t dest_mode;
174	uint32_t isr[8]; /* in service register */
175	uint32_t tmr[8]; /* trigger mode register */
176	uint32_t irr[8]; /* interrupt request register */
177	uint32_t lvt[APIC_LVT_NB];
178	uint32_t esr; /* error register */
179	uint32_t icr[2];
180
181	uint32_t divide_conf;
182	int count_shift;
183	uint32_t initial_count;
184	#ifdef VBOX
185	uint32_t Alignment0;
186	#endif
187	int64_t initial_count_load_time, next_time;
188	#ifndef VBOX
189	QEMUTimer *timer;
190
191	struct APICState *next_apic;
192	#else /* VBOX */
193	/** HC pointer to the device instance. */
194	PPDMDEVINSHC pDevInsHC;
195	/** Pointer to the APIC HC helpers. */
196	PCPDMAPICHLPR3 pApicHlpR3;
197	/** The APIC timer - HC Ptr. */
198	PTMTIMERHC pTimerHC;
199	/** Pointer to the APIC R0 helpers. */
200	PCPDMAPICHLPR0 pApicHlpR0;
201
202	/** GC pointer to the device instance. */
203	PPDMDEVINSGC pDevInsGC;
204	/** Pointer to the APIC GC helpers. */
205	PCPDMAPICHLPGC pApicHlpGC;
206	/** The APIC timer - GC Ptr. */
207	PTMTIMERGC pTimerGC;
208
209	/** Number of attempts made to optimize TPR accesses. */
210	uint32_t ulTPRPatchAttempts;
211
212	# ifdef VBOX_WITH_STATISTICS
213	STAMCOUNTER StatMMIOReadGC;
214	STAMCOUNTER StatMMIOReadHC;
215	STAMCOUNTER StatMMIOWriteGC;
216	STAMCOUNTER StatMMIOWriteHC;
217	# endif
218	#endif /* VBOX */
219	} APICState;
220
221	struct IOAPICState {
222	uint8_t id;
223	uint8_t ioregsel;
224
225	uint32_t irr;
226	uint64_t ioredtbl[IOAPIC_NUM_PINS];
227
228	#ifdef VBOX
229	/** HC pointer to the device instance. */
230	PPDMDEVINSHC pDevInsHC;
231	/** Pointer to the IOAPIC R3 helpers. */
232	PCPDMIOAPICHLPR3 pIoApicHlpR3;
233
234	/** GC pointer to the device instance. */
235	PPDMDEVINSGC pDevInsGC;
236	/** Pointer to the IOAPIC GC helpers. */
237	PCPDMIOAPICHLPGC pIoApicHlpGC;
238
239	/** Pointer to the IOAPIC R0 helpers. */
240	PCPDMIOAPICHLPR0 pIoApicHlpR0;
241	# if HC_ARCH_BITS == 32
242	uint32_t Alignment0;
243	# endif
244	# ifdef VBOX_WITH_STATISTICS
245	STAMCOUNTER StatMMIOReadGC;
246	STAMCOUNTER StatMMIOReadHC;
247	STAMCOUNTER StatMMIOWriteGC;
248	STAMCOUNTER StatMMIOWriteHC;
249	STAMCOUNTER StatSetIrqGC;
250	STAMCOUNTER StatSetIrqHC;
251	# endif
252	#endif /* VBOX */
253	};
254
255	#ifdef VBOX
256	typedef struct IOAPICState IOAPICState;
257	#endif /* VBOX */
258
259	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
260	#ifndef VBOX
261	static int apic_io_memory;
262	static APICState *first_local_apic = NULL;
263	static int last_apic_id = 0;
264	#endif /* !VBOX */
265
266	static void apic_init_ipi(APICState *s);
267	static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
268	static void apic_update_irq(APICState *s);
269
270	#ifdef VBOX
271	static uint32_t apic_get_delivery_bitmask(APICState *s, uint8_t dest, uint8_t dest_mode);
272	__BEGIN_DECLS
273	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
274	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
275	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
276	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
277	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
278	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val);
279	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns);
280	PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
281	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
282	uint8_t u8TriggerMode);
283	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
284	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
285	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
286	__END_DECLS
287	#endif /* VBOX */
288
289	#ifndef VBOX
290	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
291	uint8_t vector_num, uint8_t polarity,
292	uint8_t trigger_mode)
293	{
294	APICState *apic_iter;
295	#else /* VBOX */
296	static void apic_bus_deliver(APICState *s, uint32_t deliver_bitmask, uint8_t delivery_mode,
297	uint8_t vector_num, uint8_t polarity,
298	uint8_t trigger_mode)
299	{
300	#endif /* VBOX */
301
302	switch (delivery_mode) {
303	case APIC_DM_LOWPRI:
304	case APIC_DM_FIXED:
305	/* XXX: arbitration */
306	break;
307
308	case APIC_DM_SMI:
309	case APIC_DM_NMI:
310	break;
311
312	case APIC_DM_INIT:
313	/* normal INIT IPI sent to processors */
314	#ifdef VBOX
315	apic_init_ipi (s);
316	#else
317	for (apic_iter = first_local_apic; apic_iter != NULL;
318	apic_iter = apic_iter->next_apic) {
319	apic_init_ipi(apic_iter);
320	}
321	#endif
322	return;
323
324	case APIC_DM_EXTINT:
325	/* handled in I/O APIC code */
326	break;
327
328	default:
329	return;
330	}
331
332	#ifdef VBOX
333	if (deliver_bitmask & (1 << s->id))
334	apic_set_irq (s, vector_num, trigger_mode);
335	#else /* VBOX */
336	for (apic_iter = first_local_apic; apic_iter != NULL;
337	apic_iter = apic_iter->next_apic) {
338	if (deliver_bitmask & (1 << apic_iter->id))
339	apic_set_irq(apic_iter, vector_num, trigger_mode);
340	}
341	#endif /* VBOX */
342	}
343
344	#ifndef VBOX
345	void cpu_set_apic_base(CPUState *env, uint64_t val)
346	{
347	APICState *s = env->apic_state;
348	#ifdef DEBUG_APIC
349	Log(("cpu_set_apic_base: %016llx\n", val));
350	#endif
351
352	s->apicbase = (val & 0xfffff000) \|
353	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
354	/* if disabled, cannot be enabled again */
355	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
356	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
357	env->cpuid_features &= ~CPUID_APIC;
358	s->spurious_vec &= ~APIC_SV_ENABLE;
359	}
360	}
361	#else /* VBOX */
362	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
363	{
364	APICState s = PDMINS2DATA(pDevIns, APICState );
365	Log(("cpu_set_apic_base: %016RX64\n", val));
366
367	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
368	s->apicbase = (val & 0xfffff000) \|
369	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
370	/* if disabled, cannot be enabled again (until reset) */
371	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
372	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
373	s->spurious_vec &= ~APIC_SV_ENABLE;
374
375	/* Clear any pending APIC interrupt action flag. */
376	s->CTXALLSUFF(pApicHlp)->pfnClearInterruptFF(s->CTXSUFF(pDevIns));
377	s->CTXALLSUFF(pApicHlp)->pfnChangeFeature(pDevIns, false);
378	}
379	}
380	#endif /* VBOX */
381	#ifndef VBOX
382
383	uint64_t cpu_get_apic_base(CPUState *env)
384	{
385	APICState *s = env->apic_state;
386	#ifdef DEBUG_APIC
387	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
388	#endif
389	return s->apicbase;
390	}
391
392	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
393	{
394	APICState *s = env->apic_state;
395	s->tpr = (val & 0x0f) << 4;
396	apic_update_irq(s);
397	}
398
399	uint8_t cpu_get_apic_tpr(CPUX86State *env)
400	{
401	APICState *s = env->apic_state;
402	return s->tpr >> 4;
403	}
404
405	static int fls_bit(int value)
406	{
407	unsigned int ret = 0;
408
409	#ifdef HOST_I386
410	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
411	return ret;
412	#else
413	if (value > 0xffff)
414	value >>= 16, ret = 16;
415	if (value > 0xff)
416	value >>= 8, ret += 8;
417	if (value > 0xf)
418	value >>= 4, ret += 4;
419	if (value > 0x3)
420	value >>= 2, ret += 2;
421	return ret + (value >> 1);
422	#endif
423	}
424
425	static inline void set_bit(uint32_t *tab, int index)
426	{
427	int i, mask;
428	i = index >> 5;
429	mask = 1 << (index & 0x1f);
430	tab[i] \|= mask;
431	}
432
433	static inline void reset_bit(uint32_t *tab, int index)
434	{
435	int i, mask;
436	i = index >> 5;
437	mask = 1 << (index & 0x1f);
438	tab[i] &= ~mask;
439	}
440
441
442	#else /* VBOX */
443
444	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
445	{
446	APICState s = PDMINS2DATA(pDevIns, APICState );
447	Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
448	return s->apicbase;
449	}
450
451	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
452	{
453	APICState s = PDMINS2DATA(pDevIns, APICState );
454	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
455	s->tpr = (val & 0x0f) << 4;
456	apic_update_irq(s);
457	}
458
459	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
460	{
461	APICState s = PDMINS2DATA(pDevIns, APICState );
462	LogFlow(("apicGetTPR: returns %#x\n", s->tpr >> 4));
463	return s->tpr >> 4;
464	}
465
466	/**
467	* More or less private interface between IOAPIC, only PDM is responsible
468	* for connecting the two devices.
469	*/
470	PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
471	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
472	uint8_t u8TriggerMode)
473	{
474	APICState s = PDMINS2DATA(pDevIns, APICState );
475	LogFlow(("apicBusDeliverCallback: s=%p pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
476	s, pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
477	apic_bus_deliver(s, apic_get_delivery_bitmask(s, u8Dest, u8DestMode),
478	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
479	}
480
481	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
482	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
483	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
484
485	#endif /* VBOX */
486
487	/* return -1 if no bit is set */
488	static int get_highest_priority_int(uint32_t *tab)
489	{
490	int i;
491	for(i = 7; i >= 0; i--) {
492	if (tab[i] != 0) {
493	return i * 32 + fls_bit(tab[i]);
494	}
495	}
496	return -1;
497	}
498
499	static int apic_get_ppr(APICState *s)
500	{
501	int tpr, isrv, ppr;
502
503	tpr = (s->tpr >> 4);
504	isrv = get_highest_priority_int(s->isr);
505	if (isrv < 0)
506	isrv = 0;
507	isrv >>= 4;
508	if (tpr >= isrv)
509	ppr = s->tpr;
510	else
511	ppr = isrv << 4;
512	return ppr;
513	}
514
515	static int apic_get_arb_pri(APICState *s)
516	{
517	/* XXX: arbitration */
518	return 0;
519	}
520
521	/* signal the CPU if an irq is pending */
522	static void apic_update_irq(APICState *s)
523	{
524	int irrv, ppr;
525	if (!(s->spurious_vec & APIC_SV_ENABLE))
526	#ifdef VBOX
527	{
528	/* Clear any pending APIC interrupt action flag. */
529	s->CTXALLSUFF(pApicHlp)->pfnClearInterruptFF(s->CTXSUFF(pDevIns));
530	return;
531	}
532	#else
533	return;
534	#endif /* VBOX */
535	irrv = get_highest_priority_int(s->irr);
536	if (irrv < 0)
537	return;
538	ppr = apic_get_ppr(s);
539	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
540	return;
541	#ifndef VBOX
542	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
543	#else
544	s->CTXALLSUFF(pApicHlp)->pfnSetInterruptFF(s->CTXSUFF(pDevIns));
545	#endif
546	}
547
548	static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
549	{
550	set_bit(s->irr, vector_num);
551	if (trigger_mode)
552	set_bit(s->tmr, vector_num);
553	else
554	reset_bit(s->tmr, vector_num);
555	apic_update_irq(s);
556	}
557
558	static void apic_eoi(APICState *s)
559	{
560	int isrv;
561	isrv = get_highest_priority_int(s->isr);
562	if (isrv < 0)
563	return;
564	reset_bit(s->isr, isrv);
565	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
566	set the remote IRR bit for level triggered interrupts. */
567	apic_update_irq(s);
568	}
569
570	#ifndef VBOX
571	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
572	#else /* VBOX */
573	static uint32_t apic_get_delivery_bitmask(APICState *s, uint8_t dest, uint8_t dest_mode)
574	#endif /* VBOX */
575	{
576	uint32_t mask = 0;
577	#ifndef VBOX
578	APICState *apic_iter;
579	#endif /* !VBOX */
580
581	if (dest_mode == 0) {
582	if (dest == 0xff)
583	mask = 0xff;
584	else
585	mask = 1 << dest;
586	} else {
587	/* XXX: cluster mode */
588	#ifdef VBOX
589	if (dest & s->log_dest)
590	mask \|= 1 << s->id;
591	#else /* !VBOX */
592	for (apic_iter = first_local_apic; apic_iter != NULL;
593	apic_iter = apic_iter->next_apic) {
594	if (dest & apic_iter->log_dest)
595	mask \|= (1 << apic_iter->id);
596	}
597	#endif /* !VBOX */
598	}
599
600	return mask;
601	}
602
603
604	static void apic_init_ipi(APICState *s)
605	{
606	int i;
607
608	for(i = 0; i < APIC_LVT_NB; i++)
609	s->lvt[i] = 1 << 16; /* mask LVT */
610	s->tpr = 0;
611	s->spurious_vec = 0xff;
612	s->log_dest = 0;
613	s->dest_mode = 0xff;
614	memset(s->isr, 0, sizeof(s->isr));
615	memset(s->tmr, 0, sizeof(s->tmr));
616	memset(s->irr, 0, sizeof(s->irr));
617	memset(s->lvt, 0, sizeof(s->lvt));
618	s->esr = 0;
619	memset(s->icr, 0, sizeof(s->icr));
620	s->divide_conf = 0;
621	s->count_shift = 0;
622	s->initial_count = 0;
623	s->initial_count_load_time = 0;
624	s->next_time = 0;
625	}
626
627	static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
628	uint8_t delivery_mode, uint8_t vector_num,
629	uint8_t polarity, uint8_t trigger_mode)
630	{
631	uint32_t deliver_bitmask = 0;
632	int dest_shorthand = (s->icr[0] >> 18) & 3;
633	#ifndef VBOX
634	APICState *apic_iter;
635	#endif /* !VBOX */
636
637	switch (delivery_mode) {
638	case APIC_DM_LOWPRI:
639	/* XXX: serch for focus processor, arbitration */
640	dest = s->id;
641
642	case APIC_DM_INIT:
643	{
644	int trig_mode = (s->icr[0] >> 15) & 1;
645	int level = (s->icr[0] >> 14) & 1;
646	if (level == 0 && trig_mode == 1) {
647	#ifdef VBOX
648	if (deliver_bitmask & (1 << s->id)) {
649	s->arb_id = s->id;
650	}
651	#else /* !VBOX */
652	for (apic_iter = first_local_apic; apic_iter != NULL;
653	apic_iter = apic_iter->next_apic) {
654	if (deliver_bitmask & (1 << apic_iter->id)) {
655	apic_iter->arb_id = apic_iter->id;
656	}
657	}
658	#endif /* !VBOX */
659	return;
660	}
661	}
662	break;
663
664	case APIC_DM_SIPI:
665	#ifndef VBOX
666	for (apic_iter = first_local_apic; apic_iter != NULL;
667	apic_iter = apic_iter->next_apic) {
668	if (deliver_bitmask & (1 << apic_iter->id)) {
669	/* XXX: SMP support */
670	/* apic_startup(apic_iter); */
671	}
672	}
673	#endif /* !VBOX */
674	return;
675	}
676
677	switch (dest_shorthand) {
678	case 0:
679	#ifndef VBOX
680	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
681	#else /* VBOX */
682	deliver_bitmask = apic_get_delivery_bitmask(s, dest, dest_mode);
683	#endif /* !VBOX */
684	break;
685	case 1:
686	deliver_bitmask = (1 << s->id);
687	break;
688	case 2:
689	deliver_bitmask = 0xffffffff;
690	break;
691	case 3:
692	deliver_bitmask = 0xffffffff & ~(1 << s->id);
693	break;
694	}
695
696	#ifndef VBOX
697	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
698	trigger_mode);
699	#else /* VBOX */
700	apic_bus_deliver(s, deliver_bitmask, delivery_mode, vector_num, polarity,
701	trigger_mode);
702	#endif /* VBOX */
703	}
704
705	#ifndef VBOX
706	int apic_get_interrupt(CPUState *env)
707	{
708	APICState *s = env->apic_state;
709	#else /* VBOX */
710	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
711	{
712	APICState s = PDMINS2DATA(pDevIns, APICState );
713	#endif /* VBOX */
714	int intno;
715
716	/* if the APIC is installed or enabled, we let the 8259 handle the
717	IRQs */
718	if (!s) {
719	Log(("apic_get_interrupt: returns -1 (!s)\n"));
720	return -1;
721	}
722	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
723	Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
724	return -1;
725	}
726
727	/* XXX: spurious IRQ handling */
728	intno = get_highest_priority_int(s->irr);
729	if (intno < 0) {
730	Log(("apic_get_interrupt: returns -1 (irr)\n"));
731	return -1;
732	}
733	reset_bit(s->irr, intno);
734	if (s->tpr && (uint32_t)intno <= s->tpr) {
735	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
736	return s->spurious_vec & 0xff;
737	}
738	set_bit(s->isr, intno);
739	apic_update_irq(s);
740	LogFlow(("apic_get_interrupt: returns %d\n", intno));
741	return intno;
742	}
743
744	static uint32_t apic_get_current_count(APICState *s)
745	{
746	int64_t d;
747	uint32_t val;
748	#ifndef VBOX
749	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
750	s->count_shift;
751	#else /* VBOX */
752	d = (TMTimerGet(s->CTXSUFF(pTimer)) - s->initial_count_load_time) >>
753	s->count_shift;
754	#endif /* VBOX */
755	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
756	/* periodic */
757	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
758	} else {
759	if (d >= s->initial_count)
760	val = 0;
761	else
762	val = s->initial_count - d;
763	}
764	return val;
765	}
766
767	static void apic_timer_update(APICState *s, int64_t current_time)
768	{
769	int64_t next_time, d;
770
771	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
772	d = (current_time - s->initial_count_load_time) >>
773	s->count_shift;
774	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
775	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
776	} else {
777	if (d >= s->initial_count)
778	goto no_timer;
779	d = (uint64_t)s->initial_count + 1;
780	}
781	next_time = s->initial_count_load_time + (d << s->count_shift);
782	#ifndef VBOX
783	qemu_mod_timer(s->timer, next_time);
784	#else
785	TMTimerSet(s->CTXSUFF(pTimer), next_time);
786	#endif
787	s->next_time = next_time;
788	} else {
789	no_timer:
790	#ifndef VBOX
791	qemu_del_timer(s->timer);
792	#else
793	TMTimerStop(s->CTXSUFF(pTimer));
794	#endif
795	}
796	}
797
798	#ifdef IN_RING3
799	#ifndef VBOX
800	static void apic_timer(void *opaque)
801	{
802	APICState *s = opaque;
803	#else /* VBOX */
804	static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
805	{
806	APICState s = PDMINS2DATA(pDevIns, APICState );
807	# ifdef VBOX_WITH_PDM_LOCK
808	s->pApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
809	# endif
810	#endif /* VBOX */
811
812	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
813	apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
814	}
815	apic_timer_update(s, s->next_time);
816
817	#ifdef VBOX
818	APIC_UNLOCK(s);
819	#endif
820	}
821	#endif /* IN_RING3 */
822
823	#ifndef VBOX
824	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
825	{
826	return 0;
827	}
828
829	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
830	{
831	return 0;
832	}
833
834	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
835	{
836	}
837
838	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
839	{
840	}
841	#endif /* !VBOX */
842
843
844	#ifndef VBOX
845	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
846	{
847	CPUState *env;
848	APICState *s;
849	#else /* VBOX */
850	static uint32_t apic_mem_readl(APICState *s, target_phys_addr_t addr)
851	{
852	#endif /* VBOX */
853	uint32_t val;
854	int index;
855
856	#ifndef VBOX
857	env = cpu_single_env;
858	if (!env)
859	return 0;
860	s = env->apic_state;
861	#endif /* !VBOX */
862
863	index = (addr >> 4) & 0xff;
864	switch(index) {
865	case 0x02: /* id */
866	val = s->id << 24;
867	break;
868	case 0x03: /* version */
869	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
870	break;
871	case 0x08:
872	val = s->tpr;
873	break;
874	case 0x09:
875	val = apic_get_arb_pri(s);
876	break;
877	case 0x0a:
878	/* ppr */
879	val = apic_get_ppr(s);
880	break;
881	#ifdef VBOX
882	case 0x0b:
883	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
884	val = 0;
885	break;
886	#endif
887
888	case 0x0d:
889	val = s->log_dest << 24;
890	break;
891	case 0x0e:
892	#ifdef VBOX
893	/* Bottom 28 bits are always 1 */
894	val = (s->dest_mode << 28) \| 0xfffffff;
895	#else
896	val = s->dest_mode << 28;
897	#endif
898	break;
899	case 0x0f:
900	val = s->spurious_vec;
901	break;
902	#ifndef VBOX
903	case 0x10 ... 0x17:
904	#else /* VBOX */
905	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
906	#endif /* VBOX */
907	val = s->isr[index & 7];
908	break;
909	#ifndef VBOX
910	case 0x18 ... 0x1f:
911	#else /* VBOX */
912	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
913	#endif /* VBOX */
914	val = s->tmr[index & 7];
915	break;
916	#ifndef VBOX
917	case 0x20 ... 0x27:
918	#else /* VBOX */
919	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
920	#endif /* VBOX */
921	val = s->irr[index & 7];
922	break;
923	case 0x28:
924	val = s->esr;
925	break;
926	case 0x30:
927	case 0x31:
928	val = s->icr[index & 1];
929	break;
930	#ifndef VBOX
931	case 0x32 ... 0x37:
932	#else /* VBOX */
933	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
934	#endif /* VBOX */
935	val = s->lvt[index - 0x32];
936	break;
937	case 0x38:
938	val = s->initial_count;
939	break;
940	case 0x39:
941	val = apic_get_current_count(s);
942	break;
943	case 0x3e:
944	val = s->divide_conf;
945	break;
946	default:
947	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
948	s->esr \|= ESR_ILLEGAL_ADDRESS;
949	val = 0;
950	break;
951	}
952	#ifdef DEBUG_APIC
953	Log(("APIC read: %08x = %08x\n", (uint32_t)addr, val));
954	#endif
955	return val;
956	}
957
958	#ifndef VBOX
959	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
960	{
961	CPUState *env;
962	APICState *s;
963	#else /* VBOX */
964	static int apic_mem_writel(APICState *s, target_phys_addr_t addr, uint32_t val)
965	{
966	#endif /* VBOX */
967	int index;
968
969	#ifndef VBOX
970	env = cpu_single_env;
971	if (!env)
972	return;
973	s = env->apic_state;
974	#endif /* !VBOX */
975
976	#ifdef DEBUG_APIC
977	Log(("APIC write: %08x = %08x\n", (uint32_t)addr, val));
978	#endif
979
980	index = (addr >> 4) & 0xff;
981	switch(index) {
982	case 0x02:
983	s->id = (val >> 24);
984	break;
985	case 0x03:
986	Log(("apic_mem_writel: write to version register; ignored\n"));
987	break;
988	case 0x08:
989	s->tpr = val;
990	apic_update_irq(s);
991	break;
992	case 0x09:
993	case 0x0a:
994	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
995	break;
996	case 0x0b: /* EOI */
997	apic_eoi(s);
998	break;
999	case 0x0d:
1000	s->log_dest = val >> 24;
1001	break;
1002	case 0x0e:
1003	s->dest_mode = val >> 28;
1004	break;
1005	case 0x0f:
1006	s->spurious_vec = val & 0x1ff;
1007	apic_update_irq(s);
1008	break;
1009	#ifndef VBOX
1010	case 0x10 ... 0x17:
1011	case 0x18 ... 0x1f:
1012	case 0x20 ... 0x27:
1013	case 0x28:
1014	#else
1015	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1016	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1017	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1018	case 0x28:
1019	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1020	#endif
1021	break;
1022
1023	case 0x30:
1024	s->icr[0] = val;
1025	apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
1026	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1027	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1028	break;
1029	case 0x31:
1030	s->icr[1] = val;
1031	break;
1032	#ifndef VBOX
1033	case 0x32 ... 0x37:
1034	#else /* VBOX */
1035	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1036	#endif /* VBOX */
1037	{
1038	int n = index - 0x32;
1039	s->lvt[n] = val;
1040	if (n == APIC_LVT_TIMER)
1041	#ifndef VBOX
1042	apic_timer_update(s, qemu_get_clock(vm_clock));
1043	#else /* VBOX */
1044	apic_timer_update(s, TMTimerGet(s->CTXSUFF(pTimer)));
1045	#endif /* VBOX*/
1046	}
1047	break;
1048	case 0x38:
1049	s->initial_count = val;
1050	#ifndef VBOX
1051	s->initial_count_load_time = qemu_get_clock(vm_clock);
1052	#else /* VBOX */
1053	s->initial_count_load_time = TMTimerGet(s->CTXSUFF(pTimer));
1054	#endif /* VBOX*/
1055	apic_timer_update(s, s->initial_count_load_time);
1056	break;
1057	case 0x39:
1058	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1059	break;
1060	case 0x3e:
1061	{
1062	int v;
1063	s->divide_conf = val & 0xb;
1064	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1065	s->count_shift = (v + 1) & 7;
1066	}
1067	break;
1068	default:
1069	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1070	s->esr \|= ESR_ILLEGAL_ADDRESS;
1071	break;
1072	}
1073	#ifdef VBOX
1074	return VINF_SUCCESS;
1075	#endif
1076	}
1077
1078	#ifdef IN_RING3
1079
1080	static void apic_save(QEMUFile f, void opaque)
1081	{
1082	APICState s = (APICState)opaque;
1083	int i;
1084
1085	qemu_put_be32s(f, &s->apicbase);
1086	qemu_put_8s(f, &s->id);
1087	qemu_put_8s(f, &s->arb_id);
1088	#ifdef VBOX
1089	qemu_put_be32s(f, &s->tpr);
1090	#else
1091	qemu_put_8s(f, &s->tpr);
1092	#endif
1093	qemu_put_be32s(f, &s->spurious_vec);
1094	qemu_put_8s(f, &s->log_dest);
1095	qemu_put_8s(f, &s->dest_mode);
1096	for (i = 0; i < 8; i++) {
1097	qemu_put_be32s(f, &s->isr[i]);
1098	qemu_put_be32s(f, &s->tmr[i]);
1099	qemu_put_be32s(f, &s->irr[i]);
1100	}
1101	for (i = 0; i < APIC_LVT_NB; i++) {
1102	qemu_put_be32s(f, &s->lvt[i]);
1103	}
1104	qemu_put_be32s(f, &s->esr);
1105	qemu_put_be32s(f, &s->icr[0]);
1106	qemu_put_be32s(f, &s->icr[1]);
1107	qemu_put_be32s(f, &s->divide_conf);
1108	qemu_put_be32s(f, &s->count_shift);
1109	qemu_put_be32s(f, &s->initial_count);
1110	qemu_put_be64s(f, &s->initial_count_load_time);
1111	qemu_put_be64s(f, &s->next_time);
1112	}
1113
1114	static int apic_load(QEMUFile f, void opaque, int version_id)
1115	{
1116	APICState s = (APICState)opaque;
1117	int i;
1118
1119	if (version_id != 1)
1120	return -EINVAL;
1121
1122	/* XXX: what if the base changes? (registered memory regions) */
1123	qemu_get_be32s(f, &s->apicbase);
1124	qemu_get_8s(f, &s->id);
1125	qemu_get_8s(f, &s->arb_id);
1126	#ifdef VBOX
1127	qemu_get_be32s(f, &s->tpr);
1128	#else
1129	qemu_get_8s(f, &s->tpr);
1130	#endif
1131	qemu_get_be32s(f, &s->spurious_vec);
1132	qemu_get_8s(f, &s->log_dest);
1133	qemu_get_8s(f, &s->dest_mode);
1134	for (i = 0; i < 8; i++) {
1135	qemu_get_be32s(f, &s->isr[i]);
1136	qemu_get_be32s(f, &s->tmr[i]);
1137	qemu_get_be32s(f, &s->irr[i]);
1138	}
1139	for (i = 0; i < APIC_LVT_NB; i++) {
1140	qemu_get_be32s(f, &s->lvt[i]);
1141	}
1142	qemu_get_be32s(f, &s->esr);
1143	qemu_get_be32s(f, &s->icr[0]);
1144	qemu_get_be32s(f, &s->icr[1]);
1145	qemu_get_be32s(f, &s->divide_conf);
1146	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1147	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1148	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1149	qemu_get_be64s(f, (uint64_t *)&s->next_time);
1150	return 0;
1151	}
1152
1153	static void apic_reset(void *opaque)
1154	{
1155	APICState s = (APICState)opaque;
1156	#ifdef VBOX
1157	TMTimerStop(s->CTXSUFF(pTimer));
1158
1159	/* malc, I've removed the initing duplicated in apic_init_ipi(). This
1160	* arb_id was left over.. */
1161	s->arb_id = 0;
1162
1163	/* Reset should re-enable the APIC. */
1164	s->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE;
1165	s->pApicHlpR3->pfnChangeFeature(s->pDevInsHC, true);
1166
1167	#endif /* VBOX */
1168	apic_init_ipi(s);
1169	}
1170
1171	#endif /* IN_RING3 */
1172
1173	#ifndef VBOX
1174	static CPUReadMemoryFunc *apic_mem_read[3] = {
1175	apic_mem_readb,
1176	apic_mem_readw,
1177	apic_mem_readl,
1178	};
1179
1180	static CPUWriteMemoryFunc *apic_mem_write[3] = {
1181	apic_mem_writeb,
1182	apic_mem_writew,
1183	apic_mem_writel,
1184	};
1185
1186	int apic_init(CPUState *env)
1187	{
1188	APICState *s;
1189
1190	s = qemu_mallocz(sizeof(APICState));
1191	if (!s)
1192	return -1;
1193	env->apic_state = s;
1194	apic_init_ipi(s);
1195	s->id = last_apic_id++;
1196	s->cpu_env = env;
1197	s->apicbase = 0xfee00000 \|
1198	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
1199
1200	/* XXX: mapping more APICs at the same memory location */
1201	if (apic_io_memory == 0) {
1202	/* NOTE: the APIC is directly connected to the CPU - it is not
1203	on the global memory bus. */
1204	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1205	apic_mem_write, NULL);
1206	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1207	apic_io_memory);
1208	}
1209	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1210
1211	register_savevm("apic", 0, 1, apic_save, apic_load, s);
1212	qemu_register_reset(apic_reset, s);
1213
1214	s->next_apic = first_local_apic;
1215	first_local_apic = s;
1216
1217	return 0;
1218	}
1219	#endif /* !VBOX */
1220
1221	static void ioapic_service(IOAPICState *s)
1222	{
1223	uint8_t i;
1224	uint8_t trig_mode;
1225	uint8_t vector;
1226	uint8_t delivery_mode;
1227	uint32_t mask;
1228	uint64_t entry;
1229	uint8_t dest;
1230	uint8_t dest_mode;
1231	uint8_t polarity;
1232
1233	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1234	mask = 1 << i;
1235	if (s->irr & mask) {
1236	entry = s->ioredtbl[i];
1237	if (!(entry & APIC_LVT_MASKED)) {
1238	trig_mode = ((entry >> 15) & 1);
1239	dest = entry >> 56;
1240	dest_mode = (entry >> 11) & 1;
1241	delivery_mode = (entry >> 8) & 7;
1242	polarity = (entry >> 13) & 1;
1243	if (trig_mode == APIC_TRIGGER_EDGE)
1244	s->irr &= ~mask;
1245	if (delivery_mode == APIC_DM_EXTINT)
1246	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1247	vector = pic_read_irq(isa_pic);
1248	#else /* VBOX */
1249	{
1250	AssertMsgFailed(("Delivery mode ExtINT"));
1251	vector = 0xff; /* incorrect but shuts up gcc. */
1252	}
1253	#endif /* VBOX */
1254	else
1255	vector = entry & 0xff;
1256
1257	#ifndef VBOX
1258	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1259	delivery_mode, vector, polarity, trig_mode);
1260	#else /* VBOX */
1261	s->CTXALLSUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTXSUFF(pDevIns),
1262	dest,
1263	dest_mode,
1264	delivery_mode,
1265	vector,
1266	polarity,
1267	trig_mode);
1268	#endif /* VBOX */
1269	}
1270	}
1271	}
1272	}
1273
1274	#ifdef VBOX
1275	static
1276	#endif
1277	void ioapic_set_irq(void *opaque, int vector, int level)
1278	{
1279	IOAPICState s = (IOAPICState)opaque;
1280
1281	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1282	uint32_t mask = 1 << vector;
1283	uint64_t entry = s->ioredtbl[vector];
1284
1285	if ((entry >> 15) & 1) {
1286	/* level triggered */
1287	if (level) {
1288	s->irr \|= mask;
1289	ioapic_service(s);
1290	#ifdef VBOX
1291	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1292	s->irr &= ~mask;
1293	}
1294	#endif
1295	} else {
1296	s->irr &= ~mask;
1297	}
1298	} else {
1299	/* edge triggered */
1300	if (level) {
1301	s->irr \|= mask;
1302	ioapic_service(s);
1303	}
1304	}
1305	}
1306	}
1307
1308	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1309	{
1310	IOAPICState s = (IOAPICState)opaque;
1311	int index;
1312	uint32_t val = 0;
1313
1314	addr &= 0xff;
1315	if (addr == 0x00) {
1316	val = s->ioregsel;
1317	} else if (addr == 0x10) {
1318	switch (s->ioregsel) {
1319	case 0x00:
1320	val = s->id << 24;
1321	break;
1322	case 0x01:
1323	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1324	break;
1325	case 0x02:
1326	val = 0;
1327	break;
1328	default:
1329	index = (s->ioregsel - 0x10) >> 1;
1330	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1331	if (s->ioregsel & 1)
1332	val = s->ioredtbl[index] >> 32;
1333	else
1334	val = s->ioredtbl[index] & 0xffffffff;
1335	}
1336	}
1337	#ifdef DEBUG_IOAPIC
1338	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1339	#endif
1340	}
1341	return val;
1342	}
1343
1344	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1345	{
1346	IOAPICState s = (IOAPICState)opaque;
1347	int index;
1348
1349	addr &= 0xff;
1350	if (addr == 0x00) {
1351	s->ioregsel = val;
1352	return;
1353	} else if (addr == 0x10) {
1354	#ifdef DEBUG_IOAPIC
1355	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1356	#endif
1357	switch (s->ioregsel) {
1358	case 0x00:
1359	s->id = (val >> 24) & 0xff;
1360	return;
1361	case 0x01:
1362	case 0x02:
1363	return;
1364	default:
1365	index = (s->ioregsel - 0x10) >> 1;
1366	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1367	if (s->ioregsel & 1) {
1368	s->ioredtbl[index] &= 0xffffffff;
1369	s->ioredtbl[index] \|= (uint64_t)val << 32;
1370	} else {
1371	s->ioredtbl[index] &= ~0xffffffffULL;
1372	s->ioredtbl[index] \|= val;
1373	}
1374	ioapic_service(s);
1375	}
1376	}
1377	}
1378	}
1379
1380	#ifdef IN_RING3
1381
1382	static void ioapic_save(QEMUFile f, void opaque)
1383	{
1384	IOAPICState s = (IOAPICState)opaque;
1385	int i;
1386
1387	qemu_put_8s(f, &s->id);
1388	qemu_put_8s(f, &s->ioregsel);
1389	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1390	qemu_put_be64s(f, &s->ioredtbl[i]);
1391	}
1392	}
1393
1394	static int ioapic_load(QEMUFile f, void opaque, int version_id)
1395	{
1396	IOAPICState s = (IOAPICState)opaque;
1397	int i;
1398
1399	if (version_id != 1)
1400	return -EINVAL;
1401
1402	qemu_get_8s(f, &s->id);
1403	qemu_get_8s(f, &s->ioregsel);
1404	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1405	qemu_get_be64s(f, &s->ioredtbl[i]);
1406	}
1407	return 0;
1408	}
1409
1410	static void ioapic_reset(void *opaque)
1411	{
1412	IOAPICState s = (IOAPICState)opaque;
1413	#ifdef VBOX
1414	PPDMDEVINSHC pDevIns = s->pDevInsHC;
1415	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1416	#endif
1417	int i;
1418
1419	memset(s, 0, sizeof(*s));
1420	for(i = 0; i < IOAPIC_NUM_PINS; i++)
1421	s->ioredtbl[i] = 1 << 16; /* mask LVT */
1422
1423	#ifdef VBOX
1424	if (pDevIns)
1425	{
1426	s->pDevInsHC = pDevIns;
1427	s->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1428	}
1429	if (pIoApicHlp)
1430	{
1431	s->pIoApicHlpR3 = pIoApicHlp;
1432	s->pIoApicHlpGC = s->pIoApicHlpR3->pfnGetGCHelpers(pDevIns);
1433	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1434	}
1435	#endif
1436	}
1437
1438	#endif /* IN_RING3 */
1439
1440	#ifndef VBOX
1441	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1442	ioapic_mem_readl,
1443	ioapic_mem_readl,
1444	ioapic_mem_readl,
1445	};
1446
1447	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1448	ioapic_mem_writel,
1449	ioapic_mem_writel,
1450	ioapic_mem_writel,
1451	};
1452
1453	IOAPICState *ioapic_init(void)
1454	{
1455	IOAPICState *s;
1456	int io_memory;
1457
1458	s = qemu_mallocz(sizeof(IOAPICState));
1459	if (!s)
1460	return NULL;
1461	ioapic_reset(s);
1462	s->id = last_apic_id++;
1463
1464	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1465	ioapic_mem_write, s);
1466	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1467
1468	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1469	qemu_register_reset(ioapic_reset, s);
1470
1471	return s;
1472	}
1473	#endif /* !VBOX */
1474
1475	/* LAPIC */
1476
1477	/* LAPICs MMIO is wrong, in SMP there is no relation between memory range and
1478	lapic, it's only the CPU that executes this memory access is what matters */
1479
1480	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1481	{
1482	APICState s = PDMINS2DATA(pDevIns, APICState );
1483
1484	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
1485	switch (cb)
1486	{
1487	case 1:
1488	(uint8_t )pv = 0;
1489	break;
1490
1491	case 2:
1492	(uint16_t )pv = 0;
1493	break;
1494
1495	case 4:
1496	{
1497	#if 0 /** @note experimental */
1498	#ifndef IN_RING3
1499	uint32_t index = (GCPhysAddr >> 4) & 0xff;
1500
1501	if ( index == 0x08 /* TPR */
1502	&& ++s->ulTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
1503	{
1504	#ifdef IN_GC
1505	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
1506	#else
1507	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
1508	pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
1509	#endif
1510	return VINF_PATM_HC_MMIO_PATCH_READ;
1511	}
1512	#endif
1513	#endif /* experimental */
1514	APIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
1515	(uint32_t )pv = apic_mem_readl(s, GCPhysAddr);
1516	APIC_UNLOCK(s);
1517	break;
1518	}
1519	default:
1520	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1521	return VERR_INTERNAL_ERROR;
1522	}
1523	return VINF_SUCCESS;
1524	}
1525
1526	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1527	{
1528	APICState s = PDMINS2DATA(pDevIns, APICState );
1529
1530	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
1531	switch (cb)
1532	{
1533	case 1:
1534	case 2:
1535	/* ignore */
1536	break;
1537
1538	case 4:
1539	{
1540	int rc;
1541	APIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
1542	rc = apic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
1543	APIC_UNLOCK(s);
1544	return rc;
1545	}
1546
1547	default:
1548	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1549	return VERR_INTERNAL_ERROR;
1550	}
1551	return VINF_SUCCESS;
1552	}
1553
1554	#ifdef IN_RING3
1555
1556	/**
1557	* @copydoc FNSSMDEVSAVEEXEC
1558	*/
1559	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1560	{
1561	APICState s = PDMINS2DATA(pDevIns, APICState );
1562	apic_save(pSSMHandle, s);
1563	return TMR3TimerSave(s->CTXSUFF(pTimer), pSSMHandle);
1564	}
1565
1566	/**
1567	* @copydoc FNSSMDEVLOADEXEC
1568	*/
1569	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
1570	{
1571	APICState s = PDMINS2DATA(pDevIns, APICState );
1572	if (apic_load(pSSMHandle, s, u32Version)) {
1573	AssertFailed();
1574	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1575	}
1576	return TMR3TimerLoad(s->CTXSUFF(pTimer), pSSMHandle);
1577	}
1578
1579	/**
1580	* @copydoc FNPDMDEVRESET
1581	*/
1582	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
1583	{
1584	APICState s = PDMINS2DATA(pDevIns, APICState );
1585	#ifdef VBOX_WITH_PDM_LOCK
1586	s->pApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
1587	#endif
1588	apic_reset(s);
1589	/* Clear any pending APIC interrupt action flag. */
1590	s->pApicHlpR3->pfnClearInterruptFF(pDevIns);
1591	APIC_UNLOCK(s);
1592	}
1593
1594	/**
1595	* @copydoc FNPDMDEVRELOCATE
1596	*/
1597	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1598	{
1599	APICState pData = PDMINS2DATA(pDevIns, APICState );
1600	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1601	pData->pApicHlpGC = pData->pApicHlpR3->pfnGetGCHelpers(pDevIns);
1602	pData->pTimerGC = TMTimerGCPtr(pData->CTXSUFF(pTimer));
1603	}
1604
1605	/**
1606	* @copydoc FNPDMDEVCONSTRUCT
1607	*/
1608	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1609	{
1610	APICState pData = PDMINS2DATA(pDevIns, APICState );
1611	PDMAPICREG ApicReg;
1612	int rc;
1613	int i;
1614	bool fIOAPIC;
1615	bool fGCEnabled;
1616	bool fR0Enabled;
1617	Assert(iInstance == 0);
1618
1619	/*
1620	* Validate configuration.
1621	*/
1622	if (!CFGMR3AreValuesValid(pCfgHandle, "IOAPIC\0GCEnabled\0R0Enabled\0"))
1623	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1624
1625	rc = CFGMR3QueryBool (pCfgHandle, "IOAPIC", &fIOAPIC);
1626	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1627	fIOAPIC = true;
1628	else if (VBOX_FAILURE (rc))
1629	return PDMDEV_SET_ERROR(pDevIns, rc,
1630	N_("Configuration error: Failed to read \"IOAPIC\"."));
1631
1632	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1633	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1634	fGCEnabled = true;
1635	else
1636	return PDMDEV_SET_ERROR(pDevIns, rc,
1637	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
1638	Log(("APIC: fGCEnabled=%d\n", fGCEnabled));
1639
1640	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1641	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1642	fR0Enabled = true;
1643	else
1644	return PDMDEV_SET_ERROR(pDevIns, rc,
1645	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
1646	Log(("APIC: fR0Enabled=%d\n", fR0Enabled));
1647
1648	/*
1649	* Init the data.
1650	*/
1651	pData->pDevInsHC = pDevIns;
1652	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1653	pData->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE;
1654	for (i = 0; i < APIC_LVT_NB; i++)
1655	pData->lvt[i] = 1 << 16; /* mask LVT */
1656	pData->spurious_vec = 0xff;
1657
1658	/*
1659	* Register the APIC.
1660	*/
1661	ApicReg.u32Version = PDM_APICREG_VERSION;
1662	ApicReg.pfnGetInterruptHC = apicGetInterrupt;
1663	ApicReg.pfnSetBaseHC = apicSetBase;
1664	ApicReg.pfnGetBaseHC = apicGetBase;
1665	ApicReg.pfnSetTPRHC = apicSetTPR;
1666	ApicReg.pfnGetTPRHC = apicGetTPR;
1667	ApicReg.pfnBusDeliverHC = apicBusDeliverCallback;
1668	if (fGCEnabled) {
1669	ApicReg.pszGetInterruptGC = "apicGetInterrupt";
1670	ApicReg.pszSetBaseGC = "apicSetBase";
1671	ApicReg.pszGetBaseGC = "apicGetBase";
1672	ApicReg.pszSetTPRGC = "apicSetTPR";
1673	ApicReg.pszGetTPRGC = "apicGetTPR";
1674	ApicReg.pszBusDeliverGC = "apicBusDeliverCallback";
1675	} else {
1676	ApicReg.pszGetInterruptGC = NULL;
1677	ApicReg.pszSetBaseGC = NULL;
1678	ApicReg.pszGetBaseGC = NULL;
1679	ApicReg.pszSetTPRGC = NULL;
1680	ApicReg.pszGetTPRGC = NULL;
1681	ApicReg.pszBusDeliverGC = NULL;
1682	}
1683	if (fR0Enabled) {
1684	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
1685	ApicReg.pszSetBaseR0 = "apicSetBase";
1686	ApicReg.pszGetBaseR0 = "apicGetBase";
1687	ApicReg.pszSetTPRR0 = "apicSetTPR";
1688	ApicReg.pszGetTPRR0 = "apicGetTPR";
1689	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
1690	} else {
1691	ApicReg.pszGetInterruptR0 = NULL;
1692	ApicReg.pszSetBaseR0 = NULL;
1693	ApicReg.pszGetBaseR0 = NULL;
1694	ApicReg.pszSetTPRR0 = NULL;
1695	ApicReg.pszGetTPRR0 = NULL;
1696	ApicReg.pszBusDeliverR0 = NULL;
1697	}
1698
1699	Assert(pDevIns->pDevHlp->pfnAPICRegister);
1700	rc = pDevIns->pDevHlp->pfnAPICRegister(pDevIns, &ApicReg, &pData->pApicHlpR3);
1701	if (VBOX_FAILURE(rc))
1702	{
1703	AssertMsgFailed(("APICRegister -> %Vrc\n", rc));
1704	return rc;
1705	}
1706	pData->pApicHlpGC = pData->pApicHlpR3->pfnGetGCHelpers(pDevIns);
1707
1708	/*
1709	* The the CPUID feature bit.
1710	*/
1711	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
1712	PDMDevHlpQueryCPUId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
1713	if (u32Eax >= 1)
1714	{
1715	if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
1716	\|\| u32Ebx == 0x756e6547 && u32Ecx == 0x6c65746e && u32Edx == 0x49656e69 /* GenuineIntel */
1717	\|\| u32Ebx == 0x68747541 && u32Ecx == 0x69746e65 && u32Edx == 0x444d4163 /* AuthenticAMD */)
1718	pData->pApicHlpR3->pfnChangeFeature(pDevIns, true);
1719	}
1720
1721	/*
1722	* Register the MMIO range.
1723	*/
1724	rc = PDMDevHlpMMIORegister(pDevIns, pData->apicbase & ~0xfff, 0x1000, pData,
1725	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
1726	if (VBOX_FAILURE(rc))
1727	return rc;
1728
1729	if (fGCEnabled) {
1730	rc = PDMDevHlpMMIORegisterGC(pDevIns, pData->apicbase & ~0xfff, 0x1000, 0,
1731	"apicMMIOWrite", "apicMMIORead", NULL, "APIC Memory");
1732	if (VBOX_FAILURE(rc))
1733	return rc;
1734	}
1735
1736	if (fR0Enabled) {
1737	pData->pApicHlpR0 = pData->pApicHlpR3->pfnGetR0Helpers(pDevIns);
1738
1739	rc = PDMDevHlpMMIORegisterR0(pDevIns, pData->apicbase & ~0xfff, 0x1000, 0,
1740	"apicMMIOWrite", "apicMMIORead", NULL, "APIC Memory");
1741	if (VBOX_FAILURE(rc))
1742	return rc;
1743	}
1744
1745	/*
1746	* Create the APIC timer.
1747	*/
1748	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer,
1749	"APIC Timer", &pData->CTXSUFF(pTimer));
1750	if (VBOX_FAILURE(rc))
1751	return rc;
1752	pData->pTimerGC = TMTimerGCPtr(pData->CTXSUFF(pTimer));
1753
1754	/*
1755	* Saved state.
1756	*/
1757	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
1758	sizeof(*pData), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
1759	if (VBOX_FAILURE(rc))
1760	return rc;
1761
1762	#ifdef VBOX_WITH_STATISTICS
1763	/*
1764	* Statistics.
1765	*/
1766	PDMDevHlpSTAMRegister(pDevIns, &pData->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
1767	PDMDevHlpSTAMRegister(pDevIns, &pData->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
1768	PDMDevHlpSTAMRegister(pDevIns, &pData->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
1769	PDMDevHlpSTAMRegister(pDevIns, &pData->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
1770	#endif
1771
1772	return VINF_SUCCESS;
1773	}
1774
1775
1776	/**
1777	* APIC device registration structure.
1778	*/
1779	const PDMDEVREG g_DeviceAPIC =
1780	{
1781	/* u32Version */
1782	PDM_DEVREG_VERSION,
1783	/* szDeviceName */
1784	"apic",
1785	/* szGCMod */
1786	"VBoxDD2GC.gc",
1787	/* szR0Mod */
1788	"VBoxDD2R0.r0",
1789	/* pszDescription */
1790	"Advanced Programmable Interrupt Controller",
1791	/* fFlags */
1792	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1793	/* fClass */
1794	PDM_DEVREG_CLASS_PIC,
1795	/* cMaxInstances */
1796	1,
1797	/* cbInstance */
1798	sizeof(APICState),
1799	/* pfnConstruct */
1800	apicConstruct,
1801	/* pfnDestruct */
1802	NULL,
1803	/* pfnRelocate */
1804	apicRelocate,
1805	/* pfnIOCtl */
1806	NULL,
1807	/* pfnPowerOn */
1808	NULL,
1809	/* pfnReset */
1810	apicReset,
1811	/* pfnSuspend */
1812	NULL,
1813	/* pfnResume */
1814	NULL,
1815	/* pfnAttach */
1816	NULL,
1817	/* pfnDetach */
1818	NULL,
1819	/* pfnQueryInterface. */
1820	NULL
1821	};
1822
1823	#endif /* IN_RING3 */
1824
1825
1826
1827
1828	/* IOAPIC */
1829
1830	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1831	{
1832	IOAPICState s = PDMINS2DATA(pDevIns, IOAPICState );
1833	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
1834
1835	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
1836	switch (cb)
1837	{
1838	case 1:
1839	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
1840	break;
1841
1842	case 2:
1843	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
1844	break;
1845
1846	case 4:
1847	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
1848	break;
1849
1850	default:
1851	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1852	IOAPIC_UNLOCK(s);
1853	return VERR_INTERNAL_ERROR;
1854	}
1855	IOAPIC_UNLOCK(s);
1856	return VINF_SUCCESS;
1857	}
1858
1859	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1860	{
1861	IOAPICState s = PDMINS2DATA(pDevIns, IOAPICState );
1862
1863	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
1864	switch (cb)
1865	{
1866	case 1:
1867	case 2:
1868	case 4:
1869	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
1870	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
1871	IOAPIC_UNLOCK(s);
1872	break;
1873
1874	default:
1875	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1876	return VERR_INTERNAL_ERROR;
1877	}
1878	return VINF_SUCCESS;
1879	}
1880
1881	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1882	{
1883	IOAPICState pThis = PDMINS2DATA(pDevIns, IOAPICState );
1884	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
1885	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
1886	ioapic_set_irq(pThis, iIrq, iLevel);
1887	}
1888
1889
1890	#ifdef IN_RING3
1891
1892	/**
1893	* @copydoc FNSSMDEVSAVEEXEC
1894	*/
1895	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1896	{
1897	IOAPICState s = PDMINS2DATA(pDevIns, IOAPICState );
1898	ioapic_save(pSSMHandle, s);
1899	return VINF_SUCCESS;
1900	}
1901
1902	/**
1903	* @copydoc FNSSMDEVLOADEXEC
1904	*/
1905	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
1906	{
1907	IOAPICState s = PDMINS2DATA(pDevIns, IOAPICState );
1908
1909	if (ioapic_load(pSSMHandle, s, u32Version)) {
1910	AssertFailed();
1911	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1912	}
1913
1914	return VINF_SUCCESS;
1915	}
1916
1917	/**
1918	* @copydoc FNPDMDEVRESET
1919	*/
1920	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
1921	{
1922	IOAPICState s = PDMINS2DATA(pDevIns, IOAPICState );
1923	#ifdef VBOX_WITH_PDM_LOCK
1924	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
1925	#endif
1926	ioapic_reset(s);
1927	IOAPIC_UNLOCK(s);
1928	}
1929
1930	/**
1931	* @copydoc FNPDMDEVRELOCATE
1932	*/
1933	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1934	{
1935	IOAPICState s = PDMINS2DATA(pDevIns, IOAPICState );
1936	s->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1937	s->pIoApicHlpGC = s->pIoApicHlpR3->pfnGetGCHelpers(pDevIns);
1938	}
1939
1940	/**
1941	* @copydoc FNPDMDEVCONSTRUCT
1942	*/
1943	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1944	{
1945	IOAPICState s = PDMINS2DATA(pDevIns, IOAPICState );
1946	PDMIOAPICREG IoApicReg;
1947	bool fGCEnabled;
1948	bool fR0Enabled;
1949	int rc;
1950
1951	Assert(iInstance == 0);
1952
1953	/*
1954	* Validate and read the configuration.
1955	*/
1956	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
1957	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1958
1959	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1960	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1961	fGCEnabled = true;
1962	else if (VBOX_FAILURE(rc))
1963	return PDMDEV_SET_ERROR(pDevIns, rc,
1964	N_("Configuration error: Failed to query boolean value \"GCEnabled\"!"));
1965	Log(("IOAPIC: fGCEnabled=%d\n", fGCEnabled));
1966
1967	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1968	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1969	fR0Enabled = true;
1970	else if (VBOX_FAILURE(rc))
1971	return PDMDEV_SET_ERROR(pDevIns, rc,
1972	N_("Configuration error: Failed to query boolean value \"R0Enabled\"!"));
1973	Log(("IOAPIC: fR0Enabled=%d\n", fR0Enabled));
1974
1975	/*
1976	* Initialize the state data.
1977	*/
1978	s->pDevInsHC = pDevIns;
1979	s->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
1980	ioapic_reset(s);
1981	s->id = 0;
1982
1983	/*
1984	* Register the IOAPIC and get helpers.
1985	*/
1986	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1987	IoApicReg.pfnSetIrqHC = ioapicSetIrq;
1988	IoApicReg.pszSetIrqGC = fGCEnabled ? "ioapicSetIrq" : NULL;
1989	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
1990	rc = pDevIns->pDevHlp->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
1991	if (VBOX_FAILURE(rc))
1992	{
1993	AssertMsgFailed(("IOAPICRegister -> %Vrc\n", rc));
1994	return rc;
1995	}
1996	s->pIoApicHlpGC = s->pIoApicHlpR3->pfnGetGCHelpers(pDevIns);
1997
1998	/*
1999	* Register MMIO callbacks and saved state.
2000	*/
2001	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2002	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2003	if (VBOX_FAILURE(rc))
2004	return rc;
2005
2006	if (fGCEnabled) {
2007	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2008	"ioapicMMIOWrite", "ioapicMMIORead", NULL, "I/O APIC Memory");
2009	if (VBOX_FAILURE(rc))
2010	return rc;
2011	}
2012
2013	if (fR0Enabled) {
2014	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2015
2016	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2017	"ioapicMMIOWrite", "ioapicMMIORead", NULL, "I/O APIC Memory");
2018	if (VBOX_FAILURE(rc))
2019	return rc;
2020	}
2021
2022	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2023	sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2024	if (VBOX_FAILURE(rc))
2025	return rc;
2026
2027	#ifdef VBOX_WITH_STATISTICS
2028	/*
2029	* Statistics.
2030	*/
2031	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2032	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2033	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2034	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2035	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2036	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2037	#endif
2038
2039	return VINF_SUCCESS;
2040	}
2041
2042	/**
2043	* IO APIC device registration structure.
2044	*/
2045	const PDMDEVREG g_DeviceIOAPIC =
2046	{
2047	/* u32Version */
2048	PDM_DEVREG_VERSION,
2049	/* szDeviceName */
2050	"ioapic",
2051	/* szGCMod */
2052	"VBoxDD2GC.gc",
2053	/* szR0Mod */
2054	"VBoxDD2R0.r0",
2055	/* pszDescription */
2056	"I/O Advanced Programmable Interrupt Controller",
2057	/* fFlags */
2058	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
2059	/* fClass */
2060	PDM_DEVREG_CLASS_PIC,
2061	/* cMaxInstances */
2062	1,
2063	/* cbInstance */
2064	sizeof(IOAPICState),
2065	/* pfnConstruct */
2066	ioapicConstruct,
2067	/* pfnDestruct */
2068	NULL,
2069	/* pfnRelocate */
2070	ioapicRelocate,
2071	/* pfnIOCtl */
2072	NULL,
2073	/* pfnPowerOn */
2074	NULL,
2075	/* pfnReset */
2076	ioapicReset,
2077	/* pfnSuspend */
2078	NULL,
2079	/* pfnResume */
2080	NULL,
2081	/* pfnAttach */
2082	NULL,
2083	/* pfnDetach */
2084	NULL,
2085	/* pfnQueryInterface. */
2086	NULL,
2087	/* pfnInitComplete */
2088	NULL,
2089	/* pfnPowerOff */
2090	NULL
2091	};
2092
2093	#endif /* IN_RING3 */
2094	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2095

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 2685

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