DevAPIC.cpp@ 28346

Last change on this file since 28346 was 27342, checked in by vboxsync, 15 years ago
Backed out r58772
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1	#ifdef VBOX
2	/* $Id: DevAPIC.cpp 27342 2010-03-12 19:41:11Z vboxsync $ */
3	/** @file
4	* Advanced Programmable Interrupt Controller (APIC) Device and
5	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* apic.c revision 1.5 @@OSETODO
27	*/
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/pdmdev.h>
34
35	#include <VBox/log.h>
36	#include <VBox/stam.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40	#include "Builtins2.h"
41	#include "vl_vbox.h"
42
43	#define MSR_IA32_APICBASE 0x1b
44	#define MSR_IA32_APICBASE_BSP (1<<8)
45	#define MSR_IA32_APICBASE_ENABLE (1<<11)
46	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
47	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
48
49	#ifndef EINVAL
50	# define EINVAL 1
51	#endif
52
53	#ifdef _MSC_VER
54	# pragma warning(disable:4244)
55	#endif
56
57	/** The current saved state version.*/
58	#define APIC_SAVED_STATE_VERSION 3
59	/** The saved state version used by VirtualBox v3 and earlier.
60	* This does not include the config. */
61	#define APIC_SAVED_STATE_VERSION_VBOX_30 2
62	/** Some ancient version... */
63	#define APIC_SAVED_STATE_VERSION_ANCIENT 1
64
65	/* version 0x14: Pentium 4, Xeon; LVT count depends on that */
66	#define APIC_HW_VERSION 0x14
67
68	/** @def APIC_LOCK
69	* Acquires the PDM lock. */
70	#define APIC_LOCK(pThis, rcBusy) \
71	do { \
72	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
73	if (rc2 != VINF_SUCCESS) \
74	return rc2; \
75	} while (0)
76
77	/** @def APIC_LOCK_VOID
78	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
79	#define APIC_LOCK_VOID(pThis, rcBusy) \
80	do { \
81	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
82	AssertLogRelRCReturnVoid(rc2); \
83	} while (0)
84
85	/** @def APIC_UNLOCK
86	* Releases the PDM lock. */
87	#define APIC_UNLOCK(pThis) \
88	PDMCritSectLeave((pThis)->CTX_SUFF(pCritSect))
89
90	/** @def IOAPIC_LOCK
91	* Acquires the PDM lock. */
92	#define IOAPIC_LOCK(pThis, rc) \
93	do { \
94	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
95	if (rc2 != VINF_SUCCESS) \
96	return rc2; \
97	} while (0)
98
99	/** @def IOAPIC_UNLOCK
100	* Releases the PDM lock. */
101	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
102
103
104	#define foreach_apic(dev, mask, code) \
105	do { \
106	uint32_t i; \
107	APICState *apic = (dev)->CTX_SUFF(paLapics); \
108	for (i = 0; i < (dev)->cCpus; i++) \
109	{ \
110	if (mask & (1 << (apic->id))) \
111	{ \
112	code; \
113	} \
114	apic++; \
115	} \
116	} while (0)
117
118	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
119	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
120	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
121	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
122
123	#endif /* VBOX */
124
125	/*
126	* APIC support
127	*
128	* Copyright (c) 2004-2005 Fabrice Bellard
129	*
130	* This library is free software; you can redistribute it and/or
131	* modify it under the terms of the GNU Lesser General Public
132	* License as published by the Free Software Foundation; either
133	* version 2 of the License, or (at your option) any later version.
134	*
135	* This library is distributed in the hope that it will be useful,
136	* but WITHOUT ANY WARRANTY; without even the implied warranty of
137	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
138	* Lesser General Public License for more details.
139	*
140	* You should have received a copy of the GNU Lesser General Public
141	* License along with this library; if not, write to the Free Software
142	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
143	*/
144	#ifndef VBOX
145	#include "vl.h"
146	#endif
147
148	#define DEBUG_APIC
149	#define DEBUG_IOAPIC
150
151	/* APIC Local Vector Table */
152	#define APIC_LVT_TIMER 0
153	#define APIC_LVT_THERMAL 1
154	#define APIC_LVT_PERFORM 2
155	#define APIC_LVT_LINT0 3
156	#define APIC_LVT_LINT1 4
157	#define APIC_LVT_ERROR 5
158	#define APIC_LVT_NB 6
159
160	/* APIC delivery modes */
161	#define APIC_DM_FIXED 0
162	#define APIC_DM_LOWPRI 1
163	#define APIC_DM_SMI 2
164	#define APIC_DM_NMI 4
165	#define APIC_DM_INIT 5
166	#define APIC_DM_SIPI 6
167	#define APIC_DM_EXTINT 7
168
169	/* APIC destination mode */
170	#define APIC_DESTMODE_FLAT 0xf
171	#define APIC_DESTMODE_CLUSTER 0x0
172
173	#define APIC_TRIGGER_EDGE 0
174	#define APIC_TRIGGER_LEVEL 1
175
176	#define APIC_LVT_TIMER_PERIODIC (1<<17)
177	#define APIC_LVT_MASKED (1<<16)
178	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
179	#define APIC_LVT_REMOTE_IRR (1<<14)
180	#define APIC_INPUT_POLARITY (1<<13)
181	#define APIC_SEND_PENDING (1<<12)
182
183	#define IOAPIC_NUM_PINS 0x18
184
185	#define ESR_ILLEGAL_ADDRESS (1 << 7)
186
187	#define APIC_SV_ENABLE (1 << 8)
188
189	#ifdef VBOX
190	#define APIC_MAX_PATCH_ATTEMPTS 100
191
192	typedef uint32_t PhysApicId;
193	typedef uint32_t LogApicId;
194	#endif
195
196	typedef struct APICState {
197	#ifndef VBOX
198	CPUState *cpu_env;
199	#endif /* !VBOX */
200	uint32_t apicbase;
201	#ifdef VBOX
202	/* Task priority register (interrupt level) */
203	uint32_t tpr;
204	/* Logical APIC id - user programmable */
205	LogApicId id;
206	/* Physical APIC id - not visible to user, constant */
207	PhysApicId phys_id;
208	/** @todo: is it logical or physical? Not really used anyway now. */
209	PhysApicId arb_id;
210	#else
211	uint8_t tpr;
212	uint8_t id;
213	uint8_t arb_id;
214	#endif
215	uint32_t spurious_vec;
216	uint8_t log_dest;
217	uint8_t dest_mode;
218	uint32_t isr[8]; /* in service register */
219	uint32_t tmr[8]; /* trigger mode register */
220	uint32_t irr[8]; /* interrupt request register */
221	uint32_t lvt[APIC_LVT_NB];
222	uint32_t esr; /* error register */
223	uint32_t icr[2];
224	uint32_t divide_conf;
225	int count_shift;
226	uint32_t initial_count;
227	#ifdef VBOX
228	uint32_t Alignment0;
229	#endif
230	#ifndef VBOX
231	int64_t initial_count_load_time, next_time;
232	QEMUTimer *timer;
233	struct APICState *next_apic;
234	#else
235	/** The time stamp of the initial_count load, i.e. when it was started. */
236	uint64_t initial_count_load_time;
237	/** The time stamp of the next timer callback. */
238	uint64_t next_time;
239	/** The APIC timer - R3 Ptr. */
240	PTMTIMERR3 pTimerR3;
241	/** The APIC timer - R0 Ptr. */
242	PTMTIMERR0 pTimerR0;
243	/** The APIC timer - RC Ptr. */
244	PTMTIMERRC pTimerRC;
245	/** Whether the timer is armed or not */
246	bool fTimerArmed;
247	/** Alignment */
248	bool afAlignment[3];
249	/** Timer description timer. */
250	R3PTRTYPE(char *) pszDesc;
251	# ifdef VBOX_WITH_STATISTICS
252	# if HC_ARCH_BITS == 32
253	uint32_t u32Alignment0;
254	# endif
255	STAMCOUNTER StatTimerSetInitialCount;
256	STAMCOUNTER StatTimerSetInitialCountArm;
257	STAMCOUNTER StatTimerSetInitialCountDisarm;
258	STAMCOUNTER StatTimerSetLvt;
259	STAMCOUNTER StatTimerSetLvtClearPeriodic;
260	STAMCOUNTER StatTimerSetLvtPostponed;
261	STAMCOUNTER StatTimerSetLvtArmed;
262	STAMCOUNTER StatTimerSetLvtArm;
263	STAMCOUNTER StatTimerSetLvtArmRetries;
264	STAMCOUNTER StatTimerSetLvtNoRelevantChange;
265	# endif
266	#endif /* VBOX */
267	} APICState;
268	#ifdef VBOX
269	AssertCompileMemberAlignment(APICState, initial_count_load_time, 8);
270	# ifdef VBOX_WITH_STATISTICS
271	AssertCompileMemberAlignment(APICState, StatTimerSetInitialCount, 8);
272	# endif
273	#endif
274
275	struct IOAPICState {
276	uint8_t id;
277	uint8_t ioregsel;
278
279	uint32_t irr;
280	uint64_t ioredtbl[IOAPIC_NUM_PINS];
281
282	#ifdef VBOX
283	/** The device instance - R3 Ptr. */
284	PPDMDEVINSR3 pDevInsR3;
285	/** The IOAPIC helpers - R3 Ptr. */
286	PCPDMIOAPICHLPR3 pIoApicHlpR3;
287
288	/** The device instance - R0 Ptr. */
289	PPDMDEVINSR0 pDevInsR0;
290	/** The IOAPIC helpers - R0 Ptr. */
291	PCPDMIOAPICHLPR0 pIoApicHlpR0;
292
293	/** The device instance - RC Ptr. */
294	PPDMDEVINSRC pDevInsRC;
295	/** The IOAPIC helpers - RC Ptr. */
296	PCPDMIOAPICHLPRC pIoApicHlpRC;
297
298	# ifdef VBOX_WITH_STATISTICS
299	STAMCOUNTER StatMMIOReadGC;
300	STAMCOUNTER StatMMIOReadHC;
301	STAMCOUNTER StatMMIOWriteGC;
302	STAMCOUNTER StatMMIOWriteHC;
303	STAMCOUNTER StatSetIrqGC;
304	STAMCOUNTER StatSetIrqHC;
305	# endif
306	#endif /* VBOX */
307	};
308
309	#ifdef VBOX
310	typedef struct IOAPICState IOAPICState;
311
312	typedef struct
313	{
314	/** The device instance - R3 Ptr. */
315	PPDMDEVINSR3 pDevInsR3;
316	/** The APIC helpers - R3 Ptr. */
317	PCPDMAPICHLPR3 pApicHlpR3;
318	/** LAPICs states - R3 Ptr */
319	R3PTRTYPE(APICState *) paLapicsR3;
320	/** The critical section - R3 Ptr. */
321	R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
322
323	/** The device instance - R0 Ptr. */
324	PPDMDEVINSR0 pDevInsR0;
325	/** The APIC helpers - R0 Ptr. */
326	PCPDMAPICHLPR0 pApicHlpR0;
327	/** LAPICs states - R0 Ptr */
328	R0PTRTYPE(APICState *) paLapicsR0;
329	/** The critical section - R3 Ptr. */
330	R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
331
332	/** The device instance - RC Ptr. */
333	PPDMDEVINSRC pDevInsRC;
334	/** The APIC helpers - RC Ptr. */
335	PCPDMAPICHLPRC pApicHlpRC;
336	/** LAPICs states - RC Ptr */
337	RCPTRTYPE(APICState *) paLapicsRC;
338	/** The critical section - R3 Ptr. */
339	RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
340
341	/** APIC specification version in this virtual hardware configuration. */
342	PDMAPICVERSION enmVersion;
343
344	/** Number of attempts made to optimize TPR accesses. */
345	uint32_t cTPRPatchAttempts;
346
347	/** Number of CPUs on the system (same as LAPIC count). */
348	uint32_t cCpus;
349	/** Whether we've got an IO APIC or not. */
350	bool fIoApic;
351	/** Alignment padding. */
352	bool afPadding[3];
353
354	# ifdef VBOX_WITH_STATISTICS
355	STAMCOUNTER StatMMIOReadGC;
356	STAMCOUNTER StatMMIOReadHC;
357	STAMCOUNTER StatMMIOWriteGC;
358	STAMCOUNTER StatMMIOWriteHC;
359	STAMCOUNTER StatClearedActiveIrq;
360	# endif
361	} APICDeviceInfo;
362	# ifdef VBOX_WITH_STATISTICS
363	AssertCompileMemberAlignment(APICDeviceInfo, StatMMIOReadGC, 8);
364	# endif
365	#endif /* VBOX */
366
367	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
368
369	#ifndef VBOX
370	static int apic_io_memory;
371	static APICState *first_local_apic = NULL;
372	static int last_apic_id = 0;
373	#endif /* !VBOX */
374
375
376	#ifdef VBOX
377	/*******************************************************************************
378	* Internal Functions *
379	*******************************************************************************/
380	RT_C_DECLS_BEGIN
381	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
382	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
383	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
384	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
385	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
386	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
387	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val);
388	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu);
389	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
390	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
391	uint8_t u8TriggerMode);
392	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level);
393	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
394	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
395	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
396	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
397	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
398
399	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
400	RT_C_DECLS_END
401
402	static void apic_eoi(APICDeviceInfo dev, APICState s); /* */
403	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
404	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
405	uint8_t dest, uint8_t dest_mode,
406	uint8_t delivery_mode, uint8_t vector_num,
407	uint8_t polarity, uint8_t trigger_mode);
408	static int apic_get_arb_pri(APICState *s);
409	static int apic_get_ppr(APICState *s);
410	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
411	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState s, uint32_t initial_count);
412	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew);
413	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s);
414
415	#endif /* VBOX */
416
417	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s);
418	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
419	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
420
421
422	#ifdef VBOX
423
424	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
425	{
426	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
427	return &dev->CTX_SUFF(paLapics)[id];
428	}
429
430	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
431	{
432	/* LAPIC's array is indexed by CPU id */
433	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
434	return getLapicById(dev, id);
435	}
436
437	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
438	{
439	/* for now we assume LAPIC physical id == CPU id */
440	return VMCPUID(s->phys_id);
441	}
442
443	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
444	{
445	LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(dev, s)));
446	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
447	getCpuFromLapic(dev, s));
448	}
449
450	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
451	{
452	LogFlow(("apic: clear interrupt flag\n"));
453	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
454	getCpuFromLapic(dev, s));
455	}
456
457	# ifdef IN_RING3
458
459	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
460	{
461	Log2(("apic: send SIPI vector=%d\n", vector));
462
463	dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
464	getCpuFromLapic(dev, s),
465	vector);
466	}
467
468	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* dev, APICState *s)
469	{
470	Log2(("apic: send init IPI\n"));
471
472	dev->pApicHlpR3->pfnSendInitIpi(dev->pDevInsR3,
473	getCpuFromLapic(dev, s));
474	}
475
476	# endif /* IN_RING3 */
477
478	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
479	{
480	switch (dev->enmVersion)
481	{
482	case PDMAPICVERSION_NONE:
483	return 0;
484	case PDMAPICVERSION_APIC:
485	return MSR_IA32_APICBASE_ENABLE;
486	case PDMAPICVERSION_X2APIC:
487	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
488	default:
489	AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
490	return 0;
491	}
492	}
493
494	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
495	{
496	switch (((apic->apicbase) >> 10) & 0x3)
497	{
498	case 0:
499	return PDMAPICVERSION_NONE;
500	case 1:
501	default:
502	/* Invalid */
503	return PDMAPICVERSION_NONE;
504	case 2:
505	return PDMAPICVERSION_APIC;
506	case 3:
507	return PDMAPICVERSION_X2APIC;
508	}
509	}
510
511	#endif /* VBOX */
512
513	#ifndef VBOX
514	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
515	uint8_t vector_num, uint8_t polarity,
516	uint8_t trigger_mode)
517	{
518	APICState *apic_iter;
519	#else /* VBOX */
520	static int apic_bus_deliver(APICDeviceInfo* dev,
521	uint32_t deliver_bitmask, uint8_t delivery_mode,
522	uint8_t vector_num, uint8_t polarity,
523	uint8_t trigger_mode)
524	{
525	#endif /* VBOX */
526
527	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
528	switch (delivery_mode) {
529	case APIC_DM_LOWPRI:
530	{
531	int d = -1;
532	if (deliver_bitmask)
533	d = ffs_bit(deliver_bitmask);
534	if (d >= 0)
535	{
536	APICState* apic = getLapicById(dev, d);
537	apic_set_irq(dev, apic, vector_num, trigger_mode);
538	}
539	return VINF_SUCCESS;
540	}
541	case APIC_DM_FIXED:
542	/* XXX: arbitration */
543	break;
544
545	case APIC_DM_SMI:
546	foreach_apic(dev, deliver_bitmask,
547	cpuSetInterrupt(dev, apic, PDMAPICIRQ_SMI));
548	return VINF_SUCCESS;
549
550	case APIC_DM_NMI:
551	foreach_apic(dev, deliver_bitmask,
552	cpuSetInterrupt(dev, apic, PDMAPICIRQ_NMI));
553	return VINF_SUCCESS;
554
555	case APIC_DM_INIT:
556	/* normal INIT IPI sent to processors */
557	#ifdef VBOX
558	#ifdef IN_RING3
559	foreach_apic(dev, deliver_bitmask,
560	apicSendInitIpi(dev, apic));
561	return VINF_SUCCESS;
562	#else
563	/* We shall send init IPI only in R3, R0 calls should be
564	rescheduled to R3 */
565	return VINF_IOM_HC_MMIO_READ_WRITE;
566	#endif /* IN_RING3 */
567
568	#else
569	for (apic_iter = first_local_apic; apic_iter != NULL;
570	apic_iter = apic_iter->next_apic) {
571	apic_init_ipi(apic_iter);
572	}
573	#endif
574
575	case APIC_DM_EXTINT:
576	/* handled in I/O APIC code */
577	break;
578
579	default:
580	return VINF_SUCCESS;
581	}
582
583	#ifdef VBOX
584	foreach_apic(dev, deliver_bitmask,
585	apic_set_irq (dev, apic, vector_num, trigger_mode));
586	return VINF_SUCCESS;
587	#else /* VBOX */
588	for (apic_iter = first_local_apic; apic_iter != NULL;
589	apic_iter = apic_iter->next_apic) {
590	if (deliver_bitmask & (1 << apic_iter->id))
591	apic_set_irq(apic_iter, vector_num, trigger_mode);
592	}
593	#endif /* VBOX */
594	}
595
596	#ifndef VBOX
597	void cpu_set_apic_base(CPUState *env, uint64_t val)
598	{
599	APICState *s = env->apic_state;
600	#ifdef DEBUG_APIC
601	Log(("cpu_set_apic_base: %016llx\n", val));
602	#endif
603
604	s->apicbase = (val & 0xfffff000) \|
605	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
606	/* if disabled, cannot be enabled again */
607	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
608	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
609	env->cpuid_features &= ~CPUID_APIC;
610	s->spurious_vec &= ~APIC_SV_ENABLE;
611	}
612	}
613	#else /* VBOX */
614	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
615	{
616	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
617	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
618	APICState s = getLapic(dev); /* @todo fix interface */
619	Log(("cpu_set_apic_base: %016RX64\n", val));
620
621	/** @todo: do we need to lock here ? */
622	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
623	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
624	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
625	PDMAPICVERSION oldMode = getApicMode(s);
626	s->apicbase =
627	(val & 0xfffff000) \| /* base */
628	(val & getApicEnableBits(dev)) \| /* mode */
629	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
630	PDMAPICVERSION newMode = getApicMode(s);
631
632	if (oldMode != newMode)
633	{
634	switch (newMode)
635	{
636	case PDMAPICVERSION_NONE:
637	{
638	s->spurious_vec &= ~APIC_SV_ENABLE;
639	/* Clear any pending APIC interrupt action flag. */
640	cpuClearInterrupt(dev, s);
641	/** @todo: why do we do that? */
642	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
643	break;
644	}
645	case PDMAPICVERSION_APIC:
646	/** @todo: map MMIO ranges, if needed */
647	break;
648	case PDMAPICVERSION_X2APIC:
649	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
650	break;
651	default:
652	break;
653	}
654	}
655	/* APIC_UNLOCK(dev); */
656	}
657	#endif /* VBOX */
658
659	#ifndef VBOX
660
661	uint64_t cpu_get_apic_base(CPUState *env)
662	{
663	APICState *s = env->apic_state;
664	#ifdef DEBUG_APIC
665	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
666	#endif
667	return s->apicbase;
668	}
669
670	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
671	{
672	APICState *s = env->apic_state;
673	s->tpr = (val & 0x0f) << 4;
674	apic_update_irq(s);
675	}
676
677	uint8_t cpu_get_apic_tpr(CPUX86State *env)
678	{
679	APICState *s = env->apic_state;
680	return s->tpr >> 4;
681	}
682
683	static int fls_bit(int value)
684	{
685	unsigned int ret = 0;
686
687	#ifdef HOST_I386
688	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
689	return ret;
690	#else
691	if (value > 0xffff)
692	value >>= 16, ret = 16;
693	if (value > 0xff)
694	value >>= 8, ret += 8;
695	if (value > 0xf)
696	value >>= 4, ret += 4;
697	if (value > 0x3)
698	value >>= 2, ret += 2;
699	return ret + (value >> 1);
700	#endif
701	}
702
703	static inline void set_bit(uint32_t *tab, int index)
704	{
705	int i, mask;
706	i = index >> 5;
707	mask = 1 << (index & 0x1f);
708	tab[i] \|= mask;
709	}
710
711	static inline void reset_bit(uint32_t *tab, int index)
712	{
713	int i, mask;
714	i = index >> 5;
715	mask = 1 << (index & 0x1f);
716	tab[i] &= ~mask;
717	}
718
719
720	#else /* VBOX */
721
722	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
723	{
724	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
725	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
726	APICState s = getLapic(dev); /* @todo fix interface */
727	LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
728	return s->apicbase;
729	}
730
731	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
732	{
733	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
734	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
735	APICState *s = getLapicById(dev, idCpu);
736	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, val));
737	apic_update_tpr(dev, s, val);
738	}
739
740	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
741	{
742	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
743	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
744	APICState *s = getLapicById(dev, idCpu);
745	Log2(("apicGetTPR: returns %#x\n", s->tpr));
746	return s->tpr;
747	}
748
749	/**
750	* x2APIC MSR write interface.
751	*
752	* @returns VBox status code.
753	*
754	* @param pDevIns The device instance.
755	* @param idCpu The ID of the virtual CPU and thereby APIC index.
756	* @param u32Reg Register to write (ecx).
757	* @param u64Value The value to write (eax:edx / rax).
758	*
759	*/
760	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
761	{
762	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
763	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
764	int rc = VINF_SUCCESS;
765
766	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
767	return VERR_EM_INTERPRETER;
768
769	APICState *pThis = getLapicById(dev, idCpu);
770
771	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
772	switch (index)
773	{
774	case 0x02:
775	pThis->id = (u64Value >> 24);
776	break;
777	case 0x03:
778	break;
779	case 0x08:
780	apic_update_tpr(dev, pThis, u64Value);
781	break;
782	case 0x09: case 0x0a:
783	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
784	break;
785	case 0x0b: /* EOI */
786	apic_eoi(dev, pThis);
787	break;
788	case 0x0d:
789	pThis->log_dest = u64Value >> 24;
790	break;
791	case 0x0e:
792	pThis->dest_mode = u64Value >> 28;
793	break;
794	case 0x0f:
795	pThis->spurious_vec = u64Value & 0x1ff;
796	apic_update_irq(dev, pThis);
797	break;
798	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
799	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
800	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
801	case 0x28:
802	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
803	break;
804
805	case 0x30:
806	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
807	pThis->icr[0] = (uint32_t)u64Value;
808	pThis->icr[1] = (uint32_t)(u64Value >> 32);
809	rc = apic_deliver(dev, pThis, (pThis->icr[1] >> 24) & 0xff, (pThis->icr[0] >> 11) & 1,
810	(pThis->icr[0] >> 8) & 7, (pThis->icr[0] & 0xff),
811	(pThis->icr[0] >> 14) & 1, (pThis->icr[0] >> 15) & 1);
812	break;
813	case 0x32 + APIC_LVT_TIMER:
814	AssertCompile(APIC_LVT_TIMER == 0);
815	apicTimerSetLvt(dev, pThis, u64Value);
816	break;
817
818	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
819	pThis->lvt[index - 0x32] = u64Value;
820	break;
821	case 0x38:
822	apicTimerSetInitialCount(dev, pThis, u64Value);
823	break;
824	case 0x39:
825	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
826	break;
827	case 0x3e:
828	{
829	int v;
830	pThis->divide_conf = u64Value & 0xb;
831	v = (pThis->divide_conf & 3) \| ((pThis->divide_conf >> 1) & 4);
832	pThis->count_shift = (v + 1) & 7;
833	break;
834	}
835	case 0x3f:
836	{
837	/* Self IPI, see x2APIC book 2.4.5 */
838	int vector = u64Value & 0xff;
839	rc = apic_bus_deliver(dev,
840	1 << getLapicById(dev, idCpu)->id /* Self */,
841	0 /* Delivery mode - fixed */,
842	vector,
843	0 /* Polarity - conform to the bus */,
844	0 /* Trigger mode - edge */);
845	break;
846	}
847	default:
848	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
849	pThis->esr \|= ESR_ILLEGAL_ADDRESS;
850	break;
851	}
852
853	return rc;
854	}
855
856	/**
857	* x2APIC MSR read interface.
858	*
859	* @returns VBox status code.
860	*
861	* @param pDevIns The device instance.
862	* @param idCpu The ID of the virtual CPU and thereby APIC index.
863	* @param u32Reg Register to write (ecx).
864	* @param pu64Value Where to return the value (eax:edx / rax).
865	*/
866	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
867	{
868	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
869	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
870
871	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
872	return VERR_EM_INTERPRETER;
873
874	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
875	APICState* apic = getLapicById(dev, idCpu);
876	uint64_t val = 0;
877
878	switch (index)
879	{
880	case 0x02: /* id */
881	val = apic->id << 24;
882	break;
883	case 0x03: /* version */
884	val = APIC_HW_VERSION \|
885	((APIC_LVT_NB - 1) << 16) /* Max LVT index */ \|
886	(0 << 24) /* Support for EOI broadcast supression */;
887	break;
888	case 0x08:
889	val = apic->tpr;
890	break;
891	case 0x09:
892	val = apic_get_arb_pri(apic);
893	break;
894	case 0x0a:
895	/* ppr */
896	val = apic_get_ppr(apic);
897	break;
898	case 0x0b:
899	val = 0;
900	break;
901	case 0x0d:
902	val = apic->log_dest << 24;
903	break;
904	case 0x0e:
905	/* Bottom 28 bits are always 1 */
906	val = (apic->dest_mode << 28) \| 0xfffffff;
907	break;
908	case 0x0f:
909	val = apic->spurious_vec;
910	break;
911	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
912	val = apic->isr[index & 7];
913	break;
914	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
915	val = apic->tmr[index & 7];
916	break;
917	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
918	val = apic->irr[index & 7];
919	break;
920	case 0x28:
921	val = apic->esr;
922	break;
923	case 0x30:
924	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
925	val = ((uint64_t)apic->icr[0x31] << 32) \| apic->icr[0x30];
926	break;
927	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
928	val = apic->lvt[index - 0x32];
929	break;
930	case 0x38:
931	val = apic->initial_count;
932	break;
933	case 0x39:
934	val = apic_get_current_count(dev, apic);
935	break;
936	case 0x3e:
937	val = apic->divide_conf;
938	break;
939	case 0x3f:
940	/* Self IPI register is write only */
941	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
942	break;
943	case 0x2f:
944	/**
945	* Correctable machine check exception vector, @todo: implement me!
946	*/
947	default:
948	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
949	/**
950	* @todo: according to spec when APIC writes to ESR it msut raise error interrupt,
951	* i.e. LVT[5]
952	*/
953	apic->esr \|= ESR_ILLEGAL_ADDRESS;
954	val = 0;
955	break;
956	}
957	*pu64Value = val;
958	return VINF_SUCCESS;
959	}
960
961	/**
962	* More or less private interface between IOAPIC, only PDM is responsible
963	* for connecting the two devices.
964	*/
965	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
966	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
967	uint8_t u8TriggerMode)
968	{
969	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
970	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
971	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
972	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
973	return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
974	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
975	}
976
977	/**
978	* Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
979	* Normally used for 8259A PIC and NMI.
980	*/
981	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
982	{
983	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
984	APICState *s = getLapicById(dev, 0);
985
986	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
987	LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x u8Level=%x\n", pDevIns, u8Pin, u8Level));
988
989	/* If LAPIC is disabled, go straight to the CPU. */
990	if (!(s->spurious_vec & APIC_SV_ENABLE))
991	{
992	LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
993	if (u8Level)
994	cpuSetInterrupt(dev, s, PDMAPICIRQ_EXTINT);
995	else
996	cpuClearInterrupt(dev, s, PDMAPICIRQ_EXTINT);
997
998	return VINF_SUCCESS;
999	}
1000
1001	/* If LAPIC is enabled, interrupts are subject to LVT programming. */
1002
1003	/* There are only two local interrupt pins. */
1004	AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
1005
1006	/* NB: We currently only deliver local interrupts to the first CPU. In theory they
1007	* should be delivered to all CPUs and it is the guest's responsibility to ensure
1008	* no more than one CPU has the interrupt unmasked.
1009	*/
1010	uint32_t u32Lvec;
1011
1012	u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin]; /* Fetch corresponding LVT entry. */
1013	/* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
1014	if (!(u32Lvec & APIC_LVT_MASKED))
1015	{ uint8_t u8Delivery;
1016	PDMAPICIRQ enmType;
1017
1018	u8Delivery = (u32Lvec >> 8) & 7;
1019	switch (u8Delivery)
1020	{
1021	case APIC_DM_EXTINT:
1022	Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
1023	enmType = PDMAPICIRQ_EXTINT;
1024	/* ExtINT can be both set and cleared, NMI/SMI/INIT can only be set. */
1025	LogFlow(("apicLocalInterrupt: %s ExtINT interrupt\n", u8Level ? "setting" : "clearing"));
1026	if (u8Level)
1027	cpuSetInterrupt(dev, s, enmType);
1028	else
1029	cpuClearInterrupt(dev, s, enmType);
1030	return VINF_SUCCESS;
1031	case APIC_DM_NMI:
1032	/* External NMI should be wired to LINT1, but Linux sometimes programs
1033	* LVT0 to NMI delivery mode as well.
1034	*/
1035	enmType = PDMAPICIRQ_NMI;
1036	/* Currently delivering NMIs through here causes problems with NMI watchdogs
1037	* on certain Linux kernels, e.g. 64-bit CentOS 5.3. Disable NMIs for now.
1038	*/
1039	return VINF_SUCCESS;
1040	case APIC_DM_SMI:
1041	enmType = PDMAPICIRQ_SMI;
1042	break;
1043	case APIC_DM_FIXED:
1044	{
1045	/** @todo implement APIC_DM_FIXED! */
1046	static unsigned s_c = 0;
1047	if (s_c++ < 5)
1048	LogRel(("delivery type APIC_DM_FIXED not implemented. u8Pin=%d u8Level=%d", u8Pin, u8Level));
1049	return VINF_SUCCESS;
1050	}
1051	case APIC_DM_INIT:
1052	/** @todo implement APIC_DM_INIT? */
1053	default:
1054	{
1055	static unsigned s_c = 0;
1056	if (s_c++ < 100)
1057	AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d", u8Delivery, u8Pin, u8Level));
1058	return VERR_INTERNAL_ERROR_4;
1059	}
1060	}
1061	LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
1062	cpuSetInterrupt(dev, s, enmType);
1063	}
1064	return VINF_SUCCESS;
1065	}
1066
1067	#endif /* VBOX */
1068
1069	/* return -1 if no bit is set */
1070	static int get_highest_priority_int(uint32_t *tab)
1071	{
1072	int i;
1073	for(i = 7; i >= 0; i--) {
1074	if (tab[i] != 0) {
1075	return i * 32 + fls_bit(tab[i]);
1076	}
1077	}
1078	return -1;
1079	}
1080
1081	static int apic_get_ppr(APICState *s)
1082	{
1083	int tpr, isrv, ppr;
1084
1085	tpr = (s->tpr >> 4);
1086	isrv = get_highest_priority_int(s->isr);
1087	if (isrv < 0)
1088	isrv = 0;
1089	isrv >>= 4;
1090	if (tpr >= isrv)
1091	ppr = s->tpr;
1092	else
1093	ppr = isrv << 4;
1094	return ppr;
1095	}
1096
1097	static int apic_get_ppr_zero_tpr(APICState *s)
1098	{
1099	int isrv;
1100
1101	isrv = get_highest_priority_int(s->isr);
1102	if (isrv < 0)
1103	isrv = 0;
1104	return isrv;
1105	}
1106
1107	static int apic_get_arb_pri(APICState *s)
1108	{
1109	/* XXX: arbitration */
1110	return 0;
1111	}
1112
1113	/* signal the CPU if an irq is pending */
1114	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
1115	{
1116	int irrv, ppr;
1117	if (!(s->spurious_vec & APIC_SV_ENABLE))
1118	#ifdef VBOX
1119	{
1120	/* Clear any pending APIC interrupt action flag. */
1121	cpuClearInterrupt(dev, s);
1122	return false;
1123	}
1124	#else
1125	return false;
1126	#endif /* VBOX */
1127	irrv = get_highest_priority_int(s->irr);
1128	if (irrv < 0)
1129	return false;
1130	ppr = apic_get_ppr(s);
1131	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1132	return false;
1133	#ifndef VBOX
1134	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
1135	#else
1136	cpuSetInterrupt(dev, s);
1137	return true;
1138	#endif
1139	}
1140
1141	#ifdef VBOX
1142
1143	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
1144	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
1145	{
1146	int irrv, ppr;
1147	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1148	if (!dev)
1149	return false;
1150
1151	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
1152
1153	APICState s = getLapic(dev); /* @todo fix interface */
1154
1155	/*
1156	* All our callbacks now come from single IOAPIC, thus locking
1157	* seems to be excessive now (@todo: check)
1158	*/
1159	irrv = get_highest_priority_int(s->irr);
1160	if (irrv < 0)
1161	return false;
1162
1163	ppr = apic_get_ppr_zero_tpr(s);
1164
1165	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1166	return false;
1167
1168	return true;
1169	}
1170
1171	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
1172	{
1173	bool fIrqIsActive = false;
1174	bool fIrqWasActive = false;
1175
1176	fIrqWasActive = apic_update_irq(dev, s);
1177	s->tpr = val;
1178	fIrqIsActive = apic_update_irq(dev, s);
1179
1180	/* If an interrupt is pending and now masked, then clear the FF flag. */
1181	if (fIrqWasActive && !fIrqIsActive)
1182	{
1183	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1184	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
1185	cpuClearInterrupt(dev, s);
1186	}
1187	}
1188	#endif
1189
1190	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
1191	{
1192	LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode));
1193	set_bit(s->irr, vector_num);
1194	if (trigger_mode)
1195	set_bit(s->tmr, vector_num);
1196	else
1197	reset_bit(s->tmr, vector_num);
1198	apic_update_irq(dev, s);
1199	}
1200
1201	static void apic_eoi(APICDeviceInfo dev, APICState s)
1202	{
1203	int isrv;
1204	isrv = get_highest_priority_int(s->isr);
1205	if (isrv < 0)
1206	return;
1207	reset_bit(s->isr, isrv);
1208	LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1209	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1210	set the remote IRR bit for level triggered interrupts. */
1211	apic_update_irq(dev, s);
1212	}
1213
1214	#ifndef VBOX
1215	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1216	#else /* VBOX */
1217	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1218	#endif /* VBOX */
1219	{
1220	uint32_t mask = 0;
1221
1222	if (dest_mode == 0)
1223	{
1224	if (dest == 0xff)
1225	mask = 0xff;
1226	else
1227	mask = 1 << dest;
1228	}
1229	else
1230	{
1231	APICState *apic = dev->CTX_SUFF(paLapics);
1232	uint32_t i;
1233
1234	/* XXX: cluster mode */
1235	for(i = 0; i < dev->cCpus; i++)
1236	{
1237	if (apic->dest_mode == APIC_DESTMODE_FLAT)
1238	{
1239	if (dest & apic->log_dest)
1240	mask \|= (1 << i);
1241	}
1242	else if (apic->dest_mode == APIC_DESTMODE_CLUSTER)
1243	{
1244	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1245	&&
1246	(dest & apic->log_dest & 0x0f))
1247	{
1248	mask \|= (1 << i);
1249	}
1250	}
1251	apic++;
1252	}
1253	}
1254
1255	return mask;
1256	}
1257
1258	#ifdef IN_RING3
1259	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s)
1260	{
1261	int i;
1262
1263	for(i = 0; i < APIC_LVT_NB; i++)
1264	s->lvt[i] = 1 << 16; /* mask LVT */
1265	s->tpr = 0;
1266	s->spurious_vec = 0xff;
1267	s->log_dest = 0;
1268	s->dest_mode = 0xff;
1269	memset(s->isr, 0, sizeof(s->isr));
1270	memset(s->tmr, 0, sizeof(s->tmr));
1271	memset(s->irr, 0, sizeof(s->irr));
1272	s->esr = 0;
1273	memset(s->icr, 0, sizeof(s->icr));
1274	s->divide_conf = 0;
1275	s->count_shift = 0;
1276	s->initial_count = 0;
1277	s->initial_count_load_time = 0;
1278	s->next_time = 0;
1279	}
1280
1281
1282	#ifdef VBOX
1283	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s)
1284	{
1285	apic_init_ipi(dev, s);
1286	cpuSendInitIpi(dev, s);
1287	}
1288	#endif
1289
1290	/* send a SIPI message to the CPU to start it */
1291	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1292	{
1293	#ifndef VBOX
1294	CPUState *env = s->cpu_env;
1295	if (!env->halted)
1296	return;
1297	env->eip = 0;
1298	cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1299	0xffff, 0);
1300	env->halted = 0;
1301	#else
1302	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1303	cpuSendSipi(dev, s, vector_num);
1304	#endif
1305	}
1306	#endif /* IN_RING3 */
1307
1308	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1309	uint8_t dest, uint8_t dest_mode,
1310	uint8_t delivery_mode, uint8_t vector_num,
1311	uint8_t polarity, uint8_t trigger_mode)
1312	{
1313	uint32_t deliver_bitmask = 0;
1314	int dest_shorthand = (s->icr[0] >> 18) & 3;
1315	#ifndef VBOX
1316	APICState *apic_iter;
1317	#endif /* !VBOX */
1318
1319	LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1320
1321	switch (dest_shorthand) {
1322	case 0:
1323	#ifndef VBOX
1324	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1325	#else /* VBOX */
1326	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1327	#endif /* !VBOX */
1328	break;
1329	case 1:
1330	deliver_bitmask = (1 << s->id);
1331	break;
1332	case 2:
1333	deliver_bitmask = 0xffffffff;
1334	break;
1335	case 3:
1336	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1337	break;
1338	}
1339
1340	switch (delivery_mode) {
1341	case APIC_DM_INIT:
1342	{
1343	int trig_mode = (s->icr[0] >> 15) & 1;
1344	int level = (s->icr[0] >> 14) & 1;
1345	if (level == 0 && trig_mode == 1) {
1346	foreach_apic(dev, deliver_bitmask,
1347	apic->arb_id = apic->id);
1348	#ifndef VBOX
1349	return;
1350	#else
1351	Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1352	return VINF_SUCCESS;
1353	#endif
1354	}
1355	}
1356	break;
1357
1358	case APIC_DM_SIPI:
1359	#ifndef VBOX
1360	for (apic_iter = first_local_apic; apic_iter != NULL;
1361	apic_iter = apic_iter->next_apic) {
1362	if (deliver_bitmask & (1 << apic_iter->id)) {
1363	/* XXX: SMP support */
1364	/* apic_startup(apic_iter); */
1365	}
1366	}
1367	return;
1368	#else
1369	# ifdef IN_RING3
1370	foreach_apic(dev, deliver_bitmask,
1371	apic_startup(dev, apic, vector_num));
1372	return VINF_SUCCESS;
1373	# else
1374	/* We shall send SIPI only in R3, R0 calls should be
1375	rescheduled to R3 */
1376	return VINF_IOM_HC_MMIO_WRITE;
1377	# endif
1378	#endif /* !VBOX */
1379	}
1380
1381	#ifndef VBOX
1382	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1383	trigger_mode);
1384	#else /* VBOX */
1385	return apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num,
1386	polarity, trigger_mode);
1387	#endif /* VBOX */
1388	}
1389
1390
1391	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1392	{
1393	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1394	/* if the APIC is not installed or enabled, we let the 8259 handle the
1395	IRQs */
1396	if (!dev)
1397	{
1398	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1399	return -1;
1400	}
1401
1402	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
1403
1404	APICState s = getLapic(dev); /* @todo fix interface */
1405	int intno;
1406
1407	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1408	Log(("CPU%d: apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n", s->phys_id));
1409	return -1;
1410	}
1411
1412	/* XXX: spurious IRQ handling */
1413	intno = get_highest_priority_int(s->irr);
1414	if (intno < 0) {
1415	Log(("CPU%d: apic_get_interrupt: returns -1 (irr)\n", s->phys_id));
1416	return -1;
1417	}
1418	if (s->tpr && (uint32_t)intno <= s->tpr) {
1419	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1420	return s->spurious_vec & 0xff;
1421	}
1422	reset_bit(s->irr, intno);
1423	set_bit(s->isr, intno);
1424	apic_update_irq(dev, s);
1425	LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno));
1426	return intno;
1427	}
1428
1429	static uint32_t apic_get_current_count(APICDeviceInfo dev, APICState s)
1430	{
1431	int64_t d;
1432	uint32_t val;
1433	#ifndef VBOX
1434	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1435	s->count_shift;
1436	#else /* VBOX */
1437	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1438	s->count_shift;
1439	#endif /* VBOX */
1440	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1441	/* periodic */
1442	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1443	} else {
1444	if (d >= s->initial_count)
1445	val = 0;
1446	else
1447	val = s->initial_count - d;
1448	}
1449	return val;
1450	}
1451
1452	#ifndef VBOX /* we've replaced all the code working the APIC timer. */
1453
1454	static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1455	{
1456	int64_t next_time, d;
1457
1458	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1459	d = (current_time - s->initial_count_load_time) >>
1460	s->count_shift;
1461	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1462	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1463	} else {
1464	if (d >= s->initial_count)
1465	goto no_timer;
1466	d = (uint64_t)s->initial_count + 1;
1467	}
1468	next_time = s->initial_count_load_time + (d << s->count_shift);
1469	# ifndef VBOX
1470	qemu_mod_timer(s->timer, next_time);
1471	# else
1472	TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1473	s->fTimerArmed = true;
1474	# endif
1475	s->next_time = next_time;
1476	} else {
1477	no_timer:
1478	# ifndef VBOX
1479	qemu_del_timer(s->timer);
1480	# else
1481	TMTimerStop(s->CTX_SUFF(pTimer));
1482	s->fTimerArmed = false;
1483	# endif
1484	}
1485	}
1486
1487	static void apic_timer(void *opaque)
1488	{
1489	APICState *s = opaque;
1490
1491	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1492	LogFlow(("apic_timer: trigger irq\n"));
1493	apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1494	}
1495	apic_timer_update(dev, s, s->next_time);
1496	}
1497
1498	#else /* VBOX */
1499
1500	/**
1501	* Implementation of the 0380h access: Timer reset + new initial count.
1502	*
1503	* @param dev The device state.
1504	* @param pThis The APIC sub-device state.
1505	* @param u32NewInitialCount The new initial count for the timer.
1506	*/
1507	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState pThis, uint32_t u32NewInitialCount)
1508	{
1509	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCount);
1510	pThis->initial_count = u32NewInitialCount;
1511
1512	/*
1513	* Don't (re-)arm the timer if the it's masked or if it's
1514	* a zero length one-shot timer.
1515	*/
1516	/** @todo check the correct behavior of setting a 0 initial_count for a one-shot
1517	* timer. This is just copying the behavior of the original code. */
1518	if ( !(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)
1519	&& ( (pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1520	\|\| u32NewInitialCount != 0))
1521	{
1522	/*
1523	* Calculate the relative next time and perform a combined timer get/set
1524	* operation. This avoids racing the clock between get and set.
1525	*/
1526	uint64_t cTicksNext = u32NewInitialCount;
1527	cTicksNext += 1;
1528	cTicksNext <<= pThis->count_shift;
1529	TMTimerSetRelative(pThis->CTX_SUFF(pTimer), cTicksNext, &pThis->initial_count_load_time);
1530	pThis->next_time = pThis->initial_count_load_time + cTicksNext;
1531	pThis->fTimerArmed = true;
1532	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountArm);
1533	}
1534	else
1535	{
1536	/* Stop it if necessary and record the load time for unmasking. */
1537	if (pThis->fTimerArmed)
1538	{
1539	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountDisarm);
1540	TMTimerStop(pThis->CTX_SUFF(pTimer));
1541	pThis->fTimerArmed = false;
1542	}
1543	pThis->initial_count_load_time = TMTimerGet(pThis->CTX_SUFF(pTimer));
1544	}
1545	}
1546
1547	/**
1548	* Implementation of the 0320h access: change the LVT flags.
1549	*
1550	* @param dev The device state.
1551	* @param pThis The APIC sub-device state to operate on.
1552	* @param fNew The new flags.
1553	*/
1554	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew)
1555	{
1556	STAM_COUNTER_INC(&pThis->StatTimerSetLvt);
1557
1558	/*
1559	* Make the flag change, saving the old ones so we can avoid
1560	* unnecessary work.
1561	*/
1562	uint32_t const fOld = pThis->lvt[APIC_LVT_TIMER];
1563	pThis->lvt[APIC_LVT_TIMER] = fNew;
1564
1565	/* Only the masked and peridic bits are relevant (see apic_timer_update). */
1566	if ( (fOld & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC))
1567	!= (fNew & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC)))
1568	{
1569	/*
1570	* If changed to one-shot from periodic, stop the timer if we're not
1571	* in the first period.
1572	*/
1573	/** @todo check how clearing the periodic flag really should behave when not
1574	* in period 1. The current code just mirrors the behavior of the
1575	* original implementation. */
1576	if ( (fOld & APIC_LVT_TIMER_PERIODIC)
1577	&& !(fNew & APIC_LVT_TIMER_PERIODIC))
1578	{
1579	STAM_COUNTER_INC(&pThis->StatTimerSetLvtClearPeriodic);
1580	uint64_t cTicks = (pThis->next_time - pThis->initial_count_load_time) >> pThis->count_shift;
1581	if (cTicks >= pThis->initial_count)
1582	{
1583	/* not first period, stop it. */
1584	TMTimerStop(pThis->CTX_SUFF(pTimer));
1585	pThis->fTimerArmed = false;
1586	}
1587	/* else: first period, let it fire normally. */
1588	}
1589
1590	/*
1591	* We postpone stopping the timer when it's masked, this way we can
1592	* avoid some timer work when the guest temporarily masks the timer.
1593	* (apicTimerCallback will stop it if still masked.)
1594	*/
1595	if (fNew & APIC_LVT_MASKED)
1596	STAM_COUNTER_INC(&pThis->StatTimerSetLvtPostponed);
1597	else if (pThis->fTimerArmed)
1598	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmed);
1599	/*
1600	* If unmasked and not armed, we have to rearm the timer so it will
1601	* fire at the end of the current period.
1602	* This is code is currently RACING the virtual sync clock!
1603	*/
1604	else if (fOld & APIC_LVT_MASKED)
1605	{
1606	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArm);
1607	for (unsigned cTries = 0; ; cTries++)
1608	{
1609	uint64_t NextTS;
1610	uint64_t cTicks = (TMTimerGet(pThis->CTX_SUFF(pTimer)) - pThis->initial_count_load_time) >> pThis->count_shift;
1611	if (fNew & APIC_LVT_TIMER_PERIODIC)
1612	NextTS = ((cTicks / ((uint64_t)pThis->initial_count + 1)) + 1) * ((uint64_t)pThis->initial_count + 1);
1613	else
1614	{
1615	if (cTicks >= pThis->initial_count)
1616	break;
1617	NextTS = (uint64_t)pThis->initial_count + 1;
1618	}
1619	NextTS <<= pThis->count_shift;
1620	NextTS += pThis->initial_count_load_time;
1621
1622	/* Try avoid the assertion in TM.cpp... this isn't perfect! */
1623	if ( NextTS > TMTimerGet(pThis->CTX_SUFF(pTimer))
1624	\|\| cTries > 10)
1625	{
1626	TMTimerSet(pThis->CTX_SUFF(pTimer), NextTS);
1627	pThis->next_time = NextTS;
1628	pThis->fTimerArmed = true;
1629	break;
1630	}
1631	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmRetries);
1632	}
1633	}
1634	}
1635	else
1636	STAM_COUNTER_INC(&pThis->StatTimerSetLvtNoRelevantChange);
1637	}
1638
1639	# ifdef IN_RING3
1640	/**
1641	* Timer callback function.
1642	*
1643	* @param pDevIns The device state.
1644	* @param pTimer The timer handle.
1645	* @param pvUser User argument pointing to the APIC instance.
1646	*/
1647	static DECLCALLBACK(void) apicTimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1648	{
1649	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1650	APICState pThis = (APICState )pvUser;
1651	Assert(pThis->pTimerR3 == pTimer);
1652	Assert(pThis->fTimerArmed);
1653
1654	if (!(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1655	LogFlow(("apic_timer: trigger irq\n"));
1656	apic_set_irq(dev, pThis, pThis->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1657
1658	if (pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1659	/* new interval. */
1660	pThis->next_time += (((uint64_t)pThis->initial_count + 1) << pThis->count_shift);
1661	TMTimerSet(pThis->CTX_SUFF(pTimer), pThis->next_time);
1662	pThis->fTimerArmed = true;
1663	} else {
1664	/* single shot. */
1665	pThis->fTimerArmed = false;
1666	}
1667	} else {
1668	/* masked, do not rearm. */
1669	pThis->fTimerArmed = false;
1670	}
1671	}
1672	# endif /* IN_RING3 */
1673
1674	#endif /* VBOX */
1675
1676	#ifndef VBOX
1677	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1678	{
1679	return 0;
1680	}
1681	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1682	{
1683	return 0;
1684	}
1685
1686	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1687	{
1688	}
1689
1690	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1691	{
1692	}
1693	#endif /* !VBOX */
1694
1695
1696	#ifndef VBOX
1697	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1698	{
1699	CPUState *env;
1700	APICState *s;
1701	#else /* VBOX */
1702	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1703	{
1704	#endif /* VBOX */
1705	uint32_t val;
1706	int index;
1707
1708	#ifndef VBOX
1709	env = cpu_single_env;
1710	if (!env)
1711	return 0;
1712	s = env->apic_state;
1713	#endif /* !VBOX */
1714
1715	index = (addr >> 4) & 0xff;
1716	switch(index) {
1717	case 0x02: /* id */
1718	val = s->id << 24;
1719	break;
1720	case 0x03: /* version */
1721	val = APIC_HW_VERSION \| ((APIC_LVT_NB - 1) << 16);
1722	break;
1723	case 0x08:
1724	val = s->tpr;
1725	break;
1726	case 0x09:
1727	val = apic_get_arb_pri(s);
1728	break;
1729	case 0x0a:
1730	/* ppr */
1731	val = apic_get_ppr(s);
1732	break;
1733	case 0x0b:
1734	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1735	val = 0;
1736	break;
1737	case 0x0d:
1738	val = s->log_dest << 24;
1739	break;
1740	case 0x0e:
1741	#ifdef VBOX
1742	/* Bottom 28 bits are always 1 */
1743	val = (s->dest_mode << 28) \| 0xfffffff;
1744	#else
1745	val = s->dest_mode << 28;
1746	#endif
1747	break;
1748	case 0x0f:
1749	val = s->spurious_vec;
1750	break;
1751	#ifndef VBOX
1752	case 0x10 ... 0x17:
1753	#else /* VBOX */
1754	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1755	#endif /* VBOX */
1756	val = s->isr[index & 7];
1757	break;
1758	#ifndef VBOX
1759	case 0x18 ... 0x1f:
1760	#else /* VBOX */
1761	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1762	#endif /* VBOX */
1763	val = s->tmr[index & 7];
1764	break;
1765	#ifndef VBOX
1766	case 0x20 ... 0x27:
1767	#else /* VBOX */
1768	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1769	#endif /* VBOX */
1770	val = s->irr[index & 7];
1771	break;
1772	case 0x28:
1773	val = s->esr;
1774	break;
1775	case 0x30:
1776	case 0x31:
1777	val = s->icr[index & 1];
1778	break;
1779	#ifndef VBOX
1780	case 0x32 ... 0x37:
1781	#else /* VBOX */
1782	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1783	#endif /* VBOX */
1784	val = s->lvt[index - 0x32];
1785	break;
1786	case 0x38:
1787	val = s->initial_count;
1788	break;
1789	case 0x39:
1790	val = apic_get_current_count(dev, s);
1791	break;
1792	case 0x3e:
1793	val = s->divide_conf;
1794	break;
1795	case 0x2f:
1796	/**
1797	* Correctable machine check exception vector, @todo: implement me!
1798	*/
1799	default:
1800	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1801	s->esr \|= ESR_ILLEGAL_ADDRESS;
1802	val = 0;
1803	break;
1804	}
1805	#ifdef DEBUG_APIC
1806	Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1807	#endif
1808	return val;
1809	}
1810
1811	#ifndef VBOX
1812	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1813	{
1814	CPUState *env;
1815	APICState *s;
1816	#else /* VBOX */
1817	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1818	{
1819	int rc = VINF_SUCCESS;
1820	#endif /* VBOX */
1821	int index;
1822
1823	#ifndef VBOX
1824	env = cpu_single_env;
1825	if (!env)
1826	return;
1827	s = env->apic_state;
1828	#endif /* !VBOX */
1829
1830	#ifdef DEBUG_APIC
1831	Log(("CPU%d: APIC write: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1832	#endif
1833
1834	index = (addr >> 4) & 0xff;
1835	switch(index) {
1836	case 0x02:
1837	s->id = (val >> 24);
1838	break;
1839	case 0x03:
1840	Log(("apic_mem_writel: write to version register; ignored\n"));
1841	break;
1842	case 0x08:
1843	#ifdef VBOX
1844	apic_update_tpr(dev, s, val);
1845	#else
1846	s->tpr = val;
1847	apic_update_irq(s);
1848	#endif
1849	break;
1850	case 0x09:
1851	case 0x0a:
1852	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1853	break;
1854	case 0x0b: /* EOI */
1855	apic_eoi(dev, s);
1856	break;
1857	case 0x0d:
1858	s->log_dest = val >> 24;
1859	break;
1860	case 0x0e:
1861	s->dest_mode = val >> 28;
1862	break;
1863	case 0x0f:
1864	s->spurious_vec = val & 0x1ff;
1865	apic_update_irq(dev, s);
1866	break;
1867	#ifndef VBOX
1868	case 0x10 ... 0x17:
1869	case 0x18 ... 0x1f:
1870	case 0x20 ... 0x27:
1871	case 0x28:
1872	#else
1873	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1874	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1875	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1876	case 0x28:
1877	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1878	#endif
1879	break;
1880
1881	case 0x30:
1882	s->icr[0] = val;
1883	rc = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1884	(s->icr[0] >> 11) & 1,
1885	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1886	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1887	break;
1888	case 0x31:
1889	s->icr[1] = val;
1890	break;
1891	#ifndef VBOX
1892	case 0x32 ... 0x37:
1893	#else /* VBOX */
1894	case 0x32 + APIC_LVT_TIMER:
1895	AssertCompile(APIC_LVT_TIMER == 0);
1896	apicTimerSetLvt(dev, s, val);
1897	break;
1898	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1899	#endif /* VBOX */
1900	{
1901	int n = index - 0x32;
1902	s->lvt[n] = val;
1903	#ifndef VBOX
1904	if (n == APIC_LVT_TIMER)
1905	apic_timer_update(s, qemu_get_clock(vm_clock));
1906	#endif /* !VBOX*/
1907	}
1908	break;
1909	case 0x38:
1910	#ifndef VBOX
1911	s->initial_count = val;
1912	s->initial_count_load_time = qemu_get_clock(vm_clock);
1913	apic_timer_update(dev, s, s->initial_count_load_time);
1914	#else /* VBOX */
1915	apicTimerSetInitialCount(dev, s, val);
1916	#endif /* VBOX*/
1917	break;
1918	case 0x39:
1919	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1920	break;
1921	case 0x3e:
1922	{
1923	int v;
1924	s->divide_conf = val & 0xb;
1925	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1926	s->count_shift = (v + 1) & 7;
1927	}
1928	break;
1929	default:
1930	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1931	s->esr \|= ESR_ILLEGAL_ADDRESS;
1932	break;
1933	}
1934	#ifdef VBOX
1935	return rc;
1936	#endif
1937	}
1938
1939	#ifdef IN_RING3
1940
1941	static void apic_save(QEMUFile f, void opaque)
1942	{
1943	APICState s = (APICState)opaque;
1944	int i;
1945
1946	qemu_put_be32s(f, &s->apicbase);
1947	#ifdef VBOX
1948	qemu_put_be32s(f, &s->id);
1949	qemu_put_be32s(f, &s->phys_id);
1950	qemu_put_be32s(f, &s->arb_id);
1951	qemu_put_be32s(f, &s->tpr);
1952	#else
1953	qemu_put_8s(f, &s->id);
1954	qemu_put_8s(f, &s->arb_id);
1955	qemu_put_8s(f, &s->tpr);
1956	#endif
1957	qemu_put_be32s(f, &s->spurious_vec);
1958	qemu_put_8s(f, &s->log_dest);
1959	qemu_put_8s(f, &s->dest_mode);
1960	for (i = 0; i < 8; i++) {
1961	qemu_put_be32s(f, &s->isr[i]);
1962	qemu_put_be32s(f, &s->tmr[i]);
1963	qemu_put_be32s(f, &s->irr[i]);
1964	}
1965	for (i = 0; i < APIC_LVT_NB; i++) {
1966	qemu_put_be32s(f, &s->lvt[i]);
1967	}
1968	qemu_put_be32s(f, &s->esr);
1969	qemu_put_be32s(f, &s->icr[0]);
1970	qemu_put_be32s(f, &s->icr[1]);
1971	qemu_put_be32s(f, &s->divide_conf);
1972	qemu_put_be32s(f, &s->count_shift);
1973	qemu_put_be32s(f, &s->initial_count);
1974	qemu_put_be64s(f, &s->initial_count_load_time);
1975	qemu_put_be64s(f, &s->next_time);
1976
1977	#ifdef VBOX
1978	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1979	#endif
1980	}
1981
1982	static int apic_load(QEMUFile f, void opaque, int version_id)
1983	{
1984	APICState s = (APICState)opaque;
1985	int i;
1986
1987	#ifdef VBOX
1988	/* XXX: what if the base changes? (registered memory regions) */
1989	qemu_get_be32s(f, &s->apicbase);
1990
1991	switch (version_id)
1992	{
1993	case APIC_SAVED_STATE_VERSION_ANCIENT:
1994	{
1995	uint8_t val = 0;
1996	qemu_get_8s(f, &val);
1997	s->id = val;
1998	/* UP only in old saved states */
1999	s->phys_id = 0;
2000	qemu_get_8s(f, &val);
2001	s->arb_id = val;
2002	break;
2003	}
2004	case APIC_SAVED_STATE_VERSION:
2005	case APIC_SAVED_STATE_VERSION_VBOX_30:
2006	qemu_get_be32s(f, &s->id);
2007	qemu_get_be32s(f, &s->phys_id);
2008	qemu_get_be32s(f, &s->arb_id);
2009	break;
2010	default:
2011	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2012	}
2013	qemu_get_be32s(f, &s->tpr);
2014	#else
2015	if (version_id != 1)
2016	return -EINVAL;
2017
2018	/* XXX: what if the base changes? (registered memory regions) */
2019	qemu_get_be32s(f, &s->apicbase);
2020	qemu_get_8s(f, &s->id);
2021	qemu_get_8s(f, &s->arb_id);
2022	qemu_get_8s(f, &s->tpr);
2023	#endif
2024	qemu_get_be32s(f, &s->spurious_vec);
2025	qemu_get_8s(f, &s->log_dest);
2026	qemu_get_8s(f, &s->dest_mode);
2027	for (i = 0; i < 8; i++) {
2028	qemu_get_be32s(f, &s->isr[i]);
2029	qemu_get_be32s(f, &s->tmr[i]);
2030	qemu_get_be32s(f, &s->irr[i]);
2031	}
2032	for (i = 0; i < APIC_LVT_NB; i++) {
2033	qemu_get_be32s(f, &s->lvt[i]);
2034	}
2035	qemu_get_be32s(f, &s->esr);
2036	qemu_get_be32s(f, &s->icr[0]);
2037	qemu_get_be32s(f, &s->icr[1]);
2038	qemu_get_be32s(f, &s->divide_conf);
2039	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
2040	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
2041	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
2042	qemu_get_be64s(f, (uint64_t *)&s->next_time);
2043
2044	#ifdef VBOX
2045	int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
2046	s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
2047	#endif
2048
2049	return VINF_SUCCESS; /** @todo darn mess! */
2050	}
2051	#ifndef VBOX
2052	static void apic_reset(void *opaque)
2053	{
2054	APICState s = (APICState)opaque;
2055	apic_init_ipi(s);
2056	}
2057	#endif
2058
2059	#endif /* IN_RING3 */
2060
2061	#ifndef VBOX
2062	static CPUReadMemoryFunc *apic_mem_read[3] = {
2063	apic_mem_readb,
2064	apic_mem_readw,
2065	apic_mem_readl,
2066	};
2067
2068	static CPUWriteMemoryFunc *apic_mem_write[3] = {
2069	apic_mem_writeb,
2070	apic_mem_writew,
2071	apic_mem_writel,
2072	};
2073
2074	int apic_init(CPUState *env)
2075	{
2076	APICState *s;
2077
2078	s = qemu_mallocz(sizeof(APICState));
2079	if (!s)
2080	return -1;
2081	env->apic_state = s;
2082	apic_init_ipi(s);
2083	s->id = last_apic_id++;
2084	s->cpu_env = env;
2085	s->apicbase = 0xfee00000 \|
2086	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
2087
2088	/* XXX: mapping more APICs at the same memory location */
2089	if (apic_io_memory == 0) {
2090	/* NOTE: the APIC is directly connected to the CPU - it is not
2091	on the global memory bus. */
2092	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
2093	apic_mem_write, NULL);
2094	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
2095	apic_io_memory);
2096	}
2097	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
2098
2099	register_savevm("apic", 0, 1, apic_save, apic_load, s);
2100	qemu_register_reset(apic_reset, s);
2101
2102	s->next_apic = first_local_apic;
2103	first_local_apic = s;
2104
2105	return 0;
2106	}
2107	#endif /* !VBOX */
2108
2109	static void ioapic_service(IOAPICState *s)
2110	{
2111	uint8_t i;
2112	uint8_t trig_mode;
2113	uint8_t vector;
2114	uint8_t delivery_mode;
2115	uint32_t mask;
2116	uint64_t entry;
2117	uint8_t dest;
2118	uint8_t dest_mode;
2119	uint8_t polarity;
2120
2121	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2122	mask = 1 << i;
2123	if (s->irr & mask) {
2124	entry = s->ioredtbl[i];
2125	if (!(entry & APIC_LVT_MASKED)) {
2126	trig_mode = ((entry >> 15) & 1);
2127	dest = entry >> 56;
2128	dest_mode = (entry >> 11) & 1;
2129	delivery_mode = (entry >> 8) & 7;
2130	polarity = (entry >> 13) & 1;
2131	if (trig_mode == APIC_TRIGGER_EDGE)
2132	s->irr &= ~mask;
2133	if (delivery_mode == APIC_DM_EXTINT)
2134	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
2135	vector = pic_read_irq(isa_pic);
2136	#else /* VBOX */
2137	{
2138	AssertMsgFailed(("Delivery mode ExtINT"));
2139	vector = 0xff; /* incorrect but shuts up gcc. */
2140	}
2141	#endif /* VBOX */
2142	else
2143	vector = entry & 0xff;
2144
2145	#ifndef VBOX
2146	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
2147	delivery_mode, vector, polarity, trig_mode);
2148	#else /* VBOX */
2149	int rc = s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
2150	dest,
2151	dest_mode,
2152	delivery_mode,
2153	vector,
2154	polarity,
2155	trig_mode);
2156	/* We must be sure that attempts to reschedule in R3
2157	never get here */
2158	Assert(rc == VINF_SUCCESS);
2159	#endif /* VBOX */
2160	}
2161	}
2162	}
2163	}
2164
2165	#ifdef VBOX
2166	static
2167	#endif
2168	void ioapic_set_irq(void *opaque, int vector, int level)
2169	{
2170	IOAPICState s = (IOAPICState)opaque;
2171
2172	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
2173	uint32_t mask = 1 << vector;
2174	uint64_t entry = s->ioredtbl[vector];
2175
2176	if ((entry >> 15) & 1) {
2177	/* level triggered */
2178	if (level) {
2179	s->irr \|= mask;
2180	ioapic_service(s);
2181	#ifdef VBOX
2182	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
2183	s->irr &= ~mask;
2184	}
2185	#endif
2186	} else {
2187	s->irr &= ~mask;
2188	}
2189	} else {
2190	/* edge triggered */
2191	if (level) {
2192	s->irr \|= mask;
2193	ioapic_service(s);
2194	}
2195	}
2196	}
2197	}
2198
2199	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
2200	{
2201	IOAPICState s = (IOAPICState)opaque;
2202	int index;
2203	uint32_t val = 0;
2204
2205	addr &= 0xff;
2206	if (addr == 0x00) {
2207	val = s->ioregsel;
2208	} else if (addr == 0x10) {
2209	switch (s->ioregsel) {
2210	case 0x00:
2211	val = s->id << 24;
2212	break;
2213	case 0x01:
2214	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
2215	break;
2216	case 0x02:
2217	val = 0;
2218	break;
2219	default:
2220	index = (s->ioregsel - 0x10) >> 1;
2221	if (index >= 0 && index < IOAPIC_NUM_PINS) {
2222	if (s->ioregsel & 1)
2223	val = s->ioredtbl[index] >> 32;
2224	else
2225	val = s->ioredtbl[index] & 0xffffffff;
2226	}
2227	}
2228	#ifdef DEBUG_IOAPIC
2229	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
2230	#endif
2231	}
2232	return val;
2233	}
2234
2235	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2236	{
2237	IOAPICState s = (IOAPICState)opaque;
2238	int index;
2239
2240	addr &= 0xff;
2241	if (addr == 0x00) {
2242	s->ioregsel = val;
2243	return;
2244	} else if (addr == 0x10) {
2245	#ifdef DEBUG_IOAPIC
2246	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
2247	#endif
2248	switch (s->ioregsel) {
2249	case 0x00:
2250	s->id = (val >> 24) & 0xff;
2251	return;
2252	case 0x01:
2253	case 0x02:
2254	return;
2255	default:
2256	index = (s->ioregsel - 0x10) >> 1;
2257	if (index >= 0 && index < IOAPIC_NUM_PINS) {
2258	if (s->ioregsel & 1) {
2259	s->ioredtbl[index] &= 0xffffffff;
2260	s->ioredtbl[index] \|= (uint64_t)val << 32;
2261	} else {
2262	#ifdef VBOX
2263	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
2264	uint8_t vec = val & 0xff;
2265	if ((val & APIC_LVT_MASKED) \|\|
2266	((vec >= 0x10) && (vec < 0xff)))
2267	{
2268	s->ioredtbl[index] &= ~0xffffffffULL;
2269	s->ioredtbl[index] \|= val;
2270	}
2271	else
2272	{
2273	/*
2274	* Linux 2.6 kernels has pretty strange function
2275	* unlock_ExtINT_logic() which writes
2276	* absolutely bogus (all 0) value into the vector
2277	* with pretty vague explanation why.
2278	* So we just ignore such writes.
2279	*/
2280	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
2281	}
2282	}
2283	#else
2284	s->ioredtbl[index] &= ~0xffffffffULL;
2285	s->ioredtbl[index] \|= val;
2286	#endif
2287	ioapic_service(s);
2288	}
2289	}
2290	}
2291	}
2292
2293	#ifdef IN_RING3
2294
2295	static void ioapic_save(QEMUFile f, void opaque)
2296	{
2297	IOAPICState s = (IOAPICState)opaque;
2298	int i;
2299
2300	qemu_put_8s(f, &s->id);
2301	qemu_put_8s(f, &s->ioregsel);
2302	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2303	qemu_put_be64s(f, &s->ioredtbl[i]);
2304	}
2305	}
2306
2307	static int ioapic_load(QEMUFile f, void opaque, int version_id)
2308	{
2309	IOAPICState s = (IOAPICState)opaque;
2310	int i;
2311
2312	if (version_id != 1)
2313	return -EINVAL;
2314
2315	qemu_get_8s(f, &s->id);
2316	qemu_get_8s(f, &s->ioregsel);
2317	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2318	qemu_get_be64s(f, &s->ioredtbl[i]);
2319	}
2320	return 0;
2321	}
2322
2323	static void ioapic_reset(void *opaque)
2324	{
2325	IOAPICState s = (IOAPICState)opaque;
2326	#ifdef VBOX
2327	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
2328	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
2329	#endif
2330	int i;
2331
2332	memset(s, 0, sizeof(*s));
2333	for(i = 0; i < IOAPIC_NUM_PINS; i++)
2334	s->ioredtbl[i] = 1 << 16; /* mask LVT */
2335
2336	#ifdef VBOX
2337	if (pDevIns)
2338	{
2339	s->pDevInsR3 = pDevIns;
2340	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2341	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2342	}
2343	if (pIoApicHlp)
2344	{
2345	s->pIoApicHlpR3 = pIoApicHlp;
2346	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2347	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2348	}
2349	#endif
2350	}
2351
2352	#endif /* IN_RING3 */
2353
2354	#ifndef VBOX
2355	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
2356	ioapic_mem_readl,
2357	ioapic_mem_readl,
2358	ioapic_mem_readl,
2359	};
2360
2361	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
2362	ioapic_mem_writel,
2363	ioapic_mem_writel,
2364	ioapic_mem_writel,
2365	};
2366
2367	IOAPICState *ioapic_init(void)
2368	{
2369	IOAPICState *s;
2370	int io_memory;
2371
2372	s = qemu_mallocz(sizeof(IOAPICState));
2373	if (!s)
2374	return NULL;
2375	ioapic_reset(s);
2376	s->id = last_apic_id++;
2377
2378	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
2379	ioapic_mem_write, s);
2380	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2381
2382	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2383	qemu_register_reset(ioapic_reset, s);
2384
2385	return s;
2386	}
2387	#endif /* !VBOX */
2388
2389	/* LAPIC */
2390	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2391	{
2392	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2393	APICState *s = getLapic(dev);
2394
2395	Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2396
2397	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2398	different physical addresses, see #3092) */
2399
2400	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2401	switch (cb)
2402	{
2403	case 1:
2404	(uint8_t )pv = 0;
2405	break;
2406
2407	case 2:
2408	(uint16_t )pv = 0;
2409	break;
2410
2411	case 4:
2412	{
2413	#if 0 /** @note experimental */
2414	#ifndef IN_RING3
2415	uint32_t index = (GCPhysAddr >> 4) & 0xff;
2416
2417	if ( index == 0x08 /* TPR */
2418	&& ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2419	{
2420	#ifdef IN_RC
2421	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2422	#else
2423	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2424	pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2425	#endif
2426	return VINF_PATM_HC_MMIO_PATCH_READ;
2427	}
2428	#endif
2429	#endif /* experimental */
2430	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2431	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
2432	APIC_UNLOCK(dev);
2433	break;
2434	}
2435	default:
2436	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2437	return VERR_INTERNAL_ERROR;
2438	}
2439	return VINF_SUCCESS;
2440	}
2441
2442	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2443	{
2444	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2445	APICState *s = getLapic(dev);
2446
2447	Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2448
2449	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2450	different physical addresses, see #3092) */
2451
2452	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2453	switch (cb)
2454	{
2455	case 1:
2456	case 2:
2457	/* ignore */
2458	break;
2459
2460	case 4:
2461	{
2462	int rc;
2463	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2464	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2465	APIC_UNLOCK(dev);
2466	return rc;
2467	}
2468
2469	default:
2470	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2471	return VERR_INTERNAL_ERROR;
2472	}
2473	return VINF_SUCCESS;
2474	}
2475
2476	#ifdef IN_RING3
2477
2478	/* Print a 8-dword LAPIC bit map (256 bits). */
2479	static void lapicDumpVec(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp, unsigned start)
2480	{
2481	unsigned i;
2482	uint32_t val;
2483
2484	for (i = 0; i < 8; ++i)
2485	{
2486	val = apic_mem_readl(dev, lapic, start + (i << 4));
2487	pHlp->pfnPrintf(pHlp, "%08X", val);
2488	}
2489	pHlp->pfnPrintf(pHlp, "\n");
2490	}
2491
2492	/* Print basic LAPIC state. */
2493	static DECLCALLBACK(void) lapicInfoBasic(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2494	{
2495	uint32_t val;
2496	unsigned max_lvt;
2497
2498	pHlp->pfnPrintf(pHlp, "Local APIC at %08X:\n", lapic->apicbase);
2499	val = apic_mem_readl(dev, lapic, 0x20);
2500	pHlp->pfnPrintf(pHlp, " LAPIC ID : %08X\n", val);
2501	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
2502	val = apic_mem_readl(dev, lapic, 0x30);
2503	max_lvt = (val >> 16) & 0xff;
2504	pHlp->pfnPrintf(pHlp, " APIC VER : %08X\n", val);
2505	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
2506	pHlp->pfnPrintf(pHlp, " lvts = %d\n", ((val >> 16) & 0xff) + 1);
2507	val = apic_mem_readl(dev, lapic, 0x80);
2508	pHlp->pfnPrintf(pHlp, " TPR : %08X\n", val);
2509	pHlp->pfnPrintf(pHlp, " task pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2510	val = apic_mem_readl(dev, lapic, 0xA0);
2511	pHlp->pfnPrintf(pHlp, " PPR : %08X\n", val);
2512	pHlp->pfnPrintf(pHlp, " cpu pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2513	val = apic_mem_readl(dev, lapic, 0xD0);
2514	pHlp->pfnPrintf(pHlp, " LDR : %08X\n", val);
2515	pHlp->pfnPrintf(pHlp, " log id = %02X\n", (val >> 24) & 0xff);
2516	val = apic_mem_readl(dev, lapic, 0xE0);
2517	pHlp->pfnPrintf(pHlp, " DFR : %08X\n", val);
2518	val = apic_mem_readl(dev, lapic, 0xF0);
2519	pHlp->pfnPrintf(pHlp, " SVR : %08X\n", val);
2520	pHlp->pfnPrintf(pHlp, " focus = %s\n", val & (1 << 9) ? "check off" : "check on");
2521	pHlp->pfnPrintf(pHlp, " lapic = %s\n", val & (1 << 8) ? "ENABLED" : "DISABLED");
2522	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2523	pHlp->pfnPrintf(pHlp, " ISR : ");
2524	lapicDumpVec(dev, lapic, pHlp, 0x100);
2525	val = get_highest_priority_int(lapic->isr);
2526	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2527	pHlp->pfnPrintf(pHlp, " IRR : ");
2528	lapicDumpVec(dev, lapic, pHlp, 0x200);
2529	val = get_highest_priority_int(lapic->irr);
2530	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2531	val = apic_mem_readl(dev, lapic, 0x320);
2532	}
2533
2534	/* Print the more interesting LAPIC LVT entries. */
2535	static DECLCALLBACK(void) lapicInfoLVT(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2536	{
2537	uint32_t val;
2538	static const char *dmodes[] = { "Fixed ", "Reserved", "SMI", "Reserved",
2539	"NMI", "INIT", "Reserved", "ExtINT" };
2540
2541	val = apic_mem_readl(dev, lapic, 0x320);
2542	pHlp->pfnPrintf(pHlp, " LVT Timer : %08X\n", val);
2543	pHlp->pfnPrintf(pHlp, " mode = %s\n", val & (1 << 17) ? "periodic" : "one-shot");
2544	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2545	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2546	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2547	val = apic_mem_readl(dev, lapic, 0x350);
2548	pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08X\n", val);
2549	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2550	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2551	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2552	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2553	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2554	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2555	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2556	val = apic_mem_readl(dev, lapic, 0x360);
2557	pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08X\n", val);
2558	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2559	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2560	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2561	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2562	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2563	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2564	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2565	}
2566
2567	/* Print LAPIC timer state. */
2568	static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2569	{
2570	uint32_t val;
2571	unsigned divider;
2572
2573	pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
2574	val = apic_mem_readl(dev, lapic, 0x380);
2575	pHlp->pfnPrintf(pHlp, " Initial count : %08X\n", val);
2576	val = apic_mem_readl(dev, lapic, 0x390);
2577	pHlp->pfnPrintf(pHlp, " Current count : %08X\n", val);
2578	val = apic_mem_readl(dev, lapic, 0x3E0);
2579	pHlp->pfnPrintf(pHlp, " Divide config : %08X\n", val);
2580	divider = ((val >> 1) & 0x04) \| (val & 0x03);
2581	pHlp->pfnPrintf(pHlp, " divider = %d\n", divider == 7 ? 1 : 2 << divider);
2582	}
2583
2584	/**
2585	* Info handler, device version. Dumps Local APIC(s) state according to given argument.
2586	*
2587	* @param pDevIns Device instance which registered the info.
2588	* @param pHlp Callback functions for doing output.
2589	* @param pszArgs Argument string. Optional.
2590	*/
2591	static DECLCALLBACK(void) lapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2592	{
2593	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2594	APICState *lapic;
2595
2596	lapic = getLapic(dev);
2597
2598	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2599	{
2600	lapicInfoBasic(dev, lapic, pHlp);
2601	}
2602	else if (!strcmp(pszArgs, "lvt"))
2603	{
2604	lapicInfoLVT(dev, lapic, pHlp);
2605	}
2606	else if (!strcmp(pszArgs, "timer"))
2607	{
2608	lapicInfoTimer(dev, lapic, pHlp);
2609	}
2610	else
2611	{
2612	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
2613	}
2614	}
2615
2616	/**
2617	* @copydoc FNSSMDEVLIVEEXEC
2618	*/
2619	static DECLCALLBACK(int) apicLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
2620	{
2621	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2622
2623	SSMR3PutU32( pSSM, pThis->cCpus);
2624	SSMR3PutBool(pSSM, pThis->fIoApic);
2625	SSMR3PutU32( pSSM, pThis->enmVersion);
2626	AssertCompile(PDMAPICVERSION_APIC == 2);
2627
2628	return VINF_SSM_DONT_CALL_AGAIN;
2629	}
2630
2631	/**
2632	* @copydoc FNSSMDEVSAVEEXEC
2633	*/
2634	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2635	{
2636	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2637
2638	/* config */
2639	apicLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
2640
2641	/* save all APICs data, @todo: is it correct? */
2642	foreach_apic(dev, 0xffffffff, apic_save(pSSM, apic));
2643
2644	return VINF_SUCCESS;
2645	}
2646
2647	/**
2648	* @copydoc FNSSMDEVLOADEXEC
2649	*/
2650	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2651	{
2652	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2653
2654	if ( uVersion != APIC_SAVED_STATE_VERSION
2655	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
2656	&& uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
2657	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2658
2659	/* config */
2660	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30) {
2661	uint32_t cCpus;
2662	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2663	if (cCpus != pThis->cCpus)
2664	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pThis->cCpus);
2665	bool fIoApic;
2666	rc = SSMR3GetBool(pSSM, &fIoApic); AssertRCReturn(rc, rc);
2667	if (fIoApic != pThis->fIoApic)
2668	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pThis->fIoApic);
2669	uint32_t uApicVersion;
2670	rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
2671	if (uApicVersion != (uint32_t)pThis->enmVersion)
2672	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pThis->enmVersion);
2673	}
2674
2675	if (uPass != SSM_PASS_FINAL)
2676	return VINF_SUCCESS;
2677
2678	/* load all APICs data / /* @todo: is it correct? */
2679	foreach_apic(pThis, 0xffffffff,
2680	if (apic_load(pSSM, apic, uVersion)) {
2681	AssertFailed();
2682	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2683	}
2684	);
2685	return VINF_SUCCESS;
2686	}
2687
2688	/**
2689	* @copydoc FNPDMDEVRESET
2690	*/
2691	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2692	{
2693	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2694	unsigned i;
2695
2696	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2697
2698	/* Reset all APICs. */
2699	for (i = 0; i < dev->cCpus; i++) {
2700	APICState *pApic = &dev->CTX_SUFF(paLapics)[i];
2701	TMTimerStop(pApic->CTX_SUFF(pTimer));
2702
2703	/* Clear LAPIC state as if an INIT IPI was sent. */
2704	apic_init_ipi(dev, pApic);
2705	/* The IDs are not touched by apic_init_ipi() and must be reset now. */
2706	pApic->arb_id = pApic->id = i;
2707	Assert(pApic->id == pApic->phys_id); /* The two should match again. */
2708	/* Reset should re-enable the APIC. */
2709	pApic->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_ENABLE;
2710	if (pApic->phys_id == 0)
2711	pApic->apicbase \|= MSR_IA32_APICBASE_BSP;
2712
2713	/* Clear any pending APIC interrupt action flag. */
2714	cpuClearInterrupt(dev, pApic);
2715	}
2716	/** @todo r=bird: Why is this done everytime, while the constructor first
2717	* checks the CPUID? Who is right? */
2718	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2719
2720	APIC_UNLOCK(dev);
2721	}
2722
2723	/**
2724	* @copydoc FNPDMDEVRELOCATE
2725	*/
2726	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2727	{
2728	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2729	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2730	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2731	pThis->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pThis->paLapicsR3);
2732	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2733	for (uint32_t i = 0; i < pThis->cCpus; i++)
2734	pThis->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pThis->paLapicsR3[i].pTimerR3);
2735	}
2736
2737	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2738	{
2739	int i;
2740	memset(apic, 0, sizeof(*apic));
2741	apic->apicbase = UINT32_C(0xfee00000) \| MSR_IA32_APICBASE_ENABLE;
2742	/* Mark first CPU as BSP */
2743	if (id == 0)
2744	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2745	for (i = 0; i < APIC_LVT_NB; i++)
2746	apic->lvt[i] = 1 << 16; /* mask LVT */
2747	apic->spurious_vec = 0xff;
2748	apic->phys_id = apic->id = id;
2749	}
2750
2751	/**
2752	* @copydoc FNPDMDEVCONSTRUCT
2753	*/
2754	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2755	{
2756	PDMAPICREG ApicReg;
2757	int rc;
2758	uint32_t i;
2759	bool fIoApic;
2760	bool fGCEnabled;
2761	bool fR0Enabled;
2762	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2763	uint32_t cCpus;
2764
2765	/*
2766	* Only single device instance.
2767	*/
2768	Assert(iInstance == 0);
2769
2770	/*
2771	* Validate configuration.
2772	*/
2773	if (!CFGMR3AreValuesValid(pCfg,
2774	"IOAPIC\0"
2775	"GCEnabled\0"
2776	"R0Enabled\0"
2777	"NumCPUs\0"))
2778	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2779
2780	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fIoApic, true);
2781	if (RT_FAILURE(rc))
2782	return PDMDEV_SET_ERROR(pDevIns, rc,
2783	N_("Configuration error: Failed to read \"IOAPIC\""));
2784
2785	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2786	if (RT_FAILURE(rc))
2787	return PDMDEV_SET_ERROR(pDevIns, rc,
2788	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2789
2790	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2791	if (RT_FAILURE(rc))
2792	return PDMDEV_SET_ERROR(pDevIns, rc,
2793	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2794
2795	rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
2796	if (RT_FAILURE(rc))
2797	return PDMDEV_SET_ERROR(pDevIns, rc,
2798	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2799
2800	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIoApic));
2801
2802	/** @todo Current implementation is limited to 32 CPUs due to the use of 32
2803	* bits bitmasks. */
2804	if (cCpus > 32)
2805	return PDMDEV_SET_ERROR(pDevIns, rc,
2806	N_("Configuration error: Invalid value for \"NumCPUs\""));
2807
2808	/*
2809	* Init the data.
2810	*/
2811	pThis->pDevInsR3 = pDevIns;
2812	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2813	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2814	pThis->cCpus = cCpus;
2815	pThis->fIoApic = fIoApic;
2816	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2817	pThis->enmVersion = PDMAPICVERSION_APIC;
2818
2819	PVM pVM = PDMDevHlpGetVM(pDevIns);
2820	/*
2821	* We are not freeing this memory, as it's automatically released when guest exits.
2822	*/
2823	rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->paLapicsR3);
2824	if (RT_FAILURE(rc))
2825	return VERR_NO_MEMORY;
2826	pThis->paLapicsR0 = MMHyperR3ToR0(pVM, pThis->paLapicsR3);
2827	pThis->paLapicsRC = MMHyperR3ToRC(pVM, pThis->paLapicsR3);
2828
2829	for (i = 0; i < cCpus; i++)
2830	initApicData(&pThis->paLapicsR3[i], i);
2831
2832	/*
2833	* Register the APIC.
2834	*/
2835	ApicReg.u32Version = PDM_APICREG_VERSION;
2836	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2837	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2838	ApicReg.pfnSetBaseR3 = apicSetBase;
2839	ApicReg.pfnGetBaseR3 = apicGetBase;
2840	ApicReg.pfnSetTPRR3 = apicSetTPR;
2841	ApicReg.pfnGetTPRR3 = apicGetTPR;
2842	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2843	ApicReg.pfnReadMSRR3 = apicReadMSR;
2844	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2845	ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
2846	if (fGCEnabled) {
2847	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2848	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2849	ApicReg.pszSetBaseRC = "apicSetBase";
2850	ApicReg.pszGetBaseRC = "apicGetBase";
2851	ApicReg.pszSetTPRRC = "apicSetTPR";
2852	ApicReg.pszGetTPRRC = "apicGetTPR";
2853	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2854	ApicReg.pszReadMSRRC = "apicReadMSR";
2855	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2856	ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
2857	} else {
2858	ApicReg.pszGetInterruptRC = NULL;
2859	ApicReg.pszHasPendingIrqRC = NULL;
2860	ApicReg.pszSetBaseRC = NULL;
2861	ApicReg.pszGetBaseRC = NULL;
2862	ApicReg.pszSetTPRRC = NULL;
2863	ApicReg.pszGetTPRRC = NULL;
2864	ApicReg.pszWriteMSRRC = NULL;
2865	ApicReg.pszReadMSRRC = NULL;
2866	ApicReg.pszBusDeliverRC = NULL;
2867	ApicReg.pszLocalInterruptRC = NULL;
2868	}
2869	if (fR0Enabled) {
2870	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2871	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2872	ApicReg.pszSetBaseR0 = "apicSetBase";
2873	ApicReg.pszGetBaseR0 = "apicGetBase";
2874	ApicReg.pszSetTPRR0 = "apicSetTPR";
2875	ApicReg.pszGetTPRR0 = "apicGetTPR";
2876	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2877	ApicReg.pszReadMSRR0 = "apicReadMSR";
2878	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2879	ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
2880	} else {
2881	ApicReg.pszGetInterruptR0 = NULL;
2882	ApicReg.pszHasPendingIrqR0 = NULL;
2883	ApicReg.pszSetBaseR0 = NULL;
2884	ApicReg.pszGetBaseR0 = NULL;
2885	ApicReg.pszSetTPRR0 = NULL;
2886	ApicReg.pszGetTPRR0 = NULL;
2887	ApicReg.pszWriteMSRR0 = NULL;
2888	ApicReg.pszReadMSRR0 = NULL;
2889	ApicReg.pszBusDeliverR0 = NULL;
2890	ApicReg.pszLocalInterruptR0 = NULL;
2891	}
2892
2893	rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2894	AssertLogRelRCReturn(rc, rc);
2895	pThis->pCritSectR3 = pThis->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2896
2897	/*
2898	* The the CPUID feature bit.
2899	*/
2900	/** @todo r=bird: See remark in the apicReset. */
2901	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2902	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2903	if (u32Eax >= 1) {
2904	if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
2905	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2906	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2907	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2908	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2909	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2910	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */)) {
2911	LogRel(("Activating Local APIC\n"));
2912	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2913	}
2914	}
2915
2916	/*
2917	* Register the MMIO range.
2918	*/
2919	uint32_t ApicBase = pThis->paLapicsR3[0].apicbase & ~0xfff;
2920	rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pThis,
2921	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2922	if (RT_FAILURE(rc))
2923	return rc;
2924
2925	if (fGCEnabled) {
2926	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2927	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2928
2929	rc = PDMDevHlpMMIORegisterRC(pDevIns, ApicBase, 0x1000, 0,
2930	"apicMMIOWrite", "apicMMIORead", NULL);
2931	if (RT_FAILURE(rc))
2932	return rc;
2933	}
2934
2935	if (fR0Enabled) {
2936	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2937	pThis->pCritSectR0 = pThis->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2938
2939	rc = PDMDevHlpMMIORegisterR0(pDevIns, ApicBase, 0x1000, 0,
2940	"apicMMIOWrite", "apicMMIORead", NULL);
2941	if (RT_FAILURE(rc))
2942	return rc;
2943	}
2944
2945	/*
2946	* Create the APIC timers.
2947	*/
2948	for (i = 0; i < cCpus; i++) {
2949	APICState *pApic = &pThis->paLapicsR3[i];
2950	pApic->pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_USER, "APIC Timer #%u", i);
2951	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimerCallback, pApic,
2952	TMTIMER_FLAGS_NO_CRIT_SECT, pApic->pszDesc, &pApic->pTimerR3);
2953	if (RT_FAILURE(rc))
2954	return rc;
2955	pApic->pTimerR0 = TMTimerR0Ptr(pApic->pTimerR3);
2956	pApic->pTimerRC = TMTimerRCPtr(pApic->pTimerR3);
2957	TMR3TimerSetCritSect(pApic->pTimerR3, pThis->pCritSectR3);
2958	}
2959
2960	/*
2961	* Saved state.
2962	*/
2963	rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pThis),
2964	apicLiveExec, apicSaveExec, apicLoadExec);
2965	if (RT_FAILURE(rc))
2966	return rc;
2967
2968	/*
2969	* Register debugger info callback.
2970	*/
2971	PDMDevHlpDBGFInfoRegister(pDevIns, "lapic", "Display Local APIC state for current CPU. "
2972	"Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", lapicInfo);
2973
2974	#ifdef VBOX_WITH_STATISTICS
2975	/*
2976	* Statistics.
2977	*/
2978	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2979	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2980	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2981	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2982	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2983	for (i = 0; i < cCpus; i++) {
2984	APICState *pApic = &pThis->paLapicsR3[i];
2985	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
2986	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
2987	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
2988	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
2989	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
2990	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
2991	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
2992	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
2993	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
2994	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
2995	}
2996	#endif
2997
2998	return VINF_SUCCESS;
2999	}
3000
3001
3002	/**
3003	* APIC device registration structure.
3004	*/
3005	const PDMDEVREG g_DeviceAPIC =
3006	{
3007	/* u32Version */
3008	PDM_DEVREG_VERSION,
3009	/* szName */
3010	"apic",
3011	/* szRCMod */
3012	"VBoxDD2GC.gc",
3013	/* szR0Mod */
3014	"VBoxDD2R0.r0",
3015	/* pszDescription */
3016	"Advanced Programmable Interrupt Controller (APIC) Device",
3017	/* fFlags */
3018	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3019	/* fClass */
3020	PDM_DEVREG_CLASS_PIC,
3021	/* cMaxInstances */
3022	1,
3023	/* cbInstance */
3024	sizeof(APICState),
3025	/* pfnConstruct */
3026	apicConstruct,
3027	/* pfnDestruct */
3028	NULL,
3029	/* pfnRelocate */
3030	apicRelocate,
3031	/* pfnIOCtl */
3032	NULL,
3033	/* pfnPowerOn */
3034	NULL,
3035	/* pfnReset */
3036	apicReset,
3037	/* pfnSuspend */
3038	NULL,
3039	/* pfnResume */
3040	NULL,
3041	/* pfnAttach */
3042	NULL,
3043	/* pfnDetach */
3044	NULL,
3045	/* pfnQueryInterface. */
3046	NULL,
3047	/* pfnInitComplete */
3048	NULL,
3049	/* pfnPowerOff */
3050	NULL,
3051	/* pfnSoftReset */
3052	NULL,
3053	/* u32VersionEnd */
3054	PDM_DEVREG_VERSION
3055	};
3056
3057	#endif /* IN_RING3 */
3058
3059
3060	/* IOAPIC */
3061
3062	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3063	{
3064	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3065	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
3066
3067	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
3068	switch (cb) {
3069	case 1:
3070	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3071	break;
3072
3073	case 2:
3074	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3075	break;
3076
3077	case 4:
3078	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3079	break;
3080
3081	default:
3082	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3083	IOAPIC_UNLOCK(s);
3084	return VERR_INTERNAL_ERROR;
3085	}
3086	IOAPIC_UNLOCK(s);
3087	return VINF_SUCCESS;
3088	}
3089
3090	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3091	{
3092	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3093
3094	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
3095	switch (cb) {
3096	case 1:
3097	case 2:
3098	case 4:
3099	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
3100	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
3101	IOAPIC_UNLOCK(s);
3102	break;
3103
3104	default:
3105	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3106	return VERR_INTERNAL_ERROR;
3107	}
3108	return VINF_SUCCESS;
3109	}
3110
3111	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
3112	{
3113	/* PDM lock is taken here; @todo add assertion */
3114	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
3115	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
3116	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
3117	ioapic_set_irq(pThis, iIrq, iLevel);
3118	}
3119
3120
3121	#ifdef IN_RING3
3122
3123	/**
3124	* Info handler, device version. Dumps I/O APIC state.
3125	*
3126	* @param pDevIns Device instance which registered the info.
3127	* @param pHlp Callback functions for doing output.
3128	* @param pszArgs Argument string. Optional and specific to the handler.
3129	*/
3130	static DECLCALLBACK(void) ioapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3131	{
3132	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3133	uint32_t val;
3134	unsigned i;
3135	unsigned max_redir;
3136
3137	pHlp->pfnPrintf(pHlp, "I/O APIC at %08X:\n", 0xfec00000);
3138	val = s->id << 24; /* Would be nice to call ioapic_mem_readl() directly, but that's not so simple. */
3139	pHlp->pfnPrintf(pHlp, " IOAPICID : %08X\n", val);
3140	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
3141	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16);
3142	max_redir = (val >> 16) & 0xff;
3143	pHlp->pfnPrintf(pHlp, " IOAPICVER : %08X\n", val);
3144	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
3145	pHlp->pfnPrintf(pHlp, " redirs = %d\n", ((val >> 16) & 0xff) + 1);
3146	val = 0;
3147	pHlp->pfnPrintf(pHlp, " IOAPICARB : %08X\n", val);
3148	pHlp->pfnPrintf(pHlp, " arb ID = %02X\n", (val >> 24) & 0xff);
3149	Assert(sizeof(s->ioredtbl) / sizeof(s->ioredtbl[0]) > max_redir);
3150	pHlp->pfnPrintf(pHlp, "I/O redirection table\n");
3151	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
3152	for (i = 0; i <= max_redir; ++i)
3153	{
3154	static const char *dmodes[] = { "Fixed ", "LowPri", "SMI ", "Resrvd",
3155	"NMI ", "INIT ", "Resrvd", "ExtINT" };
3156
3157	pHlp->pfnPrintf(pHlp, " %02d %s %02X %d %s %d %s %s %s %3d (%016llX)\n",
3158	i,
3159	s->ioredtbl[i] & (1 << 11) ? "log " : "phys", /* dest mode */
3160	(int)(s->ioredtbl[i] >> 56), /* dest addr */
3161	(int)(s->ioredtbl[i] >> 16) & 1, /* mask */
3162	s->ioredtbl[i] & (1 << 15) ? "level" : "edge ", /* trigger */
3163	(int)(s->ioredtbl[i] >> 14) & 1, /* remote IRR */
3164	s->ioredtbl[i] & (1 << 13) ? "activelo" : "activehi", /* polarity */
3165	s->ioredtbl[i] & (1 << 12) ? "pend" : "idle", /* delivery status */
3166	dmodes[(s->ioredtbl[i] >> 8) & 0x07], /* delivery mode */
3167	(int)s->ioredtbl[i] & 0xff, /* vector */
3168	s->ioredtbl[i] /* entire register */
3169	);
3170	}
3171	}
3172
3173	/**
3174	* @copydoc FNSSMDEVSAVEEXEC
3175	*/
3176	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3177	{
3178	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3179	ioapic_save(pSSM, s);
3180	return VINF_SUCCESS;
3181	}
3182
3183	/**
3184	* @copydoc FNSSMDEVLOADEXEC
3185	*/
3186	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3187	{
3188	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3189
3190	if (ioapic_load(pSSM, s, uVersion)) {
3191	AssertFailed();
3192	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3193	}
3194	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3195
3196	return VINF_SUCCESS;
3197	}
3198
3199	/**
3200	* @copydoc FNPDMDEVRESET
3201	*/
3202	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
3203	{
3204	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3205	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
3206	ioapic_reset(s);
3207	IOAPIC_UNLOCK(s);
3208	}
3209
3210	/**
3211	* @copydoc FNPDMDEVRELOCATE
3212	*/
3213	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3214	{
3215	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3216	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3217	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
3218	}
3219
3220	/**
3221	* @copydoc FNPDMDEVCONSTRUCT
3222	*/
3223	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3224	{
3225	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3226	PDMIOAPICREG IoApicReg;
3227	bool fGCEnabled;
3228	bool fR0Enabled;
3229	int rc;
3230
3231	Assert(iInstance == 0);
3232
3233	/*
3234	* Validate and read the configuration.
3235	*/
3236	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
3237	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
3238
3239	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
3240	if (RT_FAILURE(rc))
3241	return PDMDEV_SET_ERROR(pDevIns, rc,
3242	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
3243
3244	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
3245	if (RT_FAILURE(rc))
3246	return PDMDEV_SET_ERROR(pDevIns, rc,
3247	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
3248	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
3249
3250	/*
3251	* Initialize the state data.
3252	*/
3253	s->pDevInsR3 = pDevIns;
3254	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3255	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3256	ioapic_reset(s);
3257	s->id = 0;
3258
3259	/*
3260	* Register the IOAPIC and get helpers.
3261	*/
3262	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
3263	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
3264	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
3265	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
3266	rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
3267	if (RT_FAILURE(rc))
3268	{
3269	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
3270	return rc;
3271	}
3272
3273	/*
3274	* Register MMIO callbacks and saved state.
3275	*/
3276	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
3277	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
3278	if (RT_FAILURE(rc))
3279	return rc;
3280
3281	if (fGCEnabled) {
3282	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
3283
3284	rc = PDMDevHlpMMIORegisterRC(pDevIns, 0xfec00000, 0x1000, 0,
3285	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
3286	if (RT_FAILURE(rc))
3287	return rc;
3288	}
3289
3290	if (fR0Enabled) {
3291	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
3292
3293	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
3294	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
3295	if (RT_FAILURE(rc))
3296	return rc;
3297	}
3298
3299	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* version /, sizeof(s), ioapicSaveExec, ioapicLoadExec);
3300	if (RT_FAILURE(rc))
3301	return rc;
3302
3303	/*
3304	* Register debugger info callback.
3305	*/
3306	PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display I/O APIC state.", ioapicInfo);
3307
3308	#ifdef VBOX_WITH_STATISTICS
3309	/*
3310	* Statistics.
3311	*/
3312	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
3313	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
3314	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
3315	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
3316	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
3317	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
3318	#endif
3319
3320	return VINF_SUCCESS;
3321	}
3322
3323	/**
3324	* IO APIC device registration structure.
3325	*/
3326	const PDMDEVREG g_DeviceIOAPIC =
3327	{
3328	/* u32Version */
3329	PDM_DEVREG_VERSION,
3330	/* szName */
3331	"ioapic",
3332	/* szRCMod */
3333	"VBoxDD2GC.gc",
3334	/* szR0Mod */
3335	"VBoxDD2R0.r0",
3336	/* pszDescription */
3337	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
3338	/* fFlags */
3339	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3340	/* fClass */
3341	PDM_DEVREG_CLASS_PIC,
3342	/* cMaxInstances */
3343	1,
3344	/* cbInstance */
3345	sizeof(IOAPICState),
3346	/* pfnConstruct */
3347	ioapicConstruct,
3348	/* pfnDestruct */
3349	NULL,
3350	/* pfnRelocate */
3351	ioapicRelocate,
3352	/* pfnIOCtl */
3353	NULL,
3354	/* pfnPowerOn */
3355	NULL,
3356	/* pfnReset */
3357	ioapicReset,
3358	/* pfnSuspend */
3359	NULL,
3360	/* pfnResume */
3361	NULL,
3362	/* pfnAttach */
3363	NULL,
3364	/* pfnDetach */
3365	NULL,
3366	/* pfnQueryInterface. */
3367	NULL,
3368	/* pfnInitComplete */
3369	NULL,
3370	/* pfnPowerOff */
3371	NULL,
3372	/* pfnSoftReset */
3373	NULL,
3374	/* u32VersionEnd */
3375	PDM_DEVREG_VERSION
3376	};
3377
3378	#endif /* IN_RING3 */
3379	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 28346

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