DevAPIC.cpp@ 18664

Last change on this file since 18664 was 17968, checked in by vboxsync, 16 years ago
APIC: locking refined
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1	#ifdef VBOX
2	/* $Id: DevAPIC.cpp 17968 2009-03-16 19:02:29Z vboxsync $ */
3	/** @file
4	* Advanced Programmable Interrupt Controller (APIC) Device and
5	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* apic.c revision 1.5 @@OSETODO
27	*/
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/pdmdev.h>
34
35	#include <VBox/log.h>
36	#include <VBox/stam.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40	#include "Builtins2.h"
41	#include "vl_vbox.h"
42
43	#define MSR_IA32_APICBASE 0x1b
44	#define MSR_IA32_APICBASE_BSP (1<<8)
45	#define MSR_IA32_APICBASE_ENABLE (1<<11)
46	#ifdef VBOX
47	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48	#endif
49	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51	#ifndef EINVAL
52	# define EINVAL 1
53	#endif
54
55	#ifdef _MSC_VER
56	# pragma warning(disable:4244)
57	#endif
58
59	/** @def APIC_LOCK
60	* Acquires the PDM lock. */
61	#define APIC_LOCK(pThis, rc) \
62	do { \
63	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
64	if (rc2 != VINF_SUCCESS) \
65	return rc2; \
66	} while (0)
67
68	/** @def APIC_LOCK_VOID
69	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
70	#define APIC_LOCK_VOID(pThis, rc) \
71	do { \
72	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
73	AssertLogRelRCReturnVoid(rc2); \
74	} while (0)
75
76	/** @def APIC_UNLOCK
77	* Releases the PDM lock. */
78	#define APIC_UNLOCK(pThis) \
79	(pThis)->CTX_SUFF(pApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
80
81	/** @def IOAPIC_LOCK
82	* Acquires the PDM lock. */
83	#define IOAPIC_LOCK(pThis, rc) \
84	do { \
85	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
86	if (rc2 != VINF_SUCCESS) \
87	return rc2; \
88	} while (0)
89
90	/** @def IOAPIC_UNLOCK
91	* Releases the PDM lock. */
92	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
93
94	/** @def LAPIC_BASE
95	* Return address of first LAPIC state. */
96	#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
97
98	#define foreach_apic(dev, mask, code) \
99	do { \
100	uint32_t i; \
101	APICState* apic = LAPIC_BASE(dev); \
102	for (i = 0; i < dev->cCpus; i++) \
103	{ \
104	if (mask & (1 << (apic->id))) \
105	{ \
106	code; \
107	} \
108	apic++; \
109	} \
110	} while (0)
111
112	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
113	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
114	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
115	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
116
117	#endif /* VBOX */
118
119	/*
120	* APIC support
121	*
122	* Copyright (c) 2004-2005 Fabrice Bellard
123	*
124	* This library is free software; you can redistribute it and/or
125	* modify it under the terms of the GNU Lesser General Public
126	* License as published by the Free Software Foundation; either
127	* version 2 of the License, or (at your option) any later version.
128	*
129	* This library is distributed in the hope that it will be useful,
130	* but WITHOUT ANY WARRANTY; without even the implied warranty of
131	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
132	* Lesser General Public License for more details.
133	*
134	* You should have received a copy of the GNU Lesser General Public
135	* License along with this library; if not, write to the Free Software
136	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
137	*/
138	#ifndef VBOX
139	#include "vl.h"
140	#endif
141
142	#define DEBUG_APIC
143	#define DEBUG_IOAPIC
144
145	/* APIC Local Vector Table */
146	#define APIC_LVT_TIMER 0
147	#define APIC_LVT_THERMAL 1
148	#define APIC_LVT_PERFORM 2
149	#define APIC_LVT_LINT0 3
150	#define APIC_LVT_LINT1 4
151	#define APIC_LVT_ERROR 5
152	#define APIC_LVT_NB 6
153
154	/* APIC delivery modes */
155	#define APIC_DM_FIXED 0
156	#define APIC_DM_LOWPRI 1
157	#define APIC_DM_SMI 2
158	#define APIC_DM_NMI 4
159	#define APIC_DM_INIT 5
160	#define APIC_DM_SIPI 6
161	#define APIC_DM_EXTINT 7
162
163	/* APIC destination mode */
164	#define APIC_DESTMODE_FLAT 0xf
165	#define APIC_DESTMODE_CLUSTER 1
166
167	#define APIC_TRIGGER_EDGE 0
168	#define APIC_TRIGGER_LEVEL 1
169
170	#define APIC_LVT_TIMER_PERIODIC (1<<17)
171	#define APIC_LVT_MASKED (1<<16)
172	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
173	#define APIC_LVT_REMOTE_IRR (1<<14)
174	#define APIC_INPUT_POLARITY (1<<13)
175	#define APIC_SEND_PENDING (1<<12)
176
177	#define IOAPIC_NUM_PINS 0x18
178
179	#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181	#define APIC_SV_ENABLE (1 << 8)
182
183	#ifdef VBOX
184	#define APIC_MAX_PATCH_ATTEMPTS 100
185
186	typedef uint32_t PhysApicId;
187	typedef uint32_t LogApicId;
188	#endif
189
190	typedef struct APICState {
191	#ifndef VBOX
192	CPUState *cpu_env;
193	#endif /* !VBOX */
194	uint32_t apicbase;
195	#ifdef VBOX
196	/* Task priority register (interrupt level) */
197	uint32_t tpr;
198	/* Logical APIC id */
199	LogApicId id;
200	/* Physical APIC id */
201	PhysApicId phys_id;
202	/** @todo: is it logical or physical? Not really used anyway now. */
203	PhysApicId arb_id;
204	#else
205	uint8_t tpr;
206	uint8_t id;
207	uint8_t arb_id;
208	#endif
209	uint32_t spurious_vec;
210	uint8_t log_dest;
211	uint8_t dest_mode;
212	uint32_t isr[8]; /* in service register */
213	uint32_t tmr[8]; /* trigger mode register */
214	uint32_t irr[8]; /* interrupt request register */
215	uint32_t lvt[APIC_LVT_NB];
216	uint32_t esr; /* error register */
217	uint32_t icr[2];
218	uint32_t divide_conf;
219	int count_shift;
220	uint32_t initial_count;
221	#ifdef VBOX
222	uint32_t Alignment0;
223	#endif
224	int64_t initial_count_load_time, next_time;
225	#ifndef VBOX
226	QEMUTimer *timer;
227	struct APICState *next_apic;
228	#else
229	/** The APIC timer - R3 Ptr. */
230	PTMTIMERR3 pTimerR3;
231
232	/** The APIC timer - R0 Ptr. */
233	PTMTIMERR0 pTimerR0;
234
235	/** The APIC timer - RC Ptr. */
236	PTMTIMERRC pTimerRC;
237
238	/** Alignment */
239	uint32_t Alignment1;
240	#endif /* VBOX */
241	} APICState;
242
243	struct IOAPICState {
244	uint8_t id;
245	uint8_t ioregsel;
246
247	uint32_t irr;
248	uint64_t ioredtbl[IOAPIC_NUM_PINS];
249
250	#ifdef VBOX
251	/** The device instance - R3 Ptr. */
252	PPDMDEVINSR3 pDevInsR3;
253	/** The IOAPIC helpers - R3 Ptr. */
254	PCPDMIOAPICHLPR3 pIoApicHlpR3;
255
256	/** The device instance - R0 Ptr. */
257	PPDMDEVINSR0 pDevInsR0;
258	/** The IOAPIC helpers - R0 Ptr. */
259	PCPDMIOAPICHLPR0 pIoApicHlpR0;
260
261	/** The device instance - RC Ptr. */
262	PPDMDEVINSRC pDevInsRC;
263	/** The IOAPIC helpers - RC Ptr. */
264	PCPDMIOAPICHLPRC pIoApicHlpRC;
265
266	# ifdef VBOX_WITH_STATISTICS
267	STAMCOUNTER StatMMIOReadGC;
268	STAMCOUNTER StatMMIOReadHC;
269	STAMCOUNTER StatMMIOWriteGC;
270	STAMCOUNTER StatMMIOWriteHC;
271	STAMCOUNTER StatSetIrqGC;
272	STAMCOUNTER StatSetIrqHC;
273	# endif
274	#endif /* VBOX */
275	};
276
277	#ifdef VBOX
278	typedef struct IOAPICState IOAPICState;
279
280	typedef struct
281	{
282	/** The device instance - R3 Ptr. */
283	PPDMDEVINSR3 pDevInsR3;
284	/** The APIC helpers - R3 Ptr. */
285	PCPDMAPICHLPR3 pApicHlpR3;
286	/** LAPICs states - R3 Ptr */
287	RTR3PTR pLapicsR3;
288
289	/** The device instance - R0 Ptr. */
290	PPDMDEVINSR0 pDevInsR0;
291	/** The APIC helpers - R0 Ptr. */
292	PCPDMAPICHLPR0 pApicHlpR0;
293	/** LAPICs states - R0 Ptr */
294	RTR0PTR pLapicsR0;
295
296	/** The device instance - RC Ptr. */
297	PPDMDEVINSRC pDevInsRC;
298	/** The APIC helpers - RC Ptr. */
299	PCPDMAPICHLPRC pApicHlpRC;
300	/** LAPICs states - RC Ptr */
301	RTRCPTR pLapicsRC;
302
303	/** APIC specification version in this virtual hardware configuration. */
304	PDMAPICVERSION enmVersion;
305
306	/** Number of attempts made to optimize TPR accesses. */
307	uint32_t ulTPRPatchAttempts;
308
309	/** Number of CPUs on the system (same as LAPIC count). */
310	uint32_t cCpus;
311
312	# ifdef VBOX_WITH_STATISTICS
313	STAMCOUNTER StatMMIOReadGC;
314	STAMCOUNTER StatMMIOReadHC;
315	STAMCOUNTER StatMMIOWriteGC;
316	STAMCOUNTER StatMMIOWriteHC;
317	STAMCOUNTER StatClearedActiveIrq;
318	# endif
319	} APICDeviceInfo;
320
321	static void apic_eoi(APICDeviceInfo dev, APICState s);
322	static void apic_deliver(APICDeviceInfo* dev, APICState *s,
323	uint8_t dest, uint8_t dest_mode,
324	uint8_t delivery_mode, uint8_t vector_num,
325	uint8_t polarity, uint8_t trigger_mode);
326	static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
327	int64_t current_time);
328	static int apic_get_arb_pri(APICState *s);
329	static int apic_get_ppr(APICState *s);
330	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
331
332
333	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
334	{
335	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
336	return LAPIC_BASE(dev) + id;
337	}
338
339	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
340	{
341	/* LAPIC's array is indexed by CPU id */
342	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
343	return getLapicById(dev, id);
344	}
345
346	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
347	{
348	/* for now we assume LAPIC physical id == CPU id */
349	return VMCPUID(s->phys_id);
350	}
351
352	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s)
353	{
354	Log2(("apic: setting interrupt flag\n"));
355	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns),
356	getCpuFromLapic(dev, s));
357	}
358
359	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
360	{
361	Log2(("apic: clear interrupt flag\n"));
362	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
363	getCpuFromLapic(dev, s));
364	}
365
366	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
367	{
368	switch (dev->enmVersion)
369	{
370	case PDMAPICVERSION_NONE:
371	return 0;
372	case PDMAPICVERSION_APIC:
373	return MSR_IA32_APICBASE_ENABLE;
374	case PDMAPICVERSION_X2APIC:
375	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
376	default:
377	AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
378	return 0;
379	}
380	}
381
382	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
383	{
384	switch (((apic->apicbase) >> 10) & 0x3)
385	{
386	case 0:
387	return PDMAPICVERSION_NONE;
388	case 1:
389	default:
390	/* Invalid */
391	return PDMAPICVERSION_NONE;
392	case 2:
393	return PDMAPICVERSION_APIC;
394	case 3:
395	return PDMAPICVERSION_X2APIC;
396	}
397	}
398
399	#endif /* VBOX */
400
401	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
402	#ifndef VBOX
403	static int apic_io_memory;
404	static APICState *first_local_apic = NULL;
405	static int last_apic_id = 0;
406	#endif /* !VBOX */
407
408	static void apic_init_ipi(APICState *s);
409	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
410	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
411
412	#ifdef VBOX
413	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
414	__BEGIN_DECLS
415	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
416	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
417	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
418	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
419	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
420	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
421	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val);
422	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns);
423	PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
424	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
425	uint8_t u8TriggerMode);
426	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
427	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
428	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
429	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
430	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
431
432	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
433	__END_DECLS
434	#endif /* VBOX */
435
436	#ifndef VBOX
437	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
438	uint8_t vector_num, uint8_t polarity,
439	uint8_t trigger_mode)
440	{
441	APICState *apic_iter;
442	#else /* VBOX */
443	static void apic_bus_deliver(APICDeviceInfo* dev,
444	uint32_t deliver_bitmask, uint8_t delivery_mode,
445	uint8_t vector_num, uint8_t polarity,
446	uint8_t trigger_mode)
447	{
448	#endif /* VBOX */
449
450	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
451	switch (delivery_mode) {
452	case APIC_DM_LOWPRI:
453	{
454	int d = -1;
455	if (deliver_bitmask)
456	d = ffs_bit(deliver_bitmask);
457	if (d >= 0)
458	{
459	APICState* apic = getLapicById(dev, d);
460	apic_set_irq(dev, apic, vector_num, trigger_mode);
461	}
462	return;
463	}
464	case APIC_DM_FIXED:
465	/* XXX: arbitration */
466	break;
467
468	case APIC_DM_SMI:
469	/** @todo: what do we really do with SMI */
470	foreach_apic(dev, deliver_bitmask,
471	cpuSetInterrupt(dev, apic));
472	return;
473
474	case APIC_DM_NMI:
475	/** @todo: what do we really do with NMI */
476	foreach_apic(dev, deliver_bitmask,
477	cpuSetInterrupt(dev, apic));
478	return;
479
480	case APIC_DM_INIT:
481	/* normal INIT IPI sent to processors */
482	#ifdef VBOX
483	foreach_apic(dev, deliver_bitmask,
484	apic_init_ipi(apic));
485	#else
486	for (apic_iter = first_local_apic; apic_iter != NULL;
487	apic_iter = apic_iter->next_apic) {
488	apic_init_ipi(apic_iter);
489	}
490	#endif
491	return;
492
493	case APIC_DM_EXTINT:
494	/* handled in I/O APIC code */
495	break;
496
497	default:
498	return;
499	}
500
501	#ifdef VBOX
502	foreach_apic(dev, deliver_bitmask,
503	apic_set_irq (dev, apic, vector_num, trigger_mode));
504	#else /* VBOX */
505	for (apic_iter = first_local_apic; apic_iter != NULL;
506	apic_iter = apic_iter->next_apic) {
507	if (deliver_bitmask & (1 << apic_iter->id))
508	apic_set_irq(apic_iter, vector_num, trigger_mode);
509	}
510	#endif /* VBOX */
511	}
512
513	#ifndef VBOX
514	void cpu_set_apic_base(CPUState *env, uint64_t val)
515	{
516	APICState *s = env->apic_state;
517	#ifdef DEBUG_APIC
518	Log(("cpu_set_apic_base: %016llx\n", val));
519	#endif
520
521	s->apicbase = (val & 0xfffff000) \|
522	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
523	/* if disabled, cannot be enabled again */
524	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
525	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
526	env->cpuid_features &= ~CPUID_APIC;
527	s->spurious_vec &= ~APIC_SV_ENABLE;
528	}
529	}
530	#else /* VBOX */
531	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
532	{
533	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
534	APICState *s = getLapic(dev);
535	Log(("cpu_set_apic_base: %016RX64\n", val));
536
537	/** @todo: do we need to lock here ? */
538	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
539	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
540	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
541	PDMAPICVERSION oldMode = getApicMode(s);
542	s->apicbase =
543	(val & 0xfffff000) \| /* base */
544	(val & getApicEnableBits(dev)) \| /* mode */
545	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
546	PDMAPICVERSION newMode = getApicMode(s);
547
548	if (oldMode != newMode)
549	{
550	switch (newMode)
551	{
552	case PDMAPICVERSION_NONE:
553	{
554	s->spurious_vec &= ~APIC_SV_ENABLE;
555	/* Clear any pending APIC interrupt action flag. */
556	cpuClearInterrupt(dev, s);
557	/** @todo: why do we do that? */
558	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
559	break;
560	}
561	case PDMAPICVERSION_APIC:
562	/** @todo: map MMIO ranges, if needed */
563	break;
564	case PDMAPICVERSION_X2APIC:
565	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
566	break;
567	default:
568	break;
569	}
570	}
571	/* APIC_UNLOCK(dev); */
572	}
573	#endif /* VBOX */
574	#ifndef VBOX
575
576	uint64_t cpu_get_apic_base(CPUState *env)
577	{
578	APICState *s = env->apic_state;
579	#ifdef DEBUG_APIC
580	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
581	#endif
582	return s->apicbase;
583	}
584
585	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
586	{
587	APICState *s = env->apic_state;
588	s->tpr = (val & 0x0f) << 4;
589	apic_update_irq(s);
590	}
591
592	uint8_t cpu_get_apic_tpr(CPUX86State *env)
593	{
594	APICState *s = env->apic_state;
595	return s->tpr >> 4;
596	}
597
598	static int fls_bit(int value)
599	{
600	unsigned int ret = 0;
601
602	#ifdef HOST_I386
603	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
604	return ret;
605	#else
606	if (value > 0xffff)
607	value >>= 16, ret = 16;
608	if (value > 0xff)
609	value >>= 8, ret += 8;
610	if (value > 0xf)
611	value >>= 4, ret += 4;
612	if (value > 0x3)
613	value >>= 2, ret += 2;
614	return ret + (value >> 1);
615	#endif
616	}
617
618	static inline void set_bit(uint32_t *tab, int index)
619	{
620	int i, mask;
621	i = index >> 5;
622	mask = 1 << (index & 0x1f);
623	tab[i] \|= mask;
624	}
625
626	static inline void reset_bit(uint32_t *tab, int index)
627	{
628	int i, mask;
629	i = index >> 5;
630	mask = 1 << (index & 0x1f);
631	tab[i] &= ~mask;
632	}
633
634
635	#else /* VBOX */
636
637	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
638	{
639	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
640	APICState *s = getLapic(dev);
641	Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
642	return s->apicbase;
643	}
644
645	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
646	{
647	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
648	APICState *s = getLapic(dev);
649	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
650	apic_update_tpr(dev, s, (val & 0x0f) << 4);
651	}
652
653	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
654	{
655	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
656	APICState *s = getLapic(dev);
657	Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
658	return s->tpr >> 4;
659	}
660
661	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
662	{
663	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
664
665	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
666	return VERR_EM_INTERPRETER;
667
668	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
669	//LogRel(("nike: WRMSR on %d: to %x written %llx\n", idCpu, index, u64Value));
670
671	APICState* apic = getLapicById(dev, idCpu);
672
673	switch (index)
674	{
675	case 0x02:
676	apic->id = (u64Value >> 24);
677	break;
678	case 0x03:
679	break;
680	case 0x08:
681	apic_update_tpr(dev, apic, u64Value);
682	break;
683	case 0x09: case 0x0a:
684	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
685	break;
686	case 0x0b: /* EOI */
687	apic_eoi(dev, apic);
688	break;
689	case 0x0d:
690	apic->log_dest = u64Value >> 24;
691	break;
692	case 0x0e:
693	apic->dest_mode = u64Value >> 28;
694	break;
695	case 0x0f:
696	apic->spurious_vec = u64Value & 0x1ff;
697	apic_update_irq(dev, apic);
698	break;
699	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
700	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
701	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
702	case 0x28:
703	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
704	break;
705
706	case 0x30:
707	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
708	apic->icr[0] = (uint32_t)u64Value;
709	apic->icr[1] = (uint32_t)(u64Value >> 32);
710	apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
711	(apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),
712	(apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
713	break;
714	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
715	{
716	int n = index - 0x32;
717	apic->lvt[n] = u64Value;
718	if (n == APIC_LVT_TIMER)
719	apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
720	}
721	break;
722	case 0x38:
723	apic->initial_count = u64Value;
724	apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
725	apic_timer_update(dev, apic, apic->initial_count_load_time);
726	break;
727	case 0x39:
728	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
729	break;
730	case 0x3e:
731	{
732	int v;
733	apic->divide_conf = u64Value & 0xb;
734	v = (apic->divide_conf & 3) \| ((apic->divide_conf >> 1) & 4);
735	apic->count_shift = (v + 1) & 7;
736	break;
737	}
738	case 0x3f:
739	{
740	/* Self IPI, see x2APIC book 2.4.5 */
741	int vector = u64Value & 0xff;
742	apic_bus_deliver(dev,
743	1 << getLapicById(dev, idCpu)->id /* Self */,
744	0 /* Delivery mode - fixed */,
745	vector,
746	0 /* Polarity - conform to the bus */,
747	0 /* Trigger mode - edge */);
748	break;
749	}
750	default:
751	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
752	apic->esr \|= ESR_ILLEGAL_ADDRESS;
753	break;
754	}
755
756	return VINF_SUCCESS;
757	}
758	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
759	{
760	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
761
762	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
763	return VERR_EM_INTERPRETER;
764
765	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
766	//LogRel(("nike: RDMSR on %d: read from %x\n", idCpu, index));
767	APICState* apic = getLapicById(dev, idCpu);
768	uint64_t val = 0;
769
770	switch (index)
771	{
772	case 0x02: /* id */
773	val = apic->id << 24;
774	break;
775	case 0x03: /* version */
776	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
777	break;
778	case 0x08:
779	val = apic->tpr;
780	break;
781	case 0x09:
782	val = apic_get_arb_pri(apic);
783	break;
784	case 0x0a:
785	/* ppr */
786	val = apic_get_ppr(apic);
787	break;
788	case 0x0b:
789	val = 0;
790	break;
791	case 0x0d:
792	val = apic->log_dest << 24;
793	break;
794	case 0x0e:
795	/* Bottom 28 bits are always 1 */
796	val = (apic->dest_mode << 28) \| 0xfffffff;
797	break;
798	case 0x0f:
799	val = apic->spurious_vec;
800	break;
801	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
802	val = apic->isr[index & 7];
803	break;
804	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
805	val = apic->tmr[index & 7];
806	break;
807	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
808	val = apic->irr[index & 7];
809	break;
810	case 0x28:
811	val = apic->esr;
812	break;
813	case 0x30:
814	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
815	val = ((uint64_t)apic->icr[0x31] << 32) \| apic->icr[0x30];
816	break;
817	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
818	val = apic->lvt[index - 0x32];
819	break;
820	case 0x38:
821	val = apic->initial_count;
822	break;
823	case 0x39:
824	val = apic_get_current_count(dev, apic);
825	break;
826	case 0x3e:
827	val = apic->divide_conf;
828	break;
829	case 0x3f:
830	/* Self IPI register is write only */
831	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
832	break;
833	default:
834	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
835	apic->esr \|= ESR_ILLEGAL_ADDRESS;
836	val = 0;
837	break;
838	}
839	*pu64Value = val;
840	return VINF_SUCCESS;
841	}
842
843	/**
844	* More or less private interface between IOAPIC, only PDM is responsible
845	* for connecting the two devices.
846	*/
847	PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
848	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
849	uint8_t u8TriggerMode)
850	{
851	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
852	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
853	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
854	apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
855	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
856	}
857
858	#endif /* VBOX */
859
860	/* return -1 if no bit is set */
861	static int get_highest_priority_int(uint32_t *tab)
862	{
863	int i;
864	for(i = 7; i >= 0; i--) {
865	if (tab[i] != 0) {
866	return i * 32 + fls_bit(tab[i]);
867	}
868	}
869	return -1;
870	}
871
872	static int apic_get_ppr(APICState *s)
873	{
874	int tpr, isrv, ppr;
875
876	tpr = (s->tpr >> 4);
877	isrv = get_highest_priority_int(s->isr);
878	if (isrv < 0)
879	isrv = 0;
880	isrv >>= 4;
881	if (tpr >= isrv)
882	ppr = s->tpr;
883	else
884	ppr = isrv << 4;
885	return ppr;
886	}
887
888	static int apic_get_ppr_zero_tpr(APICState *s)
889	{
890	int isrv;
891
892	isrv = get_highest_priority_int(s->isr);
893	if (isrv < 0)
894	isrv = 0;
895	return isrv;
896	}
897
898	static int apic_get_arb_pri(APICState *s)
899	{
900	/* XXX: arbitration */
901	return 0;
902	}
903
904	/* signal the CPU if an irq is pending */
905	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
906	{
907	int irrv, ppr;
908	if (!(s->spurious_vec & APIC_SV_ENABLE))
909	#ifdef VBOX
910	{
911	/* Clear any pending APIC interrupt action flag. */
912	cpuClearInterrupt(dev, s);
913	return false;
914	}
915	#else
916	return false;
917	#endif /* VBOX */
918	irrv = get_highest_priority_int(s->irr);
919	if (irrv < 0)
920	return false;
921	ppr = apic_get_ppr(s);
922	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
923	return false;
924	#ifndef VBOX
925	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
926	#else
927	cpuSetInterrupt(dev, s);
928	return true;
929	#endif
930	}
931
932	#ifdef VBOX
933
934	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
935	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
936	{
937	int irrv, ppr;
938	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
939	if (!dev)
940	return false;
941	APICState *s = getLapic(dev);
942
943	/*
944	* All our callbacks now come from single IOAPIC, thus locking
945	* seems to be excessive now (@todo: check)
946	*/
947	irrv = get_highest_priority_int(s->irr);
948	if (irrv < 0)
949	return false;
950
951	ppr = apic_get_ppr_zero_tpr(s);
952
953	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
954	return false;
955
956	return true;
957	}
958
959	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
960	{
961	bool fIrqIsActive = false;
962	bool fIrqWasActive = false;
963
964	fIrqWasActive = apic_update_irq(dev, s);
965	s->tpr = val;
966	fIrqIsActive = apic_update_irq(dev, s);
967
968	/* If an interrupt is pending and now masked, then clear the FF flag. */
969	if (fIrqWasActive && !fIrqIsActive)
970	{
971	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
972	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
973	cpuClearInterrupt(dev, s);
974	}
975	}
976	#endif
977
978	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
979	{
980	LogFlow(("apic_set_irq vector=%x, trigger_mode=%x\n", vector_num, trigger_mode));
981	set_bit(s->irr, vector_num);
982	if (trigger_mode)
983	set_bit(s->tmr, vector_num);
984	else
985	reset_bit(s->tmr, vector_num);
986	apic_update_irq(dev, s);
987	}
988
989	static void apic_eoi(APICDeviceInfo dev, APICState s)
990	{
991	int isrv;
992	isrv = get_highest_priority_int(s->isr);
993	if (isrv < 0)
994	return;
995	reset_bit(s->isr, isrv);
996	LogFlow(("apic_eoi isrv=%x\n", isrv));
997	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
998	set the remote IRR bit for level triggered interrupts. */
999	apic_update_irq(dev, s);
1000	}
1001
1002	#ifndef VBOX
1003	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1004	#else /* VBOX */
1005	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1006	#endif /* VBOX */
1007	{
1008	uint32_t mask = 0;
1009
1010	if (dest_mode == 0)
1011	{
1012	if (dest == 0xff)
1013	mask = 0xff;
1014	else
1015	mask = 1 << dest;
1016	}
1017	else
1018	{
1019	APICState *apic = LAPIC_BASE(dev);
1020	uint32_t i;
1021
1022	/* XXX: cluster mode */
1023	for(i = 0; i < dev->cCpus; i++)
1024	{
1025	if (apic->dest_mode == 0xf)
1026	{
1027	if (dest & apic->log_dest)
1028	mask \|= (1 << apic->id);
1029	}
1030	else if (apic->dest_mode == 0x0)
1031	{
1032	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1033	&&
1034	(dest & apic->log_dest & 0x0f))
1035	{
1036	mask \|= (1 << i);
1037	}
1038	}
1039	}
1040	apic++;
1041	}
1042
1043	return mask;
1044	}
1045
1046	static void apic_init_ipi(APICState *s)
1047	{
1048	int i;
1049
1050	for(i = 0; i < APIC_LVT_NB; i++)
1051	s->lvt[i] = 1 << 16; /* mask LVT */
1052	s->tpr = 0;
1053	s->spurious_vec = 0xff;
1054	s->log_dest = 0;
1055	s->dest_mode = 0xff;
1056	memset(s->isr, 0, sizeof(s->isr));
1057	memset(s->tmr, 0, sizeof(s->tmr));
1058	memset(s->irr, 0, sizeof(s->irr));
1059	s->esr = 0;
1060	memset(s->icr, 0, sizeof(s->icr));
1061	s->divide_conf = 0;
1062	s->count_shift = 0;
1063	s->initial_count = 0;
1064	s->initial_count_load_time = 0;
1065	s->next_time = 0;
1066	}
1067
1068
1069	/* send a SIPI message to the CPU to start it */
1070	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1071	{
1072	#ifndef VBOX
1073	CPUState *env = s->cpu_env;
1074	if (!env->halted)
1075	return;
1076	env->eip = 0;
1077	cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1078	0xffff, 0);
1079	env->halted = 0;
1080	#else
1081	/** @todo: init CPUs */
1082	LogRel(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->id));
1083	#endif
1084	}
1085	static void apic_deliver(APICDeviceInfo* dev, APICState *s,
1086	uint8_t dest, uint8_t dest_mode,
1087	uint8_t delivery_mode, uint8_t vector_num,
1088	uint8_t polarity, uint8_t trigger_mode)
1089	{
1090	uint32_t deliver_bitmask = 0;
1091	int dest_shorthand = (s->icr[0] >> 18) & 3;
1092	#ifndef VBOX
1093	APICState *apic_iter;
1094	#endif /* !VBOX */
1095
1096	LogFlow(("apic_deliver dest=%x dest_mode=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, delivery_mode, vector_num, polarity, trigger_mode));
1097
1098	switch (dest_shorthand) {
1099	case 0:
1100	#ifndef VBOX
1101	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1102	#else /* VBOX */
1103	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1104	#endif /* !VBOX */
1105	break;
1106	case 1:
1107	deliver_bitmask = (1 << s->id);
1108	break;
1109	case 2:
1110	deliver_bitmask = 0xffffffff;
1111	break;
1112	case 3:
1113	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1114	break;
1115	}
1116
1117	switch (delivery_mode) {
1118	case APIC_DM_LOWPRI:
1119	/* XXX: serch for focus processor, arbitration */
1120	dest = s->id;
1121
1122	case APIC_DM_INIT:
1123	{
1124	int trig_mode = (s->icr[0] >> 15) & 1;
1125	int level = (s->icr[0] >> 14) & 1;
1126	if (level == 0 && trig_mode == 1) {
1127	#ifdef VBOX
1128	foreach_apic(dev, deliver_bitmask,
1129	apic->arb_id = apic->id);
1130	#else /* !VBOX */
1131	for (apic_iter = first_local_apic; apic_iter != NULL;
1132	apic_iter = apic_iter->next_apic) {
1133	if (deliver_bitmask & (1 << apic_iter->id)) {
1134	apic_iter->arb_id = apic_iter->id;
1135	}
1136	}
1137	#endif /* !VBOX */
1138	return;
1139	}
1140	}
1141	break;
1142
1143	case APIC_DM_SIPI:
1144	#ifndef VBOX
1145	for (apic_iter = first_local_apic; apic_iter != NULL;
1146	apic_iter = apic_iter->next_apic) {
1147	if (deliver_bitmask & (1 << apic_iter->id)) {
1148	/* XXX: SMP support */
1149	/* apic_startup(apic_iter); */
1150	}
1151	}
1152	#else
1153	foreach_apic(dev, deliver_bitmask,
1154	apic_startup(dev, apic, vector_num));
1155	#endif /* !VBOX */
1156	return;
1157	}
1158
1159	#ifndef VBOX
1160	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1161	trigger_mode);
1162	#else /* VBOX */
1163	apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num, polarity,
1164	trigger_mode);
1165	#endif /* VBOX */
1166	}
1167
1168
1169	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1170	{
1171	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1172	/* if the APIC is not installed or enabled, we let the 8259 handle the
1173	IRQs */
1174	if (!dev)
1175	{
1176	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1177	return -1;
1178	}
1179
1180	APIC_LOCK(dev, VERR_INTERNAL_ERROR);
1181
1182	APICState *s = getLapic(dev);
1183	int intno;
1184
1185	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1186	Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
1187	intno = -1;
1188	goto done;
1189	}
1190
1191	/* XXX: spurious IRQ handling */
1192	intno = get_highest_priority_int(s->irr);
1193	if (intno < 0) {
1194	Log(("apic_get_interrupt: returns -1 (irr)\n"));
1195	intno = -1;
1196	goto done;
1197	}
1198	if (s->tpr && (uint32_t)intno <= s->tpr) {
1199	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1200	intno = s->spurious_vec & 0xff;
1201	goto done;
1202	}
1203	reset_bit(s->irr, intno);
1204	set_bit(s->isr, intno);
1205	apic_update_irq(dev, s);
1206	LogFlow(("apic_get_interrupt: returns %d\n", intno));
1207	done:
1208	APIC_UNLOCK(dev);
1209	return intno;
1210	}
1211
1212	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
1213	{
1214	int64_t d;
1215	uint32_t val;
1216	#ifndef VBOX
1217	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1218	s->count_shift;
1219	#else /* VBOX */
1220	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1221	s->count_shift;
1222	#endif /* VBOX */
1223	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1224	/* periodic */
1225	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1226	} else {
1227	if (d >= s->initial_count)
1228	val = 0;
1229	else
1230	val = s->initial_count - d;
1231	}
1232	return val;
1233	}
1234
1235	static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1236	{
1237	int64_t next_time, d;
1238
1239	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1240	d = (current_time - s->initial_count_load_time) >>
1241	s->count_shift;
1242	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1243	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1244	} else {
1245	if (d >= s->initial_count)
1246	goto no_timer;
1247	d = (uint64_t)s->initial_count + 1;
1248	}
1249	next_time = s->initial_count_load_time + (d << s->count_shift);
1250	#ifndef VBOX
1251	qemu_mod_timer(s->timer, next_time);
1252	#else
1253	TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1254	#endif
1255	s->next_time = next_time;
1256	} else {
1257	no_timer:
1258	#ifndef VBOX
1259	qemu_del_timer(s->timer);
1260	#else
1261	TMTimerStop(s->CTX_SUFF(pTimer));
1262	#endif
1263	}
1264	}
1265
1266	#ifdef IN_RING3
1267	#ifndef VBOX
1268	static void apic_timer(void *opaque)
1269	{
1270	APICState *s = opaque;
1271	#else /* VBOX */
1272	static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1273	{
1274	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1275	APICState *s = getLapic(dev);
1276
1277	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
1278	#endif /* VBOX */
1279
1280	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1281	LogFlow(("apic_timer: trigger irq\n"));
1282	apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1283	}
1284	apic_timer_update(dev, s, s->next_time);
1285
1286	#ifdef VBOX
1287	APIC_UNLOCK(dev);
1288	#endif
1289	}
1290	#endif /* IN_RING3 */
1291
1292	#ifndef VBOX
1293	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1294	{
1295	return 0;
1296	}
1297	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1298	{
1299	return 0;
1300	}
1301
1302	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1303	{
1304	}
1305
1306	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1307	{
1308	}
1309	#endif /* !VBOX */
1310
1311
1312	#ifndef VBOX
1313	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1314	{
1315	CPUState *env;
1316	APICState *s;
1317	#else /* VBOX */
1318	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1319	{
1320	#endif /* VBOX */
1321	uint32_t val;
1322	int index;
1323
1324	#ifndef VBOX
1325	env = cpu_single_env;
1326	if (!env)
1327	return 0;
1328	s = env->apic_state;
1329	#endif /* !VBOX */
1330
1331	index = (addr >> 4) & 0xff;
1332	switch(index) {
1333	case 0x02: /* id */
1334	val = s->id << 24;
1335	break;
1336	case 0x03: /* version */
1337	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1338	break;
1339	case 0x08:
1340	val = s->tpr;
1341	break;
1342	case 0x09:
1343	val = apic_get_arb_pri(s);
1344	break;
1345	case 0x0a:
1346	/* ppr */
1347	val = apic_get_ppr(s);
1348	break;
1349	case 0x0b:
1350	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1351	val = 0;
1352	break;
1353	case 0x0d:
1354	val = s->log_dest << 24;
1355	break;
1356	case 0x0e:
1357	#ifdef VBOX
1358	/* Bottom 28 bits are always 1 */
1359	val = (s->dest_mode << 28) \| 0xfffffff;
1360	#else
1361	val = s->dest_mode << 28;
1362	#endif
1363	break;
1364	case 0x0f:
1365	val = s->spurious_vec;
1366	break;
1367	#ifndef VBOX
1368	case 0x10 ... 0x17:
1369	#else /* VBOX */
1370	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1371	#endif /* VBOX */
1372	val = s->isr[index & 7];
1373	break;
1374	#ifndef VBOX
1375	case 0x18 ... 0x1f:
1376	#else /* VBOX */
1377	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1378	#endif /* VBOX */
1379	val = s->tmr[index & 7];
1380	break;
1381	#ifndef VBOX
1382	case 0x20 ... 0x27:
1383	#else /* VBOX */
1384	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1385	#endif /* VBOX */
1386	val = s->irr[index & 7];
1387	break;
1388	case 0x28:
1389	val = s->esr;
1390	break;
1391	case 0x30:
1392	case 0x31:
1393	val = s->icr[index & 1];
1394	break;
1395	#ifndef VBOX
1396	case 0x32 ... 0x37:
1397	#else /* VBOX */
1398	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1399	#endif /* VBOX */
1400	val = s->lvt[index - 0x32];
1401	break;
1402	case 0x38:
1403	val = s->initial_count;
1404	break;
1405	case 0x39:
1406	val = apic_get_current_count(dev, s);
1407	break;
1408	case 0x3e:
1409	val = s->divide_conf;
1410	break;
1411	default:
1412	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1413	s->esr \|= ESR_ILLEGAL_ADDRESS;
1414	val = 0;
1415	break;
1416	}
1417	#ifdef DEBUG_APIC
1418	Log(("APIC read: %08x = %08x\n", (uint32_t)addr, val));
1419	#endif
1420	return val;
1421	}
1422
1423	#ifndef VBOX
1424	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1425	{
1426	CPUState *env;
1427	APICState *s;
1428	#else /* VBOX */
1429	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1430	{
1431	#endif /* VBOX */
1432	int index;
1433
1434	#ifndef VBOX
1435	env = cpu_single_env;
1436	if (!env)
1437	return;
1438	s = env->apic_state;
1439	#endif /* !VBOX */
1440
1441	#ifdef DEBUG_APIC
1442	Log(("APIC write: %08x = %08x\n", (uint32_t)addr, val));
1443	#endif
1444
1445	index = (addr >> 4) & 0xff;
1446	switch(index) {
1447	case 0x02:
1448	s->id = (val >> 24);
1449	break;
1450	case 0x03:
1451	Log(("apic_mem_writel: write to version register; ignored\n"));
1452	break;
1453	case 0x08:
1454	#ifdef VBOX
1455	apic_update_tpr(dev, s, val);
1456	#else
1457	s->tpr = val;
1458	apic_update_irq(s);
1459	#endif
1460	break;
1461	case 0x09:
1462	case 0x0a:
1463	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1464	break;
1465	case 0x0b: /* EOI */
1466	apic_eoi(dev, s);
1467	break;
1468	case 0x0d:
1469	s->log_dest = val >> 24;
1470	break;
1471	case 0x0e:
1472	s->dest_mode = val >> 28;
1473	break;
1474	case 0x0f:
1475	s->spurious_vec = val & 0x1ff;
1476	apic_update_irq(dev, s);
1477	break;
1478	#ifndef VBOX
1479	case 0x10 ... 0x17:
1480	case 0x18 ... 0x1f:
1481	case 0x20 ... 0x27:
1482	case 0x28:
1483	#else
1484	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1485	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1486	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1487	case 0x28:
1488	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1489	#endif
1490	break;
1491
1492	case 0x30:
1493	s->icr[0] = val;
1494	apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
1495	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1496	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1497	break;
1498	case 0x31:
1499	s->icr[1] = val;
1500	break;
1501	#ifndef VBOX
1502	case 0x32 ... 0x37:
1503	#else /* VBOX */
1504	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1505	#endif /* VBOX */
1506	{
1507	int n = index - 0x32;
1508	s->lvt[n] = val;
1509	if (n == APIC_LVT_TIMER)
1510	#ifndef VBOX
1511	apic_timer_update(s, qemu_get_clock(vm_clock));
1512	#else /* VBOX */
1513	apic_timer_update(dev, s, TMTimerGet(s->CTX_SUFF(pTimer)));
1514	#endif /* VBOX*/
1515	}
1516	break;
1517	case 0x38:
1518	s->initial_count = val;
1519	#ifndef VBOX
1520	s->initial_count_load_time = qemu_get_clock(vm_clock);
1521	#else /* VBOX */
1522	s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
1523	#endif /* VBOX*/
1524	apic_timer_update(dev, s, s->initial_count_load_time);
1525	break;
1526	case 0x39:
1527	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1528	break;
1529	case 0x3e:
1530	{
1531	int v;
1532	s->divide_conf = val & 0xb;
1533	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1534	s->count_shift = (v + 1) & 7;
1535	}
1536	break;
1537	default:
1538	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1539	s->esr \|= ESR_ILLEGAL_ADDRESS;
1540	break;
1541	}
1542	#ifdef VBOX
1543	return VINF_SUCCESS;
1544	#endif
1545	}
1546
1547	#ifdef IN_RING3
1548
1549	static void apic_save(QEMUFile f, void opaque)
1550	{
1551	APICState s = (APICState)opaque;
1552	int i;
1553
1554	qemu_put_be32s(f, &s->apicbase);
1555	#ifdef VBOX
1556	qemu_put_be32s(f, &s->id);
1557	qemu_put_be32s(f, &s->phys_id);
1558	qemu_put_be32s(f, &s->arb_id);
1559	qemu_put_be32s(f, &s->tpr);
1560	#else
1561	qemu_put_8s(f, &s->id);
1562	qemu_put_8s(f, &s->arb_id);
1563	qemu_put_8s(f, &s->tpr);
1564	#endif
1565	qemu_put_be32s(f, &s->spurious_vec);
1566	qemu_put_8s(f, &s->log_dest);
1567	qemu_put_8s(f, &s->dest_mode);
1568	for (i = 0; i < 8; i++) {
1569	qemu_put_be32s(f, &s->isr[i]);
1570	qemu_put_be32s(f, &s->tmr[i]);
1571	qemu_put_be32s(f, &s->irr[i]);
1572	}
1573	for (i = 0; i < APIC_LVT_NB; i++) {
1574	qemu_put_be32s(f, &s->lvt[i]);
1575	}
1576	qemu_put_be32s(f, &s->esr);
1577	qemu_put_be32s(f, &s->icr[0]);
1578	qemu_put_be32s(f, &s->icr[1]);
1579	qemu_put_be32s(f, &s->divide_conf);
1580	qemu_put_be32s(f, &s->count_shift);
1581	qemu_put_be32s(f, &s->initial_count);
1582	qemu_put_be64s(f, &s->initial_count_load_time);
1583	qemu_put_be64s(f, &s->next_time);
1584
1585	#ifdef VBOX
1586	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1587	#endif
1588	}
1589
1590	static int apic_load(QEMUFile f, void opaque, int version_id)
1591	{
1592	APICState s = (APICState)opaque;
1593	int i;
1594
1595	#ifdef VBOX
1596	if ((version_id < 1) \|\| (version_id > 2))
1597	return -EINVAL;
1598
1599	/* XXX: what if the base changes? (registered memory regions) */
1600	qemu_get_be32s(f, &s->apicbase);
1601
1602	switch (version_id)
1603	{
1604	case 1:
1605	{
1606	uint8_t val = 0;
1607	qemu_get_8s(f, &val);
1608	s->id = val;
1609	/* UP only in old saved states */
1610	s->phys_id = 0;
1611	qemu_get_8s(f, &val);
1612	s->arb_id = val;
1613	break;
1614	}
1615	case 2:
1616	qemu_get_be32s(f, &s->id);
1617	qemu_get_be32s(f, &s->phys_id);
1618	qemu_get_be32s(f, &s->arb_id);
1619	break;
1620	}
1621	qemu_get_be32s(f, &s->tpr);
1622	#else
1623	if (version_id != 1)
1624	return -EINVAL;
1625
1626	/* XXX: what if the base changes? (registered memory regions) */
1627	qemu_get_be32s(f, &s->apicbase);
1628	qemu_get_8s(f, &s->id);
1629	qemu_get_8s(f, &s->arb_id);
1630	qemu_get_8s(f, &s->tpr);
1631	#endif
1632	qemu_get_be32s(f, &s->spurious_vec);
1633	qemu_get_8s(f, &s->log_dest);
1634	qemu_get_8s(f, &s->dest_mode);
1635	for (i = 0; i < 8; i++) {
1636	qemu_get_be32s(f, &s->isr[i]);
1637	qemu_get_be32s(f, &s->tmr[i]);
1638	qemu_get_be32s(f, &s->irr[i]);
1639	}
1640	for (i = 0; i < APIC_LVT_NB; i++) {
1641	qemu_get_be32s(f, &s->lvt[i]);
1642	}
1643	qemu_get_be32s(f, &s->esr);
1644	qemu_get_be32s(f, &s->icr[0]);
1645	qemu_get_be32s(f, &s->icr[1]);
1646	qemu_get_be32s(f, &s->divide_conf);
1647	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1648	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1649	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1650	qemu_get_be64s(f, (uint64_t *)&s->next_time);
1651
1652	#ifdef VBOX
1653	TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1654	#endif
1655
1656	return VINF_SUCCESS;
1657	}
1658	#ifndef VBOX
1659	static void apic_reset(void *opaque)
1660	{
1661	APICState s = (APICState)opaque;
1662	apic_init_ipi(s);
1663	}
1664	#endif
1665
1666	#endif /* IN_RING3 */
1667
1668	#ifndef VBOX
1669	static CPUReadMemoryFunc *apic_mem_read[3] = {
1670	apic_mem_readb,
1671	apic_mem_readw,
1672	apic_mem_readl,
1673	};
1674
1675	static CPUWriteMemoryFunc *apic_mem_write[3] = {
1676	apic_mem_writeb,
1677	apic_mem_writew,
1678	apic_mem_writel,
1679	};
1680
1681	int apic_init(CPUState *env)
1682	{
1683	APICState *s;
1684
1685	s = qemu_mallocz(sizeof(APICState));
1686	if (!s)
1687	return -1;
1688	env->apic_state = s;
1689	apic_init_ipi(s);
1690	s->id = last_apic_id++;
1691	s->cpu_env = env;
1692	s->apicbase = 0xfee00000 \|
1693	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
1694
1695	/* XXX: mapping more APICs at the same memory location */
1696	if (apic_io_memory == 0) {
1697	/* NOTE: the APIC is directly connected to the CPU - it is not
1698	on the global memory bus. */
1699	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1700	apic_mem_write, NULL);
1701	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1702	apic_io_memory);
1703	}
1704	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1705
1706	register_savevm("apic", 0, 1, apic_save, apic_load, s);
1707	qemu_register_reset(apic_reset, s);
1708
1709	s->next_apic = first_local_apic;
1710	first_local_apic = s;
1711
1712	return 0;
1713	}
1714	#endif /* !VBOX */
1715
1716	static void ioapic_service(IOAPICState *s)
1717	{
1718	uint8_t i;
1719	uint8_t trig_mode;
1720	uint8_t vector;
1721	uint8_t delivery_mode;
1722	uint32_t mask;
1723	uint64_t entry;
1724	uint8_t dest;
1725	uint8_t dest_mode;
1726	uint8_t polarity;
1727
1728	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1729	mask = 1 << i;
1730	if (s->irr & mask) {
1731	entry = s->ioredtbl[i];
1732	if (!(entry & APIC_LVT_MASKED)) {
1733	trig_mode = ((entry >> 15) & 1);
1734	dest = entry >> 56;
1735	dest_mode = (entry >> 11) & 1;
1736	delivery_mode = (entry >> 8) & 7;
1737	polarity = (entry >> 13) & 1;
1738	if (trig_mode == APIC_TRIGGER_EDGE)
1739	s->irr &= ~mask;
1740	if (delivery_mode == APIC_DM_EXTINT)
1741	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1742	vector = pic_read_irq(isa_pic);
1743	#else /* VBOX */
1744	{
1745	AssertMsgFailed(("Delivery mode ExtINT"));
1746	vector = 0xff; /* incorrect but shuts up gcc. */
1747	}
1748	#endif /* VBOX */
1749	else
1750	vector = entry & 0xff;
1751
1752	#ifndef VBOX
1753	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1754	delivery_mode, vector, polarity, trig_mode);
1755	#else /* VBOX */
1756	s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1757	dest,
1758	dest_mode,
1759	delivery_mode,
1760	vector,
1761	polarity,
1762	trig_mode);
1763	#endif /* VBOX */
1764	}
1765	}
1766	}
1767	}
1768
1769	#ifdef VBOX
1770	static
1771	#endif
1772	void ioapic_set_irq(void *opaque, int vector, int level)
1773	{
1774	IOAPICState s = (IOAPICState)opaque;
1775
1776	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1777	uint32_t mask = 1 << vector;
1778	uint64_t entry = s->ioredtbl[vector];
1779
1780	if ((entry >> 15) & 1) {
1781	/* level triggered */
1782	if (level) {
1783	s->irr \|= mask;
1784	ioapic_service(s);
1785	#ifdef VBOX
1786	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1787	s->irr &= ~mask;
1788	}
1789	#endif
1790	} else {
1791	s->irr &= ~mask;
1792	}
1793	} else {
1794	/* edge triggered */
1795	if (level) {
1796	s->irr \|= mask;
1797	ioapic_service(s);
1798	}
1799	}
1800	}
1801	}
1802
1803	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1804	{
1805	IOAPICState s = (IOAPICState)opaque;
1806	int index;
1807	uint32_t val = 0;
1808
1809	addr &= 0xff;
1810	if (addr == 0x00) {
1811	val = s->ioregsel;
1812	} else if (addr == 0x10) {
1813	switch (s->ioregsel) {
1814	case 0x00:
1815	val = s->id << 24;
1816	break;
1817	case 0x01:
1818	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1819	break;
1820	case 0x02:
1821	val = 0;
1822	break;
1823	default:
1824	index = (s->ioregsel - 0x10) >> 1;
1825	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1826	if (s->ioregsel & 1)
1827	val = s->ioredtbl[index] >> 32;
1828	else
1829	val = s->ioredtbl[index] & 0xffffffff;
1830	}
1831	}
1832	#ifdef DEBUG_IOAPIC
1833	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1834	#endif
1835	}
1836	return val;
1837	}
1838
1839	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1840	{
1841	IOAPICState s = (IOAPICState)opaque;
1842	int index;
1843
1844	addr &= 0xff;
1845	if (addr == 0x00) {
1846	s->ioregsel = val;
1847	return;
1848	} else if (addr == 0x10) {
1849	#ifdef DEBUG_IOAPIC
1850	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1851	#endif
1852	switch (s->ioregsel) {
1853	case 0x00:
1854	s->id = (val >> 24) & 0xff;
1855	return;
1856	case 0x01:
1857	case 0x02:
1858	return;
1859	default:
1860	index = (s->ioregsel - 0x10) >> 1;
1861	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1862	if (s->ioregsel & 1) {
1863	s->ioredtbl[index] &= 0xffffffff;
1864	s->ioredtbl[index] \|= (uint64_t)val << 32;
1865	} else {
1866	#ifdef VBOX
1867	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1868	uint8_t vec = val & 0xff;
1869	if ((val & APIC_LVT_MASKED) \|\|
1870	((vec >= 0x10) && (vec < 0xff)))
1871	{
1872	s->ioredtbl[index] &= ~0xffffffffULL;
1873	s->ioredtbl[index] \|= val;
1874	}
1875	else
1876	{
1877	/*
1878	* Linux 2.6 kernels has pretty strange function
1879	* unlock_ExtINT_logic() which writes
1880	* absolutely bogus (all 0) value into the vector
1881	* with pretty vague explanation why.
1882	* So we just ignore such writes.
1883	*/
1884	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1885	}
1886	}
1887	#else
1888	s->ioredtbl[index] &= ~0xffffffffULL;
1889	s->ioredtbl[index] \|= val;
1890	#endif
1891	ioapic_service(s);
1892	}
1893	}
1894	}
1895	}
1896
1897	#ifdef IN_RING3
1898
1899	static void ioapic_save(QEMUFile f, void opaque)
1900	{
1901	IOAPICState s = (IOAPICState)opaque;
1902	int i;
1903
1904	qemu_put_8s(f, &s->id);
1905	qemu_put_8s(f, &s->ioregsel);
1906	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1907	qemu_put_be64s(f, &s->ioredtbl[i]);
1908	}
1909	}
1910
1911	static int ioapic_load(QEMUFile f, void opaque, int version_id)
1912	{
1913	IOAPICState s = (IOAPICState)opaque;
1914	int i;
1915
1916	if (version_id != 1)
1917	return -EINVAL;
1918
1919	qemu_get_8s(f, &s->id);
1920	qemu_get_8s(f, &s->ioregsel);
1921	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1922	qemu_get_be64s(f, &s->ioredtbl[i]);
1923	}
1924	return 0;
1925	}
1926
1927	static void ioapic_reset(void *opaque)
1928	{
1929	IOAPICState s = (IOAPICState)opaque;
1930	#ifdef VBOX
1931	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1932	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1933	#endif
1934	int i;
1935
1936	memset(s, 0, sizeof(*s));
1937	for(i = 0; i < IOAPIC_NUM_PINS; i++)
1938	s->ioredtbl[i] = 1 << 16; /* mask LVT */
1939
1940	#ifdef VBOX
1941	if (pDevIns)
1942	{
1943	s->pDevInsR3 = pDevIns;
1944	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1945	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1946	}
1947	if (pIoApicHlp)
1948	{
1949	s->pIoApicHlpR3 = pIoApicHlp;
1950	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1951	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1952	}
1953	#endif
1954	}
1955
1956	#endif /* IN_RING3 */
1957
1958	#ifndef VBOX
1959	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1960	ioapic_mem_readl,
1961	ioapic_mem_readl,
1962	ioapic_mem_readl,
1963	};
1964
1965	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1966	ioapic_mem_writel,
1967	ioapic_mem_writel,
1968	ioapic_mem_writel,
1969	};
1970
1971	IOAPICState *ioapic_init(void)
1972	{
1973	IOAPICState *s;
1974	int io_memory;
1975
1976	s = qemu_mallocz(sizeof(IOAPICState));
1977	if (!s)
1978	return NULL;
1979	ioapic_reset(s);
1980	s->id = last_apic_id++;
1981
1982	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1983	ioapic_mem_write, s);
1984	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1985
1986	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1987	qemu_register_reset(ioapic_reset, s);
1988
1989	return s;
1990	}
1991	#endif /* !VBOX */
1992
1993	/* LAPIC */
1994	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1995	{
1996	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1997	APICState *s = getLapic(dev);
1998
1999	#ifdef VBOX_WITH_SMP_GUESTS
2000	LogRel(("[SMP] apicMMIORead at %llx\n", (uint64_t)GCPhysAddr));
2001	#endif
2002
2003	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2004	different physical addresses, see #3092) */
2005
2006	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2007	switch (cb)
2008	{
2009	case 1:
2010	(uint8_t )pv = 0;
2011	break;
2012
2013	case 2:
2014	(uint16_t )pv = 0;
2015	break;
2016
2017	case 4:
2018	{
2019	#if 0 /** @note experimental */
2020	#ifndef IN_RING3
2021	uint32_t index = (GCPhysAddr >> 4) & 0xff;
2022
2023	if ( index == 0x08 /* TPR */
2024	&& ++s->ulTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2025	{
2026	#ifdef IN_RC
2027	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2028	#else
2029	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2030	pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2031	#endif
2032	return VINF_PATM_HC_MMIO_PATCH_READ;
2033	}
2034	#endif
2035	#endif /* experimental */
2036	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2037	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
2038	APIC_UNLOCK(dev);
2039	break;
2040	}
2041	default:
2042	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2043	return VERR_INTERNAL_ERROR;
2044	}
2045	return VINF_SUCCESS;
2046	}
2047
2048	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2049	{
2050	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2051	APICState *s = getLapic(dev);
2052
2053	#ifdef VBOX_WITH_SMP_GUESTS
2054	LogRel(("[SMP] apicMMIOWrite at %llx\n", (uint64_t)GCPhysAddr));
2055	#endif
2056
2057	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2058	different physical addresses, see #3092) */
2059
2060	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2061	switch (cb)
2062	{
2063	case 1:
2064	case 2:
2065	/* ignore */
2066	break;
2067
2068	case 4:
2069	{
2070	int rc;
2071	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2072	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2073	APIC_UNLOCK(dev);
2074	return rc;
2075	}
2076
2077	default:
2078	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2079	return VERR_INTERNAL_ERROR;
2080	}
2081	return VINF_SUCCESS;
2082	}
2083
2084	#ifdef IN_RING3
2085
2086	/**
2087	* @copydoc FNSSMDEVSAVEEXEC
2088	*/
2089	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2090	{
2091	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2092
2093	/* save all APICs data, @todo: is it correct? */
2094	foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
2095
2096	return VINF_SUCCESS;
2097	}
2098
2099	/**
2100	* @copydoc FNSSMDEVLOADEXEC
2101	*/
2102	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2103	{
2104	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2105	/* load all APICs data, @todo: is it correct? */
2106	foreach_apic(dev, 0xffffffff,
2107	if (apic_load(pSSMHandle, apic, u32Version))
2108	{
2109	AssertFailed();
2110	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2111	}
2112	);
2113	return VINF_SUCCESS;
2114	}
2115
2116	/**
2117	* @copydoc FNPDMDEVRESET
2118	*/
2119	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2120	{
2121	APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2122	APICState *s = getLapic(dev);
2123
2124	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2125
2126	TMTimerStop(s->CTX_SUFF(pTimer));
2127
2128	apic_init_ipi(s);
2129	/* malc, I've removed the initing duplicated in apic_init_ipi(). This
2130	* arb_id was left over.. */
2131	s->arb_id = 0;
2132	/* Reset should re-enable the APIC. */
2133	s->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_ENABLE;
2134	if (s->phys_id == 0)
2135	s->apicbase \|= MSR_IA32_APICBASE_BSP;
2136	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2137	/* Clear any pending APIC interrupt action flag. */
2138	cpuClearInterrupt(dev, s);
2139	APIC_UNLOCK(dev);
2140	}
2141
2142	/**
2143	* @copydoc FNPDMDEVRELOCATE
2144	*/
2145	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2146	{
2147	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2148	#ifdef VBOX_WITH_SMP_GUESTS
2149	LogRel(("[SMP]: relocate apic on %llx\n", offDelta));
2150	#endif
2151	dev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2152	dev->pApicHlpRC = dev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2153	dev->pLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), dev->pLapicsR3);
2154	foreach_apic(dev, 0xffffffff,
2155	apic->pTimerRC = TMTimerRCPtr(apic->CTX_SUFF(pTimer)));
2156	}
2157
2158	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2159	{
2160	int i;
2161	memset(apic, 0, sizeof(*apic));
2162	apic->apicbase = UINT32_C(0xfee00000) \| MSR_IA32_APICBASE_ENABLE;
2163	/* Mark first CPU as BSP */
2164	if (id == 0)
2165	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2166	for (i = 0; i < APIC_LVT_NB; i++)
2167	apic->lvt[i] = 1 << 16; /* mask LVT */
2168	apic->spurious_vec = 0xff;
2169	apic->phys_id = apic->id = id;
2170	}
2171
2172	/**
2173	* @copydoc FNPDMDEVCONSTRUCT
2174	*/
2175	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2176	{
2177	PDMAPICREG ApicReg;
2178	int rc;
2179	uint32_t i;
2180	bool fIOAPIC;
2181	bool fGCEnabled;
2182	bool fR0Enabled;
2183	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2184	uint32_t cCpus;
2185	APICState *apic;
2186
2187	/*
2188	* Only single device instance.
2189	*/
2190	Assert(iInstance == 0);
2191
2192	/*
2193	* Validate configuration.
2194	*/
2195	if (!CFGMR3AreValuesValid(pCfgHandle,
2196	"IOAPIC\0"
2197	"GCEnabled\0"
2198	"R0Enabled\0"
2199	"NumCPUs\0"))
2200	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2201
2202	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIOAPIC, true);
2203	if (RT_FAILURE(rc))
2204	return PDMDEV_SET_ERROR(pDevIns, rc,
2205	N_("Configuration error: Failed to read \"IOAPIC\""));
2206
2207	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2208	if (RT_FAILURE(rc))
2209	return PDMDEV_SET_ERROR(pDevIns, rc,
2210	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2211
2212	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2213	if (RT_FAILURE(rc))
2214	return PDMDEV_SET_ERROR(pDevIns, rc,
2215	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2216
2217	rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2218	if (RT_FAILURE(rc))
2219	return PDMDEV_SET_ERROR(pDevIns, rc,
2220	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2221
2222	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
2223
2224	/*
2225	* Init the data.
2226	*/
2227	pThis->pDevInsR3 = pDevIns;
2228	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2229	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2230	pThis->cCpus = cCpus;
2231	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2232	pThis->enmVersion = PDMAPICVERSION_APIC;
2233
2234	PVM pVM = PDMDevHlpGetVM(pDevIns);
2235	/*
2236	* We are not freeing this memory, as it's automatically released when guest exits.
2237	*/
2238	rc = MMHyperAlloc(pVM, cCpussizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void *)&pThis->pLapicsR3);
2239	if (RT_FAILURE(rc))
2240	return VERR_NO_MEMORY;
2241	pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
2242	pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
2243
2244	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2245	{
2246	initApicData(apic, i);
2247	apic++;
2248	}
2249
2250	/*
2251	* Register the APIC.
2252	*/
2253	ApicReg.u32Version = PDM_APICREG_VERSION;
2254	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2255	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2256	ApicReg.pfnSetBaseR3 = apicSetBase;
2257	ApicReg.pfnGetBaseR3 = apicGetBase;
2258	ApicReg.pfnSetTPRR3 = apicSetTPR;
2259	ApicReg.pfnGetTPRR3 = apicGetTPR;
2260	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2261	ApicReg.pfnReadMSRR3 = apicReadMSR;
2262	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2263	if (fGCEnabled) {
2264	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2265	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2266	ApicReg.pszSetBaseRC = "apicSetBase";
2267	ApicReg.pszGetBaseRC = "apicGetBase";
2268	ApicReg.pszSetTPRRC = "apicSetTPR";
2269	ApicReg.pszGetTPRRC = "apicGetTPR";
2270	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2271	ApicReg.pszReadMSRRC = "apicReadMSR";
2272	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2273	} else {
2274	ApicReg.pszGetInterruptRC = NULL;
2275	ApicReg.pszHasPendingIrqRC = NULL;
2276	ApicReg.pszSetBaseRC = NULL;
2277	ApicReg.pszGetBaseRC = NULL;
2278	ApicReg.pszSetTPRRC = NULL;
2279	ApicReg.pszGetTPRRC = NULL;
2280	ApicReg.pszWriteMSRRC = NULL;
2281	ApicReg.pszReadMSRRC = NULL;
2282	ApicReg.pszBusDeliverRC = NULL;
2283	}
2284	if (fR0Enabled) {
2285	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2286	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2287	ApicReg.pszSetBaseR0 = "apicSetBase";
2288	ApicReg.pszGetBaseR0 = "apicGetBase";
2289	ApicReg.pszSetTPRR0 = "apicSetTPR";
2290	ApicReg.pszGetTPRR0 = "apicGetTPR";
2291	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2292	ApicReg.pszReadMSRR0 = "apicReadMSR";
2293	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2294	} else {
2295	ApicReg.pszGetInterruptR0 = NULL;
2296	ApicReg.pszHasPendingIrqR0 = NULL;
2297	ApicReg.pszSetBaseR0 = NULL;
2298	ApicReg.pszGetBaseR0 = NULL;
2299	ApicReg.pszSetTPRR0 = NULL;
2300	ApicReg.pszGetTPRR0 = NULL;
2301	ApicReg.pszWriteMSRR0 = NULL;
2302	ApicReg.pszReadMSRR0 = NULL;
2303	ApicReg.pszBusDeliverR0 = NULL;
2304	}
2305
2306	Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2307	rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2308	if (RT_FAILURE(rc))
2309	{
2310	AssertLogRelMsgFailed(("APICRegister -> %Rrc\n", rc));
2311	return rc;
2312	}
2313
2314	/*
2315	* The the CPUID feature bit.
2316	*/
2317	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2318	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2319	if (u32Eax >= 1)
2320	{
2321	if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
2322	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2323	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2324	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2325	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2326	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2327	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2328	{
2329	LogRel(("Activating Local APIC\n"));
2330	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2331	}
2332	}
2333
2334	/*
2335	* Register the MMIO range.
2336	* @todo: may need to rethink for cases when different LAPICs mapped to different address
2337	* (see IA32_APIC_BASE_MSR)
2338	*/
2339	rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
2340	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2341	if (RT_FAILURE(rc))
2342	return rc;
2343
2344	if (fGCEnabled) {
2345	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2346
2347	rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2348	"apicMMIOWrite", "apicMMIORead", NULL);
2349	if (RT_FAILURE(rc))
2350	return rc;
2351	}
2352
2353	if (fR0Enabled) {
2354	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2355
2356	rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2357	"apicMMIOWrite", "apicMMIORead", NULL);
2358	if (RT_FAILURE(rc))
2359	return rc;
2360	}
2361
2362	/*
2363	* Create the APIC timers.
2364	*/
2365	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2366	{
2367	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer,
2368	"APIC Timer", &apic->pTimerR3);
2369	if (RT_FAILURE(rc))
2370	return rc;
2371	apic->pTimerR0 = TMTimerR0Ptr(apic->pTimerR3);
2372	apic->pTimerRC = TMTimerRCPtr(apic->pTimerR3);
2373	apic++;
2374	}
2375
2376	/*
2377	* Saved state.
2378	*/
2379	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
2380	sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
2381	if (RT_FAILURE(rc))
2382	return rc;
2383
2384	#ifdef VBOX_WITH_STATISTICS
2385	/*
2386	* Statistics.
2387	*/
2388	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2389	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2390	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2391	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2392	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq, STAMTYPE_COUNTER, "/PDM/APIC/Masked/ActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2393	#endif
2394
2395	return VINF_SUCCESS;
2396	}
2397
2398
2399	/**
2400	* APIC device registration structure.
2401	*/
2402	const PDMDEVREG g_DeviceAPIC =
2403	{
2404	/* u32Version */
2405	PDM_DEVREG_VERSION,
2406	/* szDeviceName */
2407	"apic",
2408	/* szRCMod */
2409	"VBoxDD2GC.gc",
2410	/* szR0Mod */
2411	"VBoxDD2R0.r0",
2412	/* pszDescription */
2413	"Advanced Programmable Interrupt Controller (APIC) Device",
2414	/* fFlags */
2415	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2416	/* fClass */
2417	PDM_DEVREG_CLASS_PIC,
2418	/* cMaxInstances */
2419	1,
2420	/* cbInstance */
2421	sizeof(APICState),
2422	/* pfnConstruct */
2423	apicConstruct,
2424	/* pfnDestruct */
2425	NULL,
2426	/* pfnRelocate */
2427	apicRelocate,
2428	/* pfnIOCtl */
2429	NULL,
2430	/* pfnPowerOn */
2431	NULL,
2432	/* pfnReset */
2433	apicReset,
2434	/* pfnSuspend */
2435	NULL,
2436	/* pfnResume */
2437	NULL,
2438	/* pfnAttach */
2439	NULL,
2440	/* pfnDetach */
2441	NULL,
2442	/* pfnQueryInterface. */
2443	NULL,
2444	/* pfnInitComplete */
2445	NULL,
2446	/* pfnPowerOff */
2447	NULL,
2448	/* pfnSoftReset */
2449	NULL,
2450	/* u32VersionEnd */
2451	PDM_DEVREG_VERSION
2452	};
2453
2454	#endif /* IN_RING3 */
2455
2456
2457	/* IOAPIC */
2458
2459	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2460	{
2461	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2462	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2463
2464	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2465	switch (cb)
2466	{
2467	case 1:
2468	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2469	break;
2470
2471	case 2:
2472	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2473	break;
2474
2475	case 4:
2476	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2477	break;
2478
2479	default:
2480	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2481	IOAPIC_UNLOCK(s);
2482	return VERR_INTERNAL_ERROR;
2483	}
2484	IOAPIC_UNLOCK(s);
2485	return VINF_SUCCESS;
2486	}
2487
2488	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2489	{
2490	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2491
2492	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2493	switch (cb)
2494	{
2495	case 1:
2496	case 2:
2497	case 4:
2498	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2499	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
2500	IOAPIC_UNLOCK(s);
2501	break;
2502
2503	default:
2504	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2505	return VERR_INTERNAL_ERROR;
2506	}
2507	return VINF_SUCCESS;
2508	}
2509
2510	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2511	{
2512	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
2513	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2514	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2515	ioapic_set_irq(pThis, iIrq, iLevel);
2516	}
2517
2518
2519	#ifdef IN_RING3
2520
2521	/**
2522	* @copydoc FNSSMDEVSAVEEXEC
2523	*/
2524	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2525	{
2526	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2527	ioapic_save(pSSMHandle, s);
2528	return VINF_SUCCESS;
2529	}
2530
2531	/**
2532	* @copydoc FNSSMDEVLOADEXEC
2533	*/
2534	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2535	{
2536	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2537
2538	if (ioapic_load(pSSMHandle, s, u32Version)) {
2539	AssertFailed();
2540	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2541	}
2542
2543	return VINF_SUCCESS;
2544	}
2545
2546	/**
2547	* @copydoc FNPDMDEVRESET
2548	*/
2549	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2550	{
2551	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2552	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2553	ioapic_reset(s);
2554	IOAPIC_UNLOCK(s);
2555	}
2556
2557	/**
2558	* @copydoc FNPDMDEVRELOCATE
2559	*/
2560	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2561	{
2562	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2563	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2564	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2565	}
2566
2567	/**
2568	* @copydoc FNPDMDEVCONSTRUCT
2569	*/
2570	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2571	{
2572	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2573	PDMIOAPICREG IoApicReg;
2574	bool fGCEnabled;
2575	bool fR0Enabled;
2576	int rc;
2577
2578	Assert(iInstance == 0);
2579
2580	/*
2581	* Validate and read the configuration.
2582	*/
2583	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2584	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2585
2586	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2587	if (RT_FAILURE(rc))
2588	return PDMDEV_SET_ERROR(pDevIns, rc,
2589	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2590
2591	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2592	if (RT_FAILURE(rc))
2593	return PDMDEV_SET_ERROR(pDevIns, rc,
2594	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2595	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2596
2597	/*
2598	* Initialize the state data.
2599	*/
2600	s->pDevInsR3 = pDevIns;
2601	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2602	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2603	ioapic_reset(s);
2604	s->id = 0;
2605
2606	/*
2607	* Register the IOAPIC and get helpers.
2608	*/
2609	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2610	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2611	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2612	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2613	rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2614	if (RT_FAILURE(rc))
2615	{
2616	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2617	return rc;
2618	}
2619
2620	/*
2621	* Register MMIO callbacks and saved state.
2622	*/
2623	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2624	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2625	if (RT_FAILURE(rc))
2626	return rc;
2627
2628	if (fGCEnabled) {
2629	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2630
2631	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2632	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2633	if (RT_FAILURE(rc))
2634	return rc;
2635	}
2636
2637	if (fR0Enabled) {
2638	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2639
2640	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2641	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2642	if (RT_FAILURE(rc))
2643	return rc;
2644	}
2645
2646	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2647	sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2648	if (RT_FAILURE(rc))
2649	return rc;
2650
2651	#ifdef VBOX_WITH_STATISTICS
2652	/*
2653	* Statistics.
2654	*/
2655	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2656	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2657	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2658	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2659	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2660	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2661	#endif
2662
2663	return VINF_SUCCESS;
2664	}
2665
2666	/**
2667	* IO APIC device registration structure.
2668	*/
2669	const PDMDEVREG g_DeviceIOAPIC =
2670	{
2671	/* u32Version */
2672	PDM_DEVREG_VERSION,
2673	/* szDeviceName */
2674	"ioapic",
2675	/* szRCMod */
2676	"VBoxDD2GC.gc",
2677	/* szR0Mod */
2678	"VBoxDD2R0.r0",
2679	/* pszDescription */
2680	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2681	/* fFlags */
2682	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2683	/* fClass */
2684	PDM_DEVREG_CLASS_PIC,
2685	/* cMaxInstances */
2686	1,
2687	/* cbInstance */
2688	sizeof(IOAPICState),
2689	/* pfnConstruct */
2690	ioapicConstruct,
2691	/* pfnDestruct */
2692	NULL,
2693	/* pfnRelocate */
2694	ioapicRelocate,
2695	/* pfnIOCtl */
2696	NULL,
2697	/* pfnPowerOn */
2698	NULL,
2699	/* pfnReset */
2700	ioapicReset,
2701	/* pfnSuspend */
2702	NULL,
2703	/* pfnResume */
2704	NULL,
2705	/* pfnAttach */
2706	NULL,
2707	/* pfnDetach */
2708	NULL,
2709	/* pfnQueryInterface. */
2710	NULL,
2711	/* pfnInitComplete */
2712	NULL,
2713	/* pfnPowerOff */
2714	NULL,
2715	/* pfnSoftReset */
2716	NULL,
2717	/* u32VersionEnd */
2718	PDM_DEVREG_VERSION
2719	};
2720
2721	#endif /* IN_RING3 */
2722	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2723

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 18664

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