VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 19443

Last change on this file since 19443 was 19443, checked in by vboxsync, 16 years ago

Notes about missing functionality
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File size: 80.8 KB
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1#ifdef VBOX
2/* $Id: DevAPIC.cpp 19443 2009-05-06 15:58:01Z vboxsync $ */
3/** @file
4 * Advanced Programmable Interrupt Controller (APIC) Device and
5 * I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6 */
7
8/*
9 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20 * Clara, CA 95054 USA or visit http://www.sun.com if you need
21 * additional information or have any questions.
22 * --------------------------------------------------------------------
23 *
24 * This code is based on:
25 *
26 * apic.c revision 1.5 @@OSETODO
27 */
28
29/*******************************************************************************
30* Header Files *
31*******************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/pdmdev.h>
34
35#include <VBox/log.h>
36#include <VBox/stam.h>
37#include <iprt/assert.h>
38#include <iprt/asm.h>
39
40#include "Builtins2.h"
41#include "vl_vbox.h"
42
43#define MSR_IA32_APICBASE 0x1b
44#define MSR_IA32_APICBASE_BSP (1<<8)
45#define MSR_IA32_APICBASE_ENABLE (1<<11)
46#ifdef VBOX
47#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48#endif
49#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51#ifndef EINVAL
52# define EINVAL 1
53#endif
54
55#ifdef _MSC_VER
56# pragma warning(disable:4244)
57#endif
58
59/** @def APIC_LOCK
60 * Acquires the PDM lock. */
61#define APIC_LOCK(pThis, rc) \
62 do { \
63 int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
64 if (rc2 != VINF_SUCCESS) \
65 return rc2; \
66 } while (0)
67
68/** @def APIC_LOCK_VOID
69 * Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
70#define APIC_LOCK_VOID(pThis, rc) \
71 do { \
72 int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
73 AssertLogRelRCReturnVoid(rc2); \
74 } while (0)
75
76/** @def APIC_UNLOCK
77 * Releases the PDM lock. */
78#define APIC_UNLOCK(pThis) \
79 (pThis)->CTX_SUFF(pApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
80
81/** @def IOAPIC_LOCK
82 * Acquires the PDM lock. */
83#define IOAPIC_LOCK(pThis, rc) \
84 do { \
85 int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
86 if (rc2 != VINF_SUCCESS) \
87 return rc2; \
88 } while (0)
89
90/** @def IOAPIC_UNLOCK
91 * Releases the PDM lock. */
92#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
93
94/** @def LAPIC_BASE
95 * Return address of first LAPIC state. */
96#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
97
98#define foreach_apic(dev, mask, code) \
99 do { \
100 uint32_t i; \
101 APICState* apic = LAPIC_BASE(dev); \
102 for (i = 0; i < dev->cCpus; i++) \
103 { \
104 if (mask & (1 << (apic->id))) \
105 { \
106 code; \
107 } \
108 apic++; \
109 } \
110 } while (0)
111
112# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
113# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
114# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
115# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
116
117#endif /* VBOX */
118
119/*
120 * APIC support
121 *
122 * Copyright (c) 2004-2005 Fabrice Bellard
123 *
124 * This library is free software; you can redistribute it and/or
125 * modify it under the terms of the GNU Lesser General Public
126 * License as published by the Free Software Foundation; either
127 * version 2 of the License, or (at your option) any later version.
128 *
129 * This library is distributed in the hope that it will be useful,
130 * but WITHOUT ANY WARRANTY; without even the implied warranty of
131 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
132 * Lesser General Public License for more details.
133 *
134 * You should have received a copy of the GNU Lesser General Public
135 * License along with this library; if not, write to the Free Software
136 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
137 */
138#ifndef VBOX
139#include "vl.h"
140#endif
141
142#define DEBUG_APIC
143#define DEBUG_IOAPIC
144
145/* APIC Local Vector Table */
146#define APIC_LVT_TIMER 0
147#define APIC_LVT_THERMAL 1
148#define APIC_LVT_PERFORM 2
149#define APIC_LVT_LINT0 3
150#define APIC_LVT_LINT1 4
151#define APIC_LVT_ERROR 5
152#define APIC_LVT_NB 6
153
154/* APIC delivery modes */
155#define APIC_DM_FIXED 0
156#define APIC_DM_LOWPRI 1
157#define APIC_DM_SMI 2
158#define APIC_DM_NMI 4
159#define APIC_DM_INIT 5
160#define APIC_DM_SIPI 6
161#define APIC_DM_EXTINT 7
162
163/* APIC destination mode */
164#define APIC_DESTMODE_FLAT 0xf
165#define APIC_DESTMODE_CLUSTER 1
166
167#define APIC_TRIGGER_EDGE 0
168#define APIC_TRIGGER_LEVEL 1
169
170#define APIC_LVT_TIMER_PERIODIC (1<<17)
171#define APIC_LVT_MASKED (1<<16)
172#define APIC_LVT_LEVEL_TRIGGER (1<<15)
173#define APIC_LVT_REMOTE_IRR (1<<14)
174#define APIC_INPUT_POLARITY (1<<13)
175#define APIC_SEND_PENDING (1<<12)
176
177#define IOAPIC_NUM_PINS 0x18
178
179#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181#define APIC_SV_ENABLE (1 << 8)
182
183#ifdef VBOX
184#define APIC_MAX_PATCH_ATTEMPTS 100
185
186typedef uint32_t PhysApicId;
187typedef uint32_t LogApicId;
188#endif
189
190typedef struct APICState {
191#ifndef VBOX
192 CPUState *cpu_env;
193#endif /* !VBOX */
194 uint32_t apicbase;
195#ifdef VBOX
196 /* Task priority register (interrupt level) */
197 uint32_t tpr;
198 /* Logical APIC id */
199 LogApicId id;
200 /* Physical APIC id */
201 PhysApicId phys_id;
202 /** @todo: is it logical or physical? Not really used anyway now. */
203 PhysApicId arb_id;
204#else
205 uint8_t tpr;
206 uint8_t id;
207 uint8_t arb_id;
208#endif
209 uint32_t spurious_vec;
210 uint8_t log_dest;
211 uint8_t dest_mode;
212 uint32_t isr[8]; /* in service register */
213 uint32_t tmr[8]; /* trigger mode register */
214 uint32_t irr[8]; /* interrupt request register */
215 uint32_t lvt[APIC_LVT_NB];
216 uint32_t esr; /* error register */
217 uint32_t icr[2];
218 uint32_t divide_conf;
219 int count_shift;
220 uint32_t initial_count;
221#ifdef VBOX
222 uint32_t Alignment0;
223#endif
224 int64_t initial_count_load_time, next_time;
225#ifndef VBOX
226 QEMUTimer *timer;
227 struct APICState *next_apic;
228#else
229 /** The APIC timer - R3 Ptr. */
230 PTMTIMERR3 pTimerR3;
231
232 /** The APIC timer - R0 Ptr. */
233 PTMTIMERR0 pTimerR0;
234
235 /** The APIC timer - RC Ptr. */
236 PTMTIMERRC pTimerRC;
237
238 /** Alignment */
239 uint32_t Alignment1;
240#endif /* VBOX */
241} APICState;
242
243struct IOAPICState {
244 uint8_t id;
245 uint8_t ioregsel;
246
247 uint32_t irr;
248 uint64_t ioredtbl[IOAPIC_NUM_PINS];
249
250#ifdef VBOX
251 /** The device instance - R3 Ptr. */
252 PPDMDEVINSR3 pDevInsR3;
253 /** The IOAPIC helpers - R3 Ptr. */
254 PCPDMIOAPICHLPR3 pIoApicHlpR3;
255
256 /** The device instance - R0 Ptr. */
257 PPDMDEVINSR0 pDevInsR0;
258 /** The IOAPIC helpers - R0 Ptr. */
259 PCPDMIOAPICHLPR0 pIoApicHlpR0;
260
261 /** The device instance - RC Ptr. */
262 PPDMDEVINSRC pDevInsRC;
263 /** The IOAPIC helpers - RC Ptr. */
264 PCPDMIOAPICHLPRC pIoApicHlpRC;
265
266# ifdef VBOX_WITH_STATISTICS
267 STAMCOUNTER StatMMIOReadGC;
268 STAMCOUNTER StatMMIOReadHC;
269 STAMCOUNTER StatMMIOWriteGC;
270 STAMCOUNTER StatMMIOWriteHC;
271 STAMCOUNTER StatSetIrqGC;
272 STAMCOUNTER StatSetIrqHC;
273# endif
274#endif /* VBOX */
275};
276
277#ifdef VBOX
278typedef struct IOAPICState IOAPICState;
279
280typedef struct
281{
282 /** The device instance - R3 Ptr. */
283 PPDMDEVINSR3 pDevInsR3;
284 /** The APIC helpers - R3 Ptr. */
285 PCPDMAPICHLPR3 pApicHlpR3;
286 /** LAPICs states - R3 Ptr */
287 RTR3PTR pLapicsR3;
288
289 /** The device instance - R0 Ptr. */
290 PPDMDEVINSR0 pDevInsR0;
291 /** The APIC helpers - R0 Ptr. */
292 PCPDMAPICHLPR0 pApicHlpR0;
293 /** LAPICs states - R0 Ptr */
294 RTR0PTR pLapicsR0;
295
296 /** The device instance - RC Ptr. */
297 PPDMDEVINSRC pDevInsRC;
298 /** The APIC helpers - RC Ptr. */
299 PCPDMAPICHLPRC pApicHlpRC;
300 /** LAPICs states - RC Ptr */
301 RTRCPTR pLapicsRC;
302
303 /** APIC specification version in this virtual hardware configuration. */
304 PDMAPICVERSION enmVersion;
305
306 /** Number of attempts made to optimize TPR accesses. */
307 uint32_t ulTPRPatchAttempts;
308
309 /** Number of CPUs on the system (same as LAPIC count). */
310 uint32_t cCpus;
311
312# ifdef VBOX_WITH_STATISTICS
313 STAMCOUNTER StatMMIOReadGC;
314 STAMCOUNTER StatMMIOReadHC;
315 STAMCOUNTER StatMMIOWriteGC;
316 STAMCOUNTER StatMMIOWriteHC;
317 STAMCOUNTER StatClearedActiveIrq;
318# endif
319} APICDeviceInfo;
320
321static void apic_eoi(APICDeviceInfo *dev, APICState* s);
322static void apic_deliver(APICDeviceInfo* dev, APICState *s,
323 uint8_t dest, uint8_t dest_mode,
324 uint8_t delivery_mode, uint8_t vector_num,
325 uint8_t polarity, uint8_t trigger_mode);
326static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
327 int64_t current_time);
328static int apic_get_arb_pri(APICState *s);
329static int apic_get_ppr(APICState *s);
330static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
331
332
333DECLINLINE(APICState*) getLapicById(APICDeviceInfo* dev, VMCPUID id)
334{
335 AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
336 return LAPIC_BASE(dev) + id;
337}
338
339DECLINLINE(APICState*) getLapic(APICDeviceInfo* dev)
340{
341 /* LAPIC's array is indexed by CPU id */
342 VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
343 return getLapicById(dev, id);
344}
345
346DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
347{
348 /* for now we assume LAPIC physical id == CPU id */
349 return VMCPUID(s->phys_id);
350}
351
352DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s)
353{
354 Log2(("apic: setting interrupt flag\n"));
355 dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns),
356 getCpuFromLapic(dev, s));
357}
358
359DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
360{
361 Log2(("apic: clear interrupt flag\n"));
362 dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
363 getCpuFromLapic(dev, s));
364}
365
366DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
367{
368 Log2(("apic: send SIPI vector=%d\n", vector));
369 dev->CTX_SUFF(pApicHlp)->pfnSendSipi(dev->CTX_SUFF(pDevIns),
370 getCpuFromLapic(dev, s),
371 vector);
372}
373
374
375
376DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
377{
378 switch (dev->enmVersion)
379 {
380 case PDMAPICVERSION_NONE:
381 return 0;
382 case PDMAPICVERSION_APIC:
383 return MSR_IA32_APICBASE_ENABLE;
384 case PDMAPICVERSION_X2APIC:
385 return MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_X2ENABLE ;
386 default:
387 AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
388 return 0;
389 }
390}
391
392DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
393{
394 switch (((apic->apicbase) >> 10) & 0x3)
395 {
396 case 0:
397 return PDMAPICVERSION_NONE;
398 case 1:
399 default:
400 /* Invalid */
401 return PDMAPICVERSION_NONE;
402 case 2:
403 return PDMAPICVERSION_APIC;
404 case 3:
405 return PDMAPICVERSION_X2APIC;
406 }
407}
408
409#endif /* VBOX */
410
411#ifndef VBOX_DEVICE_STRUCT_TESTCASE
412#ifndef VBOX
413static int apic_io_memory;
414static APICState *first_local_apic = NULL;
415static int last_apic_id = 0;
416#endif /* !VBOX */
417
418static void apic_init_ipi(APICState *s);
419static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
420static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
421
422#ifdef VBOX
423static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
424__BEGIN_DECLS
425PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
426PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
427PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
428PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
429PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
430PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
431PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val);
432PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns);
433PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
434 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
435 uint8_t u8TriggerMode);
436PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
437PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
438PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
439PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
440PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
441
442static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val);
443__END_DECLS
444#endif /* VBOX */
445
446#ifndef VBOX
447static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
448 uint8_t vector_num, uint8_t polarity,
449 uint8_t trigger_mode)
450{
451 APICState *apic_iter;
452#else /* VBOX */
453static void apic_bus_deliver(APICDeviceInfo* dev,
454 uint32_t deliver_bitmask, uint8_t delivery_mode,
455 uint8_t vector_num, uint8_t polarity,
456 uint8_t trigger_mode)
457{
458#endif /* VBOX */
459
460 LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
461 switch (delivery_mode) {
462 case APIC_DM_LOWPRI:
463 {
464 int d = -1;
465 if (deliver_bitmask)
466 d = ffs_bit(deliver_bitmask);
467 if (d >= 0)
468 {
469 APICState* apic = getLapicById(dev, d);
470 apic_set_irq(dev, apic, vector_num, trigger_mode);
471 }
472 return;
473 }
474 case APIC_DM_FIXED:
475 /* XXX: arbitration */
476 break;
477
478 case APIC_DM_SMI:
479 /** @todo: what do we really do with SMI */
480 foreach_apic(dev, deliver_bitmask,
481 cpuSetInterrupt(dev, apic));
482 return;
483
484 case APIC_DM_NMI:
485 /** @todo: what do we really do with NMI */
486 foreach_apic(dev, deliver_bitmask,
487 cpuSetInterrupt(dev, apic));
488 return;
489
490 case APIC_DM_INIT:
491 /* normal INIT IPI sent to processors */
492#ifdef VBOX
493 foreach_apic(dev, deliver_bitmask,
494 apic_init_ipi(apic));
495#else
496 for (apic_iter = first_local_apic; apic_iter != NULL;
497 apic_iter = apic_iter->next_apic) {
498 apic_init_ipi(apic_iter);
499 }
500#endif
501 return;
502
503 case APIC_DM_EXTINT:
504 /* handled in I/O APIC code */
505 break;
506
507 default:
508 return;
509 }
510
511#ifdef VBOX
512 foreach_apic(dev, deliver_bitmask,
513 apic_set_irq (dev, apic, vector_num, trigger_mode));
514#else /* VBOX */
515 for (apic_iter = first_local_apic; apic_iter != NULL;
516 apic_iter = apic_iter->next_apic) {
517 if (deliver_bitmask & (1 << apic_iter->id))
518 apic_set_irq(apic_iter, vector_num, trigger_mode);
519 }
520#endif /* VBOX */
521}
522
523#ifndef VBOX
524void cpu_set_apic_base(CPUState *env, uint64_t val)
525{
526 APICState *s = env->apic_state;
527#ifdef DEBUG_APIC
528 Log(("cpu_set_apic_base: %016llx\n", val));
529#endif
530
531 s->apicbase = (val & 0xfffff000) |
532 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
533 /* if disabled, cannot be enabled again */
534 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
535 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
536 env->cpuid_features &= ~CPUID_APIC;
537 s->spurious_vec &= ~APIC_SV_ENABLE;
538 }
539}
540#else /* VBOX */
541PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
542{
543 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
544 APICState *s = getLapic(dev);
545 Log(("cpu_set_apic_base: %016RX64\n", val));
546
547 /** @todo: do we need to lock here ? */
548 /* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
549 /** @todo If this change is valid immediately, then we should change the MMIO registration! */
550 /* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
551 PDMAPICVERSION oldMode = getApicMode(s);
552 s->apicbase =
553 (val & 0xfffff000) | /* base */
554 (val & getApicEnableBits(dev)) | /* mode */
555 (s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
556 PDMAPICVERSION newMode = getApicMode(s);
557
558 if (oldMode != newMode)
559 {
560 switch (newMode)
561 {
562 case PDMAPICVERSION_NONE:
563 {
564 s->spurious_vec &= ~APIC_SV_ENABLE;
565 /* Clear any pending APIC interrupt action flag. */
566 cpuClearInterrupt(dev, s);
567 /** @todo: why do we do that? */
568 dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
569 break;
570 }
571 case PDMAPICVERSION_APIC:
572 /** @todo: map MMIO ranges, if needed */
573 break;
574 case PDMAPICVERSION_X2APIC:
575 /** @todo: unmap MMIO ranges of this APIC, according to the spec */
576 break;
577 default:
578 break;
579 }
580 }
581 /* APIC_UNLOCK(dev); */
582}
583#endif /* VBOX */
584#ifndef VBOX
585
586uint64_t cpu_get_apic_base(CPUState *env)
587{
588 APICState *s = env->apic_state;
589#ifdef DEBUG_APIC
590 Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
591#endif
592 return s->apicbase;
593}
594
595void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
596{
597 APICState *s = env->apic_state;
598 s->tpr = (val & 0x0f) << 4;
599 apic_update_irq(s);
600}
601
602uint8_t cpu_get_apic_tpr(CPUX86State *env)
603{
604 APICState *s = env->apic_state;
605 return s->tpr >> 4;
606}
607
608static int fls_bit(int value)
609{
610 unsigned int ret = 0;
611
612#ifdef HOST_I386
613 __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
614 return ret;
615#else
616 if (value > 0xffff)
617 value >>= 16, ret = 16;
618 if (value > 0xff)
619 value >>= 8, ret += 8;
620 if (value > 0xf)
621 value >>= 4, ret += 4;
622 if (value > 0x3)
623 value >>= 2, ret += 2;
624 return ret + (value >> 1);
625#endif
626}
627
628static inline void set_bit(uint32_t *tab, int index)
629{
630 int i, mask;
631 i = index >> 5;
632 mask = 1 << (index & 0x1f);
633 tab[i] |= mask;
634}
635
636static inline void reset_bit(uint32_t *tab, int index)
637{
638 int i, mask;
639 i = index >> 5;
640 mask = 1 << (index & 0x1f);
641 tab[i] &= ~mask;
642}
643
644
645#else /* VBOX */
646
647PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
648{
649 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
650 APICState *s = getLapic(dev);
651 Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
652 return s->apicbase;
653}
654
655PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
656{
657 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
658 APICState *s = getLapic(dev);
659 LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
660 apic_update_tpr(dev, s, (val & 0x0f) << 4);
661}
662
663PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
664{
665 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
666 APICState *s = getLapic(dev);
667 Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
668 return s->tpr >> 4;
669}
670
671PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
672{
673 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
674
675 if (dev->enmVersion < PDMAPICVERSION_X2APIC)
676 return VERR_EM_INTERPRETER;
677
678 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
679 //LogRel(("nike: WRMSR on %d: to %x written %llx\n", idCpu, index, u64Value));
680
681 APICState* apic = getLapicById(dev, idCpu);
682
683 switch (index)
684 {
685 case 0x02:
686 apic->id = (u64Value >> 24);
687 break;
688 case 0x03:
689 break;
690 case 0x08:
691 apic_update_tpr(dev, apic, u64Value);
692 break;
693 case 0x09: case 0x0a:
694 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
695 break;
696 case 0x0b: /* EOI */
697 apic_eoi(dev, apic);
698 break;
699 case 0x0d:
700 apic->log_dest = u64Value >> 24;
701 break;
702 case 0x0e:
703 apic->dest_mode = u64Value >> 28;
704 break;
705 case 0x0f:
706 apic->spurious_vec = u64Value & 0x1ff;
707 apic_update_irq(dev, apic);
708 break;
709 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
710 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
711 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
712 case 0x28:
713 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
714 break;
715
716 case 0x30:
717 /* Here one of the differences with regular APIC: ICR is single 64-bit register */
718 apic->icr[0] = (uint32_t)u64Value;
719 apic->icr[1] = (uint32_t)(u64Value >> 32);
720 apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
721 (apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),
722 (apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
723 break;
724 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
725 {
726 int n = index - 0x32;
727 apic->lvt[n] = u64Value;
728 if (n == APIC_LVT_TIMER)
729 apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
730 }
731 break;
732 case 0x38:
733 apic->initial_count = u64Value;
734 apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
735 apic_timer_update(dev, apic, apic->initial_count_load_time);
736 break;
737 case 0x39:
738 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
739 break;
740 case 0x3e:
741 {
742 int v;
743 apic->divide_conf = u64Value & 0xb;
744 v = (apic->divide_conf & 3) | ((apic->divide_conf >> 1) & 4);
745 apic->count_shift = (v + 1) & 7;
746 break;
747 }
748 case 0x3f:
749 {
750 /* Self IPI, see x2APIC book 2.4.5 */
751 int vector = u64Value & 0xff;
752 apic_bus_deliver(dev,
753 1 << getLapicById(dev, idCpu)->id /* Self */,
754 0 /* Delivery mode - fixed */,
755 vector,
756 0 /* Polarity - conform to the bus */,
757 0 /* Trigger mode - edge */);
758 break;
759 }
760 default:
761 AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
762 apic->esr |= ESR_ILLEGAL_ADDRESS;
763 break;
764 }
765
766 return VINF_SUCCESS;
767}
768PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
769{
770 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
771
772 if (dev->enmVersion < PDMAPICVERSION_X2APIC)
773 return VERR_EM_INTERPRETER;
774
775 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
776 //LogRel(("nike: RDMSR on %d: read from %x\n", idCpu, index));
777 APICState* apic = getLapicById(dev, idCpu);
778 uint64_t val = 0;
779
780 switch (index)
781 {
782 case 0x02: /* id */
783 val = apic->id << 24;
784 break;
785 case 0x03: /* version */
786 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
787 break;
788 case 0x08:
789 val = apic->tpr;
790 break;
791 case 0x09:
792 val = apic_get_arb_pri(apic);
793 break;
794 case 0x0a:
795 /* ppr */
796 val = apic_get_ppr(apic);
797 break;
798 case 0x0b:
799 val = 0;
800 break;
801 case 0x0d:
802 val = apic->log_dest << 24;
803 break;
804 case 0x0e:
805 /* Bottom 28 bits are always 1 */
806 val = (apic->dest_mode << 28) | 0xfffffff;
807 break;
808 case 0x0f:
809 val = apic->spurious_vec;
810 break;
811 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
812 val = apic->isr[index & 7];
813 break;
814 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
815 val = apic->tmr[index & 7];
816 break;
817 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
818 val = apic->irr[index & 7];
819 break;
820 case 0x28:
821 val = apic->esr;
822 break;
823 case 0x30:
824 /* Here one of the differences with regular APIC: ICR is single 64-bit register */
825 val = ((uint64_t)apic->icr[0x31] << 32) | apic->icr[0x30];
826 break;
827 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
828 val = apic->lvt[index - 0x32];
829 break;
830 case 0x38:
831 val = apic->initial_count;
832 break;
833 case 0x39:
834 val = apic_get_current_count(dev, apic);
835 break;
836 case 0x3e:
837 val = apic->divide_conf;
838 break;
839 case 0x3f:
840 /* Self IPI register is write only */
841 Log(("apicReadMSR: read from write-only register %d ignored\n", index));
842 break;
843 default:
844 AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
845 apic->esr |= ESR_ILLEGAL_ADDRESS;
846 val = 0;
847 break;
848 }
849 *pu64Value = val;
850 return VINF_SUCCESS;
851}
852
853/**
854 * More or less private interface between IOAPIC, only PDM is responsible
855 * for connecting the two devices.
856 */
857PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
858 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
859 uint8_t u8TriggerMode)
860{
861 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
862 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
863 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
864 apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
865 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
866}
867
868#endif /* VBOX */
869
870/* return -1 if no bit is set */
871static int get_highest_priority_int(uint32_t *tab)
872{
873 int i;
874 for(i = 7; i >= 0; i--) {
875 if (tab[i] != 0) {
876 return i * 32 + fls_bit(tab[i]);
877 }
878 }
879 return -1;
880}
881
882static int apic_get_ppr(APICState *s)
883{
884 int tpr, isrv, ppr;
885
886 tpr = (s->tpr >> 4);
887 isrv = get_highest_priority_int(s->isr);
888 if (isrv < 0)
889 isrv = 0;
890 isrv >>= 4;
891 if (tpr >= isrv)
892 ppr = s->tpr;
893 else
894 ppr = isrv << 4;
895 return ppr;
896}
897
898static int apic_get_ppr_zero_tpr(APICState *s)
899{
900 int isrv;
901
902 isrv = get_highest_priority_int(s->isr);
903 if (isrv < 0)
904 isrv = 0;
905 return isrv;
906}
907
908static int apic_get_arb_pri(APICState *s)
909{
910 /* XXX: arbitration */
911 return 0;
912}
913
914/* signal the CPU if an irq is pending */
915static bool apic_update_irq(APICDeviceInfo *dev, APICState* s)
916{
917 int irrv, ppr;
918 if (!(s->spurious_vec & APIC_SV_ENABLE))
919#ifdef VBOX
920 {
921 /* Clear any pending APIC interrupt action flag. */
922 cpuClearInterrupt(dev, s);
923 return false;
924 }
925#else
926 return false;
927#endif /* VBOX */
928 irrv = get_highest_priority_int(s->irr);
929 if (irrv < 0)
930 return false;
931 ppr = apic_get_ppr(s);
932 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
933 return false;
934#ifndef VBOX
935 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
936#else
937 cpuSetInterrupt(dev, s);
938 return true;
939#endif
940}
941
942#ifdef VBOX
943
944/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
945PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
946{
947 int irrv, ppr;
948 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
949 if (!dev)
950 return false;
951 APICState *s = getLapic(dev);
952
953 /*
954 * All our callbacks now come from single IOAPIC, thus locking
955 * seems to be excessive now (@todo: check)
956 */
957 irrv = get_highest_priority_int(s->irr);
958 if (irrv < 0)
959 return false;
960
961 ppr = apic_get_ppr_zero_tpr(s);
962
963 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
964 return false;
965
966 return true;
967}
968
969static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val)
970{
971 bool fIrqIsActive = false;
972 bool fIrqWasActive = false;
973
974 fIrqWasActive = apic_update_irq(dev, s);
975 s->tpr = val;
976 fIrqIsActive = apic_update_irq(dev, s);
977
978 /* If an interrupt is pending and now masked, then clear the FF flag. */
979 if (fIrqWasActive && !fIrqIsActive)
980 {
981 Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
982 STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
983 cpuClearInterrupt(dev, s);
984 }
985}
986#endif
987
988static void apic_set_irq(APICDeviceInfo *dev, APICState* s, int vector_num, int trigger_mode)
989{
990 LogFlow(("apic_set_irq vector=%x, trigger_mode=%x\n", vector_num, trigger_mode));
991 set_bit(s->irr, vector_num);
992 if (trigger_mode)
993 set_bit(s->tmr, vector_num);
994 else
995 reset_bit(s->tmr, vector_num);
996 apic_update_irq(dev, s);
997}
998
999static void apic_eoi(APICDeviceInfo *dev, APICState* s)
1000{
1001 int isrv;
1002 isrv = get_highest_priority_int(s->isr);
1003 if (isrv < 0)
1004 return;
1005 reset_bit(s->isr, isrv);
1006 LogFlow(("apic_eoi isrv=%x\n", isrv));
1007 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1008 set the remote IRR bit for level triggered interrupts. */
1009 apic_update_irq(dev, s);
1010}
1011
1012#ifndef VBOX
1013static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1014#else /* VBOX */
1015static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1016#endif /* VBOX */
1017{
1018 uint32_t mask = 0;
1019
1020 if (dest_mode == 0)
1021 {
1022 if (dest == 0xff)
1023 mask = 0xff;
1024 else
1025 mask = 1 << dest;
1026 }
1027 else
1028 {
1029 APICState *apic = LAPIC_BASE(dev);
1030 uint32_t i;
1031
1032 /* XXX: cluster mode */
1033 for(i = 0; i < dev->cCpus; i++)
1034 {
1035 if (apic->dest_mode == 0xf)
1036 {
1037 if (dest & apic->log_dest)
1038 mask |= (1 << apic->id);
1039 }
1040 else if (apic->dest_mode == 0x0)
1041 {
1042 if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1043 &&
1044 (dest & apic->log_dest & 0x0f))
1045 {
1046 mask |= (1 << i);
1047 }
1048 }
1049 }
1050 apic++;
1051 }
1052
1053 return mask;
1054}
1055
1056static void apic_init_ipi(APICState *s)
1057{
1058 int i;
1059
1060 for(i = 0; i < APIC_LVT_NB; i++)
1061 s->lvt[i] = 1 << 16; /* mask LVT */
1062 s->tpr = 0;
1063 s->spurious_vec = 0xff;
1064 s->log_dest = 0;
1065 s->dest_mode = 0xff;
1066 memset(s->isr, 0, sizeof(s->isr));
1067 memset(s->tmr, 0, sizeof(s->tmr));
1068 memset(s->irr, 0, sizeof(s->irr));
1069 s->esr = 0;
1070 memset(s->icr, 0, sizeof(s->icr));
1071 s->divide_conf = 0;
1072 s->count_shift = 0;
1073 s->initial_count = 0;
1074 s->initial_count_load_time = 0;
1075 s->next_time = 0;
1076
1077#ifdef VBOX
1078 /** @todo reset CPU, activate wait for sipi mode for application processors */
1079 /** Must be dealt with in ring 3 */
1080#endif
1081}
1082
1083
1084/* send a SIPI message to the CPU to start it */
1085static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1086{
1087#ifndef VBOX
1088 CPUState *env = s->cpu_env;
1089 if (!env->halted)
1090 return;
1091 env->eip = 0;
1092 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1093 0xffff, 0);
1094 env->halted = 0;
1095#else
1096 /** @todo: init CPUs */
1097 LogRel(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->id));
1098 cpuSendSipi(dev, s, vector_num);
1099#endif
1100}
1101static void apic_deliver(APICDeviceInfo* dev, APICState *s,
1102 uint8_t dest, uint8_t dest_mode,
1103 uint8_t delivery_mode, uint8_t vector_num,
1104 uint8_t polarity, uint8_t trigger_mode)
1105{
1106 uint32_t deliver_bitmask = 0;
1107 int dest_shorthand = (s->icr[0] >> 18) & 3;
1108#ifndef VBOX
1109 APICState *apic_iter;
1110#endif /* !VBOX */
1111
1112 LogFlow(("apic_deliver dest=%x dest_mode=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, delivery_mode, vector_num, polarity, trigger_mode));
1113
1114 switch (dest_shorthand) {
1115 case 0:
1116#ifndef VBOX
1117 deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1118#else /* VBOX */
1119 deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1120#endif /* !VBOX */
1121 break;
1122 case 1:
1123 deliver_bitmask = (1 << s->id);
1124 break;
1125 case 2:
1126 deliver_bitmask = 0xffffffff;
1127 break;
1128 case 3:
1129 deliver_bitmask = 0xffffffff & ~(1 << s->id);
1130 break;
1131 }
1132
1133 switch (delivery_mode) {
1134 case APIC_DM_LOWPRI:
1135 /* XXX: serch for focus processor, arbitration */
1136 dest = s->id;
1137
1138 case APIC_DM_INIT:
1139 {
1140 int trig_mode = (s->icr[0] >> 15) & 1;
1141 int level = (s->icr[0] >> 14) & 1;
1142 if (level == 0 && trig_mode == 1) {
1143#ifdef VBOX
1144 foreach_apic(dev, deliver_bitmask,
1145 apic->arb_id = apic->id);
1146#else /* !VBOX */
1147 for (apic_iter = first_local_apic; apic_iter != NULL;
1148 apic_iter = apic_iter->next_apic) {
1149 if (deliver_bitmask & (1 << apic_iter->id)) {
1150 apic_iter->arb_id = apic_iter->id;
1151 }
1152 }
1153#endif /* !VBOX */
1154 return;
1155 }
1156 }
1157 break;
1158
1159 case APIC_DM_SIPI:
1160#ifndef VBOX
1161 for (apic_iter = first_local_apic; apic_iter != NULL;
1162 apic_iter = apic_iter->next_apic) {
1163 if (deliver_bitmask & (1 << apic_iter->id)) {
1164 /* XXX: SMP support */
1165 /* apic_startup(apic_iter); */
1166 }
1167 }
1168#else
1169 foreach_apic(dev, deliver_bitmask,
1170 apic_startup(dev, apic, vector_num));
1171#endif /* !VBOX */
1172 return;
1173 }
1174
1175#ifndef VBOX
1176 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1177 trigger_mode);
1178#else /* VBOX */
1179 apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num, polarity,
1180 trigger_mode);
1181#endif /* VBOX */
1182}
1183
1184
1185PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1186{
1187 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1188 /* if the APIC is not installed or enabled, we let the 8259 handle the
1189 IRQs */
1190 if (!dev)
1191 {
1192 Log(("apic_get_interrupt: returns -1 (!s)\n"));
1193 return -1;
1194 }
1195
1196 APIC_LOCK(dev, VERR_INTERNAL_ERROR);
1197
1198 APICState *s = getLapic(dev);
1199 int intno;
1200
1201 if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1202 Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
1203 intno = -1;
1204 goto done;
1205 }
1206
1207 /* XXX: spurious IRQ handling */
1208 intno = get_highest_priority_int(s->irr);
1209 if (intno < 0) {
1210 Log(("apic_get_interrupt: returns -1 (irr)\n"));
1211 intno = -1;
1212 goto done;
1213 }
1214 if (s->tpr && (uint32_t)intno <= s->tpr) {
1215 Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1216 intno = s->spurious_vec & 0xff;
1217 goto done;
1218 }
1219 reset_bit(s->irr, intno);
1220 set_bit(s->isr, intno);
1221 apic_update_irq(dev, s);
1222 LogFlow(("apic_get_interrupt: returns %d\n", intno));
1223 done:
1224 APIC_UNLOCK(dev);
1225 return intno;
1226}
1227
1228static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
1229{
1230 int64_t d;
1231 uint32_t val;
1232#ifndef VBOX
1233 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1234 s->count_shift;
1235#else /* VBOX */
1236 d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1237 s->count_shift;
1238#endif /* VBOX */
1239 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1240 /* periodic */
1241 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1242 } else {
1243 if (d >= s->initial_count)
1244 val = 0;
1245 else
1246 val = s->initial_count - d;
1247 }
1248 return val;
1249}
1250
1251static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1252{
1253 int64_t next_time, d;
1254
1255 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1256 d = (current_time - s->initial_count_load_time) >>
1257 s->count_shift;
1258 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1259 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1260 } else {
1261 if (d >= s->initial_count)
1262 goto no_timer;
1263 d = (uint64_t)s->initial_count + 1;
1264 }
1265 next_time = s->initial_count_load_time + (d << s->count_shift);
1266#ifndef VBOX
1267 qemu_mod_timer(s->timer, next_time);
1268#else
1269 TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1270#endif
1271 s->next_time = next_time;
1272 } else {
1273 no_timer:
1274#ifndef VBOX
1275 qemu_del_timer(s->timer);
1276#else
1277 TMTimerStop(s->CTX_SUFF(pTimer));
1278#endif
1279 }
1280}
1281
1282#ifdef IN_RING3
1283#ifndef VBOX
1284static void apic_timer(void *opaque)
1285{
1286 APICState *s = opaque;
1287#else /* VBOX */
1288static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1289{
1290 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1291 APICState *s = getLapic(dev);
1292
1293 APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
1294#endif /* VBOX */
1295
1296 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1297 LogFlow(("apic_timer: trigger irq\n"));
1298 apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1299 }
1300 apic_timer_update(dev, s, s->next_time);
1301
1302#ifdef VBOX
1303 APIC_UNLOCK(dev);
1304#endif
1305}
1306#endif /* IN_RING3 */
1307
1308#ifndef VBOX
1309static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1310{
1311 return 0;
1312}
1313static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1314{
1315 return 0;
1316}
1317
1318static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1319{
1320}
1321
1322static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1323{
1324}
1325#endif /* !VBOX */
1326
1327
1328#ifndef VBOX
1329static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1330{
1331 CPUState *env;
1332 APICState *s;
1333#else /* VBOX */
1334static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1335{
1336#endif /* VBOX */
1337 uint32_t val;
1338 int index;
1339
1340#ifndef VBOX
1341 env = cpu_single_env;
1342 if (!env)
1343 return 0;
1344 s = env->apic_state;
1345#endif /* !VBOX */
1346
1347 index = (addr >> 4) & 0xff;
1348 switch(index) {
1349 case 0x02: /* id */
1350 val = s->id << 24;
1351 break;
1352 case 0x03: /* version */
1353 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1354 break;
1355 case 0x08:
1356 val = s->tpr;
1357 break;
1358 case 0x09:
1359 val = apic_get_arb_pri(s);
1360 break;
1361 case 0x0a:
1362 /* ppr */
1363 val = apic_get_ppr(s);
1364 break;
1365 case 0x0b:
1366 Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1367 val = 0;
1368 break;
1369 case 0x0d:
1370 val = s->log_dest << 24;
1371 break;
1372 case 0x0e:
1373#ifdef VBOX
1374 /* Bottom 28 bits are always 1 */
1375 val = (s->dest_mode << 28) | 0xfffffff;
1376#else
1377 val = s->dest_mode << 28;
1378#endif
1379 break;
1380 case 0x0f:
1381 val = s->spurious_vec;
1382 break;
1383#ifndef VBOX
1384 case 0x10 ... 0x17:
1385#else /* VBOX */
1386 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1387#endif /* VBOX */
1388 val = s->isr[index & 7];
1389 break;
1390#ifndef VBOX
1391 case 0x18 ... 0x1f:
1392#else /* VBOX */
1393 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1394#endif /* VBOX */
1395 val = s->tmr[index & 7];
1396 break;
1397#ifndef VBOX
1398 case 0x20 ... 0x27:
1399#else /* VBOX */
1400 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1401#endif /* VBOX */
1402 val = s->irr[index & 7];
1403 break;
1404 case 0x28:
1405 val = s->esr;
1406 break;
1407 case 0x30:
1408 case 0x31:
1409 val = s->icr[index & 1];
1410 break;
1411#ifndef VBOX
1412 case 0x32 ... 0x37:
1413#else /* VBOX */
1414 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1415#endif /* VBOX */
1416 val = s->lvt[index - 0x32];
1417 break;
1418 case 0x38:
1419 val = s->initial_count;
1420 break;
1421 case 0x39:
1422 val = apic_get_current_count(dev, s);
1423 break;
1424 case 0x3e:
1425 val = s->divide_conf;
1426 break;
1427 default:
1428 AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1429 s->esr |= ESR_ILLEGAL_ADDRESS;
1430 val = 0;
1431 break;
1432 }
1433#ifdef DEBUG_APIC
1434 Log(("APIC read: %08x = %08x\n", (uint32_t)addr, val));
1435#endif
1436 return val;
1437}
1438
1439#ifndef VBOX
1440static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1441{
1442 CPUState *env;
1443 APICState *s;
1444#else /* VBOX */
1445static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1446{
1447#endif /* VBOX */
1448 int index;
1449
1450#ifndef VBOX
1451 env = cpu_single_env;
1452 if (!env)
1453 return;
1454 s = env->apic_state;
1455#endif /* !VBOX */
1456
1457#ifdef DEBUG_APIC
1458 Log(("APIC write: %08x = %08x\n", (uint32_t)addr, val));
1459#endif
1460
1461 index = (addr >> 4) & 0xff;
1462 switch(index) {
1463 case 0x02:
1464 s->id = (val >> 24);
1465 break;
1466 case 0x03:
1467 Log(("apic_mem_writel: write to version register; ignored\n"));
1468 break;
1469 case 0x08:
1470#ifdef VBOX
1471 apic_update_tpr(dev, s, val);
1472#else
1473 s->tpr = val;
1474 apic_update_irq(s);
1475#endif
1476 break;
1477 case 0x09:
1478 case 0x0a:
1479 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1480 break;
1481 case 0x0b: /* EOI */
1482 apic_eoi(dev, s);
1483 break;
1484 case 0x0d:
1485 s->log_dest = val >> 24;
1486 break;
1487 case 0x0e:
1488 s->dest_mode = val >> 28;
1489 break;
1490 case 0x0f:
1491 s->spurious_vec = val & 0x1ff;
1492 apic_update_irq(dev, s);
1493 break;
1494#ifndef VBOX
1495 case 0x10 ... 0x17:
1496 case 0x18 ... 0x1f:
1497 case 0x20 ... 0x27:
1498 case 0x28:
1499#else
1500 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1501 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1502 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1503 case 0x28:
1504 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1505#endif
1506 break;
1507
1508 case 0x30:
1509 s->icr[0] = val;
1510 apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
1511 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1512 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1513 break;
1514 case 0x31:
1515 s->icr[1] = val;
1516 break;
1517#ifndef VBOX
1518 case 0x32 ... 0x37:
1519#else /* VBOX */
1520 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1521#endif /* VBOX */
1522 {
1523 int n = index - 0x32;
1524 s->lvt[n] = val;
1525 if (n == APIC_LVT_TIMER)
1526#ifndef VBOX
1527 apic_timer_update(s, qemu_get_clock(vm_clock));
1528#else /* VBOX */
1529 apic_timer_update(dev, s, TMTimerGet(s->CTX_SUFF(pTimer)));
1530#endif /* VBOX*/
1531 }
1532 break;
1533 case 0x38:
1534 s->initial_count = val;
1535#ifndef VBOX
1536 s->initial_count_load_time = qemu_get_clock(vm_clock);
1537#else /* VBOX */
1538 s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
1539#endif /* VBOX*/
1540 apic_timer_update(dev, s, s->initial_count_load_time);
1541 break;
1542 case 0x39:
1543 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1544 break;
1545 case 0x3e:
1546 {
1547 int v;
1548 s->divide_conf = val & 0xb;
1549 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
1550 s->count_shift = (v + 1) & 7;
1551 }
1552 break;
1553 default:
1554 AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1555 s->esr |= ESR_ILLEGAL_ADDRESS;
1556 break;
1557 }
1558#ifdef VBOX
1559 return VINF_SUCCESS;
1560#endif
1561}
1562
1563#ifdef IN_RING3
1564
1565static void apic_save(QEMUFile *f, void *opaque)
1566{
1567 APICState *s = (APICState*)opaque;
1568 int i;
1569
1570 qemu_put_be32s(f, &s->apicbase);
1571#ifdef VBOX
1572 qemu_put_be32s(f, &s->id);
1573 qemu_put_be32s(f, &s->phys_id);
1574 qemu_put_be32s(f, &s->arb_id);
1575 qemu_put_be32s(f, &s->tpr);
1576#else
1577 qemu_put_8s(f, &s->id);
1578 qemu_put_8s(f, &s->arb_id);
1579 qemu_put_8s(f, &s->tpr);
1580#endif
1581 qemu_put_be32s(f, &s->spurious_vec);
1582 qemu_put_8s(f, &s->log_dest);
1583 qemu_put_8s(f, &s->dest_mode);
1584 for (i = 0; i < 8; i++) {
1585 qemu_put_be32s(f, &s->isr[i]);
1586 qemu_put_be32s(f, &s->tmr[i]);
1587 qemu_put_be32s(f, &s->irr[i]);
1588 }
1589 for (i = 0; i < APIC_LVT_NB; i++) {
1590 qemu_put_be32s(f, &s->lvt[i]);
1591 }
1592 qemu_put_be32s(f, &s->esr);
1593 qemu_put_be32s(f, &s->icr[0]);
1594 qemu_put_be32s(f, &s->icr[1]);
1595 qemu_put_be32s(f, &s->divide_conf);
1596 qemu_put_be32s(f, &s->count_shift);
1597 qemu_put_be32s(f, &s->initial_count);
1598 qemu_put_be64s(f, &s->initial_count_load_time);
1599 qemu_put_be64s(f, &s->next_time);
1600
1601#ifdef VBOX
1602 TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1603#endif
1604}
1605
1606static int apic_load(QEMUFile *f, void *opaque, int version_id)
1607{
1608 APICState *s = (APICState*)opaque;
1609 int i;
1610
1611#ifdef VBOX
1612 if ((version_id < 1) || (version_id > 2))
1613 return -EINVAL;
1614
1615 /* XXX: what if the base changes? (registered memory regions) */
1616 qemu_get_be32s(f, &s->apicbase);
1617
1618 switch (version_id)
1619 {
1620 case 1:
1621 {
1622 uint8_t val = 0;
1623 qemu_get_8s(f, &val);
1624 s->id = val;
1625 /* UP only in old saved states */
1626 s->phys_id = 0;
1627 qemu_get_8s(f, &val);
1628 s->arb_id = val;
1629 break;
1630 }
1631 case 2:
1632 qemu_get_be32s(f, &s->id);
1633 qemu_get_be32s(f, &s->phys_id);
1634 qemu_get_be32s(f, &s->arb_id);
1635 break;
1636 }
1637 qemu_get_be32s(f, &s->tpr);
1638#else
1639 if (version_id != 1)
1640 return -EINVAL;
1641
1642 /* XXX: what if the base changes? (registered memory regions) */
1643 qemu_get_be32s(f, &s->apicbase);
1644 qemu_get_8s(f, &s->id);
1645 qemu_get_8s(f, &s->arb_id);
1646 qemu_get_8s(f, &s->tpr);
1647#endif
1648 qemu_get_be32s(f, &s->spurious_vec);
1649 qemu_get_8s(f, &s->log_dest);
1650 qemu_get_8s(f, &s->dest_mode);
1651 for (i = 0; i < 8; i++) {
1652 qemu_get_be32s(f, &s->isr[i]);
1653 qemu_get_be32s(f, &s->tmr[i]);
1654 qemu_get_be32s(f, &s->irr[i]);
1655 }
1656 for (i = 0; i < APIC_LVT_NB; i++) {
1657 qemu_get_be32s(f, &s->lvt[i]);
1658 }
1659 qemu_get_be32s(f, &s->esr);
1660 qemu_get_be32s(f, &s->icr[0]);
1661 qemu_get_be32s(f, &s->icr[1]);
1662 qemu_get_be32s(f, &s->divide_conf);
1663 qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1664 qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1665 qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1666 qemu_get_be64s(f, (uint64_t *)&s->next_time);
1667
1668#ifdef VBOX
1669 TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1670#endif
1671
1672 return VINF_SUCCESS;
1673}
1674#ifndef VBOX
1675static void apic_reset(void *opaque)
1676{
1677 APICState *s = (APICState*)opaque;
1678 apic_init_ipi(s);
1679}
1680#endif
1681
1682#endif /* IN_RING3 */
1683
1684#ifndef VBOX
1685static CPUReadMemoryFunc *apic_mem_read[3] = {
1686 apic_mem_readb,
1687 apic_mem_readw,
1688 apic_mem_readl,
1689};
1690
1691static CPUWriteMemoryFunc *apic_mem_write[3] = {
1692 apic_mem_writeb,
1693 apic_mem_writew,
1694 apic_mem_writel,
1695};
1696
1697int apic_init(CPUState *env)
1698{
1699 APICState *s;
1700
1701 s = qemu_mallocz(sizeof(APICState));
1702 if (!s)
1703 return -1;
1704 env->apic_state = s;
1705 apic_init_ipi(s);
1706 s->id = last_apic_id++;
1707 s->cpu_env = env;
1708 s->apicbase = 0xfee00000 |
1709 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
1710
1711 /* XXX: mapping more APICs at the same memory location */
1712 if (apic_io_memory == 0) {
1713 /* NOTE: the APIC is directly connected to the CPU - it is not
1714 on the global memory bus. */
1715 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1716 apic_mem_write, NULL);
1717 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1718 apic_io_memory);
1719 }
1720 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1721
1722 register_savevm("apic", 0, 1, apic_save, apic_load, s);
1723 qemu_register_reset(apic_reset, s);
1724
1725 s->next_apic = first_local_apic;
1726 first_local_apic = s;
1727
1728 return 0;
1729}
1730#endif /* !VBOX */
1731
1732static void ioapic_service(IOAPICState *s)
1733{
1734 uint8_t i;
1735 uint8_t trig_mode;
1736 uint8_t vector;
1737 uint8_t delivery_mode;
1738 uint32_t mask;
1739 uint64_t entry;
1740 uint8_t dest;
1741 uint8_t dest_mode;
1742 uint8_t polarity;
1743
1744 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1745 mask = 1 << i;
1746 if (s->irr & mask) {
1747 entry = s->ioredtbl[i];
1748 if (!(entry & APIC_LVT_MASKED)) {
1749 trig_mode = ((entry >> 15) & 1);
1750 dest = entry >> 56;
1751 dest_mode = (entry >> 11) & 1;
1752 delivery_mode = (entry >> 8) & 7;
1753 polarity = (entry >> 13) & 1;
1754 if (trig_mode == APIC_TRIGGER_EDGE)
1755 s->irr &= ~mask;
1756 if (delivery_mode == APIC_DM_EXTINT)
1757#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1758 vector = pic_read_irq(isa_pic);
1759#else /* VBOX */
1760 {
1761 AssertMsgFailed(("Delivery mode ExtINT"));
1762 vector = 0xff; /* incorrect but shuts up gcc. */
1763 }
1764#endif /* VBOX */
1765 else
1766 vector = entry & 0xff;
1767
1768#ifndef VBOX
1769 apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1770 delivery_mode, vector, polarity, trig_mode);
1771#else /* VBOX */
1772 s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1773 dest,
1774 dest_mode,
1775 delivery_mode,
1776 vector,
1777 polarity,
1778 trig_mode);
1779#endif /* VBOX */
1780 }
1781 }
1782 }
1783}
1784
1785#ifdef VBOX
1786static
1787#endif
1788void ioapic_set_irq(void *opaque, int vector, int level)
1789{
1790 IOAPICState *s = (IOAPICState*)opaque;
1791
1792 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1793 uint32_t mask = 1 << vector;
1794 uint64_t entry = s->ioredtbl[vector];
1795
1796 if ((entry >> 15) & 1) {
1797 /* level triggered */
1798 if (level) {
1799 s->irr |= mask;
1800 ioapic_service(s);
1801#ifdef VBOX
1802 if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1803 s->irr &= ~mask;
1804 }
1805#endif
1806 } else {
1807 s->irr &= ~mask;
1808 }
1809 } else {
1810 /* edge triggered */
1811 if (level) {
1812 s->irr |= mask;
1813 ioapic_service(s);
1814 }
1815 }
1816 }
1817}
1818
1819static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1820{
1821 IOAPICState *s = (IOAPICState*)opaque;
1822 int index;
1823 uint32_t val = 0;
1824
1825 addr &= 0xff;
1826 if (addr == 0x00) {
1827 val = s->ioregsel;
1828 } else if (addr == 0x10) {
1829 switch (s->ioregsel) {
1830 case 0x00:
1831 val = s->id << 24;
1832 break;
1833 case 0x01:
1834 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1835 break;
1836 case 0x02:
1837 val = 0;
1838 break;
1839 default:
1840 index = (s->ioregsel - 0x10) >> 1;
1841 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1842 if (s->ioregsel & 1)
1843 val = s->ioredtbl[index] >> 32;
1844 else
1845 val = s->ioredtbl[index] & 0xffffffff;
1846 }
1847 }
1848#ifdef DEBUG_IOAPIC
1849 Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1850#endif
1851 }
1852 return val;
1853}
1854
1855static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1856{
1857 IOAPICState *s = (IOAPICState*)opaque;
1858 int index;
1859
1860 addr &= 0xff;
1861 if (addr == 0x00) {
1862 s->ioregsel = val;
1863 return;
1864 } else if (addr == 0x10) {
1865#ifdef DEBUG_IOAPIC
1866 Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1867#endif
1868 switch (s->ioregsel) {
1869 case 0x00:
1870 s->id = (val >> 24) & 0xff;
1871 return;
1872 case 0x01:
1873 case 0x02:
1874 return;
1875 default:
1876 index = (s->ioregsel - 0x10) >> 1;
1877 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1878 if (s->ioregsel & 1) {
1879 s->ioredtbl[index] &= 0xffffffff;
1880 s->ioredtbl[index] |= (uint64_t)val << 32;
1881 } else {
1882#ifdef VBOX
1883 /* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1884 uint8_t vec = val & 0xff;
1885 if ((val & APIC_LVT_MASKED) ||
1886 ((vec >= 0x10) && (vec < 0xff)))
1887 {
1888 s->ioredtbl[index] &= ~0xffffffffULL;
1889 s->ioredtbl[index] |= val;
1890 }
1891 else
1892 {
1893 /*
1894 * Linux 2.6 kernels has pretty strange function
1895 * unlock_ExtINT_logic() which writes
1896 * absolutely bogus (all 0) value into the vector
1897 * with pretty vague explanation why.
1898 * So we just ignore such writes.
1899 */
1900 LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1901 }
1902 }
1903#else
1904 s->ioredtbl[index] &= ~0xffffffffULL;
1905 s->ioredtbl[index] |= val;
1906#endif
1907 ioapic_service(s);
1908 }
1909 }
1910 }
1911}
1912
1913#ifdef IN_RING3
1914
1915static void ioapic_save(QEMUFile *f, void *opaque)
1916{
1917 IOAPICState *s = (IOAPICState*)opaque;
1918 int i;
1919
1920 qemu_put_8s(f, &s->id);
1921 qemu_put_8s(f, &s->ioregsel);
1922 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1923 qemu_put_be64s(f, &s->ioredtbl[i]);
1924 }
1925}
1926
1927static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1928{
1929 IOAPICState *s = (IOAPICState*)opaque;
1930 int i;
1931
1932 if (version_id != 1)
1933 return -EINVAL;
1934
1935 qemu_get_8s(f, &s->id);
1936 qemu_get_8s(f, &s->ioregsel);
1937 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1938 qemu_get_be64s(f, &s->ioredtbl[i]);
1939 }
1940 return 0;
1941}
1942
1943static void ioapic_reset(void *opaque)
1944{
1945 IOAPICState *s = (IOAPICState*)opaque;
1946#ifdef VBOX
1947 PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1948 PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1949#endif
1950 int i;
1951
1952 memset(s, 0, sizeof(*s));
1953 for(i = 0; i < IOAPIC_NUM_PINS; i++)
1954 s->ioredtbl[i] = 1 << 16; /* mask LVT */
1955
1956#ifdef VBOX
1957 if (pDevIns)
1958 {
1959 s->pDevInsR3 = pDevIns;
1960 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1961 s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1962 }
1963 if (pIoApicHlp)
1964 {
1965 s->pIoApicHlpR3 = pIoApicHlp;
1966 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1967 s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1968 }
1969#endif
1970}
1971
1972#endif /* IN_RING3 */
1973
1974#ifndef VBOX
1975static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1976 ioapic_mem_readl,
1977 ioapic_mem_readl,
1978 ioapic_mem_readl,
1979};
1980
1981static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1982 ioapic_mem_writel,
1983 ioapic_mem_writel,
1984 ioapic_mem_writel,
1985};
1986
1987IOAPICState *ioapic_init(void)
1988{
1989 IOAPICState *s;
1990 int io_memory;
1991
1992 s = qemu_mallocz(sizeof(IOAPICState));
1993 if (!s)
1994 return NULL;
1995 ioapic_reset(s);
1996 s->id = last_apic_id++;
1997
1998 io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1999 ioapic_mem_write, s);
2000 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2001
2002 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2003 qemu_register_reset(ioapic_reset, s);
2004
2005 return s;
2006}
2007#endif /* !VBOX */
2008
2009/* LAPIC */
2010PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2011{
2012 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2013 APICState *s = getLapic(dev);
2014
2015#ifdef VBOX_WITH_SMP_GUESTS
2016 LogRel(("[SMP] apicMMIORead at %llx\n", (uint64_t)GCPhysAddr));
2017#endif
2018
2019 /** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2020 different physical addresses, see #3092) */
2021
2022 STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2023 switch (cb)
2024 {
2025 case 1:
2026 *(uint8_t *)pv = 0;
2027 break;
2028
2029 case 2:
2030 *(uint16_t *)pv = 0;
2031 break;
2032
2033 case 4:
2034 {
2035#if 0 /** @note experimental */
2036#ifndef IN_RING3
2037 uint32_t index = (GCPhysAddr >> 4) & 0xff;
2038
2039 if ( index == 0x08 /* TPR */
2040 && ++s->ulTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2041 {
2042#ifdef IN_RC
2043 pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2044#else
2045 RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2046 pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2047#endif
2048 return VINF_PATM_HC_MMIO_PATCH_READ;
2049 }
2050#endif
2051#endif /* experimental */
2052 APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2053 *(uint32_t *)pv = apic_mem_readl(dev, s, GCPhysAddr);
2054 APIC_UNLOCK(dev);
2055 break;
2056 }
2057 default:
2058 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2059 return VERR_INTERNAL_ERROR;
2060 }
2061 return VINF_SUCCESS;
2062}
2063
2064PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2065{
2066 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2067 APICState *s = getLapic(dev);
2068
2069#ifdef VBOX_WITH_SMP_GUESTS
2070 LogRel(("[SMP] apicMMIOWrite at %llx\n", (uint64_t)GCPhysAddr));
2071#endif
2072
2073 /** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2074 different physical addresses, see #3092) */
2075
2076 STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2077 switch (cb)
2078 {
2079 case 1:
2080 case 2:
2081 /* ignore */
2082 break;
2083
2084 case 4:
2085 {
2086 int rc;
2087 APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2088 rc = apic_mem_writel(dev, s, GCPhysAddr, *(uint32_t *)pv);
2089 APIC_UNLOCK(dev);
2090 return rc;
2091 }
2092
2093 default:
2094 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2095 return VERR_INTERNAL_ERROR;
2096 }
2097 return VINF_SUCCESS;
2098}
2099
2100#ifdef IN_RING3
2101
2102/**
2103 * @copydoc FNSSMDEVSAVEEXEC
2104 */
2105static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2106{
2107 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2108
2109 /* save all APICs data, @todo: is it correct? */
2110 foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
2111
2112 return VINF_SUCCESS;
2113}
2114
2115/**
2116 * @copydoc FNSSMDEVLOADEXEC
2117 */
2118static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2119{
2120 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2121 /* load all APICs data, @todo: is it correct? */
2122 foreach_apic(dev, 0xffffffff,
2123 if (apic_load(pSSMHandle, apic, u32Version))
2124 {
2125 AssertFailed();
2126 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2127 }
2128 );
2129 return VINF_SUCCESS;
2130}
2131
2132/**
2133 * @copydoc FNPDMDEVRESET
2134 */
2135static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2136{
2137 APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2138 APICState *s = getLapic(dev);
2139
2140 APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2141
2142 TMTimerStop(s->CTX_SUFF(pTimer));
2143
2144 apic_init_ipi(s);
2145 /* malc, I've removed the initing duplicated in apic_init_ipi(). This
2146 * arb_id was left over.. */
2147 s->arb_id = 0;
2148 /* Reset should re-enable the APIC. */
2149 s->apicbase = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2150 if (s->phys_id == 0)
2151 s->apicbase |= MSR_IA32_APICBASE_BSP;
2152 dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2153 /* Clear any pending APIC interrupt action flag. */
2154 cpuClearInterrupt(dev, s);
2155 APIC_UNLOCK(dev);
2156}
2157
2158/**
2159 * @copydoc FNPDMDEVRELOCATE
2160 */
2161static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2162{
2163 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2164#ifdef VBOX_WITH_SMP_GUESTS
2165 LogRel(("[SMP]: relocate apic on %llx\n", offDelta));
2166#endif
2167 dev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2168 dev->pApicHlpRC = dev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2169 dev->pLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), dev->pLapicsR3);
2170 foreach_apic(dev, 0xffffffff,
2171 apic->pTimerRC = TMTimerRCPtr(apic->CTX_SUFF(pTimer)));
2172}
2173
2174DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2175{
2176 int i;
2177 memset(apic, 0, sizeof(*apic));
2178 apic->apicbase = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_ENABLE;
2179 /* Mark first CPU as BSP */
2180 if (id == 0)
2181 apic->apicbase |= MSR_IA32_APICBASE_BSP;
2182 for (i = 0; i < APIC_LVT_NB; i++)
2183 apic->lvt[i] = 1 << 16; /* mask LVT */
2184 apic->spurious_vec = 0xff;
2185 apic->phys_id = apic->id = id;
2186}
2187
2188/**
2189 * @copydoc FNPDMDEVCONSTRUCT
2190 */
2191static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2192{
2193 PDMAPICREG ApicReg;
2194 int rc;
2195 uint32_t i;
2196 bool fIOAPIC;
2197 bool fGCEnabled;
2198 bool fR0Enabled;
2199 APICDeviceInfo *pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2200 uint32_t cCpus;
2201 APICState *apic;
2202
2203 /*
2204 * Only single device instance.
2205 */
2206 Assert(iInstance == 0);
2207
2208 /*
2209 * Validate configuration.
2210 */
2211 if (!CFGMR3AreValuesValid(pCfgHandle,
2212 "IOAPIC\0"
2213 "GCEnabled\0"
2214 "R0Enabled\0"
2215 "NumCPUs\0"))
2216 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2217
2218 rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIOAPIC, true);
2219 if (RT_FAILURE(rc))
2220 return PDMDEV_SET_ERROR(pDevIns, rc,
2221 N_("Configuration error: Failed to read \"IOAPIC\""));
2222
2223 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2224 if (RT_FAILURE(rc))
2225 return PDMDEV_SET_ERROR(pDevIns, rc,
2226 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2227
2228 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2229 if (RT_FAILURE(rc))
2230 return PDMDEV_SET_ERROR(pDevIns, rc,
2231 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2232
2233 rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2234 if (RT_FAILURE(rc))
2235 return PDMDEV_SET_ERROR(pDevIns, rc,
2236 N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2237
2238 Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
2239
2240 /*
2241 * Init the data.
2242 */
2243 pThis->pDevInsR3 = pDevIns;
2244 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2245 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2246 pThis->cCpus = cCpus;
2247 /* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2248 pThis->enmVersion = PDMAPICVERSION_APIC;
2249
2250 PVM pVM = PDMDevHlpGetVM(pDevIns);
2251 /*
2252 * We are not freeing this memory, as it's automatically released when guest exits.
2253 */
2254 rc = MMHyperAlloc(pVM, cCpus*sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->pLapicsR3);
2255 if (RT_FAILURE(rc))
2256 return VERR_NO_MEMORY;
2257 pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
2258 pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
2259
2260 for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2261 {
2262 initApicData(apic, i);
2263 apic++;
2264 }
2265
2266 /*
2267 * Register the APIC.
2268 */
2269 ApicReg.u32Version = PDM_APICREG_VERSION;
2270 ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2271 ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2272 ApicReg.pfnSetBaseR3 = apicSetBase;
2273 ApicReg.pfnGetBaseR3 = apicGetBase;
2274 ApicReg.pfnSetTPRR3 = apicSetTPR;
2275 ApicReg.pfnGetTPRR3 = apicGetTPR;
2276 ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2277 ApicReg.pfnReadMSRR3 = apicReadMSR;
2278 ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2279 if (fGCEnabled) {
2280 ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2281 ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2282 ApicReg.pszSetBaseRC = "apicSetBase";
2283 ApicReg.pszGetBaseRC = "apicGetBase";
2284 ApicReg.pszSetTPRRC = "apicSetTPR";
2285 ApicReg.pszGetTPRRC = "apicGetTPR";
2286 ApicReg.pszWriteMSRRC = "apicWriteMSR";
2287 ApicReg.pszReadMSRRC = "apicReadMSR";
2288 ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2289 } else {
2290 ApicReg.pszGetInterruptRC = NULL;
2291 ApicReg.pszHasPendingIrqRC = NULL;
2292 ApicReg.pszSetBaseRC = NULL;
2293 ApicReg.pszGetBaseRC = NULL;
2294 ApicReg.pszSetTPRRC = NULL;
2295 ApicReg.pszGetTPRRC = NULL;
2296 ApicReg.pszWriteMSRRC = NULL;
2297 ApicReg.pszReadMSRRC = NULL;
2298 ApicReg.pszBusDeliverRC = NULL;
2299 }
2300 if (fR0Enabled) {
2301 ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2302 ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2303 ApicReg.pszSetBaseR0 = "apicSetBase";
2304 ApicReg.pszGetBaseR0 = "apicGetBase";
2305 ApicReg.pszSetTPRR0 = "apicSetTPR";
2306 ApicReg.pszGetTPRR0 = "apicGetTPR";
2307 ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2308 ApicReg.pszReadMSRR0 = "apicReadMSR";
2309 ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2310 } else {
2311 ApicReg.pszGetInterruptR0 = NULL;
2312 ApicReg.pszHasPendingIrqR0 = NULL;
2313 ApicReg.pszSetBaseR0 = NULL;
2314 ApicReg.pszGetBaseR0 = NULL;
2315 ApicReg.pszSetTPRR0 = NULL;
2316 ApicReg.pszGetTPRR0 = NULL;
2317 ApicReg.pszWriteMSRR0 = NULL;
2318 ApicReg.pszReadMSRR0 = NULL;
2319 ApicReg.pszBusDeliverR0 = NULL;
2320 }
2321
2322 Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2323 rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2324 if (RT_FAILURE(rc))
2325 {
2326 AssertLogRelMsgFailed(("APICRegister -> %Rrc\n", rc));
2327 return rc;
2328 }
2329
2330 /*
2331 * The the CPUID feature bit.
2332 */
2333 uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2334 PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2335 if (u32Eax >= 1)
2336 {
2337 if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
2338 || ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2339 && u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2340 && u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2341 || ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2342 && u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2343 && u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2344 {
2345 LogRel(("Activating Local APIC\n"));
2346 pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2347 }
2348 }
2349
2350 /*
2351 * Register the MMIO range.
2352 * @todo: may need to rethink for cases when different LAPICs mapped to different address
2353 * (see IA32_APIC_BASE_MSR)
2354 */
2355 rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
2356 apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2357 if (RT_FAILURE(rc))
2358 return rc;
2359
2360 if (fGCEnabled) {
2361 pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2362
2363 rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2364 "apicMMIOWrite", "apicMMIORead", NULL);
2365 if (RT_FAILURE(rc))
2366 return rc;
2367 }
2368
2369 if (fR0Enabled) {
2370 pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2371
2372 rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2373 "apicMMIOWrite", "apicMMIORead", NULL);
2374 if (RT_FAILURE(rc))
2375 return rc;
2376 }
2377
2378 /*
2379 * Create the APIC timers.
2380 */
2381 for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2382 {
2383 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer,
2384 "APIC Timer", &apic->pTimerR3);
2385 if (RT_FAILURE(rc))
2386 return rc;
2387 apic->pTimerR0 = TMTimerR0Ptr(apic->pTimerR3);
2388 apic->pTimerRC = TMTimerRCPtr(apic->pTimerR3);
2389 apic++;
2390 }
2391
2392 /*
2393 * Saved state.
2394 */
2395 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
2396 sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
2397 if (RT_FAILURE(rc))
2398 return rc;
2399
2400#ifdef VBOX_WITH_STATISTICS
2401 /*
2402 * Statistics.
2403 */
2404 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2405 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2406 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2407 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2408 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq, STAMTYPE_COUNTER, "/PDM/APIC/Masked/ActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2409#endif
2410
2411 return VINF_SUCCESS;
2412}
2413
2414
2415/**
2416 * APIC device registration structure.
2417 */
2418const PDMDEVREG g_DeviceAPIC =
2419{
2420 /* u32Version */
2421 PDM_DEVREG_VERSION,
2422 /* szDeviceName */
2423 "apic",
2424 /* szRCMod */
2425 "VBoxDD2GC.gc",
2426 /* szR0Mod */
2427 "VBoxDD2R0.r0",
2428 /* pszDescription */
2429 "Advanced Programmable Interrupt Controller (APIC) Device",
2430 /* fFlags */
2431 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2432 /* fClass */
2433 PDM_DEVREG_CLASS_PIC,
2434 /* cMaxInstances */
2435 1,
2436 /* cbInstance */
2437 sizeof(APICState),
2438 /* pfnConstruct */
2439 apicConstruct,
2440 /* pfnDestruct */
2441 NULL,
2442 /* pfnRelocate */
2443 apicRelocate,
2444 /* pfnIOCtl */
2445 NULL,
2446 /* pfnPowerOn */
2447 NULL,
2448 /* pfnReset */
2449 apicReset,
2450 /* pfnSuspend */
2451 NULL,
2452 /* pfnResume */
2453 NULL,
2454 /* pfnAttach */
2455 NULL,
2456 /* pfnDetach */
2457 NULL,
2458 /* pfnQueryInterface. */
2459 NULL,
2460 /* pfnInitComplete */
2461 NULL,
2462 /* pfnPowerOff */
2463 NULL,
2464 /* pfnSoftReset */
2465 NULL,
2466 /* u32VersionEnd */
2467 PDM_DEVREG_VERSION
2468};
2469
2470#endif /* IN_RING3 */
2471
2472
2473/* IOAPIC */
2474
2475PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2476{
2477 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2478 IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2479
2480 STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2481 switch (cb)
2482 {
2483 case 1:
2484 *(uint8_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2485 break;
2486
2487 case 2:
2488 *(uint16_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2489 break;
2490
2491 case 4:
2492 *(uint32_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2493 break;
2494
2495 default:
2496 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2497 IOAPIC_UNLOCK(s);
2498 return VERR_INTERNAL_ERROR;
2499 }
2500 IOAPIC_UNLOCK(s);
2501 return VINF_SUCCESS;
2502}
2503
2504PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2505{
2506 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2507
2508 STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2509 switch (cb)
2510 {
2511 case 1:
2512 case 2:
2513 case 4:
2514 IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2515 ioapic_mem_writel(s, GCPhysAddr, *(uint32_t *)pv);
2516 IOAPIC_UNLOCK(s);
2517 break;
2518
2519 default:
2520 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2521 return VERR_INTERNAL_ERROR;
2522 }
2523 return VINF_SUCCESS;
2524}
2525
2526PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2527{
2528 IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *);
2529 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2530 LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2531 ioapic_set_irq(pThis, iIrq, iLevel);
2532}
2533
2534
2535#ifdef IN_RING3
2536
2537/**
2538 * @copydoc FNSSMDEVSAVEEXEC
2539 */
2540static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2541{
2542 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2543 ioapic_save(pSSMHandle, s);
2544 return VINF_SUCCESS;
2545}
2546
2547/**
2548 * @copydoc FNSSMDEVLOADEXEC
2549 */
2550static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2551{
2552 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2553
2554 if (ioapic_load(pSSMHandle, s, u32Version)) {
2555 AssertFailed();
2556 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2557 }
2558
2559 return VINF_SUCCESS;
2560}
2561
2562/**
2563 * @copydoc FNPDMDEVRESET
2564 */
2565static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2566{
2567 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2568 s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2569 ioapic_reset(s);
2570 IOAPIC_UNLOCK(s);
2571}
2572
2573/**
2574 * @copydoc FNPDMDEVRELOCATE
2575 */
2576static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2577{
2578 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2579 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2580 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2581}
2582
2583/**
2584 * @copydoc FNPDMDEVCONSTRUCT
2585 */
2586static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2587{
2588 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2589 PDMIOAPICREG IoApicReg;
2590 bool fGCEnabled;
2591 bool fR0Enabled;
2592 int rc;
2593
2594 Assert(iInstance == 0);
2595
2596 /*
2597 * Validate and read the configuration.
2598 */
2599 if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2600 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2601
2602 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2603 if (RT_FAILURE(rc))
2604 return PDMDEV_SET_ERROR(pDevIns, rc,
2605 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2606
2607 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2608 if (RT_FAILURE(rc))
2609 return PDMDEV_SET_ERROR(pDevIns, rc,
2610 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2611 Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2612
2613 /*
2614 * Initialize the state data.
2615 */
2616 s->pDevInsR3 = pDevIns;
2617 s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2618 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2619 ioapic_reset(s);
2620 s->id = 0;
2621
2622 /*
2623 * Register the IOAPIC and get helpers.
2624 */
2625 IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2626 IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2627 IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2628 IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2629 rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2630 if (RT_FAILURE(rc))
2631 {
2632 AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2633 return rc;
2634 }
2635
2636 /*
2637 * Register MMIO callbacks and saved state.
2638 */
2639 rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2640 ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2641 if (RT_FAILURE(rc))
2642 return rc;
2643
2644 if (fGCEnabled) {
2645 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2646
2647 rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2648 "ioapicMMIOWrite", "ioapicMMIORead", NULL);
2649 if (RT_FAILURE(rc))
2650 return rc;
2651 }
2652
2653 if (fR0Enabled) {
2654 s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2655
2656 rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2657 "ioapicMMIOWrite", "ioapicMMIORead", NULL);
2658 if (RT_FAILURE(rc))
2659 return rc;
2660 }
2661
2662 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2663 sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2664 if (RT_FAILURE(rc))
2665 return rc;
2666
2667#ifdef VBOX_WITH_STATISTICS
2668 /*
2669 * Statistics.
2670 */
2671 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2672 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2673 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2674 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2675 PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2676 PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2677#endif
2678
2679 return VINF_SUCCESS;
2680}
2681
2682/**
2683 * IO APIC device registration structure.
2684 */
2685const PDMDEVREG g_DeviceIOAPIC =
2686{
2687 /* u32Version */
2688 PDM_DEVREG_VERSION,
2689 /* szDeviceName */
2690 "ioapic",
2691 /* szRCMod */
2692 "VBoxDD2GC.gc",
2693 /* szR0Mod */
2694 "VBoxDD2R0.r0",
2695 /* pszDescription */
2696 "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2697 /* fFlags */
2698 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2699 /* fClass */
2700 PDM_DEVREG_CLASS_PIC,
2701 /* cMaxInstances */
2702 1,
2703 /* cbInstance */
2704 sizeof(IOAPICState),
2705 /* pfnConstruct */
2706 ioapicConstruct,
2707 /* pfnDestruct */
2708 NULL,
2709 /* pfnRelocate */
2710 ioapicRelocate,
2711 /* pfnIOCtl */
2712 NULL,
2713 /* pfnPowerOn */
2714 NULL,
2715 /* pfnReset */
2716 ioapicReset,
2717 /* pfnSuspend */
2718 NULL,
2719 /* pfnResume */
2720 NULL,
2721 /* pfnAttach */
2722 NULL,
2723 /* pfnDetach */
2724 NULL,
2725 /* pfnQueryInterface. */
2726 NULL,
2727 /* pfnInitComplete */
2728 NULL,
2729 /* pfnPowerOff */
2730 NULL,
2731 /* pfnSoftReset */
2732 NULL,
2733 /* u32VersionEnd */
2734 PDM_DEVREG_VERSION
2735};
2736
2737#endif /* IN_RING3 */
2738#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2739
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