DevAPIC.cpp@ 19468

Last change on this file since 19468 was 19468, checked in by vboxsync, 16 years ago
VMM: better SIPI sending, reschedule to R3 as needed
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 81.0 KB

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1	#ifdef VBOX
2	/* $Id: DevAPIC.cpp 19468 2009-05-07 09:03:15Z vboxsync $ */
3	/** @file
4	* Advanced Programmable Interrupt Controller (APIC) Device and
5	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* apic.c revision 1.5 @@OSETODO
27	*/
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/pdmdev.h>
34
35	#include <VBox/log.h>
36	#include <VBox/stam.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40	#include "Builtins2.h"
41	#include "vl_vbox.h"
42
43	#define MSR_IA32_APICBASE 0x1b
44	#define MSR_IA32_APICBASE_BSP (1<<8)
45	#define MSR_IA32_APICBASE_ENABLE (1<<11)
46	#ifdef VBOX
47	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48	#endif
49	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51	#ifndef EINVAL
52	# define EINVAL 1
53	#endif
54
55	#ifdef _MSC_VER
56	# pragma warning(disable:4244)
57	#endif
58
59	/** @def APIC_LOCK
60	* Acquires the PDM lock. */
61	#define APIC_LOCK(pThis, rc) \
62	do { \
63	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
64	if (rc2 != VINF_SUCCESS) \
65	return rc2; \
66	} while (0)
67
68	/** @def APIC_LOCK_VOID
69	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
70	#define APIC_LOCK_VOID(pThis, rc) \
71	do { \
72	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
73	AssertLogRelRCReturnVoid(rc2); \
74	} while (0)
75
76	/** @def APIC_UNLOCK
77	* Releases the PDM lock. */
78	#define APIC_UNLOCK(pThis) \
79	(pThis)->CTX_SUFF(pApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
80
81	/** @def IOAPIC_LOCK
82	* Acquires the PDM lock. */
83	#define IOAPIC_LOCK(pThis, rc) \
84	do { \
85	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
86	if (rc2 != VINF_SUCCESS) \
87	return rc2; \
88	} while (0)
89
90	/** @def IOAPIC_UNLOCK
91	* Releases the PDM lock. */
92	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
93
94	/** @def LAPIC_BASE
95	* Return address of first LAPIC state. */
96	#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
97
98	#define foreach_apic(dev, mask, code) \
99	do { \
100	uint32_t i; \
101	APICState* apic = LAPIC_BASE(dev); \
102	for (i = 0; i < dev->cCpus; i++) \
103	{ \
104	if (mask & (1 << (apic->id))) \
105	{ \
106	code; \
107	} \
108	apic++; \
109	} \
110	} while (0)
111
112	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
113	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
114	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
115	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
116
117	#endif /* VBOX */
118
119	/*
120	* APIC support
121	*
122	* Copyright (c) 2004-2005 Fabrice Bellard
123	*
124	* This library is free software; you can redistribute it and/or
125	* modify it under the terms of the GNU Lesser General Public
126	* License as published by the Free Software Foundation; either
127	* version 2 of the License, or (at your option) any later version.
128	*
129	* This library is distributed in the hope that it will be useful,
130	* but WITHOUT ANY WARRANTY; without even the implied warranty of
131	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
132	* Lesser General Public License for more details.
133	*
134	* You should have received a copy of the GNU Lesser General Public
135	* License along with this library; if not, write to the Free Software
136	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
137	*/
138	#ifndef VBOX
139	#include "vl.h"
140	#endif
141
142	#define DEBUG_APIC
143	#define DEBUG_IOAPIC
144
145	/* APIC Local Vector Table */
146	#define APIC_LVT_TIMER 0
147	#define APIC_LVT_THERMAL 1
148	#define APIC_LVT_PERFORM 2
149	#define APIC_LVT_LINT0 3
150	#define APIC_LVT_LINT1 4
151	#define APIC_LVT_ERROR 5
152	#define APIC_LVT_NB 6
153
154	/* APIC delivery modes */
155	#define APIC_DM_FIXED 0
156	#define APIC_DM_LOWPRI 1
157	#define APIC_DM_SMI 2
158	#define APIC_DM_NMI 4
159	#define APIC_DM_INIT 5
160	#define APIC_DM_SIPI 6
161	#define APIC_DM_EXTINT 7
162
163	/* APIC destination mode */
164	#define APIC_DESTMODE_FLAT 0xf
165	#define APIC_DESTMODE_CLUSTER 1
166
167	#define APIC_TRIGGER_EDGE 0
168	#define APIC_TRIGGER_LEVEL 1
169
170	#define APIC_LVT_TIMER_PERIODIC (1<<17)
171	#define APIC_LVT_MASKED (1<<16)
172	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
173	#define APIC_LVT_REMOTE_IRR (1<<14)
174	#define APIC_INPUT_POLARITY (1<<13)
175	#define APIC_SEND_PENDING (1<<12)
176
177	#define IOAPIC_NUM_PINS 0x18
178
179	#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181	#define APIC_SV_ENABLE (1 << 8)
182
183	#ifdef VBOX
184	#define APIC_MAX_PATCH_ATTEMPTS 100
185
186	typedef uint32_t PhysApicId;
187	typedef uint32_t LogApicId;
188	#endif
189
190	typedef struct APICState {
191	#ifndef VBOX
192	CPUState *cpu_env;
193	#endif /* !VBOX */
194	uint32_t apicbase;
195	#ifdef VBOX
196	/* Task priority register (interrupt level) */
197	uint32_t tpr;
198	/* Logical APIC id */
199	LogApicId id;
200	/* Physical APIC id */
201	PhysApicId phys_id;
202	/** @todo: is it logical or physical? Not really used anyway now. */
203	PhysApicId arb_id;
204	#else
205	uint8_t tpr;
206	uint8_t id;
207	uint8_t arb_id;
208	#endif
209	uint32_t spurious_vec;
210	uint8_t log_dest;
211	uint8_t dest_mode;
212	uint32_t isr[8]; /* in service register */
213	uint32_t tmr[8]; /* trigger mode register */
214	uint32_t irr[8]; /* interrupt request register */
215	uint32_t lvt[APIC_LVT_NB];
216	uint32_t esr; /* error register */
217	uint32_t icr[2];
218	uint32_t divide_conf;
219	int count_shift;
220	uint32_t initial_count;
221	#ifdef VBOX
222	uint32_t Alignment0;
223	#endif
224	int64_t initial_count_load_time, next_time;
225	#ifndef VBOX
226	QEMUTimer *timer;
227	struct APICState *next_apic;
228	#else
229	/** The APIC timer - R3 Ptr. */
230	PTMTIMERR3 pTimerR3;
231
232	/** The APIC timer - R0 Ptr. */
233	PTMTIMERR0 pTimerR0;
234
235	/** The APIC timer - RC Ptr. */
236	PTMTIMERRC pTimerRC;
237
238	/** Alignment */
239	uint32_t Alignment1;
240	#endif /* VBOX */
241	} APICState;
242
243	struct IOAPICState {
244	uint8_t id;
245	uint8_t ioregsel;
246
247	uint32_t irr;
248	uint64_t ioredtbl[IOAPIC_NUM_PINS];
249
250	#ifdef VBOX
251	/** The device instance - R3 Ptr. */
252	PPDMDEVINSR3 pDevInsR3;
253	/** The IOAPIC helpers - R3 Ptr. */
254	PCPDMIOAPICHLPR3 pIoApicHlpR3;
255
256	/** The device instance - R0 Ptr. */
257	PPDMDEVINSR0 pDevInsR0;
258	/** The IOAPIC helpers - R0 Ptr. */
259	PCPDMIOAPICHLPR0 pIoApicHlpR0;
260
261	/** The device instance - RC Ptr. */
262	PPDMDEVINSRC pDevInsRC;
263	/** The IOAPIC helpers - RC Ptr. */
264	PCPDMIOAPICHLPRC pIoApicHlpRC;
265
266	# ifdef VBOX_WITH_STATISTICS
267	STAMCOUNTER StatMMIOReadGC;
268	STAMCOUNTER StatMMIOReadHC;
269	STAMCOUNTER StatMMIOWriteGC;
270	STAMCOUNTER StatMMIOWriteHC;
271	STAMCOUNTER StatSetIrqGC;
272	STAMCOUNTER StatSetIrqHC;
273	# endif
274	#endif /* VBOX */
275	};
276
277	#ifdef VBOX
278	typedef struct IOAPICState IOAPICState;
279
280	typedef struct
281	{
282	/** The device instance - R3 Ptr. */
283	PPDMDEVINSR3 pDevInsR3;
284	/** The APIC helpers - R3 Ptr. */
285	PCPDMAPICHLPR3 pApicHlpR3;
286	/** LAPICs states - R3 Ptr */
287	RTR3PTR pLapicsR3;
288
289	/** The device instance - R0 Ptr. */
290	PPDMDEVINSR0 pDevInsR0;
291	/** The APIC helpers - R0 Ptr. */
292	PCPDMAPICHLPR0 pApicHlpR0;
293	/** LAPICs states - R0 Ptr */
294	RTR0PTR pLapicsR0;
295
296	/** The device instance - RC Ptr. */
297	PPDMDEVINSRC pDevInsRC;
298	/** The APIC helpers - RC Ptr. */
299	PCPDMAPICHLPRC pApicHlpRC;
300	/** LAPICs states - RC Ptr */
301	RTRCPTR pLapicsRC;
302
303	/** APIC specification version in this virtual hardware configuration. */
304	PDMAPICVERSION enmVersion;
305
306	/** Number of attempts made to optimize TPR accesses. */
307	uint32_t ulTPRPatchAttempts;
308
309	/** Number of CPUs on the system (same as LAPIC count). */
310	uint32_t cCpus;
311
312	# ifdef VBOX_WITH_STATISTICS
313	STAMCOUNTER StatMMIOReadGC;
314	STAMCOUNTER StatMMIOReadHC;
315	STAMCOUNTER StatMMIOWriteGC;
316	STAMCOUNTER StatMMIOWriteHC;
317	STAMCOUNTER StatClearedActiveIrq;
318	# endif
319	} APICDeviceInfo;
320
321	static void apic_eoi(APICDeviceInfo dev, APICState s);
322	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
323	uint8_t dest, uint8_t dest_mode,
324	uint8_t delivery_mode, uint8_t vector_num,
325	uint8_t polarity, uint8_t trigger_mode);
326	static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
327	int64_t current_time);
328	static int apic_get_arb_pri(APICState *s);
329	static int apic_get_ppr(APICState *s);
330	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
331
332
333	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
334	{
335	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
336	return LAPIC_BASE(dev) + id;
337	}
338
339	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
340	{
341	/* LAPIC's array is indexed by CPU id */
342	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
343	return getLapicById(dev, id);
344	}
345
346	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
347	{
348	/* for now we assume LAPIC physical id == CPU id */
349	return VMCPUID(s->phys_id);
350	}
351
352	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s)
353	{
354	Log2(("apic: setting interrupt flag\n"));
355	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns),
356	getCpuFromLapic(dev, s));
357	}
358
359	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
360	{
361	Log2(("apic: clear interrupt flag\n"));
362	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
363	getCpuFromLapic(dev, s));
364	}
365	#ifdef IN_RING3
366	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
367	{
368	Log2(("apic: send SIPI vector=%d\n", vector));
369
370	dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
371	getCpuFromLapic(dev, s),
372	vector);
373	}
374	#endif
375
376	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
377	{
378	switch (dev->enmVersion)
379	{
380	case PDMAPICVERSION_NONE:
381	return 0;
382	case PDMAPICVERSION_APIC:
383	return MSR_IA32_APICBASE_ENABLE;
384	case PDMAPICVERSION_X2APIC:
385	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
386	default:
387	AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
388	return 0;
389	}
390	}
391
392	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
393	{
394	switch (((apic->apicbase) >> 10) & 0x3)
395	{
396	case 0:
397	return PDMAPICVERSION_NONE;
398	case 1:
399	default:
400	/* Invalid */
401	return PDMAPICVERSION_NONE;
402	case 2:
403	return PDMAPICVERSION_APIC;
404	case 3:
405	return PDMAPICVERSION_X2APIC;
406	}
407	}
408
409	#endif /* VBOX */
410
411	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
412	#ifndef VBOX
413	static int apic_io_memory;
414	static APICState *first_local_apic = NULL;
415	static int last_apic_id = 0;
416	#endif /* !VBOX */
417
418	static void apic_init_ipi(APICState *s);
419	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
420	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
421
422	#ifdef VBOX
423	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
424	__BEGIN_DECLS
425	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
426	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
427	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
428	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
429	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
430	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
431	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val);
432	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns);
433	PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
434	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
435	uint8_t u8TriggerMode);
436	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
437	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
438	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
439	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
440	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
441
442	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
443	__END_DECLS
444	#endif /* VBOX */
445
446	#ifndef VBOX
447	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
448	uint8_t vector_num, uint8_t polarity,
449	uint8_t trigger_mode)
450	{
451	APICState *apic_iter;
452	#else /* VBOX */
453	static void apic_bus_deliver(APICDeviceInfo* dev,
454	uint32_t deliver_bitmask, uint8_t delivery_mode,
455	uint8_t vector_num, uint8_t polarity,
456	uint8_t trigger_mode)
457	{
458	#endif /* VBOX */
459
460	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
461	switch (delivery_mode) {
462	case APIC_DM_LOWPRI:
463	{
464	int d = -1;
465	if (deliver_bitmask)
466	d = ffs_bit(deliver_bitmask);
467	if (d >= 0)
468	{
469	APICState* apic = getLapicById(dev, d);
470	apic_set_irq(dev, apic, vector_num, trigger_mode);
471	}
472	return;
473	}
474	case APIC_DM_FIXED:
475	/* XXX: arbitration */
476	break;
477
478	case APIC_DM_SMI:
479	/** @todo: what do we really do with SMI */
480	foreach_apic(dev, deliver_bitmask,
481	cpuSetInterrupt(dev, apic));
482	return;
483
484	case APIC_DM_NMI:
485	/** @todo: what do we really do with NMI */
486	foreach_apic(dev, deliver_bitmask,
487	cpuSetInterrupt(dev, apic));
488	return;
489
490	case APIC_DM_INIT:
491	/* normal INIT IPI sent to processors */
492	#ifdef VBOX
493	foreach_apic(dev, deliver_bitmask,
494	apic_init_ipi(apic));
495	#else
496	for (apic_iter = first_local_apic; apic_iter != NULL;
497	apic_iter = apic_iter->next_apic) {
498	apic_init_ipi(apic_iter);
499	}
500	#endif
501	return;
502
503	case APIC_DM_EXTINT:
504	/* handled in I/O APIC code */
505	break;
506
507	default:
508	return;
509	}
510
511	#ifdef VBOX
512	foreach_apic(dev, deliver_bitmask,
513	apic_set_irq (dev, apic, vector_num, trigger_mode));
514	#else /* VBOX */
515	for (apic_iter = first_local_apic; apic_iter != NULL;
516	apic_iter = apic_iter->next_apic) {
517	if (deliver_bitmask & (1 << apic_iter->id))
518	apic_set_irq(apic_iter, vector_num, trigger_mode);
519	}
520	#endif /* VBOX */
521	}
522
523	#ifndef VBOX
524	void cpu_set_apic_base(CPUState *env, uint64_t val)
525	{
526	APICState *s = env->apic_state;
527	#ifdef DEBUG_APIC
528	Log(("cpu_set_apic_base: %016llx\n", val));
529	#endif
530
531	s->apicbase = (val & 0xfffff000) \|
532	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
533	/* if disabled, cannot be enabled again */
534	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
535	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
536	env->cpuid_features &= ~CPUID_APIC;
537	s->spurious_vec &= ~APIC_SV_ENABLE;
538	}
539	}
540	#else /* VBOX */
541	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
542	{
543	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
544	APICState *s = getLapic(dev);
545	Log(("cpu_set_apic_base: %016RX64\n", val));
546
547	/** @todo: do we need to lock here ? */
548	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
549	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
550	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
551	PDMAPICVERSION oldMode = getApicMode(s);
552	s->apicbase =
553	(val & 0xfffff000) \| /* base */
554	(val & getApicEnableBits(dev)) \| /* mode */
555	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
556	PDMAPICVERSION newMode = getApicMode(s);
557
558	if (oldMode != newMode)
559	{
560	switch (newMode)
561	{
562	case PDMAPICVERSION_NONE:
563	{
564	s->spurious_vec &= ~APIC_SV_ENABLE;
565	/* Clear any pending APIC interrupt action flag. */
566	cpuClearInterrupt(dev, s);
567	/** @todo: why do we do that? */
568	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
569	break;
570	}
571	case PDMAPICVERSION_APIC:
572	/** @todo: map MMIO ranges, if needed */
573	break;
574	case PDMAPICVERSION_X2APIC:
575	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
576	break;
577	default:
578	break;
579	}
580	}
581	/* APIC_UNLOCK(dev); */
582	}
583	#endif /* VBOX */
584	#ifndef VBOX
585
586	uint64_t cpu_get_apic_base(CPUState *env)
587	{
588	APICState *s = env->apic_state;
589	#ifdef DEBUG_APIC
590	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
591	#endif
592	return s->apicbase;
593	}
594
595	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
596	{
597	APICState *s = env->apic_state;
598	s->tpr = (val & 0x0f) << 4;
599	apic_update_irq(s);
600	}
601
602	uint8_t cpu_get_apic_tpr(CPUX86State *env)
603	{
604	APICState *s = env->apic_state;
605	return s->tpr >> 4;
606	}
607
608	static int fls_bit(int value)
609	{
610	unsigned int ret = 0;
611
612	#ifdef HOST_I386
613	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
614	return ret;
615	#else
616	if (value > 0xffff)
617	value >>= 16, ret = 16;
618	if (value > 0xff)
619	value >>= 8, ret += 8;
620	if (value > 0xf)
621	value >>= 4, ret += 4;
622	if (value > 0x3)
623	value >>= 2, ret += 2;
624	return ret + (value >> 1);
625	#endif
626	}
627
628	static inline void set_bit(uint32_t *tab, int index)
629	{
630	int i, mask;
631	i = index >> 5;
632	mask = 1 << (index & 0x1f);
633	tab[i] \|= mask;
634	}
635
636	static inline void reset_bit(uint32_t *tab, int index)
637	{
638	int i, mask;
639	i = index >> 5;
640	mask = 1 << (index & 0x1f);
641	tab[i] &= ~mask;
642	}
643
644
645	#else /* VBOX */
646
647	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
648	{
649	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
650	APICState *s = getLapic(dev);
651	Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
652	return s->apicbase;
653	}
654
655	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
656	{
657	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
658	APICState *s = getLapic(dev);
659	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
660	apic_update_tpr(dev, s, (val & 0x0f) << 4);
661	}
662
663	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
664	{
665	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
666	APICState *s = getLapic(dev);
667	Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
668	return s->tpr >> 4;
669	}
670
671	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
672	{
673	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
674	int rv = VINF_SUCCESS;
675
676	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
677	return VERR_EM_INTERPRETER;
678
679	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
680
681	APICState* apic = getLapicById(dev, idCpu);
682
683	switch (index)
684	{
685	case 0x02:
686	apic->id = (u64Value >> 24);
687	break;
688	case 0x03:
689	break;
690	case 0x08:
691	apic_update_tpr(dev, apic, u64Value);
692	break;
693	case 0x09: case 0x0a:
694	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
695	break;
696	case 0x0b: /* EOI */
697	apic_eoi(dev, apic);
698	break;
699	case 0x0d:
700	apic->log_dest = u64Value >> 24;
701	break;
702	case 0x0e:
703	apic->dest_mode = u64Value >> 28;
704	break;
705	case 0x0f:
706	apic->spurious_vec = u64Value & 0x1ff;
707	apic_update_irq(dev, apic);
708	break;
709	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
710	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
711	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
712	case 0x28:
713	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
714	break;
715
716	case 0x30:
717	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
718	apic->icr[0] = (uint32_t)u64Value;
719	apic->icr[1] = (uint32_t)(u64Value >> 32);
720	rv = apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
721	(apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),
722	(apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
723	break;
724	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
725	{
726	int n = index - 0x32;
727	apic->lvt[n] = u64Value;
728	if (n == APIC_LVT_TIMER)
729	apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
730	}
731	break;
732	case 0x38:
733	apic->initial_count = u64Value;
734	apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
735	apic_timer_update(dev, apic, apic->initial_count_load_time);
736	break;
737	case 0x39:
738	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
739	break;
740	case 0x3e:
741	{
742	int v;
743	apic->divide_conf = u64Value & 0xb;
744	v = (apic->divide_conf & 3) \| ((apic->divide_conf >> 1) & 4);
745	apic->count_shift = (v + 1) & 7;
746	break;
747	}
748	case 0x3f:
749	{
750	/* Self IPI, see x2APIC book 2.4.5 */
751	int vector = u64Value & 0xff;
752	apic_bus_deliver(dev,
753	1 << getLapicById(dev, idCpu)->id /* Self */,
754	0 /* Delivery mode - fixed */,
755	vector,
756	0 /* Polarity - conform to the bus */,
757	0 /* Trigger mode - edge */);
758	break;
759	}
760	default:
761	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
762	apic->esr \|= ESR_ILLEGAL_ADDRESS;
763	break;
764	}
765
766	return rv;
767	}
768	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
769	{
770	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
771
772	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
773	return VERR_EM_INTERPRETER;
774
775	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
776	APICState* apic = getLapicById(dev, idCpu);
777	uint64_t val = 0;
778
779	switch (index)
780	{
781	case 0x02: /* id */
782	val = apic->id << 24;
783	break;
784	case 0x03: /* version */
785	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
786	break;
787	case 0x08:
788	val = apic->tpr;
789	break;
790	case 0x09:
791	val = apic_get_arb_pri(apic);
792	break;
793	case 0x0a:
794	/* ppr */
795	val = apic_get_ppr(apic);
796	break;
797	case 0x0b:
798	val = 0;
799	break;
800	case 0x0d:
801	val = apic->log_dest << 24;
802	break;
803	case 0x0e:
804	/* Bottom 28 bits are always 1 */
805	val = (apic->dest_mode << 28) \| 0xfffffff;
806	break;
807	case 0x0f:
808	val = apic->spurious_vec;
809	break;
810	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
811	val = apic->isr[index & 7];
812	break;
813	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
814	val = apic->tmr[index & 7];
815	break;
816	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
817	val = apic->irr[index & 7];
818	break;
819	case 0x28:
820	val = apic->esr;
821	break;
822	case 0x30:
823	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
824	val = ((uint64_t)apic->icr[0x31] << 32) \| apic->icr[0x30];
825	break;
826	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
827	val = apic->lvt[index - 0x32];
828	break;
829	case 0x38:
830	val = apic->initial_count;
831	break;
832	case 0x39:
833	val = apic_get_current_count(dev, apic);
834	break;
835	case 0x3e:
836	val = apic->divide_conf;
837	break;
838	case 0x3f:
839	/* Self IPI register is write only */
840	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
841	break;
842	default:
843	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
844	apic->esr \|= ESR_ILLEGAL_ADDRESS;
845	val = 0;
846	break;
847	}
848	*pu64Value = val;
849	return VINF_SUCCESS;
850	}
851
852	/**
853	* More or less private interface between IOAPIC, only PDM is responsible
854	* for connecting the two devices.
855	*/
856	PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
857	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
858	uint8_t u8TriggerMode)
859	{
860	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
861	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
862	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
863	apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
864	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
865	}
866
867	#endif /* VBOX */
868
869	/* return -1 if no bit is set */
870	static int get_highest_priority_int(uint32_t *tab)
871	{
872	int i;
873	for(i = 7; i >= 0; i--) {
874	if (tab[i] != 0) {
875	return i * 32 + fls_bit(tab[i]);
876	}
877	}
878	return -1;
879	}
880
881	static int apic_get_ppr(APICState *s)
882	{
883	int tpr, isrv, ppr;
884
885	tpr = (s->tpr >> 4);
886	isrv = get_highest_priority_int(s->isr);
887	if (isrv < 0)
888	isrv = 0;
889	isrv >>= 4;
890	if (tpr >= isrv)
891	ppr = s->tpr;
892	else
893	ppr = isrv << 4;
894	return ppr;
895	}
896
897	static int apic_get_ppr_zero_tpr(APICState *s)
898	{
899	int isrv;
900
901	isrv = get_highest_priority_int(s->isr);
902	if (isrv < 0)
903	isrv = 0;
904	return isrv;
905	}
906
907	static int apic_get_arb_pri(APICState *s)
908	{
909	/* XXX: arbitration */
910	return 0;
911	}
912
913	/* signal the CPU if an irq is pending */
914	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
915	{
916	int irrv, ppr;
917	if (!(s->spurious_vec & APIC_SV_ENABLE))
918	#ifdef VBOX
919	{
920	/* Clear any pending APIC interrupt action flag. */
921	cpuClearInterrupt(dev, s);
922	return false;
923	}
924	#else
925	return false;
926	#endif /* VBOX */
927	irrv = get_highest_priority_int(s->irr);
928	if (irrv < 0)
929	return false;
930	ppr = apic_get_ppr(s);
931	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
932	return false;
933	#ifndef VBOX
934	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
935	#else
936	cpuSetInterrupt(dev, s);
937	return true;
938	#endif
939	}
940
941	#ifdef VBOX
942
943	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
944	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
945	{
946	int irrv, ppr;
947	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
948	if (!dev)
949	return false;
950	APICState *s = getLapic(dev);
951
952	/*
953	* All our callbacks now come from single IOAPIC, thus locking
954	* seems to be excessive now (@todo: check)
955	*/
956	irrv = get_highest_priority_int(s->irr);
957	if (irrv < 0)
958	return false;
959
960	ppr = apic_get_ppr_zero_tpr(s);
961
962	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
963	return false;
964
965	return true;
966	}
967
968	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
969	{
970	bool fIrqIsActive = false;
971	bool fIrqWasActive = false;
972
973	fIrqWasActive = apic_update_irq(dev, s);
974	s->tpr = val;
975	fIrqIsActive = apic_update_irq(dev, s);
976
977	/* If an interrupt is pending and now masked, then clear the FF flag. */
978	if (fIrqWasActive && !fIrqIsActive)
979	{
980	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
981	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
982	cpuClearInterrupt(dev, s);
983	}
984	}
985	#endif
986
987	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
988	{
989	LogFlow(("apic_set_irq vector=%x, trigger_mode=%x\n", vector_num, trigger_mode));
990	set_bit(s->irr, vector_num);
991	if (trigger_mode)
992	set_bit(s->tmr, vector_num);
993	else
994	reset_bit(s->tmr, vector_num);
995	apic_update_irq(dev, s);
996	}
997
998	static void apic_eoi(APICDeviceInfo dev, APICState s)
999	{
1000	int isrv;
1001	isrv = get_highest_priority_int(s->isr);
1002	if (isrv < 0)
1003	return;
1004	reset_bit(s->isr, isrv);
1005	LogFlow(("apic_eoi isrv=%x\n", isrv));
1006	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1007	set the remote IRR bit for level triggered interrupts. */
1008	apic_update_irq(dev, s);
1009	}
1010
1011	#ifndef VBOX
1012	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1013	#else /* VBOX */
1014	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1015	#endif /* VBOX */
1016	{
1017	uint32_t mask = 0;
1018
1019	if (dest_mode == 0)
1020	{
1021	if (dest == 0xff)
1022	mask = 0xff;
1023	else
1024	mask = 1 << dest;
1025	}
1026	else
1027	{
1028	APICState *apic = LAPIC_BASE(dev);
1029	uint32_t i;
1030
1031	/* XXX: cluster mode */
1032	for(i = 0; i < dev->cCpus; i++)
1033	{
1034	if (apic->dest_mode == 0xf)
1035	{
1036	if (dest & apic->log_dest)
1037	mask \|= (1 << apic->id);
1038	}
1039	else if (apic->dest_mode == 0x0)
1040	{
1041	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1042	&&
1043	(dest & apic->log_dest & 0x0f))
1044	{
1045	mask \|= (1 << i);
1046	}
1047	}
1048	}
1049	apic++;
1050	}
1051
1052	return mask;
1053	}
1054
1055	static void apic_init_ipi(APICState *s)
1056	{
1057	int i;
1058
1059	for(i = 0; i < APIC_LVT_NB; i++)
1060	s->lvt[i] = 1 << 16; /* mask LVT */
1061	s->tpr = 0;
1062	s->spurious_vec = 0xff;
1063	s->log_dest = 0;
1064	s->dest_mode = 0xff;
1065	memset(s->isr, 0, sizeof(s->isr));
1066	memset(s->tmr, 0, sizeof(s->tmr));
1067	memset(s->irr, 0, sizeof(s->irr));
1068	s->esr = 0;
1069	memset(s->icr, 0, sizeof(s->icr));
1070	s->divide_conf = 0;
1071	s->count_shift = 0;
1072	s->initial_count = 0;
1073	s->initial_count_load_time = 0;
1074	s->next_time = 0;
1075
1076	#ifdef VBOX
1077	/** @todo reset CPU, activate wait for sipi mode for application processors */
1078	/** Must be dealt with in ring 3 */
1079	#endif
1080	}
1081
1082	#ifdef IN_RING3
1083	/* send a SIPI message to the CPU to start it */
1084	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1085	{
1086	#ifndef VBOX
1087	CPUState *env = s->cpu_env;
1088	if (!env->halted)
1089	return;
1090	env->eip = 0;
1091	cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1092	0xffff, 0);
1093	env->halted = 0;
1094	#else
1095	/** @todo: init CPUs */
1096	LogRel(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->id));
1097	cpuSendSipi(dev, s, vector_num);
1098	#endif
1099	}
1100	#endif
1101
1102	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1103	uint8_t dest, uint8_t dest_mode,
1104	uint8_t delivery_mode, uint8_t vector_num,
1105	uint8_t polarity, uint8_t trigger_mode)
1106	{
1107	uint32_t deliver_bitmask = 0;
1108	int dest_shorthand = (s->icr[0] >> 18) & 3;
1109	#ifndef VBOX
1110	APICState *apic_iter;
1111	#endif /* !VBOX */
1112
1113	LogFlow(("apic_deliver dest=%x dest_mode=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, delivery_mode, vector_num, polarity, trigger_mode));
1114
1115	switch (dest_shorthand) {
1116	case 0:
1117	#ifndef VBOX
1118	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1119	#else /* VBOX */
1120	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1121	#endif /* !VBOX */
1122	break;
1123	case 1:
1124	deliver_bitmask = (1 << s->id);
1125	break;
1126	case 2:
1127	deliver_bitmask = 0xffffffff;
1128	break;
1129	case 3:
1130	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1131	break;
1132	}
1133
1134	switch (delivery_mode) {
1135	case APIC_DM_LOWPRI:
1136	/* XXX: serch for focus processor, arbitration */
1137	dest = s->id;
1138
1139	case APIC_DM_INIT:
1140	{
1141	int trig_mode = (s->icr[0] >> 15) & 1;
1142	int level = (s->icr[0] >> 14) & 1;
1143	if (level == 0 && trig_mode == 1) {
1144	#ifdef VBOX
1145	foreach_apic(dev, deliver_bitmask,
1146	apic->arb_id = apic->id);
1147	return VINF_SUCCESS;
1148	#else /* !VBOX */
1149	for (apic_iter = first_local_apic; apic_iter != NULL;
1150	apic_iter = apic_iter->next_apic) {
1151	if (deliver_bitmask & (1 << apic_iter->id)) {
1152	apic_iter->arb_id = apic_iter->id;
1153	}
1154	}
1155	return;
1156	#endif /* !VBOX */
1157	}
1158	}
1159	break;
1160
1161	case APIC_DM_SIPI:
1162	#ifndef VBOX
1163	for (apic_iter = first_local_apic; apic_iter != NULL;
1164	apic_iter = apic_iter->next_apic) {
1165	if (deliver_bitmask & (1 << apic_iter->id)) {
1166	/* XXX: SMP support */
1167	/* apic_startup(apic_iter); */
1168	}
1169	}
1170	return;
1171	#else
1172	# ifdef IN_RING3
1173
1174	foreach_apic(dev, deliver_bitmask,
1175	apic_startup(dev, apic, vector_num));
1176	return VINF_SUCCESS;
1177	# else
1178	/* We shall send SIPI only in R3, R0 calls should be
1179	rescheduled to R3 */
1180	return VINF_IOM_HC_MMIO_WRITE;
1181	# endif
1182	#endif /* !VBOX */
1183	}
1184
1185	#ifndef VBOX
1186	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1187	trigger_mode);
1188	#else /* VBOX */
1189	apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num, polarity,
1190	trigger_mode);
1191	return VINF_SUCCESS;
1192	#endif /* VBOX */
1193	}
1194
1195
1196	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1197	{
1198	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1199	/* if the APIC is not installed or enabled, we let the 8259 handle the
1200	IRQs */
1201	if (!dev)
1202	{
1203	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1204	return -1;
1205	}
1206
1207	APIC_LOCK(dev, VERR_INTERNAL_ERROR);
1208
1209	APICState *s = getLapic(dev);
1210	int intno;
1211
1212	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1213	Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
1214	intno = -1;
1215	goto done;
1216	}
1217
1218	/* XXX: spurious IRQ handling */
1219	intno = get_highest_priority_int(s->irr);
1220	if (intno < 0) {
1221	Log(("apic_get_interrupt: returns -1 (irr)\n"));
1222	intno = -1;
1223	goto done;
1224	}
1225	if (s->tpr && (uint32_t)intno <= s->tpr) {
1226	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1227	intno = s->spurious_vec & 0xff;
1228	goto done;
1229	}
1230	reset_bit(s->irr, intno);
1231	set_bit(s->isr, intno);
1232	apic_update_irq(dev, s);
1233	LogFlow(("apic_get_interrupt: returns %d\n", intno));
1234	done:
1235	APIC_UNLOCK(dev);
1236	return intno;
1237	}
1238
1239	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
1240	{
1241	int64_t d;
1242	uint32_t val;
1243	#ifndef VBOX
1244	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1245	s->count_shift;
1246	#else /* VBOX */
1247	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1248	s->count_shift;
1249	#endif /* VBOX */
1250	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1251	/* periodic */
1252	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1253	} else {
1254	if (d >= s->initial_count)
1255	val = 0;
1256	else
1257	val = s->initial_count - d;
1258	}
1259	return val;
1260	}
1261
1262	static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1263	{
1264	int64_t next_time, d;
1265
1266	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1267	d = (current_time - s->initial_count_load_time) >>
1268	s->count_shift;
1269	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1270	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1271	} else {
1272	if (d >= s->initial_count)
1273	goto no_timer;
1274	d = (uint64_t)s->initial_count + 1;
1275	}
1276	next_time = s->initial_count_load_time + (d << s->count_shift);
1277	#ifndef VBOX
1278	qemu_mod_timer(s->timer, next_time);
1279	#else
1280	TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1281	#endif
1282	s->next_time = next_time;
1283	} else {
1284	no_timer:
1285	#ifndef VBOX
1286	qemu_del_timer(s->timer);
1287	#else
1288	TMTimerStop(s->CTX_SUFF(pTimer));
1289	#endif
1290	}
1291	}
1292
1293	#ifdef IN_RING3
1294	#ifndef VBOX
1295	static void apic_timer(void *opaque)
1296	{
1297	APICState *s = opaque;
1298	#else /* VBOX */
1299	static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1300	{
1301	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1302	APICState *s = getLapic(dev);
1303
1304	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
1305	#endif /* VBOX */
1306
1307	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1308	LogFlow(("apic_timer: trigger irq\n"));
1309	apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1310	}
1311	apic_timer_update(dev, s, s->next_time);
1312
1313	#ifdef VBOX
1314	APIC_UNLOCK(dev);
1315	#endif
1316	}
1317	#endif /* IN_RING3 */
1318
1319	#ifndef VBOX
1320	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1321	{
1322	return 0;
1323	}
1324	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1325	{
1326	return 0;
1327	}
1328
1329	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1330	{
1331	}
1332
1333	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1334	{
1335	}
1336	#endif /* !VBOX */
1337
1338
1339	#ifndef VBOX
1340	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1341	{
1342	CPUState *env;
1343	APICState *s;
1344	#else /* VBOX */
1345	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1346	{
1347	#endif /* VBOX */
1348	uint32_t val;
1349	int index;
1350
1351	#ifndef VBOX
1352	env = cpu_single_env;
1353	if (!env)
1354	return 0;
1355	s = env->apic_state;
1356	#endif /* !VBOX */
1357
1358	index = (addr >> 4) & 0xff;
1359	switch(index) {
1360	case 0x02: /* id */
1361	val = s->id << 24;
1362	break;
1363	case 0x03: /* version */
1364	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1365	break;
1366	case 0x08:
1367	val = s->tpr;
1368	break;
1369	case 0x09:
1370	val = apic_get_arb_pri(s);
1371	break;
1372	case 0x0a:
1373	/* ppr */
1374	val = apic_get_ppr(s);
1375	break;
1376	case 0x0b:
1377	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1378	val = 0;
1379	break;
1380	case 0x0d:
1381	val = s->log_dest << 24;
1382	break;
1383	case 0x0e:
1384	#ifdef VBOX
1385	/* Bottom 28 bits are always 1 */
1386	val = (s->dest_mode << 28) \| 0xfffffff;
1387	#else
1388	val = s->dest_mode << 28;
1389	#endif
1390	break;
1391	case 0x0f:
1392	val = s->spurious_vec;
1393	break;
1394	#ifndef VBOX
1395	case 0x10 ... 0x17:
1396	#else /* VBOX */
1397	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1398	#endif /* VBOX */
1399	val = s->isr[index & 7];
1400	break;
1401	#ifndef VBOX
1402	case 0x18 ... 0x1f:
1403	#else /* VBOX */
1404	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1405	#endif /* VBOX */
1406	val = s->tmr[index & 7];
1407	break;
1408	#ifndef VBOX
1409	case 0x20 ... 0x27:
1410	#else /* VBOX */
1411	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1412	#endif /* VBOX */
1413	val = s->irr[index & 7];
1414	break;
1415	case 0x28:
1416	val = s->esr;
1417	break;
1418	case 0x30:
1419	case 0x31:
1420	val = s->icr[index & 1];
1421	break;
1422	#ifndef VBOX
1423	case 0x32 ... 0x37:
1424	#else /* VBOX */
1425	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1426	#endif /* VBOX */
1427	val = s->lvt[index - 0x32];
1428	break;
1429	case 0x38:
1430	val = s->initial_count;
1431	break;
1432	case 0x39:
1433	val = apic_get_current_count(dev, s);
1434	break;
1435	case 0x3e:
1436	val = s->divide_conf;
1437	break;
1438	default:
1439	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1440	s->esr \|= ESR_ILLEGAL_ADDRESS;
1441	val = 0;
1442	break;
1443	}
1444	#ifdef DEBUG_APIC
1445	Log(("APIC read: %08x = %08x\n", (uint32_t)addr, val));
1446	#endif
1447	return val;
1448	}
1449
1450	#ifndef VBOX
1451	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1452	{
1453	CPUState *env;
1454	APICState *s;
1455	#else /* VBOX */
1456	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1457	{
1458	int rv = VINF_SUCCESS;
1459	#endif /* VBOX */
1460	int index;
1461
1462	#ifndef VBOX
1463	env = cpu_single_env;
1464	if (!env)
1465	return;
1466	s = env->apic_state;
1467	#endif /* !VBOX */
1468
1469	#ifdef DEBUG_APIC
1470	Log(("APIC write: %08x = %08x\n", (uint32_t)addr, val));
1471	#endif
1472
1473	index = (addr >> 4) & 0xff;
1474	switch(index) {
1475	case 0x02:
1476	s->id = (val >> 24);
1477	break;
1478	case 0x03:
1479	Log(("apic_mem_writel: write to version register; ignored\n"));
1480	break;
1481	case 0x08:
1482	#ifdef VBOX
1483	apic_update_tpr(dev, s, val);
1484	#else
1485	s->tpr = val;
1486	apic_update_irq(s);
1487	#endif
1488	break;
1489	case 0x09:
1490	case 0x0a:
1491	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1492	break;
1493	case 0x0b: /* EOI */
1494	apic_eoi(dev, s);
1495	break;
1496	case 0x0d:
1497	s->log_dest = val >> 24;
1498	break;
1499	case 0x0e:
1500	s->dest_mode = val >> 28;
1501	break;
1502	case 0x0f:
1503	s->spurious_vec = val & 0x1ff;
1504	apic_update_irq(dev, s);
1505	break;
1506	#ifndef VBOX
1507	case 0x10 ... 0x17:
1508	case 0x18 ... 0x1f:
1509	case 0x20 ... 0x27:
1510	case 0x28:
1511	#else
1512	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1513	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1514	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1515	case 0x28:
1516	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1517	#endif
1518	break;
1519
1520	case 0x30:
1521	s->icr[0] = val;
1522	rv = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1523	(s->icr[0] >> 11) & 1,
1524	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1525	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1526	break;
1527	case 0x31:
1528	s->icr[1] = val;
1529	break;
1530	#ifndef VBOX
1531	case 0x32 ... 0x37:
1532	#else /* VBOX */
1533	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1534	#endif /* VBOX */
1535	{
1536	int n = index - 0x32;
1537	s->lvt[n] = val;
1538	if (n == APIC_LVT_TIMER)
1539	#ifndef VBOX
1540	apic_timer_update(s, qemu_get_clock(vm_clock));
1541	#else /* VBOX */
1542	apic_timer_update(dev, s, TMTimerGet(s->CTX_SUFF(pTimer)));
1543	#endif /* VBOX*/
1544	}
1545	break;
1546	case 0x38:
1547	s->initial_count = val;
1548	#ifndef VBOX
1549	s->initial_count_load_time = qemu_get_clock(vm_clock);
1550	#else /* VBOX */
1551	s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
1552	#endif /* VBOX*/
1553	apic_timer_update(dev, s, s->initial_count_load_time);
1554	break;
1555	case 0x39:
1556	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1557	break;
1558	case 0x3e:
1559	{
1560	int v;
1561	s->divide_conf = val & 0xb;
1562	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1563	s->count_shift = (v + 1) & 7;
1564	}
1565	break;
1566	default:
1567	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1568	s->esr \|= ESR_ILLEGAL_ADDRESS;
1569	break;
1570	}
1571	#ifdef VBOX
1572	return rv;
1573	#endif
1574	}
1575
1576	#ifdef IN_RING3
1577
1578	static void apic_save(QEMUFile f, void opaque)
1579	{
1580	APICState s = (APICState)opaque;
1581	int i;
1582
1583	qemu_put_be32s(f, &s->apicbase);
1584	#ifdef VBOX
1585	qemu_put_be32s(f, &s->id);
1586	qemu_put_be32s(f, &s->phys_id);
1587	qemu_put_be32s(f, &s->arb_id);
1588	qemu_put_be32s(f, &s->tpr);
1589	#else
1590	qemu_put_8s(f, &s->id);
1591	qemu_put_8s(f, &s->arb_id);
1592	qemu_put_8s(f, &s->tpr);
1593	#endif
1594	qemu_put_be32s(f, &s->spurious_vec);
1595	qemu_put_8s(f, &s->log_dest);
1596	qemu_put_8s(f, &s->dest_mode);
1597	for (i = 0; i < 8; i++) {
1598	qemu_put_be32s(f, &s->isr[i]);
1599	qemu_put_be32s(f, &s->tmr[i]);
1600	qemu_put_be32s(f, &s->irr[i]);
1601	}
1602	for (i = 0; i < APIC_LVT_NB; i++) {
1603	qemu_put_be32s(f, &s->lvt[i]);
1604	}
1605	qemu_put_be32s(f, &s->esr);
1606	qemu_put_be32s(f, &s->icr[0]);
1607	qemu_put_be32s(f, &s->icr[1]);
1608	qemu_put_be32s(f, &s->divide_conf);
1609	qemu_put_be32s(f, &s->count_shift);
1610	qemu_put_be32s(f, &s->initial_count);
1611	qemu_put_be64s(f, &s->initial_count_load_time);
1612	qemu_put_be64s(f, &s->next_time);
1613
1614	#ifdef VBOX
1615	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1616	#endif
1617	}
1618
1619	static int apic_load(QEMUFile f, void opaque, int version_id)
1620	{
1621	APICState s = (APICState)opaque;
1622	int i;
1623
1624	#ifdef VBOX
1625	if ((version_id < 1) \|\| (version_id > 2))
1626	return -EINVAL;
1627
1628	/* XXX: what if the base changes? (registered memory regions) */
1629	qemu_get_be32s(f, &s->apicbase);
1630
1631	switch (version_id)
1632	{
1633	case 1:
1634	{
1635	uint8_t val = 0;
1636	qemu_get_8s(f, &val);
1637	s->id = val;
1638	/* UP only in old saved states */
1639	s->phys_id = 0;
1640	qemu_get_8s(f, &val);
1641	s->arb_id = val;
1642	break;
1643	}
1644	case 2:
1645	qemu_get_be32s(f, &s->id);
1646	qemu_get_be32s(f, &s->phys_id);
1647	qemu_get_be32s(f, &s->arb_id);
1648	break;
1649	}
1650	qemu_get_be32s(f, &s->tpr);
1651	#else
1652	if (version_id != 1)
1653	return -EINVAL;
1654
1655	/* XXX: what if the base changes? (registered memory regions) */
1656	qemu_get_be32s(f, &s->apicbase);
1657	qemu_get_8s(f, &s->id);
1658	qemu_get_8s(f, &s->arb_id);
1659	qemu_get_8s(f, &s->tpr);
1660	#endif
1661	qemu_get_be32s(f, &s->spurious_vec);
1662	qemu_get_8s(f, &s->log_dest);
1663	qemu_get_8s(f, &s->dest_mode);
1664	for (i = 0; i < 8; i++) {
1665	qemu_get_be32s(f, &s->isr[i]);
1666	qemu_get_be32s(f, &s->tmr[i]);
1667	qemu_get_be32s(f, &s->irr[i]);
1668	}
1669	for (i = 0; i < APIC_LVT_NB; i++) {
1670	qemu_get_be32s(f, &s->lvt[i]);
1671	}
1672	qemu_get_be32s(f, &s->esr);
1673	qemu_get_be32s(f, &s->icr[0]);
1674	qemu_get_be32s(f, &s->icr[1]);
1675	qemu_get_be32s(f, &s->divide_conf);
1676	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1677	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1678	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1679	qemu_get_be64s(f, (uint64_t *)&s->next_time);
1680
1681	#ifdef VBOX
1682	TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1683	#endif
1684
1685	return VINF_SUCCESS;
1686	}
1687	#ifndef VBOX
1688	static void apic_reset(void *opaque)
1689	{
1690	APICState s = (APICState)opaque;
1691	apic_init_ipi(s);
1692	}
1693	#endif
1694
1695	#endif /* IN_RING3 */
1696
1697	#ifndef VBOX
1698	static CPUReadMemoryFunc *apic_mem_read[3] = {
1699	apic_mem_readb,
1700	apic_mem_readw,
1701	apic_mem_readl,
1702	};
1703
1704	static CPUWriteMemoryFunc *apic_mem_write[3] = {
1705	apic_mem_writeb,
1706	apic_mem_writew,
1707	apic_mem_writel,
1708	};
1709
1710	int apic_init(CPUState *env)
1711	{
1712	APICState *s;
1713
1714	s = qemu_mallocz(sizeof(APICState));
1715	if (!s)
1716	return -1;
1717	env->apic_state = s;
1718	apic_init_ipi(s);
1719	s->id = last_apic_id++;
1720	s->cpu_env = env;
1721	s->apicbase = 0xfee00000 \|
1722	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
1723
1724	/* XXX: mapping more APICs at the same memory location */
1725	if (apic_io_memory == 0) {
1726	/* NOTE: the APIC is directly connected to the CPU - it is not
1727	on the global memory bus. */
1728	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1729	apic_mem_write, NULL);
1730	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1731	apic_io_memory);
1732	}
1733	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1734
1735	register_savevm("apic", 0, 1, apic_save, apic_load, s);
1736	qemu_register_reset(apic_reset, s);
1737
1738	s->next_apic = first_local_apic;
1739	first_local_apic = s;
1740
1741	return 0;
1742	}
1743	#endif /* !VBOX */
1744
1745	static void ioapic_service(IOAPICState *s)
1746	{
1747	uint8_t i;
1748	uint8_t trig_mode;
1749	uint8_t vector;
1750	uint8_t delivery_mode;
1751	uint32_t mask;
1752	uint64_t entry;
1753	uint8_t dest;
1754	uint8_t dest_mode;
1755	uint8_t polarity;
1756
1757	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1758	mask = 1 << i;
1759	if (s->irr & mask) {
1760	entry = s->ioredtbl[i];
1761	if (!(entry & APIC_LVT_MASKED)) {
1762	trig_mode = ((entry >> 15) & 1);
1763	dest = entry >> 56;
1764	dest_mode = (entry >> 11) & 1;
1765	delivery_mode = (entry >> 8) & 7;
1766	polarity = (entry >> 13) & 1;
1767	if (trig_mode == APIC_TRIGGER_EDGE)
1768	s->irr &= ~mask;
1769	if (delivery_mode == APIC_DM_EXTINT)
1770	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1771	vector = pic_read_irq(isa_pic);
1772	#else /* VBOX */
1773	{
1774	AssertMsgFailed(("Delivery mode ExtINT"));
1775	vector = 0xff; /* incorrect but shuts up gcc. */
1776	}
1777	#endif /* VBOX */
1778	else
1779	vector = entry & 0xff;
1780
1781	#ifndef VBOX
1782	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1783	delivery_mode, vector, polarity, trig_mode);
1784	#else /* VBOX */
1785	s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1786	dest,
1787	dest_mode,
1788	delivery_mode,
1789	vector,
1790	polarity,
1791	trig_mode);
1792	#endif /* VBOX */
1793	}
1794	}
1795	}
1796	}
1797
1798	#ifdef VBOX
1799	static
1800	#endif
1801	void ioapic_set_irq(void *opaque, int vector, int level)
1802	{
1803	IOAPICState s = (IOAPICState)opaque;
1804
1805	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1806	uint32_t mask = 1 << vector;
1807	uint64_t entry = s->ioredtbl[vector];
1808
1809	if ((entry >> 15) & 1) {
1810	/* level triggered */
1811	if (level) {
1812	s->irr \|= mask;
1813	ioapic_service(s);
1814	#ifdef VBOX
1815	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1816	s->irr &= ~mask;
1817	}
1818	#endif
1819	} else {
1820	s->irr &= ~mask;
1821	}
1822	} else {
1823	/* edge triggered */
1824	if (level) {
1825	s->irr \|= mask;
1826	ioapic_service(s);
1827	}
1828	}
1829	}
1830	}
1831
1832	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1833	{
1834	IOAPICState s = (IOAPICState)opaque;
1835	int index;
1836	uint32_t val = 0;
1837
1838	addr &= 0xff;
1839	if (addr == 0x00) {
1840	val = s->ioregsel;
1841	} else if (addr == 0x10) {
1842	switch (s->ioregsel) {
1843	case 0x00:
1844	val = s->id << 24;
1845	break;
1846	case 0x01:
1847	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1848	break;
1849	case 0x02:
1850	val = 0;
1851	break;
1852	default:
1853	index = (s->ioregsel - 0x10) >> 1;
1854	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1855	if (s->ioregsel & 1)
1856	val = s->ioredtbl[index] >> 32;
1857	else
1858	val = s->ioredtbl[index] & 0xffffffff;
1859	}
1860	}
1861	#ifdef DEBUG_IOAPIC
1862	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1863	#endif
1864	}
1865	return val;
1866	}
1867
1868	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1869	{
1870	IOAPICState s = (IOAPICState)opaque;
1871	int index;
1872
1873	addr &= 0xff;
1874	if (addr == 0x00) {
1875	s->ioregsel = val;
1876	return;
1877	} else if (addr == 0x10) {
1878	#ifdef DEBUG_IOAPIC
1879	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1880	#endif
1881	switch (s->ioregsel) {
1882	case 0x00:
1883	s->id = (val >> 24) & 0xff;
1884	return;
1885	case 0x01:
1886	case 0x02:
1887	return;
1888	default:
1889	index = (s->ioregsel - 0x10) >> 1;
1890	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1891	if (s->ioregsel & 1) {
1892	s->ioredtbl[index] &= 0xffffffff;
1893	s->ioredtbl[index] \|= (uint64_t)val << 32;
1894	} else {
1895	#ifdef VBOX
1896	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1897	uint8_t vec = val & 0xff;
1898	if ((val & APIC_LVT_MASKED) \|\|
1899	((vec >= 0x10) && (vec < 0xff)))
1900	{
1901	s->ioredtbl[index] &= ~0xffffffffULL;
1902	s->ioredtbl[index] \|= val;
1903	}
1904	else
1905	{
1906	/*
1907	* Linux 2.6 kernels has pretty strange function
1908	* unlock_ExtINT_logic() which writes
1909	* absolutely bogus (all 0) value into the vector
1910	* with pretty vague explanation why.
1911	* So we just ignore such writes.
1912	*/
1913	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1914	}
1915	}
1916	#else
1917	s->ioredtbl[index] &= ~0xffffffffULL;
1918	s->ioredtbl[index] \|= val;
1919	#endif
1920	ioapic_service(s);
1921	}
1922	}
1923	}
1924	}
1925
1926	#ifdef IN_RING3
1927
1928	static void ioapic_save(QEMUFile f, void opaque)
1929	{
1930	IOAPICState s = (IOAPICState)opaque;
1931	int i;
1932
1933	qemu_put_8s(f, &s->id);
1934	qemu_put_8s(f, &s->ioregsel);
1935	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1936	qemu_put_be64s(f, &s->ioredtbl[i]);
1937	}
1938	}
1939
1940	static int ioapic_load(QEMUFile f, void opaque, int version_id)
1941	{
1942	IOAPICState s = (IOAPICState)opaque;
1943	int i;
1944
1945	if (version_id != 1)
1946	return -EINVAL;
1947
1948	qemu_get_8s(f, &s->id);
1949	qemu_get_8s(f, &s->ioregsel);
1950	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1951	qemu_get_be64s(f, &s->ioredtbl[i]);
1952	}
1953	return 0;
1954	}
1955
1956	static void ioapic_reset(void *opaque)
1957	{
1958	IOAPICState s = (IOAPICState)opaque;
1959	#ifdef VBOX
1960	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1961	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1962	#endif
1963	int i;
1964
1965	memset(s, 0, sizeof(*s));
1966	for(i = 0; i < IOAPIC_NUM_PINS; i++)
1967	s->ioredtbl[i] = 1 << 16; /* mask LVT */
1968
1969	#ifdef VBOX
1970	if (pDevIns)
1971	{
1972	s->pDevInsR3 = pDevIns;
1973	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1974	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1975	}
1976	if (pIoApicHlp)
1977	{
1978	s->pIoApicHlpR3 = pIoApicHlp;
1979	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1980	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1981	}
1982	#endif
1983	}
1984
1985	#endif /* IN_RING3 */
1986
1987	#ifndef VBOX
1988	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1989	ioapic_mem_readl,
1990	ioapic_mem_readl,
1991	ioapic_mem_readl,
1992	};
1993
1994	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1995	ioapic_mem_writel,
1996	ioapic_mem_writel,
1997	ioapic_mem_writel,
1998	};
1999
2000	IOAPICState *ioapic_init(void)
2001	{
2002	IOAPICState *s;
2003	int io_memory;
2004
2005	s = qemu_mallocz(sizeof(IOAPICState));
2006	if (!s)
2007	return NULL;
2008	ioapic_reset(s);
2009	s->id = last_apic_id++;
2010
2011	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
2012	ioapic_mem_write, s);
2013	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2014
2015	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2016	qemu_register_reset(ioapic_reset, s);
2017
2018	return s;
2019	}
2020	#endif /* !VBOX */
2021
2022	/* LAPIC */
2023	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2024	{
2025	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2026	APICState *s = getLapic(dev);
2027
2028	#ifdef VBOX_WITH_SMP_GUESTS
2029	LogRel(("[SMP] apicMMIORead at %llx\n", (uint64_t)GCPhysAddr));
2030	#endif
2031
2032	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2033	different physical addresses, see #3092) */
2034
2035	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2036	switch (cb)
2037	{
2038	case 1:
2039	(uint8_t )pv = 0;
2040	break;
2041
2042	case 2:
2043	(uint16_t )pv = 0;
2044	break;
2045
2046	case 4:
2047	{
2048	#if 0 /** @note experimental */
2049	#ifndef IN_RING3
2050	uint32_t index = (GCPhysAddr >> 4) & 0xff;
2051
2052	if ( index == 0x08 /* TPR */
2053	&& ++s->ulTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2054	{
2055	#ifdef IN_RC
2056	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2057	#else
2058	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2059	pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2060	#endif
2061	return VINF_PATM_HC_MMIO_PATCH_READ;
2062	}
2063	#endif
2064	#endif /* experimental */
2065	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2066	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
2067	APIC_UNLOCK(dev);
2068	break;
2069	}
2070	default:
2071	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2072	return VERR_INTERNAL_ERROR;
2073	}
2074	return VINF_SUCCESS;
2075	}
2076
2077	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2078	{
2079	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2080	APICState *s = getLapic(dev);
2081
2082	#ifdef VBOX_WITH_SMP_GUESTS
2083	LogRel(("[SMP] apicMMIOWrite at %llx\n", (uint64_t)GCPhysAddr));
2084	#endif
2085
2086	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2087	different physical addresses, see #3092) */
2088
2089	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2090	switch (cb)
2091	{
2092	case 1:
2093	case 2:
2094	/* ignore */
2095	break;
2096
2097	case 4:
2098	{
2099	int rc;
2100	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2101	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2102	APIC_UNLOCK(dev);
2103	return rc;
2104	}
2105
2106	default:
2107	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2108	return VERR_INTERNAL_ERROR;
2109	}
2110	return VINF_SUCCESS;
2111	}
2112
2113	#ifdef IN_RING3
2114
2115	/**
2116	* @copydoc FNSSMDEVSAVEEXEC
2117	*/
2118	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2119	{
2120	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2121
2122	/* save all APICs data, @todo: is it correct? */
2123	foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
2124
2125	return VINF_SUCCESS;
2126	}
2127
2128	/**
2129	* @copydoc FNSSMDEVLOADEXEC
2130	*/
2131	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2132	{
2133	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2134	/* load all APICs data, @todo: is it correct? */
2135	foreach_apic(dev, 0xffffffff,
2136	if (apic_load(pSSMHandle, apic, u32Version))
2137	{
2138	AssertFailed();
2139	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2140	}
2141	);
2142	return VINF_SUCCESS;
2143	}
2144
2145	/**
2146	* @copydoc FNPDMDEVRESET
2147	*/
2148	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2149	{
2150	APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2151	APICState *s = getLapic(dev);
2152
2153	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2154
2155	TMTimerStop(s->CTX_SUFF(pTimer));
2156
2157	apic_init_ipi(s);
2158	/* malc, I've removed the initing duplicated in apic_init_ipi(). This
2159	* arb_id was left over.. */
2160	s->arb_id = 0;
2161	/* Reset should re-enable the APIC. */
2162	s->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_ENABLE;
2163	if (s->phys_id == 0)
2164	s->apicbase \|= MSR_IA32_APICBASE_BSP;
2165	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2166	/* Clear any pending APIC interrupt action flag. */
2167	cpuClearInterrupt(dev, s);
2168	APIC_UNLOCK(dev);
2169	}
2170
2171	/**
2172	* @copydoc FNPDMDEVRELOCATE
2173	*/
2174	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2175	{
2176	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2177	dev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2178	dev->pApicHlpRC = dev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2179	dev->pLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), dev->pLapicsR3);
2180	foreach_apic(dev, 0xffffffff,
2181	apic->pTimerRC = TMTimerRCPtr(apic->CTX_SUFF(pTimer)));
2182	}
2183
2184	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2185	{
2186	int i;
2187	memset(apic, 0, sizeof(*apic));
2188	apic->apicbase = UINT32_C(0xfee00000) \| MSR_IA32_APICBASE_ENABLE;
2189	/* Mark first CPU as BSP */
2190	if (id == 0)
2191	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2192	for (i = 0; i < APIC_LVT_NB; i++)
2193	apic->lvt[i] = 1 << 16; /* mask LVT */
2194	apic->spurious_vec = 0xff;
2195	apic->phys_id = apic->id = id;
2196	}
2197
2198	/**
2199	* @copydoc FNPDMDEVCONSTRUCT
2200	*/
2201	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2202	{
2203	PDMAPICREG ApicReg;
2204	int rc;
2205	uint32_t i;
2206	bool fIOAPIC;
2207	bool fGCEnabled;
2208	bool fR0Enabled;
2209	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2210	uint32_t cCpus;
2211	APICState *apic;
2212
2213	/*
2214	* Only single device instance.
2215	*/
2216	Assert(iInstance == 0);
2217
2218	/*
2219	* Validate configuration.
2220	*/
2221	if (!CFGMR3AreValuesValid(pCfgHandle,
2222	"IOAPIC\0"
2223	"GCEnabled\0"
2224	"R0Enabled\0"
2225	"NumCPUs\0"))
2226	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2227
2228	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIOAPIC, true);
2229	if (RT_FAILURE(rc))
2230	return PDMDEV_SET_ERROR(pDevIns, rc,
2231	N_("Configuration error: Failed to read \"IOAPIC\""));
2232
2233	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2234	if (RT_FAILURE(rc))
2235	return PDMDEV_SET_ERROR(pDevIns, rc,
2236	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2237
2238	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2239	if (RT_FAILURE(rc))
2240	return PDMDEV_SET_ERROR(pDevIns, rc,
2241	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2242
2243	rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2244	if (RT_FAILURE(rc))
2245	return PDMDEV_SET_ERROR(pDevIns, rc,
2246	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2247
2248	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
2249
2250	/*
2251	* Init the data.
2252	*/
2253	pThis->pDevInsR3 = pDevIns;
2254	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2255	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2256	pThis->cCpus = cCpus;
2257	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2258	pThis->enmVersion = PDMAPICVERSION_APIC;
2259
2260	PVM pVM = PDMDevHlpGetVM(pDevIns);
2261	/*
2262	* We are not freeing this memory, as it's automatically released when guest exits.
2263	*/
2264	rc = MMHyperAlloc(pVM, cCpussizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void *)&pThis->pLapicsR3);
2265	if (RT_FAILURE(rc))
2266	return VERR_NO_MEMORY;
2267	pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
2268	pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
2269
2270	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2271	{
2272	initApicData(apic, i);
2273	apic++;
2274	}
2275
2276	/*
2277	* Register the APIC.
2278	*/
2279	ApicReg.u32Version = PDM_APICREG_VERSION;
2280	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2281	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2282	ApicReg.pfnSetBaseR3 = apicSetBase;
2283	ApicReg.pfnGetBaseR3 = apicGetBase;
2284	ApicReg.pfnSetTPRR3 = apicSetTPR;
2285	ApicReg.pfnGetTPRR3 = apicGetTPR;
2286	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2287	ApicReg.pfnReadMSRR3 = apicReadMSR;
2288	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2289	if (fGCEnabled) {
2290	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2291	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2292	ApicReg.pszSetBaseRC = "apicSetBase";
2293	ApicReg.pszGetBaseRC = "apicGetBase";
2294	ApicReg.pszSetTPRRC = "apicSetTPR";
2295	ApicReg.pszGetTPRRC = "apicGetTPR";
2296	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2297	ApicReg.pszReadMSRRC = "apicReadMSR";
2298	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2299	} else {
2300	ApicReg.pszGetInterruptRC = NULL;
2301	ApicReg.pszHasPendingIrqRC = NULL;
2302	ApicReg.pszSetBaseRC = NULL;
2303	ApicReg.pszGetBaseRC = NULL;
2304	ApicReg.pszSetTPRRC = NULL;
2305	ApicReg.pszGetTPRRC = NULL;
2306	ApicReg.pszWriteMSRRC = NULL;
2307	ApicReg.pszReadMSRRC = NULL;
2308	ApicReg.pszBusDeliverRC = NULL;
2309	}
2310	if (fR0Enabled) {
2311	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2312	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2313	ApicReg.pszSetBaseR0 = "apicSetBase";
2314	ApicReg.pszGetBaseR0 = "apicGetBase";
2315	ApicReg.pszSetTPRR0 = "apicSetTPR";
2316	ApicReg.pszGetTPRR0 = "apicGetTPR";
2317	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2318	ApicReg.pszReadMSRR0 = "apicReadMSR";
2319	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2320	} else {
2321	ApicReg.pszGetInterruptR0 = NULL;
2322	ApicReg.pszHasPendingIrqR0 = NULL;
2323	ApicReg.pszSetBaseR0 = NULL;
2324	ApicReg.pszGetBaseR0 = NULL;
2325	ApicReg.pszSetTPRR0 = NULL;
2326	ApicReg.pszGetTPRR0 = NULL;
2327	ApicReg.pszWriteMSRR0 = NULL;
2328	ApicReg.pszReadMSRR0 = NULL;
2329	ApicReg.pszBusDeliverR0 = NULL;
2330	}
2331
2332	Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2333	rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2334	if (RT_FAILURE(rc))
2335	{
2336	AssertLogRelMsgFailed(("APICRegister -> %Rrc\n", rc));
2337	return rc;
2338	}
2339
2340	/*
2341	* The the CPUID feature bit.
2342	*/
2343	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2344	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2345	if (u32Eax >= 1)
2346	{
2347	if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
2348	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2349	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2350	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2351	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2352	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2353	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2354	{
2355	LogRel(("Activating Local APIC\n"));
2356	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2357	}
2358	}
2359
2360	/*
2361	* Register the MMIO range.
2362	* @todo: may need to rethink for cases when different LAPICs mapped to different address
2363	* (see IA32_APIC_BASE_MSR)
2364	*/
2365	rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
2366	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2367	if (RT_FAILURE(rc))
2368	return rc;
2369
2370	if (fGCEnabled) {
2371	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2372
2373	rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2374	"apicMMIOWrite", "apicMMIORead", NULL);
2375	if (RT_FAILURE(rc))
2376	return rc;
2377	}
2378
2379	if (fR0Enabled) {
2380	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2381
2382	rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2383	"apicMMIOWrite", "apicMMIORead", NULL);
2384	if (RT_FAILURE(rc))
2385	return rc;
2386	}
2387
2388	/*
2389	* Create the APIC timers.
2390	*/
2391	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2392	{
2393	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer,
2394	"APIC Timer", &apic->pTimerR3);
2395	if (RT_FAILURE(rc))
2396	return rc;
2397	apic->pTimerR0 = TMTimerR0Ptr(apic->pTimerR3);
2398	apic->pTimerRC = TMTimerRCPtr(apic->pTimerR3);
2399	apic++;
2400	}
2401
2402	/*
2403	* Saved state.
2404	*/
2405	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
2406	sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
2407	if (RT_FAILURE(rc))
2408	return rc;
2409
2410	#ifdef VBOX_WITH_STATISTICS
2411	/*
2412	* Statistics.
2413	*/
2414	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2415	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2416	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2417	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2418	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq, STAMTYPE_COUNTER, "/PDM/APIC/Masked/ActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2419	#endif
2420
2421	return VINF_SUCCESS;
2422	}
2423
2424
2425	/**
2426	* APIC device registration structure.
2427	*/
2428	const PDMDEVREG g_DeviceAPIC =
2429	{
2430	/* u32Version */
2431	PDM_DEVREG_VERSION,
2432	/* szDeviceName */
2433	"apic",
2434	/* szRCMod */
2435	"VBoxDD2GC.gc",
2436	/* szR0Mod */
2437	"VBoxDD2R0.r0",
2438	/* pszDescription */
2439	"Advanced Programmable Interrupt Controller (APIC) Device",
2440	/* fFlags */
2441	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2442	/* fClass */
2443	PDM_DEVREG_CLASS_PIC,
2444	/* cMaxInstances */
2445	1,
2446	/* cbInstance */
2447	sizeof(APICState),
2448	/* pfnConstruct */
2449	apicConstruct,
2450	/* pfnDestruct */
2451	NULL,
2452	/* pfnRelocate */
2453	apicRelocate,
2454	/* pfnIOCtl */
2455	NULL,
2456	/* pfnPowerOn */
2457	NULL,
2458	/* pfnReset */
2459	apicReset,
2460	/* pfnSuspend */
2461	NULL,
2462	/* pfnResume */
2463	NULL,
2464	/* pfnAttach */
2465	NULL,
2466	/* pfnDetach */
2467	NULL,
2468	/* pfnQueryInterface. */
2469	NULL,
2470	/* pfnInitComplete */
2471	NULL,
2472	/* pfnPowerOff */
2473	NULL,
2474	/* pfnSoftReset */
2475	NULL,
2476	/* u32VersionEnd */
2477	PDM_DEVREG_VERSION
2478	};
2479
2480	#endif /* IN_RING3 */
2481
2482
2483	/* IOAPIC */
2484
2485	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2486	{
2487	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2488	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2489
2490	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2491	switch (cb)
2492	{
2493	case 1:
2494	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2495	break;
2496
2497	case 2:
2498	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2499	break;
2500
2501	case 4:
2502	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2503	break;
2504
2505	default:
2506	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2507	IOAPIC_UNLOCK(s);
2508	return VERR_INTERNAL_ERROR;
2509	}
2510	IOAPIC_UNLOCK(s);
2511	return VINF_SUCCESS;
2512	}
2513
2514	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2515	{
2516	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2517
2518	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2519	switch (cb)
2520	{
2521	case 1:
2522	case 2:
2523	case 4:
2524	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2525	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
2526	IOAPIC_UNLOCK(s);
2527	break;
2528
2529	default:
2530	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2531	return VERR_INTERNAL_ERROR;
2532	}
2533	return VINF_SUCCESS;
2534	}
2535
2536	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2537	{
2538	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
2539	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2540	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2541	ioapic_set_irq(pThis, iIrq, iLevel);
2542	}
2543
2544
2545	#ifdef IN_RING3
2546
2547	/**
2548	* @copydoc FNSSMDEVSAVEEXEC
2549	*/
2550	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2551	{
2552	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2553	ioapic_save(pSSMHandle, s);
2554	return VINF_SUCCESS;
2555	}
2556
2557	/**
2558	* @copydoc FNSSMDEVLOADEXEC
2559	*/
2560	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2561	{
2562	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2563
2564	if (ioapic_load(pSSMHandle, s, u32Version)) {
2565	AssertFailed();
2566	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2567	}
2568
2569	return VINF_SUCCESS;
2570	}
2571
2572	/**
2573	* @copydoc FNPDMDEVRESET
2574	*/
2575	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2576	{
2577	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2578	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2579	ioapic_reset(s);
2580	IOAPIC_UNLOCK(s);
2581	}
2582
2583	/**
2584	* @copydoc FNPDMDEVRELOCATE
2585	*/
2586	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2587	{
2588	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2589	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2590	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2591	}
2592
2593	/**
2594	* @copydoc FNPDMDEVCONSTRUCT
2595	*/
2596	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2597	{
2598	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2599	PDMIOAPICREG IoApicReg;
2600	bool fGCEnabled;
2601	bool fR0Enabled;
2602	int rc;
2603
2604	Assert(iInstance == 0);
2605
2606	/*
2607	* Validate and read the configuration.
2608	*/
2609	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2610	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2611
2612	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2613	if (RT_FAILURE(rc))
2614	return PDMDEV_SET_ERROR(pDevIns, rc,
2615	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2616
2617	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2618	if (RT_FAILURE(rc))
2619	return PDMDEV_SET_ERROR(pDevIns, rc,
2620	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2621	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2622
2623	/*
2624	* Initialize the state data.
2625	*/
2626	s->pDevInsR3 = pDevIns;
2627	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2628	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2629	ioapic_reset(s);
2630	s->id = 0;
2631
2632	/*
2633	* Register the IOAPIC and get helpers.
2634	*/
2635	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2636	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2637	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2638	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2639	rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2640	if (RT_FAILURE(rc))
2641	{
2642	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2643	return rc;
2644	}
2645
2646	/*
2647	* Register MMIO callbacks and saved state.
2648	*/
2649	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2650	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2651	if (RT_FAILURE(rc))
2652	return rc;
2653
2654	if (fGCEnabled) {
2655	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2656
2657	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2658	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2659	if (RT_FAILURE(rc))
2660	return rc;
2661	}
2662
2663	if (fR0Enabled) {
2664	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2665
2666	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2667	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2668	if (RT_FAILURE(rc))
2669	return rc;
2670	}
2671
2672	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2673	sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2674	if (RT_FAILURE(rc))
2675	return rc;
2676
2677	#ifdef VBOX_WITH_STATISTICS
2678	/*
2679	* Statistics.
2680	*/
2681	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2682	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2683	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2684	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2685	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2686	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2687	#endif
2688
2689	return VINF_SUCCESS;
2690	}
2691
2692	/**
2693	* IO APIC device registration structure.
2694	*/
2695	const PDMDEVREG g_DeviceIOAPIC =
2696	{
2697	/* u32Version */
2698	PDM_DEVREG_VERSION,
2699	/* szDeviceName */
2700	"ioapic",
2701	/* szRCMod */
2702	"VBoxDD2GC.gc",
2703	/* szR0Mod */
2704	"VBoxDD2R0.r0",
2705	/* pszDescription */
2706	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2707	/* fFlags */
2708	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2709	/* fClass */
2710	PDM_DEVREG_CLASS_PIC,
2711	/* cMaxInstances */
2712	1,
2713	/* cbInstance */
2714	sizeof(IOAPICState),
2715	/* pfnConstruct */
2716	ioapicConstruct,
2717	/* pfnDestruct */
2718	NULL,
2719	/* pfnRelocate */
2720	ioapicRelocate,
2721	/* pfnIOCtl */
2722	NULL,
2723	/* pfnPowerOn */
2724	NULL,
2725	/* pfnReset */
2726	ioapicReset,
2727	/* pfnSuspend */
2728	NULL,
2729	/* pfnResume */
2730	NULL,
2731	/* pfnAttach */
2732	NULL,
2733	/* pfnDetach */
2734	NULL,
2735	/* pfnQueryInterface. */
2736	NULL,
2737	/* pfnInitComplete */
2738	NULL,
2739	/* pfnPowerOff */
2740	NULL,
2741	/* pfnSoftReset */
2742	NULL,
2743	/* u32VersionEnd */
2744	PDM_DEVREG_VERSION
2745	};
2746
2747	#endif /* IN_RING3 */
2748	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 19468

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