DevAPIC.cpp@ 19741

Last change on this file since 19741 was 19741, checked in by vboxsync, 16 years ago
Handle APIC_DM_LOWPRI in apic_bus_deliver
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 81.3 KB

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1	#ifdef VBOX
2	/* $Id: DevAPIC.cpp 19741 2009-05-15 14:33:03Z vboxsync $ */
3	/** @file
4	* Advanced Programmable Interrupt Controller (APIC) Device and
5	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* apic.c revision 1.5 @@OSETODO
27	*/
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/pdmdev.h>
34
35	#include <VBox/log.h>
36	#include <VBox/stam.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40	#include "Builtins2.h"
41	#include "vl_vbox.h"
42
43	#define MSR_IA32_APICBASE 0x1b
44	#define MSR_IA32_APICBASE_BSP (1<<8)
45	#define MSR_IA32_APICBASE_ENABLE (1<<11)
46	#ifdef VBOX
47	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48	#endif
49	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51	#ifndef EINVAL
52	# define EINVAL 1
53	#endif
54
55	#ifdef _MSC_VER
56	# pragma warning(disable:4244)
57	#endif
58
59	/** @def APIC_LOCK
60	* Acquires the PDM lock. */
61	#define APIC_LOCK(pThis, rc) \
62	do { \
63	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
64	if (rc2 != VINF_SUCCESS) \
65	return rc2; \
66	} while (0)
67
68	/** @def APIC_LOCK_VOID
69	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
70	#define APIC_LOCK_VOID(pThis, rc) \
71	do { \
72	int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
73	AssertLogRelRCReturnVoid(rc2); \
74	} while (0)
75
76	/** @def APIC_UNLOCK
77	* Releases the PDM lock. */
78	#define APIC_UNLOCK(pThis) \
79	(pThis)->CTX_SUFF(pApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
80
81	/** @def IOAPIC_LOCK
82	* Acquires the PDM lock. */
83	#define IOAPIC_LOCK(pThis, rc) \
84	do { \
85	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
86	if (rc2 != VINF_SUCCESS) \
87	return rc2; \
88	} while (0)
89
90	/** @def IOAPIC_UNLOCK
91	* Releases the PDM lock. */
92	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
93
94	/** @def LAPIC_BASE
95	* Return address of first LAPIC state. */
96	#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
97
98	#define foreach_apic(dev, mask, code) \
99	do { \
100	uint32_t i; \
101	APICState* apic = LAPIC_BASE(dev); \
102	for (i = 0; i < dev->cCpus; i++) \
103	{ \
104	if (mask & (1 << (apic->id))) \
105	{ \
106	code; \
107	} \
108	apic++; \
109	} \
110	} while (0)
111
112	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
113	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
114	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
115	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
116
117	#endif /* VBOX */
118
119	/*
120	* APIC support
121	*
122	* Copyright (c) 2004-2005 Fabrice Bellard
123	*
124	* This library is free software; you can redistribute it and/or
125	* modify it under the terms of the GNU Lesser General Public
126	* License as published by the Free Software Foundation; either
127	* version 2 of the License, or (at your option) any later version.
128	*
129	* This library is distributed in the hope that it will be useful,
130	* but WITHOUT ANY WARRANTY; without even the implied warranty of
131	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
132	* Lesser General Public License for more details.
133	*
134	* You should have received a copy of the GNU Lesser General Public
135	* License along with this library; if not, write to the Free Software
136	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
137	*/
138	#ifndef VBOX
139	#include "vl.h"
140	#endif
141
142	#define DEBUG_APIC
143	#define DEBUG_IOAPIC
144
145	/* APIC Local Vector Table */
146	#define APIC_LVT_TIMER 0
147	#define APIC_LVT_THERMAL 1
148	#define APIC_LVT_PERFORM 2
149	#define APIC_LVT_LINT0 3
150	#define APIC_LVT_LINT1 4
151	#define APIC_LVT_ERROR 5
152	#define APIC_LVT_NB 6
153
154	/* APIC delivery modes */
155	#define APIC_DM_FIXED 0
156	#define APIC_DM_LOWPRI 1
157	#define APIC_DM_SMI 2
158	#define APIC_DM_NMI 4
159	#define APIC_DM_INIT 5
160	#define APIC_DM_SIPI 6
161	#define APIC_DM_EXTINT 7
162
163	/* APIC destination mode */
164	#define APIC_DESTMODE_FLAT 0xf
165	#define APIC_DESTMODE_CLUSTER 1
166
167	#define APIC_TRIGGER_EDGE 0
168	#define APIC_TRIGGER_LEVEL 1
169
170	#define APIC_LVT_TIMER_PERIODIC (1<<17)
171	#define APIC_LVT_MASKED (1<<16)
172	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
173	#define APIC_LVT_REMOTE_IRR (1<<14)
174	#define APIC_INPUT_POLARITY (1<<13)
175	#define APIC_SEND_PENDING (1<<12)
176
177	#define IOAPIC_NUM_PINS 0x18
178
179	#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181	#define APIC_SV_ENABLE (1 << 8)
182
183	#ifdef VBOX
184	#define APIC_MAX_PATCH_ATTEMPTS 100
185
186	typedef uint32_t PhysApicId;
187	typedef uint32_t LogApicId;
188	#endif
189
190	typedef struct APICState {
191	#ifndef VBOX
192	CPUState *cpu_env;
193	#endif /* !VBOX */
194	uint32_t apicbase;
195	#ifdef VBOX
196	/* Task priority register (interrupt level) */
197	uint32_t tpr;
198	/* Logical APIC id */
199	LogApicId id;
200	/* Physical APIC id */
201	PhysApicId phys_id;
202	/** @todo: is it logical or physical? Not really used anyway now. */
203	PhysApicId arb_id;
204	#else
205	uint8_t tpr;
206	uint8_t id;
207	uint8_t arb_id;
208	#endif
209	uint32_t spurious_vec;
210	uint8_t log_dest;
211	uint8_t dest_mode;
212	uint32_t isr[8]; /* in service register */
213	uint32_t tmr[8]; /* trigger mode register */
214	uint32_t irr[8]; /* interrupt request register */
215	uint32_t lvt[APIC_LVT_NB];
216	uint32_t esr; /* error register */
217	uint32_t icr[2];
218	uint32_t divide_conf;
219	int count_shift;
220	uint32_t initial_count;
221	#ifdef VBOX
222	uint32_t Alignment0;
223	#endif
224	int64_t initial_count_load_time, next_time;
225	#ifndef VBOX
226	QEMUTimer *timer;
227	struct APICState *next_apic;
228	#else
229	/** The APIC timer - R3 Ptr. */
230	PTMTIMERR3 pTimerR3;
231
232	/** The APIC timer - R0 Ptr. */
233	PTMTIMERR0 pTimerR0;
234
235	/** The APIC timer - RC Ptr. */
236	PTMTIMERRC pTimerRC;
237
238	/** Alignment */
239	uint32_t Alignment1;
240	#endif /* VBOX */
241	} APICState;
242
243	struct IOAPICState {
244	uint8_t id;
245	uint8_t ioregsel;
246
247	uint32_t irr;
248	uint64_t ioredtbl[IOAPIC_NUM_PINS];
249
250	#ifdef VBOX
251	/** The device instance - R3 Ptr. */
252	PPDMDEVINSR3 pDevInsR3;
253	/** The IOAPIC helpers - R3 Ptr. */
254	PCPDMIOAPICHLPR3 pIoApicHlpR3;
255
256	/** The device instance - R0 Ptr. */
257	PPDMDEVINSR0 pDevInsR0;
258	/** The IOAPIC helpers - R0 Ptr. */
259	PCPDMIOAPICHLPR0 pIoApicHlpR0;
260
261	/** The device instance - RC Ptr. */
262	PPDMDEVINSRC pDevInsRC;
263	/** The IOAPIC helpers - RC Ptr. */
264	PCPDMIOAPICHLPRC pIoApicHlpRC;
265
266	# ifdef VBOX_WITH_STATISTICS
267	STAMCOUNTER StatMMIOReadGC;
268	STAMCOUNTER StatMMIOReadHC;
269	STAMCOUNTER StatMMIOWriteGC;
270	STAMCOUNTER StatMMIOWriteHC;
271	STAMCOUNTER StatSetIrqGC;
272	STAMCOUNTER StatSetIrqHC;
273	# endif
274	#endif /* VBOX */
275	};
276
277	#ifdef VBOX
278	typedef struct IOAPICState IOAPICState;
279
280	typedef struct
281	{
282	/** The device instance - R3 Ptr. */
283	PPDMDEVINSR3 pDevInsR3;
284	/** The APIC helpers - R3 Ptr. */
285	PCPDMAPICHLPR3 pApicHlpR3;
286	/** LAPICs states - R3 Ptr */
287	RTR3PTR pLapicsR3;
288
289	/** The device instance - R0 Ptr. */
290	PPDMDEVINSR0 pDevInsR0;
291	/** The APIC helpers - R0 Ptr. */
292	PCPDMAPICHLPR0 pApicHlpR0;
293	/** LAPICs states - R0 Ptr */
294	RTR0PTR pLapicsR0;
295
296	/** The device instance - RC Ptr. */
297	PPDMDEVINSRC pDevInsRC;
298	/** The APIC helpers - RC Ptr. */
299	PCPDMAPICHLPRC pApicHlpRC;
300	/** LAPICs states - RC Ptr */
301	RTRCPTR pLapicsRC;
302
303	/** APIC specification version in this virtual hardware configuration. */
304	PDMAPICVERSION enmVersion;
305
306	/** Number of attempts made to optimize TPR accesses. */
307	uint32_t ulTPRPatchAttempts;
308
309	/** Number of CPUs on the system (same as LAPIC count). */
310	uint32_t cCpus;
311
312	# ifdef VBOX_WITH_STATISTICS
313	STAMCOUNTER StatMMIOReadGC;
314	STAMCOUNTER StatMMIOReadHC;
315	STAMCOUNTER StatMMIOWriteGC;
316	STAMCOUNTER StatMMIOWriteHC;
317	STAMCOUNTER StatClearedActiveIrq;
318	# endif
319	} APICDeviceInfo;
320
321	static void apic_eoi(APICDeviceInfo dev, APICState s);
322	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
323	uint8_t dest, uint8_t dest_mode,
324	uint8_t delivery_mode, uint8_t vector_num,
325	uint8_t polarity, uint8_t trigger_mode);
326	static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
327	int64_t current_time);
328	static int apic_get_arb_pri(APICState *s);
329	static int apic_get_ppr(APICState *s);
330	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
331
332
333	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
334	{
335	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
336	return LAPIC_BASE(dev) + id;
337	}
338
339	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
340	{
341	/* LAPIC's array is indexed by CPU id */
342	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
343	return getLapicById(dev, id);
344	}
345
346	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
347	{
348	/* for now we assume LAPIC physical id == CPU id */
349	return VMCPUID(s->phys_id);
350	}
351
352	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s)
353	{
354	Log2(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(dev, s)));
355	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns),
356	getCpuFromLapic(dev, s));
357	}
358
359	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
360	{
361	Log2(("apic: clear interrupt flag\n"));
362	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
363	getCpuFromLapic(dev, s));
364	}
365
366	#ifdef IN_RING3
367	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
368	{
369	Log2(("apic: send SIPI vector=%d\n", vector));
370
371	dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
372	getCpuFromLapic(dev, s),
373	vector);
374	}
375
376	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* dev, APICState *s)
377	{
378	Log2(("apic: send init IPI\n"));
379
380	dev->pApicHlpR3->pfnSendInitIpi(dev->pDevInsR3,
381	getCpuFromLapic(dev, s));
382	}
383	#endif
384
385	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
386	{
387	switch (dev->enmVersion)
388	{
389	case PDMAPICVERSION_NONE:
390	return 0;
391	case PDMAPICVERSION_APIC:
392	return MSR_IA32_APICBASE_ENABLE;
393	case PDMAPICVERSION_X2APIC:
394	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
395	default:
396	AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
397	return 0;
398	}
399	}
400
401	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
402	{
403	switch (((apic->apicbase) >> 10) & 0x3)
404	{
405	case 0:
406	return PDMAPICVERSION_NONE;
407	case 1:
408	default:
409	/* Invalid */
410	return PDMAPICVERSION_NONE;
411	case 2:
412	return PDMAPICVERSION_APIC;
413	case 3:
414	return PDMAPICVERSION_X2APIC;
415	}
416	}
417
418	#endif /* VBOX */
419
420	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
421	#ifndef VBOX
422	static int apic_io_memory;
423	static APICState *first_local_apic = NULL;
424	static int last_apic_id = 0;
425	#endif /* !VBOX */
426
427	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s);
428	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
429	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
430
431	#ifdef VBOX
432	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
433	__BEGIN_DECLS
434	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
435	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
436	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
437	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
438	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
439	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
440	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val);
441	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns);
442	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
443	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
444	uint8_t u8TriggerMode);
445	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
446	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
447	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
448	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
449	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
450
451	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
452	__END_DECLS
453	#endif /* VBOX */
454
455	#ifndef VBOX
456	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
457	uint8_t vector_num, uint8_t polarity,
458	uint8_t trigger_mode)
459	{
460	APICState *apic_iter;
461	#else /* VBOX */
462	static int apic_bus_deliver(APICDeviceInfo* dev,
463	uint32_t deliver_bitmask, uint8_t delivery_mode,
464	uint8_t vector_num, uint8_t polarity,
465	uint8_t trigger_mode)
466	{
467	#endif /* VBOX */
468
469	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
470	switch (delivery_mode) {
471	case APIC_DM_LOWPRI:
472	{
473	int d = -1;
474	if (deliver_bitmask)
475	d = ffs_bit(deliver_bitmask);
476	if (d >= 0)
477	{
478	APICState* apic = getLapicById(dev, d);
479	apic_set_irq(dev, apic, vector_num, trigger_mode);
480	}
481	return VINF_SUCCESS;
482	}
483	case APIC_DM_FIXED:
484	/* XXX: arbitration */
485	break;
486
487	case APIC_DM_SMI:
488	/** @todo: what do we really do with SMI */
489	foreach_apic(dev, deliver_bitmask,
490	cpuSetInterrupt(dev, apic));
491	return VINF_SUCCESS;
492
493	case APIC_DM_NMI:
494	/** @todo: what do we really do with NMI */
495	foreach_apic(dev, deliver_bitmask,
496	cpuSetInterrupt(dev, apic));
497	return VINF_SUCCESS;
498
499	case APIC_DM_INIT:
500	/* normal INIT IPI sent to processors */
501	#ifdef VBOX
502	#ifdef IN_RING3
503	foreach_apic(dev, deliver_bitmask,
504	apic_init_ipi(dev, apic));
505	return VINF_SUCCESS;
506	#else
507	/* We shall send init IPI only in R3, R0 calls should be
508	rescheduled to R3 */
509	return VINF_IOM_HC_MMIO_READ_WRITE;
510	#endif /* IN_RING3 */
511
512	#else
513	for (apic_iter = first_local_apic; apic_iter != NULL;
514	apic_iter = apic_iter->next_apic) {
515	apic_init_ipi(apic_iter);
516	}
517	#endif
518
519	case APIC_DM_EXTINT:
520	/* handled in I/O APIC code */
521	break;
522
523	default:
524	return VINF_SUCCESS;
525	}
526
527	#ifdef VBOX
528	foreach_apic(dev, deliver_bitmask,
529	apic_set_irq (dev, apic, vector_num, trigger_mode));
530	return VINF_SUCCESS;
531	#else /* VBOX */
532	for (apic_iter = first_local_apic; apic_iter != NULL;
533	apic_iter = apic_iter->next_apic) {
534	if (deliver_bitmask & (1 << apic_iter->id))
535	apic_set_irq(apic_iter, vector_num, trigger_mode);
536	}
537	#endif /* VBOX */
538	}
539
540	#ifndef VBOX
541	void cpu_set_apic_base(CPUState *env, uint64_t val)
542	{
543	APICState *s = env->apic_state;
544	#ifdef DEBUG_APIC
545	Log(("cpu_set_apic_base: %016llx\n", val));
546	#endif
547
548	s->apicbase = (val & 0xfffff000) \|
549	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
550	/* if disabled, cannot be enabled again */
551	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
552	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
553	env->cpuid_features &= ~CPUID_APIC;
554	s->spurious_vec &= ~APIC_SV_ENABLE;
555	}
556	}
557	#else /* VBOX */
558	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
559	{
560	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
561	APICState *s = getLapic(dev);
562	Log(("cpu_set_apic_base: %016RX64\n", val));
563
564	/** @todo: do we need to lock here ? */
565	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
566	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
567	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
568	PDMAPICVERSION oldMode = getApicMode(s);
569	s->apicbase =
570	(val & 0xfffff000) \| /* base */
571	(val & getApicEnableBits(dev)) \| /* mode */
572	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
573	PDMAPICVERSION newMode = getApicMode(s);
574
575	if (oldMode != newMode)
576	{
577	switch (newMode)
578	{
579	case PDMAPICVERSION_NONE:
580	{
581	s->spurious_vec &= ~APIC_SV_ENABLE;
582	/* Clear any pending APIC interrupt action flag. */
583	cpuClearInterrupt(dev, s);
584	/** @todo: why do we do that? */
585	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
586	break;
587	}
588	case PDMAPICVERSION_APIC:
589	/** @todo: map MMIO ranges, if needed */
590	break;
591	case PDMAPICVERSION_X2APIC:
592	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
593	break;
594	default:
595	break;
596	}
597	}
598	/* APIC_UNLOCK(dev); */
599	}
600	#endif /* VBOX */
601	#ifndef VBOX
602
603	uint64_t cpu_get_apic_base(CPUState *env)
604	{
605	APICState *s = env->apic_state;
606	#ifdef DEBUG_APIC
607	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
608	#endif
609	return s->apicbase;
610	}
611
612	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
613	{
614	APICState *s = env->apic_state;
615	s->tpr = (val & 0x0f) << 4;
616	apic_update_irq(s);
617	}
618
619	uint8_t cpu_get_apic_tpr(CPUX86State *env)
620	{
621	APICState *s = env->apic_state;
622	return s->tpr >> 4;
623	}
624
625	static int fls_bit(int value)
626	{
627	unsigned int ret = 0;
628
629	#ifdef HOST_I386
630	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
631	return ret;
632	#else
633	if (value > 0xffff)
634	value >>= 16, ret = 16;
635	if (value > 0xff)
636	value >>= 8, ret += 8;
637	if (value > 0xf)
638	value >>= 4, ret += 4;
639	if (value > 0x3)
640	value >>= 2, ret += 2;
641	return ret + (value >> 1);
642	#endif
643	}
644
645	static inline void set_bit(uint32_t *tab, int index)
646	{
647	int i, mask;
648	i = index >> 5;
649	mask = 1 << (index & 0x1f);
650	tab[i] \|= mask;
651	}
652
653	static inline void reset_bit(uint32_t *tab, int index)
654	{
655	int i, mask;
656	i = index >> 5;
657	mask = 1 << (index & 0x1f);
658	tab[i] &= ~mask;
659	}
660
661
662	#else /* VBOX */
663
664	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
665	{
666	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
667	APICState *s = getLapic(dev);
668	Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
669	return s->apicbase;
670	}
671
672	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
673	{
674	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
675	APICState *s = getLapic(dev);
676	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
677	apic_update_tpr(dev, s, (val & 0x0f) << 4);
678	}
679
680	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
681	{
682	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
683	APICState *s = getLapic(dev);
684	Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
685	return s->tpr >> 4;
686	}
687
688	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
689	{
690	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
691	int rc = VINF_SUCCESS;
692
693	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
694	return VERR_EM_INTERPRETER;
695
696	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
697
698	APICState* apic = getLapicById(dev, idCpu);
699
700	switch (index)
701	{
702	case 0x02:
703	apic->id = (u64Value >> 24);
704	break;
705	case 0x03:
706	break;
707	case 0x08:
708	apic_update_tpr(dev, apic, u64Value);
709	break;
710	case 0x09: case 0x0a:
711	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
712	break;
713	case 0x0b: /* EOI */
714	apic_eoi(dev, apic);
715	break;
716	case 0x0d:
717	apic->log_dest = u64Value >> 24;
718	break;
719	case 0x0e:
720	apic->dest_mode = u64Value >> 28;
721	break;
722	case 0x0f:
723	apic->spurious_vec = u64Value & 0x1ff;
724	apic_update_irq(dev, apic);
725	break;
726	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
727	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
728	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
729	case 0x28:
730	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
731	break;
732
733	case 0x30:
734	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
735	apic->icr[0] = (uint32_t)u64Value;
736	apic->icr[1] = (uint32_t)(u64Value >> 32);
737	rc = apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
738	(apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),
739	(apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
740	break;
741	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
742	{
743	int n = index - 0x32;
744	apic->lvt[n] = u64Value;
745	if (n == APIC_LVT_TIMER)
746	apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
747	}
748	break;
749	case 0x38:
750	apic->initial_count = u64Value;
751	apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
752	apic_timer_update(dev, apic, apic->initial_count_load_time);
753	break;
754	case 0x39:
755	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
756	break;
757	case 0x3e:
758	{
759	int v;
760	apic->divide_conf = u64Value & 0xb;
761	v = (apic->divide_conf & 3) \| ((apic->divide_conf >> 1) & 4);
762	apic->count_shift = (v + 1) & 7;
763	break;
764	}
765	case 0x3f:
766	{
767	/* Self IPI, see x2APIC book 2.4.5 */
768	int vector = u64Value & 0xff;
769	rc = apic_bus_deliver(dev,
770	1 << getLapicById(dev, idCpu)->id /* Self */,
771	0 /* Delivery mode - fixed */,
772	vector,
773	0 /* Polarity - conform to the bus */,
774	0 /* Trigger mode - edge */);
775	break;
776	}
777	default:
778	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
779	apic->esr \|= ESR_ILLEGAL_ADDRESS;
780	break;
781	}
782
783	return rc;
784	}
785	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
786	{
787	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
788
789	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
790	return VERR_EM_INTERPRETER;
791
792	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
793	APICState* apic = getLapicById(dev, idCpu);
794	uint64_t val = 0;
795
796	switch (index)
797	{
798	case 0x02: /* id */
799	val = apic->id << 24;
800	break;
801	case 0x03: /* version */
802	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
803	break;
804	case 0x08:
805	val = apic->tpr;
806	break;
807	case 0x09:
808	val = apic_get_arb_pri(apic);
809	break;
810	case 0x0a:
811	/* ppr */
812	val = apic_get_ppr(apic);
813	break;
814	case 0x0b:
815	val = 0;
816	break;
817	case 0x0d:
818	val = apic->log_dest << 24;
819	break;
820	case 0x0e:
821	/* Bottom 28 bits are always 1 */
822	val = (apic->dest_mode << 28) \| 0xfffffff;
823	break;
824	case 0x0f:
825	val = apic->spurious_vec;
826	break;
827	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
828	val = apic->isr[index & 7];
829	break;
830	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
831	val = apic->tmr[index & 7];
832	break;
833	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
834	val = apic->irr[index & 7];
835	break;
836	case 0x28:
837	val = apic->esr;
838	break;
839	case 0x30:
840	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
841	val = ((uint64_t)apic->icr[0x31] << 32) \| apic->icr[0x30];
842	break;
843	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
844	val = apic->lvt[index - 0x32];
845	break;
846	case 0x38:
847	val = apic->initial_count;
848	break;
849	case 0x39:
850	val = apic_get_current_count(dev, apic);
851	break;
852	case 0x3e:
853	val = apic->divide_conf;
854	break;
855	case 0x3f:
856	/* Self IPI register is write only */
857	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
858	break;
859	default:
860	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
861	apic->esr \|= ESR_ILLEGAL_ADDRESS;
862	val = 0;
863	break;
864	}
865	*pu64Value = val;
866	return VINF_SUCCESS;
867	}
868
869	/**
870	* More or less private interface between IOAPIC, only PDM is responsible
871	* for connecting the two devices.
872	*/
873	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
874	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
875	uint8_t u8TriggerMode)
876	{
877	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
878	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
879	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
880	return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
881	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
882	}
883
884	#endif /* VBOX */
885
886	/* return -1 if no bit is set */
887	static int get_highest_priority_int(uint32_t *tab)
888	{
889	int i;
890	for(i = 7; i >= 0; i--) {
891	if (tab[i] != 0) {
892	return i * 32 + fls_bit(tab[i]);
893	}
894	}
895	return -1;
896	}
897
898	static int apic_get_ppr(APICState *s)
899	{
900	int tpr, isrv, ppr;
901
902	tpr = (s->tpr >> 4);
903	isrv = get_highest_priority_int(s->isr);
904	if (isrv < 0)
905	isrv = 0;
906	isrv >>= 4;
907	if (tpr >= isrv)
908	ppr = s->tpr;
909	else
910	ppr = isrv << 4;
911	return ppr;
912	}
913
914	static int apic_get_ppr_zero_tpr(APICState *s)
915	{
916	int isrv;
917
918	isrv = get_highest_priority_int(s->isr);
919	if (isrv < 0)
920	isrv = 0;
921	return isrv;
922	}
923
924	static int apic_get_arb_pri(APICState *s)
925	{
926	/* XXX: arbitration */
927	return 0;
928	}
929
930	/* signal the CPU if an irq is pending */
931	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
932	{
933	int irrv, ppr;
934	if (!(s->spurious_vec & APIC_SV_ENABLE))
935	#ifdef VBOX
936	{
937	/* Clear any pending APIC interrupt action flag. */
938	cpuClearInterrupt(dev, s);
939	return false;
940	}
941	#else
942	return false;
943	#endif /* VBOX */
944	irrv = get_highest_priority_int(s->irr);
945	if (irrv < 0)
946	return false;
947	ppr = apic_get_ppr(s);
948	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
949	return false;
950	#ifndef VBOX
951	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
952	#else
953	cpuSetInterrupt(dev, s);
954	return true;
955	#endif
956	}
957
958	#ifdef VBOX
959
960	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
961	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
962	{
963	int irrv, ppr;
964	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
965	if (!dev)
966	return false;
967	APICState *s = getLapic(dev);
968
969	/*
970	* All our callbacks now come from single IOAPIC, thus locking
971	* seems to be excessive now (@todo: check)
972	*/
973	irrv = get_highest_priority_int(s->irr);
974	if (irrv < 0)
975	return false;
976
977	ppr = apic_get_ppr_zero_tpr(s);
978
979	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
980	return false;
981
982	return true;
983	}
984
985	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
986	{
987	bool fIrqIsActive = false;
988	bool fIrqWasActive = false;
989
990	fIrqWasActive = apic_update_irq(dev, s);
991	s->tpr = val;
992	fIrqIsActive = apic_update_irq(dev, s);
993
994	/* If an interrupt is pending and now masked, then clear the FF flag. */
995	if (fIrqWasActive && !fIrqIsActive)
996	{
997	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
998	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
999	cpuClearInterrupt(dev, s);
1000	}
1001	}
1002	#endif
1003
1004	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
1005	{
1006	LogFlow(("apic_set_irq vector=%x, trigger_mode=%x\n", vector_num, trigger_mode));
1007	set_bit(s->irr, vector_num);
1008	if (trigger_mode)
1009	set_bit(s->tmr, vector_num);
1010	else
1011	reset_bit(s->tmr, vector_num);
1012	apic_update_irq(dev, s);
1013	}
1014
1015	static void apic_eoi(APICDeviceInfo dev, APICState s)
1016	{
1017	int isrv;
1018	isrv = get_highest_priority_int(s->isr);
1019	if (isrv < 0)
1020	return;
1021	reset_bit(s->isr, isrv);
1022	LogFlow(("apic_eoi isrv=%x\n", isrv));
1023	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1024	set the remote IRR bit for level triggered interrupts. */
1025	apic_update_irq(dev, s);
1026	}
1027
1028	#ifndef VBOX
1029	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1030	#else /* VBOX */
1031	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1032	#endif /* VBOX */
1033	{
1034	uint32_t mask = 0;
1035
1036	if (dest_mode == 0)
1037	{
1038	if (dest == 0xff)
1039	mask = 0xff;
1040	else
1041	mask = 1 << dest;
1042	}
1043	else
1044	{
1045	APICState *apic = LAPIC_BASE(dev);
1046	uint32_t i;
1047
1048	/* XXX: cluster mode */
1049	for(i = 0; i < dev->cCpus; i++)
1050	{
1051	if (apic->dest_mode == 0xf)
1052	{
1053	if (dest & apic->log_dest)
1054	mask \|= (1 << apic->id);
1055	}
1056	else if (apic->dest_mode == 0x0)
1057	{
1058	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1059	&&
1060	(dest & apic->log_dest & 0x0f))
1061	{
1062	mask \|= (1 << i);
1063	}
1064	}
1065	apic++;
1066	}
1067	}
1068
1069	return mask;
1070	}
1071
1072	#ifdef IN_RING3
1073	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s)
1074	{
1075	int i;
1076
1077	for(i = 0; i < APIC_LVT_NB; i++)
1078	s->lvt[i] = 1 << 16; /* mask LVT */
1079	s->tpr = 0;
1080	s->spurious_vec = 0xff;
1081	s->log_dest = 0;
1082	s->dest_mode = 0xff;
1083	memset(s->isr, 0, sizeof(s->isr));
1084	memset(s->tmr, 0, sizeof(s->tmr));
1085	memset(s->irr, 0, sizeof(s->irr));
1086	s->esr = 0;
1087	memset(s->icr, 0, sizeof(s->icr));
1088	s->divide_conf = 0;
1089	s->count_shift = 0;
1090	s->initial_count = 0;
1091	s->initial_count_load_time = 0;
1092	s->next_time = 0;
1093
1094	#ifdef VBOX
1095	cpuSendInitIpi(dev, s);
1096	#endif
1097	}
1098
1099	/* send a SIPI message to the CPU to start it */
1100	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1101	{
1102	#ifndef VBOX
1103	CPUState *env = s->cpu_env;
1104	if (!env->halted)
1105	return;
1106	env->eip = 0;
1107	cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1108	0xffff, 0);
1109	env->halted = 0;
1110	#else
1111	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1112	cpuSendSipi(dev, s, vector_num);
1113	#endif
1114	}
1115	#endif /* IN_RING3 */
1116
1117	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1118	uint8_t dest, uint8_t dest_mode,
1119	uint8_t delivery_mode, uint8_t vector_num,
1120	uint8_t polarity, uint8_t trigger_mode)
1121	{
1122	uint32_t deliver_bitmask = 0;
1123	int dest_shorthand = (s->icr[0] >> 18) & 3;
1124	#ifndef VBOX
1125	APICState *apic_iter;
1126	#endif /* !VBOX */
1127
1128	LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1129
1130	switch (dest_shorthand) {
1131	case 0:
1132	#ifndef VBOX
1133	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1134	#else /* VBOX */
1135	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1136	#endif /* !VBOX */
1137	break;
1138	case 1:
1139	deliver_bitmask = (1 << s->id);
1140	break;
1141	case 2:
1142	deliver_bitmask = 0xffffffff;
1143	break;
1144	case 3:
1145	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1146	break;
1147	}
1148
1149	switch (delivery_mode) {
1150	case APIC_DM_INIT:
1151	{
1152	int trig_mode = (s->icr[0] >> 15) & 1;
1153	int level = (s->icr[0] >> 14) & 1;
1154	if (level == 0 && trig_mode == 1) {
1155	foreach_apic(dev, deliver_bitmask,
1156	apic->arb_id = apic->id);
1157	#ifndef VBOX
1158	return;
1159	#else
1160	Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1161	return VINF_SUCCESS;
1162	#endif
1163	}
1164	}
1165	break;
1166
1167	case APIC_DM_SIPI:
1168	#ifndef VBOX
1169	for (apic_iter = first_local_apic; apic_iter != NULL;
1170	apic_iter = apic_iter->next_apic) {
1171	if (deliver_bitmask & (1 << apic_iter->id)) {
1172	/* XXX: SMP support */
1173	/* apic_startup(apic_iter); */
1174	}
1175	}
1176	return;
1177	#else
1178	# ifdef IN_RING3
1179	foreach_apic(dev, deliver_bitmask,
1180	apic_startup(dev, apic, vector_num));
1181	return VINF_SUCCESS;
1182	# else
1183	/* We shall send SIPI only in R3, R0 calls should be
1184	rescheduled to R3 */
1185	return VINF_IOM_HC_MMIO_WRITE;
1186	# endif
1187	#endif /* !VBOX */
1188	}
1189
1190	#ifndef VBOX
1191	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1192	trigger_mode);
1193	#else /* VBOX */
1194	return apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num,
1195	polarity, trigger_mode);
1196	#endif /* VBOX */
1197	}
1198
1199
1200	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1201	{
1202	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1203	/* if the APIC is not installed or enabled, we let the 8259 handle the
1204	IRQs */
1205	if (!dev)
1206	{
1207	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1208	return -1;
1209	}
1210
1211	APIC_LOCK(dev, VERR_INTERNAL_ERROR);
1212
1213	APICState *s = getLapic(dev);
1214	int intno;
1215
1216	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1217	Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
1218	intno = -1;
1219	goto done;
1220	}
1221
1222	/* XXX: spurious IRQ handling */
1223	intno = get_highest_priority_int(s->irr);
1224	if (intno < 0) {
1225	Log(("apic_get_interrupt: returns -1 (irr)\n"));
1226	intno = -1;
1227	goto done;
1228	}
1229	if (s->tpr && (uint32_t)intno <= s->tpr) {
1230	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1231	intno = s->spurious_vec & 0xff;
1232	goto done;
1233	}
1234	reset_bit(s->irr, intno);
1235	set_bit(s->isr, intno);
1236	apic_update_irq(dev, s);
1237	LogFlow(("apic_get_interrupt: returns %d\n", intno));
1238	done:
1239	APIC_UNLOCK(dev);
1240	return intno;
1241	}
1242
1243	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
1244	{
1245	int64_t d;
1246	uint32_t val;
1247	#ifndef VBOX
1248	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1249	s->count_shift;
1250	#else /* VBOX */
1251	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1252	s->count_shift;
1253	#endif /* VBOX */
1254	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1255	/* periodic */
1256	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1257	} else {
1258	if (d >= s->initial_count)
1259	val = 0;
1260	else
1261	val = s->initial_count - d;
1262	}
1263	return val;
1264	}
1265
1266	static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1267	{
1268	int64_t next_time, d;
1269
1270	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1271	d = (current_time - s->initial_count_load_time) >>
1272	s->count_shift;
1273	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1274	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1275	} else {
1276	if (d >= s->initial_count)
1277	goto no_timer;
1278	d = (uint64_t)s->initial_count + 1;
1279	}
1280	next_time = s->initial_count_load_time + (d << s->count_shift);
1281	#ifndef VBOX
1282	qemu_mod_timer(s->timer, next_time);
1283	#else
1284	TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1285	#endif
1286	s->next_time = next_time;
1287	} else {
1288	no_timer:
1289	#ifndef VBOX
1290	qemu_del_timer(s->timer);
1291	#else
1292	TMTimerStop(s->CTX_SUFF(pTimer));
1293	#endif
1294	}
1295	}
1296
1297	#ifdef IN_RING3
1298	#ifndef VBOX
1299	static void apic_timer(void *opaque)
1300	{
1301	APICState *s = opaque;
1302	#else /* VBOX */
1303	static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1304	{
1305	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1306	APICState *s = getLapic(dev);
1307
1308	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
1309	#endif /* VBOX */
1310
1311	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1312	LogFlow(("apic_timer: trigger irq\n"));
1313	apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1314	}
1315	apic_timer_update(dev, s, s->next_time);
1316
1317	#ifdef VBOX
1318	APIC_UNLOCK(dev);
1319	#endif
1320	}
1321	#endif /* IN_RING3 */
1322
1323	#ifndef VBOX
1324	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1325	{
1326	return 0;
1327	}
1328	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1329	{
1330	return 0;
1331	}
1332
1333	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1334	{
1335	}
1336
1337	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1338	{
1339	}
1340	#endif /* !VBOX */
1341
1342
1343	#ifndef VBOX
1344	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1345	{
1346	CPUState *env;
1347	APICState *s;
1348	#else /* VBOX */
1349	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1350	{
1351	#endif /* VBOX */
1352	uint32_t val;
1353	int index;
1354
1355	#ifndef VBOX
1356	env = cpu_single_env;
1357	if (!env)
1358	return 0;
1359	s = env->apic_state;
1360	#endif /* !VBOX */
1361
1362	index = (addr >> 4) & 0xff;
1363	switch(index) {
1364	case 0x02: /* id */
1365	val = s->id << 24;
1366	break;
1367	case 0x03: /* version */
1368	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1369	break;
1370	case 0x08:
1371	val = s->tpr;
1372	break;
1373	case 0x09:
1374	val = apic_get_arb_pri(s);
1375	break;
1376	case 0x0a:
1377	/* ppr */
1378	val = apic_get_ppr(s);
1379	break;
1380	case 0x0b:
1381	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1382	val = 0;
1383	break;
1384	case 0x0d:
1385	val = s->log_dest << 24;
1386	break;
1387	case 0x0e:
1388	#ifdef VBOX
1389	/* Bottom 28 bits are always 1 */
1390	val = (s->dest_mode << 28) \| 0xfffffff;
1391	#else
1392	val = s->dest_mode << 28;
1393	#endif
1394	break;
1395	case 0x0f:
1396	val = s->spurious_vec;
1397	break;
1398	#ifndef VBOX
1399	case 0x10 ... 0x17:
1400	#else /* VBOX */
1401	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1402	#endif /* VBOX */
1403	val = s->isr[index & 7];
1404	break;
1405	#ifndef VBOX
1406	case 0x18 ... 0x1f:
1407	#else /* VBOX */
1408	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1409	#endif /* VBOX */
1410	val = s->tmr[index & 7];
1411	break;
1412	#ifndef VBOX
1413	case 0x20 ... 0x27:
1414	#else /* VBOX */
1415	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1416	#endif /* VBOX */
1417	val = s->irr[index & 7];
1418	break;
1419	case 0x28:
1420	val = s->esr;
1421	break;
1422	case 0x30:
1423	case 0x31:
1424	val = s->icr[index & 1];
1425	break;
1426	#ifndef VBOX
1427	case 0x32 ... 0x37:
1428	#else /* VBOX */
1429	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1430	#endif /* VBOX */
1431	val = s->lvt[index - 0x32];
1432	break;
1433	case 0x38:
1434	val = s->initial_count;
1435	break;
1436	case 0x39:
1437	val = apic_get_current_count(dev, s);
1438	break;
1439	case 0x3e:
1440	val = s->divide_conf;
1441	break;
1442	default:
1443	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1444	s->esr \|= ESR_ILLEGAL_ADDRESS;
1445	val = 0;
1446	break;
1447	}
1448	#ifdef DEBUG_APIC
1449	Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1450	#endif
1451	return val;
1452	}
1453
1454	#ifndef VBOX
1455	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1456	{
1457	CPUState *env;
1458	APICState *s;
1459	#else /* VBOX */
1460	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1461	{
1462	int rc = VINF_SUCCESS;
1463	#endif /* VBOX */
1464	int index;
1465
1466	#ifndef VBOX
1467	env = cpu_single_env;
1468	if (!env)
1469	return;
1470	s = env->apic_state;
1471	#endif /* !VBOX */
1472
1473	#ifdef DEBUG_APIC
1474	Log(("CPU%d: APIC write: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1475	#endif
1476
1477	index = (addr >> 4) & 0xff;
1478	switch(index) {
1479	case 0x02:
1480	s->id = (val >> 24);
1481	break;
1482	case 0x03:
1483	Log(("apic_mem_writel: write to version register; ignored\n"));
1484	break;
1485	case 0x08:
1486	#ifdef VBOX
1487	apic_update_tpr(dev, s, val);
1488	#else
1489	s->tpr = val;
1490	apic_update_irq(s);
1491	#endif
1492	break;
1493	case 0x09:
1494	case 0x0a:
1495	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1496	break;
1497	case 0x0b: /* EOI */
1498	apic_eoi(dev, s);
1499	break;
1500	case 0x0d:
1501	s->log_dest = val >> 24;
1502	break;
1503	case 0x0e:
1504	s->dest_mode = val >> 28;
1505	break;
1506	case 0x0f:
1507	s->spurious_vec = val & 0x1ff;
1508	apic_update_irq(dev, s);
1509	break;
1510	#ifndef VBOX
1511	case 0x10 ... 0x17:
1512	case 0x18 ... 0x1f:
1513	case 0x20 ... 0x27:
1514	case 0x28:
1515	#else
1516	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1517	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1518	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1519	case 0x28:
1520	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1521	#endif
1522	break;
1523
1524	case 0x30:
1525	s->icr[0] = val;
1526	rc = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1527	(s->icr[0] >> 11) & 1,
1528	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1529	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1530	break;
1531	case 0x31:
1532	s->icr[1] = val;
1533	break;
1534	#ifndef VBOX
1535	case 0x32 ... 0x37:
1536	#else /* VBOX */
1537	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1538	#endif /* VBOX */
1539	{
1540	int n = index - 0x32;
1541	s->lvt[n] = val;
1542	if (n == APIC_LVT_TIMER)
1543	#ifndef VBOX
1544	apic_timer_update(s, qemu_get_clock(vm_clock));
1545	#else /* VBOX */
1546	apic_timer_update(dev, s, TMTimerGet(s->CTX_SUFF(pTimer)));
1547	#endif /* VBOX*/
1548	}
1549	break;
1550	case 0x38:
1551	s->initial_count = val;
1552	#ifndef VBOX
1553	s->initial_count_load_time = qemu_get_clock(vm_clock);
1554	#else /* VBOX */
1555	s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
1556	#endif /* VBOX*/
1557	apic_timer_update(dev, s, s->initial_count_load_time);
1558	break;
1559	case 0x39:
1560	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1561	break;
1562	case 0x3e:
1563	{
1564	int v;
1565	s->divide_conf = val & 0xb;
1566	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1567	s->count_shift = (v + 1) & 7;
1568	}
1569	break;
1570	default:
1571	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1572	s->esr \|= ESR_ILLEGAL_ADDRESS;
1573	break;
1574	}
1575	#ifdef VBOX
1576	return rc;
1577	#endif
1578	}
1579
1580	#ifdef IN_RING3
1581
1582	static void apic_save(QEMUFile f, void opaque)
1583	{
1584	APICState s = (APICState)opaque;
1585	int i;
1586
1587	qemu_put_be32s(f, &s->apicbase);
1588	#ifdef VBOX
1589	qemu_put_be32s(f, &s->id);
1590	qemu_put_be32s(f, &s->phys_id);
1591	qemu_put_be32s(f, &s->arb_id);
1592	qemu_put_be32s(f, &s->tpr);
1593	#else
1594	qemu_put_8s(f, &s->id);
1595	qemu_put_8s(f, &s->arb_id);
1596	qemu_put_8s(f, &s->tpr);
1597	#endif
1598	qemu_put_be32s(f, &s->spurious_vec);
1599	qemu_put_8s(f, &s->log_dest);
1600	qemu_put_8s(f, &s->dest_mode);
1601	for (i = 0; i < 8; i++) {
1602	qemu_put_be32s(f, &s->isr[i]);
1603	qemu_put_be32s(f, &s->tmr[i]);
1604	qemu_put_be32s(f, &s->irr[i]);
1605	}
1606	for (i = 0; i < APIC_LVT_NB; i++) {
1607	qemu_put_be32s(f, &s->lvt[i]);
1608	}
1609	qemu_put_be32s(f, &s->esr);
1610	qemu_put_be32s(f, &s->icr[0]);
1611	qemu_put_be32s(f, &s->icr[1]);
1612	qemu_put_be32s(f, &s->divide_conf);
1613	qemu_put_be32s(f, &s->count_shift);
1614	qemu_put_be32s(f, &s->initial_count);
1615	qemu_put_be64s(f, &s->initial_count_load_time);
1616	qemu_put_be64s(f, &s->next_time);
1617
1618	#ifdef VBOX
1619	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1620	#endif
1621	}
1622
1623	static int apic_load(QEMUFile f, void opaque, int version_id)
1624	{
1625	APICState s = (APICState)opaque;
1626	int i;
1627
1628	#ifdef VBOX
1629	if ((version_id < 1) \|\| (version_id > 2))
1630	return -EINVAL;
1631
1632	/* XXX: what if the base changes? (registered memory regions) */
1633	qemu_get_be32s(f, &s->apicbase);
1634
1635	switch (version_id)
1636	{
1637	case 1:
1638	{
1639	uint8_t val = 0;
1640	qemu_get_8s(f, &val);
1641	s->id = val;
1642	/* UP only in old saved states */
1643	s->phys_id = 0;
1644	qemu_get_8s(f, &val);
1645	s->arb_id = val;
1646	break;
1647	}
1648	case 2:
1649	qemu_get_be32s(f, &s->id);
1650	qemu_get_be32s(f, &s->phys_id);
1651	qemu_get_be32s(f, &s->arb_id);
1652	break;
1653	}
1654	qemu_get_be32s(f, &s->tpr);
1655	#else
1656	if (version_id != 1)
1657	return -EINVAL;
1658
1659	/* XXX: what if the base changes? (registered memory regions) */
1660	qemu_get_be32s(f, &s->apicbase);
1661	qemu_get_8s(f, &s->id);
1662	qemu_get_8s(f, &s->arb_id);
1663	qemu_get_8s(f, &s->tpr);
1664	#endif
1665	qemu_get_be32s(f, &s->spurious_vec);
1666	qemu_get_8s(f, &s->log_dest);
1667	qemu_get_8s(f, &s->dest_mode);
1668	for (i = 0; i < 8; i++) {
1669	qemu_get_be32s(f, &s->isr[i]);
1670	qemu_get_be32s(f, &s->tmr[i]);
1671	qemu_get_be32s(f, &s->irr[i]);
1672	}
1673	for (i = 0; i < APIC_LVT_NB; i++) {
1674	qemu_get_be32s(f, &s->lvt[i]);
1675	}
1676	qemu_get_be32s(f, &s->esr);
1677	qemu_get_be32s(f, &s->icr[0]);
1678	qemu_get_be32s(f, &s->icr[1]);
1679	qemu_get_be32s(f, &s->divide_conf);
1680	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1681	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1682	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1683	qemu_get_be64s(f, (uint64_t *)&s->next_time);
1684
1685	#ifdef VBOX
1686	TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1687	#endif
1688
1689	return VINF_SUCCESS;
1690	}
1691	#ifndef VBOX
1692	static void apic_reset(void *opaque)
1693	{
1694	APICState s = (APICState)opaque;
1695	apic_init_ipi(s);
1696	}
1697	#endif
1698
1699	#endif /* IN_RING3 */
1700
1701	#ifndef VBOX
1702	static CPUReadMemoryFunc *apic_mem_read[3] = {
1703	apic_mem_readb,
1704	apic_mem_readw,
1705	apic_mem_readl,
1706	};
1707
1708	static CPUWriteMemoryFunc *apic_mem_write[3] = {
1709	apic_mem_writeb,
1710	apic_mem_writew,
1711	apic_mem_writel,
1712	};
1713
1714	int apic_init(CPUState *env)
1715	{
1716	APICState *s;
1717
1718	s = qemu_mallocz(sizeof(APICState));
1719	if (!s)
1720	return -1;
1721	env->apic_state = s;
1722	apic_init_ipi(s);
1723	s->id = last_apic_id++;
1724	s->cpu_env = env;
1725	s->apicbase = 0xfee00000 \|
1726	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
1727
1728	/* XXX: mapping more APICs at the same memory location */
1729	if (apic_io_memory == 0) {
1730	/* NOTE: the APIC is directly connected to the CPU - it is not
1731	on the global memory bus. */
1732	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1733	apic_mem_write, NULL);
1734	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1735	apic_io_memory);
1736	}
1737	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1738
1739	register_savevm("apic", 0, 1, apic_save, apic_load, s);
1740	qemu_register_reset(apic_reset, s);
1741
1742	s->next_apic = first_local_apic;
1743	first_local_apic = s;
1744
1745	return 0;
1746	}
1747	#endif /* !VBOX */
1748
1749	static void ioapic_service(IOAPICState *s)
1750	{
1751	uint8_t i;
1752	uint8_t trig_mode;
1753	uint8_t vector;
1754	uint8_t delivery_mode;
1755	uint32_t mask;
1756	uint64_t entry;
1757	uint8_t dest;
1758	uint8_t dest_mode;
1759	uint8_t polarity;
1760
1761	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1762	mask = 1 << i;
1763	if (s->irr & mask) {
1764	entry = s->ioredtbl[i];
1765	if (!(entry & APIC_LVT_MASKED)) {
1766	trig_mode = ((entry >> 15) & 1);
1767	dest = entry >> 56;
1768	dest_mode = (entry >> 11) & 1;
1769	delivery_mode = (entry >> 8) & 7;
1770	polarity = (entry >> 13) & 1;
1771	if (trig_mode == APIC_TRIGGER_EDGE)
1772	s->irr &= ~mask;
1773	if (delivery_mode == APIC_DM_EXTINT)
1774	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1775	vector = pic_read_irq(isa_pic);
1776	#else /* VBOX */
1777	{
1778	AssertMsgFailed(("Delivery mode ExtINT"));
1779	vector = 0xff; /* incorrect but shuts up gcc. */
1780	}
1781	#endif /* VBOX */
1782	else
1783	vector = entry & 0xff;
1784
1785	#ifndef VBOX
1786	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1787	delivery_mode, vector, polarity, trig_mode);
1788	#else /* VBOX */
1789	int rc = s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1790	dest,
1791	dest_mode,
1792	delivery_mode,
1793	vector,
1794	polarity,
1795	trig_mode);
1796	/* We must be sure that attempts to reschedule in R3
1797	never get here */
1798	Assert(rc == VINF_SUCCESS);
1799	#endif /* VBOX */
1800	}
1801	}
1802	}
1803	}
1804
1805	#ifdef VBOX
1806	static
1807	#endif
1808	void ioapic_set_irq(void *opaque, int vector, int level)
1809	{
1810	IOAPICState s = (IOAPICState)opaque;
1811
1812	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1813	uint32_t mask = 1 << vector;
1814	uint64_t entry = s->ioredtbl[vector];
1815
1816	if ((entry >> 15) & 1) {
1817	/* level triggered */
1818	if (level) {
1819	s->irr \|= mask;
1820	ioapic_service(s);
1821	#ifdef VBOX
1822	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1823	s->irr &= ~mask;
1824	}
1825	#endif
1826	} else {
1827	s->irr &= ~mask;
1828	}
1829	} else {
1830	/* edge triggered */
1831	if (level) {
1832	s->irr \|= mask;
1833	ioapic_service(s);
1834	}
1835	}
1836	}
1837	}
1838
1839	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1840	{
1841	IOAPICState s = (IOAPICState)opaque;
1842	int index;
1843	uint32_t val = 0;
1844
1845	addr &= 0xff;
1846	if (addr == 0x00) {
1847	val = s->ioregsel;
1848	} else if (addr == 0x10) {
1849	switch (s->ioregsel) {
1850	case 0x00:
1851	val = s->id << 24;
1852	break;
1853	case 0x01:
1854	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1855	break;
1856	case 0x02:
1857	val = 0;
1858	break;
1859	default:
1860	index = (s->ioregsel - 0x10) >> 1;
1861	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1862	if (s->ioregsel & 1)
1863	val = s->ioredtbl[index] >> 32;
1864	else
1865	val = s->ioredtbl[index] & 0xffffffff;
1866	}
1867	}
1868	#ifdef DEBUG_IOAPIC
1869	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1870	#endif
1871	}
1872	return val;
1873	}
1874
1875	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1876	{
1877	IOAPICState s = (IOAPICState)opaque;
1878	int index;
1879
1880	addr &= 0xff;
1881	if (addr == 0x00) {
1882	s->ioregsel = val;
1883	return;
1884	} else if (addr == 0x10) {
1885	#ifdef DEBUG_IOAPIC
1886	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1887	#endif
1888	switch (s->ioregsel) {
1889	case 0x00:
1890	s->id = (val >> 24) & 0xff;
1891	return;
1892	case 0x01:
1893	case 0x02:
1894	return;
1895	default:
1896	index = (s->ioregsel - 0x10) >> 1;
1897	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1898	if (s->ioregsel & 1) {
1899	s->ioredtbl[index] &= 0xffffffff;
1900	s->ioredtbl[index] \|= (uint64_t)val << 32;
1901	} else {
1902	#ifdef VBOX
1903	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1904	uint8_t vec = val & 0xff;
1905	if ((val & APIC_LVT_MASKED) \|\|
1906	((vec >= 0x10) && (vec < 0xff)))
1907	{
1908	s->ioredtbl[index] &= ~0xffffffffULL;
1909	s->ioredtbl[index] \|= val;
1910	}
1911	else
1912	{
1913	/*
1914	* Linux 2.6 kernels has pretty strange function
1915	* unlock_ExtINT_logic() which writes
1916	* absolutely bogus (all 0) value into the vector
1917	* with pretty vague explanation why.
1918	* So we just ignore such writes.
1919	*/
1920	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1921	}
1922	}
1923	#else
1924	s->ioredtbl[index] &= ~0xffffffffULL;
1925	s->ioredtbl[index] \|= val;
1926	#endif
1927	ioapic_service(s);
1928	}
1929	}
1930	}
1931	}
1932
1933	#ifdef IN_RING3
1934
1935	static void ioapic_save(QEMUFile f, void opaque)
1936	{
1937	IOAPICState s = (IOAPICState)opaque;
1938	int i;
1939
1940	qemu_put_8s(f, &s->id);
1941	qemu_put_8s(f, &s->ioregsel);
1942	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1943	qemu_put_be64s(f, &s->ioredtbl[i]);
1944	}
1945	}
1946
1947	static int ioapic_load(QEMUFile f, void opaque, int version_id)
1948	{
1949	IOAPICState s = (IOAPICState)opaque;
1950	int i;
1951
1952	if (version_id != 1)
1953	return -EINVAL;
1954
1955	qemu_get_8s(f, &s->id);
1956	qemu_get_8s(f, &s->ioregsel);
1957	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1958	qemu_get_be64s(f, &s->ioredtbl[i]);
1959	}
1960	return 0;
1961	}
1962
1963	static void ioapic_reset(void *opaque)
1964	{
1965	IOAPICState s = (IOAPICState)opaque;
1966	#ifdef VBOX
1967	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1968	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1969	#endif
1970	int i;
1971
1972	memset(s, 0, sizeof(*s));
1973	for(i = 0; i < IOAPIC_NUM_PINS; i++)
1974	s->ioredtbl[i] = 1 << 16; /* mask LVT */
1975
1976	#ifdef VBOX
1977	if (pDevIns)
1978	{
1979	s->pDevInsR3 = pDevIns;
1980	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1981	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1982	}
1983	if (pIoApicHlp)
1984	{
1985	s->pIoApicHlpR3 = pIoApicHlp;
1986	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1987	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1988	}
1989	#endif
1990	}
1991
1992	#endif /* IN_RING3 */
1993
1994	#ifndef VBOX
1995	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1996	ioapic_mem_readl,
1997	ioapic_mem_readl,
1998	ioapic_mem_readl,
1999	};
2000
2001	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
2002	ioapic_mem_writel,
2003	ioapic_mem_writel,
2004	ioapic_mem_writel,
2005	};
2006
2007	IOAPICState *ioapic_init(void)
2008	{
2009	IOAPICState *s;
2010	int io_memory;
2011
2012	s = qemu_mallocz(sizeof(IOAPICState));
2013	if (!s)
2014	return NULL;
2015	ioapic_reset(s);
2016	s->id = last_apic_id++;
2017
2018	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
2019	ioapic_mem_write, s);
2020	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2021
2022	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2023	qemu_register_reset(ioapic_reset, s);
2024
2025	return s;
2026	}
2027	#endif /* !VBOX */
2028
2029	/* LAPIC */
2030	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2031	{
2032	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2033	APICState *s = getLapic(dev);
2034
2035	Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2036
2037	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2038	different physical addresses, see #3092) */
2039
2040	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2041	switch (cb)
2042	{
2043	case 1:
2044	(uint8_t )pv = 0;
2045	break;
2046
2047	case 2:
2048	(uint16_t )pv = 0;
2049	break;
2050
2051	case 4:
2052	{
2053	#if 0 /** @note experimental */
2054	#ifndef IN_RING3
2055	uint32_t index = (GCPhysAddr >> 4) & 0xff;
2056
2057	if ( index == 0x08 /* TPR */
2058	&& ++s->ulTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2059	{
2060	#ifdef IN_RC
2061	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2062	#else
2063	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2064	pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2065	#endif
2066	return VINF_PATM_HC_MMIO_PATCH_READ;
2067	}
2068	#endif
2069	#endif /* experimental */
2070	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2071	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
2072	APIC_UNLOCK(dev);
2073	break;
2074	}
2075	default:
2076	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2077	return VERR_INTERNAL_ERROR;
2078	}
2079	return VINF_SUCCESS;
2080	}
2081
2082	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2083	{
2084	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2085	APICState *s = getLapic(dev);
2086
2087	Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2088
2089	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2090	different physical addresses, see #3092) */
2091
2092	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2093	switch (cb)
2094	{
2095	case 1:
2096	case 2:
2097	/* ignore */
2098	break;
2099
2100	case 4:
2101	{
2102	int rc;
2103	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2104	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2105	APIC_UNLOCK(dev);
2106	return rc;
2107	}
2108
2109	default:
2110	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2111	return VERR_INTERNAL_ERROR;
2112	}
2113	return VINF_SUCCESS;
2114	}
2115
2116	#ifdef IN_RING3
2117
2118	/**
2119	* @copydoc FNSSMDEVSAVEEXEC
2120	*/
2121	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2122	{
2123	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2124
2125	/* save all APICs data, @todo: is it correct? */
2126	foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
2127
2128	return VINF_SUCCESS;
2129	}
2130
2131	/**
2132	* @copydoc FNSSMDEVLOADEXEC
2133	*/
2134	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2135	{
2136	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2137	/* load all APICs data, @todo: is it correct? */
2138	foreach_apic(dev, 0xffffffff,
2139	if (apic_load(pSSMHandle, apic, u32Version))
2140	{
2141	AssertFailed();
2142	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2143	}
2144	);
2145	return VINF_SUCCESS;
2146	}
2147
2148	/**
2149	* @copydoc FNPDMDEVRESET
2150	*/
2151	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2152	{
2153	APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2154	APICState *s = getLapic(dev);
2155
2156	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2157
2158	TMTimerStop(s->CTX_SUFF(pTimer));
2159
2160	apic_init_ipi(dev, s);
2161	/* malc, I've removed the initing duplicated in apic_init_ipi(). This
2162	* arb_id was left over.. */
2163	s->arb_id = 0;
2164	/* Reset should re-enable the APIC. */
2165	s->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_ENABLE;
2166	if (s->phys_id == 0)
2167	s->apicbase \|= MSR_IA32_APICBASE_BSP;
2168	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2169	/* Clear any pending APIC interrupt action flag. */
2170	cpuClearInterrupt(dev, s);
2171	APIC_UNLOCK(dev);
2172	}
2173
2174	/**
2175	* @copydoc FNPDMDEVRELOCATE
2176	*/
2177	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2178	{
2179	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2180	dev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2181	dev->pApicHlpRC = dev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2182	dev->pLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), dev->pLapicsR3);
2183	foreach_apic(dev, 0xffffffff,
2184	apic->pTimerRC = TMTimerRCPtr(apic->CTX_SUFF(pTimer)));
2185	}
2186
2187	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2188	{
2189	int i;
2190	memset(apic, 0, sizeof(*apic));
2191	apic->apicbase = UINT32_C(0xfee00000) \| MSR_IA32_APICBASE_ENABLE;
2192	/* Mark first CPU as BSP */
2193	if (id == 0)
2194	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2195	for (i = 0; i < APIC_LVT_NB; i++)
2196	apic->lvt[i] = 1 << 16; /* mask LVT */
2197	apic->spurious_vec = 0xff;
2198	apic->phys_id = apic->id = id;
2199	}
2200
2201	/**
2202	* @copydoc FNPDMDEVCONSTRUCT
2203	*/
2204	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2205	{
2206	PDMAPICREG ApicReg;
2207	int rc;
2208	uint32_t i;
2209	bool fIOAPIC;
2210	bool fGCEnabled;
2211	bool fR0Enabled;
2212	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2213	uint32_t cCpus;
2214	APICState *apic;
2215
2216	/*
2217	* Only single device instance.
2218	*/
2219	Assert(iInstance == 0);
2220
2221	/*
2222	* Validate configuration.
2223	*/
2224	if (!CFGMR3AreValuesValid(pCfgHandle,
2225	"IOAPIC\0"
2226	"GCEnabled\0"
2227	"R0Enabled\0"
2228	"NumCPUs\0"))
2229	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2230
2231	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIOAPIC, true);
2232	if (RT_FAILURE(rc))
2233	return PDMDEV_SET_ERROR(pDevIns, rc,
2234	N_("Configuration error: Failed to read \"IOAPIC\""));
2235
2236	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2237	if (RT_FAILURE(rc))
2238	return PDMDEV_SET_ERROR(pDevIns, rc,
2239	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2240
2241	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2242	if (RT_FAILURE(rc))
2243	return PDMDEV_SET_ERROR(pDevIns, rc,
2244	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2245
2246	rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2247	if (RT_FAILURE(rc))
2248	return PDMDEV_SET_ERROR(pDevIns, rc,
2249	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2250
2251	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
2252
2253	/*
2254	* Init the data.
2255	*/
2256	pThis->pDevInsR3 = pDevIns;
2257	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2258	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2259	pThis->cCpus = cCpus;
2260	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2261	pThis->enmVersion = PDMAPICVERSION_APIC;
2262
2263	PVM pVM = PDMDevHlpGetVM(pDevIns);
2264	/*
2265	* We are not freeing this memory, as it's automatically released when guest exits.
2266	*/
2267	rc = MMHyperAlloc(pVM, cCpussizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void *)&pThis->pLapicsR3);
2268	if (RT_FAILURE(rc))
2269	return VERR_NO_MEMORY;
2270	pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
2271	pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
2272
2273	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2274	{
2275	initApicData(apic, i);
2276	apic++;
2277	}
2278
2279	/*
2280	* Register the APIC.
2281	*/
2282	ApicReg.u32Version = PDM_APICREG_VERSION;
2283	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2284	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2285	ApicReg.pfnSetBaseR3 = apicSetBase;
2286	ApicReg.pfnGetBaseR3 = apicGetBase;
2287	ApicReg.pfnSetTPRR3 = apicSetTPR;
2288	ApicReg.pfnGetTPRR3 = apicGetTPR;
2289	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2290	ApicReg.pfnReadMSRR3 = apicReadMSR;
2291	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2292	if (fGCEnabled) {
2293	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2294	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2295	ApicReg.pszSetBaseRC = "apicSetBase";
2296	ApicReg.pszGetBaseRC = "apicGetBase";
2297	ApicReg.pszSetTPRRC = "apicSetTPR";
2298	ApicReg.pszGetTPRRC = "apicGetTPR";
2299	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2300	ApicReg.pszReadMSRRC = "apicReadMSR";
2301	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2302	} else {
2303	ApicReg.pszGetInterruptRC = NULL;
2304	ApicReg.pszHasPendingIrqRC = NULL;
2305	ApicReg.pszSetBaseRC = NULL;
2306	ApicReg.pszGetBaseRC = NULL;
2307	ApicReg.pszSetTPRRC = NULL;
2308	ApicReg.pszGetTPRRC = NULL;
2309	ApicReg.pszWriteMSRRC = NULL;
2310	ApicReg.pszReadMSRRC = NULL;
2311	ApicReg.pszBusDeliverRC = NULL;
2312	}
2313	if (fR0Enabled) {
2314	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2315	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2316	ApicReg.pszSetBaseR0 = "apicSetBase";
2317	ApicReg.pszGetBaseR0 = "apicGetBase";
2318	ApicReg.pszSetTPRR0 = "apicSetTPR";
2319	ApicReg.pszGetTPRR0 = "apicGetTPR";
2320	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2321	ApicReg.pszReadMSRR0 = "apicReadMSR";
2322	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2323	} else {
2324	ApicReg.pszGetInterruptR0 = NULL;
2325	ApicReg.pszHasPendingIrqR0 = NULL;
2326	ApicReg.pszSetBaseR0 = NULL;
2327	ApicReg.pszGetBaseR0 = NULL;
2328	ApicReg.pszSetTPRR0 = NULL;
2329	ApicReg.pszGetTPRR0 = NULL;
2330	ApicReg.pszWriteMSRR0 = NULL;
2331	ApicReg.pszReadMSRR0 = NULL;
2332	ApicReg.pszBusDeliverR0 = NULL;
2333	}
2334
2335	Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2336	rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2337	if (RT_FAILURE(rc))
2338	{
2339	AssertLogRelMsgFailed(("APICRegister -> %Rrc\n", rc));
2340	return rc;
2341	}
2342
2343	/*
2344	* The the CPUID feature bit.
2345	*/
2346	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2347	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2348	if (u32Eax >= 1)
2349	{
2350	if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
2351	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2352	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2353	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2354	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2355	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2356	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2357	{
2358	LogRel(("Activating Local APIC\n"));
2359	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2360	}
2361	}
2362
2363	/*
2364	* Register the MMIO range.
2365	* @todo: may need to rethink for cases when different LAPICs mapped to different address
2366	* (see IA32_APIC_BASE_MSR)
2367	*/
2368	rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
2369	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2370	if (RT_FAILURE(rc))
2371	return rc;
2372
2373	if (fGCEnabled) {
2374	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2375
2376	rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2377	"apicMMIOWrite", "apicMMIORead", NULL);
2378	if (RT_FAILURE(rc))
2379	return rc;
2380	}
2381
2382	if (fR0Enabled) {
2383	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2384
2385	rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2386	"apicMMIOWrite", "apicMMIORead", NULL);
2387	if (RT_FAILURE(rc))
2388	return rc;
2389	}
2390
2391	/*
2392	* Create the APIC timers.
2393	*/
2394	for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2395	{
2396	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer,
2397	"APIC Timer", &apic->pTimerR3);
2398	if (RT_FAILURE(rc))
2399	return rc;
2400	apic->pTimerR0 = TMTimerR0Ptr(apic->pTimerR3);
2401	apic->pTimerRC = TMTimerRCPtr(apic->pTimerR3);
2402	apic++;
2403	}
2404
2405	/*
2406	* Saved state.
2407	*/
2408	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
2409	sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
2410	if (RT_FAILURE(rc))
2411	return rc;
2412
2413	#ifdef VBOX_WITH_STATISTICS
2414	/*
2415	* Statistics.
2416	*/
2417	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2418	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2419	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2420	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2421	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq, STAMTYPE_COUNTER, "/PDM/APIC/Masked/ActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2422	#endif
2423
2424	return VINF_SUCCESS;
2425	}
2426
2427
2428	/**
2429	* APIC device registration structure.
2430	*/
2431	const PDMDEVREG g_DeviceAPIC =
2432	{
2433	/* u32Version */
2434	PDM_DEVREG_VERSION,
2435	/* szDeviceName */
2436	"apic",
2437	/* szRCMod */
2438	"VBoxDD2GC.gc",
2439	/* szR0Mod */
2440	"VBoxDD2R0.r0",
2441	/* pszDescription */
2442	"Advanced Programmable Interrupt Controller (APIC) Device",
2443	/* fFlags */
2444	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2445	/* fClass */
2446	PDM_DEVREG_CLASS_PIC,
2447	/* cMaxInstances */
2448	1,
2449	/* cbInstance */
2450	sizeof(APICState),
2451	/* pfnConstruct */
2452	apicConstruct,
2453	/* pfnDestruct */
2454	NULL,
2455	/* pfnRelocate */
2456	apicRelocate,
2457	/* pfnIOCtl */
2458	NULL,
2459	/* pfnPowerOn */
2460	NULL,
2461	/* pfnReset */
2462	apicReset,
2463	/* pfnSuspend */
2464	NULL,
2465	/* pfnResume */
2466	NULL,
2467	/* pfnAttach */
2468	NULL,
2469	/* pfnDetach */
2470	NULL,
2471	/* pfnQueryInterface. */
2472	NULL,
2473	/* pfnInitComplete */
2474	NULL,
2475	/* pfnPowerOff */
2476	NULL,
2477	/* pfnSoftReset */
2478	NULL,
2479	/* u32VersionEnd */
2480	PDM_DEVREG_VERSION
2481	};
2482
2483	#endif /* IN_RING3 */
2484
2485
2486	/* IOAPIC */
2487
2488	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2489	{
2490	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2491	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2492
2493	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2494	switch (cb)
2495	{
2496	case 1:
2497	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2498	break;
2499
2500	case 2:
2501	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2502	break;
2503
2504	case 4:
2505	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2506	break;
2507
2508	default:
2509	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2510	IOAPIC_UNLOCK(s);
2511	return VERR_INTERNAL_ERROR;
2512	}
2513	IOAPIC_UNLOCK(s);
2514	return VINF_SUCCESS;
2515	}
2516
2517	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2518	{
2519	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2520
2521	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2522	switch (cb)
2523	{
2524	case 1:
2525	case 2:
2526	case 4:
2527	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2528	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
2529	IOAPIC_UNLOCK(s);
2530	break;
2531
2532	default:
2533	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2534	return VERR_INTERNAL_ERROR;
2535	}
2536	return VINF_SUCCESS;
2537	}
2538
2539	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2540	{
2541	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
2542	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2543	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2544	ioapic_set_irq(pThis, iIrq, iLevel);
2545	}
2546
2547
2548	#ifdef IN_RING3
2549
2550	/**
2551	* @copydoc FNSSMDEVSAVEEXEC
2552	*/
2553	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2554	{
2555	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2556	ioapic_save(pSSMHandle, s);
2557	return VINF_SUCCESS;
2558	}
2559
2560	/**
2561	* @copydoc FNSSMDEVLOADEXEC
2562	*/
2563	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2564	{
2565	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2566
2567	if (ioapic_load(pSSMHandle, s, u32Version)) {
2568	AssertFailed();
2569	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2570	}
2571
2572	return VINF_SUCCESS;
2573	}
2574
2575	/**
2576	* @copydoc FNPDMDEVRESET
2577	*/
2578	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2579	{
2580	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2581	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2582	ioapic_reset(s);
2583	IOAPIC_UNLOCK(s);
2584	}
2585
2586	/**
2587	* @copydoc FNPDMDEVRELOCATE
2588	*/
2589	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2590	{
2591	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2592	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2593	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2594	}
2595
2596	/**
2597	* @copydoc FNPDMDEVCONSTRUCT
2598	*/
2599	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2600	{
2601	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2602	PDMIOAPICREG IoApicReg;
2603	bool fGCEnabled;
2604	bool fR0Enabled;
2605	int rc;
2606
2607	Assert(iInstance == 0);
2608
2609	/*
2610	* Validate and read the configuration.
2611	*/
2612	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2613	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2614
2615	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2616	if (RT_FAILURE(rc))
2617	return PDMDEV_SET_ERROR(pDevIns, rc,
2618	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2619
2620	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2621	if (RT_FAILURE(rc))
2622	return PDMDEV_SET_ERROR(pDevIns, rc,
2623	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2624	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2625
2626	/*
2627	* Initialize the state data.
2628	*/
2629	s->pDevInsR3 = pDevIns;
2630	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2631	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2632	ioapic_reset(s);
2633	s->id = 0;
2634
2635	/*
2636	* Register the IOAPIC and get helpers.
2637	*/
2638	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2639	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2640	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2641	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2642	rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2643	if (RT_FAILURE(rc))
2644	{
2645	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2646	return rc;
2647	}
2648
2649	/*
2650	* Register MMIO callbacks and saved state.
2651	*/
2652	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2653	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2654	if (RT_FAILURE(rc))
2655	return rc;
2656
2657	if (fGCEnabled) {
2658	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2659
2660	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2661	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2662	if (RT_FAILURE(rc))
2663	return rc;
2664	}
2665
2666	if (fR0Enabled) {
2667	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2668
2669	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2670	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2671	if (RT_FAILURE(rc))
2672	return rc;
2673	}
2674
2675	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2676	sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2677	if (RT_FAILURE(rc))
2678	return rc;
2679
2680	#ifdef VBOX_WITH_STATISTICS
2681	/*
2682	* Statistics.
2683	*/
2684	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2685	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2686	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2687	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2688	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2689	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2690	#endif
2691
2692	return VINF_SUCCESS;
2693	}
2694
2695	/**
2696	* IO APIC device registration structure.
2697	*/
2698	const PDMDEVREG g_DeviceIOAPIC =
2699	{
2700	/* u32Version */
2701	PDM_DEVREG_VERSION,
2702	/* szDeviceName */
2703	"ioapic",
2704	/* szRCMod */
2705	"VBoxDD2GC.gc",
2706	/* szR0Mod */
2707	"VBoxDD2R0.r0",
2708	/* pszDescription */
2709	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2710	/* fFlags */
2711	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2712	/* fClass */
2713	PDM_DEVREG_CLASS_PIC,
2714	/* cMaxInstances */
2715	1,
2716	/* cbInstance */
2717	sizeof(IOAPICState),
2718	/* pfnConstruct */
2719	ioapicConstruct,
2720	/* pfnDestruct */
2721	NULL,
2722	/* pfnRelocate */
2723	ioapicRelocate,
2724	/* pfnIOCtl */
2725	NULL,
2726	/* pfnPowerOn */
2727	NULL,
2728	/* pfnReset */
2729	ioapicReset,
2730	/* pfnSuspend */
2731	NULL,
2732	/* pfnResume */
2733	NULL,
2734	/* pfnAttach */
2735	NULL,
2736	/* pfnDetach */
2737	NULL,
2738	/* pfnQueryInterface. */
2739	NULL,
2740	/* pfnInitComplete */
2741	NULL,
2742	/* pfnPowerOff */
2743	NULL,
2744	/* pfnSoftReset */
2745	NULL,
2746	/* u32VersionEnd */
2747	PDM_DEVREG_VERSION
2748	};
2749
2750	#endif /* IN_RING3 */
2751	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 19741

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