DevAPIC.cpp@ 24323

Last change on this file since 24323 was 24265, checked in by vboxsync, 15 years ago
Devices,VMM: Replaced all VERR_SSM_LOAD_CONFIG_MISMATCH returns with SSMR3SetCfgError calls.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 109.4 KB

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1	#ifdef VBOX
2	/* $Id: DevAPIC.cpp 24265 2009-11-02 15:21:30Z vboxsync $ */
3	/** @file
4	* Advanced Programmable Interrupt Controller (APIC) Device and
5	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* apic.c revision 1.5 @@OSETODO
27	*/
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/pdmdev.h>
34
35	#include <VBox/log.h>
36	#include <VBox/stam.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40	#include "Builtins2.h"
41	#include "vl_vbox.h"
42
43	#define MSR_IA32_APICBASE 0x1b
44	#define MSR_IA32_APICBASE_BSP (1<<8)
45	#define MSR_IA32_APICBASE_ENABLE (1<<11)
46	#ifdef VBOX
47	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48	#endif
49	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51	#ifndef EINVAL
52	# define EINVAL 1
53	#endif
54
55	#ifdef _MSC_VER
56	# pragma warning(disable:4244)
57	#endif
58
59	/** The current saved state version.*/
60	#define APIC_SAVED_STATE_VERSION 3
61	/** The saved state version used by VirtualBox v3 and earlier.
62	* This does not include the config. */
63	#define APIC_SAVED_STATE_VERSION_VBOX_30 2
64	/** Some ancient version... */
65	#define APIC_SAVED_STATE_VERSION_ANCIENT 1
66
67
68	/** @def APIC_LOCK
69	* Acquires the PDM lock. */
70	#define APIC_LOCK(pThis, rcBusy) \
71	do { \
72	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
73	if (rc2 != VINF_SUCCESS) \
74	return rc2; \
75	} while (0)
76
77	/** @def APIC_LOCK_VOID
78	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
79	#define APIC_LOCK_VOID(pThis, rcBusy) \
80	do { \
81	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
82	AssertLogRelRCReturnVoid(rc2); \
83	} while (0)
84
85	/** @def APIC_UNLOCK
86	* Releases the PDM lock. */
87	#define APIC_UNLOCK(pThis) \
88	PDMCritSectLeave((pThis)->CTX_SUFF(pCritSect))
89
90	/** @def IOAPIC_LOCK
91	* Acquires the PDM lock. */
92	#define IOAPIC_LOCK(pThis, rc) \
93	do { \
94	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
95	if (rc2 != VINF_SUCCESS) \
96	return rc2; \
97	} while (0)
98
99	/** @def IOAPIC_UNLOCK
100	* Releases the PDM lock. */
101	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
102
103
104	#define foreach_apic(dev, mask, code) \
105	do { \
106	uint32_t i; \
107	APICState *apic = (dev)->CTX_SUFF(paLapics); \
108	for (i = 0; i < (dev)->cCpus; i++) \
109	{ \
110	if (mask & (1 << (apic->id))) \
111	{ \
112	code; \
113	} \
114	apic++; \
115	} \
116	} while (0)
117
118	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
119	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
120	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
121	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
122
123	#endif /* VBOX */
124
125	/*
126	* APIC support
127	*
128	* Copyright (c) 2004-2005 Fabrice Bellard
129	*
130	* This library is free software; you can redistribute it and/or
131	* modify it under the terms of the GNU Lesser General Public
132	* License as published by the Free Software Foundation; either
133	* version 2 of the License, or (at your option) any later version.
134	*
135	* This library is distributed in the hope that it will be useful,
136	* but WITHOUT ANY WARRANTY; without even the implied warranty of
137	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
138	* Lesser General Public License for more details.
139	*
140	* You should have received a copy of the GNU Lesser General Public
141	* License along with this library; if not, write to the Free Software
142	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
143	*/
144	#ifndef VBOX
145	#include "vl.h"
146	#endif
147
148	#define DEBUG_APIC
149	#define DEBUG_IOAPIC
150
151	/* APIC Local Vector Table */
152	#define APIC_LVT_TIMER 0
153	#define APIC_LVT_THERMAL 1
154	#define APIC_LVT_PERFORM 2
155	#define APIC_LVT_LINT0 3
156	#define APIC_LVT_LINT1 4
157	#define APIC_LVT_ERROR 5
158	#define APIC_LVT_NB 6
159
160	/* APIC delivery modes */
161	#define APIC_DM_FIXED 0
162	#define APIC_DM_LOWPRI 1
163	#define APIC_DM_SMI 2
164	#define APIC_DM_NMI 4
165	#define APIC_DM_INIT 5
166	#define APIC_DM_SIPI 6
167	#define APIC_DM_EXTINT 7
168
169	/* APIC destination mode */
170	#define APIC_DESTMODE_FLAT 0xf
171	#define APIC_DESTMODE_CLUSTER 1
172
173	#define APIC_TRIGGER_EDGE 0
174	#define APIC_TRIGGER_LEVEL 1
175
176	#define APIC_LVT_TIMER_PERIODIC (1<<17)
177	#define APIC_LVT_MASKED (1<<16)
178	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
179	#define APIC_LVT_REMOTE_IRR (1<<14)
180	#define APIC_INPUT_POLARITY (1<<13)
181	#define APIC_SEND_PENDING (1<<12)
182
183	#define IOAPIC_NUM_PINS 0x18
184
185	#define ESR_ILLEGAL_ADDRESS (1 << 7)
186
187	#define APIC_SV_ENABLE (1 << 8)
188
189	#ifdef VBOX
190	#define APIC_MAX_PATCH_ATTEMPTS 100
191
192	typedef uint32_t PhysApicId;
193	typedef uint32_t LogApicId;
194	#endif
195
196	typedef struct APICState {
197	#ifndef VBOX
198	CPUState *cpu_env;
199	#endif /* !VBOX */
200	uint32_t apicbase;
201	#ifdef VBOX
202	/* Task priority register (interrupt level) */
203	uint32_t tpr;
204	/* Logical APIC id - user programmable */
205	LogApicId id;
206	/* Physical APIC id - not visible to user, constant */
207	PhysApicId phys_id;
208	/** @todo: is it logical or physical? Not really used anyway now. */
209	PhysApicId arb_id;
210	#else
211	uint8_t tpr;
212	uint8_t id;
213	uint8_t arb_id;
214	#endif
215	uint32_t spurious_vec;
216	uint8_t log_dest;
217	uint8_t dest_mode;
218	uint32_t isr[8]; /* in service register */
219	uint32_t tmr[8]; /* trigger mode register */
220	uint32_t irr[8]; /* interrupt request register */
221	uint32_t lvt[APIC_LVT_NB];
222	uint32_t esr; /* error register */
223	uint32_t icr[2];
224	uint32_t divide_conf;
225	int count_shift;
226	uint32_t initial_count;
227	#ifdef VBOX
228	uint32_t Alignment0;
229	#endif
230	#ifndef VBOX
231	int64_t initial_count_load_time, next_time;
232	QEMUTimer *timer;
233	struct APICState *next_apic;
234	#else
235	/** The time stamp of the initial_count load, i.e. when it was started. */
236	uint64_t initial_count_load_time;
237	/** The time stamp of the next timer callback. */
238	uint64_t next_time;
239	/** The APIC timer - R3 Ptr. */
240	PTMTIMERR3 pTimerR3;
241	/** The APIC timer - R0 Ptr. */
242	PTMTIMERR0 pTimerR0;
243	/** The APIC timer - RC Ptr. */
244	PTMTIMERRC pTimerRC;
245	/** Whether the timer is armed or not */
246	bool fTimerArmed;
247	/** Alignment */
248	bool afAlignment[3];
249	/** Timer description timer. */
250	R3PTRTYPE(char *) pszDesc;
251	# ifdef VBOX_WITH_STATISTICS
252	# if HC_ARCH_BITS == 32
253	uint32_t u32Alignment0;
254	# endif
255	STAMCOUNTER StatTimerSetInitialCount;
256	STAMCOUNTER StatTimerSetInitialCountArm;
257	STAMCOUNTER StatTimerSetInitialCountDisarm;
258	STAMCOUNTER StatTimerSetLvt;
259	STAMCOUNTER StatTimerSetLvtClearPeriodic;
260	STAMCOUNTER StatTimerSetLvtPostponed;
261	STAMCOUNTER StatTimerSetLvtArmed;
262	STAMCOUNTER StatTimerSetLvtArm;
263	STAMCOUNTER StatTimerSetLvtArmRetries;
264	STAMCOUNTER StatTimerSetLvtNoRelevantChange;
265	# endif
266	#endif /* VBOX */
267	} APICState;
268	#ifdef VBOX
269	AssertCompileMemberAlignment(APICState, initial_count_load_time, 8);
270	# ifdef VBOX_WITH_STATISTICS
271	AssertCompileMemberAlignment(APICState, StatTimerSetInitialCount, 8);
272	# endif
273	#endif
274
275	struct IOAPICState {
276	uint8_t id;
277	uint8_t ioregsel;
278
279	uint32_t irr;
280	uint64_t ioredtbl[IOAPIC_NUM_PINS];
281
282	#ifdef VBOX
283	/** The device instance - R3 Ptr. */
284	PPDMDEVINSR3 pDevInsR3;
285	/** The IOAPIC helpers - R3 Ptr. */
286	PCPDMIOAPICHLPR3 pIoApicHlpR3;
287
288	/** The device instance - R0 Ptr. */
289	PPDMDEVINSR0 pDevInsR0;
290	/** The IOAPIC helpers - R0 Ptr. */
291	PCPDMIOAPICHLPR0 pIoApicHlpR0;
292
293	/** The device instance - RC Ptr. */
294	PPDMDEVINSRC pDevInsRC;
295	/** The IOAPIC helpers - RC Ptr. */
296	PCPDMIOAPICHLPRC pIoApicHlpRC;
297
298	# ifdef VBOX_WITH_STATISTICS
299	STAMCOUNTER StatMMIOReadGC;
300	STAMCOUNTER StatMMIOReadHC;
301	STAMCOUNTER StatMMIOWriteGC;
302	STAMCOUNTER StatMMIOWriteHC;
303	STAMCOUNTER StatSetIrqGC;
304	STAMCOUNTER StatSetIrqHC;
305	# endif
306	#endif /* VBOX */
307	};
308
309	#ifdef VBOX
310	typedef struct IOAPICState IOAPICState;
311
312	typedef struct
313	{
314	/** The device instance - R3 Ptr. */
315	PPDMDEVINSR3 pDevInsR3;
316	/** The APIC helpers - R3 Ptr. */
317	PCPDMAPICHLPR3 pApicHlpR3;
318	/** LAPICs states - R3 Ptr */
319	R3PTRTYPE(APICState *) paLapicsR3;
320	/** The critical section - R3 Ptr. */
321	R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
322
323	/** The device instance - R0 Ptr. */
324	PPDMDEVINSR0 pDevInsR0;
325	/** The APIC helpers - R0 Ptr. */
326	PCPDMAPICHLPR0 pApicHlpR0;
327	/** LAPICs states - R0 Ptr */
328	R0PTRTYPE(APICState *) paLapicsR0;
329	/** The critical section - R3 Ptr. */
330	R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
331
332	/** The device instance - RC Ptr. */
333	PPDMDEVINSRC pDevInsRC;
334	/** The APIC helpers - RC Ptr. */
335	PCPDMAPICHLPRC pApicHlpRC;
336	/** LAPICs states - RC Ptr */
337	RCPTRTYPE(APICState *) paLapicsRC;
338	/** The critical section - R3 Ptr. */
339	RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
340
341	/** APIC specification version in this virtual hardware configuration. */
342	PDMAPICVERSION enmVersion;
343
344	/** Number of attempts made to optimize TPR accesses. */
345	uint32_t cTPRPatchAttempts;
346
347	/** Number of CPUs on the system (same as LAPIC count). */
348	uint32_t cCpus;
349	/** Whether we've got an IO APIC or not. */
350	bool fIoApic;
351	/** Alignment padding. */
352	bool afPadding[3];
353
354	# ifdef VBOX_WITH_STATISTICS
355	STAMCOUNTER StatMMIOReadGC;
356	STAMCOUNTER StatMMIOReadHC;
357	STAMCOUNTER StatMMIOWriteGC;
358	STAMCOUNTER StatMMIOWriteHC;
359	STAMCOUNTER StatClearedActiveIrq;
360	# endif
361	} APICDeviceInfo;
362	# ifdef VBOX_WITH_STATISTICS
363	AssertCompileMemberAlignment(APICDeviceInfo, StatMMIOReadGC, 8);
364	# endif
365	#endif /* VBOX */
366
367	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
368
369	#ifndef VBOX
370	static int apic_io_memory;
371	static APICState *first_local_apic = NULL;
372	static int last_apic_id = 0;
373	#endif /* !VBOX */
374
375
376	#ifdef VBOX
377	/*******************************************************************************
378	* Internal Functions *
379	*******************************************************************************/
380	RT_C_DECLS_BEGIN
381	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
382	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
383	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
384	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
385	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
386	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
387	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val);
388	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu);
389	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
390	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
391	uint8_t u8TriggerMode);
392	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level);
393	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
394	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
395	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
396	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
397	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
398
399	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
400	RT_C_DECLS_END
401
402	static void apic_eoi(APICDeviceInfo dev, APICState s); /* */
403	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
404	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
405	uint8_t dest, uint8_t dest_mode,
406	uint8_t delivery_mode, uint8_t vector_num,
407	uint8_t polarity, uint8_t trigger_mode);
408	static int apic_get_arb_pri(APICState *s);
409	static int apic_get_ppr(APICState *s);
410	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
411	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState s, uint32_t initial_count);
412	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew);
413	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s);
414
415	#endif /* VBOX */
416
417	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s);
418	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
419	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
420
421
422	#ifdef VBOX
423
424	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
425	{
426	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
427	return &dev->CTX_SUFF(paLapics)[id];
428	}
429
430	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
431	{
432	/* LAPIC's array is indexed by CPU id */
433	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
434	return getLapicById(dev, id);
435	}
436
437	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
438	{
439	/* for now we assume LAPIC physical id == CPU id */
440	return VMCPUID(s->phys_id);
441	}
442
443	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
444	{
445	LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(dev, s)));
446	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
447	getCpuFromLapic(dev, s));
448	}
449
450	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
451	{
452	LogFlow(("apic: clear interrupt flag\n"));
453	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
454	getCpuFromLapic(dev, s));
455	}
456
457	# ifdef IN_RING3
458
459	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
460	{
461	Log2(("apic: send SIPI vector=%d\n", vector));
462
463	dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
464	getCpuFromLapic(dev, s),
465	vector);
466	}
467
468	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* dev, APICState *s)
469	{
470	Log2(("apic: send init IPI\n"));
471
472	dev->pApicHlpR3->pfnSendInitIpi(dev->pDevInsR3,
473	getCpuFromLapic(dev, s));
474	}
475
476	# endif /* IN_RING3 */
477
478	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
479	{
480	switch (dev->enmVersion)
481	{
482	case PDMAPICVERSION_NONE:
483	return 0;
484	case PDMAPICVERSION_APIC:
485	return MSR_IA32_APICBASE_ENABLE;
486	case PDMAPICVERSION_X2APIC:
487	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
488	default:
489	AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
490	return 0;
491	}
492	}
493
494	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
495	{
496	switch (((apic->apicbase) >> 10) & 0x3)
497	{
498	case 0:
499	return PDMAPICVERSION_NONE;
500	case 1:
501	default:
502	/* Invalid */
503	return PDMAPICVERSION_NONE;
504	case 2:
505	return PDMAPICVERSION_APIC;
506	case 3:
507	return PDMAPICVERSION_X2APIC;
508	}
509	}
510
511	#endif /* VBOX */
512
513	#ifndef VBOX
514	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
515	uint8_t vector_num, uint8_t polarity,
516	uint8_t trigger_mode)
517	{
518	APICState *apic_iter;
519	#else /* VBOX */
520	static int apic_bus_deliver(APICDeviceInfo* dev,
521	uint32_t deliver_bitmask, uint8_t delivery_mode,
522	uint8_t vector_num, uint8_t polarity,
523	uint8_t trigger_mode)
524	{
525	#endif /* VBOX */
526
527	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
528	switch (delivery_mode) {
529	case APIC_DM_LOWPRI:
530	{
531	int d = -1;
532	if (deliver_bitmask)
533	d = ffs_bit(deliver_bitmask);
534	if (d >= 0)
535	{
536	APICState* apic = getLapicById(dev, d);
537	apic_set_irq(dev, apic, vector_num, trigger_mode);
538	}
539	return VINF_SUCCESS;
540	}
541	case APIC_DM_FIXED:
542	/* XXX: arbitration */
543	break;
544
545	case APIC_DM_SMI:
546	foreach_apic(dev, deliver_bitmask,
547	cpuSetInterrupt(dev, apic, PDMAPICIRQ_SMI));
548	return VINF_SUCCESS;
549
550	case APIC_DM_NMI:
551	foreach_apic(dev, deliver_bitmask,
552	cpuSetInterrupt(dev, apic, PDMAPICIRQ_NMI));
553	return VINF_SUCCESS;
554
555	case APIC_DM_INIT:
556	/* normal INIT IPI sent to processors */
557	#ifdef VBOX
558	#ifdef IN_RING3
559	foreach_apic(dev, deliver_bitmask,
560	apicSendInitIpi(dev, apic));
561	return VINF_SUCCESS;
562	#else
563	/* We shall send init IPI only in R3, R0 calls should be
564	rescheduled to R3 */
565	return VINF_IOM_HC_MMIO_READ_WRITE;
566	#endif /* IN_RING3 */
567
568	#else
569	for (apic_iter = first_local_apic; apic_iter != NULL;
570	apic_iter = apic_iter->next_apic) {
571	apic_init_ipi(apic_iter);
572	}
573	#endif
574
575	case APIC_DM_EXTINT:
576	/* handled in I/O APIC code */
577	break;
578
579	default:
580	return VINF_SUCCESS;
581	}
582
583	#ifdef VBOX
584	foreach_apic(dev, deliver_bitmask,
585	apic_set_irq (dev, apic, vector_num, trigger_mode));
586	return VINF_SUCCESS;
587	#else /* VBOX */
588	for (apic_iter = first_local_apic; apic_iter != NULL;
589	apic_iter = apic_iter->next_apic) {
590	if (deliver_bitmask & (1 << apic_iter->id))
591	apic_set_irq(apic_iter, vector_num, trigger_mode);
592	}
593	#endif /* VBOX */
594	}
595
596	#ifndef VBOX
597	void cpu_set_apic_base(CPUState *env, uint64_t val)
598	{
599	APICState *s = env->apic_state;
600	#ifdef DEBUG_APIC
601	Log(("cpu_set_apic_base: %016llx\n", val));
602	#endif
603
604	s->apicbase = (val & 0xfffff000) \|
605	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
606	/* if disabled, cannot be enabled again */
607	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
608	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
609	env->cpuid_features &= ~CPUID_APIC;
610	s->spurious_vec &= ~APIC_SV_ENABLE;
611	}
612	}
613	#else /* VBOX */
614	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
615	{
616	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
617	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
618	APICState s = getLapic(dev); /* @todo fix interface */
619	Log(("cpu_set_apic_base: %016RX64\n", val));
620
621	/** @todo: do we need to lock here ? */
622	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
623	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
624	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
625	PDMAPICVERSION oldMode = getApicMode(s);
626	s->apicbase =
627	(val & 0xfffff000) \| /* base */
628	(val & getApicEnableBits(dev)) \| /* mode */
629	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
630	PDMAPICVERSION newMode = getApicMode(s);
631
632	if (oldMode != newMode)
633	{
634	switch (newMode)
635	{
636	case PDMAPICVERSION_NONE:
637	{
638	s->spurious_vec &= ~APIC_SV_ENABLE;
639	/* Clear any pending APIC interrupt action flag. */
640	cpuClearInterrupt(dev, s);
641	/** @todo: why do we do that? */
642	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
643	break;
644	}
645	case PDMAPICVERSION_APIC:
646	/** @todo: map MMIO ranges, if needed */
647	break;
648	case PDMAPICVERSION_X2APIC:
649	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
650	break;
651	default:
652	break;
653	}
654	}
655	/* APIC_UNLOCK(dev); */
656	}
657	#endif /* VBOX */
658
659	#ifndef VBOX
660
661	uint64_t cpu_get_apic_base(CPUState *env)
662	{
663	APICState *s = env->apic_state;
664	#ifdef DEBUG_APIC
665	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
666	#endif
667	return s->apicbase;
668	}
669
670	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
671	{
672	APICState *s = env->apic_state;
673	s->tpr = (val & 0x0f) << 4;
674	apic_update_irq(s);
675	}
676
677	uint8_t cpu_get_apic_tpr(CPUX86State *env)
678	{
679	APICState *s = env->apic_state;
680	return s->tpr >> 4;
681	}
682
683	static int fls_bit(int value)
684	{
685	unsigned int ret = 0;
686
687	#ifdef HOST_I386
688	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
689	return ret;
690	#else
691	if (value > 0xffff)
692	value >>= 16, ret = 16;
693	if (value > 0xff)
694	value >>= 8, ret += 8;
695	if (value > 0xf)
696	value >>= 4, ret += 4;
697	if (value > 0x3)
698	value >>= 2, ret += 2;
699	return ret + (value >> 1);
700	#endif
701	}
702
703	static inline void set_bit(uint32_t *tab, int index)
704	{
705	int i, mask;
706	i = index >> 5;
707	mask = 1 << (index & 0x1f);
708	tab[i] \|= mask;
709	}
710
711	static inline void reset_bit(uint32_t *tab, int index)
712	{
713	int i, mask;
714	i = index >> 5;
715	mask = 1 << (index & 0x1f);
716	tab[i] &= ~mask;
717	}
718
719
720	#else /* VBOX */
721
722	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
723	{
724	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
725	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
726	APICState s = getLapic(dev); /* @todo fix interface */
727	LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
728	return s->apicbase;
729	}
730
731	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
732	{
733	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
734	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
735	APICState *s = getLapicById(dev, idCpu);
736	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, val));
737	apic_update_tpr(dev, s, val);
738	}
739
740	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
741	{
742	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
743	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
744	APICState *s = getLapicById(dev, idCpu);
745	Log2(("apicGetTPR: returns %#x\n", s->tpr));
746	return s->tpr;
747	}
748
749	/**
750	* x2APIC MSR write interface.
751	*
752	* @returns VBox status code.
753	*
754	* @param pDevIns The device instance.
755	* @param idCpu The ID of the virtual CPU and thereby APIC index.
756	* @param u32Reg Register to write (ecx).
757	* @param u64Value The value to write (eax:edx / rax).
758	*
759	*/
760	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
761	{
762	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
763	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
764	int rc = VINF_SUCCESS;
765
766	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
767	return VERR_EM_INTERPRETER;
768
769	APICState *pThis = getLapicById(dev, idCpu);
770
771	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
772	switch (index)
773	{
774	case 0x02:
775	pThis->id = (u64Value >> 24);
776	break;
777	case 0x03:
778	break;
779	case 0x08:
780	apic_update_tpr(dev, pThis, u64Value);
781	break;
782	case 0x09: case 0x0a:
783	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
784	break;
785	case 0x0b: /* EOI */
786	apic_eoi(dev, pThis);
787	break;
788	case 0x0d:
789	pThis->log_dest = u64Value >> 24;
790	break;
791	case 0x0e:
792	pThis->dest_mode = u64Value >> 28;
793	break;
794	case 0x0f:
795	pThis->spurious_vec = u64Value & 0x1ff;
796	apic_update_irq(dev, pThis);
797	break;
798	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
799	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
800	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
801	case 0x28:
802	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
803	break;
804
805	case 0x30:
806	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
807	pThis->icr[0] = (uint32_t)u64Value;
808	pThis->icr[1] = (uint32_t)(u64Value >> 32);
809	rc = apic_deliver(dev, pThis, (pThis->icr[1] >> 24) & 0xff, (pThis->icr[0] >> 11) & 1,
810	(pThis->icr[0] >> 8) & 7, (pThis->icr[0] & 0xff),
811	(pThis->icr[0] >> 14) & 1, (pThis->icr[0] >> 15) & 1);
812	break;
813	case 0x32 + APIC_LVT_TIMER:
814	AssertCompile(APIC_LVT_TIMER == 0);
815	apicTimerSetLvt(dev, pThis, u64Value);
816	break;
817
818	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
819	pThis->lvt[index - 0x32] = u64Value;
820	break;
821	case 0x38:
822	apicTimerSetInitialCount(dev, pThis, u64Value);
823	break;
824	case 0x39:
825	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
826	break;
827	case 0x3e:
828	{
829	int v;
830	pThis->divide_conf = u64Value & 0xb;
831	v = (pThis->divide_conf & 3) \| ((pThis->divide_conf >> 1) & 4);
832	pThis->count_shift = (v + 1) & 7;
833	break;
834	}
835	case 0x3f:
836	{
837	/* Self IPI, see x2APIC book 2.4.5 */
838	int vector = u64Value & 0xff;
839	rc = apic_bus_deliver(dev,
840	1 << getLapicById(dev, idCpu)->id /* Self */,
841	0 /* Delivery mode - fixed */,
842	vector,
843	0 /* Polarity - conform to the bus */,
844	0 /* Trigger mode - edge */);
845	break;
846	}
847	default:
848	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
849	pThis->esr \|= ESR_ILLEGAL_ADDRESS;
850	break;
851	}
852
853	return rc;
854	}
855
856	/**
857	* x2APIC MSR read interface.
858	*
859	* @returns VBox status code.
860	*
861	* @param pDevIns The device instance.
862	* @param idCpu The ID of the virtual CPU and thereby APIC index.
863	* @param u32Reg Register to write (ecx).
864	* @param pu64Value Where to return the value (eax:edx / rax).
865	*/
866	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
867	{
868	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
869	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
870
871	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
872	return VERR_EM_INTERPRETER;
873
874	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
875	APICState* apic = getLapicById(dev, idCpu);
876	uint64_t val = 0;
877
878	switch (index)
879	{
880	case 0x02: /* id */
881	val = apic->id << 24;
882	break;
883	case 0x03: /* version */
884	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
885	break;
886	case 0x08:
887	val = apic->tpr;
888	break;
889	case 0x09:
890	val = apic_get_arb_pri(apic);
891	break;
892	case 0x0a:
893	/* ppr */
894	val = apic_get_ppr(apic);
895	break;
896	case 0x0b:
897	val = 0;
898	break;
899	case 0x0d:
900	val = apic->log_dest << 24;
901	break;
902	case 0x0e:
903	/* Bottom 28 bits are always 1 */
904	val = (apic->dest_mode << 28) \| 0xfffffff;
905	break;
906	case 0x0f:
907	val = apic->spurious_vec;
908	break;
909	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
910	val = apic->isr[index & 7];
911	break;
912	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
913	val = apic->tmr[index & 7];
914	break;
915	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
916	val = apic->irr[index & 7];
917	break;
918	case 0x28:
919	val = apic->esr;
920	break;
921	case 0x30:
922	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
923	val = ((uint64_t)apic->icr[0x31] << 32) \| apic->icr[0x30];
924	break;
925	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
926	val = apic->lvt[index - 0x32];
927	break;
928	case 0x38:
929	val = apic->initial_count;
930	break;
931	case 0x39:
932	val = apic_get_current_count(dev, apic);
933	break;
934	case 0x3e:
935	val = apic->divide_conf;
936	break;
937	case 0x3f:
938	/* Self IPI register is write only */
939	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
940	break;
941	default:
942	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
943	apic->esr \|= ESR_ILLEGAL_ADDRESS;
944	val = 0;
945	break;
946	}
947	*pu64Value = val;
948	return VINF_SUCCESS;
949	}
950
951	/**
952	* More or less private interface between IOAPIC, only PDM is responsible
953	* for connecting the two devices.
954	*/
955	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
956	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
957	uint8_t u8TriggerMode)
958	{
959	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
960	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
961	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
962	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
963	return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
964	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
965	}
966
967	/**
968	* Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
969	* Normally used for 8259A PIC and NMI.
970	*/
971	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
972	{
973	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
974	APICState *s = getLapicById(dev, 0);
975
976	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
977	LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x\n", pDevIns, u8Pin));
978
979	/* If LAPIC is disabled, go straight to the CPU. */
980	if (!(s->spurious_vec & APIC_SV_ENABLE))
981	{
982	LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
983	if (u8Level)
984	cpuSetInterrupt(dev, s, PDMAPICIRQ_EXTINT);
985	else
986	cpuClearInterrupt(dev, s, PDMAPICIRQ_EXTINT);
987
988	return VINF_SUCCESS;
989	}
990
991	/* If LAPIC is enabled, interrupts are subject to LVT programming. */
992
993	/* There are only two local interrupt pins. */
994	AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
995
996	/* NB: We currently only deliver local interrupts to the first CPU. In theory they
997	* should be delivered to all CPUs and it is the guest's responsibility to ensure
998	* no more than one CPU has the interrupt unmasked.
999	*/
1000	uint32_t u32Lvec;
1001
1002	u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin]; /* Fetch corresponding LVT entry. */
1003	/* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
1004	if (!(u32Lvec & APIC_LVT_MASKED))
1005	{ uint8_t u8Delivery;
1006	PDMAPICIRQ enmType;
1007
1008	u8Delivery = (u32Lvec >> 8) & 7;
1009	switch (u8Delivery)
1010	{
1011	case APIC_DM_EXTINT:
1012	Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
1013	enmType = PDMAPICIRQ_EXTINT;
1014	/* ExtINT can be both set and cleared, NMI/SMI/INIT can only be set. */
1015	LogFlow(("apicLocalInterrupt: %s ExtINT interrupt\n", u8Level ? "setting" : "clearing"));
1016	if (u8Level)
1017	cpuSetInterrupt(dev, s, enmType);
1018	else
1019	cpuClearInterrupt(dev, s, enmType);
1020	return VINF_SUCCESS;
1021	case APIC_DM_NMI:
1022	Assert(u8Pin == 1); /* NMI should be wired to LINT1. */
1023	enmType = PDMAPICIRQ_NMI;
1024	break;
1025	case APIC_DM_SMI:
1026	enmType = PDMAPICIRQ_SMI;
1027	break;
1028	case APIC_DM_FIXED:
1029	/** @todo implement APIC_DM_FIXED! */
1030	case APIC_DM_INIT:
1031	/** @todo implement APIC_DM_INIT? */
1032	default:
1033	{
1034	static unsigned s_c = 0;
1035	if (s_c++ < 100)
1036	AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d", u8Delivery, u8Pin, u8Level));
1037	return VERR_INTERNAL_ERROR_4;
1038	}
1039	}
1040	LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
1041	cpuSetInterrupt(dev, s, enmType);
1042	}
1043	return VINF_SUCCESS;
1044	}
1045
1046	#endif /* VBOX */
1047
1048	/* return -1 if no bit is set */
1049	static int get_highest_priority_int(uint32_t *tab)
1050	{
1051	int i;
1052	for(i = 7; i >= 0; i--) {
1053	if (tab[i] != 0) {
1054	return i * 32 + fls_bit(tab[i]);
1055	}
1056	}
1057	return -1;
1058	}
1059
1060	static int apic_get_ppr(APICState *s)
1061	{
1062	int tpr, isrv, ppr;
1063
1064	tpr = (s->tpr >> 4);
1065	isrv = get_highest_priority_int(s->isr);
1066	if (isrv < 0)
1067	isrv = 0;
1068	isrv >>= 4;
1069	if (tpr >= isrv)
1070	ppr = s->tpr;
1071	else
1072	ppr = isrv << 4;
1073	return ppr;
1074	}
1075
1076	static int apic_get_ppr_zero_tpr(APICState *s)
1077	{
1078	int isrv;
1079
1080	isrv = get_highest_priority_int(s->isr);
1081	if (isrv < 0)
1082	isrv = 0;
1083	return isrv;
1084	}
1085
1086	static int apic_get_arb_pri(APICState *s)
1087	{
1088	/* XXX: arbitration */
1089	return 0;
1090	}
1091
1092	/* signal the CPU if an irq is pending */
1093	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
1094	{
1095	int irrv, ppr;
1096	if (!(s->spurious_vec & APIC_SV_ENABLE))
1097	#ifdef VBOX
1098	{
1099	/* Clear any pending APIC interrupt action flag. */
1100	cpuClearInterrupt(dev, s);
1101	return false;
1102	}
1103	#else
1104	return false;
1105	#endif /* VBOX */
1106	irrv = get_highest_priority_int(s->irr);
1107	if (irrv < 0)
1108	return false;
1109	ppr = apic_get_ppr(s);
1110	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1111	return false;
1112	#ifndef VBOX
1113	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
1114	#else
1115	cpuSetInterrupt(dev, s);
1116	return true;
1117	#endif
1118	}
1119
1120	#ifdef VBOX
1121
1122	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
1123	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
1124	{
1125	int irrv, ppr;
1126	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1127	if (!dev)
1128	return false;
1129
1130	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
1131
1132	APICState s = getLapic(dev); /* @todo fix interface */
1133
1134	/*
1135	* All our callbacks now come from single IOAPIC, thus locking
1136	* seems to be excessive now (@todo: check)
1137	*/
1138	irrv = get_highest_priority_int(s->irr);
1139	if (irrv < 0)
1140	return false;
1141
1142	ppr = apic_get_ppr_zero_tpr(s);
1143
1144	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1145	return false;
1146
1147	return true;
1148	}
1149
1150	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
1151	{
1152	bool fIrqIsActive = false;
1153	bool fIrqWasActive = false;
1154
1155	fIrqWasActive = apic_update_irq(dev, s);
1156	s->tpr = val;
1157	fIrqIsActive = apic_update_irq(dev, s);
1158
1159	/* If an interrupt is pending and now masked, then clear the FF flag. */
1160	if (fIrqWasActive && !fIrqIsActive)
1161	{
1162	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1163	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
1164	cpuClearInterrupt(dev, s);
1165	}
1166	}
1167	#endif
1168
1169	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
1170	{
1171	LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode));
1172	set_bit(s->irr, vector_num);
1173	if (trigger_mode)
1174	set_bit(s->tmr, vector_num);
1175	else
1176	reset_bit(s->tmr, vector_num);
1177	apic_update_irq(dev, s);
1178	}
1179
1180	static void apic_eoi(APICDeviceInfo dev, APICState s)
1181	{
1182	int isrv;
1183	isrv = get_highest_priority_int(s->isr);
1184	if (isrv < 0)
1185	return;
1186	reset_bit(s->isr, isrv);
1187	LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1188	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1189	set the remote IRR bit for level triggered interrupts. */
1190	apic_update_irq(dev, s);
1191	}
1192
1193	#ifndef VBOX
1194	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1195	#else /* VBOX */
1196	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1197	#endif /* VBOX */
1198	{
1199	uint32_t mask = 0;
1200
1201	if (dest_mode == 0)
1202	{
1203	if (dest == 0xff)
1204	mask = 0xff;
1205	else
1206	mask = 1 << dest;
1207	}
1208	else
1209	{
1210	APICState *apic = dev->CTX_SUFF(paLapics);
1211	uint32_t i;
1212
1213	/* XXX: cluster mode */
1214	for(i = 0; i < dev->cCpus; i++)
1215	{
1216	if (apic->dest_mode == 0xf)
1217	{
1218	if (dest & apic->log_dest)
1219	mask \|= (1 << apic->id);
1220	}
1221	else if (apic->dest_mode == 0x0)
1222	{
1223	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1224	&&
1225	(dest & apic->log_dest & 0x0f))
1226	{
1227	mask \|= (1 << i);
1228	}
1229	}
1230	apic++;
1231	}
1232	}
1233
1234	return mask;
1235	}
1236
1237	#ifdef IN_RING3
1238	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s)
1239	{
1240	int i;
1241
1242	for(i = 0; i < APIC_LVT_NB; i++)
1243	s->lvt[i] = 1 << 16; /* mask LVT */
1244	s->tpr = 0;
1245	s->spurious_vec = 0xff;
1246	s->log_dest = 0;
1247	s->dest_mode = 0xff;
1248	memset(s->isr, 0, sizeof(s->isr));
1249	memset(s->tmr, 0, sizeof(s->tmr));
1250	memset(s->irr, 0, sizeof(s->irr));
1251	s->esr = 0;
1252	memset(s->icr, 0, sizeof(s->icr));
1253	s->divide_conf = 0;
1254	s->count_shift = 0;
1255	s->initial_count = 0;
1256	s->initial_count_load_time = 0;
1257	s->next_time = 0;
1258	}
1259
1260
1261	#ifdef VBOX
1262	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s)
1263	{
1264	apic_init_ipi(dev, s);
1265	cpuSendInitIpi(dev, s);
1266	}
1267	#endif
1268
1269	/* send a SIPI message to the CPU to start it */
1270	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1271	{
1272	#ifndef VBOX
1273	CPUState *env = s->cpu_env;
1274	if (!env->halted)
1275	return;
1276	env->eip = 0;
1277	cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1278	0xffff, 0);
1279	env->halted = 0;
1280	#else
1281	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1282	cpuSendSipi(dev, s, vector_num);
1283	#endif
1284	}
1285	#endif /* IN_RING3 */
1286
1287	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1288	uint8_t dest, uint8_t dest_mode,
1289	uint8_t delivery_mode, uint8_t vector_num,
1290	uint8_t polarity, uint8_t trigger_mode)
1291	{
1292	uint32_t deliver_bitmask = 0;
1293	int dest_shorthand = (s->icr[0] >> 18) & 3;
1294	#ifndef VBOX
1295	APICState *apic_iter;
1296	#endif /* !VBOX */
1297
1298	LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1299
1300	switch (dest_shorthand) {
1301	case 0:
1302	#ifndef VBOX
1303	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1304	#else /* VBOX */
1305	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1306	#endif /* !VBOX */
1307	break;
1308	case 1:
1309	deliver_bitmask = (1 << s->id);
1310	break;
1311	case 2:
1312	deliver_bitmask = 0xffffffff;
1313	break;
1314	case 3:
1315	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1316	break;
1317	}
1318
1319	switch (delivery_mode) {
1320	case APIC_DM_INIT:
1321	{
1322	int trig_mode = (s->icr[0] >> 15) & 1;
1323	int level = (s->icr[0] >> 14) & 1;
1324	if (level == 0 && trig_mode == 1) {
1325	foreach_apic(dev, deliver_bitmask,
1326	apic->arb_id = apic->id);
1327	#ifndef VBOX
1328	return;
1329	#else
1330	Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1331	return VINF_SUCCESS;
1332	#endif
1333	}
1334	}
1335	break;
1336
1337	case APIC_DM_SIPI:
1338	#ifndef VBOX
1339	for (apic_iter = first_local_apic; apic_iter != NULL;
1340	apic_iter = apic_iter->next_apic) {
1341	if (deliver_bitmask & (1 << apic_iter->id)) {
1342	/* XXX: SMP support */
1343	/* apic_startup(apic_iter); */
1344	}
1345	}
1346	return;
1347	#else
1348	# ifdef IN_RING3
1349	foreach_apic(dev, deliver_bitmask,
1350	apic_startup(dev, apic, vector_num));
1351	return VINF_SUCCESS;
1352	# else
1353	/* We shall send SIPI only in R3, R0 calls should be
1354	rescheduled to R3 */
1355	return VINF_IOM_HC_MMIO_WRITE;
1356	# endif
1357	#endif /* !VBOX */
1358	}
1359
1360	#ifndef VBOX
1361	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1362	trigger_mode);
1363	#else /* VBOX */
1364	return apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num,
1365	polarity, trigger_mode);
1366	#endif /* VBOX */
1367	}
1368
1369
1370	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1371	{
1372	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1373	/* if the APIC is not installed or enabled, we let the 8259 handle the
1374	IRQs */
1375	if (!dev)
1376	{
1377	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1378	return -1;
1379	}
1380
1381	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
1382
1383	APICState s = getLapic(dev); /* @todo fix interface */
1384	int intno;
1385
1386	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1387	Log(("CPU%d: apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n", s->phys_id));
1388	return -1;
1389	}
1390
1391	/* XXX: spurious IRQ handling */
1392	intno = get_highest_priority_int(s->irr);
1393	if (intno < 0) {
1394	Log(("CPU%d: apic_get_interrupt: returns -1 (irr)\n", s->phys_id));
1395	return -1;
1396	}
1397	if (s->tpr && (uint32_t)intno <= s->tpr) {
1398	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1399	return s->spurious_vec & 0xff;
1400	}
1401	reset_bit(s->irr, intno);
1402	set_bit(s->isr, intno);
1403	apic_update_irq(dev, s);
1404	LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno));
1405	return intno;
1406	}
1407
1408	static uint32_t apic_get_current_count(APICDeviceInfo dev, APICState s)
1409	{
1410	int64_t d;
1411	uint32_t val;
1412	#ifndef VBOX
1413	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1414	s->count_shift;
1415	#else /* VBOX */
1416	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1417	s->count_shift;
1418	#endif /* VBOX */
1419	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1420	/* periodic */
1421	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1422	} else {
1423	if (d >= s->initial_count)
1424	val = 0;
1425	else
1426	val = s->initial_count - d;
1427	}
1428	return val;
1429	}
1430
1431	#ifndef VBOX /* we've replaced all the code working the APIC timer. */
1432
1433	static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1434	{
1435	int64_t next_time, d;
1436
1437	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1438	d = (current_time - s->initial_count_load_time) >>
1439	s->count_shift;
1440	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1441	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1442	} else {
1443	if (d >= s->initial_count)
1444	goto no_timer;
1445	d = (uint64_t)s->initial_count + 1;
1446	}
1447	next_time = s->initial_count_load_time + (d << s->count_shift);
1448	# ifndef VBOX
1449	qemu_mod_timer(s->timer, next_time);
1450	# else
1451	TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1452	s->fTimerArmed = true;
1453	# endif
1454	s->next_time = next_time;
1455	} else {
1456	no_timer:
1457	# ifndef VBOX
1458	qemu_del_timer(s->timer);
1459	# else
1460	TMTimerStop(s->CTX_SUFF(pTimer));
1461	s->fTimerArmed = false;
1462	# endif
1463	}
1464	}
1465
1466	static void apic_timer(void *opaque)
1467	{
1468	APICState *s = opaque;
1469
1470	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1471	LogFlow(("apic_timer: trigger irq\n"));
1472	apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1473	}
1474	apic_timer_update(dev, s, s->next_time);
1475	}
1476
1477	#else /* VBOX */
1478
1479	/**
1480	* Implementation of the 0380h access: Timer reset + new initial count.
1481	*
1482	* @param dev The device state.
1483	* @param pThis The APIC sub-device state.
1484	* @param u32NewInitialCount The new initial count for the timer.
1485	*/
1486	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState pThis, uint32_t u32NewInitialCount)
1487	{
1488	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCount);
1489	pThis->initial_count = u32NewInitialCount;
1490
1491	/*
1492	* Don't (re-)arm the timer if the it's masked or if it's
1493	* a zero length one-shot timer.
1494	*/
1495	/** @todo check the correct behavior of setting a 0 initial_count for a one-shot
1496	* timer. This is just copying the behavior of the original code. */
1497	if ( !(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)
1498	&& ( (pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1499	\|\| u32NewInitialCount != 0))
1500	{
1501	/*
1502	* Calculate the relative next time and perform a combined timer get/set
1503	* operation. This avoids racing the clock between get and set.
1504	*/
1505	uint64_t cTicksNext = u32NewInitialCount;
1506	cTicksNext += 1;
1507	cTicksNext <<= pThis->count_shift;
1508	TMTimerSetRelative(pThis->CTX_SUFF(pTimer), cTicksNext, &pThis->initial_count_load_time);
1509	pThis->next_time = pThis->initial_count_load_time + cTicksNext;
1510	pThis->fTimerArmed = true;
1511	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountArm);
1512	}
1513	else
1514	{
1515	/* Stop it if necessary and record the load time for unmasking. */
1516	if (pThis->fTimerArmed)
1517	{
1518	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountDisarm);
1519	TMTimerStop(pThis->CTX_SUFF(pTimer));
1520	pThis->fTimerArmed = false;
1521	}
1522	pThis->initial_count_load_time = TMTimerGet(pThis->CTX_SUFF(pTimer));
1523	}
1524	}
1525
1526	/**
1527	* Implementation of the 0320h access: change the LVT flags.
1528	*
1529	* @param dev The device state.
1530	* @param pThis The APIC sub-device state to operate on.
1531	* @param fNew The new flags.
1532	*/
1533	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew)
1534	{
1535	STAM_COUNTER_INC(&pThis->StatTimerSetLvt);
1536
1537	/*
1538	* Make the flag change, saving the old ones so we can avoid
1539	* unnecessary work.
1540	*/
1541	uint32_t const fOld = pThis->lvt[APIC_LVT_TIMER];
1542	pThis->lvt[APIC_LVT_TIMER] = fNew;
1543
1544	/* Only the masked and peridic bits are relevant (see apic_timer_update). */
1545	if ( (fOld & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC))
1546	!= (fNew & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC)))
1547	{
1548	/*
1549	* If changed to one-shot from periodic, stop the timer if we're not
1550	* in the first period.
1551	*/
1552	/** @todo check how clearing the periodic flag really should behave when not
1553	* in period 1. The current code just mirrors the behavior of the
1554	* original implementation. */
1555	if ( (fOld & APIC_LVT_TIMER_PERIODIC)
1556	&& !(fNew & APIC_LVT_TIMER_PERIODIC))
1557	{
1558	STAM_COUNTER_INC(&pThis->StatTimerSetLvtClearPeriodic);
1559	uint64_t cTicks = (pThis->next_time - pThis->initial_count_load_time) >> pThis->count_shift;
1560	if (cTicks >= pThis->initial_count)
1561	{
1562	/* not first period, stop it. */
1563	TMTimerStop(pThis->CTX_SUFF(pTimer));
1564	pThis->fTimerArmed = false;
1565	}
1566	/* else: first period, let it fire normally. */
1567	}
1568
1569	/*
1570	* We postpone stopping the timer when it's masked, this way we can
1571	* avoid some timer work when the guest temporarily masks the timer.
1572	* (apicTimerCallback will stop it if still masked.)
1573	*/
1574	if (fNew & APIC_LVT_MASKED)
1575	STAM_COUNTER_INC(&pThis->StatTimerSetLvtPostponed);
1576	else if (pThis->fTimerArmed)
1577	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmed);
1578	/*
1579	* If unmasked and not armed, we have to rearm the timer so it will
1580	* fire at the end of the current period.
1581	* This is code is currently RACING the virtual sync clock!
1582	*/
1583	else if (fOld & APIC_LVT_MASKED)
1584	{
1585	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArm);
1586	for (unsigned cTries = 0; ; cTries++)
1587	{
1588	uint64_t NextTS;
1589	uint64_t cTicks = (TMTimerGet(pThis->CTX_SUFF(pTimer)) - pThis->initial_count_load_time) >> pThis->count_shift;
1590	if (fNew & APIC_LVT_TIMER_PERIODIC)
1591	NextTS = ((cTicks / ((uint64_t)pThis->initial_count + 1)) + 1) * ((uint64_t)pThis->initial_count + 1);
1592	else
1593	{
1594	if (cTicks >= pThis->initial_count)
1595	break;
1596	NextTS = (uint64_t)pThis->initial_count + 1;
1597	}
1598	NextTS <<= pThis->count_shift;
1599	NextTS += pThis->initial_count_load_time;
1600
1601	/* Try avoid the assertion in TM.cpp... this isn't perfect! */
1602	if ( NextTS > TMTimerGet(pThis->CTX_SUFF(pTimer))
1603	\|\| cTries > 10)
1604	{
1605	TMTimerSet(pThis->CTX_SUFF(pTimer), NextTS);
1606	pThis->next_time = NextTS;
1607	pThis->fTimerArmed = true;
1608	break;
1609	}
1610	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmRetries);
1611	}
1612	}
1613	}
1614	else
1615	STAM_COUNTER_INC(&pThis->StatTimerSetLvtNoRelevantChange);
1616	}
1617
1618	# ifdef IN_RING3
1619	/**
1620	* Timer callback function.
1621	*
1622	* @param pDevIns The device state.
1623	* @param pTimer The timer handle.
1624	* @param pvUser User argument pointing to the APIC instance.
1625	*/
1626	static DECLCALLBACK(void) apicTimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1627	{
1628	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1629	APICState pThis = (APICState )pvUser;
1630	Assert(pThis->pTimerR3 == pTimer);
1631	Assert(pThis->fTimerArmed);
1632
1633	if (!(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1634	LogFlow(("apic_timer: trigger irq\n"));
1635	apic_set_irq(dev, pThis, pThis->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1636
1637	if (pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1638	/* new interval. */
1639	pThis->next_time += (((uint64_t)pThis->initial_count + 1) << pThis->count_shift);
1640	TMTimerSet(pThis->CTX_SUFF(pTimer), pThis->next_time);
1641	pThis->fTimerArmed = true;
1642	} else {
1643	/* single shot. */
1644	pThis->fTimerArmed = false;
1645	}
1646	} else {
1647	/* masked, do not rearm. */
1648	pThis->fTimerArmed = false;
1649	}
1650	}
1651	# endif /* IN_RING3 */
1652
1653	#endif /* VBOX */
1654
1655	#ifndef VBOX
1656	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1657	{
1658	return 0;
1659	}
1660	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1661	{
1662	return 0;
1663	}
1664
1665	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1666	{
1667	}
1668
1669	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1670	{
1671	}
1672	#endif /* !VBOX */
1673
1674
1675	#ifndef VBOX
1676	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1677	{
1678	CPUState *env;
1679	APICState *s;
1680	#else /* VBOX */
1681	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1682	{
1683	#endif /* VBOX */
1684	uint32_t val;
1685	int index;
1686
1687	#ifndef VBOX
1688	env = cpu_single_env;
1689	if (!env)
1690	return 0;
1691	s = env->apic_state;
1692	#endif /* !VBOX */
1693
1694	index = (addr >> 4) & 0xff;
1695	switch(index) {
1696	case 0x02: /* id */
1697	val = s->id << 24;
1698	break;
1699	case 0x03: /* version */
1700	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1701	break;
1702	case 0x08:
1703	val = s->tpr;
1704	break;
1705	case 0x09:
1706	val = apic_get_arb_pri(s);
1707	break;
1708	case 0x0a:
1709	/* ppr */
1710	val = apic_get_ppr(s);
1711	break;
1712	case 0x0b:
1713	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1714	val = 0;
1715	break;
1716	case 0x0d:
1717	val = s->log_dest << 24;
1718	break;
1719	case 0x0e:
1720	#ifdef VBOX
1721	/* Bottom 28 bits are always 1 */
1722	val = (s->dest_mode << 28) \| 0xfffffff;
1723	#else
1724	val = s->dest_mode << 28;
1725	#endif
1726	break;
1727	case 0x0f:
1728	val = s->spurious_vec;
1729	break;
1730	#ifndef VBOX
1731	case 0x10 ... 0x17:
1732	#else /* VBOX */
1733	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1734	#endif /* VBOX */
1735	val = s->isr[index & 7];
1736	break;
1737	#ifndef VBOX
1738	case 0x18 ... 0x1f:
1739	#else /* VBOX */
1740	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1741	#endif /* VBOX */
1742	val = s->tmr[index & 7];
1743	break;
1744	#ifndef VBOX
1745	case 0x20 ... 0x27:
1746	#else /* VBOX */
1747	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1748	#endif /* VBOX */
1749	val = s->irr[index & 7];
1750	break;
1751	case 0x28:
1752	val = s->esr;
1753	break;
1754	case 0x30:
1755	case 0x31:
1756	val = s->icr[index & 1];
1757	break;
1758	#ifndef VBOX
1759	case 0x32 ... 0x37:
1760	#else /* VBOX */
1761	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1762	#endif /* VBOX */
1763	val = s->lvt[index - 0x32];
1764	break;
1765	case 0x38:
1766	val = s->initial_count;
1767	break;
1768	case 0x39:
1769	val = apic_get_current_count(dev, s);
1770	break;
1771	case 0x3e:
1772	val = s->divide_conf;
1773	break;
1774	default:
1775	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1776	s->esr \|= ESR_ILLEGAL_ADDRESS;
1777	val = 0;
1778	break;
1779	}
1780	#ifdef DEBUG_APIC
1781	Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1782	#endif
1783	return val;
1784	}
1785
1786	#ifndef VBOX
1787	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1788	{
1789	CPUState *env;
1790	APICState *s;
1791	#else /* VBOX */
1792	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1793	{
1794	int rc = VINF_SUCCESS;
1795	#endif /* VBOX */
1796	int index;
1797
1798	#ifndef VBOX
1799	env = cpu_single_env;
1800	if (!env)
1801	return;
1802	s = env->apic_state;
1803	#endif /* !VBOX */
1804
1805	#ifdef DEBUG_APIC
1806	Log(("CPU%d: APIC write: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1807	#endif
1808
1809	index = (addr >> 4) & 0xff;
1810	switch(index) {
1811	case 0x02:
1812	s->id = (val >> 24);
1813	break;
1814	case 0x03:
1815	Log(("apic_mem_writel: write to version register; ignored\n"));
1816	break;
1817	case 0x08:
1818	#ifdef VBOX
1819	apic_update_tpr(dev, s, val);
1820	#else
1821	s->tpr = val;
1822	apic_update_irq(s);
1823	#endif
1824	break;
1825	case 0x09:
1826	case 0x0a:
1827	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1828	break;
1829	case 0x0b: /* EOI */
1830	apic_eoi(dev, s);
1831	break;
1832	case 0x0d:
1833	s->log_dest = val >> 24;
1834	break;
1835	case 0x0e:
1836	s->dest_mode = val >> 28;
1837	break;
1838	case 0x0f:
1839	s->spurious_vec = val & 0x1ff;
1840	apic_update_irq(dev, s);
1841	break;
1842	#ifndef VBOX
1843	case 0x10 ... 0x17:
1844	case 0x18 ... 0x1f:
1845	case 0x20 ... 0x27:
1846	case 0x28:
1847	#else
1848	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1849	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1850	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1851	case 0x28:
1852	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1853	#endif
1854	break;
1855
1856	case 0x30:
1857	s->icr[0] = val;
1858	rc = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1859	(s->icr[0] >> 11) & 1,
1860	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1861	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1862	break;
1863	case 0x31:
1864	s->icr[1] = val;
1865	break;
1866	#ifndef VBOX
1867	case 0x32 ... 0x37:
1868	#else /* VBOX */
1869	case 0x32 + APIC_LVT_TIMER:
1870	AssertCompile(APIC_LVT_TIMER == 0);
1871	apicTimerSetLvt(dev, s, val);
1872	break;
1873	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1874	#endif /* VBOX */
1875	{
1876	int n = index - 0x32;
1877	s->lvt[n] = val;
1878	#ifndef VBOX
1879	if (n == APIC_LVT_TIMER)
1880	apic_timer_update(s, qemu_get_clock(vm_clock));
1881	#endif /* !VBOX*/
1882	}
1883	break;
1884	case 0x38:
1885	#ifndef VBOX
1886	s->initial_count = val;
1887	s->initial_count_load_time = qemu_get_clock(vm_clock);
1888	apic_timer_update(dev, s, s->initial_count_load_time);
1889	#else /* VBOX */
1890	apicTimerSetInitialCount(dev, s, val);
1891	#endif /* VBOX*/
1892	break;
1893	case 0x39:
1894	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1895	break;
1896	case 0x3e:
1897	{
1898	int v;
1899	s->divide_conf = val & 0xb;
1900	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1901	s->count_shift = (v + 1) & 7;
1902	}
1903	break;
1904	default:
1905	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1906	s->esr \|= ESR_ILLEGAL_ADDRESS;
1907	break;
1908	}
1909	#ifdef VBOX
1910	return rc;
1911	#endif
1912	}
1913
1914	#ifdef IN_RING3
1915
1916	static void apic_save(QEMUFile f, void opaque)
1917	{
1918	APICState s = (APICState)opaque;
1919	int i;
1920
1921	qemu_put_be32s(f, &s->apicbase);
1922	#ifdef VBOX
1923	qemu_put_be32s(f, &s->id);
1924	qemu_put_be32s(f, &s->phys_id);
1925	qemu_put_be32s(f, &s->arb_id);
1926	qemu_put_be32s(f, &s->tpr);
1927	#else
1928	qemu_put_8s(f, &s->id);
1929	qemu_put_8s(f, &s->arb_id);
1930	qemu_put_8s(f, &s->tpr);
1931	#endif
1932	qemu_put_be32s(f, &s->spurious_vec);
1933	qemu_put_8s(f, &s->log_dest);
1934	qemu_put_8s(f, &s->dest_mode);
1935	for (i = 0; i < 8; i++) {
1936	qemu_put_be32s(f, &s->isr[i]);
1937	qemu_put_be32s(f, &s->tmr[i]);
1938	qemu_put_be32s(f, &s->irr[i]);
1939	}
1940	for (i = 0; i < APIC_LVT_NB; i++) {
1941	qemu_put_be32s(f, &s->lvt[i]);
1942	}
1943	qemu_put_be32s(f, &s->esr);
1944	qemu_put_be32s(f, &s->icr[0]);
1945	qemu_put_be32s(f, &s->icr[1]);
1946	qemu_put_be32s(f, &s->divide_conf);
1947	qemu_put_be32s(f, &s->count_shift);
1948	qemu_put_be32s(f, &s->initial_count);
1949	qemu_put_be64s(f, &s->initial_count_load_time);
1950	qemu_put_be64s(f, &s->next_time);
1951
1952	#ifdef VBOX
1953	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1954	#endif
1955	}
1956
1957	static int apic_load(QEMUFile f, void opaque, int version_id)
1958	{
1959	APICState s = (APICState)opaque;
1960	int i;
1961
1962	#ifdef VBOX
1963	/* XXX: what if the base changes? (registered memory regions) */
1964	qemu_get_be32s(f, &s->apicbase);
1965
1966	switch (version_id)
1967	{
1968	case APIC_SAVED_STATE_VERSION_ANCIENT:
1969	{
1970	uint8_t val = 0;
1971	qemu_get_8s(f, &val);
1972	s->id = val;
1973	/* UP only in old saved states */
1974	s->phys_id = 0;
1975	qemu_get_8s(f, &val);
1976	s->arb_id = val;
1977	break;
1978	}
1979	case APIC_SAVED_STATE_VERSION:
1980	case APIC_SAVED_STATE_VERSION_VBOX_30:
1981	qemu_get_be32s(f, &s->id);
1982	qemu_get_be32s(f, &s->phys_id);
1983	qemu_get_be32s(f, &s->arb_id);
1984	break;
1985	default:
1986	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1987	}
1988	qemu_get_be32s(f, &s->tpr);
1989	#else
1990	if (version_id != 1)
1991	return -EINVAL;
1992
1993	/* XXX: what if the base changes? (registered memory regions) */
1994	qemu_get_be32s(f, &s->apicbase);
1995	qemu_get_8s(f, &s->id);
1996	qemu_get_8s(f, &s->arb_id);
1997	qemu_get_8s(f, &s->tpr);
1998	#endif
1999	qemu_get_be32s(f, &s->spurious_vec);
2000	qemu_get_8s(f, &s->log_dest);
2001	qemu_get_8s(f, &s->dest_mode);
2002	for (i = 0; i < 8; i++) {
2003	qemu_get_be32s(f, &s->isr[i]);
2004	qemu_get_be32s(f, &s->tmr[i]);
2005	qemu_get_be32s(f, &s->irr[i]);
2006	}
2007	for (i = 0; i < APIC_LVT_NB; i++) {
2008	qemu_get_be32s(f, &s->lvt[i]);
2009	}
2010	qemu_get_be32s(f, &s->esr);
2011	qemu_get_be32s(f, &s->icr[0]);
2012	qemu_get_be32s(f, &s->icr[1]);
2013	qemu_get_be32s(f, &s->divide_conf);
2014	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
2015	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
2016	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
2017	qemu_get_be64s(f, (uint64_t *)&s->next_time);
2018
2019	#ifdef VBOX
2020	int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
2021	s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
2022	#endif
2023
2024	return VINF_SUCCESS; /** @todo darn mess! */
2025	}
2026	#ifndef VBOX
2027	static void apic_reset(void *opaque)
2028	{
2029	APICState s = (APICState)opaque;
2030	apic_init_ipi(s);
2031	}
2032	#endif
2033
2034	#endif /* IN_RING3 */
2035
2036	#ifndef VBOX
2037	static CPUReadMemoryFunc *apic_mem_read[3] = {
2038	apic_mem_readb,
2039	apic_mem_readw,
2040	apic_mem_readl,
2041	};
2042
2043	static CPUWriteMemoryFunc *apic_mem_write[3] = {
2044	apic_mem_writeb,
2045	apic_mem_writew,
2046	apic_mem_writel,
2047	};
2048
2049	int apic_init(CPUState *env)
2050	{
2051	APICState *s;
2052
2053	s = qemu_mallocz(sizeof(APICState));
2054	if (!s)
2055	return -1;
2056	env->apic_state = s;
2057	apic_init_ipi(s);
2058	s->id = last_apic_id++;
2059	s->cpu_env = env;
2060	s->apicbase = 0xfee00000 \|
2061	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
2062
2063	/* XXX: mapping more APICs at the same memory location */
2064	if (apic_io_memory == 0) {
2065	/* NOTE: the APIC is directly connected to the CPU - it is not
2066	on the global memory bus. */
2067	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
2068	apic_mem_write, NULL);
2069	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
2070	apic_io_memory);
2071	}
2072	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
2073
2074	register_savevm("apic", 0, 1, apic_save, apic_load, s);
2075	qemu_register_reset(apic_reset, s);
2076
2077	s->next_apic = first_local_apic;
2078	first_local_apic = s;
2079
2080	return 0;
2081	}
2082	#endif /* !VBOX */
2083
2084	static void ioapic_service(IOAPICState *s)
2085	{
2086	uint8_t i;
2087	uint8_t trig_mode;
2088	uint8_t vector;
2089	uint8_t delivery_mode;
2090	uint32_t mask;
2091	uint64_t entry;
2092	uint8_t dest;
2093	uint8_t dest_mode;
2094	uint8_t polarity;
2095
2096	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2097	mask = 1 << i;
2098	if (s->irr & mask) {
2099	entry = s->ioredtbl[i];
2100	if (!(entry & APIC_LVT_MASKED)) {
2101	trig_mode = ((entry >> 15) & 1);
2102	dest = entry >> 56;
2103	dest_mode = (entry >> 11) & 1;
2104	delivery_mode = (entry >> 8) & 7;
2105	polarity = (entry >> 13) & 1;
2106	if (trig_mode == APIC_TRIGGER_EDGE)
2107	s->irr &= ~mask;
2108	if (delivery_mode == APIC_DM_EXTINT)
2109	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
2110	vector = pic_read_irq(isa_pic);
2111	#else /* VBOX */
2112	{
2113	AssertMsgFailed(("Delivery mode ExtINT"));
2114	vector = 0xff; /* incorrect but shuts up gcc. */
2115	}
2116	#endif /* VBOX */
2117	else
2118	vector = entry & 0xff;
2119
2120	#ifndef VBOX
2121	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
2122	delivery_mode, vector, polarity, trig_mode);
2123	#else /* VBOX */
2124	int rc = s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
2125	dest,
2126	dest_mode,
2127	delivery_mode,
2128	vector,
2129	polarity,
2130	trig_mode);
2131	/* We must be sure that attempts to reschedule in R3
2132	never get here */
2133	Assert(rc == VINF_SUCCESS);
2134	#endif /* VBOX */
2135	}
2136	}
2137	}
2138	}
2139
2140	#ifdef VBOX
2141	static
2142	#endif
2143	void ioapic_set_irq(void *opaque, int vector, int level)
2144	{
2145	IOAPICState s = (IOAPICState)opaque;
2146
2147	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
2148	uint32_t mask = 1 << vector;
2149	uint64_t entry = s->ioredtbl[vector];
2150
2151	if ((entry >> 15) & 1) {
2152	/* level triggered */
2153	if (level) {
2154	s->irr \|= mask;
2155	ioapic_service(s);
2156	#ifdef VBOX
2157	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
2158	s->irr &= ~mask;
2159	}
2160	#endif
2161	} else {
2162	s->irr &= ~mask;
2163	}
2164	} else {
2165	/* edge triggered */
2166	if (level) {
2167	s->irr \|= mask;
2168	ioapic_service(s);
2169	}
2170	}
2171	}
2172	}
2173
2174	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
2175	{
2176	IOAPICState s = (IOAPICState)opaque;
2177	int index;
2178	uint32_t val = 0;
2179
2180	addr &= 0xff;
2181	if (addr == 0x00) {
2182	val = s->ioregsel;
2183	} else if (addr == 0x10) {
2184	switch (s->ioregsel) {
2185	case 0x00:
2186	val = s->id << 24;
2187	break;
2188	case 0x01:
2189	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
2190	break;
2191	case 0x02:
2192	val = 0;
2193	break;
2194	default:
2195	index = (s->ioregsel - 0x10) >> 1;
2196	if (index >= 0 && index < IOAPIC_NUM_PINS) {
2197	if (s->ioregsel & 1)
2198	val = s->ioredtbl[index] >> 32;
2199	else
2200	val = s->ioredtbl[index] & 0xffffffff;
2201	}
2202	}
2203	#ifdef DEBUG_IOAPIC
2204	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
2205	#endif
2206	}
2207	return val;
2208	}
2209
2210	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2211	{
2212	IOAPICState s = (IOAPICState)opaque;
2213	int index;
2214
2215	addr &= 0xff;
2216	if (addr == 0x00) {
2217	s->ioregsel = val;
2218	return;
2219	} else if (addr == 0x10) {
2220	#ifdef DEBUG_IOAPIC
2221	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
2222	#endif
2223	switch (s->ioregsel) {
2224	case 0x00:
2225	s->id = (val >> 24) & 0xff;
2226	return;
2227	case 0x01:
2228	case 0x02:
2229	return;
2230	default:
2231	index = (s->ioregsel - 0x10) >> 1;
2232	if (index >= 0 && index < IOAPIC_NUM_PINS) {
2233	if (s->ioregsel & 1) {
2234	s->ioredtbl[index] &= 0xffffffff;
2235	s->ioredtbl[index] \|= (uint64_t)val << 32;
2236	} else {
2237	#ifdef VBOX
2238	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
2239	uint8_t vec = val & 0xff;
2240	if ((val & APIC_LVT_MASKED) \|\|
2241	((vec >= 0x10) && (vec < 0xff)))
2242	{
2243	s->ioredtbl[index] &= ~0xffffffffULL;
2244	s->ioredtbl[index] \|= val;
2245	}
2246	else
2247	{
2248	/*
2249	* Linux 2.6 kernels has pretty strange function
2250	* unlock_ExtINT_logic() which writes
2251	* absolutely bogus (all 0) value into the vector
2252	* with pretty vague explanation why.
2253	* So we just ignore such writes.
2254	*/
2255	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
2256	}
2257	}
2258	#else
2259	s->ioredtbl[index] &= ~0xffffffffULL;
2260	s->ioredtbl[index] \|= val;
2261	#endif
2262	ioapic_service(s);
2263	}
2264	}
2265	}
2266	}
2267
2268	#ifdef IN_RING3
2269
2270	static void ioapic_save(QEMUFile f, void opaque)
2271	{
2272	IOAPICState s = (IOAPICState)opaque;
2273	int i;
2274
2275	qemu_put_8s(f, &s->id);
2276	qemu_put_8s(f, &s->ioregsel);
2277	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2278	qemu_put_be64s(f, &s->ioredtbl[i]);
2279	}
2280	}
2281
2282	static int ioapic_load(QEMUFile f, void opaque, int version_id)
2283	{
2284	IOAPICState s = (IOAPICState)opaque;
2285	int i;
2286
2287	if (version_id != 1)
2288	return -EINVAL;
2289
2290	qemu_get_8s(f, &s->id);
2291	qemu_get_8s(f, &s->ioregsel);
2292	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2293	qemu_get_be64s(f, &s->ioredtbl[i]);
2294	}
2295	return 0;
2296	}
2297
2298	static void ioapic_reset(void *opaque)
2299	{
2300	IOAPICState s = (IOAPICState)opaque;
2301	#ifdef VBOX
2302	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
2303	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
2304	#endif
2305	int i;
2306
2307	memset(s, 0, sizeof(*s));
2308	for(i = 0; i < IOAPIC_NUM_PINS; i++)
2309	s->ioredtbl[i] = 1 << 16; /* mask LVT */
2310
2311	#ifdef VBOX
2312	if (pDevIns)
2313	{
2314	s->pDevInsR3 = pDevIns;
2315	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2316	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2317	}
2318	if (pIoApicHlp)
2319	{
2320	s->pIoApicHlpR3 = pIoApicHlp;
2321	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2322	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2323	}
2324	#endif
2325	}
2326
2327	#endif /* IN_RING3 */
2328
2329	#ifndef VBOX
2330	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
2331	ioapic_mem_readl,
2332	ioapic_mem_readl,
2333	ioapic_mem_readl,
2334	};
2335
2336	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
2337	ioapic_mem_writel,
2338	ioapic_mem_writel,
2339	ioapic_mem_writel,
2340	};
2341
2342	IOAPICState *ioapic_init(void)
2343	{
2344	IOAPICState *s;
2345	int io_memory;
2346
2347	s = qemu_mallocz(sizeof(IOAPICState));
2348	if (!s)
2349	return NULL;
2350	ioapic_reset(s);
2351	s->id = last_apic_id++;
2352
2353	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
2354	ioapic_mem_write, s);
2355	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2356
2357	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2358	qemu_register_reset(ioapic_reset, s);
2359
2360	return s;
2361	}
2362	#endif /* !VBOX */
2363
2364	/* LAPIC */
2365	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2366	{
2367	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2368	APICState *s = getLapic(dev);
2369
2370	Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2371
2372	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2373	different physical addresses, see #3092) */
2374
2375	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2376	switch (cb)
2377	{
2378	case 1:
2379	(uint8_t )pv = 0;
2380	break;
2381
2382	case 2:
2383	(uint16_t )pv = 0;
2384	break;
2385
2386	case 4:
2387	{
2388	#if 0 /** @note experimental */
2389	#ifndef IN_RING3
2390	uint32_t index = (GCPhysAddr >> 4) & 0xff;
2391
2392	if ( index == 0x08 /* TPR */
2393	&& ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2394	{
2395	#ifdef IN_RC
2396	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2397	#else
2398	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2399	pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2400	#endif
2401	return VINF_PATM_HC_MMIO_PATCH_READ;
2402	}
2403	#endif
2404	#endif /* experimental */
2405	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2406	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
2407	APIC_UNLOCK(dev);
2408	break;
2409	}
2410	default:
2411	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2412	return VERR_INTERNAL_ERROR;
2413	}
2414	return VINF_SUCCESS;
2415	}
2416
2417	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2418	{
2419	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2420	APICState *s = getLapic(dev);
2421
2422	Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2423
2424	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2425	different physical addresses, see #3092) */
2426
2427	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2428	switch (cb)
2429	{
2430	case 1:
2431	case 2:
2432	/* ignore */
2433	break;
2434
2435	case 4:
2436	{
2437	int rc;
2438	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2439	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2440	APIC_UNLOCK(dev);
2441	return rc;
2442	}
2443
2444	default:
2445	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2446	return VERR_INTERNAL_ERROR;
2447	}
2448	return VINF_SUCCESS;
2449	}
2450
2451	#ifdef IN_RING3
2452
2453	/* Print a 8-dword LAPIC bit map (256 bits). */
2454	static void lapicDumpVec(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp, unsigned start)
2455	{
2456	unsigned i;
2457	uint32_t val;
2458
2459	for (i = 0; i < 8; ++i)
2460	{
2461	val = apic_mem_readl(dev, lapic, start + (i << 4));
2462	pHlp->pfnPrintf(pHlp, "%08X", val);
2463	}
2464	pHlp->pfnPrintf(pHlp, "\n");
2465	}
2466
2467	/* Print basic LAPIC state. */
2468	static DECLCALLBACK(void) lapicInfoBasic(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2469	{
2470	uint32_t val;
2471	unsigned max_lvt;
2472
2473	pHlp->pfnPrintf(pHlp, "Local APIC at %08X:\n", lapic->apicbase);
2474	val = apic_mem_readl(dev, lapic, 0x20);
2475	pHlp->pfnPrintf(pHlp, " LAPIC ID : %08X\n", val);
2476	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
2477	val = apic_mem_readl(dev, lapic, 0x30);
2478	max_lvt = (val >> 16) & 0xff;
2479	pHlp->pfnPrintf(pHlp, " APIC VER : %08X\n", val);
2480	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
2481	pHlp->pfnPrintf(pHlp, " lvts = %d\n", ((val >> 16) & 0xff) + 1);
2482	val = apic_mem_readl(dev, lapic, 0x80);
2483	pHlp->pfnPrintf(pHlp, " TPR : %08X\n", val);
2484	pHlp->pfnPrintf(pHlp, " task pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2485	val = apic_mem_readl(dev, lapic, 0xA0);
2486	pHlp->pfnPrintf(pHlp, " PPR : %08X\n", val);
2487	pHlp->pfnPrintf(pHlp, " cpu pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2488	val = apic_mem_readl(dev, lapic, 0xD0);
2489	pHlp->pfnPrintf(pHlp, " LDR : %08X\n", val);
2490	pHlp->pfnPrintf(pHlp, " log id = %02X\n", (val >> 24) & 0xff);
2491	val = apic_mem_readl(dev, lapic, 0xE0);
2492	pHlp->pfnPrintf(pHlp, " DFR : %08X\n", val);
2493	val = apic_mem_readl(dev, lapic, 0xF0);
2494	pHlp->pfnPrintf(pHlp, " SVR : %08X\n", val);
2495	pHlp->pfnPrintf(pHlp, " focus = %s\n", val & (1 << 9) ? "check off" : "check on");
2496	pHlp->pfnPrintf(pHlp, " lapic = %s\n", val & (1 << 8) ? "ENABLED" : "DISABLED");
2497	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2498	pHlp->pfnPrintf(pHlp, " ISR : ");
2499	lapicDumpVec(dev, lapic, pHlp, 0x100);
2500	val = get_highest_priority_int(lapic->isr);
2501	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2502	pHlp->pfnPrintf(pHlp, " IRR : ");
2503	lapicDumpVec(dev, lapic, pHlp, 0x200);
2504	val = get_highest_priority_int(lapic->irr);
2505	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2506	val = apic_mem_readl(dev, lapic, 0x320);
2507	}
2508
2509	/* Print the more interesting LAPIC LVT entries. */
2510	static DECLCALLBACK(void) lapicInfoLVT(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2511	{
2512	uint32_t val;
2513	static const char *dmodes[] = { "Fixed ", "Reserved", "SMI", "Reserved",
2514	"NMI", "INIT", "Reserved", "ExtINT" };
2515
2516	val = apic_mem_readl(dev, lapic, 0x320);
2517	pHlp->pfnPrintf(pHlp, " LVT Timer : %08X\n", val);
2518	pHlp->pfnPrintf(pHlp, " mode = %s\n", val & (1 << 17) ? "periodic" : "one-shot");
2519	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2520	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2521	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2522	val = apic_mem_readl(dev, lapic, 0x350);
2523	pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08X\n", val);
2524	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2525	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2526	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2527	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2528	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2529	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2530	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2531	val = apic_mem_readl(dev, lapic, 0x360);
2532	pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08X\n", val);
2533	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2534	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2535	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2536	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2537	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2538	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2539	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2540	}
2541
2542	/* Print LAPIC timer state. */
2543	static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2544	{
2545	uint32_t val;
2546	unsigned divider;
2547
2548	pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
2549	val = apic_mem_readl(dev, lapic, 0x380);
2550	pHlp->pfnPrintf(pHlp, " Initial count : %08X\n", val);
2551	val = apic_mem_readl(dev, lapic, 0x390);
2552	pHlp->pfnPrintf(pHlp, " Current count : %08X\n", val);
2553	val = apic_mem_readl(dev, lapic, 0x3E0);
2554	pHlp->pfnPrintf(pHlp, " Divide config : %08X\n", val);
2555	divider = ((val >> 1) & 0x04) \| (val & 0x03);
2556	pHlp->pfnPrintf(pHlp, " divider = %d\n", divider == 7 ? 1 : 2 << divider);
2557	}
2558
2559	/**
2560	* Info handler, device version. Dumps Local APIC(s) state according to given argument.
2561	*
2562	* @param pDevIns Device instance which registered the info.
2563	* @param pHlp Callback functions for doing output.
2564	* @param pszArgs Argument string. Optional.
2565	*/
2566	static DECLCALLBACK(void) lapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2567	{
2568	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2569	APICState *lapic;
2570
2571	lapic = getLapic(dev);
2572
2573	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2574	{
2575	lapicInfoBasic(dev, lapic, pHlp);
2576	}
2577	else if (!strcmp(pszArgs, "lvt"))
2578	{
2579	lapicInfoLVT(dev, lapic, pHlp);
2580	}
2581	else if (!strcmp(pszArgs, "timer"))
2582	{
2583	lapicInfoTimer(dev, lapic, pHlp);
2584	}
2585	else
2586	{
2587	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
2588	}
2589	}
2590
2591	/**
2592	* @copydoc FNSSMDEVLIVEEXEC
2593	*/
2594	static DECLCALLBACK(int) apicLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
2595	{
2596	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2597
2598	SSMR3PutU32( pSSM, pThis->cCpus);
2599	SSMR3PutBool(pSSM, pThis->fIoApic);
2600	SSMR3PutU32( pSSM, pThis->enmVersion);
2601	AssertCompile(PDMAPICVERSION_APIC == 2);
2602
2603	return VINF_SSM_DONT_CALL_AGAIN;
2604	}
2605
2606	/**
2607	* @copydoc FNSSMDEVSAVEEXEC
2608	*/
2609	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2610	{
2611	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2612
2613	/* config */
2614	apicLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
2615
2616	/* save all APICs data, @todo: is it correct? */
2617	foreach_apic(dev, 0xffffffff, apic_save(pSSM, apic));
2618
2619	return VINF_SUCCESS;
2620	}
2621
2622	/**
2623	* @copydoc FNSSMDEVLOADEXEC
2624	*/
2625	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2626	{
2627	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2628
2629	if ( uVersion != APIC_SAVED_STATE_VERSION
2630	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
2631	&& uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
2632	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2633
2634	/* config */
2635	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30) {
2636	uint32_t cCpus;
2637	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2638	if (cCpus != pThis->cCpus)
2639	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pThis->cCpus);
2640	bool fIoApic;
2641	rc = SSMR3GetBool(pSSM, &fIoApic); AssertRCReturn(rc, rc);
2642	if (fIoApic != pThis->fIoApic)
2643	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pThis->fIoApic);
2644	uint32_t uApicVersion;
2645	rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
2646	if (uApicVersion != (uint32_t)pThis->enmVersion)
2647	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pThis->enmVersion);
2648	}
2649
2650	if (uPass != SSM_PASS_FINAL)
2651	return VINF_SUCCESS;
2652
2653	/* load all APICs data / /* @todo: is it correct? */
2654	foreach_apic(pThis, 0xffffffff,
2655	if (apic_load(pSSM, apic, uVersion)) {
2656	AssertFailed();
2657	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2658	}
2659	);
2660	return VINF_SUCCESS;
2661	}
2662
2663	/**
2664	* @copydoc FNPDMDEVRESET
2665	*/
2666	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2667	{
2668	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2669	unsigned i;
2670
2671	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2672
2673	/* Reset all APICs. */
2674	for (i = 0; i < dev->cCpus; i++) {
2675	APICState *pApic = &dev->CTX_SUFF(paLapics)[i];
2676	TMTimerStop(pApic->CTX_SUFF(pTimer));
2677
2678	/* Clear LAPIC state as if an INIT IPI was sent. */
2679	apic_init_ipi(dev, pApic);
2680	/* The IDs are not touched by apic_init_ipi() and must be reset now. */
2681	pApic->arb_id = pApic->id = i;
2682	Assert(pApic->id == pApic->phys_id); /* The two should match again. */
2683	/* Reset should re-enable the APIC. */
2684	pApic->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_ENABLE;
2685	if (pApic->phys_id == 0)
2686	pApic->apicbase \|= MSR_IA32_APICBASE_BSP;
2687
2688	/* Clear any pending APIC interrupt action flag. */
2689	cpuClearInterrupt(dev, pApic);
2690	}
2691	/** @todo r=bird: Why is this done everytime, while the constructor first
2692	* checks the CPUID? Who is right? */
2693	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2694
2695	APIC_UNLOCK(dev);
2696	}
2697
2698	/**
2699	* @copydoc FNPDMDEVRELOCATE
2700	*/
2701	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2702	{
2703	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2704	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2705	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2706	pThis->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pThis->paLapicsR3);
2707	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2708	for (uint32_t i = 0; i < pThis->cCpus; i++)
2709	pThis->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pThis->paLapicsR3[i].pTimerR3);
2710	}
2711
2712	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2713	{
2714	int i;
2715	memset(apic, 0, sizeof(*apic));
2716	apic->apicbase = UINT32_C(0xfee00000) \| MSR_IA32_APICBASE_ENABLE;
2717	/* Mark first CPU as BSP */
2718	if (id == 0)
2719	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2720	for (i = 0; i < APIC_LVT_NB; i++)
2721	apic->lvt[i] = 1 << 16; /* mask LVT */
2722	apic->spurious_vec = 0xff;
2723	apic->phys_id = apic->id = id;
2724	}
2725
2726	/**
2727	* @copydoc FNPDMDEVCONSTRUCT
2728	*/
2729	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2730	{
2731	PDMAPICREG ApicReg;
2732	int rc;
2733	uint32_t i;
2734	bool fIoApic;
2735	bool fGCEnabled;
2736	bool fR0Enabled;
2737	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2738	uint32_t cCpus;
2739
2740	/*
2741	* Only single device instance.
2742	*/
2743	Assert(iInstance == 0);
2744
2745	/*
2746	* Validate configuration.
2747	*/
2748	if (!CFGMR3AreValuesValid(pCfgHandle,
2749	"IOAPIC\0"
2750	"GCEnabled\0"
2751	"R0Enabled\0"
2752	"NumCPUs\0"))
2753	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2754
2755	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIoApic, true);
2756	if (RT_FAILURE(rc))
2757	return PDMDEV_SET_ERROR(pDevIns, rc,
2758	N_("Configuration error: Failed to read \"IOAPIC\""));
2759
2760	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2761	if (RT_FAILURE(rc))
2762	return PDMDEV_SET_ERROR(pDevIns, rc,
2763	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2764
2765	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2766	if (RT_FAILURE(rc))
2767	return PDMDEV_SET_ERROR(pDevIns, rc,
2768	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2769
2770	rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2771	if (RT_FAILURE(rc))
2772	return PDMDEV_SET_ERROR(pDevIns, rc,
2773	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2774
2775	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIoApic));
2776
2777	/** @todo Current implementation is limited to 32 CPUs due to the use of 32
2778	* bits bitmasks. */
2779	if (cCpus > 32)
2780	return PDMDEV_SET_ERROR(pDevIns, rc,
2781	N_("Configuration error: Invalid value for \"NumCPUs\""));
2782
2783	/*
2784	* Init the data.
2785	*/
2786	pThis->pDevInsR3 = pDevIns;
2787	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2788	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2789	pThis->cCpus = cCpus;
2790	pThis->fIoApic = fIoApic;
2791	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2792	pThis->enmVersion = PDMAPICVERSION_APIC;
2793
2794	PVM pVM = PDMDevHlpGetVM(pDevIns);
2795	/*
2796	* We are not freeing this memory, as it's automatically released when guest exits.
2797	*/
2798	rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->paLapicsR3);
2799	if (RT_FAILURE(rc))
2800	return VERR_NO_MEMORY;
2801	pThis->paLapicsR0 = MMHyperR3ToR0(pVM, pThis->paLapicsR3);
2802	pThis->paLapicsRC = MMHyperR3ToRC(pVM, pThis->paLapicsR3);
2803
2804	for (i = 0; i < cCpus; i++)
2805	initApicData(&pThis->paLapicsR3[i], i);
2806
2807	/*
2808	* Register the APIC.
2809	*/
2810	ApicReg.u32Version = PDM_APICREG_VERSION;
2811	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2812	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2813	ApicReg.pfnSetBaseR3 = apicSetBase;
2814	ApicReg.pfnGetBaseR3 = apicGetBase;
2815	ApicReg.pfnSetTPRR3 = apicSetTPR;
2816	ApicReg.pfnGetTPRR3 = apicGetTPR;
2817	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2818	ApicReg.pfnReadMSRR3 = apicReadMSR;
2819	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2820	ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
2821	if (fGCEnabled) {
2822	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2823	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2824	ApicReg.pszSetBaseRC = "apicSetBase";
2825	ApicReg.pszGetBaseRC = "apicGetBase";
2826	ApicReg.pszSetTPRRC = "apicSetTPR";
2827	ApicReg.pszGetTPRRC = "apicGetTPR";
2828	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2829	ApicReg.pszReadMSRRC = "apicReadMSR";
2830	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2831	ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
2832	} else {
2833	ApicReg.pszGetInterruptRC = NULL;
2834	ApicReg.pszHasPendingIrqRC = NULL;
2835	ApicReg.pszSetBaseRC = NULL;
2836	ApicReg.pszGetBaseRC = NULL;
2837	ApicReg.pszSetTPRRC = NULL;
2838	ApicReg.pszGetTPRRC = NULL;
2839	ApicReg.pszWriteMSRRC = NULL;
2840	ApicReg.pszReadMSRRC = NULL;
2841	ApicReg.pszBusDeliverRC = NULL;
2842	ApicReg.pszLocalInterruptRC = NULL;
2843	}
2844	if (fR0Enabled) {
2845	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2846	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2847	ApicReg.pszSetBaseR0 = "apicSetBase";
2848	ApicReg.pszGetBaseR0 = "apicGetBase";
2849	ApicReg.pszSetTPRR0 = "apicSetTPR";
2850	ApicReg.pszGetTPRR0 = "apicGetTPR";
2851	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2852	ApicReg.pszReadMSRR0 = "apicReadMSR";
2853	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2854	ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
2855	} else {
2856	ApicReg.pszGetInterruptR0 = NULL;
2857	ApicReg.pszHasPendingIrqR0 = NULL;
2858	ApicReg.pszSetBaseR0 = NULL;
2859	ApicReg.pszGetBaseR0 = NULL;
2860	ApicReg.pszSetTPRR0 = NULL;
2861	ApicReg.pszGetTPRR0 = NULL;
2862	ApicReg.pszWriteMSRR0 = NULL;
2863	ApicReg.pszReadMSRR0 = NULL;
2864	ApicReg.pszBusDeliverR0 = NULL;
2865	ApicReg.pszLocalInterruptR0 = NULL;
2866	}
2867
2868	Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2869	rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2870	AssertLogRelRCReturn(rc, rc);
2871	pThis->pCritSectR3 = pThis->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2872
2873	/*
2874	* The the CPUID feature bit.
2875	*/
2876	/** @todo r=bird: See remark in the apicReset. */
2877	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2878	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2879	if (u32Eax >= 1) {
2880	if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
2881	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2882	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2883	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2884	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2885	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2886	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */)) {
2887	LogRel(("Activating Local APIC\n"));
2888	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2889	}
2890	}
2891
2892	/*
2893	* Register the MMIO range.
2894	*/
2895	uint32_t ApicBase = pThis->paLapicsR3[0].apicbase & ~0xfff;
2896	rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pThis,
2897	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2898	if (RT_FAILURE(rc))
2899	return rc;
2900
2901	if (fGCEnabled) {
2902	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2903	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2904
2905	rc = PDMDevHlpMMIORegisterGC(pDevIns, ApicBase, 0x1000, 0,
2906	"apicMMIOWrite", "apicMMIORead", NULL);
2907	if (RT_FAILURE(rc))
2908	return rc;
2909	}
2910
2911	if (fR0Enabled) {
2912	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2913	pThis->pCritSectR0 = pThis->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2914
2915	rc = PDMDevHlpMMIORegisterR0(pDevIns, ApicBase, 0x1000, 0,
2916	"apicMMIOWrite", "apicMMIORead", NULL);
2917	if (RT_FAILURE(rc))
2918	return rc;
2919	}
2920
2921	/*
2922	* Create the APIC timers.
2923	*/
2924	for (i = 0; i < cCpus; i++) {
2925	APICState *pApic = &pThis->paLapicsR3[i];
2926	pApic->pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_USER, "APIC Timer #%u", i);
2927	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimerCallback, pApic,
2928	TMTIMER_FLAGS_NO_CRIT_SECT, pApic->pszDesc, &pApic->pTimerR3);
2929	if (RT_FAILURE(rc))
2930	return rc;
2931	pApic->pTimerR0 = TMTimerR0Ptr(pApic->pTimerR3);
2932	pApic->pTimerRC = TMTimerRCPtr(pApic->pTimerR3);
2933	TMR3TimerSetCritSect(pApic->pTimerR3, pThis->pCritSectR3);
2934	}
2935
2936	/*
2937	* Saved state.
2938	*/
2939	rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pThis),
2940	apicLiveExec, apicSaveExec, apicLoadExec);
2941	if (RT_FAILURE(rc))
2942	return rc;
2943
2944	/*
2945	* Register debugger info callback.
2946	*/
2947	PDMDevHlpDBGFInfoRegister(pDevIns, "lapic", "Display Local APIC state for current CPU. "
2948	"Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", lapicInfo);
2949
2950	#ifdef VBOX_WITH_STATISTICS
2951	/*
2952	* Statistics.
2953	*/
2954	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2955	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2956	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2957	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2958	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2959	for (i = 0; i < cCpus; i++) {
2960	APICState *pApic = &pThis->paLapicsR3[i];
2961	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
2962	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
2963	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
2964	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
2965	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
2966	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
2967	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
2968	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
2969	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
2970	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
2971	}
2972	#endif
2973
2974	return VINF_SUCCESS;
2975	}
2976
2977
2978	/**
2979	* APIC device registration structure.
2980	*/
2981	const PDMDEVREG g_DeviceAPIC =
2982	{
2983	/* u32Version */
2984	PDM_DEVREG_VERSION,
2985	/* szDeviceName */
2986	"apic",
2987	/* szRCMod */
2988	"VBoxDD2GC.gc",
2989	/* szR0Mod */
2990	"VBoxDD2R0.r0",
2991	/* pszDescription */
2992	"Advanced Programmable Interrupt Controller (APIC) Device",
2993	/* fFlags */
2994	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2995	/* fClass */
2996	PDM_DEVREG_CLASS_PIC,
2997	/* cMaxInstances */
2998	1,
2999	/* cbInstance */
3000	sizeof(APICState),
3001	/* pfnConstruct */
3002	apicConstruct,
3003	/* pfnDestruct */
3004	NULL,
3005	/* pfnRelocate */
3006	apicRelocate,
3007	/* pfnIOCtl */
3008	NULL,
3009	/* pfnPowerOn */
3010	NULL,
3011	/* pfnReset */
3012	apicReset,
3013	/* pfnSuspend */
3014	NULL,
3015	/* pfnResume */
3016	NULL,
3017	/* pfnAttach */
3018	NULL,
3019	/* pfnDetach */
3020	NULL,
3021	/* pfnQueryInterface. */
3022	NULL,
3023	/* pfnInitComplete */
3024	NULL,
3025	/* pfnPowerOff */
3026	NULL,
3027	/* pfnSoftReset */
3028	NULL,
3029	/* u32VersionEnd */
3030	PDM_DEVREG_VERSION
3031	};
3032
3033	#endif /* IN_RING3 */
3034
3035
3036	/* IOAPIC */
3037
3038	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3039	{
3040	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3041	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
3042
3043	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
3044	switch (cb) {
3045	case 1:
3046	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3047	break;
3048
3049	case 2:
3050	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3051	break;
3052
3053	case 4:
3054	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3055	break;
3056
3057	default:
3058	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3059	IOAPIC_UNLOCK(s);
3060	return VERR_INTERNAL_ERROR;
3061	}
3062	IOAPIC_UNLOCK(s);
3063	return VINF_SUCCESS;
3064	}
3065
3066	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3067	{
3068	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3069
3070	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
3071	switch (cb) {
3072	case 1:
3073	case 2:
3074	case 4:
3075	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
3076	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
3077	IOAPIC_UNLOCK(s);
3078	break;
3079
3080	default:
3081	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3082	return VERR_INTERNAL_ERROR;
3083	}
3084	return VINF_SUCCESS;
3085	}
3086
3087	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
3088	{
3089	/* PDM lock is taken here; @todo add assertion */
3090	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
3091	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
3092	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
3093	ioapic_set_irq(pThis, iIrq, iLevel);
3094	}
3095
3096
3097	#ifdef IN_RING3
3098
3099	/**
3100	* Info handler, device version. Dumps I/O APIC state.
3101	*
3102	* @param pDevIns Device instance which registered the info.
3103	* @param pHlp Callback functions for doing output.
3104	* @param pszArgs Argument string. Optional and specific to the handler.
3105	*/
3106	static DECLCALLBACK(void) ioapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3107	{
3108	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3109	uint32_t val;
3110	unsigned i;
3111	unsigned max_redir;
3112
3113	pHlp->pfnPrintf(pHlp, "I/O APIC at %08X:\n", 0xfec00000);
3114	val = s->id << 24; /* Would be nice to call ioapic_mem_readl() directly, but that's not so simple. */
3115	pHlp->pfnPrintf(pHlp, " IOAPICID : %08X\n", val);
3116	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
3117	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16);
3118	max_redir = (val >> 16) & 0xff;
3119	pHlp->pfnPrintf(pHlp, " IOAPICVER : %08X\n", val);
3120	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
3121	pHlp->pfnPrintf(pHlp, " redirs = %d\n", ((val >> 16) & 0xff) + 1);
3122	val = 0;
3123	pHlp->pfnPrintf(pHlp, " IOAPICARB : %08X\n", val);
3124	pHlp->pfnPrintf(pHlp, " arb ID = %02X\n", (val >> 24) & 0xff);
3125	Assert(sizeof(s->ioredtbl) / sizeof(s->ioredtbl[0]) > max_redir);
3126	pHlp->pfnPrintf(pHlp, "I/O redirection table\n");
3127	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
3128	for (i = 0; i <= max_redir; ++i)
3129	{
3130	static const char *dmodes[] = { "Fixed ", "LowPri", "SMI ", "Resrvd",
3131	"NMI ", "INIT ", "Resrvd", "ExtINT" };
3132
3133	pHlp->pfnPrintf(pHlp, " %02d %s %02X %d %s %d %s %s %s %3d (%016llX)\n",
3134	i,
3135	s->ioredtbl[i] & (1 << 11) ? "log " : "phys", /* dest mode */
3136	(int)(s->ioredtbl[i] >> 56), /* dest addr */
3137	(int)(s->ioredtbl[i] >> 16) & 1, /* mask */
3138	s->ioredtbl[i] & (1 << 15) ? "level" : "edge ", /* trigger */
3139	(int)(s->ioredtbl[i] >> 14) & 1, /* remote IRR */
3140	s->ioredtbl[i] & (1 << 13) ? "activelo" : "activehi", /* polarity */
3141	s->ioredtbl[i] & (1 << 12) ? "pend" : "idle", /* delivery status */
3142	dmodes[(s->ioredtbl[i] >> 8) & 0x07], /* delivery mode */
3143	(int)s->ioredtbl[i] & 0xff, /* vector */
3144	s->ioredtbl[i] /* entire register */
3145	);
3146	}
3147	}
3148
3149	/**
3150	* @copydoc FNSSMDEVSAVEEXEC
3151	*/
3152	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3153	{
3154	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3155	ioapic_save(pSSM, s);
3156	return VINF_SUCCESS;
3157	}
3158
3159	/**
3160	* @copydoc FNSSMDEVLOADEXEC
3161	*/
3162	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3163	{
3164	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3165
3166	if (ioapic_load(pSSM, s, uVersion)) {
3167	AssertFailed();
3168	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3169	}
3170	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3171
3172	return VINF_SUCCESS;
3173	}
3174
3175	/**
3176	* @copydoc FNPDMDEVRESET
3177	*/
3178	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
3179	{
3180	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3181	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
3182	ioapic_reset(s);
3183	IOAPIC_UNLOCK(s);
3184	}
3185
3186	/**
3187	* @copydoc FNPDMDEVRELOCATE
3188	*/
3189	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3190	{
3191	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3192	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3193	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
3194	}
3195
3196	/**
3197	* @copydoc FNPDMDEVCONSTRUCT
3198	*/
3199	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3200	{
3201	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3202	PDMIOAPICREG IoApicReg;
3203	bool fGCEnabled;
3204	bool fR0Enabled;
3205	int rc;
3206
3207	Assert(iInstance == 0);
3208
3209	/*
3210	* Validate and read the configuration.
3211	*/
3212	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
3213	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
3214
3215	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
3216	if (RT_FAILURE(rc))
3217	return PDMDEV_SET_ERROR(pDevIns, rc,
3218	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
3219
3220	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
3221	if (RT_FAILURE(rc))
3222	return PDMDEV_SET_ERROR(pDevIns, rc,
3223	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
3224	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
3225
3226	/*
3227	* Initialize the state data.
3228	*/
3229	s->pDevInsR3 = pDevIns;
3230	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3231	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3232	ioapic_reset(s);
3233	s->id = 0;
3234
3235	/*
3236	* Register the IOAPIC and get helpers.
3237	*/
3238	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
3239	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
3240	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
3241	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
3242	rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
3243	if (RT_FAILURE(rc))
3244	{
3245	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
3246	return rc;
3247	}
3248
3249	/*
3250	* Register MMIO callbacks and saved state.
3251	*/
3252	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
3253	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
3254	if (RT_FAILURE(rc))
3255	return rc;
3256
3257	if (fGCEnabled) {
3258	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
3259
3260	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
3261	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
3262	if (RT_FAILURE(rc))
3263	return rc;
3264	}
3265
3266	if (fR0Enabled) {
3267	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
3268
3269	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
3270	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
3271	if (RT_FAILURE(rc))
3272	return rc;
3273	}
3274
3275	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* version /, sizeof(s), ioapicSaveExec, ioapicLoadExec);
3276	if (RT_FAILURE(rc))
3277	return rc;
3278
3279	/*
3280	* Register debugger info callback.
3281	*/
3282	PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display I/O APIC state.", ioapicInfo);
3283
3284	#ifdef VBOX_WITH_STATISTICS
3285	/*
3286	* Statistics.
3287	*/
3288	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
3289	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
3290	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
3291	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
3292	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
3293	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
3294	#endif
3295
3296	return VINF_SUCCESS;
3297	}
3298
3299	/**
3300	* IO APIC device registration structure.
3301	*/
3302	const PDMDEVREG g_DeviceIOAPIC =
3303	{
3304	/* u32Version */
3305	PDM_DEVREG_VERSION,
3306	/* szDeviceName */
3307	"ioapic",
3308	/* szRCMod */
3309	"VBoxDD2GC.gc",
3310	/* szR0Mod */
3311	"VBoxDD2R0.r0",
3312	/* pszDescription */
3313	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
3314	/* fFlags */
3315	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3316	/* fClass */
3317	PDM_DEVREG_CLASS_PIC,
3318	/* cMaxInstances */
3319	1,
3320	/* cbInstance */
3321	sizeof(IOAPICState),
3322	/* pfnConstruct */
3323	ioapicConstruct,
3324	/* pfnDestruct */
3325	NULL,
3326	/* pfnRelocate */
3327	ioapicRelocate,
3328	/* pfnIOCtl */
3329	NULL,
3330	/* pfnPowerOn */
3331	NULL,
3332	/* pfnReset */
3333	ioapicReset,
3334	/* pfnSuspend */
3335	NULL,
3336	/* pfnResume */
3337	NULL,
3338	/* pfnAttach */
3339	NULL,
3340	/* pfnDetach */
3341	NULL,
3342	/* pfnQueryInterface. */
3343	NULL,
3344	/* pfnInitComplete */
3345	NULL,
3346	/* pfnPowerOff */
3347	NULL,
3348	/* pfnSoftReset */
3349	NULL,
3350	/* u32VersionEnd */
3351	PDM_DEVREG_VERSION
3352	};
3353
3354	#endif /* IN_RING3 */
3355	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 24323

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