DevAPIC.cpp@ 24873

Last change on this file since 24873 was 24609, checked in by vboxsync, 15 years ago
DevAPIC: Disable NMI delivery through LAPIC (Linux NMI watchdog problems).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 109.7 KB

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1	#ifdef VBOX
2	/* $Id: DevAPIC.cpp 24609 2009-11-12 14:46:48Z vboxsync $ */
3	/** @file
4	* Advanced Programmable Interrupt Controller (APIC) Device and
5	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* apic.c revision 1.5 @@OSETODO
27	*/
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/pdmdev.h>
34
35	#include <VBox/log.h>
36	#include <VBox/stam.h>
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39
40	#include "Builtins2.h"
41	#include "vl_vbox.h"
42
43	#define MSR_IA32_APICBASE 0x1b
44	#define MSR_IA32_APICBASE_BSP (1<<8)
45	#define MSR_IA32_APICBASE_ENABLE (1<<11)
46	#ifdef VBOX
47	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48	#endif
49	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51	#ifndef EINVAL
52	# define EINVAL 1
53	#endif
54
55	#ifdef _MSC_VER
56	# pragma warning(disable:4244)
57	#endif
58
59	/** The current saved state version.*/
60	#define APIC_SAVED_STATE_VERSION 3
61	/** The saved state version used by VirtualBox v3 and earlier.
62	* This does not include the config. */
63	#define APIC_SAVED_STATE_VERSION_VBOX_30 2
64	/** Some ancient version... */
65	#define APIC_SAVED_STATE_VERSION_ANCIENT 1
66
67
68	/** @def APIC_LOCK
69	* Acquires the PDM lock. */
70	#define APIC_LOCK(pThis, rcBusy) \
71	do { \
72	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
73	if (rc2 != VINF_SUCCESS) \
74	return rc2; \
75	} while (0)
76
77	/** @def APIC_LOCK_VOID
78	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
79	#define APIC_LOCK_VOID(pThis, rcBusy) \
80	do { \
81	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
82	AssertLogRelRCReturnVoid(rc2); \
83	} while (0)
84
85	/** @def APIC_UNLOCK
86	* Releases the PDM lock. */
87	#define APIC_UNLOCK(pThis) \
88	PDMCritSectLeave((pThis)->CTX_SUFF(pCritSect))
89
90	/** @def IOAPIC_LOCK
91	* Acquires the PDM lock. */
92	#define IOAPIC_LOCK(pThis, rc) \
93	do { \
94	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
95	if (rc2 != VINF_SUCCESS) \
96	return rc2; \
97	} while (0)
98
99	/** @def IOAPIC_UNLOCK
100	* Releases the PDM lock. */
101	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
102
103
104	#define foreach_apic(dev, mask, code) \
105	do { \
106	uint32_t i; \
107	APICState *apic = (dev)->CTX_SUFF(paLapics); \
108	for (i = 0; i < (dev)->cCpus; i++) \
109	{ \
110	if (mask & (1 << (apic->id))) \
111	{ \
112	code; \
113	} \
114	apic++; \
115	} \
116	} while (0)
117
118	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
119	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
120	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
121	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
122
123	#endif /* VBOX */
124
125	/*
126	* APIC support
127	*
128	* Copyright (c) 2004-2005 Fabrice Bellard
129	*
130	* This library is free software; you can redistribute it and/or
131	* modify it under the terms of the GNU Lesser General Public
132	* License as published by the Free Software Foundation; either
133	* version 2 of the License, or (at your option) any later version.
134	*
135	* This library is distributed in the hope that it will be useful,
136	* but WITHOUT ANY WARRANTY; without even the implied warranty of
137	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
138	* Lesser General Public License for more details.
139	*
140	* You should have received a copy of the GNU Lesser General Public
141	* License along with this library; if not, write to the Free Software
142	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
143	*/
144	#ifndef VBOX
145	#include "vl.h"
146	#endif
147
148	#define DEBUG_APIC
149	#define DEBUG_IOAPIC
150
151	/* APIC Local Vector Table */
152	#define APIC_LVT_TIMER 0
153	#define APIC_LVT_THERMAL 1
154	#define APIC_LVT_PERFORM 2
155	#define APIC_LVT_LINT0 3
156	#define APIC_LVT_LINT1 4
157	#define APIC_LVT_ERROR 5
158	#define APIC_LVT_NB 6
159
160	/* APIC delivery modes */
161	#define APIC_DM_FIXED 0
162	#define APIC_DM_LOWPRI 1
163	#define APIC_DM_SMI 2
164	#define APIC_DM_NMI 4
165	#define APIC_DM_INIT 5
166	#define APIC_DM_SIPI 6
167	#define APIC_DM_EXTINT 7
168
169	/* APIC destination mode */
170	#define APIC_DESTMODE_FLAT 0xf
171	#define APIC_DESTMODE_CLUSTER 1
172
173	#define APIC_TRIGGER_EDGE 0
174	#define APIC_TRIGGER_LEVEL 1
175
176	#define APIC_LVT_TIMER_PERIODIC (1<<17)
177	#define APIC_LVT_MASKED (1<<16)
178	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
179	#define APIC_LVT_REMOTE_IRR (1<<14)
180	#define APIC_INPUT_POLARITY (1<<13)
181	#define APIC_SEND_PENDING (1<<12)
182
183	#define IOAPIC_NUM_PINS 0x18
184
185	#define ESR_ILLEGAL_ADDRESS (1 << 7)
186
187	#define APIC_SV_ENABLE (1 << 8)
188
189	#ifdef VBOX
190	#define APIC_MAX_PATCH_ATTEMPTS 100
191
192	typedef uint32_t PhysApicId;
193	typedef uint32_t LogApicId;
194	#endif
195
196	typedef struct APICState {
197	#ifndef VBOX
198	CPUState *cpu_env;
199	#endif /* !VBOX */
200	uint32_t apicbase;
201	#ifdef VBOX
202	/* Task priority register (interrupt level) */
203	uint32_t tpr;
204	/* Logical APIC id - user programmable */
205	LogApicId id;
206	/* Physical APIC id - not visible to user, constant */
207	PhysApicId phys_id;
208	/** @todo: is it logical or physical? Not really used anyway now. */
209	PhysApicId arb_id;
210	#else
211	uint8_t tpr;
212	uint8_t id;
213	uint8_t arb_id;
214	#endif
215	uint32_t spurious_vec;
216	uint8_t log_dest;
217	uint8_t dest_mode;
218	uint32_t isr[8]; /* in service register */
219	uint32_t tmr[8]; /* trigger mode register */
220	uint32_t irr[8]; /* interrupt request register */
221	uint32_t lvt[APIC_LVT_NB];
222	uint32_t esr; /* error register */
223	uint32_t icr[2];
224	uint32_t divide_conf;
225	int count_shift;
226	uint32_t initial_count;
227	#ifdef VBOX
228	uint32_t Alignment0;
229	#endif
230	#ifndef VBOX
231	int64_t initial_count_load_time, next_time;
232	QEMUTimer *timer;
233	struct APICState *next_apic;
234	#else
235	/** The time stamp of the initial_count load, i.e. when it was started. */
236	uint64_t initial_count_load_time;
237	/** The time stamp of the next timer callback. */
238	uint64_t next_time;
239	/** The APIC timer - R3 Ptr. */
240	PTMTIMERR3 pTimerR3;
241	/** The APIC timer - R0 Ptr. */
242	PTMTIMERR0 pTimerR0;
243	/** The APIC timer - RC Ptr. */
244	PTMTIMERRC pTimerRC;
245	/** Whether the timer is armed or not */
246	bool fTimerArmed;
247	/** Alignment */
248	bool afAlignment[3];
249	/** Timer description timer. */
250	R3PTRTYPE(char *) pszDesc;
251	# ifdef VBOX_WITH_STATISTICS
252	# if HC_ARCH_BITS == 32
253	uint32_t u32Alignment0;
254	# endif
255	STAMCOUNTER StatTimerSetInitialCount;
256	STAMCOUNTER StatTimerSetInitialCountArm;
257	STAMCOUNTER StatTimerSetInitialCountDisarm;
258	STAMCOUNTER StatTimerSetLvt;
259	STAMCOUNTER StatTimerSetLvtClearPeriodic;
260	STAMCOUNTER StatTimerSetLvtPostponed;
261	STAMCOUNTER StatTimerSetLvtArmed;
262	STAMCOUNTER StatTimerSetLvtArm;
263	STAMCOUNTER StatTimerSetLvtArmRetries;
264	STAMCOUNTER StatTimerSetLvtNoRelevantChange;
265	# endif
266	#endif /* VBOX */
267	} APICState;
268	#ifdef VBOX
269	AssertCompileMemberAlignment(APICState, initial_count_load_time, 8);
270	# ifdef VBOX_WITH_STATISTICS
271	AssertCompileMemberAlignment(APICState, StatTimerSetInitialCount, 8);
272	# endif
273	#endif
274
275	struct IOAPICState {
276	uint8_t id;
277	uint8_t ioregsel;
278
279	uint32_t irr;
280	uint64_t ioredtbl[IOAPIC_NUM_PINS];
281
282	#ifdef VBOX
283	/** The device instance - R3 Ptr. */
284	PPDMDEVINSR3 pDevInsR3;
285	/** The IOAPIC helpers - R3 Ptr. */
286	PCPDMIOAPICHLPR3 pIoApicHlpR3;
287
288	/** The device instance - R0 Ptr. */
289	PPDMDEVINSR0 pDevInsR0;
290	/** The IOAPIC helpers - R0 Ptr. */
291	PCPDMIOAPICHLPR0 pIoApicHlpR0;
292
293	/** The device instance - RC Ptr. */
294	PPDMDEVINSRC pDevInsRC;
295	/** The IOAPIC helpers - RC Ptr. */
296	PCPDMIOAPICHLPRC pIoApicHlpRC;
297
298	# ifdef VBOX_WITH_STATISTICS
299	STAMCOUNTER StatMMIOReadGC;
300	STAMCOUNTER StatMMIOReadHC;
301	STAMCOUNTER StatMMIOWriteGC;
302	STAMCOUNTER StatMMIOWriteHC;
303	STAMCOUNTER StatSetIrqGC;
304	STAMCOUNTER StatSetIrqHC;
305	# endif
306	#endif /* VBOX */
307	};
308
309	#ifdef VBOX
310	typedef struct IOAPICState IOAPICState;
311
312	typedef struct
313	{
314	/** The device instance - R3 Ptr. */
315	PPDMDEVINSR3 pDevInsR3;
316	/** The APIC helpers - R3 Ptr. */
317	PCPDMAPICHLPR3 pApicHlpR3;
318	/** LAPICs states - R3 Ptr */
319	R3PTRTYPE(APICState *) paLapicsR3;
320	/** The critical section - R3 Ptr. */
321	R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
322
323	/** The device instance - R0 Ptr. */
324	PPDMDEVINSR0 pDevInsR0;
325	/** The APIC helpers - R0 Ptr. */
326	PCPDMAPICHLPR0 pApicHlpR0;
327	/** LAPICs states - R0 Ptr */
328	R0PTRTYPE(APICState *) paLapicsR0;
329	/** The critical section - R3 Ptr. */
330	R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
331
332	/** The device instance - RC Ptr. */
333	PPDMDEVINSRC pDevInsRC;
334	/** The APIC helpers - RC Ptr. */
335	PCPDMAPICHLPRC pApicHlpRC;
336	/** LAPICs states - RC Ptr */
337	RCPTRTYPE(APICState *) paLapicsRC;
338	/** The critical section - R3 Ptr. */
339	RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
340
341	/** APIC specification version in this virtual hardware configuration. */
342	PDMAPICVERSION enmVersion;
343
344	/** Number of attempts made to optimize TPR accesses. */
345	uint32_t cTPRPatchAttempts;
346
347	/** Number of CPUs on the system (same as LAPIC count). */
348	uint32_t cCpus;
349	/** Whether we've got an IO APIC or not. */
350	bool fIoApic;
351	/** Alignment padding. */
352	bool afPadding[3];
353
354	# ifdef VBOX_WITH_STATISTICS
355	STAMCOUNTER StatMMIOReadGC;
356	STAMCOUNTER StatMMIOReadHC;
357	STAMCOUNTER StatMMIOWriteGC;
358	STAMCOUNTER StatMMIOWriteHC;
359	STAMCOUNTER StatClearedActiveIrq;
360	# endif
361	} APICDeviceInfo;
362	# ifdef VBOX_WITH_STATISTICS
363	AssertCompileMemberAlignment(APICDeviceInfo, StatMMIOReadGC, 8);
364	# endif
365	#endif /* VBOX */
366
367	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
368
369	#ifndef VBOX
370	static int apic_io_memory;
371	static APICState *first_local_apic = NULL;
372	static int last_apic_id = 0;
373	#endif /* !VBOX */
374
375
376	#ifdef VBOX
377	/*******************************************************************************
378	* Internal Functions *
379	*******************************************************************************/
380	RT_C_DECLS_BEGIN
381	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
382	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
383	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
384	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
385	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
386	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
387	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val);
388	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu);
389	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
390	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
391	uint8_t u8TriggerMode);
392	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level);
393	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
394	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
395	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
396	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
397	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
398
399	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
400	RT_C_DECLS_END
401
402	static void apic_eoi(APICDeviceInfo dev, APICState s); /* */
403	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
404	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
405	uint8_t dest, uint8_t dest_mode,
406	uint8_t delivery_mode, uint8_t vector_num,
407	uint8_t polarity, uint8_t trigger_mode);
408	static int apic_get_arb_pri(APICState *s);
409	static int apic_get_ppr(APICState *s);
410	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
411	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState s, uint32_t initial_count);
412	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew);
413	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s);
414
415	#endif /* VBOX */
416
417	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s);
418	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
419	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
420
421
422	#ifdef VBOX
423
424	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
425	{
426	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
427	return &dev->CTX_SUFF(paLapics)[id];
428	}
429
430	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
431	{
432	/* LAPIC's array is indexed by CPU id */
433	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
434	return getLapicById(dev, id);
435	}
436
437	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
438	{
439	/* for now we assume LAPIC physical id == CPU id */
440	return VMCPUID(s->phys_id);
441	}
442
443	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
444	{
445	LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(dev, s)));
446	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
447	getCpuFromLapic(dev, s));
448	}
449
450	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
451	{
452	LogFlow(("apic: clear interrupt flag\n"));
453	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
454	getCpuFromLapic(dev, s));
455	}
456
457	# ifdef IN_RING3
458
459	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
460	{
461	Log2(("apic: send SIPI vector=%d\n", vector));
462
463	dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
464	getCpuFromLapic(dev, s),
465	vector);
466	}
467
468	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* dev, APICState *s)
469	{
470	Log2(("apic: send init IPI\n"));
471
472	dev->pApicHlpR3->pfnSendInitIpi(dev->pDevInsR3,
473	getCpuFromLapic(dev, s));
474	}
475
476	# endif /* IN_RING3 */
477
478	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
479	{
480	switch (dev->enmVersion)
481	{
482	case PDMAPICVERSION_NONE:
483	return 0;
484	case PDMAPICVERSION_APIC:
485	return MSR_IA32_APICBASE_ENABLE;
486	case PDMAPICVERSION_X2APIC:
487	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
488	default:
489	AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
490	return 0;
491	}
492	}
493
494	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
495	{
496	switch (((apic->apicbase) >> 10) & 0x3)
497	{
498	case 0:
499	return PDMAPICVERSION_NONE;
500	case 1:
501	default:
502	/* Invalid */
503	return PDMAPICVERSION_NONE;
504	case 2:
505	return PDMAPICVERSION_APIC;
506	case 3:
507	return PDMAPICVERSION_X2APIC;
508	}
509	}
510
511	#endif /* VBOX */
512
513	#ifndef VBOX
514	static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
515	uint8_t vector_num, uint8_t polarity,
516	uint8_t trigger_mode)
517	{
518	APICState *apic_iter;
519	#else /* VBOX */
520	static int apic_bus_deliver(APICDeviceInfo* dev,
521	uint32_t deliver_bitmask, uint8_t delivery_mode,
522	uint8_t vector_num, uint8_t polarity,
523	uint8_t trigger_mode)
524	{
525	#endif /* VBOX */
526
527	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
528	switch (delivery_mode) {
529	case APIC_DM_LOWPRI:
530	{
531	int d = -1;
532	if (deliver_bitmask)
533	d = ffs_bit(deliver_bitmask);
534	if (d >= 0)
535	{
536	APICState* apic = getLapicById(dev, d);
537	apic_set_irq(dev, apic, vector_num, trigger_mode);
538	}
539	return VINF_SUCCESS;
540	}
541	case APIC_DM_FIXED:
542	/* XXX: arbitration */
543	break;
544
545	case APIC_DM_SMI:
546	foreach_apic(dev, deliver_bitmask,
547	cpuSetInterrupt(dev, apic, PDMAPICIRQ_SMI));
548	return VINF_SUCCESS;
549
550	case APIC_DM_NMI:
551	foreach_apic(dev, deliver_bitmask,
552	cpuSetInterrupt(dev, apic, PDMAPICIRQ_NMI));
553	return VINF_SUCCESS;
554
555	case APIC_DM_INIT:
556	/* normal INIT IPI sent to processors */
557	#ifdef VBOX
558	#ifdef IN_RING3
559	foreach_apic(dev, deliver_bitmask,
560	apicSendInitIpi(dev, apic));
561	return VINF_SUCCESS;
562	#else
563	/* We shall send init IPI only in R3, R0 calls should be
564	rescheduled to R3 */
565	return VINF_IOM_HC_MMIO_READ_WRITE;
566	#endif /* IN_RING3 */
567
568	#else
569	for (apic_iter = first_local_apic; apic_iter != NULL;
570	apic_iter = apic_iter->next_apic) {
571	apic_init_ipi(apic_iter);
572	}
573	#endif
574
575	case APIC_DM_EXTINT:
576	/* handled in I/O APIC code */
577	break;
578
579	default:
580	return VINF_SUCCESS;
581	}
582
583	#ifdef VBOX
584	foreach_apic(dev, deliver_bitmask,
585	apic_set_irq (dev, apic, vector_num, trigger_mode));
586	return VINF_SUCCESS;
587	#else /* VBOX */
588	for (apic_iter = first_local_apic; apic_iter != NULL;
589	apic_iter = apic_iter->next_apic) {
590	if (deliver_bitmask & (1 << apic_iter->id))
591	apic_set_irq(apic_iter, vector_num, trigger_mode);
592	}
593	#endif /* VBOX */
594	}
595
596	#ifndef VBOX
597	void cpu_set_apic_base(CPUState *env, uint64_t val)
598	{
599	APICState *s = env->apic_state;
600	#ifdef DEBUG_APIC
601	Log(("cpu_set_apic_base: %016llx\n", val));
602	#endif
603
604	s->apicbase = (val & 0xfffff000) \|
605	(s->apicbase & (MSR_IA32_APICBASE_BSP \| MSR_IA32_APICBASE_ENABLE));
606	/* if disabled, cannot be enabled again */
607	if (!(val & MSR_IA32_APICBASE_ENABLE)) {
608	s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
609	env->cpuid_features &= ~CPUID_APIC;
610	s->spurious_vec &= ~APIC_SV_ENABLE;
611	}
612	}
613	#else /* VBOX */
614	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
615	{
616	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
617	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
618	APICState s = getLapic(dev); /* @todo fix interface */
619	Log(("cpu_set_apic_base: %016RX64\n", val));
620
621	/** @todo: do we need to lock here ? */
622	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
623	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
624	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
625	PDMAPICVERSION oldMode = getApicMode(s);
626	s->apicbase =
627	(val & 0xfffff000) \| /* base */
628	(val & getApicEnableBits(dev)) \| /* mode */
629	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
630	PDMAPICVERSION newMode = getApicMode(s);
631
632	if (oldMode != newMode)
633	{
634	switch (newMode)
635	{
636	case PDMAPICVERSION_NONE:
637	{
638	s->spurious_vec &= ~APIC_SV_ENABLE;
639	/* Clear any pending APIC interrupt action flag. */
640	cpuClearInterrupt(dev, s);
641	/** @todo: why do we do that? */
642	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
643	break;
644	}
645	case PDMAPICVERSION_APIC:
646	/** @todo: map MMIO ranges, if needed */
647	break;
648	case PDMAPICVERSION_X2APIC:
649	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
650	break;
651	default:
652	break;
653	}
654	}
655	/* APIC_UNLOCK(dev); */
656	}
657	#endif /* VBOX */
658
659	#ifndef VBOX
660
661	uint64_t cpu_get_apic_base(CPUState *env)
662	{
663	APICState *s = env->apic_state;
664	#ifdef DEBUG_APIC
665	Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
666	#endif
667	return s->apicbase;
668	}
669
670	void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
671	{
672	APICState *s = env->apic_state;
673	s->tpr = (val & 0x0f) << 4;
674	apic_update_irq(s);
675	}
676
677	uint8_t cpu_get_apic_tpr(CPUX86State *env)
678	{
679	APICState *s = env->apic_state;
680	return s->tpr >> 4;
681	}
682
683	static int fls_bit(int value)
684	{
685	unsigned int ret = 0;
686
687	#ifdef HOST_I386
688	__asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
689	return ret;
690	#else
691	if (value > 0xffff)
692	value >>= 16, ret = 16;
693	if (value > 0xff)
694	value >>= 8, ret += 8;
695	if (value > 0xf)
696	value >>= 4, ret += 4;
697	if (value > 0x3)
698	value >>= 2, ret += 2;
699	return ret + (value >> 1);
700	#endif
701	}
702
703	static inline void set_bit(uint32_t *tab, int index)
704	{
705	int i, mask;
706	i = index >> 5;
707	mask = 1 << (index & 0x1f);
708	tab[i] \|= mask;
709	}
710
711	static inline void reset_bit(uint32_t *tab, int index)
712	{
713	int i, mask;
714	i = index >> 5;
715	mask = 1 << (index & 0x1f);
716	tab[i] &= ~mask;
717	}
718
719
720	#else /* VBOX */
721
722	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
723	{
724	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
725	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
726	APICState s = getLapic(dev); /* @todo fix interface */
727	LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
728	return s->apicbase;
729	}
730
731	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
732	{
733	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
734	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
735	APICState *s = getLapicById(dev, idCpu);
736	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, val));
737	apic_update_tpr(dev, s, val);
738	}
739
740	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
741	{
742	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
743	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
744	APICState *s = getLapicById(dev, idCpu);
745	Log2(("apicGetTPR: returns %#x\n", s->tpr));
746	return s->tpr;
747	}
748
749	/**
750	* x2APIC MSR write interface.
751	*
752	* @returns VBox status code.
753	*
754	* @param pDevIns The device instance.
755	* @param idCpu The ID of the virtual CPU and thereby APIC index.
756	* @param u32Reg Register to write (ecx).
757	* @param u64Value The value to write (eax:edx / rax).
758	*
759	*/
760	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
761	{
762	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
763	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
764	int rc = VINF_SUCCESS;
765
766	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
767	return VERR_EM_INTERPRETER;
768
769	APICState *pThis = getLapicById(dev, idCpu);
770
771	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
772	switch (index)
773	{
774	case 0x02:
775	pThis->id = (u64Value >> 24);
776	break;
777	case 0x03:
778	break;
779	case 0x08:
780	apic_update_tpr(dev, pThis, u64Value);
781	break;
782	case 0x09: case 0x0a:
783	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
784	break;
785	case 0x0b: /* EOI */
786	apic_eoi(dev, pThis);
787	break;
788	case 0x0d:
789	pThis->log_dest = u64Value >> 24;
790	break;
791	case 0x0e:
792	pThis->dest_mode = u64Value >> 28;
793	break;
794	case 0x0f:
795	pThis->spurious_vec = u64Value & 0x1ff;
796	apic_update_irq(dev, pThis);
797	break;
798	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
799	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
800	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
801	case 0x28:
802	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
803	break;
804
805	case 0x30:
806	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
807	pThis->icr[0] = (uint32_t)u64Value;
808	pThis->icr[1] = (uint32_t)(u64Value >> 32);
809	rc = apic_deliver(dev, pThis, (pThis->icr[1] >> 24) & 0xff, (pThis->icr[0] >> 11) & 1,
810	(pThis->icr[0] >> 8) & 7, (pThis->icr[0] & 0xff),
811	(pThis->icr[0] >> 14) & 1, (pThis->icr[0] >> 15) & 1);
812	break;
813	case 0x32 + APIC_LVT_TIMER:
814	AssertCompile(APIC_LVT_TIMER == 0);
815	apicTimerSetLvt(dev, pThis, u64Value);
816	break;
817
818	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
819	pThis->lvt[index - 0x32] = u64Value;
820	break;
821	case 0x38:
822	apicTimerSetInitialCount(dev, pThis, u64Value);
823	break;
824	case 0x39:
825	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
826	break;
827	case 0x3e:
828	{
829	int v;
830	pThis->divide_conf = u64Value & 0xb;
831	v = (pThis->divide_conf & 3) \| ((pThis->divide_conf >> 1) & 4);
832	pThis->count_shift = (v + 1) & 7;
833	break;
834	}
835	case 0x3f:
836	{
837	/* Self IPI, see x2APIC book 2.4.5 */
838	int vector = u64Value & 0xff;
839	rc = apic_bus_deliver(dev,
840	1 << getLapicById(dev, idCpu)->id /* Self */,
841	0 /* Delivery mode - fixed */,
842	vector,
843	0 /* Polarity - conform to the bus */,
844	0 /* Trigger mode - edge */);
845	break;
846	}
847	default:
848	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
849	pThis->esr \|= ESR_ILLEGAL_ADDRESS;
850	break;
851	}
852
853	return rc;
854	}
855
856	/**
857	* x2APIC MSR read interface.
858	*
859	* @returns VBox status code.
860	*
861	* @param pDevIns The device instance.
862	* @param idCpu The ID of the virtual CPU and thereby APIC index.
863	* @param u32Reg Register to write (ecx).
864	* @param pu64Value Where to return the value (eax:edx / rax).
865	*/
866	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
867	{
868	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
869	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
870
871	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
872	return VERR_EM_INTERPRETER;
873
874	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
875	APICState* apic = getLapicById(dev, idCpu);
876	uint64_t val = 0;
877
878	switch (index)
879	{
880	case 0x02: /* id */
881	val = apic->id << 24;
882	break;
883	case 0x03: /* version */
884	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
885	break;
886	case 0x08:
887	val = apic->tpr;
888	break;
889	case 0x09:
890	val = apic_get_arb_pri(apic);
891	break;
892	case 0x0a:
893	/* ppr */
894	val = apic_get_ppr(apic);
895	break;
896	case 0x0b:
897	val = 0;
898	break;
899	case 0x0d:
900	val = apic->log_dest << 24;
901	break;
902	case 0x0e:
903	/* Bottom 28 bits are always 1 */
904	val = (apic->dest_mode << 28) \| 0xfffffff;
905	break;
906	case 0x0f:
907	val = apic->spurious_vec;
908	break;
909	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
910	val = apic->isr[index & 7];
911	break;
912	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
913	val = apic->tmr[index & 7];
914	break;
915	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
916	val = apic->irr[index & 7];
917	break;
918	case 0x28:
919	val = apic->esr;
920	break;
921	case 0x30:
922	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
923	val = ((uint64_t)apic->icr[0x31] << 32) \| apic->icr[0x30];
924	break;
925	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
926	val = apic->lvt[index - 0x32];
927	break;
928	case 0x38:
929	val = apic->initial_count;
930	break;
931	case 0x39:
932	val = apic_get_current_count(dev, apic);
933	break;
934	case 0x3e:
935	val = apic->divide_conf;
936	break;
937	case 0x3f:
938	/* Self IPI register is write only */
939	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
940	break;
941	default:
942	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
943	apic->esr \|= ESR_ILLEGAL_ADDRESS;
944	val = 0;
945	break;
946	}
947	*pu64Value = val;
948	return VINF_SUCCESS;
949	}
950
951	/**
952	* More or less private interface between IOAPIC, only PDM is responsible
953	* for connecting the two devices.
954	*/
955	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
956	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
957	uint8_t u8TriggerMode)
958	{
959	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
960	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
961	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
962	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
963	return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
964	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
965	}
966
967	/**
968	* Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
969	* Normally used for 8259A PIC and NMI.
970	*/
971	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
972	{
973	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
974	APICState *s = getLapicById(dev, 0);
975
976	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
977	LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x\n", pDevIns, u8Pin));
978
979	/* If LAPIC is disabled, go straight to the CPU. */
980	if (!(s->spurious_vec & APIC_SV_ENABLE))
981	{
982	LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
983	if (u8Level)
984	cpuSetInterrupt(dev, s, PDMAPICIRQ_EXTINT);
985	else
986	cpuClearInterrupt(dev, s, PDMAPICIRQ_EXTINT);
987
988	return VINF_SUCCESS;
989	}
990
991	/* If LAPIC is enabled, interrupts are subject to LVT programming. */
992
993	/* There are only two local interrupt pins. */
994	AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
995
996	/* NB: We currently only deliver local interrupts to the first CPU. In theory they
997	* should be delivered to all CPUs and it is the guest's responsibility to ensure
998	* no more than one CPU has the interrupt unmasked.
999	*/
1000	uint32_t u32Lvec;
1001
1002	u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin]; /* Fetch corresponding LVT entry. */
1003	/* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
1004	if (!(u32Lvec & APIC_LVT_MASKED))
1005	{ uint8_t u8Delivery;
1006	PDMAPICIRQ enmType;
1007
1008	u8Delivery = (u32Lvec >> 8) & 7;
1009	switch (u8Delivery)
1010	{
1011	case APIC_DM_EXTINT:
1012	Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
1013	enmType = PDMAPICIRQ_EXTINT;
1014	/* ExtINT can be both set and cleared, NMI/SMI/INIT can only be set. */
1015	LogFlow(("apicLocalInterrupt: %s ExtINT interrupt\n", u8Level ? "setting" : "clearing"));
1016	if (u8Level)
1017	cpuSetInterrupt(dev, s, enmType);
1018	else
1019	cpuClearInterrupt(dev, s, enmType);
1020	return VINF_SUCCESS;
1021	case APIC_DM_NMI:
1022	/* External NMI should be wired to LINT1, but Linux sometimes programs
1023	* LVT0 to NMI delivery mode as well.
1024	*/
1025	enmType = PDMAPICIRQ_NMI;
1026	/* Currently delivering NMIs through here causes problems with NMI watchdogs
1027	* on certain Linux kernels, e.g. 64-bit CentOS 5.3. Disable NMIs for now.
1028	*/
1029	return VINF_SUCCESS;
1030	case APIC_DM_SMI:
1031	enmType = PDMAPICIRQ_SMI;
1032	break;
1033	case APIC_DM_FIXED:
1034	/** @todo implement APIC_DM_FIXED! */
1035	case APIC_DM_INIT:
1036	/** @todo implement APIC_DM_INIT? */
1037	default:
1038	{
1039	static unsigned s_c = 0;
1040	if (s_c++ < 100)
1041	AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d", u8Delivery, u8Pin, u8Level));
1042	return VERR_INTERNAL_ERROR_4;
1043	}
1044	}
1045	LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
1046	cpuSetInterrupt(dev, s, enmType);
1047	}
1048	return VINF_SUCCESS;
1049	}
1050
1051	#endif /* VBOX */
1052
1053	/* return -1 if no bit is set */
1054	static int get_highest_priority_int(uint32_t *tab)
1055	{
1056	int i;
1057	for(i = 7; i >= 0; i--) {
1058	if (tab[i] != 0) {
1059	return i * 32 + fls_bit(tab[i]);
1060	}
1061	}
1062	return -1;
1063	}
1064
1065	static int apic_get_ppr(APICState *s)
1066	{
1067	int tpr, isrv, ppr;
1068
1069	tpr = (s->tpr >> 4);
1070	isrv = get_highest_priority_int(s->isr);
1071	if (isrv < 0)
1072	isrv = 0;
1073	isrv >>= 4;
1074	if (tpr >= isrv)
1075	ppr = s->tpr;
1076	else
1077	ppr = isrv << 4;
1078	return ppr;
1079	}
1080
1081	static int apic_get_ppr_zero_tpr(APICState *s)
1082	{
1083	int isrv;
1084
1085	isrv = get_highest_priority_int(s->isr);
1086	if (isrv < 0)
1087	isrv = 0;
1088	return isrv;
1089	}
1090
1091	static int apic_get_arb_pri(APICState *s)
1092	{
1093	/* XXX: arbitration */
1094	return 0;
1095	}
1096
1097	/* signal the CPU if an irq is pending */
1098	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
1099	{
1100	int irrv, ppr;
1101	if (!(s->spurious_vec & APIC_SV_ENABLE))
1102	#ifdef VBOX
1103	{
1104	/* Clear any pending APIC interrupt action flag. */
1105	cpuClearInterrupt(dev, s);
1106	return false;
1107	}
1108	#else
1109	return false;
1110	#endif /* VBOX */
1111	irrv = get_highest_priority_int(s->irr);
1112	if (irrv < 0)
1113	return false;
1114	ppr = apic_get_ppr(s);
1115	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1116	return false;
1117	#ifndef VBOX
1118	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
1119	#else
1120	cpuSetInterrupt(dev, s);
1121	return true;
1122	#endif
1123	}
1124
1125	#ifdef VBOX
1126
1127	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
1128	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
1129	{
1130	int irrv, ppr;
1131	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1132	if (!dev)
1133	return false;
1134
1135	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
1136
1137	APICState s = getLapic(dev); /* @todo fix interface */
1138
1139	/*
1140	* All our callbacks now come from single IOAPIC, thus locking
1141	* seems to be excessive now (@todo: check)
1142	*/
1143	irrv = get_highest_priority_int(s->irr);
1144	if (irrv < 0)
1145	return false;
1146
1147	ppr = apic_get_ppr_zero_tpr(s);
1148
1149	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1150	return false;
1151
1152	return true;
1153	}
1154
1155	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
1156	{
1157	bool fIrqIsActive = false;
1158	bool fIrqWasActive = false;
1159
1160	fIrqWasActive = apic_update_irq(dev, s);
1161	s->tpr = val;
1162	fIrqIsActive = apic_update_irq(dev, s);
1163
1164	/* If an interrupt is pending and now masked, then clear the FF flag. */
1165	if (fIrqWasActive && !fIrqIsActive)
1166	{
1167	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1168	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
1169	cpuClearInterrupt(dev, s);
1170	}
1171	}
1172	#endif
1173
1174	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
1175	{
1176	LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode));
1177	set_bit(s->irr, vector_num);
1178	if (trigger_mode)
1179	set_bit(s->tmr, vector_num);
1180	else
1181	reset_bit(s->tmr, vector_num);
1182	apic_update_irq(dev, s);
1183	}
1184
1185	static void apic_eoi(APICDeviceInfo dev, APICState s)
1186	{
1187	int isrv;
1188	isrv = get_highest_priority_int(s->isr);
1189	if (isrv < 0)
1190	return;
1191	reset_bit(s->isr, isrv);
1192	LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1193	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1194	set the remote IRR bit for level triggered interrupts. */
1195	apic_update_irq(dev, s);
1196	}
1197
1198	#ifndef VBOX
1199	static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1200	#else /* VBOX */
1201	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1202	#endif /* VBOX */
1203	{
1204	uint32_t mask = 0;
1205
1206	if (dest_mode == 0)
1207	{
1208	if (dest == 0xff)
1209	mask = 0xff;
1210	else
1211	mask = 1 << dest;
1212	}
1213	else
1214	{
1215	APICState *apic = dev->CTX_SUFF(paLapics);
1216	uint32_t i;
1217
1218	/* XXX: cluster mode */
1219	for(i = 0; i < dev->cCpus; i++)
1220	{
1221	if (apic->dest_mode == 0xf)
1222	{
1223	if (dest & apic->log_dest)
1224	mask \|= (1 << apic->id);
1225	}
1226	else if (apic->dest_mode == 0x0)
1227	{
1228	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1229	&&
1230	(dest & apic->log_dest & 0x0f))
1231	{
1232	mask \|= (1 << i);
1233	}
1234	}
1235	apic++;
1236	}
1237	}
1238
1239	return mask;
1240	}
1241
1242	#ifdef IN_RING3
1243	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s)
1244	{
1245	int i;
1246
1247	for(i = 0; i < APIC_LVT_NB; i++)
1248	s->lvt[i] = 1 << 16; /* mask LVT */
1249	s->tpr = 0;
1250	s->spurious_vec = 0xff;
1251	s->log_dest = 0;
1252	s->dest_mode = 0xff;
1253	memset(s->isr, 0, sizeof(s->isr));
1254	memset(s->tmr, 0, sizeof(s->tmr));
1255	memset(s->irr, 0, sizeof(s->irr));
1256	s->esr = 0;
1257	memset(s->icr, 0, sizeof(s->icr));
1258	s->divide_conf = 0;
1259	s->count_shift = 0;
1260	s->initial_count = 0;
1261	s->initial_count_load_time = 0;
1262	s->next_time = 0;
1263	}
1264
1265
1266	#ifdef VBOX
1267	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s)
1268	{
1269	apic_init_ipi(dev, s);
1270	cpuSendInitIpi(dev, s);
1271	}
1272	#endif
1273
1274	/* send a SIPI message to the CPU to start it */
1275	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1276	{
1277	#ifndef VBOX
1278	CPUState *env = s->cpu_env;
1279	if (!env->halted)
1280	return;
1281	env->eip = 0;
1282	cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1283	0xffff, 0);
1284	env->halted = 0;
1285	#else
1286	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1287	cpuSendSipi(dev, s, vector_num);
1288	#endif
1289	}
1290	#endif /* IN_RING3 */
1291
1292	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1293	uint8_t dest, uint8_t dest_mode,
1294	uint8_t delivery_mode, uint8_t vector_num,
1295	uint8_t polarity, uint8_t trigger_mode)
1296	{
1297	uint32_t deliver_bitmask = 0;
1298	int dest_shorthand = (s->icr[0] >> 18) & 3;
1299	#ifndef VBOX
1300	APICState *apic_iter;
1301	#endif /* !VBOX */
1302
1303	LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1304
1305	switch (dest_shorthand) {
1306	case 0:
1307	#ifndef VBOX
1308	deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1309	#else /* VBOX */
1310	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1311	#endif /* !VBOX */
1312	break;
1313	case 1:
1314	deliver_bitmask = (1 << s->id);
1315	break;
1316	case 2:
1317	deliver_bitmask = 0xffffffff;
1318	break;
1319	case 3:
1320	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1321	break;
1322	}
1323
1324	switch (delivery_mode) {
1325	case APIC_DM_INIT:
1326	{
1327	int trig_mode = (s->icr[0] >> 15) & 1;
1328	int level = (s->icr[0] >> 14) & 1;
1329	if (level == 0 && trig_mode == 1) {
1330	foreach_apic(dev, deliver_bitmask,
1331	apic->arb_id = apic->id);
1332	#ifndef VBOX
1333	return;
1334	#else
1335	Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1336	return VINF_SUCCESS;
1337	#endif
1338	}
1339	}
1340	break;
1341
1342	case APIC_DM_SIPI:
1343	#ifndef VBOX
1344	for (apic_iter = first_local_apic; apic_iter != NULL;
1345	apic_iter = apic_iter->next_apic) {
1346	if (deliver_bitmask & (1 << apic_iter->id)) {
1347	/* XXX: SMP support */
1348	/* apic_startup(apic_iter); */
1349	}
1350	}
1351	return;
1352	#else
1353	# ifdef IN_RING3
1354	foreach_apic(dev, deliver_bitmask,
1355	apic_startup(dev, apic, vector_num));
1356	return VINF_SUCCESS;
1357	# else
1358	/* We shall send SIPI only in R3, R0 calls should be
1359	rescheduled to R3 */
1360	return VINF_IOM_HC_MMIO_WRITE;
1361	# endif
1362	#endif /* !VBOX */
1363	}
1364
1365	#ifndef VBOX
1366	apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1367	trigger_mode);
1368	#else /* VBOX */
1369	return apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num,
1370	polarity, trigger_mode);
1371	#endif /* VBOX */
1372	}
1373
1374
1375	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1376	{
1377	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1378	/* if the APIC is not installed or enabled, we let the 8259 handle the
1379	IRQs */
1380	if (!dev)
1381	{
1382	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1383	return -1;
1384	}
1385
1386	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
1387
1388	APICState s = getLapic(dev); /* @todo fix interface */
1389	int intno;
1390
1391	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1392	Log(("CPU%d: apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n", s->phys_id));
1393	return -1;
1394	}
1395
1396	/* XXX: spurious IRQ handling */
1397	intno = get_highest_priority_int(s->irr);
1398	if (intno < 0) {
1399	Log(("CPU%d: apic_get_interrupt: returns -1 (irr)\n", s->phys_id));
1400	return -1;
1401	}
1402	if (s->tpr && (uint32_t)intno <= s->tpr) {
1403	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1404	return s->spurious_vec & 0xff;
1405	}
1406	reset_bit(s->irr, intno);
1407	set_bit(s->isr, intno);
1408	apic_update_irq(dev, s);
1409	LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno));
1410	return intno;
1411	}
1412
1413	static uint32_t apic_get_current_count(APICDeviceInfo dev, APICState s)
1414	{
1415	int64_t d;
1416	uint32_t val;
1417	#ifndef VBOX
1418	d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1419	s->count_shift;
1420	#else /* VBOX */
1421	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1422	s->count_shift;
1423	#endif /* VBOX */
1424	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1425	/* periodic */
1426	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1427	} else {
1428	if (d >= s->initial_count)
1429	val = 0;
1430	else
1431	val = s->initial_count - d;
1432	}
1433	return val;
1434	}
1435
1436	#ifndef VBOX /* we've replaced all the code working the APIC timer. */
1437
1438	static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1439	{
1440	int64_t next_time, d;
1441
1442	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1443	d = (current_time - s->initial_count_load_time) >>
1444	s->count_shift;
1445	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1446	d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1447	} else {
1448	if (d >= s->initial_count)
1449	goto no_timer;
1450	d = (uint64_t)s->initial_count + 1;
1451	}
1452	next_time = s->initial_count_load_time + (d << s->count_shift);
1453	# ifndef VBOX
1454	qemu_mod_timer(s->timer, next_time);
1455	# else
1456	TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1457	s->fTimerArmed = true;
1458	# endif
1459	s->next_time = next_time;
1460	} else {
1461	no_timer:
1462	# ifndef VBOX
1463	qemu_del_timer(s->timer);
1464	# else
1465	TMTimerStop(s->CTX_SUFF(pTimer));
1466	s->fTimerArmed = false;
1467	# endif
1468	}
1469	}
1470
1471	static void apic_timer(void *opaque)
1472	{
1473	APICState *s = opaque;
1474
1475	if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1476	LogFlow(("apic_timer: trigger irq\n"));
1477	apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1478	}
1479	apic_timer_update(dev, s, s->next_time);
1480	}
1481
1482	#else /* VBOX */
1483
1484	/**
1485	* Implementation of the 0380h access: Timer reset + new initial count.
1486	*
1487	* @param dev The device state.
1488	* @param pThis The APIC sub-device state.
1489	* @param u32NewInitialCount The new initial count for the timer.
1490	*/
1491	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState pThis, uint32_t u32NewInitialCount)
1492	{
1493	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCount);
1494	pThis->initial_count = u32NewInitialCount;
1495
1496	/*
1497	* Don't (re-)arm the timer if the it's masked or if it's
1498	* a zero length one-shot timer.
1499	*/
1500	/** @todo check the correct behavior of setting a 0 initial_count for a one-shot
1501	* timer. This is just copying the behavior of the original code. */
1502	if ( !(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)
1503	&& ( (pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1504	\|\| u32NewInitialCount != 0))
1505	{
1506	/*
1507	* Calculate the relative next time and perform a combined timer get/set
1508	* operation. This avoids racing the clock between get and set.
1509	*/
1510	uint64_t cTicksNext = u32NewInitialCount;
1511	cTicksNext += 1;
1512	cTicksNext <<= pThis->count_shift;
1513	TMTimerSetRelative(pThis->CTX_SUFF(pTimer), cTicksNext, &pThis->initial_count_load_time);
1514	pThis->next_time = pThis->initial_count_load_time + cTicksNext;
1515	pThis->fTimerArmed = true;
1516	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountArm);
1517	}
1518	else
1519	{
1520	/* Stop it if necessary and record the load time for unmasking. */
1521	if (pThis->fTimerArmed)
1522	{
1523	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountDisarm);
1524	TMTimerStop(pThis->CTX_SUFF(pTimer));
1525	pThis->fTimerArmed = false;
1526	}
1527	pThis->initial_count_load_time = TMTimerGet(pThis->CTX_SUFF(pTimer));
1528	}
1529	}
1530
1531	/**
1532	* Implementation of the 0320h access: change the LVT flags.
1533	*
1534	* @param dev The device state.
1535	* @param pThis The APIC sub-device state to operate on.
1536	* @param fNew The new flags.
1537	*/
1538	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew)
1539	{
1540	STAM_COUNTER_INC(&pThis->StatTimerSetLvt);
1541
1542	/*
1543	* Make the flag change, saving the old ones so we can avoid
1544	* unnecessary work.
1545	*/
1546	uint32_t const fOld = pThis->lvt[APIC_LVT_TIMER];
1547	pThis->lvt[APIC_LVT_TIMER] = fNew;
1548
1549	/* Only the masked and peridic bits are relevant (see apic_timer_update). */
1550	if ( (fOld & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC))
1551	!= (fNew & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC)))
1552	{
1553	/*
1554	* If changed to one-shot from periodic, stop the timer if we're not
1555	* in the first period.
1556	*/
1557	/** @todo check how clearing the periodic flag really should behave when not
1558	* in period 1. The current code just mirrors the behavior of the
1559	* original implementation. */
1560	if ( (fOld & APIC_LVT_TIMER_PERIODIC)
1561	&& !(fNew & APIC_LVT_TIMER_PERIODIC))
1562	{
1563	STAM_COUNTER_INC(&pThis->StatTimerSetLvtClearPeriodic);
1564	uint64_t cTicks = (pThis->next_time - pThis->initial_count_load_time) >> pThis->count_shift;
1565	if (cTicks >= pThis->initial_count)
1566	{
1567	/* not first period, stop it. */
1568	TMTimerStop(pThis->CTX_SUFF(pTimer));
1569	pThis->fTimerArmed = false;
1570	}
1571	/* else: first period, let it fire normally. */
1572	}
1573
1574	/*
1575	* We postpone stopping the timer when it's masked, this way we can
1576	* avoid some timer work when the guest temporarily masks the timer.
1577	* (apicTimerCallback will stop it if still masked.)
1578	*/
1579	if (fNew & APIC_LVT_MASKED)
1580	STAM_COUNTER_INC(&pThis->StatTimerSetLvtPostponed);
1581	else if (pThis->fTimerArmed)
1582	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmed);
1583	/*
1584	* If unmasked and not armed, we have to rearm the timer so it will
1585	* fire at the end of the current period.
1586	* This is code is currently RACING the virtual sync clock!
1587	*/
1588	else if (fOld & APIC_LVT_MASKED)
1589	{
1590	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArm);
1591	for (unsigned cTries = 0; ; cTries++)
1592	{
1593	uint64_t NextTS;
1594	uint64_t cTicks = (TMTimerGet(pThis->CTX_SUFF(pTimer)) - pThis->initial_count_load_time) >> pThis->count_shift;
1595	if (fNew & APIC_LVT_TIMER_PERIODIC)
1596	NextTS = ((cTicks / ((uint64_t)pThis->initial_count + 1)) + 1) * ((uint64_t)pThis->initial_count + 1);
1597	else
1598	{
1599	if (cTicks >= pThis->initial_count)
1600	break;
1601	NextTS = (uint64_t)pThis->initial_count + 1;
1602	}
1603	NextTS <<= pThis->count_shift;
1604	NextTS += pThis->initial_count_load_time;
1605
1606	/* Try avoid the assertion in TM.cpp... this isn't perfect! */
1607	if ( NextTS > TMTimerGet(pThis->CTX_SUFF(pTimer))
1608	\|\| cTries > 10)
1609	{
1610	TMTimerSet(pThis->CTX_SUFF(pTimer), NextTS);
1611	pThis->next_time = NextTS;
1612	pThis->fTimerArmed = true;
1613	break;
1614	}
1615	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmRetries);
1616	}
1617	}
1618	}
1619	else
1620	STAM_COUNTER_INC(&pThis->StatTimerSetLvtNoRelevantChange);
1621	}
1622
1623	# ifdef IN_RING3
1624	/**
1625	* Timer callback function.
1626	*
1627	* @param pDevIns The device state.
1628	* @param pTimer The timer handle.
1629	* @param pvUser User argument pointing to the APIC instance.
1630	*/
1631	static DECLCALLBACK(void) apicTimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1632	{
1633	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1634	APICState pThis = (APICState )pvUser;
1635	Assert(pThis->pTimerR3 == pTimer);
1636	Assert(pThis->fTimerArmed);
1637
1638	if (!(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1639	LogFlow(("apic_timer: trigger irq\n"));
1640	apic_set_irq(dev, pThis, pThis->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1641
1642	if (pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1643	/* new interval. */
1644	pThis->next_time += (((uint64_t)pThis->initial_count + 1) << pThis->count_shift);
1645	TMTimerSet(pThis->CTX_SUFF(pTimer), pThis->next_time);
1646	pThis->fTimerArmed = true;
1647	} else {
1648	/* single shot. */
1649	pThis->fTimerArmed = false;
1650	}
1651	} else {
1652	/* masked, do not rearm. */
1653	pThis->fTimerArmed = false;
1654	}
1655	}
1656	# endif /* IN_RING3 */
1657
1658	#endif /* VBOX */
1659
1660	#ifndef VBOX
1661	static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1662	{
1663	return 0;
1664	}
1665	static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1666	{
1667	return 0;
1668	}
1669
1670	static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1671	{
1672	}
1673
1674	static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1675	{
1676	}
1677	#endif /* !VBOX */
1678
1679
1680	#ifndef VBOX
1681	static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1682	{
1683	CPUState *env;
1684	APICState *s;
1685	#else /* VBOX */
1686	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1687	{
1688	#endif /* VBOX */
1689	uint32_t val;
1690	int index;
1691
1692	#ifndef VBOX
1693	env = cpu_single_env;
1694	if (!env)
1695	return 0;
1696	s = env->apic_state;
1697	#endif /* !VBOX */
1698
1699	index = (addr >> 4) & 0xff;
1700	switch(index) {
1701	case 0x02: /* id */
1702	val = s->id << 24;
1703	break;
1704	case 0x03: /* version */
1705	val = 0x11 \| ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1706	break;
1707	case 0x08:
1708	val = s->tpr;
1709	break;
1710	case 0x09:
1711	val = apic_get_arb_pri(s);
1712	break;
1713	case 0x0a:
1714	/* ppr */
1715	val = apic_get_ppr(s);
1716	break;
1717	case 0x0b:
1718	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1719	val = 0;
1720	break;
1721	case 0x0d:
1722	val = s->log_dest << 24;
1723	break;
1724	case 0x0e:
1725	#ifdef VBOX
1726	/* Bottom 28 bits are always 1 */
1727	val = (s->dest_mode << 28) \| 0xfffffff;
1728	#else
1729	val = s->dest_mode << 28;
1730	#endif
1731	break;
1732	case 0x0f:
1733	val = s->spurious_vec;
1734	break;
1735	#ifndef VBOX
1736	case 0x10 ... 0x17:
1737	#else /* VBOX */
1738	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1739	#endif /* VBOX */
1740	val = s->isr[index & 7];
1741	break;
1742	#ifndef VBOX
1743	case 0x18 ... 0x1f:
1744	#else /* VBOX */
1745	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1746	#endif /* VBOX */
1747	val = s->tmr[index & 7];
1748	break;
1749	#ifndef VBOX
1750	case 0x20 ... 0x27:
1751	#else /* VBOX */
1752	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1753	#endif /* VBOX */
1754	val = s->irr[index & 7];
1755	break;
1756	case 0x28:
1757	val = s->esr;
1758	break;
1759	case 0x30:
1760	case 0x31:
1761	val = s->icr[index & 1];
1762	break;
1763	#ifndef VBOX
1764	case 0x32 ... 0x37:
1765	#else /* VBOX */
1766	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1767	#endif /* VBOX */
1768	val = s->lvt[index - 0x32];
1769	break;
1770	case 0x38:
1771	val = s->initial_count;
1772	break;
1773	case 0x39:
1774	val = apic_get_current_count(dev, s);
1775	break;
1776	case 0x3e:
1777	val = s->divide_conf;
1778	break;
1779	default:
1780	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1781	s->esr \|= ESR_ILLEGAL_ADDRESS;
1782	val = 0;
1783	break;
1784	}
1785	#ifdef DEBUG_APIC
1786	Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1787	#endif
1788	return val;
1789	}
1790
1791	#ifndef VBOX
1792	static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1793	{
1794	CPUState *env;
1795	APICState *s;
1796	#else /* VBOX */
1797	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1798	{
1799	int rc = VINF_SUCCESS;
1800	#endif /* VBOX */
1801	int index;
1802
1803	#ifndef VBOX
1804	env = cpu_single_env;
1805	if (!env)
1806	return;
1807	s = env->apic_state;
1808	#endif /* !VBOX */
1809
1810	#ifdef DEBUG_APIC
1811	Log(("CPU%d: APIC write: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1812	#endif
1813
1814	index = (addr >> 4) & 0xff;
1815	switch(index) {
1816	case 0x02:
1817	s->id = (val >> 24);
1818	break;
1819	case 0x03:
1820	Log(("apic_mem_writel: write to version register; ignored\n"));
1821	break;
1822	case 0x08:
1823	#ifdef VBOX
1824	apic_update_tpr(dev, s, val);
1825	#else
1826	s->tpr = val;
1827	apic_update_irq(s);
1828	#endif
1829	break;
1830	case 0x09:
1831	case 0x0a:
1832	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1833	break;
1834	case 0x0b: /* EOI */
1835	apic_eoi(dev, s);
1836	break;
1837	case 0x0d:
1838	s->log_dest = val >> 24;
1839	break;
1840	case 0x0e:
1841	s->dest_mode = val >> 28;
1842	break;
1843	case 0x0f:
1844	s->spurious_vec = val & 0x1ff;
1845	apic_update_irq(dev, s);
1846	break;
1847	#ifndef VBOX
1848	case 0x10 ... 0x17:
1849	case 0x18 ... 0x1f:
1850	case 0x20 ... 0x27:
1851	case 0x28:
1852	#else
1853	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1854	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1855	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1856	case 0x28:
1857	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1858	#endif
1859	break;
1860
1861	case 0x30:
1862	s->icr[0] = val;
1863	rc = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1864	(s->icr[0] >> 11) & 1,
1865	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1866	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1867	break;
1868	case 0x31:
1869	s->icr[1] = val;
1870	break;
1871	#ifndef VBOX
1872	case 0x32 ... 0x37:
1873	#else /* VBOX */
1874	case 0x32 + APIC_LVT_TIMER:
1875	AssertCompile(APIC_LVT_TIMER == 0);
1876	apicTimerSetLvt(dev, s, val);
1877	break;
1878	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1879	#endif /* VBOX */
1880	{
1881	int n = index - 0x32;
1882	s->lvt[n] = val;
1883	#ifndef VBOX
1884	if (n == APIC_LVT_TIMER)
1885	apic_timer_update(s, qemu_get_clock(vm_clock));
1886	#endif /* !VBOX*/
1887	}
1888	break;
1889	case 0x38:
1890	#ifndef VBOX
1891	s->initial_count = val;
1892	s->initial_count_load_time = qemu_get_clock(vm_clock);
1893	apic_timer_update(dev, s, s->initial_count_load_time);
1894	#else /* VBOX */
1895	apicTimerSetInitialCount(dev, s, val);
1896	#endif /* VBOX*/
1897	break;
1898	case 0x39:
1899	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1900	break;
1901	case 0x3e:
1902	{
1903	int v;
1904	s->divide_conf = val & 0xb;
1905	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1906	s->count_shift = (v + 1) & 7;
1907	}
1908	break;
1909	default:
1910	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1911	s->esr \|= ESR_ILLEGAL_ADDRESS;
1912	break;
1913	}
1914	#ifdef VBOX
1915	return rc;
1916	#endif
1917	}
1918
1919	#ifdef IN_RING3
1920
1921	static void apic_save(QEMUFile f, void opaque)
1922	{
1923	APICState s = (APICState)opaque;
1924	int i;
1925
1926	qemu_put_be32s(f, &s->apicbase);
1927	#ifdef VBOX
1928	qemu_put_be32s(f, &s->id);
1929	qemu_put_be32s(f, &s->phys_id);
1930	qemu_put_be32s(f, &s->arb_id);
1931	qemu_put_be32s(f, &s->tpr);
1932	#else
1933	qemu_put_8s(f, &s->id);
1934	qemu_put_8s(f, &s->arb_id);
1935	qemu_put_8s(f, &s->tpr);
1936	#endif
1937	qemu_put_be32s(f, &s->spurious_vec);
1938	qemu_put_8s(f, &s->log_dest);
1939	qemu_put_8s(f, &s->dest_mode);
1940	for (i = 0; i < 8; i++) {
1941	qemu_put_be32s(f, &s->isr[i]);
1942	qemu_put_be32s(f, &s->tmr[i]);
1943	qemu_put_be32s(f, &s->irr[i]);
1944	}
1945	for (i = 0; i < APIC_LVT_NB; i++) {
1946	qemu_put_be32s(f, &s->lvt[i]);
1947	}
1948	qemu_put_be32s(f, &s->esr);
1949	qemu_put_be32s(f, &s->icr[0]);
1950	qemu_put_be32s(f, &s->icr[1]);
1951	qemu_put_be32s(f, &s->divide_conf);
1952	qemu_put_be32s(f, &s->count_shift);
1953	qemu_put_be32s(f, &s->initial_count);
1954	qemu_put_be64s(f, &s->initial_count_load_time);
1955	qemu_put_be64s(f, &s->next_time);
1956
1957	#ifdef VBOX
1958	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1959	#endif
1960	}
1961
1962	static int apic_load(QEMUFile f, void opaque, int version_id)
1963	{
1964	APICState s = (APICState)opaque;
1965	int i;
1966
1967	#ifdef VBOX
1968	/* XXX: what if the base changes? (registered memory regions) */
1969	qemu_get_be32s(f, &s->apicbase);
1970
1971	switch (version_id)
1972	{
1973	case APIC_SAVED_STATE_VERSION_ANCIENT:
1974	{
1975	uint8_t val = 0;
1976	qemu_get_8s(f, &val);
1977	s->id = val;
1978	/* UP only in old saved states */
1979	s->phys_id = 0;
1980	qemu_get_8s(f, &val);
1981	s->arb_id = val;
1982	break;
1983	}
1984	case APIC_SAVED_STATE_VERSION:
1985	case APIC_SAVED_STATE_VERSION_VBOX_30:
1986	qemu_get_be32s(f, &s->id);
1987	qemu_get_be32s(f, &s->phys_id);
1988	qemu_get_be32s(f, &s->arb_id);
1989	break;
1990	default:
1991	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1992	}
1993	qemu_get_be32s(f, &s->tpr);
1994	#else
1995	if (version_id != 1)
1996	return -EINVAL;
1997
1998	/* XXX: what if the base changes? (registered memory regions) */
1999	qemu_get_be32s(f, &s->apicbase);
2000	qemu_get_8s(f, &s->id);
2001	qemu_get_8s(f, &s->arb_id);
2002	qemu_get_8s(f, &s->tpr);
2003	#endif
2004	qemu_get_be32s(f, &s->spurious_vec);
2005	qemu_get_8s(f, &s->log_dest);
2006	qemu_get_8s(f, &s->dest_mode);
2007	for (i = 0; i < 8; i++) {
2008	qemu_get_be32s(f, &s->isr[i]);
2009	qemu_get_be32s(f, &s->tmr[i]);
2010	qemu_get_be32s(f, &s->irr[i]);
2011	}
2012	for (i = 0; i < APIC_LVT_NB; i++) {
2013	qemu_get_be32s(f, &s->lvt[i]);
2014	}
2015	qemu_get_be32s(f, &s->esr);
2016	qemu_get_be32s(f, &s->icr[0]);
2017	qemu_get_be32s(f, &s->icr[1]);
2018	qemu_get_be32s(f, &s->divide_conf);
2019	qemu_get_be32s(f, (uint32_t *)&s->count_shift);
2020	qemu_get_be32s(f, (uint32_t *)&s->initial_count);
2021	qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
2022	qemu_get_be64s(f, (uint64_t *)&s->next_time);
2023
2024	#ifdef VBOX
2025	int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
2026	s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
2027	#endif
2028
2029	return VINF_SUCCESS; /** @todo darn mess! */
2030	}
2031	#ifndef VBOX
2032	static void apic_reset(void *opaque)
2033	{
2034	APICState s = (APICState)opaque;
2035	apic_init_ipi(s);
2036	}
2037	#endif
2038
2039	#endif /* IN_RING3 */
2040
2041	#ifndef VBOX
2042	static CPUReadMemoryFunc *apic_mem_read[3] = {
2043	apic_mem_readb,
2044	apic_mem_readw,
2045	apic_mem_readl,
2046	};
2047
2048	static CPUWriteMemoryFunc *apic_mem_write[3] = {
2049	apic_mem_writeb,
2050	apic_mem_writew,
2051	apic_mem_writel,
2052	};
2053
2054	int apic_init(CPUState *env)
2055	{
2056	APICState *s;
2057
2058	s = qemu_mallocz(sizeof(APICState));
2059	if (!s)
2060	return -1;
2061	env->apic_state = s;
2062	apic_init_ipi(s);
2063	s->id = last_apic_id++;
2064	s->cpu_env = env;
2065	s->apicbase = 0xfee00000 \|
2066	(s->id ? 0 : MSR_IA32_APICBASE_BSP) \| MSR_IA32_APICBASE_ENABLE;
2067
2068	/* XXX: mapping more APICs at the same memory location */
2069	if (apic_io_memory == 0) {
2070	/* NOTE: the APIC is directly connected to the CPU - it is not
2071	on the global memory bus. */
2072	apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
2073	apic_mem_write, NULL);
2074	cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
2075	apic_io_memory);
2076	}
2077	s->timer = qemu_new_timer(vm_clock, apic_timer, s);
2078
2079	register_savevm("apic", 0, 1, apic_save, apic_load, s);
2080	qemu_register_reset(apic_reset, s);
2081
2082	s->next_apic = first_local_apic;
2083	first_local_apic = s;
2084
2085	return 0;
2086	}
2087	#endif /* !VBOX */
2088
2089	static void ioapic_service(IOAPICState *s)
2090	{
2091	uint8_t i;
2092	uint8_t trig_mode;
2093	uint8_t vector;
2094	uint8_t delivery_mode;
2095	uint32_t mask;
2096	uint64_t entry;
2097	uint8_t dest;
2098	uint8_t dest_mode;
2099	uint8_t polarity;
2100
2101	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2102	mask = 1 << i;
2103	if (s->irr & mask) {
2104	entry = s->ioredtbl[i];
2105	if (!(entry & APIC_LVT_MASKED)) {
2106	trig_mode = ((entry >> 15) & 1);
2107	dest = entry >> 56;
2108	dest_mode = (entry >> 11) & 1;
2109	delivery_mode = (entry >> 8) & 7;
2110	polarity = (entry >> 13) & 1;
2111	if (trig_mode == APIC_TRIGGER_EDGE)
2112	s->irr &= ~mask;
2113	if (delivery_mode == APIC_DM_EXTINT)
2114	#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
2115	vector = pic_read_irq(isa_pic);
2116	#else /* VBOX */
2117	{
2118	AssertMsgFailed(("Delivery mode ExtINT"));
2119	vector = 0xff; /* incorrect but shuts up gcc. */
2120	}
2121	#endif /* VBOX */
2122	else
2123	vector = entry & 0xff;
2124
2125	#ifndef VBOX
2126	apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
2127	delivery_mode, vector, polarity, trig_mode);
2128	#else /* VBOX */
2129	int rc = s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
2130	dest,
2131	dest_mode,
2132	delivery_mode,
2133	vector,
2134	polarity,
2135	trig_mode);
2136	/* We must be sure that attempts to reschedule in R3
2137	never get here */
2138	Assert(rc == VINF_SUCCESS);
2139	#endif /* VBOX */
2140	}
2141	}
2142	}
2143	}
2144
2145	#ifdef VBOX
2146	static
2147	#endif
2148	void ioapic_set_irq(void *opaque, int vector, int level)
2149	{
2150	IOAPICState s = (IOAPICState)opaque;
2151
2152	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
2153	uint32_t mask = 1 << vector;
2154	uint64_t entry = s->ioredtbl[vector];
2155
2156	if ((entry >> 15) & 1) {
2157	/* level triggered */
2158	if (level) {
2159	s->irr \|= mask;
2160	ioapic_service(s);
2161	#ifdef VBOX
2162	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
2163	s->irr &= ~mask;
2164	}
2165	#endif
2166	} else {
2167	s->irr &= ~mask;
2168	}
2169	} else {
2170	/* edge triggered */
2171	if (level) {
2172	s->irr \|= mask;
2173	ioapic_service(s);
2174	}
2175	}
2176	}
2177	}
2178
2179	static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
2180	{
2181	IOAPICState s = (IOAPICState)opaque;
2182	int index;
2183	uint32_t val = 0;
2184
2185	addr &= 0xff;
2186	if (addr == 0x00) {
2187	val = s->ioregsel;
2188	} else if (addr == 0x10) {
2189	switch (s->ioregsel) {
2190	case 0x00:
2191	val = s->id << 24;
2192	break;
2193	case 0x01:
2194	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
2195	break;
2196	case 0x02:
2197	val = 0;
2198	break;
2199	default:
2200	index = (s->ioregsel - 0x10) >> 1;
2201	if (index >= 0 && index < IOAPIC_NUM_PINS) {
2202	if (s->ioregsel & 1)
2203	val = s->ioredtbl[index] >> 32;
2204	else
2205	val = s->ioredtbl[index] & 0xffffffff;
2206	}
2207	}
2208	#ifdef DEBUG_IOAPIC
2209	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
2210	#endif
2211	}
2212	return val;
2213	}
2214
2215	static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2216	{
2217	IOAPICState s = (IOAPICState)opaque;
2218	int index;
2219
2220	addr &= 0xff;
2221	if (addr == 0x00) {
2222	s->ioregsel = val;
2223	return;
2224	} else if (addr == 0x10) {
2225	#ifdef DEBUG_IOAPIC
2226	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
2227	#endif
2228	switch (s->ioregsel) {
2229	case 0x00:
2230	s->id = (val >> 24) & 0xff;
2231	return;
2232	case 0x01:
2233	case 0x02:
2234	return;
2235	default:
2236	index = (s->ioregsel - 0x10) >> 1;
2237	if (index >= 0 && index < IOAPIC_NUM_PINS) {
2238	if (s->ioregsel & 1) {
2239	s->ioredtbl[index] &= 0xffffffff;
2240	s->ioredtbl[index] \|= (uint64_t)val << 32;
2241	} else {
2242	#ifdef VBOX
2243	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
2244	uint8_t vec = val & 0xff;
2245	if ((val & APIC_LVT_MASKED) \|\|
2246	((vec >= 0x10) && (vec < 0xff)))
2247	{
2248	s->ioredtbl[index] &= ~0xffffffffULL;
2249	s->ioredtbl[index] \|= val;
2250	}
2251	else
2252	{
2253	/*
2254	* Linux 2.6 kernels has pretty strange function
2255	* unlock_ExtINT_logic() which writes
2256	* absolutely bogus (all 0) value into the vector
2257	* with pretty vague explanation why.
2258	* So we just ignore such writes.
2259	*/
2260	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
2261	}
2262	}
2263	#else
2264	s->ioredtbl[index] &= ~0xffffffffULL;
2265	s->ioredtbl[index] \|= val;
2266	#endif
2267	ioapic_service(s);
2268	}
2269	}
2270	}
2271	}
2272
2273	#ifdef IN_RING3
2274
2275	static void ioapic_save(QEMUFile f, void opaque)
2276	{
2277	IOAPICState s = (IOAPICState)opaque;
2278	int i;
2279
2280	qemu_put_8s(f, &s->id);
2281	qemu_put_8s(f, &s->ioregsel);
2282	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2283	qemu_put_be64s(f, &s->ioredtbl[i]);
2284	}
2285	}
2286
2287	static int ioapic_load(QEMUFile f, void opaque, int version_id)
2288	{
2289	IOAPICState s = (IOAPICState)opaque;
2290	int i;
2291
2292	if (version_id != 1)
2293	return -EINVAL;
2294
2295	qemu_get_8s(f, &s->id);
2296	qemu_get_8s(f, &s->ioregsel);
2297	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2298	qemu_get_be64s(f, &s->ioredtbl[i]);
2299	}
2300	return 0;
2301	}
2302
2303	static void ioapic_reset(void *opaque)
2304	{
2305	IOAPICState s = (IOAPICState)opaque;
2306	#ifdef VBOX
2307	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
2308	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
2309	#endif
2310	int i;
2311
2312	memset(s, 0, sizeof(*s));
2313	for(i = 0; i < IOAPIC_NUM_PINS; i++)
2314	s->ioredtbl[i] = 1 << 16; /* mask LVT */
2315
2316	#ifdef VBOX
2317	if (pDevIns)
2318	{
2319	s->pDevInsR3 = pDevIns;
2320	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2321	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2322	}
2323	if (pIoApicHlp)
2324	{
2325	s->pIoApicHlpR3 = pIoApicHlp;
2326	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2327	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2328	}
2329	#endif
2330	}
2331
2332	#endif /* IN_RING3 */
2333
2334	#ifndef VBOX
2335	static CPUReadMemoryFunc *ioapic_mem_read[3] = {
2336	ioapic_mem_readl,
2337	ioapic_mem_readl,
2338	ioapic_mem_readl,
2339	};
2340
2341	static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
2342	ioapic_mem_writel,
2343	ioapic_mem_writel,
2344	ioapic_mem_writel,
2345	};
2346
2347	IOAPICState *ioapic_init(void)
2348	{
2349	IOAPICState *s;
2350	int io_memory;
2351
2352	s = qemu_mallocz(sizeof(IOAPICState));
2353	if (!s)
2354	return NULL;
2355	ioapic_reset(s);
2356	s->id = last_apic_id++;
2357
2358	io_memory = cpu_register_io_memory(0, ioapic_mem_read,
2359	ioapic_mem_write, s);
2360	cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
2361
2362	register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
2363	qemu_register_reset(ioapic_reset, s);
2364
2365	return s;
2366	}
2367	#endif /* !VBOX */
2368
2369	/* LAPIC */
2370	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2371	{
2372	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2373	APICState *s = getLapic(dev);
2374
2375	Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2376
2377	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
2378	different physical addresses, see #3092) */
2379
2380	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2381	switch (cb)
2382	{
2383	case 1:
2384	(uint8_t )pv = 0;
2385	break;
2386
2387	case 2:
2388	(uint16_t )pv = 0;
2389	break;
2390
2391	case 4:
2392	{
2393	#if 0 /** @note experimental */
2394	#ifndef IN_RING3
2395	uint32_t index = (GCPhysAddr >> 4) & 0xff;
2396
2397	if ( index == 0x08 /* TPR */
2398	&& ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2399	{
2400	#ifdef IN_RC
2401	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2402	#else
2403	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2404	pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2405	#endif
2406	return VINF_PATM_HC_MMIO_PATCH_READ;
2407	}
2408	#endif
2409	#endif /* experimental */
2410	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2411	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
2412	APIC_UNLOCK(dev);
2413	break;
2414	}
2415	default:
2416	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2417	return VERR_INTERNAL_ERROR;
2418	}
2419	return VINF_SUCCESS;
2420	}
2421
2422	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2423	{
2424	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2425	APICState *s = getLapic(dev);
2426
2427	Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2428
2429	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2430	different physical addresses, see #3092) */
2431
2432	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2433	switch (cb)
2434	{
2435	case 1:
2436	case 2:
2437	/* ignore */
2438	break;
2439
2440	case 4:
2441	{
2442	int rc;
2443	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2444	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2445	APIC_UNLOCK(dev);
2446	return rc;
2447	}
2448
2449	default:
2450	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2451	return VERR_INTERNAL_ERROR;
2452	}
2453	return VINF_SUCCESS;
2454	}
2455
2456	#ifdef IN_RING3
2457
2458	/* Print a 8-dword LAPIC bit map (256 bits). */
2459	static void lapicDumpVec(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp, unsigned start)
2460	{
2461	unsigned i;
2462	uint32_t val;
2463
2464	for (i = 0; i < 8; ++i)
2465	{
2466	val = apic_mem_readl(dev, lapic, start + (i << 4));
2467	pHlp->pfnPrintf(pHlp, "%08X", val);
2468	}
2469	pHlp->pfnPrintf(pHlp, "\n");
2470	}
2471
2472	/* Print basic LAPIC state. */
2473	static DECLCALLBACK(void) lapicInfoBasic(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2474	{
2475	uint32_t val;
2476	unsigned max_lvt;
2477
2478	pHlp->pfnPrintf(pHlp, "Local APIC at %08X:\n", lapic->apicbase);
2479	val = apic_mem_readl(dev, lapic, 0x20);
2480	pHlp->pfnPrintf(pHlp, " LAPIC ID : %08X\n", val);
2481	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
2482	val = apic_mem_readl(dev, lapic, 0x30);
2483	max_lvt = (val >> 16) & 0xff;
2484	pHlp->pfnPrintf(pHlp, " APIC VER : %08X\n", val);
2485	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
2486	pHlp->pfnPrintf(pHlp, " lvts = %d\n", ((val >> 16) & 0xff) + 1);
2487	val = apic_mem_readl(dev, lapic, 0x80);
2488	pHlp->pfnPrintf(pHlp, " TPR : %08X\n", val);
2489	pHlp->pfnPrintf(pHlp, " task pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2490	val = apic_mem_readl(dev, lapic, 0xA0);
2491	pHlp->pfnPrintf(pHlp, " PPR : %08X\n", val);
2492	pHlp->pfnPrintf(pHlp, " cpu pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2493	val = apic_mem_readl(dev, lapic, 0xD0);
2494	pHlp->pfnPrintf(pHlp, " LDR : %08X\n", val);
2495	pHlp->pfnPrintf(pHlp, " log id = %02X\n", (val >> 24) & 0xff);
2496	val = apic_mem_readl(dev, lapic, 0xE0);
2497	pHlp->pfnPrintf(pHlp, " DFR : %08X\n", val);
2498	val = apic_mem_readl(dev, lapic, 0xF0);
2499	pHlp->pfnPrintf(pHlp, " SVR : %08X\n", val);
2500	pHlp->pfnPrintf(pHlp, " focus = %s\n", val & (1 << 9) ? "check off" : "check on");
2501	pHlp->pfnPrintf(pHlp, " lapic = %s\n", val & (1 << 8) ? "ENABLED" : "DISABLED");
2502	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2503	pHlp->pfnPrintf(pHlp, " ISR : ");
2504	lapicDumpVec(dev, lapic, pHlp, 0x100);
2505	val = get_highest_priority_int(lapic->isr);
2506	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2507	pHlp->pfnPrintf(pHlp, " IRR : ");
2508	lapicDumpVec(dev, lapic, pHlp, 0x200);
2509	val = get_highest_priority_int(lapic->irr);
2510	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2511	val = apic_mem_readl(dev, lapic, 0x320);
2512	}
2513
2514	/* Print the more interesting LAPIC LVT entries. */
2515	static DECLCALLBACK(void) lapicInfoLVT(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2516	{
2517	uint32_t val;
2518	static const char *dmodes[] = { "Fixed ", "Reserved", "SMI", "Reserved",
2519	"NMI", "INIT", "Reserved", "ExtINT" };
2520
2521	val = apic_mem_readl(dev, lapic, 0x320);
2522	pHlp->pfnPrintf(pHlp, " LVT Timer : %08X\n", val);
2523	pHlp->pfnPrintf(pHlp, " mode = %s\n", val & (1 << 17) ? "periodic" : "one-shot");
2524	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2525	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2526	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2527	val = apic_mem_readl(dev, lapic, 0x350);
2528	pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08X\n", val);
2529	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2530	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2531	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2532	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2533	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2534	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2535	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2536	val = apic_mem_readl(dev, lapic, 0x360);
2537	pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08X\n", val);
2538	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2539	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2540	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2541	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2542	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2543	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2544	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2545	}
2546
2547	/* Print LAPIC timer state. */
2548	static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2549	{
2550	uint32_t val;
2551	unsigned divider;
2552
2553	pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
2554	val = apic_mem_readl(dev, lapic, 0x380);
2555	pHlp->pfnPrintf(pHlp, " Initial count : %08X\n", val);
2556	val = apic_mem_readl(dev, lapic, 0x390);
2557	pHlp->pfnPrintf(pHlp, " Current count : %08X\n", val);
2558	val = apic_mem_readl(dev, lapic, 0x3E0);
2559	pHlp->pfnPrintf(pHlp, " Divide config : %08X\n", val);
2560	divider = ((val >> 1) & 0x04) \| (val & 0x03);
2561	pHlp->pfnPrintf(pHlp, " divider = %d\n", divider == 7 ? 1 : 2 << divider);
2562	}
2563
2564	/**
2565	* Info handler, device version. Dumps Local APIC(s) state according to given argument.
2566	*
2567	* @param pDevIns Device instance which registered the info.
2568	* @param pHlp Callback functions for doing output.
2569	* @param pszArgs Argument string. Optional.
2570	*/
2571	static DECLCALLBACK(void) lapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2572	{
2573	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2574	APICState *lapic;
2575
2576	lapic = getLapic(dev);
2577
2578	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2579	{
2580	lapicInfoBasic(dev, lapic, pHlp);
2581	}
2582	else if (!strcmp(pszArgs, "lvt"))
2583	{
2584	lapicInfoLVT(dev, lapic, pHlp);
2585	}
2586	else if (!strcmp(pszArgs, "timer"))
2587	{
2588	lapicInfoTimer(dev, lapic, pHlp);
2589	}
2590	else
2591	{
2592	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
2593	}
2594	}
2595
2596	/**
2597	* @copydoc FNSSMDEVLIVEEXEC
2598	*/
2599	static DECLCALLBACK(int) apicLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
2600	{
2601	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2602
2603	SSMR3PutU32( pSSM, pThis->cCpus);
2604	SSMR3PutBool(pSSM, pThis->fIoApic);
2605	SSMR3PutU32( pSSM, pThis->enmVersion);
2606	AssertCompile(PDMAPICVERSION_APIC == 2);
2607
2608	return VINF_SSM_DONT_CALL_AGAIN;
2609	}
2610
2611	/**
2612	* @copydoc FNSSMDEVSAVEEXEC
2613	*/
2614	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2615	{
2616	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2617
2618	/* config */
2619	apicLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
2620
2621	/* save all APICs data, @todo: is it correct? */
2622	foreach_apic(dev, 0xffffffff, apic_save(pSSM, apic));
2623
2624	return VINF_SUCCESS;
2625	}
2626
2627	/**
2628	* @copydoc FNSSMDEVLOADEXEC
2629	*/
2630	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2631	{
2632	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2633
2634	if ( uVersion != APIC_SAVED_STATE_VERSION
2635	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
2636	&& uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
2637	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2638
2639	/* config */
2640	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30) {
2641	uint32_t cCpus;
2642	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2643	if (cCpus != pThis->cCpus)
2644	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pThis->cCpus);
2645	bool fIoApic;
2646	rc = SSMR3GetBool(pSSM, &fIoApic); AssertRCReturn(rc, rc);
2647	if (fIoApic != pThis->fIoApic)
2648	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pThis->fIoApic);
2649	uint32_t uApicVersion;
2650	rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
2651	if (uApicVersion != (uint32_t)pThis->enmVersion)
2652	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pThis->enmVersion);
2653	}
2654
2655	if (uPass != SSM_PASS_FINAL)
2656	return VINF_SUCCESS;
2657
2658	/* load all APICs data / /* @todo: is it correct? */
2659	foreach_apic(pThis, 0xffffffff,
2660	if (apic_load(pSSM, apic, uVersion)) {
2661	AssertFailed();
2662	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2663	}
2664	);
2665	return VINF_SUCCESS;
2666	}
2667
2668	/**
2669	* @copydoc FNPDMDEVRESET
2670	*/
2671	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2672	{
2673	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2674	unsigned i;
2675
2676	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2677
2678	/* Reset all APICs. */
2679	for (i = 0; i < dev->cCpus; i++) {
2680	APICState *pApic = &dev->CTX_SUFF(paLapics)[i];
2681	TMTimerStop(pApic->CTX_SUFF(pTimer));
2682
2683	/* Clear LAPIC state as if an INIT IPI was sent. */
2684	apic_init_ipi(dev, pApic);
2685	/* The IDs are not touched by apic_init_ipi() and must be reset now. */
2686	pApic->arb_id = pApic->id = i;
2687	Assert(pApic->id == pApic->phys_id); /* The two should match again. */
2688	/* Reset should re-enable the APIC. */
2689	pApic->apicbase = 0xfee00000 \| MSR_IA32_APICBASE_ENABLE;
2690	if (pApic->phys_id == 0)
2691	pApic->apicbase \|= MSR_IA32_APICBASE_BSP;
2692
2693	/* Clear any pending APIC interrupt action flag. */
2694	cpuClearInterrupt(dev, pApic);
2695	}
2696	/** @todo r=bird: Why is this done everytime, while the constructor first
2697	* checks the CPUID? Who is right? */
2698	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2699
2700	APIC_UNLOCK(dev);
2701	}
2702
2703	/**
2704	* @copydoc FNPDMDEVRELOCATE
2705	*/
2706	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2707	{
2708	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2709	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2710	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2711	pThis->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pThis->paLapicsR3);
2712	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2713	for (uint32_t i = 0; i < pThis->cCpus; i++)
2714	pThis->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pThis->paLapicsR3[i].pTimerR3);
2715	}
2716
2717	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2718	{
2719	int i;
2720	memset(apic, 0, sizeof(*apic));
2721	apic->apicbase = UINT32_C(0xfee00000) \| MSR_IA32_APICBASE_ENABLE;
2722	/* Mark first CPU as BSP */
2723	if (id == 0)
2724	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2725	for (i = 0; i < APIC_LVT_NB; i++)
2726	apic->lvt[i] = 1 << 16; /* mask LVT */
2727	apic->spurious_vec = 0xff;
2728	apic->phys_id = apic->id = id;
2729	}
2730
2731	/**
2732	* @copydoc FNPDMDEVCONSTRUCT
2733	*/
2734	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2735	{
2736	PDMAPICREG ApicReg;
2737	int rc;
2738	uint32_t i;
2739	bool fIoApic;
2740	bool fGCEnabled;
2741	bool fR0Enabled;
2742	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2743	uint32_t cCpus;
2744
2745	/*
2746	* Only single device instance.
2747	*/
2748	Assert(iInstance == 0);
2749
2750	/*
2751	* Validate configuration.
2752	*/
2753	if (!CFGMR3AreValuesValid(pCfgHandle,
2754	"IOAPIC\0"
2755	"GCEnabled\0"
2756	"R0Enabled\0"
2757	"NumCPUs\0"))
2758	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2759
2760	rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIoApic, true);
2761	if (RT_FAILURE(rc))
2762	return PDMDEV_SET_ERROR(pDevIns, rc,
2763	N_("Configuration error: Failed to read \"IOAPIC\""));
2764
2765	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2766	if (RT_FAILURE(rc))
2767	return PDMDEV_SET_ERROR(pDevIns, rc,
2768	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2769
2770	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2771	if (RT_FAILURE(rc))
2772	return PDMDEV_SET_ERROR(pDevIns, rc,
2773	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2774
2775	rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2776	if (RT_FAILURE(rc))
2777	return PDMDEV_SET_ERROR(pDevIns, rc,
2778	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2779
2780	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIoApic));
2781
2782	/** @todo Current implementation is limited to 32 CPUs due to the use of 32
2783	* bits bitmasks. */
2784	if (cCpus > 32)
2785	return PDMDEV_SET_ERROR(pDevIns, rc,
2786	N_("Configuration error: Invalid value for \"NumCPUs\""));
2787
2788	/*
2789	* Init the data.
2790	*/
2791	pThis->pDevInsR3 = pDevIns;
2792	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2793	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2794	pThis->cCpus = cCpus;
2795	pThis->fIoApic = fIoApic;
2796	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2797	pThis->enmVersion = PDMAPICVERSION_APIC;
2798
2799	PVM pVM = PDMDevHlpGetVM(pDevIns);
2800	/*
2801	* We are not freeing this memory, as it's automatically released when guest exits.
2802	*/
2803	rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->paLapicsR3);
2804	if (RT_FAILURE(rc))
2805	return VERR_NO_MEMORY;
2806	pThis->paLapicsR0 = MMHyperR3ToR0(pVM, pThis->paLapicsR3);
2807	pThis->paLapicsRC = MMHyperR3ToRC(pVM, pThis->paLapicsR3);
2808
2809	for (i = 0; i < cCpus; i++)
2810	initApicData(&pThis->paLapicsR3[i], i);
2811
2812	/*
2813	* Register the APIC.
2814	*/
2815	ApicReg.u32Version = PDM_APICREG_VERSION;
2816	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2817	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2818	ApicReg.pfnSetBaseR3 = apicSetBase;
2819	ApicReg.pfnGetBaseR3 = apicGetBase;
2820	ApicReg.pfnSetTPRR3 = apicSetTPR;
2821	ApicReg.pfnGetTPRR3 = apicGetTPR;
2822	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2823	ApicReg.pfnReadMSRR3 = apicReadMSR;
2824	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2825	ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
2826	if (fGCEnabled) {
2827	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2828	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2829	ApicReg.pszSetBaseRC = "apicSetBase";
2830	ApicReg.pszGetBaseRC = "apicGetBase";
2831	ApicReg.pszSetTPRRC = "apicSetTPR";
2832	ApicReg.pszGetTPRRC = "apicGetTPR";
2833	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2834	ApicReg.pszReadMSRRC = "apicReadMSR";
2835	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2836	ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
2837	} else {
2838	ApicReg.pszGetInterruptRC = NULL;
2839	ApicReg.pszHasPendingIrqRC = NULL;
2840	ApicReg.pszSetBaseRC = NULL;
2841	ApicReg.pszGetBaseRC = NULL;
2842	ApicReg.pszSetTPRRC = NULL;
2843	ApicReg.pszGetTPRRC = NULL;
2844	ApicReg.pszWriteMSRRC = NULL;
2845	ApicReg.pszReadMSRRC = NULL;
2846	ApicReg.pszBusDeliverRC = NULL;
2847	ApicReg.pszLocalInterruptRC = NULL;
2848	}
2849	if (fR0Enabled) {
2850	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2851	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2852	ApicReg.pszSetBaseR0 = "apicSetBase";
2853	ApicReg.pszGetBaseR0 = "apicGetBase";
2854	ApicReg.pszSetTPRR0 = "apicSetTPR";
2855	ApicReg.pszGetTPRR0 = "apicGetTPR";
2856	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2857	ApicReg.pszReadMSRR0 = "apicReadMSR";
2858	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2859	ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
2860	} else {
2861	ApicReg.pszGetInterruptR0 = NULL;
2862	ApicReg.pszHasPendingIrqR0 = NULL;
2863	ApicReg.pszSetBaseR0 = NULL;
2864	ApicReg.pszGetBaseR0 = NULL;
2865	ApicReg.pszSetTPRR0 = NULL;
2866	ApicReg.pszGetTPRR0 = NULL;
2867	ApicReg.pszWriteMSRR0 = NULL;
2868	ApicReg.pszReadMSRR0 = NULL;
2869	ApicReg.pszBusDeliverR0 = NULL;
2870	ApicReg.pszLocalInterruptR0 = NULL;
2871	}
2872
2873	Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2874	rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2875	AssertLogRelRCReturn(rc, rc);
2876	pThis->pCritSectR3 = pThis->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2877
2878	/*
2879	* The the CPUID feature bit.
2880	*/
2881	/** @todo r=bird: See remark in the apicReset. */
2882	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2883	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2884	if (u32Eax >= 1) {
2885	if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
2886	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2887	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2888	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2889	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2890	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2891	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */)) {
2892	LogRel(("Activating Local APIC\n"));
2893	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2894	}
2895	}
2896
2897	/*
2898	* Register the MMIO range.
2899	*/
2900	uint32_t ApicBase = pThis->paLapicsR3[0].apicbase & ~0xfff;
2901	rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pThis,
2902	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2903	if (RT_FAILURE(rc))
2904	return rc;
2905
2906	if (fGCEnabled) {
2907	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2908	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2909
2910	rc = PDMDevHlpMMIORegisterGC(pDevIns, ApicBase, 0x1000, 0,
2911	"apicMMIOWrite", "apicMMIORead", NULL);
2912	if (RT_FAILURE(rc))
2913	return rc;
2914	}
2915
2916	if (fR0Enabled) {
2917	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2918	pThis->pCritSectR0 = pThis->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2919
2920	rc = PDMDevHlpMMIORegisterR0(pDevIns, ApicBase, 0x1000, 0,
2921	"apicMMIOWrite", "apicMMIORead", NULL);
2922	if (RT_FAILURE(rc))
2923	return rc;
2924	}
2925
2926	/*
2927	* Create the APIC timers.
2928	*/
2929	for (i = 0; i < cCpus; i++) {
2930	APICState *pApic = &pThis->paLapicsR3[i];
2931	pApic->pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_USER, "APIC Timer #%u", i);
2932	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimerCallback, pApic,
2933	TMTIMER_FLAGS_NO_CRIT_SECT, pApic->pszDesc, &pApic->pTimerR3);
2934	if (RT_FAILURE(rc))
2935	return rc;
2936	pApic->pTimerR0 = TMTimerR0Ptr(pApic->pTimerR3);
2937	pApic->pTimerRC = TMTimerRCPtr(pApic->pTimerR3);
2938	TMR3TimerSetCritSect(pApic->pTimerR3, pThis->pCritSectR3);
2939	}
2940
2941	/*
2942	* Saved state.
2943	*/
2944	rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pThis),
2945	apicLiveExec, apicSaveExec, apicLoadExec);
2946	if (RT_FAILURE(rc))
2947	return rc;
2948
2949	/*
2950	* Register debugger info callback.
2951	*/
2952	PDMDevHlpDBGFInfoRegister(pDevIns, "lapic", "Display Local APIC state for current CPU. "
2953	"Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", lapicInfo);
2954
2955	#ifdef VBOX_WITH_STATISTICS
2956	/*
2957	* Statistics.
2958	*/
2959	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2960	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2961	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2962	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2963	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2964	for (i = 0; i < cCpus; i++) {
2965	APICState *pApic = &pThis->paLapicsR3[i];
2966	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
2967	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
2968	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
2969	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
2970	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
2971	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
2972	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
2973	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
2974	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
2975	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
2976	}
2977	#endif
2978
2979	return VINF_SUCCESS;
2980	}
2981
2982
2983	/**
2984	* APIC device registration structure.
2985	*/
2986	const PDMDEVREG g_DeviceAPIC =
2987	{
2988	/* u32Version */
2989	PDM_DEVREG_VERSION,
2990	/* szDeviceName */
2991	"apic",
2992	/* szRCMod */
2993	"VBoxDD2GC.gc",
2994	/* szR0Mod */
2995	"VBoxDD2R0.r0",
2996	/* pszDescription */
2997	"Advanced Programmable Interrupt Controller (APIC) Device",
2998	/* fFlags */
2999	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3000	/* fClass */
3001	PDM_DEVREG_CLASS_PIC,
3002	/* cMaxInstances */
3003	1,
3004	/* cbInstance */
3005	sizeof(APICState),
3006	/* pfnConstruct */
3007	apicConstruct,
3008	/* pfnDestruct */
3009	NULL,
3010	/* pfnRelocate */
3011	apicRelocate,
3012	/* pfnIOCtl */
3013	NULL,
3014	/* pfnPowerOn */
3015	NULL,
3016	/* pfnReset */
3017	apicReset,
3018	/* pfnSuspend */
3019	NULL,
3020	/* pfnResume */
3021	NULL,
3022	/* pfnAttach */
3023	NULL,
3024	/* pfnDetach */
3025	NULL,
3026	/* pfnQueryInterface. */
3027	NULL,
3028	/* pfnInitComplete */
3029	NULL,
3030	/* pfnPowerOff */
3031	NULL,
3032	/* pfnSoftReset */
3033	NULL,
3034	/* u32VersionEnd */
3035	PDM_DEVREG_VERSION
3036	};
3037
3038	#endif /* IN_RING3 */
3039
3040
3041	/* IOAPIC */
3042
3043	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3044	{
3045	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3046	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
3047
3048	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
3049	switch (cb) {
3050	case 1:
3051	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3052	break;
3053
3054	case 2:
3055	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3056	break;
3057
3058	case 4:
3059	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
3060	break;
3061
3062	default:
3063	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3064	IOAPIC_UNLOCK(s);
3065	return VERR_INTERNAL_ERROR;
3066	}
3067	IOAPIC_UNLOCK(s);
3068	return VINF_SUCCESS;
3069	}
3070
3071	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3072	{
3073	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3074
3075	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
3076	switch (cb) {
3077	case 1:
3078	case 2:
3079	case 4:
3080	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
3081	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
3082	IOAPIC_UNLOCK(s);
3083	break;
3084
3085	default:
3086	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3087	return VERR_INTERNAL_ERROR;
3088	}
3089	return VINF_SUCCESS;
3090	}
3091
3092	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
3093	{
3094	/* PDM lock is taken here; @todo add assertion */
3095	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
3096	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
3097	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
3098	ioapic_set_irq(pThis, iIrq, iLevel);
3099	}
3100
3101
3102	#ifdef IN_RING3
3103
3104	/**
3105	* Info handler, device version. Dumps I/O APIC state.
3106	*
3107	* @param pDevIns Device instance which registered the info.
3108	* @param pHlp Callback functions for doing output.
3109	* @param pszArgs Argument string. Optional and specific to the handler.
3110	*/
3111	static DECLCALLBACK(void) ioapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3112	{
3113	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3114	uint32_t val;
3115	unsigned i;
3116	unsigned max_redir;
3117
3118	pHlp->pfnPrintf(pHlp, "I/O APIC at %08X:\n", 0xfec00000);
3119	val = s->id << 24; /* Would be nice to call ioapic_mem_readl() directly, but that's not so simple. */
3120	pHlp->pfnPrintf(pHlp, " IOAPICID : %08X\n", val);
3121	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
3122	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16);
3123	max_redir = (val >> 16) & 0xff;
3124	pHlp->pfnPrintf(pHlp, " IOAPICVER : %08X\n", val);
3125	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
3126	pHlp->pfnPrintf(pHlp, " redirs = %d\n", ((val >> 16) & 0xff) + 1);
3127	val = 0;
3128	pHlp->pfnPrintf(pHlp, " IOAPICARB : %08X\n", val);
3129	pHlp->pfnPrintf(pHlp, " arb ID = %02X\n", (val >> 24) & 0xff);
3130	Assert(sizeof(s->ioredtbl) / sizeof(s->ioredtbl[0]) > max_redir);
3131	pHlp->pfnPrintf(pHlp, "I/O redirection table\n");
3132	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
3133	for (i = 0; i <= max_redir; ++i)
3134	{
3135	static const char *dmodes[] = { "Fixed ", "LowPri", "SMI ", "Resrvd",
3136	"NMI ", "INIT ", "Resrvd", "ExtINT" };
3137
3138	pHlp->pfnPrintf(pHlp, " %02d %s %02X %d %s %d %s %s %s %3d (%016llX)\n",
3139	i,
3140	s->ioredtbl[i] & (1 << 11) ? "log " : "phys", /* dest mode */
3141	(int)(s->ioredtbl[i] >> 56), /* dest addr */
3142	(int)(s->ioredtbl[i] >> 16) & 1, /* mask */
3143	s->ioredtbl[i] & (1 << 15) ? "level" : "edge ", /* trigger */
3144	(int)(s->ioredtbl[i] >> 14) & 1, /* remote IRR */
3145	s->ioredtbl[i] & (1 << 13) ? "activelo" : "activehi", /* polarity */
3146	s->ioredtbl[i] & (1 << 12) ? "pend" : "idle", /* delivery status */
3147	dmodes[(s->ioredtbl[i] >> 8) & 0x07], /* delivery mode */
3148	(int)s->ioredtbl[i] & 0xff, /* vector */
3149	s->ioredtbl[i] /* entire register */
3150	);
3151	}
3152	}
3153
3154	/**
3155	* @copydoc FNSSMDEVSAVEEXEC
3156	*/
3157	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3158	{
3159	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3160	ioapic_save(pSSM, s);
3161	return VINF_SUCCESS;
3162	}
3163
3164	/**
3165	* @copydoc FNSSMDEVLOADEXEC
3166	*/
3167	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3168	{
3169	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3170
3171	if (ioapic_load(pSSM, s, uVersion)) {
3172	AssertFailed();
3173	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3174	}
3175	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3176
3177	return VINF_SUCCESS;
3178	}
3179
3180	/**
3181	* @copydoc FNPDMDEVRESET
3182	*/
3183	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
3184	{
3185	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3186	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
3187	ioapic_reset(s);
3188	IOAPIC_UNLOCK(s);
3189	}
3190
3191	/**
3192	* @copydoc FNPDMDEVRELOCATE
3193	*/
3194	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
3195	{
3196	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3197	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3198	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
3199	}
3200
3201	/**
3202	* @copydoc FNPDMDEVCONSTRUCT
3203	*/
3204	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
3205	{
3206	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
3207	PDMIOAPICREG IoApicReg;
3208	bool fGCEnabled;
3209	bool fR0Enabled;
3210	int rc;
3211
3212	Assert(iInstance == 0);
3213
3214	/*
3215	* Validate and read the configuration.
3216	*/
3217	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
3218	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
3219
3220	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
3221	if (RT_FAILURE(rc))
3222	return PDMDEV_SET_ERROR(pDevIns, rc,
3223	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
3224
3225	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
3226	if (RT_FAILURE(rc))
3227	return PDMDEV_SET_ERROR(pDevIns, rc,
3228	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
3229	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
3230
3231	/*
3232	* Initialize the state data.
3233	*/
3234	s->pDevInsR3 = pDevIns;
3235	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3236	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3237	ioapic_reset(s);
3238	s->id = 0;
3239
3240	/*
3241	* Register the IOAPIC and get helpers.
3242	*/
3243	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
3244	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
3245	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
3246	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
3247	rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
3248	if (RT_FAILURE(rc))
3249	{
3250	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
3251	return rc;
3252	}
3253
3254	/*
3255	* Register MMIO callbacks and saved state.
3256	*/
3257	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
3258	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
3259	if (RT_FAILURE(rc))
3260	return rc;
3261
3262	if (fGCEnabled) {
3263	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
3264
3265	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
3266	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
3267	if (RT_FAILURE(rc))
3268	return rc;
3269	}
3270
3271	if (fR0Enabled) {
3272	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
3273
3274	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
3275	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
3276	if (RT_FAILURE(rc))
3277	return rc;
3278	}
3279
3280	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* version /, sizeof(s), ioapicSaveExec, ioapicLoadExec);
3281	if (RT_FAILURE(rc))
3282	return rc;
3283
3284	/*
3285	* Register debugger info callback.
3286	*/
3287	PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display I/O APIC state.", ioapicInfo);
3288
3289	#ifdef VBOX_WITH_STATISTICS
3290	/*
3291	* Statistics.
3292	*/
3293	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
3294	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
3295	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
3296	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
3297	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
3298	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
3299	#endif
3300
3301	return VINF_SUCCESS;
3302	}
3303
3304	/**
3305	* IO APIC device registration structure.
3306	*/
3307	const PDMDEVREG g_DeviceIOAPIC =
3308	{
3309	/* u32Version */
3310	PDM_DEVREG_VERSION,
3311	/* szDeviceName */
3312	"ioapic",
3313	/* szRCMod */
3314	"VBoxDD2GC.gc",
3315	/* szR0Mod */
3316	"VBoxDD2R0.r0",
3317	/* pszDescription */
3318	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
3319	/* fFlags */
3320	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
3321	/* fClass */
3322	PDM_DEVREG_CLASS_PIC,
3323	/* cMaxInstances */
3324	1,
3325	/* cbInstance */
3326	sizeof(IOAPICState),
3327	/* pfnConstruct */
3328	ioapicConstruct,
3329	/* pfnDestruct */
3330	NULL,
3331	/* pfnRelocate */
3332	ioapicRelocate,
3333	/* pfnIOCtl */
3334	NULL,
3335	/* pfnPowerOn */
3336	NULL,
3337	/* pfnReset */
3338	ioapicReset,
3339	/* pfnSuspend */
3340	NULL,
3341	/* pfnResume */
3342	NULL,
3343	/* pfnAttach */
3344	NULL,
3345	/* pfnDetach */
3346	NULL,
3347	/* pfnQueryInterface. */
3348	NULL,
3349	/* pfnInitComplete */
3350	NULL,
3351	/* pfnPowerOff */
3352	NULL,
3353	/* pfnSoftReset */
3354	NULL,
3355	/* u32VersionEnd */
3356	PDM_DEVREG_VERSION
3357	};
3358
3359	#endif /* IN_RING3 */
3360	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 24873

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