DevDMA.cpp@ 47928

Last change on this file since 47928 was 46499, checked in by vboxsync, 12 years ago
DevDMA: Set TC status bit on transfer completion.
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1	/* $Id: DevDMA.cpp 46499 2013-06-11 15:54:48Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_DMA
47	#include <VBox/vmm/pdmdev.h>
48	#include <VBox/err.h>
49
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include <stdio.h>
55	#include <stdlib.h>
56
57	#include "VBoxDD.h"
58
59
60	/** @page pg_dev_dma DMA Overview and notes
61	*
62	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
63	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
64	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
65	* 74LS612 extends addressing to 24 bits. That leads to well known and
66	* inconvenient DMA limitations:
67	* - DMA can only access physical memory under the 16MB line
68	* - DMA transfers must occur within a 64KB/128KB 'page'
69	*
70	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
71	* left by one, including the control registers addresses. The DMA register
72	* offsets (except for the page registers) are therefore "double spaced".
73	*
74	* Due to the address shifting, the DMA controller decodes more addresses
75	* than are usually documented, with aliasing. See the ICH8 datasheet.
76	*
77	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
78	* preventing the use of memory-to-memory DMA transfers (which use channels
79	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
80	* However, it would transfer a single byte at a time, while the CPU can
81	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
82	* compatibles, memory-to-memory DMA is not even implemented at all, and
83	* therefore has no practical use.
84	*
85	* Auto-init mode is handled implicitly; a device's transfer handler may
86	* return an end count lower than the start count.
87	*
88	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
89	* while 'chidx' refers to a DMA channel index within a controller (0-3).
90	*
91	* References:
92	* - IBM Personal Computer AT Technical Reference, 1984
93	* - Intel 8237A-5 Datasheet, 1993
94	* - Frank van Gilluwe, The Undocumented PC, 1994
95	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
96	* - Intel ICH8 Datasheet, 2007
97	*/
98
99
100	/* Saved state versions. */
101	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
102	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
103
104	/* State information for a single DMA channel. */
105	typedef struct {
106	void pvUser; / User specific context. */
107	PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
108	uint16_t u16BaseAddr; /* Base address for transfers. */
109	uint16_t u16BaseCount; /* Base count for transfers. */
110	uint16_t u16CurAddr; /* Current address. */
111	uint16_t u16CurCount; /* Current count. */
112	uint8_t u8Mode; /* Channel mode. */
113	} DMAChannel;
114
115	/* State information for a DMA controller (DMA8 or DMA16). */
116	typedef struct {
117	DMAChannel ChState[4]; /* Per-channel state. */
118	uint8_t au8Page[8]; /* Page registers (A16-A23). */
119	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
120	uint8_t u8Command; /* Command register. */
121	uint8_t u8Status; /* Status register. */
122	uint8_t u8Mask; /* Mask register. */
123	uint8_t u8Temp; /* Temporary (mem/mem) register. */
124	uint8_t u8ModeCtr; /* Mode register counter for reads. */
125	bool fHiByte; /* Byte pointer (T/F -> high/low). */
126	uint32_t is16bit; /* True for 16-bit DMA. */
127	} DMAControl;
128
129	/* Complete DMA state information. */
130	typedef struct {
131	PPDMDEVINS pDevIns; /* Device instance. */
132	PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
133	DMAControl DMAC[2]; /* Two DMA controllers. */
134	} DMAState;
135
136	/* DMA command register bits. */
137	enum {
138	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
139	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
140	CMD_DISABLE = 0x04, /* Disable controller. */
141	CMD_COMPRTIME = 0x08, /* Compressed timing. */
142	CMD_ROTPRIO = 0x10, /* Rotating priority. */
143	CMD_EXTWR = 0x20, /* Extended write. */
144	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
145	CMD_DACKHI = 0x80, /* DACK is active high if set. */
146	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
147	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
148	};
149
150	/* DMA control register offsets for read accesses. */
151	enum {
152	CTL_R_STAT, /* Read status registers. */
153	CTL_R_DMAREQ, /* Read DRQ register. */
154	CTL_R_CMD, /* Read command register. */
155	CTL_R_MODE, /* Read mode register. */
156	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
157	CTL_R_TEMP, /* Read temporary register. */
158	CTL_R_CLRMODE, /* Clear mode register counter. */
159	CTL_R_MASK /* Read all DRQ mask bits. */
160	};
161
162	/* DMA control register offsets for read accesses. */
163	enum {
164	CTL_W_CMD, /* Write command register. */
165	CTL_W_DMAREQ, /* Write DRQ register. */
166	CTL_W_MASKONE, /* Write single DRQ mask bit. */
167	CTL_W_MODE, /* Write mode register. */
168	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
169	CTL_W_MASTRCLR, /* Master clear. */
170	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
171	CTL_W_MASK /* Write all DRQ mask bits. */
172	};
173
174	/* DMA transfer modes. */
175	enum {
176	DMODE_DEMAND, /* Demand transfer mode. */
177	DMODE_SINGLE, /* Single transfer mode. */
178	DMODE_BLOCK, /* Block transfer mode. */
179	DMODE_CASCADE /* Cascade mode. */
180	};
181
182	/* Convert DMA channel number (0-7) to controller number (0-1). */
183	#define DMACH2C(c) (c < 4 ? 0 : 1)
184
185	static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
186	/* Map a DMA page register offset (0-7) to channel index (0-3). */
187	#define DMAPG2CX(c) (dmaChannelMap[c])
188
189	static int dmaMapChannel[4] = {7, 3, 1, 2};
190	/* Map a channel index (0-3) to DMA page register offset (0-7). */
191	#define DMACX2PG(c) (dmaMapChannel[c])
192	/* Map a channel number (0-7) to DMA page register offset (0-7). */
193	#define DMACH2PG(c) (dmaMapChannel[c & 3])
194
195	/* Test the decrement bit of mode register. */
196	#define IS_MODE_DEC(c) ((c) & 0x20)
197	/* Test the auto-init bit of mode register. */
198	#define IS_MODE_AI(c) ((c) & 0x10)
199
200	/* Perform a master clear (reset) on a DMA controller. */
201	static void dmaClear(DMAControl *dc)
202	{
203	dc->u8Command = 0;
204	dc->u8Status = 0;
205	dc->u8Temp = 0;
206	dc->u8ModeCtr = 0;
207	dc->fHiByte = false;
208	dc->u8Mask = ~0;
209	}
210
211	/* Read the byte pointer and flip it. */
212	static inline bool dmaReadBytePtr(DMAControl *dc)
213	{
214	bool bHighByte;
215
216	bHighByte = !!dc->fHiByte;
217	dc->fHiByte ^= 1;
218	return bHighByte;
219	}
220
221	/* DMA address registers writes and reads. */
222
223	static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
224	{
225	if (cb == 1)
226	{
227	DMAControl dc = (DMAControl )pvUser;
228	DMAChannel *ch;
229	int chidx, reg, is_count;
230
231	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
232	reg = (port >> dc->is16bit) & 0x0f;
233	chidx = reg >> 1;
234	is_count = reg & 1;
235	ch = &dc->ChState[chidx];
236	if (dmaReadBytePtr(dc))
237	{
238	/* Write the high byte. */
239	if (is_count)
240	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
241	else
242	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
243
244	ch->u16CurCount = 0;
245	ch->u16CurAddr = ch->u16BaseAddr;
246	}
247	else
248	{
249	/* Write the low byte. */
250	if (is_count)
251	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
252	else
253	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
254	}
255	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
256	port, chidx, u32));
257	}
258	else
259	{
260	/* Likely a guest bug. */
261	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
262	port, cb, u32));
263	}
264	return VINF_SUCCESS;
265	}
266
267	static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
268	{
269	if (cb == 1)
270	{
271	DMAControl dc = (DMAControl )pvUser;
272	DMAChannel *ch;
273	int chidx, reg, val, dir;
274	int bptr;
275
276	reg = (port >> dc->is16bit) & 0x0f;
277	chidx = reg >> 1;
278	ch = &dc->ChState[chidx];
279
280	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
281	if (reg & 1)
282	val = ch->u16BaseCount - ch->u16CurCount;
283	else
284	val = ch->u16CurAddr + ch->u16CurCount * dir;
285
286	bptr = dmaReadBytePtr(dc);
287	pu32 = RT_LOBYTE(val >> (bptr 8));
288
289	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
290	return VINF_SUCCESS;
291	}
292	else
293	return VERR_IOM_IOPORT_UNUSED;
294	}
295
296	/* DMA control registers writes and reads. */
297
298	static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
299	uint32_t u32, unsigned cb)
300	{
301	if (cb == 1)
302	{
303	DMAControl dc = (DMAControl )pvUser;
304	int chidx = 0;
305	int reg;
306
307	reg = ((port >> dc->is16bit) & 0x0f) - 8;
308	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
309	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
310
311	switch (reg) {
312	case CTL_W_CMD:
313	/* Unsupported commands are entirely ignored. */
314	if (u32 & CMD_UNSUPPORTED)
315	{
316	Log(("DMA command %#x is not supported, ignoring!\n", u32));
317	break;
318	}
319	dc->u8Command = u32;
320	break;
321	case CTL_W_DMAREQ:
322	chidx = u32 & 3;
323	if (u32 & 4)
324	dc->u8Status \|= 1 << (chidx + 4);
325	else
326	dc->u8Status &= ~(1 << (chidx + 4));
327	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
328	break;
329	case CTL_W_MASKONE:
330	chidx = u32 & 3;
331	if (u32 & 4)
332	dc->u8Mask \|= 1 << chidx;
333	else
334	dc->u8Mask &= ~(1 << chidx);
335	break;
336	case CTL_W_MODE:
337	{
338	int op, opmode;
339
340	chidx = u32 & 3;
341	op = (u32 >> 2) & 3;
342	opmode = (u32 >> 6) & 3;
343	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
344	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
345	IS_MODE_DEC(u32) ? "de" : "in", opmode));
346
347	dc->ChState[chidx].u8Mode = u32;
348	break;
349	}
350	case CTL_W_CLRBPTR:
351	dc->fHiByte = false;
352	break;
353	case CTL_W_MASTRCLR:
354	dmaClear(dc);
355	break;
356	case CTL_W_CLRMASK:
357	dc->u8Mask = 0;
358	break;
359	case CTL_W_MASK:
360	dc->u8Mask = u32;
361	break;
362	default:
363	Assert(0);
364	break;
365	}
366	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
367	port, chidx, u32));
368	}
369	else
370	{
371	/* Likely a guest bug. */
372	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
373	port, cb, u32));
374	}
375	return VINF_SUCCESS;
376	}
377
378	static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
379	{
380	if (cb == 1)
381	{
382	DMAControl dc = (DMAControl )pvUser;
383	uint8_t val = 0;
384	int reg;
385
386	reg = ((port >> dc->is16bit) & 0x0f) - 8;
387	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
388
389	switch (reg)
390	{
391	case CTL_R_STAT:
392	val = dc->u8Status;
393	dc->u8Status &= 0xf0; /* A read clears all TCs. */
394	break;
395	case CTL_R_DMAREQ:
396	val = (dc->u8Status >> 4) \| 0xf0;
397	break;
398	case CTL_R_CMD:
399	val = dc->u8Command;
400	break;
401	case CTL_R_MODE:
402	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
403	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
404	case CTL_R_SETBPTR:
405	dc->fHiByte = true;
406	break;
407	case CTL_R_TEMP:
408	val = dc->u8Temp;
409	break;
410	case CTL_R_CLRMODE:
411	dc->u8ModeCtr = 0;
412	break;
413	case CTL_R_MASK:
414	val = dc->u8Mask;
415	break;
416	default:
417	Assert(0);
418	break;
419	}
420
421	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
422	*pu32 = val;
423
424	return VINF_SUCCESS;
425	}
426	return VERR_IOM_IOPORT_UNUSED;
427	}
428
429	/** DMA page registers. There are 16 R/W page registers for compatibility with
430	* the IBM PC/AT; only some of those registers are used for DMA. The page register
431	* accessible via port 80h may be read to insert small delays or used as a scratch
432	* register by a BIOS.
433	*/
434	static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
435	{
436	DMAControl dc = (DMAControl )pvUser;
437	int reg;
438
439	if (cb == 1)
440	{
441	reg = port & 7;
442	*pu32 = dc->au8Page[reg];
443	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
444	*pu32, port, DMAPG2CX(reg)));
445	return VINF_SUCCESS;
446	}
447
448	if (cb == 2)
449	{
450	reg = port & 7;
451	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
452	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
453	*pu32, port, DMAPG2CX(reg)));
454	return VINF_SUCCESS;
455	}
456
457	return VERR_IOM_IOPORT_UNUSED;
458	}
459
460	static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
461	{
462	DMAControl dc = (DMAControl )pvUser;
463	int reg;
464
465	if (cb == 1)
466	{
467	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
468	reg = port & 7;
469	dc->au8Page[reg] = u32;
470	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
471	Log2(("Wrote %#x to page register %#x (channel %d)\n",
472	u32, port, DMAPG2CX(reg)));
473	}
474	else if (cb == 2)
475	{
476	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
477	reg = port & 7;
478	dc->au8Page[reg] = u32;
479	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
480	reg = (port + 1) & 7;
481	dc->au8Page[reg] = u32 >> 8;
482	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
483	}
484	else
485	{
486	/* Likely a guest bug. */
487	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
488	port, cb, u32));
489	}
490	return VINF_SUCCESS;
491	}
492
493	/**
494	* EISA style high page registers, for extending the DMA addresses to cover
495	* the entire 32-bit address space.
496	*/
497	static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
498	{
499	if (cb == 1)
500	{
501	DMAControl dc = (DMAControl )pvUser;
502	int reg;
503
504	reg = port & 7;
505	*pu32 = dc->au8PageHi[reg];
506	Log2(("Read %#x to from high page register %#x (channel %d)\n",
507	*pu32, port, DMAPG2CX(reg)));
508	return VINF_SUCCESS;
509	}
510	return VERR_IOM_IOPORT_UNUSED;
511	}
512
513	static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
514	{
515	if (cb == 1)
516	{
517	DMAControl dc = (DMAControl )pvUser;
518	int reg;
519
520	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
521	reg = port & 7;
522	dc->au8PageHi[reg] = u32;
523	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
524	u32, port, DMAPG2CX(reg)));
525	}
526	else
527	{
528	/* Likely a guest bug. */
529	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
530	port, cb, u32));
531	}
532	return VINF_SUCCESS;
533	}
534
535	/** Perform any pending transfers on a single DMA channel. */
536	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
537	{
538	DMAControl *dc = &pThis->DMAC[ctlidx];
539	DMAChannel *ch = &dc->ChState[chidx];
540	uint32_t start_cnt, end_cnt;
541	int opmode;
542
543	opmode = (ch->u8Mode >> 6) & 3;
544
545	Log3(("DMA address %screment, mode %d\n",
546	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
547	ch->u8Mode >> 6));
548
549	/* Addresses and counts are shifted for 16-bit channels. */
550	start_cnt = ch->u16CurCount << dc->is16bit;
551	/* NB: The device is responsible for examining the DMA mode and not
552	* transferring more than it should if auto-init is not in use.
553	*/
554	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
555	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
556	ch->u16CurCount = end_cnt >> dc->is16bit;
557	/* Set the TC (Terminal Count) bit if transfer was completed. */
558	if (ch->u16CurCount == ch->u16BaseCount + 1)
559	switch (opmode)
560	{
561	case DMODE_DEMAND:
562	case DMODE_SINGLE:
563	case DMODE_BLOCK:
564	dc->u8Status \|= RT_BIT(chidx);
565	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
566	break;
567	default:
568	break;
569	}
570	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
571	}
572
573	/**
574	* @interface_method_impl{PDMDMAREG,pfnRun}
575	*/
576	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
577	{
578	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
579	DMAControl *dc;
580	int ctlidx, chidx, mask;
581	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
582
583	/* Run all controllers and channels. */
584	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
585	{
586	dc = &pThis->DMAC[ctlidx];
587
588	/* If controller is disabled, don't even bother. */
589	if (dc->u8Command & CMD_DISABLE)
590	continue;
591
592	for (chidx = 0; chidx < 4; ++chidx)
593	{
594	mask = 1 << chidx;
595	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
596	dmaRunChannel(pThis, ctlidx, chidx);
597	}
598	}
599
600	PDMCritSectLeave(pDevIns->pCritSectRoR3);
601	return 0;
602	}
603
604	/**
605	* @interface_method_impl{PDMDMAREG,pfnRegister}
606	*/
607	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
608	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
609	{
610	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
611	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
612
613	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
614
615	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
616	ch->pfnXferHandler = pfnTransferHandler;
617	ch->pvUser = pvUser;
618	PDMCritSectLeave(pDevIns->pCritSectRoR3);
619	}
620
621	/** Reverse the order of bytes in a memory buffer. */
622	static void dmaReverseBuf8(void *buf, unsigned len)
623	{
624	uint8_t pBeg, pEnd;
625	uint8_t temp;
626
627	pBeg = (uint8_t *)buf;
628	pEnd = pBeg + len - 1;
629	for (len = len / 2; len; --len)
630	{
631	temp = *pBeg;
632	pBeg++ = pEnd;
633	*pEnd-- = temp;
634	}
635	}
636
637	/** Reverse the order of words in a memory buffer. */
638	static void dmaReverseBuf16(void *buf, unsigned len)
639	{
640	uint16_t pBeg, pEnd;
641	uint16_t temp;
642
643	Assert(!(len & 1));
644	len /= 2; /* Convert to word count. */
645	pBeg = (uint16_t *)buf;
646	pEnd = pBeg + len - 1;
647	for (len = len / 2; len; --len)
648	{
649	temp = *pBeg;
650	pBeg++ = pEnd;
651	*pEnd-- = temp;
652	}
653	}
654
655	/**
656	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
657	*/
658	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
659	void *pvBuffer, uint32_t off, uint32_t cbBlock)
660	{
661	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
662	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
663	DMAChannel *ch = &dc->ChState[uChannel & 3];
664	uint32_t page, pagehi;
665	uint32_t addr;
666
667	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
668
669	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
670
671	/* Build the address for this transfer. */
672	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
673	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
674	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
675
676	if (IS_MODE_DEC(ch->u8Mode))
677	{
678	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
679	if (dc->is16bit)
680	dmaReverseBuf16(pvBuffer, cbBlock);
681	else
682	dmaReverseBuf8(pvBuffer, cbBlock);
683	}
684	else
685	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
686
687	PDMCritSectLeave(pDevIns->pCritSectRoR3);
688	return cbBlock;
689	}
690
691	/**
692	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
693	*/
694	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
695	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
696	{
697	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
698	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
699	DMAChannel *ch = &dc->ChState[uChannel & 3];
700	uint32_t page, pagehi;
701	uint32_t addr;
702
703	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
704	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
705
706	/* Build the address for this transfer. */
707	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
708	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
709	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
710
711	if (IS_MODE_DEC(ch->u8Mode))
712	{
713	//@todo: This would need a temporary buffer.
714	Assert(0);
715	#if 0
716	if (dc->is16bit)
717	dmaReverseBuf16(pvBuffer, cbBlock);
718	else
719	dmaReverseBuf8(pvBuffer, cbBlock);
720	#endif
721	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
722	}
723	else
724	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
725
726	PDMCritSectLeave(pDevIns->pCritSectRoR3);
727	return cbBlock;
728	}
729
730	/**
731	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
732	*/
733	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
734	{
735	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
736	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
737	int chidx;
738
739	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
740
741	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
742	chidx = uChannel & 3;
743	if (uLevel)
744	dc->u8Status \|= 1 << (chidx + 4);
745	else
746	dc->u8Status &= ~(1 << (chidx + 4));
747	PDMCritSectLeave(pDevIns->pCritSectRoR3);
748	}
749
750	/**
751	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
752	*/
753	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
754	{
755	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
756
757	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
758
759	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
760	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
761	PDMCritSectLeave(pDevIns->pCritSectRoR3);
762	return u8Mode;
763	}
764
765
766	/**
767	* @interface_method_impl{PDMDEVREG,pfnReset}
768	*/
769	static void dmaReset(PPDMDEVINS pDevIns)
770	{
771	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
772
773	LogFlow(("dmaReset: pThis=%p\n", pThis));
774
775	/* NB: The page and address registers are unaffected by a reset
776	* and in an undefined state after power-up.
777	*/
778	dmaClear(&pThis->DMAC[0]);
779	dmaClear(&pThis->DMAC[1]);
780	}
781
782	/** Register DMA I/O port handlers. */
783	static void dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
784	{
785	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
786	DMAControl *dc8 = &pThis->DMAC[0];
787	DMAControl *dc16 = &pThis->DMAC[1];
788
789	dc8->is16bit = false;
790	dc16->is16bit = true;
791
792	/* Base and current address for each channel. */
793	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
794	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
795
796	/* Control registers for both DMA controllers. */
797	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
798	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
799
800	/* Page registers for each channel (plus a few unused ones). */
801	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
802	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
803
804	/* Optional EISA style high page registers (address bits 24-31). */
805	if (fHighPage)
806	{
807	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
808	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
809	}
810	}
811
812	static void dmaSaveController(PSSMHANDLE pSSMHandle, DMAControl *dc)
813	{
814	int chidx;
815
816	/* Save controller state... */
817	SSMR3PutU8(pSSMHandle, dc->u8Command);
818	SSMR3PutU8(pSSMHandle, dc->u8Mask);
819	SSMR3PutU8(pSSMHandle, dc->fHiByte);
820	SSMR3PutU32(pSSMHandle, dc->is16bit);
821	SSMR3PutU8(pSSMHandle, dc->u8Status);
822	SSMR3PutU8(pSSMHandle, dc->u8Temp);
823	SSMR3PutU8(pSSMHandle, dc->u8ModeCtr);
824	SSMR3PutMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
825	SSMR3PutMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
826
827	/* ...and all four of its channels. */
828	for (chidx = 0; chidx < 4; ++chidx)
829	{
830	DMAChannel *ch = &dc->ChState[chidx];
831
832	SSMR3PutU16(pSSMHandle, ch->u16CurAddr);
833	SSMR3PutU16(pSSMHandle, ch->u16CurCount);
834	SSMR3PutU16(pSSMHandle, ch->u16BaseAddr);
835	SSMR3PutU16(pSSMHandle, ch->u16BaseCount);
836	SSMR3PutU8(pSSMHandle, ch->u8Mode);
837	}
838	}
839
840	static int dmaLoadController(PSSMHANDLE pSSMHandle, DMAControl *dc, int version)
841	{
842	uint8_t u8val;
843	uint32_t u32val;
844	int chidx;
845
846	SSMR3GetU8(pSSMHandle, &dc->u8Command);
847	SSMR3GetU8(pSSMHandle, &dc->u8Mask);
848	SSMR3GetU8(pSSMHandle, &u8val);
849	dc->fHiByte = !!u8val;
850	SSMR3GetU32(pSSMHandle, &dc->is16bit);
851	if (version > DMA_SAVESTATE_OLD)
852	{
853	SSMR3GetU8(pSSMHandle, &dc->u8Status);
854	SSMR3GetU8(pSSMHandle, &dc->u8Temp);
855	SSMR3GetU8(pSSMHandle, &dc->u8ModeCtr);
856	SSMR3GetMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
857	SSMR3GetMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
858	}
859
860	for (chidx = 0; chidx < 4; ++chidx)
861	{
862	DMAChannel *ch = &dc->ChState[chidx];
863
864	if (version == DMA_SAVESTATE_OLD)
865	{
866	/* Convert from 17-bit to 16-bit format. */
867	SSMR3GetU32(pSSMHandle, &u32val);
868	ch->u16CurAddr = u32val >> dc->is16bit;
869	SSMR3GetU32(pSSMHandle, &u32val);
870	ch->u16CurCount = u32val >> dc->is16bit;
871	}
872	else
873	{
874	SSMR3GetU16(pSSMHandle, &ch->u16CurAddr);
875	SSMR3GetU16(pSSMHandle, &ch->u16CurCount);
876	}
877	SSMR3GetU16(pSSMHandle, &ch->u16BaseAddr);
878	SSMR3GetU16(pSSMHandle, &ch->u16BaseCount);
879	SSMR3GetU8(pSSMHandle, &ch->u8Mode);
880	/* Convert from old save state. */
881	if (version == DMA_SAVESTATE_OLD)
882	{
883	/* Remap page register contents. */
884	SSMR3GetU8(pSSMHandle, &u8val);
885	dc->au8Page[DMACX2PG(chidx)] = u8val;
886	SSMR3GetU8(pSSMHandle, &u8val);
887	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
888	/* Throw away dack, eop. */
889	SSMR3GetU8(pSSMHandle, &u8val);
890	SSMR3GetU8(pSSMHandle, &u8val);
891	}
892	}
893	return 0;
894	}
895
896	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
897	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
898	{
899	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
900
901	dmaSaveController(pSSMHandle, &pThis->DMAC[0]);
902	dmaSaveController(pSSMHandle, &pThis->DMAC[1]);
903	return VINF_SUCCESS;
904	}
905
906	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
907	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
908	{
909	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
910
911	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
912	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
913
914	dmaLoadController(pSSMHandle, &pThis->DMAC[0], uVersion);
915	return dmaLoadController(pSSMHandle, &pThis->DMAC[1], uVersion);
916	}
917
918	/**
919	* @interface_method_impl{PDMDEVREG,pfnConstruct}
920	*/
921	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
922	{
923	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
924	bool bHighPage = false;
925	PDMDMACREG reg;
926	int rc;
927
928	pThis->pDevIns = pDevIns;
929
930	/*
931	* Validate configuration.
932	*/
933	if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
934	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
935
936	#if 0
937	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
938	if (RT_FAILURE (rc))
939	return rc;
940	#endif
941
942	dmaIORegister(pDevIns, bHighPage);
943	dmaReset(pDevIns);
944
945	reg.u32Version = PDM_DMACREG_VERSION;
946	reg.pfnRun = dmaRun;
947	reg.pfnRegister = dmaRegister;
948	reg.pfnReadMemory = dmaReadMemory;
949	reg.pfnWriteMemory = dmaWriteMemory;
950	reg.pfnSetDREQ = dmaSetDREQ;
951	reg.pfnGetChannelMode = dmaGetChannelMode;
952
953	rc = PDMDevHlpDMACRegister(pDevIns, &reg, &pThis->pHlp);
954	if (RT_FAILURE (rc))
955	return rc;
956
957	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
958	if (RT_FAILURE(rc))
959	return rc;
960
961	return VINF_SUCCESS;
962	}
963
964	/**
965	* The device registration structure.
966	*/
967	const PDMDEVREG g_DeviceDMA =
968	{
969	/* u32Version */
970	PDM_DEVREG_VERSION,
971	/* szName */
972	"8237A",
973	/* szRCMod */
974	"",
975	/* szR0Mod */
976	"",
977	/* pszDescription */
978	"DMA Controller Device",
979	/* fFlags */
980	PDM_DEVREG_FLAGS_DEFAULT_BITS,
981	/* fClass */
982	PDM_DEVREG_CLASS_DMA,
983	/* cMaxInstances */
984	1,
985	/* cbInstance */
986	sizeof(DMAState),
987	/* pfnConstruct */
988	dmaConstruct,
989	/* pfnDestruct */
990	NULL,
991	/* pfnRelocate */
992	NULL,
993	/* pfnMemSetup */
994	NULL,
995	/* pfnPowerOn */
996	NULL,
997	/* pfnReset */
998	dmaReset,
999	/* pfnSuspend */
1000	NULL,
1001	/* pfnResume */
1002	NULL,
1003	/* pfnAttach */
1004	NULL,
1005	/* pfnDetach */
1006	NULL,
1007	/* pfnQueryInterface. */
1008	NULL,
1009	/* pfnInitComplete */
1010	NULL,
1011	/* pfnPowerOff */
1012	NULL,
1013	/* pfnSoftReset */
1014	NULL,
1015	/* u32VersionEnd */
1016	PDM_DEVREG_VERSION
1017	};

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 47928

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