DevDMA.cpp@ 53426

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1	/* $Id: DevDMA.cpp 48947 2013-10-07 21:41:00Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_DMA
47	#include <VBox/vmm/pdmdev.h>
48	#include <VBox/err.h>
49
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include <stdio.h>
55	#include <stdlib.h>
56
57	#include "VBoxDD.h"
58
59
60	/** @page pg_dev_dma DMA Overview and notes
61	*
62	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
63	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
64	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
65	* 74LS612 extends addressing to 24 bits. That leads to well known and
66	* inconvenient DMA limitations:
67	* - DMA can only access physical memory under the 16MB line
68	* - DMA transfers must occur within a 64KB/128KB 'page'
69	*
70	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
71	* left by one, including the control registers addresses. The DMA register
72	* offsets (except for the page registers) are therefore "double spaced".
73	*
74	* Due to the address shifting, the DMA controller decodes more addresses
75	* than are usually documented, with aliasing. See the ICH8 datasheet.
76	*
77	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
78	* preventing the use of memory-to-memory DMA transfers (which use channels
79	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
80	* However, it would transfer a single byte at a time, while the CPU can
81	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
82	* compatibles, memory-to-memory DMA is not even implemented at all, and
83	* therefore has no practical use.
84	*
85	* Auto-init mode is handled implicitly; a device's transfer handler may
86	* return an end count lower than the start count.
87	*
88	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
89	* while 'chidx' refers to a DMA channel index within a controller (0-3).
90	*
91	* References:
92	* - IBM Personal Computer AT Technical Reference, 1984
93	* - Intel 8237A-5 Datasheet, 1993
94	* - Frank van Gilluwe, The Undocumented PC, 1994
95	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
96	* - Intel ICH8 Datasheet, 2007
97	*/
98
99
100	/* Saved state versions. */
101	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
102	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
103
104	/* State information for a single DMA channel. */
105	typedef struct {
106	void pvUser; / User specific context. */
107	PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
108	uint16_t u16BaseAddr; /* Base address for transfers. */
109	uint16_t u16BaseCount; /* Base count for transfers. */
110	uint16_t u16CurAddr; /* Current address. */
111	uint16_t u16CurCount; /* Current count. */
112	uint8_t u8Mode; /* Channel mode. */
113	} DMAChannel;
114
115	/* State information for a DMA controller (DMA8 or DMA16). */
116	typedef struct {
117	DMAChannel ChState[4]; /* Per-channel state. */
118	uint8_t au8Page[8]; /* Page registers (A16-A23). */
119	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
120	uint8_t u8Command; /* Command register. */
121	uint8_t u8Status; /* Status register. */
122	uint8_t u8Mask; /* Mask register. */
123	uint8_t u8Temp; /* Temporary (mem/mem) register. */
124	uint8_t u8ModeCtr; /* Mode register counter for reads. */
125	bool fHiByte; /* Byte pointer (T/F -> high/low). */
126	uint32_t is16bit; /* True for 16-bit DMA. */
127	} DMAControl;
128
129	/* Complete DMA state information. */
130	typedef struct {
131	PPDMDEVINS pDevIns; /* Device instance. */
132	PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
133	DMAControl DMAC[2]; /* Two DMA controllers. */
134	} DMAState;
135
136	/* DMA command register bits. */
137	enum {
138	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
139	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
140	CMD_DISABLE = 0x04, /* Disable controller. */
141	CMD_COMPRTIME = 0x08, /* Compressed timing. */
142	CMD_ROTPRIO = 0x10, /* Rotating priority. */
143	CMD_EXTWR = 0x20, /* Extended write. */
144	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
145	CMD_DACKHI = 0x80, /* DACK is active high if set. */
146	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
147	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
148	};
149
150	/* DMA control register offsets for read accesses. */
151	enum {
152	CTL_R_STAT, /* Read status registers. */
153	CTL_R_DMAREQ, /* Read DRQ register. */
154	CTL_R_CMD, /* Read command register. */
155	CTL_R_MODE, /* Read mode register. */
156	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
157	CTL_R_TEMP, /* Read temporary register. */
158	CTL_R_CLRMODE, /* Clear mode register counter. */
159	CTL_R_MASK /* Read all DRQ mask bits. */
160	};
161
162	/* DMA control register offsets for read accesses. */
163	enum {
164	CTL_W_CMD, /* Write command register. */
165	CTL_W_DMAREQ, /* Write DRQ register. */
166	CTL_W_MASKONE, /* Write single DRQ mask bit. */
167	CTL_W_MODE, /* Write mode register. */
168	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
169	CTL_W_MASTRCLR, /* Master clear. */
170	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
171	CTL_W_MASK /* Write all DRQ mask bits. */
172	};
173
174	/* DMA transfer modes. */
175	enum {
176	DMODE_DEMAND, /* Demand transfer mode. */
177	DMODE_SINGLE, /* Single transfer mode. */
178	DMODE_BLOCK, /* Block transfer mode. */
179	DMODE_CASCADE /* Cascade mode. */
180	};
181
182	/* DMA transfer types. */
183	enum {
184	DTYPE_VERIFY, /* Verify transfer type. */
185	DTYPE_WRITE, /* Write transfer type. */
186	DTYPE_READ, /* Read transfer type. */
187	DTYPE_ILLEGAL /* Undefined. */
188	};
189
190	/* Convert DMA channel number (0-7) to controller number (0-1). */
191	#define DMACH2C(c) (c < 4 ? 0 : 1)
192
193	static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
194	/* Map a DMA page register offset (0-7) to channel index (0-3). */
195	#define DMAPG2CX(c) (dmaChannelMap[c])
196
197	static int dmaMapChannel[4] = {7, 3, 1, 2};
198	/* Map a channel index (0-3) to DMA page register offset (0-7). */
199	#define DMACX2PG(c) (dmaMapChannel[c])
200	/* Map a channel number (0-7) to DMA page register offset (0-7). */
201	#define DMACH2PG(c) (dmaMapChannel[c & 3])
202
203	/* Test the decrement bit of mode register. */
204	#define IS_MODE_DEC(c) ((c) & 0x20)
205	/* Test the auto-init bit of mode register. */
206	#define IS_MODE_AI(c) ((c) & 0x10)
207	/* Extract the transfer type bits of mode register. */
208	#define GET_MODE_XTYP(c)(((c) & 0x0c) >> 2)
209
210	/* Perform a master clear (reset) on a DMA controller. */
211	static void dmaClear(DMAControl *dc)
212	{
213	dc->u8Command = 0;
214	dc->u8Status = 0;
215	dc->u8Temp = 0;
216	dc->u8ModeCtr = 0;
217	dc->fHiByte = false;
218	dc->u8Mask = ~0;
219	}
220
221	/* Read the byte pointer and flip it. */
222	static inline bool dmaReadBytePtr(DMAControl *dc)
223	{
224	bool bHighByte;
225
226	bHighByte = !!dc->fHiByte;
227	dc->fHiByte ^= 1;
228	return bHighByte;
229	}
230
231	/* DMA address registers writes and reads. */
232
233	static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
234	{
235	if (cb == 1)
236	{
237	DMAControl dc = (DMAControl )pvUser;
238	DMAChannel *ch;
239	int chidx, reg, is_count;
240
241	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
242	reg = (port >> dc->is16bit) & 0x0f;
243	chidx = reg >> 1;
244	is_count = reg & 1;
245	ch = &dc->ChState[chidx];
246	if (dmaReadBytePtr(dc))
247	{
248	/* Write the high byte. */
249	if (is_count)
250	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
251	else
252	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
253
254	ch->u16CurCount = 0;
255	ch->u16CurAddr = ch->u16BaseAddr;
256	}
257	else
258	{
259	/* Write the low byte. */
260	if (is_count)
261	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
262	else
263	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
264	}
265	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
266	port, chidx, u32));
267	}
268	else
269	{
270	/* Likely a guest bug. */
271	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
272	port, cb, u32));
273	}
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
278	{
279	if (cb == 1)
280	{
281	DMAControl dc = (DMAControl )pvUser;
282	DMAChannel *ch;
283	int chidx, reg, val, dir;
284	int bptr;
285
286	reg = (port >> dc->is16bit) & 0x0f;
287	chidx = reg >> 1;
288	ch = &dc->ChState[chidx];
289
290	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
291	if (reg & 1)
292	val = ch->u16BaseCount - ch->u16CurCount;
293	else
294	val = ch->u16CurAddr + ch->u16CurCount * dir;
295
296	bptr = dmaReadBytePtr(dc);
297	pu32 = RT_LOBYTE(val >> (bptr 8));
298
299	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
300	return VINF_SUCCESS;
301	}
302	else
303	return VERR_IOM_IOPORT_UNUSED;
304	}
305
306	/* DMA control registers writes and reads. */
307
308	static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
309	uint32_t u32, unsigned cb)
310	{
311	if (cb == 1)
312	{
313	DMAControl dc = (DMAControl )pvUser;
314	int chidx = 0;
315	int reg;
316
317	reg = ((port >> dc->is16bit) & 0x0f) - 8;
318	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
319	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
320
321	switch (reg) {
322	case CTL_W_CMD:
323	/* Unsupported commands are entirely ignored. */
324	if (u32 & CMD_UNSUPPORTED)
325	{
326	Log(("DMA command %#x is not supported, ignoring!\n", u32));
327	break;
328	}
329	dc->u8Command = u32;
330	break;
331	case CTL_W_DMAREQ:
332	chidx = u32 & 3;
333	if (u32 & 4)
334	dc->u8Status \|= 1 << (chidx + 4);
335	else
336	dc->u8Status &= ~(1 << (chidx + 4));
337	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
338	break;
339	case CTL_W_MASKONE:
340	chidx = u32 & 3;
341	if (u32 & 4)
342	dc->u8Mask \|= 1 << chidx;
343	else
344	dc->u8Mask &= ~(1 << chidx);
345	break;
346	case CTL_W_MODE:
347	{
348	int op, opmode;
349
350	chidx = u32 & 3;
351	op = (u32 >> 2) & 3;
352	opmode = (u32 >> 6) & 3;
353	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
354	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
355	IS_MODE_DEC(u32) ? "de" : "in", opmode));
356
357	dc->ChState[chidx].u8Mode = u32;
358	break;
359	}
360	case CTL_W_CLRBPTR:
361	dc->fHiByte = false;
362	break;
363	case CTL_W_MASTRCLR:
364	dmaClear(dc);
365	break;
366	case CTL_W_CLRMASK:
367	dc->u8Mask = 0;
368	break;
369	case CTL_W_MASK:
370	dc->u8Mask = u32;
371	break;
372	default:
373	Assert(0);
374	break;
375	}
376	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
377	port, chidx, u32));
378	}
379	else
380	{
381	/* Likely a guest bug. */
382	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
383	port, cb, u32));
384	}
385	return VINF_SUCCESS;
386	}
387
388	static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
389	{
390	if (cb == 1)
391	{
392	DMAControl dc = (DMAControl )pvUser;
393	uint8_t val = 0;
394	int reg;
395
396	reg = ((port >> dc->is16bit) & 0x0f) - 8;
397	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
398
399	switch (reg)
400	{
401	case CTL_R_STAT:
402	val = dc->u8Status;
403	dc->u8Status &= 0xf0; /* A read clears all TCs. */
404	break;
405	case CTL_R_DMAREQ:
406	val = (dc->u8Status >> 4) \| 0xf0;
407	break;
408	case CTL_R_CMD:
409	val = dc->u8Command;
410	break;
411	case CTL_R_MODE:
412	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
413	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
414	case CTL_R_SETBPTR:
415	dc->fHiByte = true;
416	break;
417	case CTL_R_TEMP:
418	val = dc->u8Temp;
419	break;
420	case CTL_R_CLRMODE:
421	dc->u8ModeCtr = 0;
422	break;
423	case CTL_R_MASK:
424	val = dc->u8Mask;
425	break;
426	default:
427	Assert(0);
428	break;
429	}
430
431	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
432	*pu32 = val;
433
434	return VINF_SUCCESS;
435	}
436	return VERR_IOM_IOPORT_UNUSED;
437	}
438
439	/** DMA page registers. There are 16 R/W page registers for compatibility with
440	* the IBM PC/AT; only some of those registers are used for DMA. The page register
441	* accessible via port 80h may be read to insert small delays or used as a scratch
442	* register by a BIOS.
443	*/
444	static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
445	{
446	DMAControl dc = (DMAControl )pvUser;
447	int reg;
448
449	if (cb == 1)
450	{
451	reg = port & 7;
452	*pu32 = dc->au8Page[reg];
453	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
454	*pu32, port, DMAPG2CX(reg)));
455	return VINF_SUCCESS;
456	}
457
458	if (cb == 2)
459	{
460	reg = port & 7;
461	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
462	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
463	*pu32, port, DMAPG2CX(reg)));
464	return VINF_SUCCESS;
465	}
466
467	return VERR_IOM_IOPORT_UNUSED;
468	}
469
470	static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
471	{
472	DMAControl dc = (DMAControl )pvUser;
473	int reg;
474
475	if (cb == 1)
476	{
477	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
478	reg = port & 7;
479	dc->au8Page[reg] = u32;
480	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
481	Log2(("Wrote %#x to page register %#x (channel %d)\n",
482	u32, port, DMAPG2CX(reg)));
483	}
484	else if (cb == 2)
485	{
486	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
487	reg = port & 7;
488	dc->au8Page[reg] = u32;
489	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
490	reg = (port + 1) & 7;
491	dc->au8Page[reg] = u32 >> 8;
492	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
493	}
494	else
495	{
496	/* Likely a guest bug. */
497	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
498	port, cb, u32));
499	}
500	return VINF_SUCCESS;
501	}
502
503	/**
504	* EISA style high page registers, for extending the DMA addresses to cover
505	* the entire 32-bit address space.
506	*/
507	static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
508	{
509	if (cb == 1)
510	{
511	DMAControl dc = (DMAControl )pvUser;
512	int reg;
513
514	reg = port & 7;
515	*pu32 = dc->au8PageHi[reg];
516	Log2(("Read %#x to from high page register %#x (channel %d)\n",
517	*pu32, port, DMAPG2CX(reg)));
518	return VINF_SUCCESS;
519	}
520	return VERR_IOM_IOPORT_UNUSED;
521	}
522
523	static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
524	{
525	if (cb == 1)
526	{
527	DMAControl dc = (DMAControl )pvUser;
528	int reg;
529
530	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
531	reg = port & 7;
532	dc->au8PageHi[reg] = u32;
533	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
534	u32, port, DMAPG2CX(reg)));
535	}
536	else
537	{
538	/* Likely a guest bug. */
539	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
540	port, cb, u32));
541	}
542	return VINF_SUCCESS;
543	}
544
545	/** Perform any pending transfers on a single DMA channel. */
546	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
547	{
548	DMAControl *dc = &pThis->DMAC[ctlidx];
549	DMAChannel *ch = &dc->ChState[chidx];
550	uint32_t start_cnt, end_cnt;
551	int opmode;
552
553	opmode = (ch->u8Mode >> 6) & 3;
554
555	Log3(("DMA address %screment, mode %d\n",
556	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
557	ch->u8Mode >> 6));
558
559	/* Addresses and counts are shifted for 16-bit channels. */
560	start_cnt = ch->u16CurCount << dc->is16bit;
561	/* NB: The device is responsible for examining the DMA mode and not
562	* transferring more than it should if auto-init is not in use.
563	*/
564	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
565	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
566	ch->u16CurCount = end_cnt >> dc->is16bit;
567	/* Set the TC (Terminal Count) bit if transfer was completed. */
568	if (ch->u16CurCount == ch->u16BaseCount + 1)
569	switch (opmode)
570	{
571	case DMODE_DEMAND:
572	case DMODE_SINGLE:
573	case DMODE_BLOCK:
574	dc->u8Status \|= RT_BIT(chidx);
575	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
576	break;
577	default:
578	break;
579	}
580	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
581	}
582
583	/**
584	* @interface_method_impl{PDMDMAREG,pfnRun}
585	*/
586	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
587	{
588	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
589	DMAControl *dc;
590	int ctlidx, chidx, mask;
591	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
592
593	/* Run all controllers and channels. */
594	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
595	{
596	dc = &pThis->DMAC[ctlidx];
597
598	/* If controller is disabled, don't even bother. */
599	if (dc->u8Command & CMD_DISABLE)
600	continue;
601
602	for (chidx = 0; chidx < 4; ++chidx)
603	{
604	mask = 1 << chidx;
605	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
606	dmaRunChannel(pThis, ctlidx, chidx);
607	}
608	}
609
610	PDMCritSectLeave(pDevIns->pCritSectRoR3);
611	return 0;
612	}
613
614	/**
615	* @interface_method_impl{PDMDMAREG,pfnRegister}
616	*/
617	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
618	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
619	{
620	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
621	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
622
623	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
624
625	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
626	ch->pfnXferHandler = pfnTransferHandler;
627	ch->pvUser = pvUser;
628	PDMCritSectLeave(pDevIns->pCritSectRoR3);
629	}
630
631	/** Reverse the order of bytes in a memory buffer. */
632	static void dmaReverseBuf8(void *buf, unsigned len)
633	{
634	uint8_t pBeg, pEnd;
635	uint8_t temp;
636
637	pBeg = (uint8_t *)buf;
638	pEnd = pBeg + len - 1;
639	for (len = len / 2; len; --len)
640	{
641	temp = *pBeg;
642	pBeg++ = pEnd;
643	*pEnd-- = temp;
644	}
645	}
646
647	/** Reverse the order of words in a memory buffer. */
648	static void dmaReverseBuf16(void *buf, unsigned len)
649	{
650	uint16_t pBeg, pEnd;
651	uint16_t temp;
652
653	Assert(!(len & 1));
654	len /= 2; /* Convert to word count. */
655	pBeg = (uint16_t *)buf;
656	pEnd = pBeg + len - 1;
657	for (len = len / 2; len; --len)
658	{
659	temp = *pBeg;
660	pBeg++ = pEnd;
661	*pEnd-- = temp;
662	}
663	}
664
665	/**
666	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
667	*/
668	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
669	void *pvBuffer, uint32_t off, uint32_t cbBlock)
670	{
671	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
672	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
673	DMAChannel *ch = &dc->ChState[uChannel & 3];
674	uint32_t page, pagehi;
675	uint32_t addr;
676
677	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
678
679	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
680
681	/* Build the address for this transfer. */
682	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
683	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
684	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
685
686	if (IS_MODE_DEC(ch->u8Mode))
687	{
688	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
689	if (dc->is16bit)
690	dmaReverseBuf16(pvBuffer, cbBlock);
691	else
692	dmaReverseBuf8(pvBuffer, cbBlock);
693	}
694	else
695	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
696
697	PDMCritSectLeave(pDevIns->pCritSectRoR3);
698	return cbBlock;
699	}
700
701	/**
702	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
703	*/
704	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
705	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
706	{
707	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
708	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
709	DMAChannel *ch = &dc->ChState[uChannel & 3];
710	uint32_t page, pagehi;
711	uint32_t addr;
712
713	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
714	if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
715	{
716	Log(("DMA verify transfer, ignoring write.\n"));
717	return cbBlock;
718	}
719
720	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
721
722	/* Build the address for this transfer. */
723	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
724	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
725	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
726
727	if (IS_MODE_DEC(ch->u8Mode))
728	{
729	//@todo: This would need a temporary buffer.
730	Assert(0);
731	#if 0
732	if (dc->is16bit)
733	dmaReverseBuf16(pvBuffer, cbBlock);
734	else
735	dmaReverseBuf8(pvBuffer, cbBlock);
736	#endif
737	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
738	}
739	else
740	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
741
742	PDMCritSectLeave(pDevIns->pCritSectRoR3);
743	return cbBlock;
744	}
745
746	/**
747	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
748	*/
749	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
750	{
751	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
752	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
753	int chidx;
754
755	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
756
757	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
758	chidx = uChannel & 3;
759	if (uLevel)
760	dc->u8Status \|= 1 << (chidx + 4);
761	else
762	dc->u8Status &= ~(1 << (chidx + 4));
763	PDMCritSectLeave(pDevIns->pCritSectRoR3);
764	}
765
766	/**
767	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
768	*/
769	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
770	{
771	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
772
773	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
774
775	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
776	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
777	PDMCritSectLeave(pDevIns->pCritSectRoR3);
778	return u8Mode;
779	}
780
781
782	/**
783	* @interface_method_impl{PDMDEVREG,pfnReset}
784	*/
785	static void dmaReset(PPDMDEVINS pDevIns)
786	{
787	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
788
789	LogFlow(("dmaReset: pThis=%p\n", pThis));
790
791	/* NB: The page and address registers are unaffected by a reset
792	* and in an undefined state after power-up.
793	*/
794	dmaClear(&pThis->DMAC[0]);
795	dmaClear(&pThis->DMAC[1]);
796	}
797
798	/** Register DMA I/O port handlers. */
799	static void dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
800	{
801	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
802	DMAControl *dc8 = &pThis->DMAC[0];
803	DMAControl *dc16 = &pThis->DMAC[1];
804
805	dc8->is16bit = false;
806	dc16->is16bit = true;
807
808	/* Base and current address for each channel. */
809	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
810	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
811
812	/* Control registers for both DMA controllers. */
813	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
814	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
815
816	/* Page registers for each channel (plus a few unused ones). */
817	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
818	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
819
820	/* Optional EISA style high page registers (address bits 24-31). */
821	if (fHighPage)
822	{
823	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
824	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
825	}
826	}
827
828	static void dmaSaveController(PSSMHANDLE pSSMHandle, DMAControl *dc)
829	{
830	int chidx;
831
832	/* Save controller state... */
833	SSMR3PutU8(pSSMHandle, dc->u8Command);
834	SSMR3PutU8(pSSMHandle, dc->u8Mask);
835	SSMR3PutU8(pSSMHandle, dc->fHiByte);
836	SSMR3PutU32(pSSMHandle, dc->is16bit);
837	SSMR3PutU8(pSSMHandle, dc->u8Status);
838	SSMR3PutU8(pSSMHandle, dc->u8Temp);
839	SSMR3PutU8(pSSMHandle, dc->u8ModeCtr);
840	SSMR3PutMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
841	SSMR3PutMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
842
843	/* ...and all four of its channels. */
844	for (chidx = 0; chidx < 4; ++chidx)
845	{
846	DMAChannel *ch = &dc->ChState[chidx];
847
848	SSMR3PutU16(pSSMHandle, ch->u16CurAddr);
849	SSMR3PutU16(pSSMHandle, ch->u16CurCount);
850	SSMR3PutU16(pSSMHandle, ch->u16BaseAddr);
851	SSMR3PutU16(pSSMHandle, ch->u16BaseCount);
852	SSMR3PutU8(pSSMHandle, ch->u8Mode);
853	}
854	}
855
856	static int dmaLoadController(PSSMHANDLE pSSMHandle, DMAControl *dc, int version)
857	{
858	uint8_t u8val;
859	uint32_t u32val;
860	int chidx;
861
862	SSMR3GetU8(pSSMHandle, &dc->u8Command);
863	SSMR3GetU8(pSSMHandle, &dc->u8Mask);
864	SSMR3GetU8(pSSMHandle, &u8val);
865	dc->fHiByte = !!u8val;
866	SSMR3GetU32(pSSMHandle, &dc->is16bit);
867	if (version > DMA_SAVESTATE_OLD)
868	{
869	SSMR3GetU8(pSSMHandle, &dc->u8Status);
870	SSMR3GetU8(pSSMHandle, &dc->u8Temp);
871	SSMR3GetU8(pSSMHandle, &dc->u8ModeCtr);
872	SSMR3GetMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
873	SSMR3GetMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
874	}
875
876	for (chidx = 0; chidx < 4; ++chidx)
877	{
878	DMAChannel *ch = &dc->ChState[chidx];
879
880	if (version == DMA_SAVESTATE_OLD)
881	{
882	/* Convert from 17-bit to 16-bit format. */
883	SSMR3GetU32(pSSMHandle, &u32val);
884	ch->u16CurAddr = u32val >> dc->is16bit;
885	SSMR3GetU32(pSSMHandle, &u32val);
886	ch->u16CurCount = u32val >> dc->is16bit;
887	}
888	else
889	{
890	SSMR3GetU16(pSSMHandle, &ch->u16CurAddr);
891	SSMR3GetU16(pSSMHandle, &ch->u16CurCount);
892	}
893	SSMR3GetU16(pSSMHandle, &ch->u16BaseAddr);
894	SSMR3GetU16(pSSMHandle, &ch->u16BaseCount);
895	SSMR3GetU8(pSSMHandle, &ch->u8Mode);
896	/* Convert from old save state. */
897	if (version == DMA_SAVESTATE_OLD)
898	{
899	/* Remap page register contents. */
900	SSMR3GetU8(pSSMHandle, &u8val);
901	dc->au8Page[DMACX2PG(chidx)] = u8val;
902	SSMR3GetU8(pSSMHandle, &u8val);
903	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
904	/* Throw away dack, eop. */
905	SSMR3GetU8(pSSMHandle, &u8val);
906	SSMR3GetU8(pSSMHandle, &u8val);
907	}
908	}
909	return 0;
910	}
911
912	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
913	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
914	{
915	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
916
917	dmaSaveController(pSSMHandle, &pThis->DMAC[0]);
918	dmaSaveController(pSSMHandle, &pThis->DMAC[1]);
919	return VINF_SUCCESS;
920	}
921
922	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
923	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
924	{
925	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
926
927	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
928	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
929
930	dmaLoadController(pSSMHandle, &pThis->DMAC[0], uVersion);
931	return dmaLoadController(pSSMHandle, &pThis->DMAC[1], uVersion);
932	}
933
934	/**
935	* @interface_method_impl{PDMDEVREG,pfnConstruct}
936	*/
937	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
938	{
939	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
940	bool bHighPage = false;
941	PDMDMACREG reg;
942	int rc;
943
944	pThis->pDevIns = pDevIns;
945
946	/*
947	* Validate configuration.
948	*/
949	if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
950	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
951
952	#if 0
953	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
954	if (RT_FAILURE (rc))
955	return rc;
956	#endif
957
958	dmaIORegister(pDevIns, bHighPage);
959	dmaReset(pDevIns);
960
961	reg.u32Version = PDM_DMACREG_VERSION;
962	reg.pfnRun = dmaRun;
963	reg.pfnRegister = dmaRegister;
964	reg.pfnReadMemory = dmaReadMemory;
965	reg.pfnWriteMemory = dmaWriteMemory;
966	reg.pfnSetDREQ = dmaSetDREQ;
967	reg.pfnGetChannelMode = dmaGetChannelMode;
968
969	rc = PDMDevHlpDMACRegister(pDevIns, &reg, &pThis->pHlp);
970	if (RT_FAILURE (rc))
971	return rc;
972
973	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
974	if (RT_FAILURE(rc))
975	return rc;
976
977	return VINF_SUCCESS;
978	}
979
980	/**
981	* The device registration structure.
982	*/
983	const PDMDEVREG g_DeviceDMA =
984	{
985	/* u32Version */
986	PDM_DEVREG_VERSION,
987	/* szName */
988	"8237A",
989	/* szRCMod */
990	"",
991	/* szR0Mod */
992	"",
993	/* pszDescription */
994	"DMA Controller Device",
995	/* fFlags */
996	PDM_DEVREG_FLAGS_DEFAULT_BITS,
997	/* fClass */
998	PDM_DEVREG_CLASS_DMA,
999	/* cMaxInstances */
1000	1,
1001	/* cbInstance */
1002	sizeof(DMAState),
1003	/* pfnConstruct */
1004	dmaConstruct,
1005	/* pfnDestruct */
1006	NULL,
1007	/* pfnRelocate */
1008	NULL,
1009	/* pfnMemSetup */
1010	NULL,
1011	/* pfnPowerOn */
1012	NULL,
1013	/* pfnReset */
1014	dmaReset,
1015	/* pfnSuspend */
1016	NULL,
1017	/* pfnResume */
1018	NULL,
1019	/* pfnAttach */
1020	NULL,
1021	/* pfnDetach */
1022	NULL,
1023	/* pfnQueryInterface. */
1024	NULL,
1025	/* pfnInitComplete */
1026	NULL,
1027	/* pfnPowerOff */
1028	NULL,
1029	/* pfnSoftReset */
1030	NULL,
1031	/* u32VersionEnd */
1032	PDM_DEVREG_VERSION
1033	};

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 53426

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