DevDMA.cpp@ 61497

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1	/* $Id: DevDMA.cpp 58132 2015-10-09 00:09:37Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_DMA
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/err.h>
50
51	#include <VBox/log.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include <stdio.h>
56	#include <stdlib.h>
57
58	#include "VBoxDD.h"
59
60
61	/** @page pg_dev_dma DMA Overview and notes
62	*
63	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
64	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
65	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
66	* 74LS612 extends addressing to 24 bits. That leads to well known and
67	* inconvenient DMA limitations:
68	* - DMA can only access physical memory under the 16MB line
69	* - DMA transfers must occur within a 64KB/128KB 'page'
70	*
71	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
72	* left by one, including the control registers addresses. The DMA register
73	* offsets (except for the page registers) are therefore "double spaced".
74	*
75	* Due to the address shifting, the DMA controller decodes more addresses
76	* than are usually documented, with aliasing. See the ICH8 datasheet.
77	*
78	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
79	* preventing the use of memory-to-memory DMA transfers (which use channels
80	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
81	* However, it would transfer a single byte at a time, while the CPU can
82	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
83	* compatibles, memory-to-memory DMA is not even implemented at all, and
84	* therefore has no practical use.
85	*
86	* Auto-init mode is handled implicitly; a device's transfer handler may
87	* return an end count lower than the start count.
88	*
89	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
90	* while 'chidx' refers to a DMA channel index within a controller (0-3).
91	*
92	* References:
93	* - IBM Personal Computer AT Technical Reference, 1984
94	* - Intel 8237A-5 Datasheet, 1993
95	* - Frank van Gilluwe, The Undocumented PC, 1994
96	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
97	* - Intel ICH8 Datasheet, 2007
98	*/
99
100
101	/* Saved state versions. */
102	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
103	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
104
105	/* State information for a single DMA channel. */
106	typedef struct {
107	void pvUser; / User specific context. */
108	PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
109	uint16_t u16BaseAddr; /* Base address for transfers. */
110	uint16_t u16BaseCount; /* Base count for transfers. */
111	uint16_t u16CurAddr; /* Current address. */
112	uint16_t u16CurCount; /* Current count. */
113	uint8_t u8Mode; /* Channel mode. */
114	} DMAChannel;
115
116	/* State information for a DMA controller (DMA8 or DMA16). */
117	typedef struct {
118	DMAChannel ChState[4]; /* Per-channel state. */
119	uint8_t au8Page[8]; /* Page registers (A16-A23). */
120	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
121	uint8_t u8Command; /* Command register. */
122	uint8_t u8Status; /* Status register. */
123	uint8_t u8Mask; /* Mask register. */
124	uint8_t u8Temp; /* Temporary (mem/mem) register. */
125	uint8_t u8ModeCtr; /* Mode register counter for reads. */
126	bool fHiByte; /* Byte pointer (T/F -> high/low). */
127	uint32_t is16bit; /* True for 16-bit DMA. */
128	} DMAControl;
129
130	/* Complete DMA state information. */
131	typedef struct {
132	PPDMDEVINS pDevIns; /* Device instance. */
133	PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
134	DMAControl DMAC[2]; /* Two DMA controllers. */
135	} DMAState;
136
137	/* DMA command register bits. */
138	enum {
139	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
140	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
141	CMD_DISABLE = 0x04, /* Disable controller. */
142	CMD_COMPRTIME = 0x08, /* Compressed timing. */
143	CMD_ROTPRIO = 0x10, /* Rotating priority. */
144	CMD_EXTWR = 0x20, /* Extended write. */
145	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
146	CMD_DACKHI = 0x80, /* DACK is active high if set. */
147	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
148	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
149	};
150
151	/* DMA control register offsets for read accesses. */
152	enum {
153	CTL_R_STAT, /* Read status registers. */
154	CTL_R_DMAREQ, /* Read DRQ register. */
155	CTL_R_CMD, /* Read command register. */
156	CTL_R_MODE, /* Read mode register. */
157	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
158	CTL_R_TEMP, /* Read temporary register. */
159	CTL_R_CLRMODE, /* Clear mode register counter. */
160	CTL_R_MASK /* Read all DRQ mask bits. */
161	};
162
163	/* DMA control register offsets for read accesses. */
164	enum {
165	CTL_W_CMD, /* Write command register. */
166	CTL_W_DMAREQ, /* Write DRQ register. */
167	CTL_W_MASKONE, /* Write single DRQ mask bit. */
168	CTL_W_MODE, /* Write mode register. */
169	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
170	CTL_W_MASTRCLR, /* Master clear. */
171	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
172	CTL_W_MASK /* Write all DRQ mask bits. */
173	};
174
175	/* DMA transfer modes. */
176	enum {
177	DMODE_DEMAND, /* Demand transfer mode. */
178	DMODE_SINGLE, /* Single transfer mode. */
179	DMODE_BLOCK, /* Block transfer mode. */
180	DMODE_CASCADE /* Cascade mode. */
181	};
182
183	/* DMA transfer types. */
184	enum {
185	DTYPE_VERIFY, /* Verify transfer type. */
186	DTYPE_WRITE, /* Write transfer type. */
187	DTYPE_READ, /* Read transfer type. */
188	DTYPE_ILLEGAL /* Undefined. */
189	};
190
191	/* Convert DMA channel number (0-7) to controller number (0-1). */
192	#define DMACH2C(c) (c < 4 ? 0 : 1)
193
194	static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
195	/* Map a DMA page register offset (0-7) to channel index (0-3). */
196	#define DMAPG2CX(c) (dmaChannelMap[c])
197
198	static int dmaMapChannel[4] = {7, 3, 1, 2};
199	/* Map a channel index (0-3) to DMA page register offset (0-7). */
200	#define DMACX2PG(c) (dmaMapChannel[c])
201	/* Map a channel number (0-7) to DMA page register offset (0-7). */
202	#define DMACH2PG(c) (dmaMapChannel[c & 3])
203
204	/* Test the decrement bit of mode register. */
205	#define IS_MODE_DEC(c) ((c) & 0x20)
206	/* Test the auto-init bit of mode register. */
207	#define IS_MODE_AI(c) ((c) & 0x10)
208	/* Extract the transfer type bits of mode register. */
209	#define GET_MODE_XTYP(c)(((c) & 0x0c) >> 2)
210
211	/* Perform a master clear (reset) on a DMA controller. */
212	static void dmaClear(DMAControl *dc)
213	{
214	dc->u8Command = 0;
215	dc->u8Status = 0;
216	dc->u8Temp = 0;
217	dc->u8ModeCtr = 0;
218	dc->fHiByte = false;
219	dc->u8Mask = ~0;
220	}
221
222	/* Read the byte pointer and flip it. */
223	static inline bool dmaReadBytePtr(DMAControl *dc)
224	{
225	bool bHighByte;
226
227	bHighByte = !!dc->fHiByte;
228	dc->fHiByte ^= 1;
229	return bHighByte;
230	}
231
232	/* DMA address registers writes and reads. */
233
234	static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
235	{
236	if (cb == 1)
237	{
238	DMAControl dc = (DMAControl )pvUser;
239	DMAChannel *ch;
240	int chidx, reg, is_count;
241
242	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
243	reg = (port >> dc->is16bit) & 0x0f;
244	chidx = reg >> 1;
245	is_count = reg & 1;
246	ch = &dc->ChState[chidx];
247	if (dmaReadBytePtr(dc))
248	{
249	/* Write the high byte. */
250	if (is_count)
251	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
252	else
253	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
254
255	ch->u16CurCount = 0;
256	ch->u16CurAddr = ch->u16BaseAddr;
257	}
258	else
259	{
260	/* Write the low byte. */
261	if (is_count)
262	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
263	else
264	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
265	}
266	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
267	port, chidx, u32));
268	}
269	else
270	{
271	/* Likely a guest bug. */
272	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
273	port, cb, u32));
274	}
275	return VINF_SUCCESS;
276	}
277
278	static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
279	{
280	if (cb == 1)
281	{
282	DMAControl dc = (DMAControl )pvUser;
283	DMAChannel *ch;
284	int chidx, reg, val, dir;
285	int bptr;
286
287	reg = (port >> dc->is16bit) & 0x0f;
288	chidx = reg >> 1;
289	ch = &dc->ChState[chidx];
290
291	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
292	if (reg & 1)
293	val = ch->u16BaseCount - ch->u16CurCount;
294	else
295	val = ch->u16CurAddr + ch->u16CurCount * dir;
296
297	bptr = dmaReadBytePtr(dc);
298	pu32 = RT_LOBYTE(val >> (bptr 8));
299
300	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
301	return VINF_SUCCESS;
302	}
303	else
304	return VERR_IOM_IOPORT_UNUSED;
305	}
306
307	/* DMA control registers writes and reads. */
308
309	static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
310	uint32_t u32, unsigned cb)
311	{
312	if (cb == 1)
313	{
314	DMAControl dc = (DMAControl )pvUser;
315	int chidx = 0;
316	int reg;
317
318	reg = ((port >> dc->is16bit) & 0x0f) - 8;
319	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
320	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
321
322	switch (reg) {
323	case CTL_W_CMD:
324	/* Unsupported commands are entirely ignored. */
325	if (u32 & CMD_UNSUPPORTED)
326	{
327	Log(("DMA command %#x is not supported, ignoring!\n", u32));
328	break;
329	}
330	dc->u8Command = u32;
331	break;
332	case CTL_W_DMAREQ:
333	chidx = u32 & 3;
334	if (u32 & 4)
335	dc->u8Status \|= 1 << (chidx + 4);
336	else
337	dc->u8Status &= ~(1 << (chidx + 4));
338	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
339	break;
340	case CTL_W_MASKONE:
341	chidx = u32 & 3;
342	if (u32 & 4)
343	dc->u8Mask \|= 1 << chidx;
344	else
345	dc->u8Mask &= ~(1 << chidx);
346	break;
347	case CTL_W_MODE:
348	{
349	int op, opmode;
350
351	chidx = u32 & 3;
352	op = (u32 >> 2) & 3;
353	opmode = (u32 >> 6) & 3;
354	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
355	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
356	IS_MODE_DEC(u32) ? "de" : "in", opmode));
357
358	dc->ChState[chidx].u8Mode = u32;
359	break;
360	}
361	case CTL_W_CLRBPTR:
362	dc->fHiByte = false;
363	break;
364	case CTL_W_MASTRCLR:
365	dmaClear(dc);
366	break;
367	case CTL_W_CLRMASK:
368	dc->u8Mask = 0;
369	break;
370	case CTL_W_MASK:
371	dc->u8Mask = u32;
372	break;
373	default:
374	Assert(0);
375	break;
376	}
377	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
378	port, chidx, u32));
379	}
380	else
381	{
382	/* Likely a guest bug. */
383	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
384	port, cb, u32));
385	}
386	return VINF_SUCCESS;
387	}
388
389	static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
390	{
391	if (cb == 1)
392	{
393	DMAControl dc = (DMAControl )pvUser;
394	uint8_t val = 0;
395	int reg;
396
397	reg = ((port >> dc->is16bit) & 0x0f) - 8;
398	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
399
400	switch (reg)
401	{
402	case CTL_R_STAT:
403	val = dc->u8Status;
404	dc->u8Status &= 0xf0; /* A read clears all TCs. */
405	break;
406	case CTL_R_DMAREQ:
407	val = (dc->u8Status >> 4) \| 0xf0;
408	break;
409	case CTL_R_CMD:
410	val = dc->u8Command;
411	break;
412	case CTL_R_MODE:
413	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
414	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
415	case CTL_R_SETBPTR:
416	dc->fHiByte = true;
417	break;
418	case CTL_R_TEMP:
419	val = dc->u8Temp;
420	break;
421	case CTL_R_CLRMODE:
422	dc->u8ModeCtr = 0;
423	break;
424	case CTL_R_MASK:
425	val = dc->u8Mask;
426	break;
427	default:
428	Assert(0);
429	break;
430	}
431
432	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
433	*pu32 = val;
434
435	return VINF_SUCCESS;
436	}
437	return VERR_IOM_IOPORT_UNUSED;
438	}
439
440	/** DMA page registers. There are 16 R/W page registers for compatibility with
441	* the IBM PC/AT; only some of those registers are used for DMA. The page register
442	* accessible via port 80h may be read to insert small delays or used as a scratch
443	* register by a BIOS.
444	*/
445	static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
446	{
447	DMAControl dc = (DMAControl )pvUser;
448	int reg;
449
450	if (cb == 1)
451	{
452	reg = port & 7;
453	*pu32 = dc->au8Page[reg];
454	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
455	*pu32, port, DMAPG2CX(reg)));
456	return VINF_SUCCESS;
457	}
458
459	if (cb == 2)
460	{
461	reg = port & 7;
462	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
463	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
464	*pu32, port, DMAPG2CX(reg)));
465	return VINF_SUCCESS;
466	}
467
468	return VERR_IOM_IOPORT_UNUSED;
469	}
470
471	static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
472	{
473	DMAControl dc = (DMAControl )pvUser;
474	int reg;
475
476	if (cb == 1)
477	{
478	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
479	reg = port & 7;
480	dc->au8Page[reg] = u32;
481	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
482	Log2(("Wrote %#x to page register %#x (channel %d)\n",
483	u32, port, DMAPG2CX(reg)));
484	}
485	else if (cb == 2)
486	{
487	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
488	reg = port & 7;
489	dc->au8Page[reg] = u32;
490	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
491	reg = (port + 1) & 7;
492	dc->au8Page[reg] = u32 >> 8;
493	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
494	}
495	else
496	{
497	/* Likely a guest bug. */
498	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
499	port, cb, u32));
500	}
501	return VINF_SUCCESS;
502	}
503
504	/**
505	* EISA style high page registers, for extending the DMA addresses to cover
506	* the entire 32-bit address space.
507	*/
508	static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
509	{
510	if (cb == 1)
511	{
512	DMAControl dc = (DMAControl )pvUser;
513	int reg;
514
515	reg = port & 7;
516	*pu32 = dc->au8PageHi[reg];
517	Log2(("Read %#x to from high page register %#x (channel %d)\n",
518	*pu32, port, DMAPG2CX(reg)));
519	return VINF_SUCCESS;
520	}
521	return VERR_IOM_IOPORT_UNUSED;
522	}
523
524	static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
525	{
526	if (cb == 1)
527	{
528	DMAControl dc = (DMAControl )pvUser;
529	int reg;
530
531	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
532	reg = port & 7;
533	dc->au8PageHi[reg] = u32;
534	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
535	u32, port, DMAPG2CX(reg)));
536	}
537	else
538	{
539	/* Likely a guest bug. */
540	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
541	port, cb, u32));
542	}
543	return VINF_SUCCESS;
544	}
545
546	/** Perform any pending transfers on a single DMA channel. */
547	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
548	{
549	DMAControl *dc = &pThis->DMAC[ctlidx];
550	DMAChannel *ch = &dc->ChState[chidx];
551	uint32_t start_cnt, end_cnt;
552	int opmode;
553
554	opmode = (ch->u8Mode >> 6) & 3;
555
556	Log3(("DMA address %screment, mode %d\n",
557	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
558	ch->u8Mode >> 6));
559
560	/* Addresses and counts are shifted for 16-bit channels. */
561	start_cnt = ch->u16CurCount << dc->is16bit;
562	/* NB: The device is responsible for examining the DMA mode and not
563	* transferring more than it should if auto-init is not in use.
564	*/
565	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
566	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
567	ch->u16CurCount = end_cnt >> dc->is16bit;
568	/* Set the TC (Terminal Count) bit if transfer was completed. */
569	if (ch->u16CurCount == ch->u16BaseCount + 1)
570	switch (opmode)
571	{
572	case DMODE_DEMAND:
573	case DMODE_SINGLE:
574	case DMODE_BLOCK:
575	dc->u8Status \|= RT_BIT(chidx);
576	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
577	break;
578	default:
579	break;
580	}
581	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
582	}
583
584	/**
585	* @interface_method_impl{PDMDMAREG,pfnRun}
586	*/
587	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
588	{
589	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
590	DMAControl *dc;
591	int ctlidx, chidx, mask;
592	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
593
594	/* Run all controllers and channels. */
595	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
596	{
597	dc = &pThis->DMAC[ctlidx];
598
599	/* If controller is disabled, don't even bother. */
600	if (dc->u8Command & CMD_DISABLE)
601	continue;
602
603	for (chidx = 0; chidx < 4; ++chidx)
604	{
605	mask = 1 << chidx;
606	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
607	dmaRunChannel(pThis, ctlidx, chidx);
608	}
609	}
610
611	PDMCritSectLeave(pDevIns->pCritSectRoR3);
612	return 0;
613	}
614
615	/**
616	* @interface_method_impl{PDMDMAREG,pfnRegister}
617	*/
618	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
619	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
620	{
621	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
622	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
623
624	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
625
626	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
627	ch->pfnXferHandler = pfnTransferHandler;
628	ch->pvUser = pvUser;
629	PDMCritSectLeave(pDevIns->pCritSectRoR3);
630	}
631
632	/** Reverse the order of bytes in a memory buffer. */
633	static void dmaReverseBuf8(void *buf, unsigned len)
634	{
635	uint8_t pBeg, pEnd;
636	uint8_t temp;
637
638	pBeg = (uint8_t *)buf;
639	pEnd = pBeg + len - 1;
640	for (len = len / 2; len; --len)
641	{
642	temp = *pBeg;
643	pBeg++ = pEnd;
644	*pEnd-- = temp;
645	}
646	}
647
648	/** Reverse the order of words in a memory buffer. */
649	static void dmaReverseBuf16(void *buf, unsigned len)
650	{
651	uint16_t pBeg, pEnd;
652	uint16_t temp;
653
654	Assert(!(len & 1));
655	len /= 2; /* Convert to word count. */
656	pBeg = (uint16_t *)buf;
657	pEnd = pBeg + len - 1;
658	for (len = len / 2; len; --len)
659	{
660	temp = *pBeg;
661	pBeg++ = pEnd;
662	*pEnd-- = temp;
663	}
664	}
665
666	/**
667	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
668	*/
669	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
670	void *pvBuffer, uint32_t off, uint32_t cbBlock)
671	{
672	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
673	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
674	DMAChannel *ch = &dc->ChState[uChannel & 3];
675	uint32_t page, pagehi;
676	uint32_t addr;
677
678	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
679
680	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
681
682	/* Build the address for this transfer. */
683	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
684	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
685	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
686
687	if (IS_MODE_DEC(ch->u8Mode))
688	{
689	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
690	if (dc->is16bit)
691	dmaReverseBuf16(pvBuffer, cbBlock);
692	else
693	dmaReverseBuf8(pvBuffer, cbBlock);
694	}
695	else
696	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
697
698	PDMCritSectLeave(pDevIns->pCritSectRoR3);
699	return cbBlock;
700	}
701
702	/**
703	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
704	*/
705	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
706	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
707	{
708	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
709	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
710	DMAChannel *ch = &dc->ChState[uChannel & 3];
711	uint32_t page, pagehi;
712	uint32_t addr;
713
714	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
715	if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
716	{
717	Log(("DMA verify transfer, ignoring write.\n"));
718	return cbBlock;
719	}
720
721	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
722
723	/* Build the address for this transfer. */
724	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
725	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
726	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
727
728	if (IS_MODE_DEC(ch->u8Mode))
729	{
730	//@todo: This would need a temporary buffer.
731	Assert(0);
732	#if 0
733	if (dc->is16bit)
734	dmaReverseBuf16(pvBuffer, cbBlock);
735	else
736	dmaReverseBuf8(pvBuffer, cbBlock);
737	#endif
738	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
739	}
740	else
741	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
742
743	PDMCritSectLeave(pDevIns->pCritSectRoR3);
744	return cbBlock;
745	}
746
747	/**
748	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
749	*/
750	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
751	{
752	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
753	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
754	int chidx;
755
756	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
757
758	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
759	chidx = uChannel & 3;
760	if (uLevel)
761	dc->u8Status \|= 1 << (chidx + 4);
762	else
763	dc->u8Status &= ~(1 << (chidx + 4));
764	PDMCritSectLeave(pDevIns->pCritSectRoR3);
765	}
766
767	/**
768	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
769	*/
770	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
771	{
772	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
773
774	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
775
776	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
777	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
778	PDMCritSectLeave(pDevIns->pCritSectRoR3);
779	return u8Mode;
780	}
781
782
783	/**
784	* @interface_method_impl{PDMDEVREG,pfnReset}
785	*/
786	static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
787	{
788	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
789
790	LogFlow(("dmaReset: pThis=%p\n", pThis));
791
792	/* NB: The page and address registers are unaffected by a reset
793	* and in an undefined state after power-up.
794	*/
795	dmaClear(&pThis->DMAC[0]);
796	dmaClear(&pThis->DMAC[1]);
797	}
798
799	/** Register DMA I/O port handlers. */
800	static void dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
801	{
802	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
803	DMAControl *dc8 = &pThis->DMAC[0];
804	DMAControl *dc16 = &pThis->DMAC[1];
805
806	dc8->is16bit = false;
807	dc16->is16bit = true;
808
809	/* Base and current address for each channel. */
810	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
811	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
812
813	/* Control registers for both DMA controllers. */
814	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
815	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
816
817	/* Page registers for each channel (plus a few unused ones). */
818	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
819	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
820
821	/* Optional EISA style high page registers (address bits 24-31). */
822	if (fHighPage)
823	{
824	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
825	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
826	}
827	}
828
829	static void dmaSaveController(PSSMHANDLE pSSM, DMAControl *dc)
830	{
831	int chidx;
832
833	/* Save controller state... */
834	SSMR3PutU8(pSSM, dc->u8Command);
835	SSMR3PutU8(pSSM, dc->u8Mask);
836	SSMR3PutU8(pSSM, dc->fHiByte);
837	SSMR3PutU32(pSSM, dc->is16bit);
838	SSMR3PutU8(pSSM, dc->u8Status);
839	SSMR3PutU8(pSSM, dc->u8Temp);
840	SSMR3PutU8(pSSM, dc->u8ModeCtr);
841	SSMR3PutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
842	SSMR3PutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
843
844	/* ...and all four of its channels. */
845	for (chidx = 0; chidx < 4; ++chidx)
846	{
847	DMAChannel *ch = &dc->ChState[chidx];
848
849	SSMR3PutU16(pSSM, ch->u16CurAddr);
850	SSMR3PutU16(pSSM, ch->u16CurCount);
851	SSMR3PutU16(pSSM, ch->u16BaseAddr);
852	SSMR3PutU16(pSSM, ch->u16BaseCount);
853	SSMR3PutU8(pSSM, ch->u8Mode);
854	}
855	}
856
857	static int dmaLoadController(PSSMHANDLE pSSM, DMAControl *dc, int version)
858	{
859	uint8_t u8val;
860	uint32_t u32val;
861	int chidx;
862
863	SSMR3GetU8(pSSM, &dc->u8Command);
864	SSMR3GetU8(pSSM, &dc->u8Mask);
865	SSMR3GetU8(pSSM, &u8val);
866	dc->fHiByte = !!u8val;
867	SSMR3GetU32(pSSM, &dc->is16bit);
868	if (version > DMA_SAVESTATE_OLD)
869	{
870	SSMR3GetU8(pSSM, &dc->u8Status);
871	SSMR3GetU8(pSSM, &dc->u8Temp);
872	SSMR3GetU8(pSSM, &dc->u8ModeCtr);
873	SSMR3GetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
874	SSMR3GetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
875	}
876
877	for (chidx = 0; chidx < 4; ++chidx)
878	{
879	DMAChannel *ch = &dc->ChState[chidx];
880
881	if (version == DMA_SAVESTATE_OLD)
882	{
883	/* Convert from 17-bit to 16-bit format. */
884	SSMR3GetU32(pSSM, &u32val);
885	ch->u16CurAddr = u32val >> dc->is16bit;
886	SSMR3GetU32(pSSM, &u32val);
887	ch->u16CurCount = u32val >> dc->is16bit;
888	}
889	else
890	{
891	SSMR3GetU16(pSSM, &ch->u16CurAddr);
892	SSMR3GetU16(pSSM, &ch->u16CurCount);
893	}
894	SSMR3GetU16(pSSM, &ch->u16BaseAddr);
895	SSMR3GetU16(pSSM, &ch->u16BaseCount);
896	SSMR3GetU8(pSSM, &ch->u8Mode);
897	/* Convert from old save state. */
898	if (version == DMA_SAVESTATE_OLD)
899	{
900	/* Remap page register contents. */
901	SSMR3GetU8(pSSM, &u8val);
902	dc->au8Page[DMACX2PG(chidx)] = u8val;
903	SSMR3GetU8(pSSM, &u8val);
904	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
905	/* Throw away dack, eop. */
906	SSMR3GetU8(pSSM, &u8val);
907	SSMR3GetU8(pSSM, &u8val);
908	}
909	}
910	return 0;
911	}
912
913	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
914	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
915	{
916	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
917
918	dmaSaveController(pSSM, &pThis->DMAC[0]);
919	dmaSaveController(pSSM, &pThis->DMAC[1]);
920	return VINF_SUCCESS;
921	}
922
923	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
924	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
925	{
926	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
927
928	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
929	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
930
931	dmaLoadController(pSSM, &pThis->DMAC[0], uVersion);
932	return dmaLoadController(pSSM, &pThis->DMAC[1], uVersion);
933	}
934
935	/**
936	* @interface_method_impl{PDMDEVREG,pfnConstruct}
937	*/
938	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
939	{
940	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
941	bool bHighPage = false;
942	PDMDMACREG reg;
943	int rc;
944
945	pThis->pDevIns = pDevIns;
946
947	/*
948	* Validate configuration.
949	*/
950	if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
951	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
952
953	#if 0
954	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
955	if (RT_FAILURE (rc))
956	return rc;
957	#endif
958
959	dmaIORegister(pDevIns, bHighPage);
960	dmaReset(pDevIns);
961
962	reg.u32Version = PDM_DMACREG_VERSION;
963	reg.pfnRun = dmaRun;
964	reg.pfnRegister = dmaRegister;
965	reg.pfnReadMemory = dmaReadMemory;
966	reg.pfnWriteMemory = dmaWriteMemory;
967	reg.pfnSetDREQ = dmaSetDREQ;
968	reg.pfnGetChannelMode = dmaGetChannelMode;
969
970	rc = PDMDevHlpDMACRegister(pDevIns, &reg, &pThis->pHlp);
971	if (RT_FAILURE (rc))
972	return rc;
973
974	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
975	if (RT_FAILURE(rc))
976	return rc;
977
978	return VINF_SUCCESS;
979	}
980
981	/**
982	* The device registration structure.
983	*/
984	const PDMDEVREG g_DeviceDMA =
985	{
986	/* u32Version */
987	PDM_DEVREG_VERSION,
988	/* szName */
989	"8237A",
990	/* szRCMod */
991	"",
992	/* szR0Mod */
993	"",
994	/* pszDescription */
995	"DMA Controller Device",
996	/* fFlags */
997	PDM_DEVREG_FLAGS_DEFAULT_BITS,
998	/* fClass */
999	PDM_DEVREG_CLASS_DMA,
1000	/* cMaxInstances */
1001	1,
1002	/* cbInstance */
1003	sizeof(DMAState),
1004	/* pfnConstruct */
1005	dmaConstruct,
1006	/* pfnDestruct */
1007	NULL,
1008	/* pfnRelocate */
1009	NULL,
1010	/* pfnMemSetup */
1011	NULL,
1012	/* pfnPowerOn */
1013	NULL,
1014	/* pfnReset */
1015	dmaReset,
1016	/* pfnSuspend */
1017	NULL,
1018	/* pfnResume */
1019	NULL,
1020	/* pfnAttach */
1021	NULL,
1022	/* pfnDetach */
1023	NULL,
1024	/* pfnQueryInterface. */
1025	NULL,
1026	/* pfnInitComplete */
1027	NULL,
1028	/* pfnPowerOff */
1029	NULL,
1030	/* pfnSoftReset */
1031	NULL,
1032	/* u32VersionEnd */
1033	PDM_DEVREG_VERSION
1034	};

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 61497

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