DevDMA.cpp@ 36204

Last change on this file since 36204 was 36204, checked in by vboxsync, 14 years ago
DMA: Reworked the DMA code, added comments, fixed minor issues, made less obfuscated.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 30.4 KB

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1	/* $Id: DevDMA.cpp 36204 2011-03-08 16:12:19Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_DMA
47	#include <VBox/vmm/pdmdev.h>
48	#include <VBox/err.h>
49
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include <stdio.h>
55	#include <stdlib.h>
56
57	#include "VBoxDD.h"
58
59
60	/* DMA Overview and notes
61	*
62	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
63	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
64	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
65	* 74LS612 extends addressing to 24 bits. That leads to well known and
66	* inconvenient DMA limitations:
67	* - DMA can only access physical memory under the 16MB line
68	* - DMA transfers must occur within a 64KB/128KB 'page'
69	*
70	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
71	* left by one, including the control registers addresses. The DMA register
72	* offsets (except for the page registers) are therefore "double spaced".
73	*
74	* Due to the address shifting, the DMA controller decodes more addresses
75	* than are usually documented, with aliasing. See the ICH8 datasheet.
76	*
77	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
78	* preventing the use of memory-to-memory DMA transfers (which use channels
79	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
80	* However, it would transfer a single byte at a time, while the CPU can
81	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
82	* compatibles, memory-to-memory DMA is not even implemented at all, and
83	* therefore has no practical use.
84	*
85	* Auto-init mode is handled implicitly; a device's transfer handler may
86	* return an end count lower than the start count.
87	*
88	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
89	* while 'chidx' refers to a DMA channel index within a controller (0-3).
90	*
91	* References:
92	* - IBM Personal Computer AT Technical Reference, 1984
93	* - Intel 8237A-5 Datasheet, 1993
94	* - Frank van Gilluwe, The Undocumented PC, 1994
95	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
96	* - Intel ICH8 Datasheet, 2007
97	*/
98
99
100	/* Saved state versions. */
101	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
102	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
103
104	/* State information for a single DMA channel. */
105	typedef struct {
106	void pvUser; / User specific context. */
107	PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
108	uint16_t u16BaseAddr; /* Base address for transfers. */
109	uint16_t u16BaseCount; /* Base count for transfers. */
110	uint16_t u16CurAddr; /* Current address. */
111	uint16_t u16CurCount; /* Current count. */
112	uint8_t u8Mode; /* Channel mode. */
113	} DMAChannel;
114
115	/* State information for a DMA controller (DMA8 or DMA16). */
116	typedef struct {
117	DMAChannel ChState[4]; /* Per-channel state. */
118	uint8_t au8Page[8]; /* Page registers (A16-A23). */
119	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
120	uint8_t u8Command; /* Command register. */
121	uint8_t u8Status; /* Status register. */
122	uint8_t u8Mask; /* Mask register. */
123	uint8_t u8Temp; /* Temporary (mem/mem) register. */
124	uint8_t u8ModeCtr; /* Mode register counter for reads. */
125	bool bHiByte; /* Byte pointer (T/F -> high/low). */
126	uint32_t is16bit; /* True for 16-bit DMA. */
127	} DMAControl;
128
129	/* Complete DMA state information. */
130	typedef struct {
131	PPDMDEVINS pDevIns; /* Device instance. */
132	PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
133	DMAControl DMAC[2]; /* Two DMA controllers. */
134	} DMAState;
135
136	/* DMA command register bits. */
137	enum {
138	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
139	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
140	CMD_DISABLE = 0x04, /* Disable controller. */
141	CMD_COMPRTIME = 0x08, /* Compressed timing. */
142	CMD_ROTPRIO = 0x10, /* Rotating priority. */
143	CMD_EXTWR = 0x20, /* Extended write. */
144	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
145	CMD_DACKHI = 0x80, /* DACK is active high if set. */
146	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
147	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
148	};
149
150	/* DMA control register offsets for read accesses. */
151	enum {
152	CTL_R_STAT, /* Read status registers. */
153	CTL_R_DMAREQ, /* Read DRQ register. */
154	CTL_R_CMD, /* Read command register. */
155	CTL_R_MODE, /* Read mode register. */
156	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
157	CTL_R_TEMP, /* Read temporary register. */
158	CTL_R_CLRMODE, /* Clear mode register counter. */
159	CTL_R_MASK /* Read all DRQ mask bits. */
160	};
161
162	/* DMA control register offsets for read accesses. */
163	enum {
164	CTL_W_CMD, /* Write command register. */
165	CTL_W_DMAREQ, /* Write DRQ register. */
166	CTL_W_MASKONE, /* Write single DRQ mask bit. */
167	CTL_W_MODE, /* Write mode register. */
168	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
169	CTL_W_MASTRCLR, /* Master clear. */
170	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
171	CTL_W_MASK /* Write all DRQ mask bits. */
172	};
173
174	/* Convert DMA channel number (0-7) to controller number (0-1). */
175	#define DMACH2C(c) (c < 4 ? 0 : 1)
176
177	static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
178	/* Map a DMA page register offset (0-7) to channel index (0-3). */
179	#define DMAPG2CX(c) (dmaChannelMap[c])
180
181	static int dmaMapChannel[4] = {7, 3, 1, 2};
182	/* Map a channel index (0-3) to DMA page register offset (0-7). */
183	#define DMACX2PG(c) (dmaMapChannel[c])
184	/* Map a channel number (0-7) to DMA page register offset (0-7). */
185	#define DMACH2PG(c) (dmaMapChannel[c & 3])
186
187	/* Test the decrement bit of mode register. */
188	#define IS_MODE_DEC(c) ((c) & 0x20)
189	/* Test the auto-init bit of mode register. */
190	#define IS_MODE_AI(c) ((c) & 0x10)
191
192	/* Perform a master clear (reset) on a DMA controller. */
193	static void dmaClear(DMAControl *dc)
194	{
195	dc->u8Command = 0;
196	dc->u8Status = 0;
197	dc->u8Temp = 0;
198	dc->u8ModeCtr = 0;
199	dc->bHiByte = false;
200	dc->u8Mask = ~0;
201	}
202
203	/* Read the byte pointer and flip it. */
204	static inline bool dmaReadBytePtr(DMAControl *dc)
205	{
206	bool bHighByte;
207
208	bHighByte = !!dc->bHiByte;
209	dc->bHiByte ^= 1;
210	return bHighByte;
211	}
212
213	/* DMA address registers writes and reads. */
214
215	static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
216	uint32_t u32, unsigned cb)
217	{
218	if (cb == 1)
219	{
220	DMAControl dc = (DMAControl )pvUser;
221	DMAChannel *ch;
222	int chidx, reg, is_count;
223
224	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
225	reg = (port >> dc->is16bit) & 0x0f;
226	chidx = reg >> 1;
227	is_count = reg & 1;
228	ch = &dc->ChState[chidx];
229	if (dmaReadBytePtr(dc))
230	{
231	/* Write the high byte. */
232	if (is_count)
233	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
234	else
235	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
236
237	ch->u16CurCount = 0;
238	ch->u16CurAddr = ch->u16BaseAddr;
239	}
240	else
241	{
242	/* Write the low byte. */
243	if (is_count)
244	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
245	else
246	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
247	}
248	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
249	port, chidx, u32));
250	}
251	else
252	{
253	/* Likely a guest bug. */
254	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
255	port, cb, u32));
256	}
257	return VINF_SUCCESS;
258	}
259
260	static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
261	uint32_t *pu32, unsigned cb)
262	{
263	if (cb == 1)
264	{
265	DMAControl dc = (DMAControl )pvUser;
266	DMAChannel *ch;
267	int chidx, reg, val, dir;
268	int bptr;
269
270	reg = (port >> dc->is16bit) & 0x0f;
271	chidx = reg >> 1;
272	ch = &dc->ChState[chidx];
273
274	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
275	if (reg & 1)
276	val = ch->u16BaseCount - ch->u16CurCount;
277	else
278	val = ch->u16CurAddr + ch->u16CurCount * dir;
279
280	bptr = dmaReadBytePtr(dc);
281	pu32 = RT_LOBYTE(val >> (bptr 8));
282
283	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
284	return VINF_SUCCESS;
285	}
286	else
287	return VERR_IOM_IOPORT_UNUSED;
288	}
289
290	/* DMA control registers writes and reads. */
291
292	static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
293	uint32_t u32, unsigned cb)
294	{
295	if (cb == 1)
296	{
297	DMAControl dc = (DMAControl )pvUser;
298	int chidx = 0;
299	int reg;
300
301	reg = ((port >> dc->is16bit) & 0x0f) - 8;
302	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
303	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
304
305	switch (reg) {
306	case CTL_W_CMD:
307	/* Unsupported commands are entirely ignored. */
308	if (u32 & CMD_UNSUPPORTED)
309	{
310	Log(("DMA command %#x is not supported, ignoring!\n", u32));
311	break;
312	}
313	dc->u8Command = u32;
314	break;
315	case CTL_W_DMAREQ:
316	chidx = u32 & 3;
317	if (u32 & 4)
318	dc->u8Status \|= 1 << (chidx + 4);
319	else
320	dc->u8Status &= ~(1 << (chidx + 4));
321	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
322	break;
323	case CTL_W_MASKONE:
324	chidx = u32 & 3;
325	if (u32 & 4)
326	dc->u8Mask \|= 1 << chidx;
327	else
328	dc->u8Mask &= ~(1 << chidx);
329	break;
330	case CTL_W_MODE:
331	{
332	int op, opmode;
333
334	chidx = u32 & 3;
335	op = (u32 >> 2) & 3;
336	opmode = (u32 >> 6) & 3;
337	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
338	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
339	IS_MODE_DEC(u32) ? "de" : "in", opmode));
340
341	dc->ChState[chidx].u8Mode = u32;
342	break;
343	}
344	case CTL_W_CLRBPTR:
345	dc->bHiByte = false;
346	break;
347	case CTL_W_MASTRCLR:
348	dmaClear(dc);
349	break;
350	case CTL_W_CLRMASK:
351	dc->u8Mask = 0;
352	break;
353	case CTL_W_MASK:
354	dc->u8Mask = u32;
355	break;
356	default:
357	Assert(0);
358	break;
359	}
360	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
361	port, chidx, u32));
362	}
363	else
364	{
365	/* Likely a guest bug. */
366	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
367	port, cb, u32));
368	}
369	return VINF_SUCCESS;
370	}
371
372	static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
373	uint32_t *pu32, unsigned cb)
374	{
375	if (cb == 1)
376	{
377	DMAControl dc = (DMAControl )pvUser;
378	uint8_t val;
379	int reg;
380
381	reg = ((port >> dc->is16bit) & 0x0f) - 8;
382	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
383
384	switch (reg) {
385	case CTL_R_STAT:
386	val = dc->u8Status;
387	dc->u8Status &= 0xf0; /* A read clears all TCs. */
388	break;
389	case CTL_R_DMAREQ:
390	val = (dc->u8Status >> 4) \| 0xf0;
391	break;
392	case CTL_R_CMD:
393	val = dc->u8Command;
394	break;
395	case CTL_R_MODE:
396	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
397	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
398	case CTL_R_SETBPTR:
399	dc->bHiByte = true;
400	break;
401	case CTL_R_TEMP:
402	val = dc->u8Temp;
403	break;
404	case CTL_R_CLRMODE:
405	dc->u8ModeCtr = 0;
406	break;
407	case CTL_R_MASK:
408	val = dc->u8Mask;
409	break;
410	default:
411	Assert(0);
412	val = 0;
413	break;
414	}
415
416	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
417	*pu32 = val;
418
419	return VINF_SUCCESS;
420	}
421	else
422	return VERR_IOM_IOPORT_UNUSED;
423	}
424
425	/* DMA page registers. There are 16 R/W page registers for compatibility with
426	* the IBM PC/AT; only some of those registers are used for DMA. The page register
427	* accessible via port 80h may be read to insert small delays or used as a scratch
428	* register by a BIOS.
429	*/
430	static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
431	uint32_t *pu32, unsigned cb)
432	{
433	if (cb == 1)
434	{
435	DMAControl dc = (DMAControl )pvUser;
436	int reg;
437
438	reg = port & 7;
439	*pu32 = dc->au8Page[reg];
440	Log2(("Read %#x to from page register %#x (channel %d)\n",
441	*pu32, port, DMAPG2CX(reg)));
442	return VINF_SUCCESS;
443	}
444	else
445	return VERR_IOM_IOPORT_UNUSED;
446	}
447
448	static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
449	uint32_t u32, unsigned cb)
450	{
451	if (cb == 1)
452	{
453	DMAControl dc = (DMAControl )pvUser;
454	int reg;
455
456	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
457	reg = port & 7;
458	dc->au8Page[reg] = u32;
459	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
460	Log2(("Wrote %#x to page register %#x (channel %d)\n",
461	u32, port, DMAPG2CX(reg)));
462	}
463	else
464	{
465	/* Likely a guest bug. */
466	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
467	port, cb, u32));
468	}
469	return VINF_SUCCESS;
470	}
471
472	/* EISA style high page registers, for extending the DMA addresses to cover
473	* the entire 32-bit address space.
474	*/
475	static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
476	uint32_t *pu32, unsigned cb)
477	{
478	if (cb == 1)
479	{
480	DMAControl dc = (DMAControl )pvUser;
481	int reg;
482
483	reg = port & 7;
484	*pu32 = dc->au8PageHi[reg];
485	Log2(("Read %#x to from high page register %#x (channel %d)\n",
486	*pu32, port, DMAPG2CX(reg)));
487	return VINF_SUCCESS;
488	}
489	else
490	return VERR_IOM_IOPORT_UNUSED;
491	}
492
493	static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
494	uint32_t u32, unsigned cb)
495	{
496	if (cb == 1)
497	{
498	DMAControl dc = (DMAControl )pvUser;
499	int reg;
500
501	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
502	reg = port & 7;
503	dc->au8PageHi[reg] = u32;
504	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
505	u32, port, DMAPG2CX(reg)));
506	}
507	else
508	{
509	/* Likely a guest bug. */
510	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
511	port, cb, u32));
512	}
513	return VINF_SUCCESS;
514	}
515
516	/* Perform any pending transfers on a single DMA channel. */
517	static void dmaRunChannel(DMAState *s, int ctlidx, int chidx)
518	{
519	DMAControl *dc = &s->DMAC[ctlidx];
520	DMAChannel *ch = &dc->ChState[chidx];
521	uint32_t start_cnt, end_cnt;
522	int opmode;
523
524	opmode = (ch->u8Mode >> 6) & 3;
525
526	Log3(("DMA address %screment, mode %d\n",
527	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
528	ch->u8Mode >> 6));
529
530	/* Addresses and counts are shifted for 16-bit channels. */
531	start_cnt = ch->u16CurCount << dc->is16bit;
532	end_cnt = ch->pfnXferHandler(s->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
533	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
534	ch->u16CurCount = end_cnt >> dc->is16bit;
535	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
536	}
537
538	static bool dmaRun(PPDMDEVINS pDevIns)
539	{
540	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
541	DMAControl *dc;
542	int ctlidx, chidx, mask;
543
544	/* Run all controllers and channels. */
545	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
546	{
547	dc = &s->DMAC[ctlidx];
548
549	/* If controller is disabled, don't even bother. */
550	if (dc->u8Command & CMD_DISABLE)
551	continue;
552
553	for (chidx = 0; chidx < 4; ++chidx)
554	{
555	mask = 1 << chidx;
556	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
557	dmaRunChannel(s, ctlidx, chidx);
558	}
559	}
560	return 0;
561	}
562
563	static void dmaRegister(PPDMDEVINS pDevIns, unsigned channel,
564	PFNDMATRANSFERHANDLER handler, void *pvUser)
565	{
566	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
567	DMAChannel *ch = &s->DMAC[DMACH2C(channel)].ChState[channel & 3];
568
569	LogFlow(("dmaRegister: s=%p channel=%u XferHandler=%p pvUser=%p\n",
570	s, channel, handler, pvUser));
571
572	ch->pfnXferHandler = handler;
573	ch->pvUser = pvUser;
574	}
575
576	/* Reverse the order of bytes in a memory buffer. */
577	static void dmaReverseBuf8(void *buf, unsigned len)
578	{
579	uint8_t pBeg, pEnd;
580	uint8_t temp;
581
582	pBeg = (uint8_t *)buf;
583	pEnd = pBeg + len - 1;
584	for (len = len / 2; len; --len)
585	{
586	temp = *pBeg;
587	pBeg++ = pEnd;
588	*pEnd-- = temp;
589	}
590	}
591
592	/* Reverse the order of words in a memory buffer. */
593	static void dmaReverseBuf16(void *buf, unsigned len)
594	{
595	uint16_t pBeg, pEnd;
596	uint16_t temp;
597
598	Assert(!(len & 1));
599	len /= 2; /* Convert to word count. */
600	pBeg = (uint16_t *)buf;
601	pEnd = pBeg + len - 1;
602	for (len = len / 2; len; --len)
603	{
604	temp = *pBeg;
605	pBeg++ = pEnd;
606	*pEnd-- = temp;
607	}
608	}
609
610	static uint32_t dmaReadMemory(PPDMDEVINS pDevIns, unsigned channel,
611	void *buf, uint32_t pos, uint32_t len)
612	{
613	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
614	DMAControl *dc = &s->DMAC[DMACH2C(channel)];
615	DMAChannel *ch = &dc->ChState[channel & 3];
616	uint32_t page, pagehi;
617	uint32_t addr;
618
619	LogFlow(("dmaReadMemory: s=%p channel=%u buf=%p pos=%u len=%u\n",
620	s, channel, buf, pos, len));
621
622	/* Build the address for this transfer. */
623	page = dc->au8Page[DMACH2PG(channel)] & ~dc->is16bit;
624	pagehi = dc->au8PageHi[DMACH2PG(channel)];
625	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
626
627	if (IS_MODE_DEC(ch->u8Mode))
628	{
629	PDMDevHlpPhysRead(s->pDevIns, addr - pos - len, buf, len);
630	if (dc->is16bit)
631	dmaReverseBuf16(buf, len);
632	else
633	dmaReverseBuf8(buf, len);
634	}
635	else
636	PDMDevHlpPhysRead(s->pDevIns, addr + pos, buf, len);
637
638	return len;
639	}
640
641	static uint32_t dmaWriteMemory(PPDMDEVINS pDevIns, unsigned channel,
642	const void *buf, uint32_t pos, uint32_t len)
643	{
644	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
645	DMAControl *dc = &s->DMAC[DMACH2C(channel)];
646	DMAChannel *ch = &dc->ChState[channel & 3];
647	uint32_t page, pagehi;
648	uint32_t addr;
649
650	LogFlow(("dmaWriteMemory: s=%p channel=%u buf=%p pos=%u len=%u\n",
651	s, channel, buf, pos, len));
652
653	/* Build the address for this transfer. */
654	page = dc->au8Page[DMACH2PG(channel)] & ~dc->is16bit;
655	pagehi = dc->au8PageHi[DMACH2PG(channel)];
656	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
657
658	if (IS_MODE_DEC(ch->u8Mode))
659	{
660	//@todo: This would need a temporary buffer.
661	Assert(0);
662	#if 0
663	if (dc->is16bit)
664	dmaReverseBuf16(buf, len);
665	else
666	dmaReverseBuf8(buf, len);
667	#endif
668	PDMDevHlpPhysWrite(s->pDevIns, addr - pos - len, buf, len);
669	}
670	else
671	PDMDevHlpPhysWrite(s->pDevIns, addr + pos, buf, len);
672
673	return len;
674	}
675
676	static void dmaSetDREQ(PPDMDEVINS pDevIns, unsigned channel, unsigned level)
677	{
678	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
679	DMAControl *dc = &s->DMAC[DMACH2C(channel)];
680	int chidx;
681
682	LogFlow(("dmaSetDREQ: s=%p channel=%u level=%u\n", s, channel, level));
683
684	chidx = channel & 3;
685	if (level)
686	dc->u8Status \|= 1 << (chidx + 4);
687	else
688	dc->u8Status &= ~(1 << (chidx + 4));
689	}
690
691	static uint8_t dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned channel)
692	{
693	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
694
695	LogFlow(("dmaGetChannelMode: s=%p channel=%u\n", s, channel));
696
697	return s->DMAC[DMACH2C(channel)].ChState[channel & 3].u8Mode;
698	}
699
700	static void dmaReset(PPDMDEVINS pDevIns)
701	{
702	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
703
704	LogFlow(("dmaReset: s=%p\n", s));
705
706	/* NB: The page and address registers are unaffected by a reset
707	* and in an undefined state after power-up.
708	*/
709	dmaClear(&s->DMAC[0]);
710	dmaClear(&s->DMAC[1]);
711	}
712
713	/* Register DMA I/O port handlers. */
714	static void dmaIORegister(PPDMDEVINS pDevIns, bool bHighPage)
715	{
716	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
717	DMAControl *dc8;
718	DMAControl *dc16;
719
720	dc8 = &s->DMAC[0];
721	dc16 = &s->DMAC[1];
722
723	dc8->is16bit = false;
724	dc16->is16bit = true;
725
726	/* Base and current address for each channel. */
727	PDMDevHlpIOPortRegister(s->pDevIns, 0x00, 8, dc8,
728	dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
729	PDMDevHlpIOPortRegister(s->pDevIns, 0xC0, 16, dc16,
730	dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
731	/* Control registers for both DMA controllers. */
732	PDMDevHlpIOPortRegister(s->pDevIns, 0x08, 8, dc8,
733	dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
734	PDMDevHlpIOPortRegister(s->pDevIns, 0xD0, 16, dc16,
735	dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
736	/* Page registers for each channel (plus a few unused ones). */
737	PDMDevHlpIOPortRegister(s->pDevIns, 0x80, 8, dc8,
738	dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
739	PDMDevHlpIOPortRegister(s->pDevIns, 0x88, 8, dc16,
740	dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
741	/* Optional EISA style high page registers (address bits 24-31). */
742	if (bHighPage)
743	{
744	PDMDevHlpIOPortRegister(s->pDevIns, 0x480, 8, dc8,
745	dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
746	PDMDevHlpIOPortRegister(s->pDevIns, 0x488, 8, dc16,
747	dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
748	}
749	}
750
751	static void dmaSaveController(PSSMHANDLE pSSMHandle, DMAControl *dc)
752	{
753	int chidx;
754
755	/* Save controller state... */
756	SSMR3PutU8(pSSMHandle, dc->u8Command);
757	SSMR3PutU8(pSSMHandle, dc->u8Mask);
758	SSMR3PutU8(pSSMHandle, dc->bHiByte);
759	SSMR3PutU32(pSSMHandle, dc->is16bit);
760	SSMR3PutU8(pSSMHandle, dc->u8Status);
761	SSMR3PutU8(pSSMHandle, dc->u8Temp);
762	SSMR3PutU8(pSSMHandle, dc->u8ModeCtr);
763	SSMR3PutMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
764	SSMR3PutMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
765
766	/* ...and all four of its channels. */
767	for (chidx = 0; chidx < 4; ++chidx)
768	{
769	DMAChannel *ch = &dc->ChState[chidx];
770
771	SSMR3PutU16(pSSMHandle, ch->u16CurAddr);
772	SSMR3PutU16(pSSMHandle, ch->u16CurCount);
773	SSMR3PutU16(pSSMHandle, ch->u16BaseAddr);
774	SSMR3PutU16(pSSMHandle, ch->u16BaseCount);
775	SSMR3PutU8(pSSMHandle, ch->u8Mode);
776	}
777	}
778
779	static int dmaLoadController(PSSMHANDLE pSSMHandle, DMAControl *dc, int version)
780	{
781	uint8_t u8val;
782	uint32_t u32val;
783	int chidx;
784
785	SSMR3GetU8(pSSMHandle, &dc->u8Command);
786	SSMR3GetU8(pSSMHandle, &dc->u8Mask);
787	SSMR3GetU8(pSSMHandle, &u8val);
788	dc->bHiByte = !!u8val;
789	SSMR3GetU32(pSSMHandle, &dc->is16bit);
790	if (version > DMA_SAVESTATE_OLD)
791	{
792	SSMR3GetU8(pSSMHandle, &dc->u8Status);
793	SSMR3GetU8(pSSMHandle, &dc->u8Temp);
794	SSMR3GetU8(pSSMHandle, &dc->u8ModeCtr);
795	SSMR3GetMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
796	SSMR3GetMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
797	}
798
799	for (chidx = 0; chidx < 4; ++chidx)
800	{
801	DMAChannel *ch = &dc->ChState[chidx];
802
803	if (version == DMA_SAVESTATE_OLD)
804	{
805	/* Convert from 17-bit to 16-bit format. */
806	SSMR3GetU32(pSSMHandle, &u32val);
807	ch->u16CurAddr = u32val >> dc->is16bit;
808	SSMR3GetU32(pSSMHandle, &u32val);
809	ch->u16CurCount = u32val >> dc->is16bit;
810	}
811	else
812	{
813	SSMR3GetU16(pSSMHandle, &ch->u16CurAddr);
814	SSMR3GetU16(pSSMHandle, &ch->u16CurCount);
815	}
816	SSMR3GetU16(pSSMHandle, &ch->u16BaseAddr);
817	SSMR3GetU16(pSSMHandle, &ch->u16BaseCount);
818	SSMR3GetU8(pSSMHandle, &ch->u8Mode);
819	/* Convert from old save state. */
820	if (version == DMA_SAVESTATE_OLD)
821	{
822	/* Remap page register contents. */
823	SSMR3GetU8(pSSMHandle, &u8val);
824	dc->au8Page[DMACX2PG(chidx)] = u8val;
825	SSMR3GetU8(pSSMHandle, &u8val);
826	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
827	/* Throw away dack, eop. */
828	SSMR3GetU8(pSSMHandle, &u8val);
829	SSMR3GetU8(pSSMHandle, &u8val);
830	}
831	}
832	return 0;
833	}
834
835	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
836	{
837	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
838
839	dmaSaveController(pSSMHandle, &s->DMAC[0]);
840	dmaSaveController(pSSMHandle, &s->DMAC[1]);
841	return VINF_SUCCESS;
842	}
843
844	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
845	uint32_t uVersion, uint32_t uPass)
846	{
847	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
848
849	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
850	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
851
852	dmaLoadController(pSSMHandle, &s->DMAC[0], uVersion);
853	return dmaLoadController(pSSMHandle, &s->DMAC[1], uVersion);
854	}
855
856	/**
857	* @interface_method_impl{PDMDEVREG,pfnConstruct}
858	*/
859	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
860	{
861	DMAState s = PDMINS_2_DATA(pDevIns, DMAState );
862	bool bHighPage = false;
863	PDMDMACREG reg;
864	int rc;
865
866	s->pDevIns = pDevIns;
867
868	/*
869	* Validate configuration.
870	*/
871	if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
872	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
873
874	#if 0
875	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
876	if (RT_FAILURE (rc))
877	return rc;
878	#endif
879
880	dmaIORegister(pDevIns, bHighPage);
881	dmaReset(pDevIns);
882
883	reg.u32Version = PDM_DMACREG_VERSION;
884	reg.pfnRun = dmaRun;
885	reg.pfnRegister = dmaRegister;
886	reg.pfnReadMemory = dmaReadMemory;
887	reg.pfnWriteMemory = dmaWriteMemory;
888	reg.pfnSetDREQ = dmaSetDREQ;
889	reg.pfnGetChannelMode = dmaGetChannelMode;
890
891	rc = PDMDevHlpDMACRegister(pDevIns, &reg, &s->pHlp);
892	if (RT_FAILURE (rc))
893	return rc;
894
895	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*s),
896	dmaSaveExec, dmaLoadExec);
897	if (RT_FAILURE(rc))
898	return rc;
899
900	return VINF_SUCCESS;
901	}
902
903	/**
904	* The device registration structure.
905	*/
906	const PDMDEVREG g_DeviceDMA =
907	{
908	/* u32Version */
909	PDM_DEVREG_VERSION,
910	/* szName */
911	"8237A",
912	/* szRCMod */
913	"",
914	/* szR0Mod */
915	"",
916	/* pszDescription */
917	"DMA Controller Device",
918	/* fFlags */
919	PDM_DEVREG_FLAGS_DEFAULT_BITS,
920	/* fClass */
921	PDM_DEVREG_CLASS_DMA,
922	/* cMaxInstances */
923	1,
924	/* cbInstance */
925	sizeof(DMAState),
926	/* pfnConstruct */
927	dmaConstruct,
928	/* pfnDestruct */
929	NULL,
930	/* pfnRelocate */
931	NULL,
932	/* pfnIOCtl */
933	NULL,
934	/* pfnPowerOn */
935	NULL,
936	/* pfnReset */
937	dmaReset,
938	/* pfnSuspend */
939	NULL,
940	/* pfnResume */
941	NULL,
942	/* pfnAttach */
943	NULL,
944	/* pfnDetach */
945	NULL,
946	/* pfnQueryInterface. */
947	NULL,
948	/* pfnInitComplete */
949	NULL,
950	/* pfnPowerOff */
951	NULL,
952	/* pfnSoftReset */
953	NULL,
954	/* u32VersionEnd */
955	PDM_DEVREG_VERSION
956	};

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 36204

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