DevDMA.cpp@ 45025

Last change on this file since 45025 was 45025, checked in by vboxsync, 12 years ago
Update PDMDEVREG initialization comment so they refer to pfnMemSetup instead of pfnIOCtl.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 32.2 KB

Line
1	/* $Id: DevDMA.cpp 45025 2013-03-13 16:45:15Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	/*******************************************************************************
44	* Header Files *
45	*******************************************************************************/
46	#define LOG_GROUP LOG_GROUP_DEV_DMA
47	#include <VBox/vmm/pdmdev.h>
48	#include <VBox/err.h>
49
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include <stdio.h>
55	#include <stdlib.h>
56
57	#include "VBoxDD.h"
58
59
60	/** @page pg_dev_dma DMA Overview and notes
61	*
62	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
63	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
64	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
65	* 74LS612 extends addressing to 24 bits. That leads to well known and
66	* inconvenient DMA limitations:
67	* - DMA can only access physical memory under the 16MB line
68	* - DMA transfers must occur within a 64KB/128KB 'page'
69	*
70	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
71	* left by one, including the control registers addresses. The DMA register
72	* offsets (except for the page registers) are therefore "double spaced".
73	*
74	* Due to the address shifting, the DMA controller decodes more addresses
75	* than are usually documented, with aliasing. See the ICH8 datasheet.
76	*
77	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
78	* preventing the use of memory-to-memory DMA transfers (which use channels
79	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
80	* However, it would transfer a single byte at a time, while the CPU can
81	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
82	* compatibles, memory-to-memory DMA is not even implemented at all, and
83	* therefore has no practical use.
84	*
85	* Auto-init mode is handled implicitly; a device's transfer handler may
86	* return an end count lower than the start count.
87	*
88	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
89	* while 'chidx' refers to a DMA channel index within a controller (0-3).
90	*
91	* References:
92	* - IBM Personal Computer AT Technical Reference, 1984
93	* - Intel 8237A-5 Datasheet, 1993
94	* - Frank van Gilluwe, The Undocumented PC, 1994
95	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
96	* - Intel ICH8 Datasheet, 2007
97	*/
98
99
100	/* Saved state versions. */
101	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
102	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
103
104	/* State information for a single DMA channel. */
105	typedef struct {
106	void pvUser; / User specific context. */
107	PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
108	uint16_t u16BaseAddr; /* Base address for transfers. */
109	uint16_t u16BaseCount; /* Base count for transfers. */
110	uint16_t u16CurAddr; /* Current address. */
111	uint16_t u16CurCount; /* Current count. */
112	uint8_t u8Mode; /* Channel mode. */
113	} DMAChannel;
114
115	/* State information for a DMA controller (DMA8 or DMA16). */
116	typedef struct {
117	DMAChannel ChState[4]; /* Per-channel state. */
118	uint8_t au8Page[8]; /* Page registers (A16-A23). */
119	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
120	uint8_t u8Command; /* Command register. */
121	uint8_t u8Status; /* Status register. */
122	uint8_t u8Mask; /* Mask register. */
123	uint8_t u8Temp; /* Temporary (mem/mem) register. */
124	uint8_t u8ModeCtr; /* Mode register counter for reads. */
125	bool fHiByte; /* Byte pointer (T/F -> high/low). */
126	uint32_t is16bit; /* True for 16-bit DMA. */
127	} DMAControl;
128
129	/* Complete DMA state information. */
130	typedef struct {
131	PPDMDEVINS pDevIns; /* Device instance. */
132	PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
133	DMAControl DMAC[2]; /* Two DMA controllers. */
134	} DMAState;
135
136	/* DMA command register bits. */
137	enum {
138	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
139	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
140	CMD_DISABLE = 0x04, /* Disable controller. */
141	CMD_COMPRTIME = 0x08, /* Compressed timing. */
142	CMD_ROTPRIO = 0x10, /* Rotating priority. */
143	CMD_EXTWR = 0x20, /* Extended write. */
144	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
145	CMD_DACKHI = 0x80, /* DACK is active high if set. */
146	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
147	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
148	};
149
150	/* DMA control register offsets for read accesses. */
151	enum {
152	CTL_R_STAT, /* Read status registers. */
153	CTL_R_DMAREQ, /* Read DRQ register. */
154	CTL_R_CMD, /* Read command register. */
155	CTL_R_MODE, /* Read mode register. */
156	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
157	CTL_R_TEMP, /* Read temporary register. */
158	CTL_R_CLRMODE, /* Clear mode register counter. */
159	CTL_R_MASK /* Read all DRQ mask bits. */
160	};
161
162	/* DMA control register offsets for read accesses. */
163	enum {
164	CTL_W_CMD, /* Write command register. */
165	CTL_W_DMAREQ, /* Write DRQ register. */
166	CTL_W_MASKONE, /* Write single DRQ mask bit. */
167	CTL_W_MODE, /* Write mode register. */
168	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
169	CTL_W_MASTRCLR, /* Master clear. */
170	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
171	CTL_W_MASK /* Write all DRQ mask bits. */
172	};
173
174	/* Convert DMA channel number (0-7) to controller number (0-1). */
175	#define DMACH2C(c) (c < 4 ? 0 : 1)
176
177	static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
178	/* Map a DMA page register offset (0-7) to channel index (0-3). */
179	#define DMAPG2CX(c) (dmaChannelMap[c])
180
181	static int dmaMapChannel[4] = {7, 3, 1, 2};
182	/* Map a channel index (0-3) to DMA page register offset (0-7). */
183	#define DMACX2PG(c) (dmaMapChannel[c])
184	/* Map a channel number (0-7) to DMA page register offset (0-7). */
185	#define DMACH2PG(c) (dmaMapChannel[c & 3])
186
187	/* Test the decrement bit of mode register. */
188	#define IS_MODE_DEC(c) ((c) & 0x20)
189	/* Test the auto-init bit of mode register. */
190	#define IS_MODE_AI(c) ((c) & 0x10)
191
192	/* Perform a master clear (reset) on a DMA controller. */
193	static void dmaClear(DMAControl *dc)
194	{
195	dc->u8Command = 0;
196	dc->u8Status = 0;
197	dc->u8Temp = 0;
198	dc->u8ModeCtr = 0;
199	dc->fHiByte = false;
200	dc->u8Mask = ~0;
201	}
202
203	/* Read the byte pointer and flip it. */
204	static inline bool dmaReadBytePtr(DMAControl *dc)
205	{
206	bool bHighByte;
207
208	bHighByte = !!dc->fHiByte;
209	dc->fHiByte ^= 1;
210	return bHighByte;
211	}
212
213	/* DMA address registers writes and reads. */
214
215	static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
216	{
217	if (cb == 1)
218	{
219	DMAControl dc = (DMAControl )pvUser;
220	DMAChannel *ch;
221	int chidx, reg, is_count;
222
223	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
224	reg = (port >> dc->is16bit) & 0x0f;
225	chidx = reg >> 1;
226	is_count = reg & 1;
227	ch = &dc->ChState[chidx];
228	if (dmaReadBytePtr(dc))
229	{
230	/* Write the high byte. */
231	if (is_count)
232	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
233	else
234	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
235
236	ch->u16CurCount = 0;
237	ch->u16CurAddr = ch->u16BaseAddr;
238	}
239	else
240	{
241	/* Write the low byte. */
242	if (is_count)
243	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
244	else
245	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
246	}
247	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
248	port, chidx, u32));
249	}
250	else
251	{
252	/* Likely a guest bug. */
253	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
254	port, cb, u32));
255	}
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
260	{
261	if (cb == 1)
262	{
263	DMAControl dc = (DMAControl )pvUser;
264	DMAChannel *ch;
265	int chidx, reg, val, dir;
266	int bptr;
267
268	reg = (port >> dc->is16bit) & 0x0f;
269	chidx = reg >> 1;
270	ch = &dc->ChState[chidx];
271
272	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
273	if (reg & 1)
274	val = ch->u16BaseCount - ch->u16CurCount;
275	else
276	val = ch->u16CurAddr + ch->u16CurCount * dir;
277
278	bptr = dmaReadBytePtr(dc);
279	pu32 = RT_LOBYTE(val >> (bptr 8));
280
281	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
282	return VINF_SUCCESS;
283	}
284	else
285	return VERR_IOM_IOPORT_UNUSED;
286	}
287
288	/* DMA control registers writes and reads. */
289
290	static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
291	uint32_t u32, unsigned cb)
292	{
293	if (cb == 1)
294	{
295	DMAControl dc = (DMAControl )pvUser;
296	int chidx = 0;
297	int reg;
298
299	reg = ((port >> dc->is16bit) & 0x0f) - 8;
300	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
301	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
302
303	switch (reg) {
304	case CTL_W_CMD:
305	/* Unsupported commands are entirely ignored. */
306	if (u32 & CMD_UNSUPPORTED)
307	{
308	Log(("DMA command %#x is not supported, ignoring!\n", u32));
309	break;
310	}
311	dc->u8Command = u32;
312	break;
313	case CTL_W_DMAREQ:
314	chidx = u32 & 3;
315	if (u32 & 4)
316	dc->u8Status \|= 1 << (chidx + 4);
317	else
318	dc->u8Status &= ~(1 << (chidx + 4));
319	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
320	break;
321	case CTL_W_MASKONE:
322	chidx = u32 & 3;
323	if (u32 & 4)
324	dc->u8Mask \|= 1 << chidx;
325	else
326	dc->u8Mask &= ~(1 << chidx);
327	break;
328	case CTL_W_MODE:
329	{
330	int op, opmode;
331
332	chidx = u32 & 3;
333	op = (u32 >> 2) & 3;
334	opmode = (u32 >> 6) & 3;
335	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
336	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
337	IS_MODE_DEC(u32) ? "de" : "in", opmode));
338
339	dc->ChState[chidx].u8Mode = u32;
340	break;
341	}
342	case CTL_W_CLRBPTR:
343	dc->fHiByte = false;
344	break;
345	case CTL_W_MASTRCLR:
346	dmaClear(dc);
347	break;
348	case CTL_W_CLRMASK:
349	dc->u8Mask = 0;
350	break;
351	case CTL_W_MASK:
352	dc->u8Mask = u32;
353	break;
354	default:
355	Assert(0);
356	break;
357	}
358	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
359	port, chidx, u32));
360	}
361	else
362	{
363	/* Likely a guest bug. */
364	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
365	port, cb, u32));
366	}
367	return VINF_SUCCESS;
368	}
369
370	static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
371	{
372	if (cb == 1)
373	{
374	DMAControl dc = (DMAControl )pvUser;
375	uint8_t val = 0;
376	int reg;
377
378	reg = ((port >> dc->is16bit) & 0x0f) - 8;
379	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
380
381	switch (reg)
382	{
383	case CTL_R_STAT:
384	val = dc->u8Status;
385	dc->u8Status &= 0xf0; /* A read clears all TCs. */
386	break;
387	case CTL_R_DMAREQ:
388	val = (dc->u8Status >> 4) \| 0xf0;
389	break;
390	case CTL_R_CMD:
391	val = dc->u8Command;
392	break;
393	case CTL_R_MODE:
394	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
395	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
396	case CTL_R_SETBPTR:
397	dc->fHiByte = true;
398	break;
399	case CTL_R_TEMP:
400	val = dc->u8Temp;
401	break;
402	case CTL_R_CLRMODE:
403	dc->u8ModeCtr = 0;
404	break;
405	case CTL_R_MASK:
406	val = dc->u8Mask;
407	break;
408	default:
409	Assert(0);
410	break;
411	}
412
413	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
414	*pu32 = val;
415
416	return VINF_SUCCESS;
417	}
418	return VERR_IOM_IOPORT_UNUSED;
419	}
420
421	/** DMA page registers. There are 16 R/W page registers for compatibility with
422	* the IBM PC/AT; only some of those registers are used for DMA. The page register
423	* accessible via port 80h may be read to insert small delays or used as a scratch
424	* register by a BIOS.
425	*/
426	static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
427	{
428	DMAControl dc = (DMAControl )pvUser;
429	int reg;
430
431	if (cb == 1)
432	{
433	reg = port & 7;
434	*pu32 = dc->au8Page[reg];
435	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
436	*pu32, port, DMAPG2CX(reg)));
437	return VINF_SUCCESS;
438	}
439
440	if (cb == 2)
441	{
442	reg = port & 7;
443	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
444	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
445	*pu32, port, DMAPG2CX(reg)));
446	return VINF_SUCCESS;
447	}
448
449	return VERR_IOM_IOPORT_UNUSED;
450	}
451
452	static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
453	{
454	DMAControl dc = (DMAControl )pvUser;
455	int reg;
456
457	if (cb == 1)
458	{
459	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
460	reg = port & 7;
461	dc->au8Page[reg] = u32;
462	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
463	Log2(("Wrote %#x to page register %#x (channel %d)\n",
464	u32, port, DMAPG2CX(reg)));
465	}
466	else if (cb == 2)
467	{
468	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
469	reg = port & 7;
470	dc->au8Page[reg] = u32;
471	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
472	reg = (port + 1) & 7;
473	dc->au8Page[reg] = u32 >> 8;
474	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
475	}
476	else
477	{
478	/* Likely a guest bug. */
479	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
480	port, cb, u32));
481	}
482	return VINF_SUCCESS;
483	}
484
485	/**
486	* EISA style high page registers, for extending the DMA addresses to cover
487	* the entire 32-bit address space.
488	*/
489	static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
490	{
491	if (cb == 1)
492	{
493	DMAControl dc = (DMAControl )pvUser;
494	int reg;
495
496	reg = port & 7;
497	*pu32 = dc->au8PageHi[reg];
498	Log2(("Read %#x to from high page register %#x (channel %d)\n",
499	*pu32, port, DMAPG2CX(reg)));
500	return VINF_SUCCESS;
501	}
502	return VERR_IOM_IOPORT_UNUSED;
503	}
504
505	static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
506	{
507	if (cb == 1)
508	{
509	DMAControl dc = (DMAControl )pvUser;
510	int reg;
511
512	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
513	reg = port & 7;
514	dc->au8PageHi[reg] = u32;
515	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
516	u32, port, DMAPG2CX(reg)));
517	}
518	else
519	{
520	/* Likely a guest bug. */
521	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
522	port, cb, u32));
523	}
524	return VINF_SUCCESS;
525	}
526
527	/** Perform any pending transfers on a single DMA channel. */
528	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
529	{
530	DMAControl *dc = &pThis->DMAC[ctlidx];
531	DMAChannel *ch = &dc->ChState[chidx];
532	uint32_t start_cnt, end_cnt;
533	int opmode;
534
535	opmode = (ch->u8Mode >> 6) & 3;
536
537	Log3(("DMA address %screment, mode %d\n",
538	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
539	ch->u8Mode >> 6));
540
541	/* Addresses and counts are shifted for 16-bit channels. */
542	start_cnt = ch->u16CurCount << dc->is16bit;
543	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
544	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
545	ch->u16CurCount = end_cnt >> dc->is16bit;
546	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
547	}
548
549	/**
550	* @interface_method_impl{PDMDMAREG,pfnRun}
551	*/
552	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
553	{
554	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
555	DMAControl *dc;
556	int ctlidx, chidx, mask;
557	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
558
559	/* Run all controllers and channels. */
560	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
561	{
562	dc = &pThis->DMAC[ctlidx];
563
564	/* If controller is disabled, don't even bother. */
565	if (dc->u8Command & CMD_DISABLE)
566	continue;
567
568	for (chidx = 0; chidx < 4; ++chidx)
569	{
570	mask = 1 << chidx;
571	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
572	dmaRunChannel(pThis, ctlidx, chidx);
573	}
574	}
575
576	PDMCritSectLeave(pDevIns->pCritSectRoR3);
577	return 0;
578	}
579
580	/**
581	* @interface_method_impl{PDMDMAREG,pfnRegister}
582	*/
583	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
584	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
585	{
586	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
587	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
588
589	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
590
591	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
592	ch->pfnXferHandler = pfnTransferHandler;
593	ch->pvUser = pvUser;
594	PDMCritSectLeave(pDevIns->pCritSectRoR3);
595	}
596
597	/** Reverse the order of bytes in a memory buffer. */
598	static void dmaReverseBuf8(void *buf, unsigned len)
599	{
600	uint8_t pBeg, pEnd;
601	uint8_t temp;
602
603	pBeg = (uint8_t *)buf;
604	pEnd = pBeg + len - 1;
605	for (len = len / 2; len; --len)
606	{
607	temp = *pBeg;
608	pBeg++ = pEnd;
609	*pEnd-- = temp;
610	}
611	}
612
613	/** Reverse the order of words in a memory buffer. */
614	static void dmaReverseBuf16(void *buf, unsigned len)
615	{
616	uint16_t pBeg, pEnd;
617	uint16_t temp;
618
619	Assert(!(len & 1));
620	len /= 2; /* Convert to word count. */
621	pBeg = (uint16_t *)buf;
622	pEnd = pBeg + len - 1;
623	for (len = len / 2; len; --len)
624	{
625	temp = *pBeg;
626	pBeg++ = pEnd;
627	*pEnd-- = temp;
628	}
629	}
630
631	/**
632	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
633	*/
634	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
635	void *pvBuffer, uint32_t off, uint32_t cbBlock)
636	{
637	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
638	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
639	DMAChannel *ch = &dc->ChState[uChannel & 3];
640	uint32_t page, pagehi;
641	uint32_t addr;
642
643	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
644
645	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
646
647	/* Build the address for this transfer. */
648	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
649	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
650	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
651
652	if (IS_MODE_DEC(ch->u8Mode))
653	{
654	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
655	if (dc->is16bit)
656	dmaReverseBuf16(pvBuffer, cbBlock);
657	else
658	dmaReverseBuf8(pvBuffer, cbBlock);
659	}
660	else
661	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
662
663	PDMCritSectLeave(pDevIns->pCritSectRoR3);
664	return cbBlock;
665	}
666
667	/**
668	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
669	*/
670	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
671	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
672	{
673	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
674	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
675	DMAChannel *ch = &dc->ChState[uChannel & 3];
676	uint32_t page, pagehi;
677	uint32_t addr;
678
679	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
680	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
681
682	/* Build the address for this transfer. */
683	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
684	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
685	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
686
687	if (IS_MODE_DEC(ch->u8Mode))
688	{
689	//@todo: This would need a temporary buffer.
690	Assert(0);
691	#if 0
692	if (dc->is16bit)
693	dmaReverseBuf16(pvBuffer, cbBlock);
694	else
695	dmaReverseBuf8(pvBuffer, cbBlock);
696	#endif
697	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
698	}
699	else
700	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
701
702	PDMCritSectLeave(pDevIns->pCritSectRoR3);
703	return cbBlock;
704	}
705
706	/**
707	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
708	*/
709	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
710	{
711	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
712	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
713	int chidx;
714
715	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
716
717	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
718	chidx = uChannel & 3;
719	if (uLevel)
720	dc->u8Status \|= 1 << (chidx + 4);
721	else
722	dc->u8Status &= ~(1 << (chidx + 4));
723	PDMCritSectLeave(pDevIns->pCritSectRoR3);
724	}
725
726	/**
727	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
728	*/
729	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
730	{
731	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
732
733	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
734
735	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
736	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
737	PDMCritSectLeave(pDevIns->pCritSectRoR3);
738	return u8Mode;
739	}
740
741
742	/**
743	* @interface_method_impl{PDMDEVREG,pfnReset}
744	*/
745	static void dmaReset(PPDMDEVINS pDevIns)
746	{
747	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
748
749	LogFlow(("dmaReset: pThis=%p\n", pThis));
750
751	/* NB: The page and address registers are unaffected by a reset
752	* and in an undefined state after power-up.
753	*/
754	dmaClear(&pThis->DMAC[0]);
755	dmaClear(&pThis->DMAC[1]);
756	}
757
758	/** Register DMA I/O port handlers. */
759	static void dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
760	{
761	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
762	DMAControl *dc8 = &pThis->DMAC[0];
763	DMAControl *dc16 = &pThis->DMAC[1];
764
765	dc8->is16bit = false;
766	dc16->is16bit = true;
767
768	/* Base and current address for each channel. */
769	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
770	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
771
772	/* Control registers for both DMA controllers. */
773	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
774	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
775
776	/* Page registers for each channel (plus a few unused ones). */
777	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
778	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
779
780	/* Optional EISA style high page registers (address bits 24-31). */
781	if (fHighPage)
782	{
783	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
784	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
785	}
786	}
787
788	static void dmaSaveController(PSSMHANDLE pSSMHandle, DMAControl *dc)
789	{
790	int chidx;
791
792	/* Save controller state... */
793	SSMR3PutU8(pSSMHandle, dc->u8Command);
794	SSMR3PutU8(pSSMHandle, dc->u8Mask);
795	SSMR3PutU8(pSSMHandle, dc->fHiByte);
796	SSMR3PutU32(pSSMHandle, dc->is16bit);
797	SSMR3PutU8(pSSMHandle, dc->u8Status);
798	SSMR3PutU8(pSSMHandle, dc->u8Temp);
799	SSMR3PutU8(pSSMHandle, dc->u8ModeCtr);
800	SSMR3PutMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
801	SSMR3PutMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
802
803	/* ...and all four of its channels. */
804	for (chidx = 0; chidx < 4; ++chidx)
805	{
806	DMAChannel *ch = &dc->ChState[chidx];
807
808	SSMR3PutU16(pSSMHandle, ch->u16CurAddr);
809	SSMR3PutU16(pSSMHandle, ch->u16CurCount);
810	SSMR3PutU16(pSSMHandle, ch->u16BaseAddr);
811	SSMR3PutU16(pSSMHandle, ch->u16BaseCount);
812	SSMR3PutU8(pSSMHandle, ch->u8Mode);
813	}
814	}
815
816	static int dmaLoadController(PSSMHANDLE pSSMHandle, DMAControl *dc, int version)
817	{
818	uint8_t u8val;
819	uint32_t u32val;
820	int chidx;
821
822	SSMR3GetU8(pSSMHandle, &dc->u8Command);
823	SSMR3GetU8(pSSMHandle, &dc->u8Mask);
824	SSMR3GetU8(pSSMHandle, &u8val);
825	dc->fHiByte = !!u8val;
826	SSMR3GetU32(pSSMHandle, &dc->is16bit);
827	if (version > DMA_SAVESTATE_OLD)
828	{
829	SSMR3GetU8(pSSMHandle, &dc->u8Status);
830	SSMR3GetU8(pSSMHandle, &dc->u8Temp);
831	SSMR3GetU8(pSSMHandle, &dc->u8ModeCtr);
832	SSMR3GetMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
833	SSMR3GetMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
834	}
835
836	for (chidx = 0; chidx < 4; ++chidx)
837	{
838	DMAChannel *ch = &dc->ChState[chidx];
839
840	if (version == DMA_SAVESTATE_OLD)
841	{
842	/* Convert from 17-bit to 16-bit format. */
843	SSMR3GetU32(pSSMHandle, &u32val);
844	ch->u16CurAddr = u32val >> dc->is16bit;
845	SSMR3GetU32(pSSMHandle, &u32val);
846	ch->u16CurCount = u32val >> dc->is16bit;
847	}
848	else
849	{
850	SSMR3GetU16(pSSMHandle, &ch->u16CurAddr);
851	SSMR3GetU16(pSSMHandle, &ch->u16CurCount);
852	}
853	SSMR3GetU16(pSSMHandle, &ch->u16BaseAddr);
854	SSMR3GetU16(pSSMHandle, &ch->u16BaseCount);
855	SSMR3GetU8(pSSMHandle, &ch->u8Mode);
856	/* Convert from old save state. */
857	if (version == DMA_SAVESTATE_OLD)
858	{
859	/* Remap page register contents. */
860	SSMR3GetU8(pSSMHandle, &u8val);
861	dc->au8Page[DMACX2PG(chidx)] = u8val;
862	SSMR3GetU8(pSSMHandle, &u8val);
863	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
864	/* Throw away dack, eop. */
865	SSMR3GetU8(pSSMHandle, &u8val);
866	SSMR3GetU8(pSSMHandle, &u8val);
867	}
868	}
869	return 0;
870	}
871
872	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
873	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
874	{
875	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
876
877	dmaSaveController(pSSMHandle, &pThis->DMAC[0]);
878	dmaSaveController(pSSMHandle, &pThis->DMAC[1]);
879	return VINF_SUCCESS;
880	}
881
882	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
883	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
884	{
885	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
886
887	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
888	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
889
890	dmaLoadController(pSSMHandle, &pThis->DMAC[0], uVersion);
891	return dmaLoadController(pSSMHandle, &pThis->DMAC[1], uVersion);
892	}
893
894	/**
895	* @interface_method_impl{PDMDEVREG,pfnConstruct}
896	*/
897	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
898	{
899	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
900	bool bHighPage = false;
901	PDMDMACREG reg;
902	int rc;
903
904	pThis->pDevIns = pDevIns;
905
906	/*
907	* Validate configuration.
908	*/
909	if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
910	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
911
912	#if 0
913	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
914	if (RT_FAILURE (rc))
915	return rc;
916	#endif
917
918	dmaIORegister(pDevIns, bHighPage);
919	dmaReset(pDevIns);
920
921	reg.u32Version = PDM_DMACREG_VERSION;
922	reg.pfnRun = dmaRun;
923	reg.pfnRegister = dmaRegister;
924	reg.pfnReadMemory = dmaReadMemory;
925	reg.pfnWriteMemory = dmaWriteMemory;
926	reg.pfnSetDREQ = dmaSetDREQ;
927	reg.pfnGetChannelMode = dmaGetChannelMode;
928
929	rc = PDMDevHlpDMACRegister(pDevIns, &reg, &pThis->pHlp);
930	if (RT_FAILURE (rc))
931	return rc;
932
933	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
934	if (RT_FAILURE(rc))
935	return rc;
936
937	return VINF_SUCCESS;
938	}
939
940	/**
941	* The device registration structure.
942	*/
943	const PDMDEVREG g_DeviceDMA =
944	{
945	/* u32Version */
946	PDM_DEVREG_VERSION,
947	/* szName */
948	"8237A",
949	/* szRCMod */
950	"",
951	/* szR0Mod */
952	"",
953	/* pszDescription */
954	"DMA Controller Device",
955	/* fFlags */
956	PDM_DEVREG_FLAGS_DEFAULT_BITS,
957	/* fClass */
958	PDM_DEVREG_CLASS_DMA,
959	/* cMaxInstances */
960	1,
961	/* cbInstance */
962	sizeof(DMAState),
963	/* pfnConstruct */
964	dmaConstruct,
965	/* pfnDestruct */
966	NULL,
967	/* pfnRelocate */
968	NULL,
969	/* pfnMemSetup */
970	NULL,
971	/* pfnPowerOn */
972	NULL,
973	/* pfnReset */
974	dmaReset,
975	/* pfnSuspend */
976	NULL,
977	/* pfnResume */
978	NULL,
979	/* pfnAttach */
980	NULL,
981	/* pfnDetach */
982	NULL,
983	/* pfnQueryInterface. */
984	NULL,
985	/* pfnInitComplete */
986	NULL,
987	/* pfnPowerOff */
988	NULL,
989	/* pfnSoftReset */
990	NULL,
991	/* u32VersionEnd */
992	PDM_DEVREG_VERSION
993	};

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 45025

Download in other formats: