DevDMA.cpp@ 67789

Last change on this file since 67789 was 65916, checked in by vboxsync, 8 years ago
DevDMA: missing break (harmless because most likely not used by any guest)
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1	/* $Id: DevDMA.cpp 65916 2017-03-01 16:31:19Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_DMA
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/err.h>
50
51	#include <VBox/log.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include <stdio.h>
56	#include <stdlib.h>
57
58	#include "VBoxDD.h"
59
60
61	/** @page pg_dev_dma DMA Overview and notes
62	*
63	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
64	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
65	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
66	* 74LS612 extends addressing to 24 bits. That leads to well known and
67	* inconvenient DMA limitations:
68	* - DMA can only access physical memory under the 16MB line
69	* - DMA transfers must occur within a 64KB/128KB 'page'
70	*
71	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
72	* left by one, including the control registers addresses. The DMA register
73	* offsets (except for the page registers) are therefore "double spaced".
74	*
75	* Due to the address shifting, the DMA controller decodes more addresses
76	* than are usually documented, with aliasing. See the ICH8 datasheet.
77	*
78	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
79	* preventing the use of memory-to-memory DMA transfers (which use channels
80	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
81	* However, it would transfer a single byte at a time, while the CPU can
82	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
83	* compatibles, memory-to-memory DMA is not even implemented at all, and
84	* therefore has no practical use.
85	*
86	* Auto-init mode is handled implicitly; a device's transfer handler may
87	* return an end count lower than the start count.
88	*
89	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
90	* while 'chidx' refers to a DMA channel index within a controller (0-3).
91	*
92	* References:
93	* - IBM Personal Computer AT Technical Reference, 1984
94	* - Intel 8237A-5 Datasheet, 1993
95	* - Frank van Gilluwe, The Undocumented PC, 1994
96	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
97	* - Intel ICH8 Datasheet, 2007
98	*/
99
100
101	/* Saved state versions. */
102	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
103	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
104
105	/* State information for a single DMA channel. */
106	typedef struct {
107	void pvUser; / User specific context. */
108	PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
109	uint16_t u16BaseAddr; /* Base address for transfers. */
110	uint16_t u16BaseCount; /* Base count for transfers. */
111	uint16_t u16CurAddr; /* Current address. */
112	uint16_t u16CurCount; /* Current count. */
113	uint8_t u8Mode; /* Channel mode. */
114	} DMAChannel;
115
116	/* State information for a DMA controller (DMA8 or DMA16). */
117	typedef struct {
118	DMAChannel ChState[4]; /* Per-channel state. */
119	uint8_t au8Page[8]; /* Page registers (A16-A23). */
120	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
121	uint8_t u8Command; /* Command register. */
122	uint8_t u8Status; /* Status register. */
123	uint8_t u8Mask; /* Mask register. */
124	uint8_t u8Temp; /* Temporary (mem/mem) register. */
125	uint8_t u8ModeCtr; /* Mode register counter for reads. */
126	bool fHiByte; /* Byte pointer (T/F -> high/low). */
127	uint32_t is16bit; /* True for 16-bit DMA. */
128	} DMAControl;
129
130	/* Complete DMA state information. */
131	typedef struct {
132	PPDMDEVINS pDevIns; /* Device instance. */
133	PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
134	DMAControl DMAC[2]; /* Two DMA controllers. */
135	} DMAState;
136
137	/* DMA command register bits. */
138	enum {
139	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
140	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
141	CMD_DISABLE = 0x04, /* Disable controller. */
142	CMD_COMPRTIME = 0x08, /* Compressed timing. */
143	CMD_ROTPRIO = 0x10, /* Rotating priority. */
144	CMD_EXTWR = 0x20, /* Extended write. */
145	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
146	CMD_DACKHI = 0x80, /* DACK is active high if set. */
147	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
148	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
149	};
150
151	/* DMA control register offsets for read accesses. */
152	enum {
153	CTL_R_STAT, /* Read status registers. */
154	CTL_R_DMAREQ, /* Read DRQ register. */
155	CTL_R_CMD, /* Read command register. */
156	CTL_R_MODE, /* Read mode register. */
157	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
158	CTL_R_TEMP, /* Read temporary register. */
159	CTL_R_CLRMODE, /* Clear mode register counter. */
160	CTL_R_MASK /* Read all DRQ mask bits. */
161	};
162
163	/* DMA control register offsets for read accesses. */
164	enum {
165	CTL_W_CMD, /* Write command register. */
166	CTL_W_DMAREQ, /* Write DRQ register. */
167	CTL_W_MASKONE, /* Write single DRQ mask bit. */
168	CTL_W_MODE, /* Write mode register. */
169	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
170	CTL_W_MASTRCLR, /* Master clear. */
171	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
172	CTL_W_MASK /* Write all DRQ mask bits. */
173	};
174
175	/* DMA transfer modes. */
176	enum {
177	DMODE_DEMAND, /* Demand transfer mode. */
178	DMODE_SINGLE, /* Single transfer mode. */
179	DMODE_BLOCK, /* Block transfer mode. */
180	DMODE_CASCADE /* Cascade mode. */
181	};
182
183	/* DMA transfer types. */
184	enum {
185	DTYPE_VERIFY, /* Verify transfer type. */
186	DTYPE_WRITE, /* Write transfer type. */
187	DTYPE_READ, /* Read transfer type. */
188	DTYPE_ILLEGAL /* Undefined. */
189	};
190
191	/* Convert DMA channel number (0-7) to controller number (0-1). */
192	#define DMACH2C(c) (c < 4 ? 0 : 1)
193
194	#ifdef LOG_ENABLED
195	static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
196	/* Map a DMA page register offset (0-7) to channel index (0-3). */
197	#define DMAPG2CX(c) (dmaChannelMap[c])
198	#endif
199
200	static int dmaMapChannel[4] = {7, 3, 1, 2};
201	/* Map a channel index (0-3) to DMA page register offset (0-7). */
202	#define DMACX2PG(c) (dmaMapChannel[c])
203	/* Map a channel number (0-7) to DMA page register offset (0-7). */
204	#define DMACH2PG(c) (dmaMapChannel[c & 3])
205
206	/* Test the decrement bit of mode register. */
207	#define IS_MODE_DEC(c) ((c) & 0x20)
208	/* Test the auto-init bit of mode register. */
209	#define IS_MODE_AI(c) ((c) & 0x10)
210	/* Extract the transfer type bits of mode register. */
211	#define GET_MODE_XTYP(c)(((c) & 0x0c) >> 2)
212
213
214	/* Perform a master clear (reset) on a DMA controller. */
215	static void dmaClear(DMAControl *dc)
216	{
217	dc->u8Command = 0;
218	dc->u8Status = 0;
219	dc->u8Temp = 0;
220	dc->u8ModeCtr = 0;
221	dc->fHiByte = false;
222	dc->u8Mask = UINT8_MAX;
223	}
224
225
226	/** Read the byte pointer and flip it. */
227	DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
228	{
229	bool bHighByte;
230
231	bHighByte = !!dc->fHiByte;
232	dc->fHiByte ^= 1;
233	return bHighByte;
234	}
235
236
237	/* DMA address registers writes and reads. */
238
239	/**
240	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
241	*/
242	static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
243	{
244	RT_NOREF(pDevIns);
245	if (cb == 1)
246	{
247	DMAControl dc = (DMAControl )pvUser;
248	DMAChannel *ch;
249	int chidx, reg, is_count;
250
251	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
252	reg = (port >> dc->is16bit) & 0x0f;
253	chidx = reg >> 1;
254	is_count = reg & 1;
255	ch = &dc->ChState[chidx];
256	if (dmaReadBytePtr(dc))
257	{
258	/* Write the high byte. */
259	if (is_count)
260	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
261	else
262	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
263
264	ch->u16CurCount = 0;
265	ch->u16CurAddr = ch->u16BaseAddr;
266	}
267	else
268	{
269	/* Write the low byte. */
270	if (is_count)
271	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
272	else
273	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
274	}
275	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
276	port, chidx, u32));
277	}
278	else
279	{
280	/* Likely a guest bug. */
281	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
282	port, cb, u32));
283	}
284	return VINF_SUCCESS;
285	}
286
287
288	/**
289	* @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
290	*/
291	static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
292	{
293	RT_NOREF(pDevIns);
294	if (cb == 1)
295	{
296	DMAControl dc = (DMAControl )pvUser;
297	DMAChannel *ch;
298	int chidx, reg, val, dir;
299	int bptr;
300
301	reg = (port >> dc->is16bit) & 0x0f;
302	chidx = reg >> 1;
303	ch = &dc->ChState[chidx];
304
305	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
306	if (reg & 1)
307	val = ch->u16BaseCount - ch->u16CurCount;
308	else
309	val = ch->u16CurAddr + ch->u16CurCount * dir;
310
311	bptr = dmaReadBytePtr(dc);
312	pu32 = RT_LOBYTE(val >> (bptr 8));
313
314	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
315	return VINF_SUCCESS;
316	}
317	return VERR_IOM_IOPORT_UNUSED;
318	}
319
320	/* DMA control registers writes and reads. */
321
322	/**
323	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
324	*/
325	static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
326	{
327	RT_NOREF(pDevIns);
328	if (cb == 1)
329	{
330	DMAControl dc = (DMAControl )pvUser;
331	int chidx = 0;
332	int reg;
333
334	reg = ((port >> dc->is16bit) & 0x0f) - 8;
335	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
336	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
337
338	switch (reg) {
339	case CTL_W_CMD:
340	/* Unsupported commands are entirely ignored. */
341	if (u32 & CMD_UNSUPPORTED)
342	{
343	Log(("DMA command %#x is not supported, ignoring!\n", u32));
344	break;
345	}
346	dc->u8Command = u32;
347	break;
348	case CTL_W_DMAREQ:
349	chidx = u32 & 3;
350	if (u32 & 4)
351	dc->u8Status \|= 1 << (chidx + 4);
352	else
353	dc->u8Status &= ~(1 << (chidx + 4));
354	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
355	break;
356	case CTL_W_MASKONE:
357	chidx = u32 & 3;
358	if (u32 & 4)
359	dc->u8Mask \|= 1 << chidx;
360	else
361	dc->u8Mask &= ~(1 << chidx);
362	break;
363	case CTL_W_MODE:
364	{
365	int op, opmode;
366
367	chidx = u32 & 3;
368	op = (u32 >> 2) & 3;
369	opmode = (u32 >> 6) & 3;
370	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
371	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
372	IS_MODE_DEC(u32) ? "de" : "in", opmode));
373
374	dc->ChState[chidx].u8Mode = u32;
375	break;
376	}
377	case CTL_W_CLRBPTR:
378	dc->fHiByte = false;
379	break;
380	case CTL_W_MASTRCLR:
381	dmaClear(dc);
382	break;
383	case CTL_W_CLRMASK:
384	dc->u8Mask = 0;
385	break;
386	case CTL_W_MASK:
387	dc->u8Mask = u32;
388	break;
389	default:
390	Assert(0);
391	break;
392	}
393	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
394	port, chidx, u32));
395	}
396	else
397	{
398	/* Likely a guest bug. */
399	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
400	port, cb, u32));
401	}
402	return VINF_SUCCESS;
403	}
404
405
406	/**
407	* @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
408	*/
409	static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
410	{
411	RT_NOREF(pDevIns);
412	if (cb == 1)
413	{
414	DMAControl dc = (DMAControl )pvUser;
415	uint8_t val = 0;
416	int reg;
417
418	reg = ((port >> dc->is16bit) & 0x0f) - 8;
419	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
420
421	switch (reg)
422	{
423	case CTL_R_STAT:
424	val = dc->u8Status;
425	dc->u8Status &= 0xf0; /* A read clears all TCs. */
426	break;
427	case CTL_R_DMAREQ:
428	val = (dc->u8Status >> 4) \| 0xf0;
429	break;
430	case CTL_R_CMD:
431	val = dc->u8Command;
432	break;
433	case CTL_R_MODE:
434	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
435	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
436	break;
437	case CTL_R_SETBPTR:
438	dc->fHiByte = true;
439	break;
440	case CTL_R_TEMP:
441	val = dc->u8Temp;
442	break;
443	case CTL_R_CLRMODE:
444	dc->u8ModeCtr = 0;
445	break;
446	case CTL_R_MASK:
447	val = dc->u8Mask;
448	break;
449	default:
450	Assert(0);
451	break;
452	}
453
454	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
455	*pu32 = val;
456
457	return VINF_SUCCESS;
458	}
459	return VERR_IOM_IOPORT_UNUSED;
460	}
461
462	/**
463	*/
464
465	/**
466	* @callback_method_impl{FNIOMIOPORTIN,
467	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
468	*
469	* There are 16 R/W page registers for compatibility with the IBM PC/AT; only
470	* some of those registers are used for DMA. The page register accessible via
471	* port 80h may be read to insert small delays or used as a scratch register by
472	* a BIOS.
473	*/
474	static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
475	{
476	RT_NOREF(pDevIns);
477	DMAControl dc = (DMAControl )pvUser;
478	int reg;
479
480	if (cb == 1)
481	{
482	reg = port & 7;
483	*pu32 = dc->au8Page[reg];
484	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
485	*pu32, port, DMAPG2CX(reg)));
486	return VINF_SUCCESS;
487	}
488
489	if (cb == 2)
490	{
491	reg = port & 7;
492	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
493	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
494	*pu32, port, DMAPG2CX(reg)));
495	return VINF_SUCCESS;
496	}
497
498	return VERR_IOM_IOPORT_UNUSED;
499	}
500
501
502	/**
503	* @callback_method_impl{FNIOMIOPORTOUT,
504	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
505	*/
506	static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
507	{
508	RT_NOREF(pDevIns);
509	DMAControl dc = (DMAControl )pvUser;
510	int reg;
511
512	if (cb == 1)
513	{
514	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
515	reg = port & 7;
516	dc->au8Page[reg] = u32;
517	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
518	Log2(("Wrote %#x to page register %#x (channel %d)\n",
519	u32, port, DMAPG2CX(reg)));
520	}
521	else if (cb == 2)
522	{
523	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
524	reg = port & 7;
525	dc->au8Page[reg] = u32;
526	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
527	reg = (port + 1) & 7;
528	dc->au8Page[reg] = u32 >> 8;
529	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
530	}
531	else
532	{
533	/* Likely a guest bug. */
534	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
535	port, cb, u32));
536	}
537	return VINF_SUCCESS;
538	}
539
540
541	/**
542	* @callback_method_impl{FNIOMIOPORTIN,
543	* EISA style high page registers for extending the DMA addresses to cover
544	* the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
545	*/
546	static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
547	{
548	RT_NOREF(pDevIns);
549	if (cb == 1)
550	{
551	DMAControl dc = (DMAControl )pvUser;
552	int reg;
553
554	reg = port & 7;
555	*pu32 = dc->au8PageHi[reg];
556	Log2(("Read %#x to from high page register %#x (channel %d)\n",
557	*pu32, port, DMAPG2CX(reg)));
558	return VINF_SUCCESS;
559	}
560	return VERR_IOM_IOPORT_UNUSED;
561	}
562
563
564	/**
565	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
566	*/
567	static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
568	{
569	RT_NOREF(pDevIns);
570	if (cb == 1)
571	{
572	DMAControl dc = (DMAControl )pvUser;
573	int reg;
574
575	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
576	reg = port & 7;
577	dc->au8PageHi[reg] = u32;
578	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
579	u32, port, DMAPG2CX(reg)));
580	}
581	else
582	{
583	/* Likely a guest bug. */
584	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
585	port, cb, u32));
586	}
587	return VINF_SUCCESS;
588	}
589
590	/** Perform any pending transfers on a single DMA channel. */
591	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
592	{
593	DMAControl *dc = &pThis->DMAC[ctlidx];
594	DMAChannel *ch = &dc->ChState[chidx];
595	uint32_t start_cnt, end_cnt;
596	int opmode;
597
598	opmode = (ch->u8Mode >> 6) & 3;
599
600	Log3(("DMA address %screment, mode %d\n",
601	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
602	ch->u8Mode >> 6));
603
604	/* Addresses and counts are shifted for 16-bit channels. */
605	start_cnt = ch->u16CurCount << dc->is16bit;
606	/* NB: The device is responsible for examining the DMA mode and not
607	* transferring more than it should if auto-init is not in use.
608	*/
609	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
610	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
611	ch->u16CurCount = end_cnt >> dc->is16bit;
612	/* Set the TC (Terminal Count) bit if transfer was completed. */
613	if (ch->u16CurCount == ch->u16BaseCount + 1)
614	switch (opmode)
615	{
616	case DMODE_DEMAND:
617	case DMODE_SINGLE:
618	case DMODE_BLOCK:
619	dc->u8Status \|= RT_BIT(chidx);
620	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
621	break;
622	default:
623	break;
624	}
625	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
626	}
627
628	/**
629	* @interface_method_impl{PDMDMAREG,pfnRun}
630	*/
631	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
632	{
633	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
634	DMAControl *dc;
635	int ctlidx, chidx, mask;
636	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
637
638	/* Run all controllers and channels. */
639	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
640	{
641	dc = &pThis->DMAC[ctlidx];
642
643	/* If controller is disabled, don't even bother. */
644	if (dc->u8Command & CMD_DISABLE)
645	continue;
646
647	for (chidx = 0; chidx < 4; ++chidx)
648	{
649	mask = 1 << chidx;
650	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
651	dmaRunChannel(pThis, ctlidx, chidx);
652	}
653	}
654
655	PDMCritSectLeave(pDevIns->pCritSectRoR3);
656	return 0;
657	}
658
659	/**
660	* @interface_method_impl{PDMDMAREG,pfnRegister}
661	*/
662	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
663	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
664	{
665	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
666	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
667
668	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
669
670	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
671	ch->pfnXferHandler = pfnTransferHandler;
672	ch->pvUser = pvUser;
673	PDMCritSectLeave(pDevIns->pCritSectRoR3);
674	}
675
676	/** Reverse the order of bytes in a memory buffer. */
677	static void dmaReverseBuf8(void *buf, unsigned len)
678	{
679	uint8_t pBeg, pEnd;
680	uint8_t temp;
681
682	pBeg = (uint8_t *)buf;
683	pEnd = pBeg + len - 1;
684	for (len = len / 2; len; --len)
685	{
686	temp = *pBeg;
687	pBeg++ = pEnd;
688	*pEnd-- = temp;
689	}
690	}
691
692	/** Reverse the order of words in a memory buffer. */
693	static void dmaReverseBuf16(void *buf, unsigned len)
694	{
695	uint16_t pBeg, pEnd;
696	uint16_t temp;
697
698	Assert(!(len & 1));
699	len /= 2; /* Convert to word count. */
700	pBeg = (uint16_t *)buf;
701	pEnd = pBeg + len - 1;
702	for (len = len / 2; len; --len)
703	{
704	temp = *pBeg;
705	pBeg++ = pEnd;
706	*pEnd-- = temp;
707	}
708	}
709
710	/**
711	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
712	*/
713	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
714	void *pvBuffer, uint32_t off, uint32_t cbBlock)
715	{
716	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
717	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
718	DMAChannel *ch = &dc->ChState[uChannel & 3];
719	uint32_t page, pagehi;
720	uint32_t addr;
721
722	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
723
724	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
725
726	/* Build the address for this transfer. */
727	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
728	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
729	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
730
731	if (IS_MODE_DEC(ch->u8Mode))
732	{
733	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
734	if (dc->is16bit)
735	dmaReverseBuf16(pvBuffer, cbBlock);
736	else
737	dmaReverseBuf8(pvBuffer, cbBlock);
738	}
739	else
740	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
741
742	PDMCritSectLeave(pDevIns->pCritSectRoR3);
743	return cbBlock;
744	}
745
746	/**
747	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
748	*/
749	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
750	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
751	{
752	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
753	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
754	DMAChannel *ch = &dc->ChState[uChannel & 3];
755	uint32_t page, pagehi;
756	uint32_t addr;
757
758	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
759	if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
760	{
761	Log(("DMA verify transfer, ignoring write.\n"));
762	return cbBlock;
763	}
764
765	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
766
767	/* Build the address for this transfer. */
768	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
769	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
770	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
771
772	if (IS_MODE_DEC(ch->u8Mode))
773	{
774	/// @todo This would need a temporary buffer.
775	Assert(0);
776	#if 0
777	if (dc->is16bit)
778	dmaReverseBuf16(pvBuffer, cbBlock);
779	else
780	dmaReverseBuf8(pvBuffer, cbBlock);
781	#endif
782	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
783	}
784	else
785	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
786
787	PDMCritSectLeave(pDevIns->pCritSectRoR3);
788	return cbBlock;
789	}
790
791	/**
792	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
793	*/
794	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
795	{
796	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
797	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
798	int chidx;
799
800	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
801
802	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
803	chidx = uChannel & 3;
804	if (uLevel)
805	dc->u8Status \|= 1 << (chidx + 4);
806	else
807	dc->u8Status &= ~(1 << (chidx + 4));
808	PDMCritSectLeave(pDevIns->pCritSectRoR3);
809	}
810
811	/**
812	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
813	*/
814	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
815	{
816	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
817
818	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
819
820	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
821	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
822	PDMCritSectLeave(pDevIns->pCritSectRoR3);
823	return u8Mode;
824	}
825
826
827	/**
828	* @interface_method_impl{PDMDEVREG,pfnReset}
829	*/
830	static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
831	{
832	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
833
834	LogFlow(("dmaReset: pThis=%p\n", pThis));
835
836	/* NB: The page and address registers are unaffected by a reset
837	* and in an undefined state after power-up.
838	*/
839	dmaClear(&pThis->DMAC[0]);
840	dmaClear(&pThis->DMAC[1]);
841	}
842
843	/** Register DMA I/O port handlers. */
844	static void dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
845	{
846	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
847	DMAControl *dc8 = &pThis->DMAC[0];
848	DMAControl *dc16 = &pThis->DMAC[1];
849
850	dc8->is16bit = false;
851	dc16->is16bit = true;
852
853	/* Base and current address for each channel. */
854	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
855	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
856
857	/* Control registers for both DMA controllers. */
858	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
859	PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
860
861	/* Page registers for each channel (plus a few unused ones). */
862	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
863	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
864
865	/* Optional EISA style high page registers (address bits 24-31). */
866	if (fHighPage)
867	{
868	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
869	PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
870	}
871	}
872
873	static void dmaSaveController(PSSMHANDLE pSSM, DMAControl *dc)
874	{
875	int chidx;
876
877	/* Save controller state... */
878	SSMR3PutU8(pSSM, dc->u8Command);
879	SSMR3PutU8(pSSM, dc->u8Mask);
880	SSMR3PutU8(pSSM, dc->fHiByte);
881	SSMR3PutU32(pSSM, dc->is16bit);
882	SSMR3PutU8(pSSM, dc->u8Status);
883	SSMR3PutU8(pSSM, dc->u8Temp);
884	SSMR3PutU8(pSSM, dc->u8ModeCtr);
885	SSMR3PutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
886	SSMR3PutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
887
888	/* ...and all four of its channels. */
889	for (chidx = 0; chidx < 4; ++chidx)
890	{
891	DMAChannel *ch = &dc->ChState[chidx];
892
893	SSMR3PutU16(pSSM, ch->u16CurAddr);
894	SSMR3PutU16(pSSM, ch->u16CurCount);
895	SSMR3PutU16(pSSM, ch->u16BaseAddr);
896	SSMR3PutU16(pSSM, ch->u16BaseCount);
897	SSMR3PutU8(pSSM, ch->u8Mode);
898	}
899	}
900
901	static int dmaLoadController(PSSMHANDLE pSSM, DMAControl *dc, int version)
902	{
903	uint8_t u8val;
904	uint32_t u32val;
905	int chidx;
906
907	SSMR3GetU8(pSSM, &dc->u8Command);
908	SSMR3GetU8(pSSM, &dc->u8Mask);
909	SSMR3GetU8(pSSM, &u8val);
910	dc->fHiByte = !!u8val;
911	SSMR3GetU32(pSSM, &dc->is16bit);
912	if (version > DMA_SAVESTATE_OLD)
913	{
914	SSMR3GetU8(pSSM, &dc->u8Status);
915	SSMR3GetU8(pSSM, &dc->u8Temp);
916	SSMR3GetU8(pSSM, &dc->u8ModeCtr);
917	SSMR3GetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
918	SSMR3GetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
919	}
920
921	for (chidx = 0; chidx < 4; ++chidx)
922	{
923	DMAChannel *ch = &dc->ChState[chidx];
924
925	if (version == DMA_SAVESTATE_OLD)
926	{
927	/* Convert from 17-bit to 16-bit format. */
928	SSMR3GetU32(pSSM, &u32val);
929	ch->u16CurAddr = u32val >> dc->is16bit;
930	SSMR3GetU32(pSSM, &u32val);
931	ch->u16CurCount = u32val >> dc->is16bit;
932	}
933	else
934	{
935	SSMR3GetU16(pSSM, &ch->u16CurAddr);
936	SSMR3GetU16(pSSM, &ch->u16CurCount);
937	}
938	SSMR3GetU16(pSSM, &ch->u16BaseAddr);
939	SSMR3GetU16(pSSM, &ch->u16BaseCount);
940	SSMR3GetU8(pSSM, &ch->u8Mode);
941	/* Convert from old save state. */
942	if (version == DMA_SAVESTATE_OLD)
943	{
944	/* Remap page register contents. */
945	SSMR3GetU8(pSSM, &u8val);
946	dc->au8Page[DMACX2PG(chidx)] = u8val;
947	SSMR3GetU8(pSSM, &u8val);
948	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
949	/* Throw away dack, eop. */
950	SSMR3GetU8(pSSM, &u8val);
951	SSMR3GetU8(pSSM, &u8val);
952	}
953	}
954	return 0;
955	}
956
957	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
958	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
959	{
960	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
961
962	dmaSaveController(pSSM, &pThis->DMAC[0]);
963	dmaSaveController(pSSM, &pThis->DMAC[1]);
964	return VINF_SUCCESS;
965	}
966
967	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
968	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
969	{
970	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
971
972	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
973	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
974
975	dmaLoadController(pSSM, &pThis->DMAC[0], uVersion);
976	return dmaLoadController(pSSM, &pThis->DMAC[1], uVersion);
977	}
978
979	/**
980	* @interface_method_impl{PDMDEVREG,pfnConstruct}
981	*/
982	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
983	{
984	RT_NOREF(iInstance);
985	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
986
987	/*
988	* Initialize data.
989	*/
990	pThis->pDevIns = pDevIns;
991
992	/*
993	* Validate configuration.
994	*/
995	if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
996	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
997
998	bool bHighPage = false;
999	#if 0
1000	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
1001	if (RT_FAILURE (rc))
1002	return rc;
1003	#endif
1004
1005	dmaIORegister(pDevIns, bHighPage);
1006	dmaReset(pDevIns);
1007
1008	PDMDMACREG Reg;
1009	Reg.u32Version = PDM_DMACREG_VERSION;
1010	Reg.pfnRun = dmaRun;
1011	Reg.pfnRegister = dmaRegister;
1012	Reg.pfnReadMemory = dmaReadMemory;
1013	Reg.pfnWriteMemory = dmaWriteMemory;
1014	Reg.pfnSetDREQ = dmaSetDREQ;
1015	Reg.pfnGetChannelMode = dmaGetChannelMode;
1016
1017	int rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
1018	if (RT_FAILURE (rc))
1019	return rc;
1020
1021	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
1022	if (RT_FAILURE(rc))
1023	return rc;
1024
1025	return VINF_SUCCESS;
1026	}
1027
1028	/**
1029	* The device registration structure.
1030	*/
1031	const PDMDEVREG g_DeviceDMA =
1032	{
1033	/* u32Version */
1034	PDM_DEVREG_VERSION,
1035	/* szName */
1036	"8237A",
1037	/* szRCMod */
1038	"",
1039	/* szR0Mod */
1040	"",
1041	/* pszDescription */
1042	"DMA Controller Device",
1043	/* fFlags */
1044	PDM_DEVREG_FLAGS_DEFAULT_BITS,
1045	/* fClass */
1046	PDM_DEVREG_CLASS_DMA,
1047	/* cMaxInstances */
1048	1,
1049	/* cbInstance */
1050	sizeof(DMAState),
1051	/* pfnConstruct */
1052	dmaConstruct,
1053	/* pfnDestruct */
1054	NULL,
1055	/* pfnRelocate */
1056	NULL,
1057	/* pfnMemSetup */
1058	NULL,
1059	/* pfnPowerOn */
1060	NULL,
1061	/* pfnReset */
1062	dmaReset,
1063	/* pfnSuspend */
1064	NULL,
1065	/* pfnResume */
1066	NULL,
1067	/* pfnAttach */
1068	NULL,
1069	/* pfnDetach */
1070	NULL,
1071	/* pfnQueryInterface. */
1072	NULL,
1073	/* pfnInitComplete */
1074	NULL,
1075	/* pfnPowerOff */
1076	NULL,
1077	/* pfnSoftReset */
1078	NULL,
1079	/* u32VersionEnd */
1080	PDM_DEVREG_VERSION
1081	};

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 67789

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