DevDMA.cpp@ 72063

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1	/* $Id: DevDMA.cpp 71809 2018-04-10 11:49:53Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_DMA
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/err.h>
50
51	#include <VBox/log.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include "VBoxDD.h"
56
57
58	/** @page pg_dev_dma DMA Overview and notes
59	*
60	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
61	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
62	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
63	* 74LS612 extends addressing to 24 bits. That leads to well known and
64	* inconvenient DMA limitations:
65	* - DMA can only access physical memory under the 16MB line
66	* - DMA transfers must occur within a 64KB/128KB 'page'
67	*
68	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
69	* left by one, including the control registers addresses. The DMA register
70	* offsets (except for the page registers) are therefore "double spaced".
71	*
72	* Due to the address shifting, the DMA controller decodes more addresses
73	* than are usually documented, with aliasing. See the ICH8 datasheet.
74	*
75	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
76	* preventing the use of memory-to-memory DMA transfers (which use channels
77	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
78	* However, it would transfer a single byte at a time, while the CPU can
79	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
80	* compatibles, memory-to-memory DMA is not even implemented at all, and
81	* therefore has no practical use.
82	*
83	* Auto-init mode is handled implicitly; a device's transfer handler may
84	* return an end count lower than the start count.
85	*
86	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
87	* while 'chidx' refers to a DMA channel index within a controller (0-3).
88	*
89	* References:
90	* - IBM Personal Computer AT Technical Reference, 1984
91	* - Intel 8237A-5 Datasheet, 1993
92	* - Frank van Gilluwe, The Undocumented PC, 1994
93	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
94	* - Intel ICH8 Datasheet, 2007
95	*/
96
97
98	/* Saved state versions. */
99	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
100	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
101
102	/* State information for a single DMA channel. */
103	typedef struct {
104	RTR3PTR pvUser; /* User specific context. */
105	R3PTRTYPE(PFNDMATRANSFERHANDLER) pfnXferHandler; /* Transfer handler for channel. */
106	uint16_t u16BaseAddr; /* Base address for transfers. */
107	uint16_t u16BaseCount; /* Base count for transfers. */
108	uint16_t u16CurAddr; /* Current address. */
109	uint16_t u16CurCount; /* Current count. */
110	uint8_t u8Mode; /* Channel mode. */
111	uint8_t abPadding[7];
112	} DMAChannel;
113
114	/* State information for a DMA controller (DMA8 or DMA16). */
115	typedef struct {
116	DMAChannel ChState[4]; /* Per-channel state. */
117	uint8_t au8Page[8]; /* Page registers (A16-A23). */
118	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
119	uint8_t u8Command; /* Command register. */
120	uint8_t u8Status; /* Status register. */
121	uint8_t u8Mask; /* Mask register. */
122	uint8_t u8Temp; /* Temporary (mem/mem) register. */
123	uint8_t u8ModeCtr; /* Mode register counter for reads. */
124	bool fHiByte; /* Byte pointer (T/F -> high/low). */
125	uint8_t abPadding0[2];
126	uint32_t is16bit; /* True for 16-bit DMA. */
127	uint8_t abPadding1[4];
128	} DMAControl;
129
130	/* Complete DMA state information. */
131	typedef struct {
132	PPDMDEVINSR3 pDevIns; /* Device instance. */
133	R3PTRTYPE(PCPDMDMACHLP) pHlp; /* PDM DMA helpers. */
134	DMAControl DMAC[2]; /* Two DMA controllers. */
135	bool fRZEnabled;
136	uint8_t abPadding[7];
137	} DMAState;
138
139	/* DMA command register bits. */
140	enum {
141	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
142	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
143	CMD_DISABLE = 0x04, /* Disable controller. */
144	CMD_COMPRTIME = 0x08, /* Compressed timing. */
145	CMD_ROTPRIO = 0x10, /* Rotating priority. */
146	CMD_EXTWR = 0x20, /* Extended write. */
147	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
148	CMD_DACKHI = 0x80, /* DACK is active high if set. */
149	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
150	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
151	};
152
153	/* DMA control register offsets for read accesses. */
154	enum {
155	CTL_R_STAT, /* Read status registers. */
156	CTL_R_DMAREQ, /* Read DRQ register. */
157	CTL_R_CMD, /* Read command register. */
158	CTL_R_MODE, /* Read mode register. */
159	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
160	CTL_R_TEMP, /* Read temporary register. */
161	CTL_R_CLRMODE, /* Clear mode register counter. */
162	CTL_R_MASK /* Read all DRQ mask bits. */
163	};
164
165	/* DMA control register offsets for read accesses. */
166	enum {
167	CTL_W_CMD, /* Write command register. */
168	CTL_W_DMAREQ, /* Write DRQ register. */
169	CTL_W_MASKONE, /* Write single DRQ mask bit. */
170	CTL_W_MODE, /* Write mode register. */
171	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
172	CTL_W_MASTRCLR, /* Master clear. */
173	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
174	CTL_W_MASK /* Write all DRQ mask bits. */
175	};
176
177	/* DMA transfer modes. */
178	enum {
179	DMODE_DEMAND, /* Demand transfer mode. */
180	DMODE_SINGLE, /* Single transfer mode. */
181	DMODE_BLOCK, /* Block transfer mode. */
182	DMODE_CASCADE /* Cascade mode. */
183	};
184
185	/* DMA transfer types. */
186	enum {
187	DTYPE_VERIFY, /* Verify transfer type. */
188	DTYPE_WRITE, /* Write transfer type. */
189	DTYPE_READ, /* Read transfer type. */
190	DTYPE_ILLEGAL /* Undefined. */
191	};
192
193	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
194
195
196	/* Convert DMA channel number (0-7) to controller number (0-1). */
197	#define DMACH2C(c) (c < 4 ? 0 : 1)
198
199	#ifdef LOG_ENABLED
200	static int const g_aiDmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
201	/* Map a DMA page register offset (0-7) to channel index (0-3). */
202	# define DMAPG2CX(c) (g_aiDmaChannelMap[c])
203	#endif
204
205	#ifdef IN_RING3
206	static int const g_aiDmaMapChannel[4] = {7, 3, 1, 2};
207	/* Map a channel index (0-3) to DMA page register offset (0-7). */
208	# define DMACX2PG(c) (g_aiDmaMapChannel[c])
209	/* Map a channel number (0-7) to DMA page register offset (0-7). */
210	# define DMACH2PG(c) (g_aiDmaMapChannel[c & 3])
211	#endif
212
213	/* Test the decrement bit of mode register. */
214	#define IS_MODE_DEC(c) ((c) & 0x20)
215	/* Test the auto-init bit of mode register. */
216	#define IS_MODE_AI(c) ((c) & 0x10)
217	/* Extract the transfer type bits of mode register. */
218	#define GET_MODE_XTYP(c) (((c) & 0x0c) >> 2)
219
220
221	/* Perform a master clear (reset) on a DMA controller. */
222	static void dmaClear(DMAControl *dc)
223	{
224	dc->u8Command = 0;
225	dc->u8Status = 0;
226	dc->u8Temp = 0;
227	dc->u8ModeCtr = 0;
228	dc->fHiByte = false;
229	dc->u8Mask = UINT8_MAX;
230	}
231
232
233	/** Read the byte pointer and flip it. */
234	DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
235	{
236	bool fHighByte = !!dc->fHiByte;
237	dc->fHiByte ^= 1;
238	return fHighByte;
239	}
240
241
242	/* DMA address registers writes and reads. */
243
244	/**
245	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
246	*/
247	PDMBOTHCBDECL(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
248	{
249	RT_NOREF(pDevIns);
250	if (cb == 1)
251	{
252	DMAControl dc = (DMAControl )pvUser;
253	DMAChannel *ch;
254	int chidx, reg, is_count;
255
256	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
257	reg = (port >> dc->is16bit) & 0x0f;
258	chidx = reg >> 1;
259	is_count = reg & 1;
260	ch = &dc->ChState[chidx];
261	if (dmaReadBytePtr(dc))
262	{
263	/* Write the high byte. */
264	if (is_count)
265	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
266	else
267	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
268
269	ch->u16CurCount = 0;
270	ch->u16CurAddr = ch->u16BaseAddr;
271	}
272	else
273	{
274	/* Write the low byte. */
275	if (is_count)
276	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
277	else
278	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
279	}
280	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
281	port, chidx, u32));
282	}
283	else
284	{
285	/* Likely a guest bug. */
286	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
287	port, cb, u32));
288	}
289	return VINF_SUCCESS;
290	}
291
292
293	/**
294	* @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
295	*/
296	PDMBOTHCBDECL(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
297	{
298	RT_NOREF(pDevIns);
299	if (cb == 1)
300	{
301	DMAControl dc = (DMAControl )pvUser;
302	DMAChannel *ch;
303	int chidx, reg, val, dir;
304	int bptr;
305
306	reg = (port >> dc->is16bit) & 0x0f;
307	chidx = reg >> 1;
308	ch = &dc->ChState[chidx];
309
310	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
311	if (reg & 1)
312	val = ch->u16BaseCount - ch->u16CurCount;
313	else
314	val = ch->u16CurAddr + ch->u16CurCount * dir;
315
316	bptr = dmaReadBytePtr(dc);
317	pu32 = RT_LOBYTE(val >> (bptr 8));
318
319	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
320	return VINF_SUCCESS;
321	}
322	return VERR_IOM_IOPORT_UNUSED;
323	}
324
325	/* DMA control registers writes and reads. */
326
327	/**
328	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
329	*/
330	PDMBOTHCBDECL(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
331	{
332	RT_NOREF(pDevIns);
333	if (cb == 1)
334	{
335	DMAControl dc = (DMAControl )pvUser;
336	int chidx = 0;
337	int reg;
338
339	reg = ((port >> dc->is16bit) & 0x0f) - 8;
340	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
341	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
342
343	switch (reg) {
344	case CTL_W_CMD:
345	/* Unsupported commands are entirely ignored. */
346	if (u32 & CMD_UNSUPPORTED)
347	{
348	Log(("DMA command %#x is not supported, ignoring!\n", u32));
349	break;
350	}
351	dc->u8Command = u32;
352	break;
353	case CTL_W_DMAREQ:
354	chidx = u32 & 3;
355	if (u32 & 4)
356	dc->u8Status \|= 1 << (chidx + 4);
357	else
358	dc->u8Status &= ~(1 << (chidx + 4));
359	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
360	break;
361	case CTL_W_MASKONE:
362	chidx = u32 & 3;
363	if (u32 & 4)
364	dc->u8Mask \|= 1 << chidx;
365	else
366	dc->u8Mask &= ~(1 << chidx);
367	break;
368	case CTL_W_MODE:
369	{
370	int op, opmode;
371
372	chidx = u32 & 3;
373	op = (u32 >> 2) & 3;
374	opmode = (u32 >> 6) & 3;
375	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
376	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
377	IS_MODE_DEC(u32) ? "de" : "in", opmode));
378
379	dc->ChState[chidx].u8Mode = u32;
380	break;
381	}
382	case CTL_W_CLRBPTR:
383	dc->fHiByte = false;
384	break;
385	case CTL_W_MASTRCLR:
386	dmaClear(dc);
387	break;
388	case CTL_W_CLRMASK:
389	dc->u8Mask = 0;
390	break;
391	case CTL_W_MASK:
392	dc->u8Mask = u32;
393	break;
394	default:
395	Assert(0);
396	break;
397	}
398	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
399	port, chidx, u32));
400	}
401	else
402	{
403	/* Likely a guest bug. */
404	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
405	port, cb, u32));
406	}
407	return VINF_SUCCESS;
408	}
409
410
411	/**
412	* @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
413	*/
414	PDMBOTHCBDECL(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
415	{
416	RT_NOREF(pDevIns);
417	if (cb == 1)
418	{
419	DMAControl dc = (DMAControl )pvUser;
420	uint8_t val = 0;
421	int reg;
422
423	reg = ((port >> dc->is16bit) & 0x0f) - 8;
424	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
425
426	switch (reg)
427	{
428	case CTL_R_STAT:
429	val = dc->u8Status;
430	dc->u8Status &= 0xf0; /* A read clears all TCs. */
431	break;
432	case CTL_R_DMAREQ:
433	val = (dc->u8Status >> 4) \| 0xf0;
434	break;
435	case CTL_R_CMD:
436	val = dc->u8Command;
437	break;
438	case CTL_R_MODE:
439	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
440	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
441	break;
442	case CTL_R_SETBPTR:
443	dc->fHiByte = true;
444	break;
445	case CTL_R_TEMP:
446	val = dc->u8Temp;
447	break;
448	case CTL_R_CLRMODE:
449	dc->u8ModeCtr = 0;
450	break;
451	case CTL_R_MASK:
452	val = dc->u8Mask;
453	break;
454	default:
455	Assert(0);
456	break;
457	}
458
459	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
460	*pu32 = val;
461
462	return VINF_SUCCESS;
463	}
464	return VERR_IOM_IOPORT_UNUSED;
465	}
466
467
468
469	/**
470	* @callback_method_impl{FNIOMIOPORTIN,
471	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
472	*
473	* There are 16 R/W page registers for compatibility with the IBM PC/AT; only
474	* some of those registers are used for DMA. The page register accessible via
475	* port 80h may be read to insert small delays or used as a scratch register by
476	* a BIOS.
477	*/
478	PDMBOTHCBDECL(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
479	{
480	RT_NOREF(pDevIns);
481	DMAControl dc = (DMAControl )pvUser;
482	int reg;
483
484	if (cb == 1)
485	{
486	reg = port & 7;
487	*pu32 = dc->au8Page[reg];
488	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
489	*pu32, port, DMAPG2CX(reg)));
490	return VINF_SUCCESS;
491	}
492
493	if (cb == 2)
494	{
495	reg = port & 7;
496	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
497	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
498	*pu32, port, DMAPG2CX(reg)));
499	return VINF_SUCCESS;
500	}
501
502	return VERR_IOM_IOPORT_UNUSED;
503	}
504
505
506	/**
507	* @callback_method_impl{FNIOMIOPORTOUT,
508	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
509	*/
510	PDMBOTHCBDECL(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
511	{
512	RT_NOREF(pDevIns);
513	DMAControl dc = (DMAControl )pvUser;
514	int reg;
515
516	if (cb == 1)
517	{
518	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
519	reg = port & 7;
520	dc->au8Page[reg] = u32;
521	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
522	Log2(("Wrote %#x to page register %#x (channel %d)\n",
523	u32, port, DMAPG2CX(reg)));
524	}
525	else if (cb == 2)
526	{
527	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
528	reg = port & 7;
529	dc->au8Page[reg] = u32;
530	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
531	reg = (port + 1) & 7;
532	dc->au8Page[reg] = u32 >> 8;
533	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
534	}
535	else
536	{
537	/* Likely a guest bug. */
538	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
539	port, cb, u32));
540	}
541	return VINF_SUCCESS;
542	}
543
544
545	/**
546	* @callback_method_impl{FNIOMIOPORTIN,
547	* EISA style high page registers for extending the DMA addresses to cover
548	* the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
549	*/
550	PDMBOTHCBDECL(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
551	{
552	RT_NOREF(pDevIns);
553	if (cb == 1)
554	{
555	DMAControl dc = (DMAControl )pvUser;
556	int reg;
557
558	reg = port & 7;
559	*pu32 = dc->au8PageHi[reg];
560	Log2(("Read %#x to from high page register %#x (channel %d)\n",
561	*pu32, port, DMAPG2CX(reg)));
562	return VINF_SUCCESS;
563	}
564	return VERR_IOM_IOPORT_UNUSED;
565	}
566
567
568	/**
569	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
570	*/
571	PDMBOTHCBDECL(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
572	{
573	RT_NOREF(pDevIns);
574	if (cb == 1)
575	{
576	DMAControl dc = (DMAControl )pvUser;
577	int reg;
578
579	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
580	reg = port & 7;
581	dc->au8PageHi[reg] = u32;
582	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
583	u32, port, DMAPG2CX(reg)));
584	}
585	else
586	{
587	/* Likely a guest bug. */
588	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
589	port, cb, u32));
590	}
591	return VINF_SUCCESS;
592	}
593
594
595	#ifdef IN_RING3
596
597	/** Perform any pending transfers on a single DMA channel. */
598	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
599	{
600	DMAControl *dc = &pThis->DMAC[ctlidx];
601	DMAChannel *ch = &dc->ChState[chidx];
602	uint32_t start_cnt, end_cnt;
603	int opmode;
604
605	opmode = (ch->u8Mode >> 6) & 3;
606
607	Log3(("DMA address %screment, mode %d\n",
608	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
609	ch->u8Mode >> 6));
610
611	/* Addresses and counts are shifted for 16-bit channels. */
612	start_cnt = ch->u16CurCount << dc->is16bit;
613	/* NB: The device is responsible for examining the DMA mode and not
614	* transferring more than it should if auto-init is not in use.
615	*/
616	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
617	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
618	ch->u16CurCount = end_cnt >> dc->is16bit;
619	/* Set the TC (Terminal Count) bit if transfer was completed. */
620	if (ch->u16CurCount == ch->u16BaseCount + 1)
621	switch (opmode)
622	{
623	case DMODE_DEMAND:
624	case DMODE_SINGLE:
625	case DMODE_BLOCK:
626	dc->u8Status \|= RT_BIT(chidx);
627	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
628	break;
629	default:
630	break;
631	}
632	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
633	}
634
635	/**
636	* @interface_method_impl{PDMDMAREG,pfnRun}
637	*/
638	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
639	{
640	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
641	DMAControl *dc;
642	int ctlidx, chidx, mask;
643	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
644
645	/* Run all controllers and channels. */
646	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
647	{
648	dc = &pThis->DMAC[ctlidx];
649
650	/* If controller is disabled, don't even bother. */
651	if (dc->u8Command & CMD_DISABLE)
652	continue;
653
654	for (chidx = 0; chidx < 4; ++chidx)
655	{
656	mask = 1 << chidx;
657	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
658	dmaRunChannel(pThis, ctlidx, chidx);
659	}
660	}
661
662	PDMCritSectLeave(pDevIns->pCritSectRoR3);
663	return 0;
664	}
665
666	/**
667	* @interface_method_impl{PDMDMAREG,pfnRegister}
668	*/
669	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
670	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
671	{
672	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
673	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
674
675	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
676
677	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
678	ch->pfnXferHandler = pfnTransferHandler;
679	ch->pvUser = pvUser;
680	PDMCritSectLeave(pDevIns->pCritSectRoR3);
681	}
682
683	/** Reverse the order of bytes in a memory buffer. */
684	static void dmaReverseBuf8(void *buf, unsigned len)
685	{
686	uint8_t pBeg, pEnd;
687	uint8_t temp;
688
689	pBeg = (uint8_t *)buf;
690	pEnd = pBeg + len - 1;
691	for (len = len / 2; len; --len)
692	{
693	temp = *pBeg;
694	pBeg++ = pEnd;
695	*pEnd-- = temp;
696	}
697	}
698
699	/** Reverse the order of words in a memory buffer. */
700	static void dmaReverseBuf16(void *buf, unsigned len)
701	{
702	uint16_t pBeg, pEnd;
703	uint16_t temp;
704
705	Assert(!(len & 1));
706	len /= 2; /* Convert to word count. */
707	pBeg = (uint16_t *)buf;
708	pEnd = pBeg + len - 1;
709	for (len = len / 2; len; --len)
710	{
711	temp = *pBeg;
712	pBeg++ = pEnd;
713	*pEnd-- = temp;
714	}
715	}
716
717	/**
718	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
719	*/
720	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
721	void *pvBuffer, uint32_t off, uint32_t cbBlock)
722	{
723	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
724	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
725	DMAChannel *ch = &dc->ChState[uChannel & 3];
726	uint32_t page, pagehi;
727	uint32_t addr;
728
729	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
730
731	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
732
733	/* Build the address for this transfer. */
734	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
735	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
736	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
737
738	if (IS_MODE_DEC(ch->u8Mode))
739	{
740	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
741	if (dc->is16bit)
742	dmaReverseBuf16(pvBuffer, cbBlock);
743	else
744	dmaReverseBuf8(pvBuffer, cbBlock);
745	}
746	else
747	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
748
749	PDMCritSectLeave(pDevIns->pCritSectRoR3);
750	return cbBlock;
751	}
752
753	/**
754	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
755	*/
756	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
757	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
758	{
759	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
760	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
761	DMAChannel *ch = &dc->ChState[uChannel & 3];
762	uint32_t page, pagehi;
763	uint32_t addr;
764
765	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
766	if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
767	{
768	Log(("DMA verify transfer, ignoring write.\n"));
769	return cbBlock;
770	}
771
772	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
773
774	/* Build the address for this transfer. */
775	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
776	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
777	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
778
779	if (IS_MODE_DEC(ch->u8Mode))
780	{
781	/// @todo This would need a temporary buffer.
782	Assert(0);
783	#if 0
784	if (dc->is16bit)
785	dmaReverseBuf16(pvBuffer, cbBlock);
786	else
787	dmaReverseBuf8(pvBuffer, cbBlock);
788	#endif
789	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
790	}
791	else
792	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
793
794	PDMCritSectLeave(pDevIns->pCritSectRoR3);
795	return cbBlock;
796	}
797
798	/**
799	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
800	*/
801	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
802	{
803	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
804	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
805	int chidx;
806
807	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
808
809	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
810	chidx = uChannel & 3;
811	if (uLevel)
812	dc->u8Status \|= 1 << (chidx + 4);
813	else
814	dc->u8Status &= ~(1 << (chidx + 4));
815	PDMCritSectLeave(pDevIns->pCritSectRoR3);
816	}
817
818	/**
819	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
820	*/
821	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
822	{
823	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
824
825	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
826
827	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
828	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
829	PDMCritSectLeave(pDevIns->pCritSectRoR3);
830	return u8Mode;
831	}
832
833
834	/**
835	* @interface_method_impl{PDMDEVREG,pfnReset}
836	*/
837	static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
838	{
839	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
840
841	LogFlow(("dmaReset: pThis=%p\n", pThis));
842
843	/* NB: The page and address registers are unaffected by a reset
844	* and in an undefined state after power-up.
845	*/
846	dmaClear(&pThis->DMAC[0]);
847	dmaClear(&pThis->DMAC[1]);
848	}
849
850	/** Register DMA I/O port handlers. */
851	static int dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
852	{
853	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
854	DMAControl *dc8 = &pThis->DMAC[0];
855	DMAControl *dc16 = &pThis->DMAC[1];
856	int rc;
857
858	dc8->is16bit = false;
859	dc16->is16bit = true;
860
861	/* Base and current address for each channel. */
862	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
863	AssertLogRelRCReturn(rc, rc);
864	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
865	AssertLogRelRCReturn(rc, rc);
866
867	/* Control registers for both DMA controllers. */
868	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
869	AssertLogRelRCReturn(rc, rc);
870	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
871	AssertLogRelRCReturn(rc, rc);
872
873	/* Page registers for each channel (plus a few unused ones). */
874	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
875	AssertLogRelRCReturn(rc, rc);
876	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
877	AssertLogRelRCReturn(rc, rc);
878
879	/* Optional EISA style high page registers (address bits 24-31). */
880	if (fHighPage)
881	{
882	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
883	AssertLogRelRCReturn(rc, rc);
884	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
885	AssertLogRelRCReturn(rc, rc);
886	}
887
888	if (pThis->fRZEnabled)
889	{
890	/*
891	* Ditto for raw-mode.
892	*/
893	RTRCPTR RCPtrDc8 = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
894	RTRCPTR RCPtrDc16 = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
895
896	/* Base and current address for each channel. */
897	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x00, 8, RCPtrDc8, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA8 Address");
898	AssertLogRelRCReturn(rc, rc);
899	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xC0, 16, RCPtrDc16, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA16 Address");
900	AssertLogRelRCReturn(rc, rc);
901
902	/* Control registers for both DMA controllers. */
903	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x08, 8, RCPtrDc8, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA8 Control");
904	AssertLogRelRCReturn(rc, rc);
905	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xD0, 16, RCPtrDc16, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA16 Control");
906	AssertLogRelRCReturn(rc, rc);
907
908	/* Page registers for each channel (plus a few unused ones). */
909	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x80, 8, RCPtrDc8, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA8 Page");
910	AssertLogRelRCReturn(rc, rc);
911	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x88, 8, RCPtrDc16, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA16 Page");
912	AssertLogRelRCReturn(rc, rc);
913
914	/* Optional EISA style high page registers (address bits 24-31). */
915	if (fHighPage)
916	{
917	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x480, 8, RCPtrDc8, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
918	AssertLogRelRCReturn(rc, rc);
919	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x488, 8, RCPtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
920	AssertLogRelRCReturn(rc, rc);
921	}
922
923	/*
924	* Ditto for ring-0.
925	*/
926	RTR0PTR R0PtrDc8 = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
927	RTR0PTR R0PtrDc16 = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
928
929	/* Base and current address for each channel. */
930	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x00, 8, R0PtrDc8, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA8 Address");
931	AssertLogRelRCReturn(rc, rc);
932	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xC0, 16, R0PtrDc16, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA16 Address");
933	AssertLogRelRCReturn(rc, rc);
934
935	/* Control registers for both DMA controllers. */
936	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x08, 8, R0PtrDc8, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA8 Control");
937	AssertLogRelRCReturn(rc, rc);
938	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xD0, 16, R0PtrDc16, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA16 Control");
939	AssertLogRelRCReturn(rc, rc);
940
941	/* Page registers for each channel (plus a few unused ones). */
942	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x80, 8, R0PtrDc8, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA8 Page");
943	AssertLogRelRCReturn(rc, rc);
944	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x88, 8, R0PtrDc16, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA16 Page");
945	AssertLogRelRCReturn(rc, rc);
946
947	/* Optional EISA style high page registers (address bits 24-31). */
948	if (fHighPage)
949	{
950	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x480, 8, R0PtrDc8, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
951	AssertLogRelRCReturn(rc, rc);
952	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x488, 8, R0PtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
953	AssertLogRelRCReturn(rc, rc);
954	}
955	}
956
957	return VINF_SUCCESS;
958	}
959
960	static void dmaSaveController(PSSMHANDLE pSSM, DMAControl *dc)
961	{
962	int chidx;
963
964	/* Save controller state... */
965	SSMR3PutU8(pSSM, dc->u8Command);
966	SSMR3PutU8(pSSM, dc->u8Mask);
967	SSMR3PutU8(pSSM, dc->fHiByte);
968	SSMR3PutU32(pSSM, dc->is16bit);
969	SSMR3PutU8(pSSM, dc->u8Status);
970	SSMR3PutU8(pSSM, dc->u8Temp);
971	SSMR3PutU8(pSSM, dc->u8ModeCtr);
972	SSMR3PutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
973	SSMR3PutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
974
975	/* ...and all four of its channels. */
976	for (chidx = 0; chidx < 4; ++chidx)
977	{
978	DMAChannel *ch = &dc->ChState[chidx];
979
980	SSMR3PutU16(pSSM, ch->u16CurAddr);
981	SSMR3PutU16(pSSM, ch->u16CurCount);
982	SSMR3PutU16(pSSM, ch->u16BaseAddr);
983	SSMR3PutU16(pSSM, ch->u16BaseCount);
984	SSMR3PutU8(pSSM, ch->u8Mode);
985	}
986	}
987
988	static int dmaLoadController(PSSMHANDLE pSSM, DMAControl *dc, int version)
989	{
990	uint8_t u8val;
991	uint32_t u32val;
992	int chidx;
993
994	SSMR3GetU8(pSSM, &dc->u8Command);
995	SSMR3GetU8(pSSM, &dc->u8Mask);
996	SSMR3GetU8(pSSM, &u8val);
997	dc->fHiByte = !!u8val;
998	SSMR3GetU32(pSSM, &dc->is16bit);
999	if (version > DMA_SAVESTATE_OLD)
1000	{
1001	SSMR3GetU8(pSSM, &dc->u8Status);
1002	SSMR3GetU8(pSSM, &dc->u8Temp);
1003	SSMR3GetU8(pSSM, &dc->u8ModeCtr);
1004	SSMR3GetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
1005	SSMR3GetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
1006	}
1007
1008	for (chidx = 0; chidx < 4; ++chidx)
1009	{
1010	DMAChannel *ch = &dc->ChState[chidx];
1011
1012	if (version == DMA_SAVESTATE_OLD)
1013	{
1014	/* Convert from 17-bit to 16-bit format. */
1015	SSMR3GetU32(pSSM, &u32val);
1016	ch->u16CurAddr = u32val >> dc->is16bit;
1017	SSMR3GetU32(pSSM, &u32val);
1018	ch->u16CurCount = u32val >> dc->is16bit;
1019	}
1020	else
1021	{
1022	SSMR3GetU16(pSSM, &ch->u16CurAddr);
1023	SSMR3GetU16(pSSM, &ch->u16CurCount);
1024	}
1025	SSMR3GetU16(pSSM, &ch->u16BaseAddr);
1026	SSMR3GetU16(pSSM, &ch->u16BaseCount);
1027	SSMR3GetU8(pSSM, &ch->u8Mode);
1028	/* Convert from old save state. */
1029	if (version == DMA_SAVESTATE_OLD)
1030	{
1031	/* Remap page register contents. */
1032	SSMR3GetU8(pSSM, &u8val);
1033	dc->au8Page[DMACX2PG(chidx)] = u8val;
1034	SSMR3GetU8(pSSM, &u8val);
1035	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
1036	/* Throw away dack, eop. */
1037	SSMR3GetU8(pSSM, &u8val);
1038	SSMR3GetU8(pSSM, &u8val);
1039	}
1040	}
1041	return 0;
1042	}
1043
1044	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
1045	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1046	{
1047	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1048
1049	dmaSaveController(pSSM, &pThis->DMAC[0]);
1050	dmaSaveController(pSSM, &pThis->DMAC[1]);
1051	return VINF_SUCCESS;
1052	}
1053
1054	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
1055	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1056	{
1057	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1058
1059	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1060	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1061
1062	dmaLoadController(pSSM, &pThis->DMAC[0], uVersion);
1063	return dmaLoadController(pSSM, &pThis->DMAC[1], uVersion);
1064	}
1065
1066	/**
1067	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1068	*/
1069	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1070	{
1071	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1072	RT_NOREF(iInstance);
1073	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1074
1075	/*
1076	* Initialize data.
1077	*/
1078	pThis->pDevIns = pDevIns;
1079
1080	/*
1081	* Validate configuration.
1082	*/
1083	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1084	"\0")) /* "HighPageEnable\0")) */
1085	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1086
1087	bool bHighPage = false;
1088	#if 0
1089	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
1090	if (RT_FAILURE (rc))
1091	return rc;
1092	#endif
1093
1094	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
1095	AssertLogRelRCReturn(rc, rc);
1096
1097	rc = dmaIORegister(pDevIns, bHighPage);
1098	AssertLogRelRCReturn(rc, rc);
1099
1100	dmaReset(pDevIns);
1101
1102	PDMDMACREG Reg;
1103	Reg.u32Version = PDM_DMACREG_VERSION;
1104	Reg.pfnRun = dmaRun;
1105	Reg.pfnRegister = dmaRegister;
1106	Reg.pfnReadMemory = dmaReadMemory;
1107	Reg.pfnWriteMemory = dmaWriteMemory;
1108	Reg.pfnSetDREQ = dmaSetDREQ;
1109	Reg.pfnGetChannelMode = dmaGetChannelMode;
1110
1111	rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
1112	if (RT_FAILURE (rc))
1113	return rc;
1114
1115	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
1116	if (RT_FAILURE(rc))
1117	return rc;
1118
1119	return VINF_SUCCESS;
1120	}
1121
1122	/**
1123	* The device registration structure.
1124	*/
1125	const PDMDEVREG g_DeviceDMA =
1126	{
1127	/* u32Version */
1128	PDM_DEVREG_VERSION,
1129	/* szName */
1130	"8237A",
1131	/* szRCMod */
1132	"VBoxDDRC.rc",
1133	/* szR0Mod */
1134	"VBoxDDR0.r0",
1135	/* pszDescription */
1136	"DMA Controller Device",
1137	/* fFlags */
1138	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC,
1139	/* fClass */
1140	PDM_DEVREG_CLASS_DMA,
1141	/* cMaxInstances */
1142	1,
1143	/* cbInstance */
1144	sizeof(DMAState),
1145	/* pfnConstruct */
1146	dmaConstruct,
1147	/* pfnDestruct */
1148	NULL,
1149	/* pfnRelocate */
1150	NULL,
1151	/* pfnMemSetup */
1152	NULL,
1153	/* pfnPowerOn */
1154	NULL,
1155	/* pfnReset */
1156	dmaReset,
1157	/* pfnSuspend */
1158	NULL,
1159	/* pfnResume */
1160	NULL,
1161	/* pfnAttach */
1162	NULL,
1163	/* pfnDetach */
1164	NULL,
1165	/* pfnQueryInterface. */
1166	NULL,
1167	/* pfnInitComplete */
1168	NULL,
1169	/* pfnPowerOff */
1170	NULL,
1171	/* pfnSoftReset */
1172	NULL,
1173	/* u32VersionEnd */
1174	PDM_DEVREG_VERSION
1175	};
1176	#endif /* IN_RING3 */
1177	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1178

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 72063

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