DevDMA.cpp@ 81985

Last change on this file since 81985 was 81985, checked in by vboxsync, 5 years ago
DevDMA: Added some paranoia. bugref:9218
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1	/* $Id: DevDMA.cpp 81985 2019-11-19 11:07:48Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_DMA
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/err.h>
50
51	#include <VBox/AssertGuest.h>
52	#include <VBox/log.h>
53	#include <iprt/assert.h>
54	#include <iprt/string.h>
55
56	#include "VBoxDD.h"
57
58
59	/** @page pg_dev_dma DMA Overview and notes
60	*
61	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
62	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
63	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
64	* 74LS612 extends addressing to 24 bits. That leads to well known and
65	* inconvenient DMA limitations:
66	* - DMA can only access physical memory under the 16MB line
67	* - DMA transfers must occur within a 64KB/128KB 'page'
68	*
69	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
70	* left by one, including the control registers addresses. The DMA register
71	* offsets (except for the page registers) are therefore "double spaced".
72	*
73	* Due to the address shifting, the DMA controller decodes more addresses
74	* than are usually documented, with aliasing. See the ICH8 datasheet.
75	*
76	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
77	* preventing the use of memory-to-memory DMA transfers (which use channels
78	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
79	* However, it would transfer a single byte at a time, while the CPU can
80	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
81	* compatibles, memory-to-memory DMA is not even implemented at all, and
82	* therefore has no practical use.
83	*
84	* Auto-init mode is handled implicitly; a device's transfer handler may
85	* return an end count lower than the start count.
86	*
87	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
88	* while 'chidx' refers to a DMA channel index within a controller (0-3).
89	*
90	* References:
91	* - IBM Personal Computer AT Technical Reference, 1984
92	* - Intel 8237A-5 Datasheet, 1993
93	* - Frank van Gilluwe, The Undocumented PC, 1994
94	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
95	* - Intel ICH8 Datasheet, 2007
96	*/
97
98
99	/* Saved state versions. */
100	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
101	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
102
103	/* State information for a single DMA channel. */
104	typedef struct {
105	RTR3PTR pvUser; /* User specific context. */
106	R3PTRTYPE(PFNDMATRANSFERHANDLER) pfnXferHandler; /* Transfer handler for channel. */
107	uint16_t u16BaseAddr; /* Base address for transfers. */
108	uint16_t u16BaseCount; /* Base count for transfers. */
109	uint16_t u16CurAddr; /* Current address. */
110	uint16_t u16CurCount; /* Current count. */
111	uint8_t u8Mode; /* Channel mode. */
112	uint8_t abPadding[7];
113	} DMAChannel, DMACHANNEL;
114	typedef DMACHANNEL *PDMACHANNEL;
115
116	/* State information for a DMA controller (DMA8 or DMA16). */
117	typedef struct {
118	DMAChannel ChState[4]; /* Per-channel state. */
119	uint8_t au8Page[8]; /* Page registers (A16-A23). */
120	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
121	uint8_t u8Command; /* Command register. */
122	uint8_t u8Status; /* Status register. */
123	uint8_t u8Mask; /* Mask register. */
124	uint8_t u8Temp; /* Temporary (mem/mem) register. */
125	uint8_t u8ModeCtr; /* Mode register counter for reads. */
126	bool fHiByte; /* Byte pointer (T/F -> high/low). */
127	uint8_t abPadding0[2];
128	uint32_t is16bit; /* True for 16-bit DMA. */
129	uint8_t abPadding1[4];
130	/** The base abd current address I/O port registration. */
131	IOMIOPORTHANDLE hIoPortBase;
132	/** The control register I/O port registration. */
133	IOMIOPORTHANDLE hIoPortCtl;
134	/** The page registers I/O port registration. */
135	IOMIOPORTHANDLE hIoPortPage;
136	/** The EISA style high page registers I/O port registration. */
137	IOMIOPORTHANDLE hIoPortHi;
138	} DMAControl, DMACONTROLLER;
139	/** Pointer to the shared DMA controller state. */
140	typedef DMACONTROLLER *PDMACONTROLLER;
141
142	/* Complete DMA state information. */
143	typedef struct {
144	DMAControl DMAC[2]; /* Two DMA controllers. */
145	PPDMDEVINSR3 pDevIns; /* Device instance. */
146	R3PTRTYPE(PCPDMDMACHLP) pHlp; /* PDM DMA helpers. */
147	STAMPROFILE StatRun;
148	} DMAState, DMASTATE;
149	/** Pointer to the shared DMA state information. */
150	typedef DMASTATE *PDMASTATE;
151
152	/* DMA command register bits. */
153	enum {
154	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
155	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
156	CMD_DISABLE = 0x04, /* Disable controller. */
157	CMD_COMPRTIME = 0x08, /* Compressed timing. */
158	CMD_ROTPRIO = 0x10, /* Rotating priority. */
159	CMD_EXTWR = 0x20, /* Extended write. */
160	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
161	CMD_DACKHI = 0x80, /* DACK is active high if set. */
162	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
163	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
164	};
165
166	/* DMA control register offsets for read accesses. */
167	enum {
168	CTL_R_STAT, /* Read status registers. */
169	CTL_R_DMAREQ, /* Read DRQ register. */
170	CTL_R_CMD, /* Read command register. */
171	CTL_R_MODE, /* Read mode register. */
172	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
173	CTL_R_TEMP, /* Read temporary register. */
174	CTL_R_CLRMODE, /* Clear mode register counter. */
175	CTL_R_MASK /* Read all DRQ mask bits. */
176	};
177
178	/* DMA control register offsets for read accesses. */
179	enum {
180	CTL_W_CMD, /* Write command register. */
181	CTL_W_DMAREQ, /* Write DRQ register. */
182	CTL_W_MASKONE, /* Write single DRQ mask bit. */
183	CTL_W_MODE, /* Write mode register. */
184	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
185	CTL_W_MASTRCLR, /* Master clear. */
186	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
187	CTL_W_MASK /* Write all DRQ mask bits. */
188	};
189
190	/* DMA transfer modes. */
191	enum {
192	DMODE_DEMAND, /* Demand transfer mode. */
193	DMODE_SINGLE, /* Single transfer mode. */
194	DMODE_BLOCK, /* Block transfer mode. */
195	DMODE_CASCADE /* Cascade mode. */
196	};
197
198	/* DMA transfer types. */
199	enum {
200	DTYPE_VERIFY, /* Verify transfer type. */
201	DTYPE_WRITE, /* Write transfer type. */
202	DTYPE_READ, /* Read transfer type. */
203	DTYPE_ILLEGAL /* Undefined. */
204	};
205
206	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
207
208
209	/* Convert DMA channel number (0-7) to controller number (0-1). */
210	#define DMACH2C(c) (c < 4 ? 0 : 1)
211
212	#ifdef LOG_ENABLED
213	static int const g_aiDmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
214	/* Map a DMA page register offset (0-7) to channel index (0-3). */
215	# define DMAPG2CX(c) (g_aiDmaChannelMap[c])
216	#endif
217
218	#ifdef IN_RING3
219	static int const g_aiDmaMapChannel[4] = {7, 3, 1, 2};
220	/* Map a channel index (0-3) to DMA page register offset (0-7). */
221	# define DMACX2PG(c) (g_aiDmaMapChannel[c])
222	/* Map a channel number (0-7) to DMA page register offset (0-7). */
223	# define DMACH2PG(c) (g_aiDmaMapChannel[c & 3])
224	#endif
225
226	/* Test the decrement bit of mode register. */
227	#define IS_MODE_DEC(c) ((c) & 0x20)
228	/* Test the auto-init bit of mode register. */
229	#define IS_MODE_AI(c) ((c) & 0x10)
230	/* Extract the transfer type bits of mode register. */
231	#define GET_MODE_XTYP(c) (((c) & 0x0c) >> 2)
232
233
234	/* Perform a master clear (reset) on a DMA controller. */
235	static void dmaClear(DMAControl *dc)
236	{
237	dc->u8Command = 0;
238	dc->u8Status = 0;
239	dc->u8Temp = 0;
240	dc->u8ModeCtr = 0;
241	dc->fHiByte = false;
242	dc->u8Mask = UINT8_MAX;
243	}
244
245
246	/** Read the byte pointer and flip it. */
247	DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
248	{
249	bool fHighByte = !!dc->fHiByte;
250	dc->fHiByte ^= 1;
251	return fHighByte;
252	}
253
254
255	/* DMA address registers writes and reads. */
256
257	/**
258	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
259	*/
260	static DECLCALLBACK(VBOXSTRICTRC) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
261	{
262	RT_NOREF(pDevIns);
263	if (cb == 1)
264	{
265	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
266	unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
267	unsigned const chidx = reg >> 1;
268	unsigned const is_count = reg & 1;
269	PDMACHANNEL ch = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx);
270	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
271
272	if (dmaReadBytePtr(dc))
273	{
274	/* Write the high byte. */
275	if (is_count)
276	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
277	else
278	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
279
280	ch->u16CurCount = 0;
281	ch->u16CurAddr = ch->u16BaseAddr;
282	}
283	else
284	{
285	/* Write the low byte. */
286	if (is_count)
287	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
288	else
289	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
290	}
291	Log2(("dmaWriteAddr: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
292	}
293	else
294	{
295	/* Likely a guest bug. */
296	Log(("Bad size write to count register %#x (size %d, data %#x)\n", offPort, cb, u32));
297	}
298	return VINF_SUCCESS;
299	}
300
301
302	/**
303	* @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
304	*/
305	static DECLCALLBACK(VBOXSTRICTRC) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
306	{
307	RT_NOREF(pDevIns);
308	if (cb == 1)
309	{
310	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
311	unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
312	unsigned const chidx = reg >> 1;
313	PDMACHANNEL ch = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx);
314	int const dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
315	int val;
316	int bptr;
317
318	if (reg & 1)
319	val = ch->u16BaseCount - ch->u16CurCount;
320	else
321	val = ch->u16CurAddr + ch->u16CurCount * dir;
322
323	bptr = dmaReadBytePtr(dc);
324	pu32 = RT_LOBYTE(val >> (bptr 8));
325
326	Log(("Count read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
327	return VINF_SUCCESS;
328	}
329	return VERR_IOM_IOPORT_UNUSED;
330	}
331
332	/* DMA control registers writes and reads. */
333
334	/**
335	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
336	*/
337	static DECLCALLBACK(VBOXSTRICTRC) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
338	{
339	RT_NOREF(pDevIns);
340	if (cb == 1)
341	{
342	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
343	unsigned chidx = 0;
344
345	unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
346	Assert((int)reg >= CTL_W_CMD && reg <= CTL_W_MASK);
347	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
348
349	switch (reg) {
350	case CTL_W_CMD:
351	/* Unsupported commands are entirely ignored. */
352	if (u32 & CMD_UNSUPPORTED)
353	{
354	Log(("DMA command %#x is not supported, ignoring!\n", u32));
355	break;
356	}
357	dc->u8Command = u32;
358	break;
359	case CTL_W_DMAREQ:
360	chidx = u32 & 3;
361	if (u32 & 4)
362	dc->u8Status \|= 1 << (chidx + 4);
363	else
364	dc->u8Status &= ~(1 << (chidx + 4));
365	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
366	break;
367	case CTL_W_MASKONE:
368	chidx = u32 & 3;
369	if (u32 & 4)
370	dc->u8Mask \|= 1 << chidx;
371	else
372	dc->u8Mask &= ~(1 << chidx);
373	break;
374	case CTL_W_MODE:
375	chidx = u32 & 3;
376	dc->ChState[chidx].u8Mode = u32;
377	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
378	chidx, (u32 >> 2) & 3, IS_MODE_AI(u32) ? "" : "no ", IS_MODE_DEC(u32) ? "de" : "in", (u32 >> 6) & 3));
379	break;
380	case CTL_W_CLRBPTR:
381	dc->fHiByte = false;
382	break;
383	case CTL_W_MASTRCLR:
384	dmaClear(dc);
385	break;
386	case CTL_W_CLRMASK:
387	dc->u8Mask = 0;
388	break;
389	case CTL_W_MASK:
390	dc->u8Mask = u32;
391	break;
392	default:
393	ASSERT_GUEST_MSG_FAILED(("reg=%u\n", reg));
394	break;
395	}
396	Log(("dmaWriteCtl: offPort %#06x, chidx %d, data %#02x\n", offPort, chidx, u32));
397	}
398	else
399	{
400	/* Likely a guest bug. */
401	Log(("Bad size write to controller register %#x (size %d, data %#x)\n", offPort, cb, u32));
402	}
403	return VINF_SUCCESS;
404	}
405
406
407	/**
408	* @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
409	*/
410	static DECLCALLBACK(VBOXSTRICTRC) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
411	{
412	RT_NOREF(pDevIns);
413	if (cb == 1)
414	{
415	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
416	uint8_t val = 0;
417
418	unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
419	Assert((int)reg >= CTL_R_STAT && reg <= CTL_R_MASK);
420
421	switch (reg)
422	{
423	case CTL_R_STAT:
424	val = dc->u8Status;
425	dc->u8Status &= 0xf0; /* A read clears all TCs. */
426	break;
427	case CTL_R_DMAREQ:
428	val = (dc->u8Status >> 4) \| 0xf0;
429	break;
430	case CTL_R_CMD:
431	val = dc->u8Command;
432	break;
433	case CTL_R_MODE:
434	val = RT_SAFE_SUBSCRIPT(dc->ChState, dc->u8ModeCtr).u8Mode \| 3;
435	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
436	break;
437	case CTL_R_SETBPTR:
438	dc->fHiByte = true;
439	break;
440	case CTL_R_TEMP:
441	val = dc->u8Temp;
442	break;
443	case CTL_R_CLRMODE:
444	dc->u8ModeCtr = 0;
445	break;
446	case CTL_R_MASK:
447	val = dc->u8Mask;
448	break;
449	default:
450	Assert(0);
451	break;
452	}
453
454	Log(("Ctrl read: offPort %#06x, reg %#04x, data %#x\n", offPort, reg, val));
455	*pu32 = val;
456
457	return VINF_SUCCESS;
458	}
459	return VERR_IOM_IOPORT_UNUSED;
460	}
461
462
463
464	/**
465	* @callback_method_impl{FNIOMIOPORTIN,
466	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
467	*
468	* There are 16 R/W page registers for compatibility with the IBM PC/AT; only
469	* some of those registers are used for DMA. The page register accessible via
470	* port 80h may be read to insert small delays or used as a scratch register by
471	* a BIOS.
472	*/
473	static DECLCALLBACK(VBOXSTRICTRC) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
474	{
475	RT_NOREF(pDevIns);
476	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
477	int reg;
478
479	if (cb == 1)
480	{
481	reg = offPort & 7;
482	*pu32 = dc->au8Page[reg];
483	Log2(("Read %#x (byte) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
484	return VINF_SUCCESS;
485	}
486
487	if (cb == 2)
488	{
489	reg = offPort & 7;
490	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
491	Log2(("Read %#x (word) from page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
492	return VINF_SUCCESS;
493	}
494
495	return VERR_IOM_IOPORT_UNUSED;
496	}
497
498
499	/**
500	* @callback_method_impl{FNIOMIOPORTOUT,
501	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
502	*/
503	static DECLCALLBACK(VBOXSTRICTRC) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
504	{
505	RT_NOREF(pDevIns);
506	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
507	unsigned reg;
508
509	if (cb == 1)
510	{
511	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
512	reg = offPort & 7;
513	dc->au8Page[reg] = u32;
514	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
515	Log2(("Wrote %#x to page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
516	}
517	else if (cb == 2)
518	{
519	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
520	reg = offPort & 7;
521	dc->au8Page[reg] = u32;
522	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
523	reg = (offPort + 1) & 7;
524	dc->au8Page[reg] = u32 >> 8;
525	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
526	}
527	else
528	{
529	/* Likely a guest bug. */
530	Log(("Bad size write to page register %#x (size %d, data %#x)\n", offPort, cb, u32));
531	}
532	return VINF_SUCCESS;
533	}
534
535
536	/**
537	* @callback_method_impl{FNIOMIOPORTIN,
538	* EISA style high page registers for extending the DMA addresses to cover
539	* the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
540	*/
541	static DECLCALLBACK(VBOXSTRICTRC) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
542	{
543	RT_NOREF(pDevIns);
544	if (cb == 1)
545	{
546	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
547	unsigned const reg = offPort & 7;
548
549	*pu32 = dc->au8PageHi[reg];
550	Log2(("Read %#x to from high page register %#x (channel %d)\n", *pu32, offPort, DMAPG2CX(reg)));
551	return VINF_SUCCESS;
552	}
553	return VERR_IOM_IOPORT_UNUSED;
554	}
555
556
557	/**
558	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
559	*/
560	static DECLCALLBACK(VBOXSTRICTRC) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
561	{
562	RT_NOREF(pDevIns);
563	if (cb == 1)
564	{
565	PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
566	unsigned const reg = offPort & 7;
567
568	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
569	dc->au8PageHi[reg] = u32;
570	Log2(("Wrote %#x to high page register %#x (channel %d)\n", u32, offPort, DMAPG2CX(reg)));
571	}
572	else
573	{
574	/* Likely a guest bug. */
575	Log(("Bad size write to high page register %#x (size %d, data %#x)\n", offPort, cb, u32));
576	}
577	return VINF_SUCCESS;
578	}
579
580
581	#ifdef IN_RING3
582
583	/** Perform any pending transfers on a single DMA channel. */
584	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
585	{
586	DMAControl *dc = &pThis->DMAC[ctlidx];
587	DMAChannel *ch = &dc->ChState[chidx];
588	uint32_t start_cnt, end_cnt;
589	int opmode;
590
591	opmode = (ch->u8Mode >> 6) & 3;
592
593	Log3(("DMA address %screment, mode %d\n", IS_MODE_DEC(ch->u8Mode) ? "de" : "in", ch->u8Mode >> 6));
594
595	/* Addresses and counts are shifted for 16-bit channels. */
596	start_cnt = ch->u16CurCount << dc->is16bit;
597	/* NB: The device is responsible for examining the DMA mode and not
598	* transferring more than it should if auto-init is not in use.
599	*/
600	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
601	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
602	ch->u16CurCount = end_cnt >> dc->is16bit;
603	/* Set the TC (Terminal Count) bit if transfer was completed. */
604	if (ch->u16CurCount == ch->u16BaseCount + 1)
605	switch (opmode)
606	{
607	case DMODE_DEMAND:
608	case DMODE_SINGLE:
609	case DMODE_BLOCK:
610	dc->u8Status \|= RT_BIT(chidx);
611	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
612	break;
613	default:
614	break;
615	}
616	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
617	}
618
619	/**
620	* @interface_method_impl{PDMDMAREG,pfnRun}
621	*/
622	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
623	{
624	DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
625	DMAControl *dc;
626	int ctlidx, chidx, mask;
627	STAM_PROFILE_START(&pThis->StatRun, a);
628	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
629
630	/* Run all controllers and channels. */
631	for (ctlidx = 0; ctlidx < RT_ELEMENTS(pThis->DMAC); ++ctlidx)
632	{
633	dc = &pThis->DMAC[ctlidx];
634
635	/* If controller is disabled, don't even bother. */
636	if (dc->u8Command & CMD_DISABLE)
637	continue;
638
639	for (chidx = 0; chidx < 4; ++chidx)
640	{
641	mask = 1 << chidx;
642	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
643	dmaRunChannel(pThis, ctlidx, chidx);
644	}
645	}
646
647	PDMCritSectLeave(pDevIns->pCritSectRoR3);
648	STAM_PROFILE_STOP(&pThis->StatRun, a);
649	return 0;
650	}
651
652	/**
653	* @interface_method_impl{PDMDMAREG,pfnRegister}
654	*/
655	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
656	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
657	{
658	DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
659	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
660
661	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
662
663	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
664	ch->pfnXferHandler = pfnTransferHandler;
665	ch->pvUser = pvUser;
666	PDMCritSectLeave(pDevIns->pCritSectRoR3);
667	}
668
669	/** Reverse the order of bytes in a memory buffer. */
670	static void dmaReverseBuf8(void *buf, unsigned len)
671	{
672	uint8_t pBeg, pEnd;
673	uint8_t temp;
674
675	pBeg = (uint8_t *)buf;
676	pEnd = pBeg + len - 1;
677	for (len = len / 2; len; --len)
678	{
679	temp = *pBeg;
680	pBeg++ = pEnd;
681	*pEnd-- = temp;
682	}
683	}
684
685	/** Reverse the order of words in a memory buffer. */
686	static void dmaReverseBuf16(void *buf, unsigned len)
687	{
688	uint16_t pBeg, pEnd;
689	uint16_t temp;
690
691	Assert(!(len & 1));
692	len /= 2; /* Convert to word count. */
693	pBeg = (uint16_t *)buf;
694	pEnd = pBeg + len - 1;
695	for (len = len / 2; len; --len)
696	{
697	temp = *pBeg;
698	pBeg++ = pEnd;
699	*pEnd-- = temp;
700	}
701	}
702
703	/**
704	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
705	*/
706	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
707	void *pvBuffer, uint32_t off, uint32_t cbBlock)
708	{
709	DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
710	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
711	DMAChannel *ch = &dc->ChState[uChannel & 3];
712	uint32_t page, pagehi;
713	uint32_t addr;
714
715	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
716
717	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
718
719	/* Build the address for this transfer. */
720	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
721	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
722	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
723
724	if (IS_MODE_DEC(ch->u8Mode))
725	{
726	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
727	if (dc->is16bit)
728	dmaReverseBuf16(pvBuffer, cbBlock);
729	else
730	dmaReverseBuf8(pvBuffer, cbBlock);
731	}
732	else
733	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
734
735	PDMCritSectLeave(pDevIns->pCritSectRoR3);
736	return cbBlock;
737	}
738
739	/**
740	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
741	*/
742	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
743	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
744	{
745	DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
746	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
747	DMAChannel *ch = &dc->ChState[uChannel & 3];
748	uint32_t page, pagehi;
749	uint32_t addr;
750
751	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
752	if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
753	{
754	Log(("DMA verify transfer, ignoring write.\n"));
755	return cbBlock;
756	}
757
758	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
759
760	/* Build the address for this transfer. */
761	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
762	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
763	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
764
765	if (IS_MODE_DEC(ch->u8Mode))
766	{
767	/// @todo This would need a temporary buffer.
768	Assert(0);
769	#if 0
770	if (dc->is16bit)
771	dmaReverseBuf16(pvBuffer, cbBlock);
772	else
773	dmaReverseBuf8(pvBuffer, cbBlock);
774	#endif
775	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
776	}
777	else
778	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
779
780	PDMCritSectLeave(pDevIns->pCritSectRoR3);
781	return cbBlock;
782	}
783
784	/**
785	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
786	*/
787	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
788	{
789	DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
790	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
791	int chidx;
792
793	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
794
795	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
796	chidx = uChannel & 3;
797	if (uLevel)
798	dc->u8Status \|= 1 << (chidx + 4);
799	else
800	dc->u8Status &= ~(1 << (chidx + 4));
801	PDMCritSectLeave(pDevIns->pCritSectRoR3);
802	}
803
804	/**
805	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
806	*/
807	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
808	{
809	PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
810
811	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
812
813	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
814	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
815	PDMCritSectLeave(pDevIns->pCritSectRoR3);
816	return u8Mode;
817	}
818
819
820	/**
821	* @interface_method_impl{PDMDEVREG,pfnReset}
822	*/
823	static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
824	{
825	PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
826
827	LogFlow(("dmaReset: pThis=%p\n", pThis));
828
829	/* NB: The page and address registers are unaffected by a reset
830	* and in an undefined state after power-up.
831	*/
832	dmaClear(&pThis->DMAC[0]);
833	dmaClear(&pThis->DMAC[1]);
834	}
835
836	static void dmaSaveController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc)
837	{
838	int chidx;
839
840	/* Save controller state... */
841	pHlp->pfnSSMPutU8(pSSM, dc->u8Command);
842	pHlp->pfnSSMPutU8(pSSM, dc->u8Mask);
843	pHlp->pfnSSMPutU8(pSSM, dc->fHiByte);
844	pHlp->pfnSSMPutU32(pSSM, dc->is16bit);
845	pHlp->pfnSSMPutU8(pSSM, dc->u8Status);
846	pHlp->pfnSSMPutU8(pSSM, dc->u8Temp);
847	pHlp->pfnSSMPutU8(pSSM, dc->u8ModeCtr);
848	pHlp->pfnSSMPutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
849	pHlp->pfnSSMPutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
850
851	/* ...and all four of its channels. */
852	for (chidx = 0; chidx < 4; ++chidx)
853	{
854	DMAChannel *ch = &dc->ChState[chidx];
855
856	pHlp->pfnSSMPutU16(pSSM, ch->u16CurAddr);
857	pHlp->pfnSSMPutU16(pSSM, ch->u16CurCount);
858	pHlp->pfnSSMPutU16(pSSM, ch->u16BaseAddr);
859	pHlp->pfnSSMPutU16(pSSM, ch->u16BaseCount);
860	pHlp->pfnSSMPutU8(pSSM, ch->u8Mode);
861	}
862	}
863
864	static int dmaLoadController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc, int version)
865	{
866	uint8_t u8val;
867	uint32_t u32val;
868	int chidx;
869
870	pHlp->pfnSSMGetU8(pSSM, &dc->u8Command);
871	pHlp->pfnSSMGetU8(pSSM, &dc->u8Mask);
872	pHlp->pfnSSMGetU8(pSSM, &u8val);
873	dc->fHiByte = !!u8val;
874	pHlp->pfnSSMGetU32(pSSM, &dc->is16bit);
875	if (version > DMA_SAVESTATE_OLD)
876	{
877	pHlp->pfnSSMGetU8(pSSM, &dc->u8Status);
878	pHlp->pfnSSMGetU8(pSSM, &dc->u8Temp);
879	pHlp->pfnSSMGetU8(pSSM, &dc->u8ModeCtr);
880	pHlp->pfnSSMGetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
881	pHlp->pfnSSMGetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
882	}
883
884	for (chidx = 0; chidx < 4; ++chidx)
885	{
886	DMAChannel *ch = &dc->ChState[chidx];
887
888	if (version == DMA_SAVESTATE_OLD)
889	{
890	/* Convert from 17-bit to 16-bit format. */
891	pHlp->pfnSSMGetU32(pSSM, &u32val);
892	ch->u16CurAddr = u32val >> dc->is16bit;
893	pHlp->pfnSSMGetU32(pSSM, &u32val);
894	ch->u16CurCount = u32val >> dc->is16bit;
895	}
896	else
897	{
898	pHlp->pfnSSMGetU16(pSSM, &ch->u16CurAddr);
899	pHlp->pfnSSMGetU16(pSSM, &ch->u16CurCount);
900	}
901	pHlp->pfnSSMGetU16(pSSM, &ch->u16BaseAddr);
902	pHlp->pfnSSMGetU16(pSSM, &ch->u16BaseCount);
903	pHlp->pfnSSMGetU8(pSSM, &ch->u8Mode);
904	/* Convert from old save state. */
905	if (version == DMA_SAVESTATE_OLD)
906	{
907	/* Remap page register contents. */
908	pHlp->pfnSSMGetU8(pSSM, &u8val);
909	dc->au8Page[DMACX2PG(chidx)] = u8val;
910	pHlp->pfnSSMGetU8(pSSM, &u8val);
911	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
912	/* Throw away dack, eop. */
913	pHlp->pfnSSMGetU8(pSSM, &u8val);
914	pHlp->pfnSSMGetU8(pSSM, &u8val);
915	}
916	}
917	return 0;
918	}
919
920	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
921	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
922	{
923	PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
924	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
925
926	dmaSaveController(pHlp, pSSM, &pThis->DMAC[0]);
927	dmaSaveController(pHlp, pSSM, &pThis->DMAC[1]);
928	return VINF_SUCCESS;
929	}
930
931	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
932	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
933	{
934	PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
935	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
936
937	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
938	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
939
940	dmaLoadController(pHlp, pSSM, &pThis->DMAC[0], uVersion);
941	return dmaLoadController(pHlp, pSSM, &pThis->DMAC[1], uVersion);
942	}
943
944	/**
945	* @interface_method_impl{PDMDEVREG,pfnConstruct}
946	*/
947	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
948	{
949	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
950	PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
951	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
952	RT_NOREF(iInstance);
953
954	/*
955	* Initialize data.
956	*/
957	pThis->pDevIns = pDevIns;
958
959	DMAControl *pDC8 = &pThis->DMAC[0];
960	DMAControl *pDC16 = &pThis->DMAC[1];
961	pDC8->is16bit = false;
962	pDC16->is16bit = true;
963
964	/*
965	* Validate and read the configuration.
966	*/
967	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "HighPageEnable", "");
968
969	bool fHighPage = false;
970	int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HighPageEnable", &fHighPage, false);
971	AssertRCReturn(rc, rc);
972
973	/*
974	* Register I/O callbacks.
975	*/
976	/* Base and current address for each channel. */
977	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x00, 8, dmaWriteAddr, dmaReadAddr, pDC8, "DMA8 Address", NULL, &pDC8->hIoPortBase);
978	AssertLogRelRCReturn(rc, rc);
979	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xc0, 16, dmaWriteAddr, dmaReadAddr, pDC16, "DMA16 Address", NULL, &pDC16->hIoPortBase);
980	AssertLogRelRCReturn(rc, rc);
981
982	/* Control registers for both DMA controllers. */
983	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x08, 8, dmaWriteCtl, dmaReadCtl, pDC8, "DMA8 Control", NULL, &pDC8->hIoPortCtl);
984	AssertLogRelRCReturn(rc, rc);
985	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xd0, 16, dmaWriteCtl, dmaReadCtl, pDC16, "DMA16 Control", NULL, &pDC16->hIoPortCtl);
986	AssertLogRelRCReturn(rc, rc);
987
988	/* Page registers for each channel (plus a few unused ones). */
989	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x80, 8, dmaWritePage, dmaReadPage, pDC8, "DMA8 Page", NULL, &pDC8->hIoPortPage);
990	AssertLogRelRCReturn(rc, rc);
991	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x88, 8, dmaWritePage, dmaReadPage, pDC16, "DMA16 Page", NULL, &pDC16->hIoPortPage);
992	AssertLogRelRCReturn(rc, rc);
993
994	/* Optional EISA style high page registers (address bits 24-31). */
995	if (fHighPage)
996	{
997	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x480, 8, dmaWriteHiPage, dmaReadHiPage, pDC8, "DMA8 Page High", NULL, &pDC8->hIoPortHi);
998	AssertLogRelRCReturn(rc, rc);
999	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x488, 8, dmaWriteHiPage, dmaReadHiPage, pDC16, "DMA16 Page High", NULL, &pDC16->hIoPortHi);
1000	AssertLogRelRCReturn(rc, rc);
1001	}
1002	else
1003	{
1004	pDC8->hIoPortHi = NIL_IOMIOPORTHANDLE;
1005	pDC16->hIoPortHi = NIL_IOMIOPORTHANDLE;
1006	}
1007
1008	/*
1009	* Reset controller state.
1010	*/
1011	dmaReset(pDevIns);
1012
1013	/*
1014	* Register ourselves with PDM as the DMA controller.
1015	*/
1016	PDMDMACREG Reg;
1017	Reg.u32Version = PDM_DMACREG_VERSION;
1018	Reg.pfnRun = dmaRun;
1019	Reg.pfnRegister = dmaRegister;
1020	Reg.pfnReadMemory = dmaReadMemory;
1021	Reg.pfnWriteMemory = dmaWriteMemory;
1022	Reg.pfnSetDREQ = dmaSetDREQ;
1023	Reg.pfnGetChannelMode = dmaGetChannelMode;
1024
1025	rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
1026	AssertRCReturn(rc, rc);
1027
1028	/*
1029	* Register the saved state.
1030	*/
1031	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
1032	AssertRCReturn(rc, rc);
1033
1034	/*
1035	* Statistics.
1036	*/
1037	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRun, STAMTYPE_PROFILE, "DmaRun", STAMUNIT_TICKS_PER_CALL, "Profiling dmaRun().");
1038
1039	return VINF_SUCCESS;
1040	}
1041
1042	#else /* !IN_RING3 */
1043
1044	/**
1045	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1046	*/
1047	static DECLCALLBACK(int) dmaRZConstruct(PPDMDEVINS pDevIns)
1048	{
1049	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1050	PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
1051	int rc;
1052
1053	for (unsigned i = 0; i < RT_ELEMENTS(pThis->DMAC); i++)
1054	{
1055	PDMACONTROLLER pCtl = &pThis->DMAC[i];
1056
1057	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortBase, dmaWriteAddr, dmaReadAddr, pCtl);
1058	AssertLogRelRCReturn(rc, rc);
1059
1060	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortCtl, dmaWriteCtl, dmaReadCtl, pCtl);
1061	AssertLogRelRCReturn(rc, rc);
1062
1063	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortPage, dmaWritePage, dmaReadPage, pCtl);
1064	AssertLogRelRCReturn(rc, rc);
1065
1066	if (pCtl->hIoPortHi != NIL_IOMIOPORTHANDLE)
1067	{
1068	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortHi, dmaWriteHiPage, dmaReadHiPage, pCtl);
1069	AssertLogRelRCReturn(rc, rc);
1070	}
1071	}
1072
1073	return VINF_SUCCESS;
1074	}
1075
1076	#endif /* !IN_RING3 */
1077
1078	/**
1079	* The device registration structure.
1080	*/
1081	const PDMDEVREG g_DeviceDMA =
1082	{
1083	/* .u32Version = */ PDM_DEVREG_VERSION,
1084	/* .uReserved0 = */ 0,
1085	/* .szName = */ "8237A",
1086	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1087	/* .fClass = */ PDM_DEVREG_CLASS_DMA,
1088	/* .cMaxInstances = */ 1,
1089	/* .uSharedVersion = */ 42,
1090	/* .cbInstanceShared = */ sizeof(DMAState),
1091	/* .cbInstanceCC = */ 0,
1092	/* .cbInstanceRC = */ 0,
1093	/* .cMaxPciDevices = */ 0,
1094	/* .cMaxMsixVectors = */ 0,
1095	/* .pszDescription = */ "DMA Controller Device",
1096	#if defined(IN_RING3)
1097	/* .pszRCMod = */ "VBoxDDRC.rc",
1098	/* .pszR0Mod = */ "VBoxDDR0.r0",
1099	/* .pfnConstruct = */ dmaConstruct,
1100	/* .pfnDestruct = */ NULL,
1101	/* .pfnRelocate = */ NULL,
1102	/* .pfnMemSetup = */ NULL,
1103	/* .pfnPowerOn = */ NULL,
1104	/* .pfnReset = */ dmaReset,
1105	/* .pfnSuspend = */ NULL,
1106	/* .pfnResume = */ NULL,
1107	/* .pfnAttach = */ NULL,
1108	/* .pfnDetach = */ NULL,
1109	/* .pfnQueryInterface = */ NULL,
1110	/* .pfnInitComplete = */ NULL,
1111	/* .pfnPowerOff = */ NULL,
1112	/* .pfnSoftReset = */ NULL,
1113	/* .pfnReserved0 = */ NULL,
1114	/* .pfnReserved1 = */ NULL,
1115	/* .pfnReserved2 = */ NULL,
1116	/* .pfnReserved3 = */ NULL,
1117	/* .pfnReserved4 = */ NULL,
1118	/* .pfnReserved5 = */ NULL,
1119	/* .pfnReserved6 = */ NULL,
1120	/* .pfnReserved7 = */ NULL,
1121	#elif defined(IN_RING0)
1122	/* .pfnEarlyConstruct = */ NULL,
1123	/* .pfnConstruct = */ dmaRZConstruct,
1124	/* .pfnDestruct = */ NULL,
1125	/* .pfnFinalDestruct = */ NULL,
1126	/* .pfnRequest = */ NULL,
1127	/* .pfnReserved0 = */ NULL,
1128	/* .pfnReserved1 = */ NULL,
1129	/* .pfnReserved2 = */ NULL,
1130	/* .pfnReserved3 = */ NULL,
1131	/* .pfnReserved4 = */ NULL,
1132	/* .pfnReserved5 = */ NULL,
1133	/* .pfnReserved6 = */ NULL,
1134	/* .pfnReserved7 = */ NULL,
1135	#elif defined(IN_RC)
1136	/* .pfnConstruct = */ dmaRZConstruct,
1137	/* .pfnReserved0 = */ NULL,
1138	/* .pfnReserved1 = */ NULL,
1139	/* .pfnReserved2 = */ NULL,
1140	/* .pfnReserved3 = */ NULL,
1141	/* .pfnReserved4 = */ NULL,
1142	/* .pfnReserved5 = */ NULL,
1143	/* .pfnReserved6 = */ NULL,
1144	/* .pfnReserved7 = */ NULL,
1145	#else
1146	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1147	#endif
1148	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1149	};
1150
1151	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1152

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 81985

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