DevFwCommon.cpp@ 32767

Last change on this file since 32767 was 32720, checked in by vboxsync, 14 years ago
Devices/BIOS: allow to overwrite DmiSystemSKU
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 37.4 KB

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1	/* $Id: DevFwCommon.cpp 32720 2010-09-23 13:17:35Z vboxsync $ */
2	/** @file
3	* FwCommon - Shared firmware code (used by DevPcBios & DevEFI).
4	*/
5
6	/*
7	* Copyright (C) 2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV
22	#include <VBox/pdmdev.h>
23
24	#include <VBox/log.h>
25	#include <VBox/err.h>
26	#include <VBox/param.h>
27
28	#include <iprt/asm.h>
29	#include <iprt/assert.h>
30	#include <iprt/buildconfig.h>
31	#include <iprt/file.h>
32	#include <iprt/mem.h>
33	#include <iprt/string.h>
34	#include <iprt/uuid.h>
35	#include <iprt/system.h>
36
37	#include "../Builtins.h"
38	#include "../Builtins2.h"
39	#include "DevFwCommon.h"
40
41
42	/*******************************************************************************
43	* Defined Constants And Macros *
44	*******************************************************************************/
45
46	/*
47	* Default DMI data (legacy).
48	* Don't change this information otherwise Windows guests will demand re-activation!
49	*/
50	static const int32_t s_iDefDmiBIOSReleaseMajor = 0;
51	static const int32_t s_iDefDmiBIOSReleaseMinor = 0;
52	static const int32_t s_iDefDmiBIOSFirmwareMajor = 0;
53	static const int32_t s_iDefDmiBIOSFirmwareMinor = 0;
54	static const char *s_szDefDmiBIOSVendor = "innotek GmbH";
55	static const char *s_szDefDmiBIOSVersion = "VirtualBox";
56	static const char *s_szDefDmiBIOSReleaseDate = "12/01/2006";
57	static const char *s_szDefDmiSystemVendor = "innotek GmbH";
58	static const char *s_szDefDmiSystemProduct = "VirtualBox";
59	static const char *s_szDefDmiSystemVersion = "1.2";
60	static const char *s_szDefDmiSystemSerial = "0";
61	static const char *s_szDefDmiSystemSKU = "";
62	static const char *s_szDefDmiSystemFamily = "Virtual Machine";
63	static const char *s_szDefDmiChassisVendor = "Sun Microsystems, Inc.";
64	static const char *s_szDefDmiChassisVersion = "";
65	static const char *s_szDefDmiChassisSerial = "";
66	static const char *s_szDefDmiChassisAssetTag = "";
67
68	static char g_szHostDmiSystemProduct[64];
69	static char g_szHostDmiSystemVersion[64];
70
71
72	/*******************************************************************************
73	* Structures and Typedefs *
74	*******************************************************************************/
75	#pragma pack(1)
76
77	typedef struct SMBIOSHDR
78	{
79	uint8_t au8Signature[4];
80	uint8_t u8Checksum;
81	uint8_t u8Eps;
82	uint8_t u8VersionMajor;
83	uint8_t u8VersionMinor;
84	uint16_t u16MaxStructureSize;
85	uint8_t u8EntryPointRevision;
86	uint8_t u8Pad[5];
87	} *SMBIOSHDRPTR;
88	AssertCompileSize(SMBIOSHDR, 16);
89
90	typedef struct DMIMAINHDR
91	{
92	uint8_t au8Signature[5];
93	uint8_t u8Checksum;
94	uint16_t u16TablesLength;
95	uint32_t u32TableBase;
96	uint16_t u16TableEntries;
97	uint8_t u8TableVersion;
98	} *DMIMAINHDRPTR;
99	AssertCompileSize(DMIMAINHDR, 15);
100
101	/** DMI header */
102	typedef struct DMIHDR
103	{
104	uint8_t u8Type;
105	uint8_t u8Length;
106	uint16_t u16Handle;
107	} *PDMIHDR;
108	AssertCompileSize(DMIHDR, 4);
109
110	/** DMI BIOS information (Type 0) */
111	typedef struct DMIBIOSINF
112	{
113	DMIHDR header;
114	uint8_t u8Vendor;
115	uint8_t u8Version;
116	uint16_t u16Start;
117	uint8_t u8Release;
118	uint8_t u8ROMSize;
119	uint64_t u64Characteristics;
120	uint8_t u8CharacteristicsByte1;
121	uint8_t u8CharacteristicsByte2;
122	uint8_t u8ReleaseMajor;
123	uint8_t u8ReleaseMinor;
124	uint8_t u8FirmwareMajor;
125	uint8_t u8FirmwareMinor;
126	} *PDMIBIOSINF;
127	AssertCompileSize(DMIBIOSINF, 0x18);
128
129	/** DMI system information (Type 1) */
130	typedef struct DMISYSTEMINF
131	{
132	DMIHDR header;
133	uint8_t u8Manufacturer;
134	uint8_t u8ProductName;
135	uint8_t u8Version;
136	uint8_t u8SerialNumber;
137	uint8_t au8Uuid[16];
138	uint8_t u8WakeupType;
139	uint8_t u8SKUNumber;
140	uint8_t u8Family;
141	} *PDMISYSTEMINF;
142	AssertCompileSize(DMISYSTEMINF, 0x1b);
143
144	/** DMI board (or module) information (Type 2) */
145	typedef struct DMIBOARDINF
146	{
147	DMIHDR header;
148	uint8_t u8Manufacturer;
149	uint8_t u8Product;
150	uint8_t u8Version;
151	uint8_t u8SerialNumber;
152	uint8_t u8AssetTag;
153	uint8_t u8FeatureFlags;
154	uint8_t u8LocationInChassis;
155	uint16_t u16ChassisHandle;
156	uint8_t u8BoardType;
157	uint8_t u8cObjectHandles;
158	} *PDMIBOARDINF;
159	AssertCompileSize(DMIBOARDINF, 0x0f);
160
161	/** DMI system enclosure or chassis type (Type 3) */
162	typedef struct DMICHASSIS
163	{
164	DMIHDR header;
165	uint8_t u8Manufacturer;
166	uint8_t u8Type;
167	uint8_t u8Version;
168	uint8_t u8SerialNumber;
169	uint8_t u8AssetTag;
170	uint8_t u8BootupState;
171	uint8_t u8PowerSupplyState;
172	uint8_t u8ThermalState;
173	uint8_t u8SecurityStatus;
174	/* v2.3+, currently not supported */
175	uint32_t u32OEMdefined;
176	uint8_t u8Height;
177	uint8_t u8NumPowerChords;
178	uint8_t u8ContElems;
179	uint8_t u8ContElemRecLen;
180	} *PDMICHASSIS;
181	AssertCompileSize(DMICHASSIS, 0x15);
182
183	/** DMI processor information (Type 4) */
184	typedef struct DMIPROCESSORINF
185	{
186	DMIHDR header;
187	uint8_t u8SocketDesignation;
188	uint8_t u8ProcessorType;
189	uint8_t u8ProcessorFamily;
190	uint8_t u8ProcessorManufacturer;
191	uint64_t u64ProcessorIdentification;
192	uint8_t u8ProcessorVersion;
193	uint8_t u8Voltage;
194	uint16_t u16ExternalClock;
195	uint16_t u16MaxSpeed;
196	uint16_t u16CurrentSpeed;
197	uint8_t u8Status;
198	uint8_t u8ProcessorUpgrade;
199	uint16_t u16L1CacheHandle;
200	uint16_t u16L2CacheHandle;
201	uint16_t u16L3CacheHandle;
202	uint8_t u8SerialNumber;
203	uint8_t u8AssetTag;
204	uint8_t u8PartNumber;
205	uint8_t u8CoreCount;
206	uint8_t u8CoreEnabled;
207	uint8_t u8ThreadCount;
208	uint16_t u16ProcessorCharacteristics;
209	uint16_t u16ProcessorFamily2;
210	} *PDMIPROCESSORINF;
211	AssertCompileSize(DMIPROCESSORINF, 0x2a);
212
213	/** DMI OEM strings (Type 11) */
214	typedef struct DMIOEMSTRINGS
215	{
216	DMIHDR header;
217	uint8_t u8Count;
218	uint8_t u8VBoxVersion;
219	uint8_t u8VBoxRevision;
220	} *PDMIOEMSTRINGS;
221	AssertCompileSize(DMIOEMSTRINGS, 0x7);
222
223	/** Physical memory array (Type 16) */
224	typedef struct DMIRAMARRAY
225	{
226	DMIHDR header;
227	uint8_t u8Location;
228	uint8_t u8Use;
229	uint8_t u8MemErrorCorrection;
230	uint32_t u32MaxCapacity;
231	uint16_t u16MemErrorHandle;
232	uint16_t u16NumberOfMemDevices;
233	} *PDMIRAMARRAY;
234	AssertCompileSize(DMIRAMARRAY, 15);
235
236	/** DMI Memory Device (Type 17) */
237	typedef struct DMIMEMORYDEV
238	{
239	DMIHDR header;
240	uint16_t u16PhysMemArrayHandle;
241	uint16_t u16MemErrHandle;
242	uint16_t u16TotalWidth;
243	uint16_t u16DataWidth;
244	uint16_t u16Size;
245	uint8_t u8FormFactor;
246	uint8_t u8DeviceSet;
247	uint8_t u8DeviceLocator;
248	uint8_t u8BankLocator;
249	uint8_t u8MemoryType;
250	uint16_t u16TypeDetail;
251	uint16_t u16Speed;
252	uint8_t u8Manufacturer;
253	uint8_t u8SerialNumber;
254	uint8_t u8AssetTag;
255	uint8_t u8PartNumber;
256	/* v2.6+ */
257	uint8_t u8Attributes;
258	} *PDMIMEMORYDEV;
259	AssertCompileSize(DMIMEMORYDEV, 28);
260
261	/** MPS floating pointer structure */
262	typedef struct MPSFLOATPTR
263	{
264	uint8_t au8Signature[4];
265	uint32_t u32MPSAddr;
266	uint8_t u8Length;
267	uint8_t u8SpecRev;
268	uint8_t u8Checksum;
269	uint8_t au8Feature[5];
270	} *PMPSFLOATPTR;
271	AssertCompileSize(MPSFLOATPTR, 16);
272
273	/** MPS config table header */
274	typedef struct MPSCFGTBLHEADER
275	{
276	uint8_t au8Signature[4];
277	uint16_t u16Length;
278	uint8_t u8SpecRev;
279	uint8_t u8Checksum;
280	uint8_t au8OemId[8];
281	uint8_t au8ProductId[12];
282	uint32_t u32OemTablePtr;
283	uint16_t u16OemTableSize;
284	uint16_t u16EntryCount;
285	uint32_t u32AddrLocalApic;
286	uint16_t u16ExtTableLength;
287	uint8_t u8ExtTableChecksum;
288	uint8_t u8Reserved;
289	} *PMPSCFGTBLHEADER;
290	AssertCompileSize(MPSCFGTBLHEADER, 0x2c);
291
292	/** MPS processor entry */
293	typedef struct MPSPROCENTRY
294	{
295	uint8_t u8EntryType;
296	uint8_t u8LocalApicId;
297	uint8_t u8LocalApicVersion;
298	uint8_t u8CPUFlags;
299	uint32_t u32CPUSignature;
300	uint32_t u32CPUFeatureFlags;
301	uint32_t u32Reserved[2];
302	} *PMPSPROCENTRY;
303	AssertCompileSize(MPSPROCENTRY, 20);
304
305	/** MPS bus entry */
306	typedef struct MPSBUSENTRY
307	{
308	uint8_t u8EntryType;
309	uint8_t u8BusId;
310	uint8_t au8BusTypeStr[6];
311	} *PMPSBUSENTRY;
312	AssertCompileSize(MPSBUSENTRY, 8);
313
314	/** MPS I/O-APIC entry */
315	typedef struct MPSIOAPICENTRY
316	{
317	uint8_t u8EntryType;
318	uint8_t u8Id;
319	uint8_t u8Version;
320	uint8_t u8Flags;
321	uint32_t u32Addr;
322	} *PMPSIOAPICENTRY;
323	AssertCompileSize(MPSIOAPICENTRY, 8);
324
325	/** MPS I/O-Interrupt entry */
326	typedef struct MPSIOINTERRUPTENTRY
327	{
328	uint8_t u8EntryType;
329	uint8_t u8Type;
330	uint16_t u16Flags;
331	uint8_t u8SrcBusId;
332	uint8_t u8SrcBusIrq;
333	uint8_t u8DstIOAPICId;
334	uint8_t u8DstIOAPICInt;
335	} *PMPSIOIRQENTRY;
336	AssertCompileSize(MPSIOINTERRUPTENTRY, 8);
337
338	#pragma pack()
339
340
341	/**
342	* Calculate a simple checksum for the MPS table.
343	*
344	* @param data data
345	* @param len size of data
346	*/
347	static uint8_t fwCommonChecksum(const uint8_t * const au8Data, uint32_t u32Length)
348	{
349	uint8_t u8Sum = 0;
350	for (size_t i = 0; i < u32Length; ++i)
351	u8Sum += au8Data[i];
352	return -u8Sum;
353	}
354
355	#if 0 /* unused */
356	static bool fwCommonChecksumOk(const uint8_t * const au8Data, uint32_t u32Length)
357	{
358	uint8_t u8Sum = 0;
359	for (size_t i = 0; i < u32Length; i++)
360	u8Sum += au8Data[i];
361	return (u8Sum == 0);
362	}
363	#endif
364
365	/**
366	* Try fetch the DMI strings from the system.
367	*/
368	static void fwCommonUseHostDMIStrings(void)
369	{
370	int rc;
371
372	rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME,
373	g_szHostDmiSystemProduct, sizeof(g_szHostDmiSystemProduct));
374	if (RT_SUCCESS(rc))
375	{
376	s_szDefDmiSystemProduct = g_szHostDmiSystemProduct;
377	LogRel(("DMI: Using DmiSystemProduct from host: %s\n", g_szHostDmiSystemProduct));
378	}
379
380	rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_VERSION,
381	g_szHostDmiSystemVersion, sizeof(g_szHostDmiSystemVersion));
382	if (RT_SUCCESS(rc))
383	{
384	s_szDefDmiSystemVersion = g_szHostDmiSystemVersion;
385	LogRel(("DMI: Using DmiSystemVersion from host: %s\n", g_szHostDmiSystemVersion));
386	}
387	}
388
389	/**
390	* Construct the DMI table.
391	*
392	* @returns VBox status code.
393	* @param pDevIns The device instance.
394	* @param pTable Where to create the DMI table.
395	* @param cbMax The maximum size of the DMI table.
396	* @param pUuid Pointer to the UUID to use if the DmiUuid
397	* configuration string isn't present.
398	* @param pCfg The handle to our config node.
399	*/
400	int FwCommonPlantDMITable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, PCRTUUID pUuid, PCFGMNODE pCfg)
401	{
402	#define CHECKSIZE(cbWant) \
403	{ \
404	size_t cbNeed = (size_t)(pszStr + cbWant - (char )pTable) + 5; / +1 for strtab terminator +4 for end-of-table entry */ \
405	if (cbNeed > cbMax) \
406	{ \
407	if (fHideErrors) \
408	{ \
409	LogRel(("One of the DMI strings is too long -- using default DMI data!\n")); \
410	continue; \
411	} \
412	return PDMDevHlpVMSetError(pDevIns, VERR_TOO_MUCH_DATA, RT_SRC_POS, \
413	N_("One of the DMI strings is too long. Check all bios/Dmi* configuration entries. At least %zu bytes are needed but there is no space for more than %d bytes"), cbNeed, cbMax); \
414	} \
415	}
416
417	#define READCFGSTRDEF(variable, name, default_value) \
418	{ \
419	if (fForceDefault) \
420	pszTmp = default_value; \
421	else \
422	{ \
423	rc = CFGMR3QueryStringDef(pCfg, name, szBuf, sizeof(szBuf), default_value); \
424	if (RT_FAILURE(rc)) \
425	{ \
426	if (fHideErrors) \
427	{ \
428	LogRel(("Configuration error: Querying \"" name "\" as a string failed -- using default DMI data!\n")); \
429	continue; \
430	} \
431	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
432	N_("Configuration error: Querying \"" name "\" as a string failed")); \
433	} \
434	else if (!strcmp(szBuf, "<EMPTY>")) \
435	pszTmp = ""; \
436	else \
437	pszTmp = szBuf; \
438	} \
439	if (!pszTmp[0]) \
440	variable = 0; /* empty string */ \
441	else \
442	{ \
443	variable = iStrNr++; \
444	size_t cStr = strlen(pszTmp) + 1; \
445	CHECKSIZE(cStr); \
446	memcpy(pszStr, pszTmp, cStr); \
447	pszStr += cStr ; \
448	} \
449	}
450
451	#define READCFGSTR(variable, name) \
452	READCFGSTRDEF(variable, # name, s_szDef ## name)
453
454	#define READCFGINT(variable, name) \
455	{ \
456	if (fForceDefault) \
457	variable = s_iDef ## name; \
458	else \
459	{ \
460	rc = CFGMR3QueryS32Def(pCfg, # name, & variable, s_iDef ## name); \
461	if (RT_FAILURE(rc)) \
462	{ \
463	if (fHideErrors) \
464	{ \
465	LogRel(("Configuration error: Querying \"" # name "\" as an int failed -- using default DMI data!\n")); \
466	continue; \
467	} \
468	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
469	N_("Configuration error: Querying \"" # name "\" as an int failed")); \
470	} \
471	} \
472	}
473
474	#define START_STRUCT(tbl) \
475	pszStr = (char *)(tbl + 1); \
476	iStrNr = 1;
477
478	#define TERM_STRUCT \
479	{ \
480	pszStr++ = '\0'; / terminate set of text strings */ \
481	if (iStrNr == 1) \
482	pszStr++ = '\0'; / terminate a structure without strings */ \
483	}
484
485	bool fForceDefault = false;
486	#ifdef VBOX_BIOS_DMI_FALLBACK
487	/*
488	* There will be two passes. If an error occurs during the first pass, a
489	* message will be written to the release log and we fall back to default
490	* DMI data and start a second pass.
491	*/
492	bool fHideErrors = true;
493	#else
494	/*
495	* There will be one pass, every error is fatal and will prevent the VM
496	* from starting.
497	*/
498	bool fHideErrors = false;
499	#endif
500
501	uint8_t fDmiUseHostInfo;
502	int rc = CFGMR3QueryU8Def(pCfg, "DmiUseHostInfo", &fDmiUseHostInfo, 0);
503	if (RT_FAILURE (rc))
504	return PDMDEV_SET_ERROR(pDevIns, rc,
505	N_("Configuration error: Failed to read \"DmiUseHostInfo\""));
506
507	/* Sync up with host default DMI values */
508	if (fDmiUseHostInfo)
509	fwCommonUseHostDMIStrings();
510
511	uint8_t fDmiExposeMemoryTable;
512	rc = CFGMR3QueryU8Def(pCfg, "DmiExposeMemoryTable", &fDmiExposeMemoryTable, 0);
513	if (RT_FAILURE (rc))
514	return PDMDEV_SET_ERROR(pDevIns, rc,
515	N_("Configuration error: Failed to read \"DmiExposeMemoryTable\""));
516
517	for (;; fForceDefault = true, fHideErrors = false)
518	{
519	int iStrNr;
520	char szBuf[256];
521	char pszStr = (char )pTable;
522	char szDmiSystemUuid[64];
523	char *pszDmiSystemUuid;
524	const char *pszTmp;
525
526	if (fForceDefault)
527	pszDmiSystemUuid = NULL;
528	else
529	{
530	rc = CFGMR3QueryString(pCfg, "DmiSystemUuid", szDmiSystemUuid, sizeof(szDmiSystemUuid));
531	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
532	pszDmiSystemUuid = NULL;
533	else if (RT_FAILURE(rc))
534	{
535	if (fHideErrors)
536	{
537	LogRel(("Configuration error: Querying \"DmiSystemUuid\" as a string failed, using default DMI data\n"));
538	continue;
539	}
540	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
541	N_("Configuration error: Querying \"DmiSystemUuid\" as a string failed"));
542	}
543	else
544	pszDmiSystemUuid = szDmiSystemUuid;
545	}
546
547	/*********************************
548	* DMI BIOS information (Type 0) *
549	*********************************/
550	PDMIBIOSINF pBIOSInf = (PDMIBIOSINF)pszStr;
551	CHECKSIZE(sizeof(*pBIOSInf));
552
553	pszStr = (char *)&pBIOSInf->u8ReleaseMajor;
554	pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8ReleaseMajor);
555
556	/* don't set these fields by default for legacy compatibility */
557	int iDmiBIOSReleaseMajor, iDmiBIOSReleaseMinor;
558	READCFGINT(iDmiBIOSReleaseMajor, DmiBIOSReleaseMajor);
559	READCFGINT(iDmiBIOSReleaseMinor, DmiBIOSReleaseMinor);
560	if (iDmiBIOSReleaseMajor != 0 \|\| iDmiBIOSReleaseMinor != 0)
561	{
562	pszStr = (char *)&pBIOSInf->u8FirmwareMajor;
563	pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8FirmwareMajor);
564	pBIOSInf->u8ReleaseMajor = iDmiBIOSReleaseMajor;
565	pBIOSInf->u8ReleaseMinor = iDmiBIOSReleaseMinor;
566
567	int iDmiBIOSFirmwareMajor, iDmiBIOSFirmwareMinor;
568	READCFGINT(iDmiBIOSFirmwareMajor, DmiBIOSFirmwareMajor);
569	READCFGINT(iDmiBIOSFirmwareMinor, DmiBIOSFirmwareMinor);
570	if (iDmiBIOSFirmwareMajor != 0 \|\| iDmiBIOSFirmwareMinor != 0)
571	{
572	pszStr = (char *)(pBIOSInf + 1);
573	pBIOSInf->header.u8Length = sizeof(DMIBIOSINF);
574	pBIOSInf->u8FirmwareMajor = iDmiBIOSFirmwareMajor;
575	pBIOSInf->u8FirmwareMinor = iDmiBIOSFirmwareMinor;
576	}
577	}
578
579	iStrNr = 1;
580	pBIOSInf->header.u8Type = 0; /* BIOS Information */
581	pBIOSInf->header.u16Handle = 0x0000;
582	READCFGSTR(pBIOSInf->u8Vendor, DmiBIOSVendor);
583	READCFGSTR(pBIOSInf->u8Version, DmiBIOSVersion);
584	pBIOSInf->u16Start = 0xE000;
585	READCFGSTR(pBIOSInf->u8Release, DmiBIOSReleaseDate);
586	pBIOSInf->u8ROMSize = 1; /* 128K */
587	pBIOSInf->u64Characteristics = RT_BIT(4) /* ISA is supported */
588	\| RT_BIT(7) /* PCI is supported */
589	\| RT_BIT(15) /* Boot from CD is supported */
590	\| RT_BIT(16) /* Selectable Boot is supported */
591	\| RT_BIT(27) /* Int 9h, 8042 Keyboard services supported */
592	\| RT_BIT(30) /* Int 10h, CGA/Mono Video Services supported */
593	/* any more?? */
594	;
595	pBIOSInf->u8CharacteristicsByte1 = RT_BIT(0) /* ACPI is supported */
596	/* any more?? */
597	;
598	pBIOSInf->u8CharacteristicsByte2 = 0
599	/* any more?? */
600	;
601	TERM_STRUCT;
602
603	/***********************************
604	* DMI system information (Type 1) *
605	***********************************/
606	PDMISYSTEMINF pSystemInf = (PDMISYSTEMINF)pszStr;
607	CHECKSIZE(sizeof(*pSystemInf));
608	pszStr = (char *)(pSystemInf + 1);
609	iStrNr = 1;
610	pSystemInf->header.u8Type = 1; /* System Information */
611	pSystemInf->header.u8Length = sizeof(*pSystemInf);
612	pSystemInf->header.u16Handle = 0x0001;
613	READCFGSTR(pSystemInf->u8Manufacturer, DmiSystemVendor);
614	READCFGSTR(pSystemInf->u8ProductName, DmiSystemProduct);
615	READCFGSTR(pSystemInf->u8Version, DmiSystemVersion);
616	READCFGSTR(pSystemInf->u8SerialNumber, DmiSystemSerial);
617
618	RTUUID uuid;
619	if (pszDmiSystemUuid)
620	{
621	rc = RTUuidFromStr(&uuid, pszDmiSystemUuid);
622	if (RT_FAILURE(rc))
623	{
624	if (fHideErrors)
625	{
626	LogRel(("Configuration error: Invalid UUID for DMI tables specified, using default DMI data\n"));
627	continue;
628	}
629	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
630	N_("Configuration error: Invalid UUID for DMI tables specified"));
631	}
632	uuid.Gen.u32TimeLow = RT_H2BE_U32(uuid.Gen.u32TimeLow);
633	uuid.Gen.u16TimeMid = RT_H2BE_U16(uuid.Gen.u16TimeMid);
634	uuid.Gen.u16TimeHiAndVersion = RT_H2BE_U16(uuid.Gen.u16TimeHiAndVersion);
635	pUuid = &uuid;
636	}
637	memcpy(pSystemInf->au8Uuid, pUuid, sizeof(RTUUID));
638
639	pSystemInf->u8WakeupType = 6; /* Power Switch */
640	READCFGSTR(pSystemInf->u8SKUNumber, DmiSystemSKU);
641	READCFGSTR(pSystemInf->u8Family, DmiSystemFamily);
642	TERM_STRUCT;
643
644	/********************************************
645	* DMI System Enclosure or Chassis (Type 3) *
646	********************************************/
647	PDMICHASSIS pChassis = (PDMICHASSIS)pszStr;
648	CHECKSIZE(sizeof(*pChassis));
649	pszStr = (char*)&pChassis->u32OEMdefined;
650	iStrNr = 1;
651	#ifdef VBOX_WITH_DMI_CHASSIS
652	pChassis->header.u8Type = 3; /* System Enclosure or Chassis */
653	#else
654	pChassis->header.u8Type = 0x7e; /* inactive */
655	#endif
656	pChassis->header.u8Length = RT_OFFSETOF(DMICHASSIS, u32OEMdefined);
657	pChassis->header.u16Handle = 0x0003;
658	READCFGSTR(pChassis->u8Manufacturer, DmiChassisVendor);
659	pChassis->u8Type = 0x01; /* ''other'', no chassis lock present */
660	READCFGSTR(pChassis->u8Version, DmiChassisVersion);
661	READCFGSTR(pChassis->u8SerialNumber, DmiChassisSerial);
662	READCFGSTR(pChassis->u8AssetTag, DmiChassisAssetTag);
663	pChassis->u8BootupState = 0x03; /* safe */
664	pChassis->u8PowerSupplyState = 0x03; /* safe */
665	pChassis->u8ThermalState = 0x03; /* safe */
666	pChassis->u8SecurityStatus = 0x03; /* none XXX */
667	# if 0
668	/* v2.3+, currently not supported */
669	pChassis->u32OEMdefined = 0;
670	pChassis->u8Height = 0; /* unspecified */
671	pChassis->u8NumPowerChords = 0; /* unspecified */
672	pChassis->u8ContElems = 0; /* no contained elements */
673	pChassis->u8ContElemRecLen = 0; /* no contained elements */
674	# endif
675	TERM_STRUCT;
676
677	if (fDmiExposeMemoryTable)
678	{
679	/***************************************
680	* DMI Physical Memory Array (Type 16) *
681	***************************************/
682	uint64_t u64RamSize;
683	rc = CFGMR3QueryU64(pCfg, "RamSize", &u64RamSize);
684	if (RT_FAILURE (rc))
685	return PDMDEV_SET_ERROR(pDevIns, rc,
686	N_("Configuration error: Failed to read \"RamSize\""));
687
688	PDMIRAMARRAY pMemArray = (PDMIRAMARRAY)pszStr;
689	CHECKSIZE(sizeof(*pMemArray));
690
691	START_STRUCT(pMemArray);
692	pMemArray->header.u8Type = 16; /* Physical Memory Array */
693	pMemArray->header.u8Length = sizeof(*pMemArray);
694	pMemArray->header.u16Handle = 0x0005;
695	pMemArray->u8Location = 0x03; /* Motherboard */
696	pMemArray->u8Use = 0x03; /* System memory */
697	pMemArray->u8MemErrorCorrection = 0x01; /* Other */
698	uint32_t u32RamSizeK = (uint32_t)(u64RamSize / _1K);
699	pMemArray->u32MaxCapacity = u32RamSizeK; /* RAM size in K */
700	pMemArray->u16MemErrorHandle = 0xfffe; /* No error info structure */
701	pMemArray->u16NumberOfMemDevices = 1;
702	TERM_STRUCT;
703
704	/***************************************
705	* DMI Memory Device (Type 17) *
706	***************************************/
707	PDMIMEMORYDEV pMemDev = (PDMIMEMORYDEV)pszStr;
708	CHECKSIZE(sizeof(*pMemDev));
709
710	START_STRUCT(pMemDev);
711	pMemDev->header.u8Type = 17; /* Memory Device */
712	pMemDev->header.u8Length = sizeof(*pMemDev);
713	pMemDev->header.u16Handle = 0x0006;
714	pMemDev->u16PhysMemArrayHandle = 0x0005; /* handle of array we belong to */
715	pMemDev->u16MemErrHandle = 0xfffe; /* system doesn't provide this information */
716	pMemDev->u16TotalWidth = 0xffff; /* Unknown */
717	pMemDev->u16DataWidth = 0xffff; /* Unknown */
718	int16_t u16RamSizeM = (uint16_t)(u64RamSize / _1M);
719	if (u16RamSizeM == 0)
720	u16RamSizeM = 0x400; /* 1G */
721	pMemDev->u16Size = u16RamSizeM; /* RAM size */
722	pMemDev->u8FormFactor = 0x09; /* DIMM */
723	pMemDev->u8DeviceSet = 0x00; /* Not part of a device set */
724	READCFGSTRDEF(pMemDev->u8DeviceLocator, " ", "DIMM 0");
725	READCFGSTRDEF(pMemDev->u8BankLocator, " ", "Bank 0");
726	pMemDev->u8MemoryType = 0x03; /* DRAM */
727	pMemDev->u16TypeDetail = 0; /* Nothing special */
728	pMemDev->u16Speed = 1600; /* Unknown, shall be speed in MHz */
729	READCFGSTR(pMemDev->u8Manufacturer, DmiSystemVendor);
730	READCFGSTRDEF(pMemDev->u8SerialNumber, " ", "00000000");
731	READCFGSTRDEF(pMemDev->u8AssetTag, " ", "00000000");
732	READCFGSTRDEF(pMemDev->u8PartNumber, " ", "00000000");
733	pMemDev->u8Attributes = 0; /* Unknown */
734	TERM_STRUCT;
735	}
736
737	/*****************************
738	* DMI OEM strings (Type 11) *
739	*****************************/
740	PDMIOEMSTRINGS pOEMStrings = (PDMIOEMSTRINGS)pszStr;
741	CHECKSIZE(sizeof(*pOEMStrings));
742	pszStr = (char *)(pOEMStrings + 1);
743	iStrNr = 1;
744	#ifdef VBOX_WITH_DMI_OEMSTRINGS
745	pOEMStrings->header.u8Type = 0xb; /* OEM Strings */
746	#else
747	pOEMStrings->header.u8Type = 0x7e; /* inactive */
748	#endif
749	pOEMStrings->header.u8Length = sizeof(*pOEMStrings);
750	pOEMStrings->header.u16Handle = 0x0002;
751	pOEMStrings->u8Count = 2;
752
753	char szTmp[64];
754	RTStrPrintf(szTmp, sizeof(szTmp), "vboxVer_%u.%u.%u",
755	RTBldCfgVersionMajor(), RTBldCfgVersionMinor(), RTBldCfgVersionBuild());
756	READCFGSTRDEF(pOEMStrings->u8VBoxVersion, "DmiOEMVBoxVer", szTmp);
757	RTStrPrintf(szTmp, sizeof(szTmp), "vboxRev_%u", RTBldCfgRevision());
758	READCFGSTRDEF(pOEMStrings->u8VBoxRevision, "DmiOEMVBoxRev", szTmp);
759	TERM_STRUCT;
760
761	/* End-of-table marker - includes padding to account for fixed table size. */
762	PDMIHDR pEndOfTable = (PDMIHDR)pszStr;
763	pEndOfTable->u8Type = 0x7f;
764	pEndOfTable->u8Length = cbMax - ((char )pszStr - (char )pTable) - 2;
765	pEndOfTable->u16Handle = 0xFEFF;
766
767	/* If more fields are added here, fix the size check in READCFGSTR */
768
769	/* Success! */
770	break;
771	}
772
773	#undef READCFGSTR
774	#undef READCFGINT
775	#undef CHECKSIZE
776	return VINF_SUCCESS;
777	}
778
779	/**
780	* Construct the SMBIOS and DMI headers table pointer at VM construction and
781	* reset.
782	*
783	* @param pDevIns The device instance data.
784	*/
785	void FwCommonPlantSmbiosAndDmiHdrs(PPDMDEVINS pDevIns)
786	{
787	struct
788	{
789	struct SMBIOSHDR smbios;
790	struct DMIMAINHDR dmi;
791	} aBiosHeaders =
792	{
793	// The SMBIOS header
794	{
795	{ 0x5f, 0x53, 0x4d, 0x5f}, // "_SM_" signature
796	0x00, // checksum
797	0x1f, // EPS length, defined by standard
798	VBOX_SMBIOS_MAJOR_VER, // SMBIOS major version
799	VBOX_SMBIOS_MINOR_VER, // SMBIOS minor version
800	VBOX_SMBIOS_MAXSS, // Maximum structure size
801	0x00, // Entry point revision
802	{ 0x00, 0x00, 0x00, 0x00, 0x00 } // padding
803	},
804	// The DMI header
805	{
806	{ 0x5f, 0x44, 0x4d, 0x49, 0x5f }, // "_DMI_" signature
807	0x00, // checksum
808	VBOX_DMI_TABLE_SIZE, // DMI tables length
809	VBOX_DMI_TABLE_BASE, // DMI tables base
810	VBOX_DMI_TABLE_ENTR, // DMI tables entries
811	VBOX_DMI_TABLE_VER, // DMI version
812	}
813	};
814
815	aBiosHeaders.smbios.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.smbios, sizeof(aBiosHeaders.smbios));
816	aBiosHeaders.dmi.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.dmi, sizeof(aBiosHeaders.dmi));
817
818	PDMDevHlpPhysWrite(pDevIns, 0xfe300, &aBiosHeaders, sizeof(aBiosHeaders));
819	}
820	AssertCompile(VBOX_DMI_TABLE_ENTR == 5);
821
822	/**
823	* Construct the MPS table for implanting as a ROM page.
824	*
825	* Only applicable if IOAPIC is active!
826	*
827	* See ``MultiProcessor Specificatiton Version 1.4 (May 1997)'':
828	* ``1.3 Scope
829	* ...
830	* The hardware required to implement the MP specification is kept to a
831	* minimum, as follows:
832	* * One or more processors that are Intel architecture instruction set
833	* compatible, such as the CPUs in the Intel486 or Pentium processor
834	* family.
835	* * One or more APICs, such as the Intel 82489DX Advanced Programmable
836	* Interrupt Controller or the integrated APIC, such as that on the
837	* Intel Pentium 735\\90 and 815\\100 processors, together with a discrete
838	* I/O APIC unit.''
839	* and later:
840	* ``4.3.3 I/O APIC Entries
841	* The configuration table contains one or more entries for I/O APICs.
842	* ...
843	* I/O APIC FLAGS: EN 3:0 1 If zero, this I/O APIC is unusable, and the
844	* operating system should not attempt to access
845	* this I/O APIC.
846	* At least one I/O APIC must be enabled.''
847	*
848	* @param pDevIns The device instance data.
849	* @param pTable Where to write the table.
850	* @param cbMax The maximum size of the MPS table.
851	* @param cCpus The number of guest CPUs.
852	*/
853	void FwCommonPlantMpsTable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, uint16_t cCpus)
854	{
855	/* configuration table */
856	PMPSCFGTBLHEADER pCfgTab = (MPSCFGTBLHEADER*)pTable;
857	memcpy(pCfgTab->au8Signature, "PCMP", 4);
858	pCfgTab->u8SpecRev = 4; /* 1.4 */
859	memcpy(pCfgTab->au8OemId, "VBOXCPU ", 8);
860	memcpy(pCfgTab->au8ProductId, "VirtualBox ", 12);
861	pCfgTab->u32OemTablePtr = 0;
862	pCfgTab->u16OemTableSize = 0;
863	pCfgTab->u16EntryCount = cCpus /* Processors */
864	+ 1 /* ISA Bus */
865	+ 1 /* PCI Bus */
866	+ 1 /* I/O-APIC */
867	+ 16 /* Interrupts */
868	+ 1 /* Local interrupts */;
869	pCfgTab->u32AddrLocalApic = 0xfee00000;
870	pCfgTab->u16ExtTableLength = 0;
871	pCfgTab->u8ExtTableChecksum = 0;
872	pCfgTab->u8Reserved = 0;
873
874	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
875	uint32_t u32CPUSignature = 0x0520; /* default: Pentium 100 */
876	uint32_t u32FeatureFlags = 0x0001; /* default: FPU */
877	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
878	if (u32Eax >= 1)
879	{
880	PDMDevHlpGetCpuId(pDevIns, 1, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
881	u32CPUSignature = u32Eax & 0xfff;
882	/* Local APIC will be enabled later so override it here. Since we provide
883	* an MP table we have an IOAPIC and therefore a Local APIC. */
884	u32FeatureFlags = u32Edx \| X86_CPUID_FEATURE_EDX_APIC;
885	}
886	/* Construct MPS table for each VCPU. */
887	PMPSPROCENTRY pProcEntry = (PMPSPROCENTRY)(pCfgTab+1);
888	for (int i = 0; i < cCpus; i++)
889	{
890	pProcEntry->u8EntryType = 0; /* processor entry */
891	pProcEntry->u8LocalApicId = i;
892	pProcEntry->u8LocalApicVersion = 0x14;
893	pProcEntry->u8CPUFlags = (i == 0 ? 2 /* bootstrap processor / : 0 / application processor /) \| 1 / enabled */;
894	pProcEntry->u32CPUSignature = u32CPUSignature;
895	pProcEntry->u32CPUFeatureFlags = u32FeatureFlags;
896	pProcEntry->u32Reserved[0] =
897	pProcEntry->u32Reserved[1] = 0;
898	pProcEntry++;
899	}
900
901	uint32_t iBusIdPci0 = 0;
902	uint32_t iBusIdIsa = 1;
903
904	/* ISA bus */
905	PMPSBUSENTRY pBusEntry = (PMPSBUSENTRY)pProcEntry;
906	pBusEntry->u8EntryType = 1; /* bus entry */
907	pBusEntry->u8BusId = iBusIdIsa; /* this ID is referenced by the interrupt entries */
908	memcpy(pBusEntry->au8BusTypeStr, "ISA ", 6);
909	pBusEntry++;
910
911	/* PCI bus */
912	pBusEntry->u8EntryType = 1; /* bus entry */
913	pBusEntry->u8BusId = iBusIdPci0; /* this ID can be referenced by the interrupt entries */
914	memcpy(pBusEntry->au8BusTypeStr, "PCI ", 6);
915
916
917	/* I/O-APIC.
918	* MP spec: "The configuration table contains one or more entries for I/O APICs.
919	* ... At least one I/O APIC must be enabled." */
920	PMPSIOAPICENTRY pIOAPICEntry = (PMPSIOAPICENTRY)(pBusEntry+1);
921	uint16_t iApicId = 0;
922	pIOAPICEntry->u8EntryType = 2; /* I/O-APIC entry */
923	pIOAPICEntry->u8Id = iApicId; /* this ID is referenced by the interrupt entries */
924	pIOAPICEntry->u8Version = 0x11;
925	pIOAPICEntry->u8Flags = 1 /* enable */;
926	pIOAPICEntry->u32Addr = 0xfec00000;
927
928	/* Interrupt tables */
929	/* Bus vectors */
930	PMPSIOIRQENTRY pIrqEntry = (PMPSIOIRQENTRY)(pIOAPICEntry+1);
931	for (int iPin = 0; iPin < 16; iPin++, pIrqEntry++)
932	{
933	pIrqEntry->u8EntryType = 3; /* I/O interrupt entry */
934	/*
935	* 0 - INT, vectored interrupt,
936	* 3 - ExtINT, vectored interrupt provided by PIC
937	* As we emulate system with both APIC and PIC, it's needed for their coexistence.
938	*/
939	pIrqEntry->u8Type = (iPin == 0) ? 3 : 0;
940	pIrqEntry->u16Flags = 0; /* polarity of APIC I/O input signal = conforms to bus,
941	trigger mode = conforms to bus */
942	pIrqEntry->u8SrcBusId = iBusIdIsa; /* ISA bus */
943	/* IRQ0 mapped to pin 2, other are identity mapped */
944	/* If changing, also update PDMIsaSetIrq() and MADT */
945	pIrqEntry->u8SrcBusIrq = (iPin == 2) ? 0 : iPin; /* IRQ on the bus */
946	pIrqEntry->u8DstIOAPICId = iApicId; /* destintion IO-APIC */
947	pIrqEntry->u8DstIOAPICInt = iPin; /* pin on destination IO-APIC */
948	}
949	/* Local delivery */
950	pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
951	pIrqEntry->u8Type = 3; /* ExtINT */
952	pIrqEntry->u16Flags = (1 << 2) \| 1; /* active-high, edge-triggered */
953	pIrqEntry->u8SrcBusId = iBusIdIsa;
954	pIrqEntry->u8SrcBusIrq = 0;
955	pIrqEntry->u8DstIOAPICId = 0xff;
956	pIrqEntry->u8DstIOAPICInt = 0;
957	pIrqEntry++;
958
959	pCfgTab->u16Length = (uint8_t*)pIrqEntry - pTable;
960	pCfgTab->u8Checksum = fwCommonChecksum(pTable, pCfgTab->u16Length);
961
962	AssertMsg(pCfgTab->u16Length < cbMax,
963	("VBOX_MPS_TABLE_SIZE=%d, maximum allowed size is %d",
964	pCfgTab->u16Length, cbMax));
965	}
966
967	/**
968	* Construct the MPS table pointer at VM construction and reset.
969	*
970	* Only applicable if IOAPIC is active!
971	*
972	* @param pDevIns The device instance data.
973	*/
974	void FwCommonPlantMpsFloatPtr(PPDMDEVINS pDevIns)
975	{
976	MPSFLOATPTR floatPtr;
977	floatPtr.au8Signature[0] = '_';
978	floatPtr.au8Signature[1] = 'M';
979	floatPtr.au8Signature[2] = 'P';
980	floatPtr.au8Signature[3] = '_';
981	floatPtr.u32MPSAddr = VBOX_MPS_TABLE_BASE;
982	floatPtr.u8Length = 1; /* structure size in paragraphs */
983	floatPtr.u8SpecRev = 4; /* MPS revision 1.4 */
984	floatPtr.u8Checksum = 0;
985	floatPtr.au8Feature[0] = 0;
986	floatPtr.au8Feature[1] = 0;
987	floatPtr.au8Feature[2] = 0;
988	floatPtr.au8Feature[3] = 0;
989	floatPtr.au8Feature[4] = 0;
990	floatPtr.u8Checksum = fwCommonChecksum((uint8_t*)&floatPtr, 16);
991	PDMDevHlpPhysWrite(pDevIns, 0x9fff0, &floatPtr, 16);
992	}

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source: vbox/trunk/src/VBox/Devices/PC/DevFwCommon.cpp@ 32767

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