DevFwCommon.cpp@ 45761

Last change on this file since 45761 was 44821, checked in by vboxsync, 12 years ago
BUGZ:6633 Use RT_H2LE_* instead of cpu_to_le*.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 44.9 KB

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1	/* $Id: DevFwCommon.cpp 44821 2013-02-25 15:06:40Z vboxsync $ */
2	/** @file
3	* FwCommon - Shared firmware code (used by DevPcBios & DevEFI).
4	*/
5
6	/*
7	* Copyright (C) 2009-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV
22	#include <VBox/vmm/pdmdev.h>
23
24	#include <VBox/log.h>
25	#include <VBox/err.h>
26	#include <VBox/param.h>
27
28	#include <iprt/asm.h>
29	#include <iprt/assert.h>
30	#include <iprt/buildconfig.h>
31	#include <iprt/file.h>
32	#include <iprt/mem.h>
33	#include <iprt/string.h>
34	#include <iprt/uuid.h>
35	#include <iprt/system.h>
36	#include <iprt/cdefs.h>
37
38	#include "VBoxDD.h"
39	#include "VBoxDD2.h"
40	#include "DevFwCommon.h"
41
42
43	/*******************************************************************************
44	* Defined Constants And Macros *
45	*******************************************************************************/
46
47	/*
48	* Default DMI data (legacy).
49	* Don't change this information otherwise Windows guests might demand re-activation!
50	*/
51
52	/* type 0 -- DMI BIOS information */
53	static const int32_t s_iDefDmiBIOSReleaseMajor = 0;
54	static const int32_t s_iDefDmiBIOSReleaseMinor = 0;
55	static const int32_t s_iDefDmiBIOSFirmwareMajor = 0;
56	static const int32_t s_iDefDmiBIOSFirmwareMinor = 0;
57	static const char *s_szDefDmiBIOSVendor = "innotek GmbH";
58	static const char *s_szDefDmiBIOSVersion = "VirtualBox";
59	static const char *s_szDefDmiBIOSReleaseDate = "12/01/2006";
60	/* type 1 -- DMI system information */
61	static const char *s_szDefDmiSystemVendor = "innotek GmbH";
62	static const char *s_szDefDmiSystemProduct = "VirtualBox";
63	static const char *s_szDefDmiSystemVersion = "1.2";
64	static const char *s_szDefDmiSystemSerial = "0";
65	static const char *s_szDefDmiSystemSKU = "";
66	static const char *s_szDefDmiSystemFamily = "Virtual Machine";
67	/* type 2 -- DMI board information */
68	static const char *s_szDefDmiBoardVendor = "Oracle Corporation";
69	static const char *s_szDefDmiBoardProduct = "VirtualBox";
70	static const char *s_szDefDmiBoardVersion = "1.2";
71	static const char *s_szDefDmiBoardSerial = "0";
72	static const char *s_szDefDmiBoardAssetTag = "";
73	static const char *s_szDefDmiBoardLocInChass = "";
74	static const int32_t s_iDefDmiBoardBoardType = 0x0A; /* Motherboard */
75	/* type 3 -- DMI chassis information */
76	static const char *s_szDefDmiChassisVendor = "Oracle Corporation";
77	static const char *s_szDefDmiChassisVersion = "";
78	static const char *s_szDefDmiChassisSerial = "";
79	static const char *s_szDefDmiChassisAssetTag = "";
80	/* type 4 -- DMI processor information */
81	static const char *s_szDefDmiProcManufacturer = "GenuineIntel";
82	static const char *s_szDefDmiProcVersion = "Pentium(R) III";
83
84	static char g_szHostDmiSystemProduct[64];
85	static char g_szHostDmiSystemVersion[64];
86
87
88	/*******************************************************************************
89	* Structures and Typedefs *
90	*******************************************************************************/
91	#pragma pack(1)
92
93	typedef struct SMBIOSHDR
94	{
95	uint8_t au8Signature[4];
96	uint8_t u8Checksum;
97	uint8_t u8Eps;
98	uint8_t u8VersionMajor;
99	uint8_t u8VersionMinor;
100	uint16_t u16MaxStructureSize;
101	uint8_t u8EntryPointRevision;
102	uint8_t u8Pad[5];
103	} *SMBIOSHDRPTR;
104	AssertCompileSize(SMBIOSHDR, 16);
105
106	typedef struct DMIMAINHDR
107	{
108	uint8_t au8Signature[5];
109	uint8_t u8Checksum;
110	uint16_t u16TablesLength;
111	uint32_t u32TableBase;
112	uint16_t u16TableEntries;
113	uint8_t u8TableVersion;
114	} *DMIMAINHDRPTR;
115	AssertCompileSize(DMIMAINHDR, 15);
116
117	/** DMI header */
118	typedef struct DMIHDR
119	{
120	uint8_t u8Type;
121	uint8_t u8Length;
122	uint16_t u16Handle;
123	} *PDMIHDR;
124	AssertCompileSize(DMIHDR, 4);
125
126	/** DMI BIOS information (Type 0) */
127	typedef struct DMIBIOSINF
128	{
129	DMIHDR header;
130	uint8_t u8Vendor;
131	uint8_t u8Version;
132	uint16_t u16Start;
133	uint8_t u8Release;
134	uint8_t u8ROMSize;
135	uint64_t u64Characteristics;
136	uint8_t u8CharacteristicsByte1;
137	uint8_t u8CharacteristicsByte2;
138	uint8_t u8ReleaseMajor;
139	uint8_t u8ReleaseMinor;
140	uint8_t u8FirmwareMajor;
141	uint8_t u8FirmwareMinor;
142	} *PDMIBIOSINF;
143	AssertCompileSize(DMIBIOSINF, 0x18);
144
145	/** DMI system information (Type 1) */
146	typedef struct DMISYSTEMINF
147	{
148	DMIHDR header;
149	uint8_t u8Manufacturer;
150	uint8_t u8ProductName;
151	uint8_t u8Version;
152	uint8_t u8SerialNumber;
153	uint8_t au8Uuid[16];
154	uint8_t u8WakeupType;
155	uint8_t u8SKUNumber;
156	uint8_t u8Family;
157	} *PDMISYSTEMINF;
158	AssertCompileSize(DMISYSTEMINF, 0x1b);
159
160	/** DMI board (or module) information (Type 2) */
161	typedef struct DMIBOARDINF
162	{
163	DMIHDR header;
164	uint8_t u8Manufacturer;
165	uint8_t u8Product;
166	uint8_t u8Version;
167	uint8_t u8SerialNumber;
168	uint8_t u8AssetTag;
169	uint8_t u8FeatureFlags;
170	uint8_t u8LocationInChass;
171	uint16_t u16ChassisHandle;
172	uint8_t u8BoardType;
173	uint8_t u8cObjectHandles;
174	} *PDMIBOARDINF;
175	AssertCompileSize(DMIBOARDINF, 0x0f);
176
177	/** DMI system enclosure or chassis type (Type 3) */
178	typedef struct DMICHASSIS
179	{
180	DMIHDR header;
181	uint8_t u8Manufacturer;
182	uint8_t u8Type;
183	uint8_t u8Version;
184	uint8_t u8SerialNumber;
185	uint8_t u8AssetTag;
186	uint8_t u8BootupState;
187	uint8_t u8PowerSupplyState;
188	uint8_t u8ThermalState;
189	uint8_t u8SecurityStatus;
190	/* v2.3+, currently not supported */
191	uint32_t u32OEMdefined;
192	uint8_t u8Height;
193	uint8_t u8NumPowerChords;
194	uint8_t u8ContElems;
195	uint8_t u8ContElemRecLen;
196	} *PDMICHASSIS;
197	AssertCompileSize(DMICHASSIS, 0x15);
198
199	/** DMI processor information (Type 4) */
200	typedef struct DMIPROCESSORINF
201	{
202	DMIHDR header;
203	uint8_t u8SocketDesignation;
204	uint8_t u8ProcessorType;
205	uint8_t u8ProcessorFamily;
206	uint8_t u8ProcessorManufacturer;
207	uint64_t u64ProcessorID;
208	uint8_t u8ProcessorVersion;
209	uint8_t u8Voltage;
210	uint16_t u16ExternalClock;
211	uint16_t u16MaxSpeed;
212	uint16_t u16CurrentSpeed;
213	uint8_t u8Status;
214	uint8_t u8ProcessorUpgrade;
215	/* v2.1+ */
216	uint16_t u16L1CacheHandle;
217	uint16_t u16L2CacheHandle;
218	uint16_t u16L3CacheHandle;
219	/* v2.3+ */
220	uint8_t u8SerialNumber;
221	uint8_t u8AssetTag;
222	uint8_t u8PartNumber;
223	/* v2.5+ */
224	uint8_t u8CoreCount;
225	uint8_t u8CoreEnabled;
226	uint8_t u8ThreadCount;
227	uint16_t u16ProcessorCharacteristics;
228	/* v2.6+ */
229	uint16_t u16ProcessorFamily2;
230	} *PDMIPROCESSORINF;
231	AssertCompileSize(DMIPROCESSORINF, 0x2a);
232
233	/** DMI OEM strings (Type 11) */
234	typedef struct DMIOEMSTRINGS
235	{
236	DMIHDR header;
237	uint8_t u8Count;
238	uint8_t u8VBoxVersion;
239	uint8_t u8VBoxRevision;
240	} *PDMIOEMSTRINGS;
241	AssertCompileSize(DMIOEMSTRINGS, 0x7);
242
243	/** DMI OEM-specific table (Type 128) */
244	typedef struct DMIOEMSPECIFIC
245	{
246	DMIHDR header;
247	uint32_t u32CpuFreqKHz;
248	} *PDMIOEMSPECIFIC;
249	AssertCompileSize(DMIOEMSPECIFIC, 0x8);
250
251	/** Physical memory array (Type 16) */
252	typedef struct DMIRAMARRAY
253	{
254	DMIHDR header;
255	uint8_t u8Location;
256	uint8_t u8Use;
257	uint8_t u8MemErrorCorrection;
258	uint32_t u32MaxCapacity;
259	uint16_t u16MemErrorHandle;
260	uint16_t u16NumberOfMemDevices;
261	} *PDMIRAMARRAY;
262	AssertCompileSize(DMIRAMARRAY, 15);
263
264	/** DMI Memory Device (Type 17) */
265	typedef struct DMIMEMORYDEV
266	{
267	DMIHDR header;
268	uint16_t u16PhysMemArrayHandle;
269	uint16_t u16MemErrHandle;
270	uint16_t u16TotalWidth;
271	uint16_t u16DataWidth;
272	uint16_t u16Size;
273	uint8_t u8FormFactor;
274	uint8_t u8DeviceSet;
275	uint8_t u8DeviceLocator;
276	uint8_t u8BankLocator;
277	uint8_t u8MemoryType;
278	uint16_t u16TypeDetail;
279	uint16_t u16Speed;
280	uint8_t u8Manufacturer;
281	uint8_t u8SerialNumber;
282	uint8_t u8AssetTag;
283	uint8_t u8PartNumber;
284	/* v2.6+ */
285	uint8_t u8Attributes;
286	} *PDMIMEMORYDEV;
287	AssertCompileSize(DMIMEMORYDEV, 28);
288
289	/** MPS floating pointer structure */
290	typedef struct MPSFLOATPTR
291	{
292	uint8_t au8Signature[4];
293	uint32_t u32MPSAddr;
294	uint8_t u8Length;
295	uint8_t u8SpecRev;
296	uint8_t u8Checksum;
297	uint8_t au8Feature[5];
298	} *PMPSFLOATPTR;
299	AssertCompileSize(MPSFLOATPTR, 16);
300
301	/** MPS config table header */
302	typedef struct MPSCFGTBLHEADER
303	{
304	uint8_t au8Signature[4];
305	uint16_t u16Length;
306	uint8_t u8SpecRev;
307	uint8_t u8Checksum;
308	uint8_t au8OemId[8];
309	uint8_t au8ProductId[12];
310	uint32_t u32OemTablePtr;
311	uint16_t u16OemTableSize;
312	uint16_t u16EntryCount;
313	uint32_t u32AddrLocalApic;
314	uint16_t u16ExtTableLength;
315	uint8_t u8ExtTableChecksum;
316	uint8_t u8Reserved;
317	} *PMPSCFGTBLHEADER;
318	AssertCompileSize(MPSCFGTBLHEADER, 0x2c);
319
320	/** MPS processor entry */
321	typedef struct MPSPROCENTRY
322	{
323	uint8_t u8EntryType;
324	uint8_t u8LocalApicId;
325	uint8_t u8LocalApicVersion;
326	uint8_t u8CPUFlags;
327	uint32_t u32CPUSignature;
328	uint32_t u32CPUFeatureFlags;
329	uint32_t u32Reserved[2];
330	} *PMPSPROCENTRY;
331	AssertCompileSize(MPSPROCENTRY, 20);
332
333	/** MPS bus entry */
334	typedef struct MPSBUSENTRY
335	{
336	uint8_t u8EntryType;
337	uint8_t u8BusId;
338	uint8_t au8BusTypeStr[6];
339	} *PMPSBUSENTRY;
340	AssertCompileSize(MPSBUSENTRY, 8);
341
342	/** MPS I/O-APIC entry */
343	typedef struct MPSIOAPICENTRY
344	{
345	uint8_t u8EntryType;
346	uint8_t u8Id;
347	uint8_t u8Version;
348	uint8_t u8Flags;
349	uint32_t u32Addr;
350	} *PMPSIOAPICENTRY;
351	AssertCompileSize(MPSIOAPICENTRY, 8);
352
353	/** MPS I/O-Interrupt entry */
354	typedef struct MPSIOINTERRUPTENTRY
355	{
356	uint8_t u8EntryType;
357	uint8_t u8Type;
358	uint16_t u16Flags;
359	uint8_t u8SrcBusId;
360	uint8_t u8SrcBusIrq;
361	uint8_t u8DstIOAPICId;
362	uint8_t u8DstIOAPICInt;
363	} *PMPSIOIRQENTRY;
364	AssertCompileSize(MPSIOINTERRUPTENTRY, 8);
365
366	#pragma pack()
367
368
369	/**
370	* Calculate a simple checksum for the MPS table.
371	*
372	* @param data data
373	* @param len size of data
374	*/
375	static uint8_t fwCommonChecksum(const uint8_t * const au8Data, uint32_t u32Length)
376	{
377	uint8_t u8Sum = 0;
378	for (size_t i = 0; i < u32Length; ++i)
379	u8Sum += au8Data[i];
380	return -u8Sum;
381	}
382
383	#if 0 /* unused */
384	static bool fwCommonChecksumOk(const uint8_t * const au8Data, uint32_t u32Length)
385	{
386	uint8_t u8Sum = 0;
387	for (size_t i = 0; i < u32Length; i++)
388	u8Sum += au8Data[i];
389	return (u8Sum == 0);
390	}
391	#endif
392
393	/**
394	* Try fetch the DMI strings from the system.
395	*/
396	static void fwCommonUseHostDMIStrings(void)
397	{
398	int rc;
399
400	rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME,
401	g_szHostDmiSystemProduct, sizeof(g_szHostDmiSystemProduct));
402	if (RT_SUCCESS(rc))
403	{
404	s_szDefDmiSystemProduct = g_szHostDmiSystemProduct;
405	LogRel(("DMI: Using DmiSystemProduct from host: %s\n", g_szHostDmiSystemProduct));
406	}
407
408	rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_VERSION,
409	g_szHostDmiSystemVersion, sizeof(g_szHostDmiSystemVersion));
410	if (RT_SUCCESS(rc))
411	{
412	s_szDefDmiSystemVersion = g_szHostDmiSystemVersion;
413	LogRel(("DMI: Using DmiSystemVersion from host: %s\n", g_szHostDmiSystemVersion));
414	}
415	}
416
417	/**
418	* Construct the DMI table.
419	*
420	* @returns VBox status code.
421	* @param pDevIns The device instance.
422	* @param pTable Where to create the DMI table.
423	* @param cbMax The maximum size of the DMI table.
424	* @param pUuid Pointer to the UUID to use if the DmiUuid
425	* configuration string isn't present.
426	* @param pCfg The handle to our config node.
427	* @param cCpus Number of VCPUs.
428	* @param pcbDmiTables Size of DMI data in bytes.
429	* @param pcNumDmiTables Number of DMI tables.
430	*/
431	int FwCommonPlantDMITable(PPDMDEVINS pDevIns, uint8_t pTable, unsigned cbMax, PCRTUUID pUuid, PCFGMNODE pCfg, uint16_t cCpus, uint16_t pcbDmiTables, uint16_t *pcNumDmiTables)
432	{
433	#define CHECKSIZE(cbWant) \
434	{ \
435	size_t cbNeed = (size_t)(pszStr + cbWant - (char )pTable) + 5; / +1 for strtab terminator +4 for end-of-table entry */ \
436	if (cbNeed > cbMax) \
437	{ \
438	if (fHideErrors) \
439	{ \
440	LogRel(("One of the DMI strings is too long -- using default DMI data!\n")); \
441	continue; \
442	} \
443	return PDMDevHlpVMSetError(pDevIns, VERR_TOO_MUCH_DATA, RT_SRC_POS, \
444	N_("One of the DMI strings is too long. Check all bios/Dmi* configuration entries. At least %zu bytes are needed but there is no space for more than %d bytes"), cbNeed, cbMax); \
445	} \
446	}
447
448	#define READCFGSTRDEF(variable, name, default_value) \
449	{ \
450	if (fForceDefault) \
451	pszTmp = default_value; \
452	else \
453	{ \
454	rc = CFGMR3QueryStringDef(pCfg, name, szBuf, sizeof(szBuf), default_value); \
455	if (RT_FAILURE(rc)) \
456	{ \
457	if (fHideErrors) \
458	{ \
459	LogRel(("Configuration error: Querying \"" name "\" as a string failed -- using default DMI data!\n")); \
460	continue; \
461	} \
462	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
463	N_("Configuration error: Querying \"" name "\" as a string failed")); \
464	} \
465	else if (!strcmp(szBuf, "<EMPTY>")) \
466	pszTmp = ""; \
467	else \
468	pszTmp = szBuf; \
469	} \
470	if (!pszTmp[0]) \
471	variable = 0; /* empty string */ \
472	else \
473	{ \
474	variable = iStrNr++; \
475	size_t cStr = strlen(pszTmp) + 1; \
476	CHECKSIZE(cStr); \
477	memcpy(pszStr, pszTmp, cStr); \
478	pszStr += cStr ; \
479	} \
480	}
481
482	#define READCFGSTR(variable, name) \
483	READCFGSTRDEF(variable, # name, s_szDef ## name)
484
485	#define READCFGINT(variable, name) \
486	{ \
487	if (fForceDefault) \
488	variable = s_iDef ## name; \
489	else \
490	{ \
491	rc = CFGMR3QueryS32Def(pCfg, # name, & variable, s_iDef ## name); \
492	if (RT_FAILURE(rc)) \
493	{ \
494	if (fHideErrors) \
495	{ \
496	LogRel(("Configuration error: Querying \"" # name "\" as an int failed -- using default DMI data!\n")); \
497	continue; \
498	} \
499	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
500	N_("Configuration error: Querying \"" # name "\" as an int failed")); \
501	} \
502	} \
503	}
504
505	#define START_STRUCT(tbl) \
506	pszStr = (char *)(tbl + 1); \
507	iStrNr = 1;
508
509	#define TERM_STRUCT \
510	{ \
511	pszStr++ = '\0'; / terminate set of text strings */ \
512	if (iStrNr == 1) \
513	pszStr++ = '\0'; / terminate a structure without strings */ \
514	}
515
516	bool fForceDefault = false;
517	#ifdef VBOX_BIOS_DMI_FALLBACK
518	/*
519	* There will be two passes. If an error occurs during the first pass, a
520	* message will be written to the release log and we fall back to default
521	* DMI data and start a second pass.
522	*/
523	bool fHideErrors = true;
524	#else
525	/*
526	* There will be one pass, every error is fatal and will prevent the VM
527	* from starting.
528	*/
529	bool fHideErrors = false;
530	#endif
531
532	uint8_t fDmiUseHostInfo;
533	int rc = CFGMR3QueryU8Def(pCfg, "DmiUseHostInfo", &fDmiUseHostInfo, 0);
534	if (RT_FAILURE (rc))
535	return PDMDEV_SET_ERROR(pDevIns, rc,
536	N_("Configuration error: Failed to read \"DmiUseHostInfo\""));
537
538	/* Sync up with host default DMI values */
539	if (fDmiUseHostInfo)
540	fwCommonUseHostDMIStrings();
541
542	uint8_t fDmiExposeMemoryTable;
543	rc = CFGMR3QueryU8Def(pCfg, "DmiExposeMemoryTable", &fDmiExposeMemoryTable, 0);
544	if (RT_FAILURE (rc))
545	return PDMDEV_SET_ERROR(pDevIns, rc,
546	N_("Configuration error: Failed to read \"DmiExposeMemoryTable\""));
547	uint8_t fDmiExposeProcessorInf;
548	rc = CFGMR3QueryU8Def(pCfg, "DmiExposeProcInf", &fDmiExposeProcessorInf, 0);
549	if (RT_FAILURE (rc))
550	return PDMDEV_SET_ERROR(pDevIns, rc,
551	N_("Configuration error: Failed to read \"DmiExposeProcInf\""));
552
553	for (;; fForceDefault = true, fHideErrors = false)
554	{
555	int iStrNr;
556	char szBuf[256];
557	char pszStr = (char )pTable;
558	char szDmiSystemUuid[64];
559	char *pszDmiSystemUuid;
560	const char *pszTmp;
561
562	if (fForceDefault)
563	pszDmiSystemUuid = NULL;
564	else
565	{
566	rc = CFGMR3QueryString(pCfg, "DmiSystemUuid", szDmiSystemUuid, sizeof(szDmiSystemUuid));
567	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
568	pszDmiSystemUuid = NULL;
569	else if (RT_FAILURE(rc))
570	{
571	if (fHideErrors)
572	{
573	LogRel(("Configuration error: Querying \"DmiSystemUuid\" as a string failed, using default DMI data\n"));
574	continue;
575	}
576	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
577	N_("Configuration error: Querying \"DmiSystemUuid\" as a string failed"));
578	}
579	else
580	pszDmiSystemUuid = szDmiSystemUuid;
581	}
582
583	/*********************************
584	* DMI BIOS information (Type 0) *
585	*********************************/
586	PDMIBIOSINF pBIOSInf = (PDMIBIOSINF)pszStr;
587	CHECKSIZE(sizeof(*pBIOSInf));
588
589	pszStr = (char *)&pBIOSInf->u8ReleaseMajor;
590	pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8ReleaseMajor);
591
592	/* don't set these fields by default for legacy compatibility */
593	int iDmiBIOSReleaseMajor, iDmiBIOSReleaseMinor;
594	READCFGINT(iDmiBIOSReleaseMajor, DmiBIOSReleaseMajor);
595	READCFGINT(iDmiBIOSReleaseMinor, DmiBIOSReleaseMinor);
596	if (iDmiBIOSReleaseMajor != 0 \|\| iDmiBIOSReleaseMinor != 0)
597	{
598	pszStr = (char *)&pBIOSInf->u8FirmwareMajor;
599	pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8FirmwareMajor);
600	pBIOSInf->u8ReleaseMajor = iDmiBIOSReleaseMajor;
601	pBIOSInf->u8ReleaseMinor = iDmiBIOSReleaseMinor;
602
603	int iDmiBIOSFirmwareMajor, iDmiBIOSFirmwareMinor;
604	READCFGINT(iDmiBIOSFirmwareMajor, DmiBIOSFirmwareMajor);
605	READCFGINT(iDmiBIOSFirmwareMinor, DmiBIOSFirmwareMinor);
606	if (iDmiBIOSFirmwareMajor != 0 \|\| iDmiBIOSFirmwareMinor != 0)
607	{
608	pszStr = (char *)(pBIOSInf + 1);
609	pBIOSInf->header.u8Length = sizeof(DMIBIOSINF);
610	pBIOSInf->u8FirmwareMajor = iDmiBIOSFirmwareMajor;
611	pBIOSInf->u8FirmwareMinor = iDmiBIOSFirmwareMinor;
612	}
613	}
614
615	iStrNr = 1;
616	pBIOSInf->header.u8Type = 0; /* BIOS Information */
617	pBIOSInf->header.u16Handle = 0x0000;
618	READCFGSTR(pBIOSInf->u8Vendor, DmiBIOSVendor);
619	READCFGSTR(pBIOSInf->u8Version, DmiBIOSVersion);
620	pBIOSInf->u16Start = 0xE000;
621	READCFGSTR(pBIOSInf->u8Release, DmiBIOSReleaseDate);
622	pBIOSInf->u8ROMSize = 1; /* 128K */
623	pBIOSInf->u64Characteristics = RT_BIT(4) /* ISA is supported */
624	\| RT_BIT(7) /* PCI is supported */
625	\| RT_BIT(15) /* Boot from CD is supported */
626	\| RT_BIT(16) /* Selectable Boot is supported */
627	\| RT_BIT(27) /* Int 9h, 8042 Keyboard services supported */
628	\| RT_BIT(30) /* Int 10h, CGA/Mono Video Services supported */
629	/* any more?? */
630	;
631	pBIOSInf->u8CharacteristicsByte1 = RT_BIT(0) /* ACPI is supported */
632	/* any more?? */
633	;
634	pBIOSInf->u8CharacteristicsByte2 = 0
635	/* any more?? */
636	;
637	TERM_STRUCT;
638
639	/***********************************
640	* DMI system information (Type 1) *
641	***********************************/
642	PDMISYSTEMINF pSystemInf = (PDMISYSTEMINF)pszStr;
643	CHECKSIZE(sizeof(*pSystemInf));
644	START_STRUCT(pSystemInf);
645	pSystemInf->header.u8Type = 1; /* System Information */
646	pSystemInf->header.u8Length = sizeof(*pSystemInf);
647	pSystemInf->header.u16Handle = 0x0001;
648	READCFGSTR(pSystemInf->u8Manufacturer, DmiSystemVendor);
649	READCFGSTR(pSystemInf->u8ProductName, DmiSystemProduct);
650	READCFGSTR(pSystemInf->u8Version, DmiSystemVersion);
651	READCFGSTR(pSystemInf->u8SerialNumber, DmiSystemSerial);
652
653	RTUUID uuid;
654	if (pszDmiSystemUuid)
655	{
656	rc = RTUuidFromStr(&uuid, pszDmiSystemUuid);
657	if (RT_FAILURE(rc))
658	{
659	if (fHideErrors)
660	{
661	LogRel(("Configuration error: Invalid UUID for DMI tables specified, using default DMI data\n"));
662	continue;
663	}
664	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
665	N_("Configuration error: Invalid UUID for DMI tables specified"));
666	}
667	uuid.Gen.u32TimeLow = RT_H2BE_U32(uuid.Gen.u32TimeLow);
668	uuid.Gen.u16TimeMid = RT_H2BE_U16(uuid.Gen.u16TimeMid);
669	uuid.Gen.u16TimeHiAndVersion = RT_H2BE_U16(uuid.Gen.u16TimeHiAndVersion);
670	pUuid = &uuid;
671	}
672	memcpy(pSystemInf->au8Uuid, pUuid, sizeof(RTUUID));
673
674	pSystemInf->u8WakeupType = 6; /* Power Switch */
675	READCFGSTR(pSystemInf->u8SKUNumber, DmiSystemSKU);
676	READCFGSTR(pSystemInf->u8Family, DmiSystemFamily);
677	TERM_STRUCT;
678
679	/**********************************
680	* DMI board information (Type 2) *
681	**********************************/
682	PDMIBOARDINF pBoardInf = (PDMIBOARDINF)pszStr;
683	CHECKSIZE(sizeof(*pBoardInf));
684	START_STRUCT(pBoardInf);
685	int iDmiBoardBoardType;
686	pBoardInf->header.u8Type = 2; /* Board Information */
687	pBoardInf->header.u8Length = sizeof(*pBoardInf);
688	pBoardInf->header.u16Handle = 0x0008;
689	READCFGSTR(pBoardInf->u8Manufacturer, DmiBoardVendor);
690	READCFGSTR(pBoardInf->u8Product, DmiBoardProduct);
691	READCFGSTR(pBoardInf->u8Version, DmiBoardVersion);
692	READCFGSTR(pBoardInf->u8SerialNumber, DmiBoardSerial);
693	READCFGSTR(pBoardInf->u8AssetTag, DmiBoardAssetTag);
694	pBoardInf->u8FeatureFlags = RT_BIT(0) /* hosting board, e.g. motherboard */
695	;
696	READCFGSTR(pBoardInf->u8LocationInChass, DmiBoardLocInChass);
697	pBoardInf->u16ChassisHandle = 0x0003; /* see type 3 */
698	READCFGINT(iDmiBoardBoardType, DmiBoardBoardType);
699	pBoardInf->u8BoardType = iDmiBoardBoardType;
700	pBoardInf->u8cObjectHandles = 0;
701
702	TERM_STRUCT;
703
704	/********************************************
705	* DMI System Enclosure or Chassis (Type 3) *
706	********************************************/
707	PDMICHASSIS pChassis = (PDMICHASSIS)pszStr;
708	CHECKSIZE(sizeof(*pChassis));
709	pszStr = (char*)&pChassis->u32OEMdefined;
710	iStrNr = 1;
711	#ifdef VBOX_WITH_DMI_CHASSIS
712	pChassis->header.u8Type = 3; /* System Enclosure or Chassis */
713	#else
714	pChassis->header.u8Type = 0x7e; /* inactive */
715	#endif
716	pChassis->header.u8Length = RT_OFFSETOF(DMICHASSIS, u32OEMdefined);
717	pChassis->header.u16Handle = 0x0003;
718	READCFGSTR(pChassis->u8Manufacturer, DmiChassisVendor);
719	pChassis->u8Type = 0x01; /* ''other'', no chassis lock present */
720	READCFGSTR(pChassis->u8Version, DmiChassisVersion);
721	READCFGSTR(pChassis->u8SerialNumber, DmiChassisSerial);
722	READCFGSTR(pChassis->u8AssetTag, DmiChassisAssetTag);
723	pChassis->u8BootupState = 0x03; /* safe */
724	pChassis->u8PowerSupplyState = 0x03; /* safe */
725	pChassis->u8ThermalState = 0x03; /* safe */
726	pChassis->u8SecurityStatus = 0x03; /* none XXX */
727	# if 0
728	/* v2.3+, currently not supported */
729	pChassis->u32OEMdefined = 0;
730	pChassis->u8Height = 0; /* unspecified */
731	pChassis->u8NumPowerChords = 0; /* unspecified */
732	pChassis->u8ContElems = 0; /* no contained elements */
733	pChassis->u8ContElemRecLen = 0; /* no contained elements */
734	# endif
735	TERM_STRUCT;
736
737	/**************************************
738	* DMI Processor Information (Type 4) *
739	**************************************/
740
741	/*
742	* This is just a dummy processor. Should we expose the real guest CPU features
743	* here? Accessing this information at this point is difficult.
744	*/
745	char szSocket[32];
746	PDMIPROCESSORINF pProcessorInf = (PDMIPROCESSORINF)pszStr;
747	CHECKSIZE(sizeof(*pProcessorInf));
748	START_STRUCT(pProcessorInf);
749	if (fDmiExposeProcessorInf)
750	pProcessorInf->header.u8Type = 4; /* Processor Information */
751	else
752	pProcessorInf->header.u8Type = 126; /* inactive structure */
753	pProcessorInf->header.u8Length = sizeof(*pProcessorInf);
754	pProcessorInf->header.u16Handle = 0x0007;
755	RTStrPrintf(szSocket, sizeof(szSocket), "Socket #%u", 0);
756	pProcessorInf->u8SocketDesignation = iStrNr++;
757	{
758	size_t cStr = strlen(szSocket) + 1;
759	CHECKSIZE(cStr);
760	memcpy(pszStr, szSocket, cStr);
761	pszStr += cStr;
762	}
763	pProcessorInf->u8ProcessorType = 0x03; /* Central Processor */
764	pProcessorInf->u8ProcessorFamily = 0xB1; /* Pentium III with Intel SpeedStep(TM) */
765	READCFGSTR(pProcessorInf->u8ProcessorManufacturer, DmiProcManufacturer);
766
767	pProcessorInf->u64ProcessorID = UINT64_C(0x0FEBFBFF00010676);
768	/* Ext Family ID = 0
769	* Ext Model ID = 2
770	* Processor Type = 0
771	* Family ID = 6
772	* Model = 7
773	* Stepping = 6
774	* Features: FPU, VME, DE, PSE, TSC, MSR, PAE, MCE, CX8,
775	* APIC, SEP, MTRR, PGE, MCA, CMOV, PAT, PSE-36,
776	* CFLSH, DS, ACPI, MMX, FXSR, SSE, SSE2, SS */
777	READCFGSTR(pProcessorInf->u8ProcessorVersion, DmiProcVersion);
778	pProcessorInf->u8Voltage = 0x02; /* 3.3V */
779	pProcessorInf->u16ExternalClock = 0x00; /* unknown */
780	pProcessorInf->u16MaxSpeed = 3000; /* 3GHz */
781	pProcessorInf->u16CurrentSpeed = 3000; /* 3GHz */
782	pProcessorInf->u8Status = RT_BIT(6) /* CPU socket populated */
783	\| RT_BIT(0) /* CPU enabled */
784	;
785	pProcessorInf->u8ProcessorUpgrade = 0x04; /* ZIF Socket */
786	pProcessorInf->u16L1CacheHandle = 0xFFFF; /* not specified */
787	pProcessorInf->u16L2CacheHandle = 0xFFFF; /* not specified */
788	pProcessorInf->u16L3CacheHandle = 0xFFFF; /* not specified */
789	pProcessorInf->u8SerialNumber = 0; /* not specified */
790	pProcessorInf->u8AssetTag = 0; /* not specified */
791	pProcessorInf->u8PartNumber = 0; /* not specified */
792	pProcessorInf->u8CoreCount = cCpus; /* */
793	pProcessorInf->u8CoreEnabled = cCpus;
794	pProcessorInf->u8ThreadCount = 1;
795	pProcessorInf->u16ProcessorCharacteristics
796	= RT_BIT(2); /* 64-bit capable */
797	pProcessorInf->u16ProcessorFamily2 = 0;
798	TERM_STRUCT;
799
800	/***************************************
801	* DMI Physical Memory Array (Type 16) *
802	***************************************/
803	uint64_t u64RamSize;
804	rc = CFGMR3QueryU64(pCfg, "RamSize", &u64RamSize);
805	if (RT_FAILURE (rc))
806	return PDMDEV_SET_ERROR(pDevIns, rc,
807	N_("Configuration error: Failed to read \"RamSize\""));
808
809	PDMIRAMARRAY pMemArray = (PDMIRAMARRAY)pszStr;
810	CHECKSIZE(sizeof(*pMemArray));
811	START_STRUCT(pMemArray);
812	if (fDmiExposeMemoryTable)
813	pMemArray->header.u8Type = 16; /* Physical Memory Array */
814	else
815	pMemArray->header.u8Type = 126; /* inactive structure */
816	pMemArray->header.u8Length = sizeof(*pMemArray);
817	pMemArray->header.u16Handle = 0x0005;
818	pMemArray->u8Location = 0x03; /* Motherboard */
819	pMemArray->u8Use = 0x03; /* System memory */
820	pMemArray->u8MemErrorCorrection = 0x01; /* Other */
821	pMemArray->u32MaxCapacity = (uint32_t)(u64RamSize / _1K); /* RAM size in K */
822	pMemArray->u16MemErrorHandle = 0xfffe; /* No error info structure */
823	pMemArray->u16NumberOfMemDevices = 1;
824	TERM_STRUCT;
825
826	/***************************************
827	* DMI Memory Device (Type 17) *
828	***************************************/
829	PDMIMEMORYDEV pMemDev = (PDMIMEMORYDEV)pszStr;
830	CHECKSIZE(sizeof(*pMemDev));
831	START_STRUCT(pMemDev);
832	if (fDmiExposeMemoryTable)
833	pMemDev->header.u8Type = 17; /* Memory Device */
834	else
835	pMemDev->header.u8Type = 126; /* inactive structure */
836	pMemDev->header.u8Length = sizeof(*pMemDev);
837	pMemDev->header.u16Handle = 0x0006;
838	pMemDev->u16PhysMemArrayHandle = 0x0005; /* handle of array we belong to */
839	pMemDev->u16MemErrHandle = 0xfffe; /* system doesn't provide this information */
840	pMemDev->u16TotalWidth = 0xffff; /* Unknown */
841	pMemDev->u16DataWidth = 0xffff; /* Unknown */
842	int16_t u16RamSizeM = (uint16_t)(u64RamSize / _1M);
843	if (u16RamSizeM == 0)
844	u16RamSizeM = 0x400; /* 1G */
845	pMemDev->u16Size = u16RamSizeM; /* RAM size */
846	pMemDev->u8FormFactor = 0x09; /* DIMM */
847	pMemDev->u8DeviceSet = 0x00; /* Not part of a device set */
848	READCFGSTRDEF(pMemDev->u8DeviceLocator, " ", "DIMM 0");
849	READCFGSTRDEF(pMemDev->u8BankLocator, " ", "Bank 0");
850	pMemDev->u8MemoryType = 0x03; /* DRAM */
851	pMemDev->u16TypeDetail = 0; /* Nothing special */
852	pMemDev->u16Speed = 1600; /* Unknown, shall be speed in MHz */
853	READCFGSTR(pMemDev->u8Manufacturer, DmiSystemVendor);
854	READCFGSTRDEF(pMemDev->u8SerialNumber, " ", "00000000");
855	READCFGSTRDEF(pMemDev->u8AssetTag, " ", "00000000");
856	READCFGSTRDEF(pMemDev->u8PartNumber, " ", "00000000");
857	pMemDev->u8Attributes = 0; /* Unknown */
858	TERM_STRUCT;
859
860	/*****************************
861	* DMI OEM strings (Type 11) *
862	*****************************/
863	PDMIOEMSTRINGS pOEMStrings = (PDMIOEMSTRINGS)pszStr;
864	CHECKSIZE(sizeof(*pOEMStrings));
865	START_STRUCT(pOEMStrings);
866	#ifdef VBOX_WITH_DMI_OEMSTRINGS
867	pOEMStrings->header.u8Type = 0xb; /* OEM Strings */
868	#else
869	pOEMStrings->header.u8Type = 126; /* inactive structure */
870	#endif
871	pOEMStrings->header.u8Length = sizeof(*pOEMStrings);
872	pOEMStrings->header.u16Handle = 0x0002;
873	pOEMStrings->u8Count = 2;
874
875	char szTmp[64];
876	RTStrPrintf(szTmp, sizeof(szTmp), "vboxVer_%u.%u.%u",
877	RTBldCfgVersionMajor(), RTBldCfgVersionMinor(), RTBldCfgVersionBuild());
878	READCFGSTRDEF(pOEMStrings->u8VBoxVersion, "DmiOEMVBoxVer", szTmp);
879	RTStrPrintf(szTmp, sizeof(szTmp), "vboxRev_%u", RTBldCfgRevision());
880	READCFGSTRDEF(pOEMStrings->u8VBoxRevision, "DmiOEMVBoxRev", szTmp);
881	TERM_STRUCT;
882
883	/*************************************
884	* DMI OEM specific table (Type 128) *
885	************************************/
886	PDMIOEMSPECIFIC pOEMSpecific = (PDMIOEMSPECIFIC)pszStr;
887	CHECKSIZE(sizeof(*pOEMSpecific));
888	START_STRUCT(pOEMSpecific);
889	pOEMSpecific->header.u8Type = 0x80; /* OEM specific */
890	pOEMSpecific->header.u8Length = sizeof(*pOEMSpecific);
891	pOEMSpecific->header.u16Handle = 0x0008; /* Just next free handle */
892	pOEMSpecific->u32CpuFreqKHz = RT_H2LE_U32((uint32_t)((uint64_t)TMCpuTicksPerSecond(PDMDevHlpGetVM(pDevIns)) / 1000));
893	TERM_STRUCT;
894
895	/* End-of-table marker - includes padding to account for fixed table size. */
896	PDMIHDR pEndOfTable = (PDMIHDR)pszStr;
897	pszStr = (char *)(pEndOfTable + 1);
898	pEndOfTable->u8Type = 0x7f;
899
900	pEndOfTable->u8Length = sizeof(*pEndOfTable);
901	pEndOfTable->u16Handle = 0xFEFF;
902	*pcbDmiTables = ((uintptr_t)pszStr - (uintptr_t)pTable) + 2;
903
904	/* We currently plant 10 DMI tables. Update this if tables number changed. */
905	*pcNumDmiTables = 10;
906
907	/* If more fields are added here, fix the size check in READCFGSTR */
908
909	/* Success! */
910	break;
911	}
912
913	#undef READCFGSTR
914	#undef READCFGINT
915	#undef CHECKSIZE
916	return VINF_SUCCESS;
917	}
918
919	/**
920	* Construct the SMBIOS and DMI headers table pointer at VM construction and
921	* reset.
922	*
923	* @param pDevIns The device instance data.
924	*/
925	void FwCommonPlantSmbiosAndDmiHdrs(PPDMDEVINS pDevIns, uint16_t cbDmiTables, uint16_t cNumDmiTables)
926	{
927	struct
928	{
929	struct SMBIOSHDR smbios;
930	struct DMIMAINHDR dmi;
931	}
932	aBiosHeaders =
933	{
934	// The SMBIOS header
935	{
936	{ 0x5f, 0x53, 0x4d, 0x5f}, // "_SM_" signature
937	0x00, // checksum
938	0x1f, // EPS length, defined by standard
939	VBOX_SMBIOS_MAJOR_VER, // SMBIOS major version
940	VBOX_SMBIOS_MINOR_VER, // SMBIOS minor version
941	VBOX_SMBIOS_MAXSS, // Maximum structure size
942	0x00, // Entry point revision
943	{ 0x00, 0x00, 0x00, 0x00, 0x00 } // padding
944	},
945	// The DMI header
946	{
947	{ 0x5f, 0x44, 0x4d, 0x49, 0x5f }, // "_DMI_" signature
948	0x00, // checksum
949	0, // DMI tables length
950	VBOX_DMI_TABLE_BASE, // DMI tables base
951	0, // DMI tables entries
952	VBOX_DMI_TABLE_VER, // DMI version
953	}
954	};
955
956	aBiosHeaders.dmi.u16TablesLength = cbDmiTables;
957	aBiosHeaders.dmi.u16TableEntries = cNumDmiTables;
958	aBiosHeaders.smbios.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.smbios, sizeof(aBiosHeaders.smbios));
959	aBiosHeaders.dmi.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.dmi, sizeof(aBiosHeaders.dmi));
960
961	PDMDevHlpPhysWrite(pDevIns, 0xfe300, &aBiosHeaders, sizeof(aBiosHeaders));
962	}
963
964	/**
965	* Construct the MPS table for implanting as a ROM page.
966	*
967	* Only applicable if IOAPIC is active!
968	*
969	* See ``MultiProcessor Specification Version 1.4 (May 1997)'':
970	* ``1.3 Scope
971	* ...
972	* The hardware required to implement the MP specification is kept to a
973	* minimum, as follows:
974	* * One or more processors that are Intel architecture instruction set
975	* compatible, such as the CPUs in the Intel486 or Pentium processor
976	* family.
977	* * One or more APICs, such as the Intel 82489DX Advanced Programmable
978	* Interrupt Controller or the integrated APIC, such as that on the
979	* Intel Pentium 735\\90 and 815\\100 processors, together with a discrete
980	* I/O APIC unit.''
981	* and later:
982	* ``4.3.3 I/O APIC Entries
983	* The configuration table contains one or more entries for I/O APICs.
984	* ...
985	* I/O APIC FLAGS: EN 3:0 1 If zero, this I/O APIC is unusable, and the
986	* operating system should not attempt to access
987	* this I/O APIC.
988	* At least one I/O APIC must be enabled.''
989	*
990	* @param pDevIns The device instance data.
991	* @param pTable Where to write the table.
992	* @param cbMax The maximum size of the MPS table.
993	* @param cCpus The number of guest CPUs.
994	*/
995	void FwCommonPlantMpsTable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, uint16_t cCpus)
996	{
997	/* configuration table */
998	PMPSCFGTBLHEADER pCfgTab = (MPSCFGTBLHEADER*)pTable;
999	memcpy(pCfgTab->au8Signature, "PCMP", 4);
1000	pCfgTab->u8SpecRev = 4; /* 1.4 */
1001	memcpy(pCfgTab->au8OemId, "VBOXCPU ", 8);
1002	memcpy(pCfgTab->au8ProductId, "VirtualBox ", 12);
1003	pCfgTab->u32OemTablePtr = 0;
1004	pCfgTab->u16OemTableSize = 0;
1005	pCfgTab->u16EntryCount = 0; /* Incremented as we go. */
1006	pCfgTab->u32AddrLocalApic = 0xfee00000;
1007	pCfgTab->u16ExtTableLength = 0;
1008	pCfgTab->u8ExtTableChecksum = 0;
1009	pCfgTab->u8Reserved = 0;
1010
1011	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
1012	uint32_t u32CPUSignature = 0x0520; /* default: Pentium 100 */
1013	uint32_t u32FeatureFlags = 0x0001; /* default: FPU */
1014	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
1015	if (u32Eax >= 1)
1016	{
1017	PDMDevHlpGetCpuId(pDevIns, 1, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
1018	u32CPUSignature = u32Eax & 0xfff;
1019	/* Local APIC will be enabled later so override it here. Since we provide
1020	* an MP table we have an IOAPIC and therefore a Local APIC. */
1021	u32FeatureFlags = u32Edx \| X86_CPUID_FEATURE_EDX_APIC;
1022	}
1023	/* Construct MPS table for each VCPU. */
1024	PMPSPROCENTRY pProcEntry = (PMPSPROCENTRY)(pCfgTab+1);
1025	for (int i = 0; i < cCpus; i++)
1026	{
1027	pProcEntry->u8EntryType = 0; /* processor entry */
1028	pProcEntry->u8LocalApicId = i;
1029	pProcEntry->u8LocalApicVersion = 0x14;
1030	pProcEntry->u8CPUFlags = (i == 0 ? 2 /* bootstrap processor / : 0 / application processor /) \| 1 / enabled */;
1031	pProcEntry->u32CPUSignature = u32CPUSignature;
1032	pProcEntry->u32CPUFeatureFlags = u32FeatureFlags;
1033	pProcEntry->u32Reserved[0] =
1034	pProcEntry->u32Reserved[1] = 0;
1035	pProcEntry++;
1036	pCfgTab->u16EntryCount++;
1037	}
1038
1039	uint32_t iBusIdIsa = 0;
1040	uint32_t iBusIdPci0 = 1;
1041
1042	/* ISA bus */
1043	PMPSBUSENTRY pBusEntry = (PMPSBUSENTRY)pProcEntry;
1044	pBusEntry->u8EntryType = 1; /* bus entry */
1045	pBusEntry->u8BusId = iBusIdIsa; /* this ID is referenced by the interrupt entries */
1046	memcpy(pBusEntry->au8BusTypeStr, "ISA ", 6);
1047	pBusEntry++;
1048	pCfgTab->u16EntryCount++;
1049
1050	/* PCI bus */
1051	pBusEntry->u8EntryType = 1; /* bus entry */
1052	pBusEntry->u8BusId = iBusIdPci0; /* this ID can be referenced by the interrupt entries */
1053	memcpy(pBusEntry->au8BusTypeStr, "PCI ", 6);
1054	pCfgTab->u16EntryCount++;
1055
1056
1057	/* I/O-APIC.
1058	* MP spec: "The configuration table contains one or more entries for I/O APICs.
1059	* ... At least one I/O APIC must be enabled." */
1060	PMPSIOAPICENTRY pIOAPICEntry = (PMPSIOAPICENTRY)(pBusEntry+1);
1061	uint16_t iApicId = 0;
1062	pIOAPICEntry->u8EntryType = 2; /* I/O-APIC entry */
1063	pIOAPICEntry->u8Id = iApicId; /* this ID is referenced by the interrupt entries */
1064	pIOAPICEntry->u8Version = 0x11;
1065	pIOAPICEntry->u8Flags = 1 /* enable */;
1066	pIOAPICEntry->u32Addr = 0xfec00000;
1067	pCfgTab->u16EntryCount++;
1068
1069	/* Interrupt tables */
1070	/* Bus vectors */
1071	/* Note: The PIC is currently not routed to the I/O APIC. Therefore we skip
1072	* pin 0 on the I/O APIC.
1073	*/
1074	PMPSIOIRQENTRY pIrqEntry = (PMPSIOIRQENTRY)(pIOAPICEntry+1);
1075	for (int iPin = 1; iPin < 16; iPin++, pIrqEntry++)
1076	{
1077	pIrqEntry->u8EntryType = 3; /* I/O interrupt entry */
1078	/*
1079	* 0 - INT, vectored interrupt,
1080	* 3 - ExtINT, vectored interrupt provided by PIC
1081	* As we emulate system with both APIC and PIC, it's needed for their coexistence.
1082	*/
1083	pIrqEntry->u8Type = (iPin == 0) ? 3 : 0;
1084	pIrqEntry->u16Flags = 0; /* polarity of APIC I/O input signal = conforms to bus,
1085	trigger mode = conforms to bus */
1086	pIrqEntry->u8SrcBusId = iBusIdIsa; /* ISA bus */
1087	/* IRQ0 mapped to pin 2, other are identity mapped */
1088	/* If changing, also update PDMIsaSetIrq() and MADT */
1089	pIrqEntry->u8SrcBusIrq = (iPin == 2) ? 0 : iPin; /* IRQ on the bus */
1090	pIrqEntry->u8DstIOAPICId = iApicId; /* destination IO-APIC */
1091	pIrqEntry->u8DstIOAPICInt = iPin; /* pin on destination IO-APIC */
1092	pCfgTab->u16EntryCount++;
1093	}
1094	/* Local delivery */
1095	pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
1096	pIrqEntry->u8Type = 3; /* ExtINT */
1097	pIrqEntry->u16Flags = (1 << 2) \| 1; /* active-high, edge-triggered */
1098	pIrqEntry->u8SrcBusId = iBusIdIsa;
1099	pIrqEntry->u8SrcBusIrq = 0;
1100	pIrqEntry->u8DstIOAPICId = 0xff;
1101	pIrqEntry->u8DstIOAPICInt = 0;
1102	pIrqEntry++;
1103	pCfgTab->u16EntryCount++;
1104	pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
1105	pIrqEntry->u8Type = 1; /* NMI */
1106	pIrqEntry->u16Flags = (1 << 2) \| 1; /* active-high, edge-triggered */
1107	pIrqEntry->u8SrcBusId = iBusIdIsa;
1108	pIrqEntry->u8SrcBusIrq = 0;
1109	pIrqEntry->u8DstIOAPICId = 0xff;
1110	pIrqEntry->u8DstIOAPICInt = 1;
1111	pIrqEntry++;
1112	pCfgTab->u16EntryCount++;
1113
1114	pCfgTab->u16Length = (uint8_t*)pIrqEntry - pTable;
1115	pCfgTab->u8Checksum = fwCommonChecksum(pTable, pCfgTab->u16Length);
1116
1117	AssertMsg(pCfgTab->u16Length < cbMax,
1118	("VBOX_MPS_TABLE_SIZE=%d, maximum allowed size is %d",
1119	pCfgTab->u16Length, cbMax));
1120	}
1121
1122	/**
1123	* Construct the MPS table pointer at VM construction and reset.
1124	*
1125	* Only applicable if IOAPIC is active!
1126	*
1127	* @param pDevIns The device instance data.
1128	*/
1129	void FwCommonPlantMpsFloatPtr(PPDMDEVINS pDevIns)
1130	{
1131	MPSFLOATPTR floatPtr;
1132	floatPtr.au8Signature[0] = '_';
1133	floatPtr.au8Signature[1] = 'M';
1134	floatPtr.au8Signature[2] = 'P';
1135	floatPtr.au8Signature[3] = '_';
1136	floatPtr.u32MPSAddr = VBOX_MPS_TABLE_BASE;
1137	floatPtr.u8Length = 1; /* structure size in paragraphs */
1138	floatPtr.u8SpecRev = 4; /* MPS revision 1.4 */
1139	floatPtr.u8Checksum = 0;
1140	floatPtr.au8Feature[0] = 0;
1141	floatPtr.au8Feature[1] = 0;
1142	floatPtr.au8Feature[2] = 0;
1143	floatPtr.au8Feature[3] = 0;
1144	floatPtr.au8Feature[4] = 0;
1145	floatPtr.u8Checksum = fwCommonChecksum((uint8_t*)&floatPtr, 16);
1146	PDMDevHlpPhysWrite(pDevIns, 0x9fff0, &floatPtr, 16);
1147	}

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source: vbox/trunk/src/VBox/Devices/PC/DevFwCommon.cpp@ 45761

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