DevIOAPIC_New.cpp@ 61815

Last change on this file since 61815 was 61815, checked in by vboxsync, 9 years ago
IOAPIC: Fixed/hacked the debug register accessors.
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1	/* $Id: DevIOAPIC_New.cpp 61815 2016-06-22 13:05:44Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/** The current IO APIC saved state version. */
36	#define IOAPIC_SAVED_STATE_VERSION 2
37	/** The saved state version used by VirtualBox 5.0 and
38	* earlier. */
39	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
40
41	/** Implementation specified by the "Intel I/O Controller Hub 9
42	* (ICH9) Family" */
43	#define IOAPIC_HARDWARE_VERSION_ICH9 1
44	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
45	Controller" */
46	#define IOAPIC_HARDWARE_VERSION_82093AA 2
47	/** The IO APIC implementation to use. */
48	#define IOAPIC_HARDWARE_VERSION IOAPIC_HARDWARE_VERSION_ICH9
49
50	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
51	/** The version. */
52	# define IOAPIC_VERSION 0x11
53	/** The ID mask. */
54	# define IOAPIC_ID_MASK 0x0f
55	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
56	/** The version. */
57	# define IOAPIC_VERSION 0x20
58	/** The ID mask. */
59	# define IOAPIC_ID_MASK 0xff
60	#else
61	# error "Implement me"
62	#endif
63
64	/** The default MMIO base physical address. */
65	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
66	/** The size of the MMIO range. */
67	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
68	/** The mask for getting direct registers from physical address. */
69	#define IOAPIC_MMIO_REG_MASK 0xff
70
71	/** The number of interrupt input pins. */
72	#define IOAPIC_NUM_INTR_PINS 24
73	/** Maximum redirection entires. */
74	#define IOAPIC_MAX_REDIR_ENTRIES (IOAPIC_NUM_INTR_PINS - 1)
75
76	/** Version register - Gets the version. */
77	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
78	/** Version register - Gets the maximum redirection entry. */
79	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
80	/** Version register - Gets whether Pin Assertion Register (PRQ) is
81	* supported. */
82	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
83
84	/** Index register - Valid write mask. */
85	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
86
87	/** Arbitration register - Gets the ID. */
88	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
89
90	/** ID register - Gets the ID. */
91	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & IOAPIC_ID_MASK)
92
93	/** Redirection table entry - Vector. */
94	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
95	/** Redirection table entry - Delivery mode. */
96	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
97	/** Redirection table entry - Destination mode. */
98	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
99	/** Redirection table entry - Delivery status. */
100	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
101	/** Redirection table entry - Interrupt input pin polarity. */
102	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
103	/** Redirection table entry - Remote IRR. */
104	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
105	/** Redirection table entry - Trigger Mode. */
106	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
107	/** Redirection table entry - the mask bit number. */
108	#define IOAPIC_RTE_MASK_BIT 16
109	/** Redirection table entry - the mask. */
110	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
111	/** Redirection table entry - Extended Destination ID. */
112	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
113	/** Redirection table entry - Destination. */
114	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
115
116	/** Redirection table entry - Gets the destination. */
117	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
118	/** Redirection table entry - Gets the mask flag. */
119	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
120	/** Redirection table entry - Checks whether it's masked. */
121	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
122	/** Redirection table entry - Gets the trigger mode. */
123	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
124	/** Redirection table entry - Gets the remote IRR flag. */
125	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
126	/** Redirection table entry - Gets the interrupt pin polarity. */
127	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
128	/** Redirection table entry - Gets the delivery status. */
129	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
130	/** Redirection table entry - Gets the destination mode. */
131	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
132	/** Redirection table entry - Gets the delivery mode. */
133	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
134	/** Redirection table entry - Gets the vector. */
135	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
136	/** Redirection table entry - Valid write mask. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
139	\| IOAPIC_RTE_VECTOR)
140
141	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
142	/** Redirection table entry - Valid read mask. */
143	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
144	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
145	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
146	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
147	/** Redirection table entry - Valid read mask. */
148	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
149	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
150	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
151	\| IOAPIC_RTE_VECTOR)
152	#endif
153	/** Redirection table entry - Trigger mode edge. */
154	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
155	/** Redirection table entry - Trigger mode level. */
156	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
157	/** Redirection table entry - Destination mode physical. */
158	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
159	/** Redirection table entry - Destination mode logical. */
160	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
161
162
163	/** Index of indirect registers in the I/O APIC register table. */
164	#define IOAPIC_INDIRECT_INDEX_ID 0x0
165	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
166	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
167	# define IOAPIC_INDIRECT_INDEX_ARB 0x2
168	#endif
169	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10
170	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_END 0x3F
171
172	/** Offset of direct registers in the I/O APIC MMIO space. */
173	#define IOAPIC_DIRECT_OFF_INDEX 0x00
174	#define IOAPIC_DIRECT_OFF_DATA 0x10
175	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
176	# define IOAPIC_DIRECT_OFF_EOI 0x40
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The per-VM I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The device instance - R3 Ptr. */
189	PPDMDEVINSR3 pDevInsR3;
190	/** The IOAPIC helpers - R3 Ptr. */
191	PCPDMIOAPICHLPR3 pIoApicHlpR3;
192
193	/** The device instance - R0 Ptr. */
194	PPDMDEVINSR0 pDevInsR0;
195	/** The IOAPIC helpers - R0 Ptr. */
196	PCPDMIOAPICHLPR0 pIoApicHlpR0;
197
198	/** The device instance - RC Ptr. */
199	PPDMDEVINSRC pDevInsRC;
200	/** The IOAPIC helpers - RC Ptr. */
201	PCPDMIOAPICHLPRC pIoApicHlpRC;
202
203	/** The ID register. */
204	uint8_t volatile u8Id;
205	/** The index register. */
206	uint8_t volatile u8Index;
207	/** Number of CPUs. */
208	uint8_t cCpus;
209	/* Alignment padding. */
210	uint8_t u8Padding0[5];
211
212	/** The redirection table registers. */
213	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
214	/** The IRQ tags and source IDs for each pin (tracing purposes). */
215	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
216
217	/** Alignment padding. */
218	uint32_t u32Padding2;
219	/** The internal IRR reflecting state of the interrupt lines. */
220	uint32_t uIrr;
221
222	/** The critsect for updating to the RTEs. */
223	PDMCRITSECT CritSect;
224
225	#ifdef VBOX_WITH_STATISTICS
226	/** Number of MMIO reads in R0. */
227	STAMCOUNTER StatMmioReadR0;
228	/** Number of MMIO reads in R3. */
229	STAMCOUNTER StatMmioReadR3;
230	/** Number of MMIO reads in RC. */
231	STAMCOUNTER StatMmioReadRC;
232
233	/** Number of MMIO writes in R0. */
234	STAMCOUNTER StatMmioWriteR0;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237	/** Number of MMIO writes in RC. */
238	STAMCOUNTER StatMmioWriteRC;
239
240	/** Number of SetIrq calls in R0. */
241	STAMCOUNTER StatSetIrqR0;
242	/** Number of SetIrq calls in R3. */
243	STAMCOUNTER StatSetIrqR3;
244	/** Number of SetIrq calls in RC. */
245	STAMCOUNTER StatSetIrqRC;
246
247	/** Number of SetEoi calls in R0. */
248	STAMCOUNTER StatSetEoiR0;
249	/** Number of SetEoi calls in R3. */
250	STAMCOUNTER StatSetEoiR3;
251	/** Number of SetEoi calls in RC. */
252	STAMCOUNTER StatSetEoiRC;
253
254	/** Number of redundant edge-triggered interrupts. */
255	STAMCOUNTER StatRedundantEdgeIntr;
256	/** Number of redundant level-triggered interrupts. */
257	STAMCOUNTER StatRedundantLevelIntr;
258	/** Number of suppressed level-triggered interrupts (by remote IRR). */
259	STAMCOUNTER StatSuppressedLevelIntr;
260	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
261	STAMCOUNTER StatEoiContention;
262	/** Number of returns to ring-3 due to Set RTE lock contention. */
263	STAMCOUNTER StatSetRteContention;
264	#endif
265	} IOAPIC;
266	/** Pointer to IOAPIC data. */
267	typedef IOAPIC *PIOAPIC;
268	/** Pointer to a const IOAPIC data. */
269	typedef IOAPIC const *PCIOAPIC;
270	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
271
272	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
273
274	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
275	/**
276	* Gets the arbitration register.
277	*
278	* @returns The arbitration.
279	*/
280	DECLINLINE(uint32_t) ioapicGetArb(void)
281	{
282	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
283	return 0;
284	}
285	#endif
286
287
288	/**
289	* Gets the version register.
290	*
291	* @returns The version.
292	*/
293	DECLINLINE(uint32_t) ioapicGetVersion(void)
294	{
295	uint32_t uValue = RT_MAKE_U32(0x11, IOAPIC_MAX_REDIR_ENTRIES);
296	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
297	return uValue;
298	}
299
300
301	/**
302	* Sets the ID register.
303	*
304	* @param pThis Pointer to the IOAPIC instance.
305	* @param uValue The value to set.
306	*/
307	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
308	{
309	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
310	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & IOAPIC_ID_MASK);
311	}
312
313
314	/**
315	* Gets the ID register.
316	*
317	* @returns The ID.
318	* @param pThis Pointer to the IOAPIC instance.
319	*/
320	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
321	{
322	uint32_t uValue = (uint32_t)(pThis->u8Id & IOAPIC_ID_MASK) << 24;
323	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
324	return uValue;
325	}
326
327
328	/**
329	* Sets the index register.
330	*
331	* @param pThis Pointer to the IOAPIC instance.
332	* @param uValue The value to set.
333	*/
334	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
335	{
336	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
337	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
338	}
339
340
341	/**
342	* Gets the index register.
343	*
344	* @returns The index value.
345	*/
346	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
347	{
348	uint32_t const uValue = pThis->u8Index;
349	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
350	return uValue;
351	}
352
353
354	/**
355	* Signals the next pending interrupt for the specified Redirection Table Entry
356	* (RTE).
357	*
358	* @param pThis The IOAPIC instance.
359	* @param idxRte The index of the RTE.
360	*
361	* @remarks It is the responsibility of the caller to verify that an interrupt is
362	* pending for the pin corresponding to the RTE before calling this
363	* function.
364	*/
365	static void ioapicSignalIntrForRte(PIOAPIC pThis, uint8_t idxRte)
366	{
367	Assert(PDMCritSectIsOwner(&pThis->CritSect));
368
369	/* Ensure the RTE isn't masked. */
370	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
371	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
372	{
373	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
374	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
375	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
376	{
377	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
378	if (u8RemoteIrr)
379	{
380	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
381	return;
382	}
383	}
384
385	uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
386	uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
387	uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
388	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
389	uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
390	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
391
392	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)",
393	u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
394	u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
395
396	/*
397	* Deliver to the local APIC via the system/3-wire-APIC bus.
398	*/
399	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns),
400	u8Dest,
401	u8DestMode,
402	u8DeliveryMode,
403	u8Vector,
404	u8Polarity,
405	u8TriggerMode,
406	u32TagSrc);
407	/* Can't reschedule to R3. */
408	Assert(rc == VINF_SUCCESS);
409
410	/*
411	* For level-triggered interrupts, we set the remote IRR bit to indicate
412	* the local APIC has accepted the interrupt.
413	*
414	* For edge-triggered interrupts, we should not clear the IRR bit as it
415	* should remain intact to reflect the state of the interrupt line.
416	* The device will explicitly transition to inactive state via the
417	* ioapicSetIrq() callback.
418	*/
419	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
420	{
421	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
422	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
423	}
424	}
425	}
426
427
428	/**
429	* Gets the redirection table entry.
430	*
431	* @returns The redirection table entry.
432	* @param pThis Pointer to the IOAPIC instance.
433	* @param uIndex The index value.
434	*/
435	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
436	{
437	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
438	uint32_t uValue;
439	if (!(uIndex & 1))
440	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(IOAPIC_RTE_VALID_READ_MASK);
441	else
442	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(IOAPIC_RTE_VALID_READ_MASK);
443
444	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
445	return uValue;
446	}
447
448
449	/**
450	* Sets the redirection table entry.
451	*
452	* @param pThis Pointer to the IOAPIC instance.
453	* @param uIndex The index value.
454	* @param uValue The value to set.
455	*/
456	static int ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)
457	{
458	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
459	AssertMsg(idxRte < RT_ELEMENTS(pThis->au64RedirTable), ("Invalid index %u, expected <= %u\n", idxRte,
460	RT_ELEMENTS(pThis->au64RedirTable)));
461
462	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_MMIO_WRITE);
463	if (rc == VINF_SUCCESS)
464	{
465	/*
466	* Write the low or high 32-bit value into the specified 64-bit RTE register.
467	* Update only the valid, writable bits.
468	*/
469	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
470	if (!(uIndex & 1))
471	{
472	uint32_t const u32RteNewLo = uValue & RT_LO_U32(IOAPIC_RTE_VALID_WRITE_MASK);
473	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
474	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
475	}
476	else
477	{
478	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
479	uint64_t const u64RteNewHi = (uint64_t)(uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) << 32;
480	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
481	}
482
483	/*
484	* Signal the next pending interrupt for this RTE.
485	*/
486	uint32_t const uPinMask = UINT32_C(1) << idxRte;
487	if (pThis->uIrr & uPinMask)
488	ioapicSignalIntrForRte(pThis, idxRte);
489
490	PDMCritSectLeave(&pThis->CritSect);
491	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
492	}
493	else
494	STAM_COUNTER_INC(&pThis->StatSetRteContention);
495
496	return rc;
497	}
498
499
500	/**
501	* Gets the data register.
502	*
503	* @returns The data value.
504	* @param pThis Pointer to the IOAPIC instance.
505	*/
506	static uint32_t ioapicGetData(PCIOAPIC pThis)
507	{
508	uint8_t const uIndex = pThis->u8Index;
509	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
510	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
511	return ioapicGetRedirTableEntry(pThis, uIndex);
512
513	uint32_t uValue;
514	switch (uIndex)
515	{
516	case IOAPIC_INDIRECT_INDEX_ID:
517	uValue = ioapicGetId(pThis);
518	break;
519
520	case IOAPIC_INDIRECT_INDEX_VERSION:
521	uValue = ioapicGetVersion();
522	break;
523
524	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
525	case IOAPIC_INDIRECT_INDEX_ARB:
526	uValue = ioapicGetArb();
527	break;
528	#endif
529
530	default:
531	uValue = UINT32_C(0xffffffff);
532	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
533	break;
534	}
535	return uValue;
536	}
537
538
539	/**
540	* Sets the data register.
541	*
542	* @param pThis Pointer to the IOAPIC instance.
543	* @param uValue The value to set.
544	*/
545	static int ioapicSetData(PIOAPIC pThis, uint32_t uValue)
546	{
547	uint8_t const uIndex = pThis->u8Index;
548	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
549
550	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
551	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
552	return ioapicSetRedirTableEntry(pThis, uIndex, uValue);
553
554	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
555	ioapicSetId(pThis, uValue);
556	else
557	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
558
559	return VINF_SUCCESS;
560	}
561
562
563	/**
564	* @interface_method_impl{PDMIOAPICREG,pfnSetEoiR3}
565	*/
566	PDMBOTHCBDECL(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
567	{
568	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
569	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatSetEoi));
570	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
571
572	bool fRemoteIrrCleared = false;
573	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_MMIO_WRITE);
574	if (rc == VINF_SUCCESS)
575	{
576	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
577	{
578	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
579	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
580	{
581	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
582	fRemoteIrrCleared = true;
583	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
584
585	/*
586	* Signal the next pending interrupt for this RTE.
587	*/
588	uint32_t const uPinMask = UINT32_C(1) << idxRte;
589	if (pThis->uIrr & uPinMask)
590	ioapicSignalIntrForRte(pThis, idxRte);
591	}
592	}
593
594	PDMCritSectLeave(&pThis->CritSect);
595	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
596	}
597	else
598	STAM_COUNTER_INC(&pThis->StatEoiContention);
599
600	return rc;
601	}
602
603
604	/**
605	* @interface_method_impl{PDMIOAPICREG,pfnSetIrqR3}
606	*/
607	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
608	{
609	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
610	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
611
612	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatSetIrq));
613
614	if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))
615	{
616	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_SUCCESS);
617	AssertRC(rc);
618
619	uint8_t const idxRte = iIrq;
620	uint32_t const uPinMask = UINT32_C(1) << idxRte;
621	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
622	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
623
624	bool fActive = RT_BOOL(iLevel & 1);
625	/** @todo Polarity is busted elsewhere, we need to fix that
626	* first. See @bugref{8386#c7}. */
627	#if 0
628	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
629	fActive ^= u8Polarity; */
630	#endif
631	if (!fActive)
632	{
633	pThis->uIrr &= ~uPinMask;
634	PDMCritSectLeave(&pThis->CritSect);
635	return;
636	}
637
638	/*
639	* If the device is flip-flopping the interrupt line, there's no need to
640	* set and unset the IRR.
641	*/
642	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
643	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
644	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
645	{
646	/*
647	* For edge-triggered interrupts, we need to act only on an edge transition.
648	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)"
649	*/
650	if (!uPrevIrr)
651	{
652	if (!fFlipFlop)
653	pThis->uIrr \|= uPinMask;
654
655	if (!pThis->au32TagSrc[idxRte])
656	pThis->au32TagSrc[idxRte] = uTagSrc;
657	else
658	pThis->au32TagSrc[idxRte] = RT_BIT_32(31);
659
660	ioapicSignalIntrForRte(pThis, idxRte);
661	}
662	else
663	{
664	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
665	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
666	}
667	}
668	else
669	{
670	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
671
672	/*
673	* For level-triggered interrupts, redundant interrupts are not a problem
674	* and will eventually be delivered anyway after an EOI, but our PDM devices
675	* should not typically call us with no change to the level.
676	*/
677	if (!uPrevIrr)
678	{ /* likely */ }
679	else
680	{
681	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
682	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
683	}
684
685	if (!fFlipFlop)
686	pThis->uIrr \|= uPinMask;
687
688	if (!pThis->au32TagSrc[idxRte])
689	pThis->au32TagSrc[idxRte] = uTagSrc;
690	else
691	pThis->au32TagSrc[idxRte] = RT_BIT_32(31);
692
693	ioapicSignalIntrForRte(pThis, idxRte);
694	}
695
696	PDMCritSectLeave(&pThis->CritSect);
697	}
698	}
699
700
701	/**
702	* @interface_method_impl{PDMIOAPICREG,pfnSendMsiR3}
703	*/
704	PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
705	{
706	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
707	LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
708
709	/*
710	* Parse the message from the physical address.
711	* See Intel spec. 10.11.1 "Message Address Register Format".
712	*/
713	uint8_t const u8DestAddr = (GCPhys & VBOX_MSI_ADDR_DEST_ID_MASK) >> VBOX_MSI_ADDR_DEST_ID_SHIFT;
714	uint8_t const u8DestMode = (GCPhys >> VBOX_MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
715	/** @todo Check if we need to implement Redirection Hint Indicator. */
716	/* uint8_t const uRedirectHint = (GCPhys >> VBOX_MSI_ADDR_REDIRECTION_SHIFT) & 0x1; */
717
718	/*
719	* Parse the message data.
720	* See Intel spec. 10.11.2 "Message Data Register Format".
721	*/
722	uint8_t const u8Vector = (uValue & VBOX_MSI_DATA_VECTOR_MASK) >> VBOX_MSI_DATA_VECTOR_SHIFT;
723	uint8_t const u8TriggerMode = (uValue >> VBOX_MSI_DATA_TRIGGER_SHIFT) & 0x1;
724	uint8_t const u8DeliveryMode = (uValue >> VBOX_MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
725
726	/*
727	* Deliver to the local APIC via the system/3-wire-APIC bus.
728	*/
729	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,
730	u8DestAddr,
731	u8DestMode,
732	u8DeliveryMode,
733	u8Vector,
734	0 /* u8Polarity - N/A */,
735	u8TriggerMode,
736	uTagSrc);
737	/* Can't reschedule to R3. */
738	Assert(rc == VINF_SUCCESS);
739	}
740
741
742	/**
743	* @callback_method_impl{FNIOMMMIOREAD}
744	*/
745	PDMBOTHCBDECL(int) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
746	{
747	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
748	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatMmioRead));
749
750	int rc = VINF_SUCCESS;
751	uint32_t puValue = (uint32_t )pv;
752	uint32_t offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
753	switch (offReg)
754	{
755	case IOAPIC_DIRECT_OFF_INDEX:
756	*puValue = ioapicGetIndex(pThis);
757	break;
758
759	case IOAPIC_DIRECT_OFF_DATA:
760	*puValue = ioapicGetData(pThis);
761	break;
762
763	default:
764	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
765	rc = VINF_IOM_MMIO_UNUSED_FF;
766	break;
767	}
768
769	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
770	return rc;
771	}
772
773
774	/**
775	* @callback_method_impl{FNIOMMMIOWRITE}
776	*/
777	PDMBOTHCBDECL(int) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
778	{
779	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
780
781	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatMmioWrite));
782
783	Assert(!(GCPhysAddr & 3));
784	Assert(cb == 4);
785
786	uint32_t const uValue = (uint32_t const )pv;
787	uint32_t const offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
788
789	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p GCPhysAddr=%#RGp cb=%u uValue=%#RX32\n", pThis, GCPhysAddr, cb, uValue));
790	int rc = VINF_SUCCESS;
791	switch (offReg)
792	{
793	case IOAPIC_DIRECT_OFF_INDEX:
794	ioapicSetIndex(pThis, uValue);
795	break;
796
797	case IOAPIC_DIRECT_OFF_DATA:
798	rc = ioapicSetData(pThis, uValue);
799	break;
800
801	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
802	case IOAPIC_DIRECT_OFF_EOI:
803	rc = ioapicSetEoi(pDevIns, uValue);
804	break;
805	#endif
806
807	default:
808	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
809	break;
810	}
811
812	return rc;
813	}
814
815
816	#ifdef IN_RING3
817	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
818	static DECLCALLBACK(int) ioapicDbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
819	{
820	pValue->u32 = ioapicGetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
821	return VINF_SUCCESS;
822	}
823
824	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
825	static DECLCALLBACK(int) ioapicDbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
826	{
827	ioapicSetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
828	return VINF_SUCCESS;
829	}
830
831	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
832	static DECLCALLBACK(int) ioapicDbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
833	{
834	pValue->u32 = ioapicGetData((PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
835	return VINF_SUCCESS;
836	}
837
838	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
839	static DECLCALLBACK(int) ioapicDbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
840	{
841	return ioapicSetData(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);
842	}
843
844	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
845	static DECLCALLBACK(int) ioapicDbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
846	{
847	pValue->u32 = ioapicGetVersion();
848	return VINF_SUCCESS;
849	}
850
851	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
852	static DECLCALLBACK(int) ioapicDbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
853	{
854	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
855	pValue->u32 = ioapicGetArb(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
856	#else
857	pValue->u32 = UINT32_C(0xffffffff);
858	#endif
859	return VINF_SUCCESS;
860	}
861
862	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
863	static DECLCALLBACK(int) ioapicDbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
864	{
865	PCIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
866	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
867	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
868	return VINF_SUCCESS;
869	}
870
871	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
872	static DECLCALLBACK(int) ioapicDbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
873	{
874	PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
875	/* No locks, no checks, just do it. */
876	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
877	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
878	return VINF_SUCCESS;
879	}
880
881	/** IOREDTBLn sub fields. */
882	static DBGFREGSUBFIELD const g_aRteSubs[] =
883	{
884	{ "vector", 0, 8, 0, 0, NULL, NULL },
885	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
886	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
887	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
888	{ "polarity", 13, 1, 0, 0, NULL, NULL },
889	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
890	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
891	{ "mask", 16, 1, 0, 0, NULL, NULL },
892	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
893	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
894	#endif
895	{ "dest", 56, 8, 0, 0, NULL, NULL },
896	DBGFREGSUBFIELD_TERMINATOR()
897	};
898
899	/** Register descriptors for DBGF. */
900	static DBGFREGDESC const g_aRegDesc[] =
901	{
902	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicDbgReg_GetIndex, ioapicDbgReg_SetIndex, NULL, NULL },
903	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicDbgReg_GetData, ioapicDbgReg_SetData, NULL, NULL },
904	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetVersion, NULL, NULL, NULL },
905	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
906	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetArb, NULL, NULL, NULL },
907	#endif
908	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
909	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
910	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
911	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
912	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
913	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
914	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
915	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
916	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
917	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
918	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
919	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
920	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
921	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
922	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
923	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
924	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
925	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
926	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
927	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
928	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
929	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
930	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
931	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
932	DBGFREGDESC_TERMINATOR()
933	};
934
935
936	/**
937	* @callback_method_impl{FNDBGFHANDLERDEV}
938	*/
939	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
940	{
941	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
942	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
943
944	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
945
946	uint32_t const uId = ioapicGetId(pThis);
947	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
948	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
949
950	uint32_t const uVer = ioapicGetVersion();
951	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
952	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
953	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
954	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
955
956	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
957	uint32_t const uArb = ioapicGetArb();
958	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
959	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
960	#endif
961
962	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
963
964	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
965	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
966
967	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
968	{
969	static const char * const s_apszDeliveryModes[] =
970	{
971	"Fixed ",
972	"LowPri",
973	"SMI ",
974	"Rsvd ",
975	"NMI ",
976	"INIT ",
977	"Rsvd ",
978	"ExtINT"
979	};
980
981	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
982	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
983	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
984	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
985	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
986	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
987	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
988	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
989	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
990	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
991	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
992	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
993
994	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
995	idxRte,
996	pszDestMode,
997	uDest,
998	uMask,
999	(pThis->uIrr >> idxRte) & 1,
1000	pszTriggerMode,
1001	uRemoteIrr,
1002	pszPolarity,
1003	pszDeliveryStatus,
1004	pszDeliveryMode,
1005	uVector,
1006	u64Rte);
1007	}
1008	}
1009
1010
1011	/**
1012	* @copydoc FNSSMDEVSAVEEXEC
1013	*/
1014	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1015	{
1016	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
1017	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1018
1019	SSMR3PutU32(pSSM, pThis->uIrr);
1020	SSMR3PutU8(pSSM, pThis->u8Id);
1021	SSMR3PutU8(pSSM, pThis->u8Index);
1022	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1023	SSMR3PutU64(pSSM, pThis->au64RedirTable[idxRte]);
1024
1025	return VINF_SUCCESS;
1026	}
1027
1028
1029	/**
1030	* @copydoc FNSSMDEVLOADEXEC
1031	*/
1032	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1033	{
1034	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1035	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1036
1037	Assert(uPass == SSM_PASS_FINAL);
1038	NOREF(uPass);
1039
1040	/* Weed out invalid versions. */
1041	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1042	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1043	{
1044	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1045	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1046	}
1047
1048	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1049	SSMR3GetU32(pSSM, (uint32_t *)&pThis->uIrr);
1050
1051	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Id);
1052	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Index);
1053	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1054	SSMR3GetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1055
1056	return VINF_SUCCESS;
1057	}
1058
1059
1060	/**
1061	* @interface_method_impl{PDMDEVREG,pfnReset}
1062	*/
1063	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1064	{
1065	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1066	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1067
1068	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1069	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1070
1071	pThis->uIrr = 0;
1072	pThis->u8Index = 0;
1073	pThis->u8Id = 0;
1074
1075	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1076	{
1077	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1078	pThis->au32TagSrc[idxRte] = 0;
1079	}
1080
1081	PDMCritSectLeave(&pThis->CritSect);
1082	}
1083
1084
1085	/**
1086	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1087	*/
1088	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1089	{
1090	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1091	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", pThis, offDelta));
1092
1093	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1094	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1095	}
1096
1097
1098	/**
1099	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1100	*/
1101	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1102	{
1103	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1104	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1105	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1106
1107	/*
1108	* Destroy the RTE critical section.
1109	*/
1110	if (PDMCritSectIsInitialized(&pThis->CritSect))
1111	PDMR3CritSectDelete(&pThis->CritSect);
1112
1113	return VINF_SUCCESS;
1114	}
1115
1116
1117	/**
1118	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1119	*/
1120	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1121	{
1122	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1123	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1124	Assert(iInstance == 0);
1125
1126	/*
1127	* Initialize the state data.
1128	*/
1129	pThis->pDevInsR3 = pDevIns;
1130	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1131	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1132
1133	/*
1134	* Validate and read the configuration.
1135	*/
1136	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|RZEnabled", "");
1137
1138	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1139	upsets some guest which we haven't yet tested. */
1140	uint32_t cCpus;
1141	int rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1142	if (RT_FAILURE(rc))
1143	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1144	pThis->cCpus = (uint8_t)cCpus;
1145
1146	bool fRZEnabled;
1147	rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
1148	if (RT_FAILURE(rc))
1149	return PDMDEV_SET_ERROR(pDevIns, rc,
1150	N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
1151
1152	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool\n", cCpus, fRZEnabled));
1153
1154	/*
1155	* We will use our own critical section for the IOAPIC device.
1156	*/
1157	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1158	AssertRCReturn(rc, rc);
1159
1160	/*
1161	* Setup the critical section to protect concurrent writes to the RTEs.
1162	*/
1163	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1164	if (RT_FAILURE(rc))
1165	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("IOAPIC: Failed to create critical section. rc=%Rrc"), rc);
1166
1167	/*
1168	* Register the IOAPIC.
1169	*/
1170	PDMIOAPICREG IoApicReg;
1171	RT_ZERO(IoApicReg);
1172	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1173	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
1174	IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
1175	IoApicReg.pfnSetEoiR3 = ioapicSetEoi;
1176	if (fRZEnabled)
1177	{
1178	IoApicReg.pszSetIrqRC = "ioapicSetIrq";
1179	IoApicReg.pszSetIrqR0 = "ioapicSetIrq";
1180
1181	IoApicReg.pszSendMsiRC = "ioapicSendMsi";
1182	IoApicReg.pszSendMsiR0 = "ioapicSendMsi";
1183
1184	IoApicReg.pszSetEoiRC = "ioapicSetEoi";
1185	IoApicReg.pszSetEoiR0 = "ioapicSetEoi";
1186	}
1187	rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
1188	if (RT_FAILURE(rc))
1189	{
1190	AssertMsgFailed(("IOAPIC: PDMDevHlpIOAPICRegister failed! rc=%Rrc\n", rc));
1191	return rc;
1192	}
1193
1194	/*
1195	* Register MMIO callbacks.
1196	*/
1197	rc = PDMDevHlpMMIORegister(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, pThis,
1198	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead,
1199	"I/O APIC");
1200	if (RT_SUCCESS(rc))
1201	{
1202	if (fRZEnabled)
1203	{
1204	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1205	rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
1206	"ioapicMmioWrite", "ioapicMmioRead");
1207	AssertRCReturn(rc, rc);
1208
1209	pThis->pIoApicHlpR0 = pThis->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1210	rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
1211	"ioapicMmioWrite", "ioapicMmioRead");
1212	AssertRCReturn(rc, rc);
1213	}
1214	}
1215	else
1216	{
1217	LogRel(("IOAPIC: PDMDevHlpMMIORegister failed! rc=%Rrc\n", rc));
1218	return rc;
1219	}
1220
1221	/*
1222	* Register saved-state callbacks.
1223	*/
1224	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1225	if (RT_FAILURE(rc))
1226	{
1227	LogRel(("IOAPIC: PDMDevHlpSSMRegister failed! rc=%Rrc\n", rc));
1228	return rc;
1229	}
1230
1231	/*
1232	* Register debugger info callback.
1233	*/
1234	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1235	AssertRCReturn(rc, rc);
1236
1237	/*
1238	* Register debugger register access.
1239	*/
1240	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); AssertRC(rc);
1241	AssertRCReturn(rc, rc);
1242
1243	#ifdef VBOX_WITH_STATISTICS
1244	/*
1245	* Statistics.
1246	*/
1247	bool fHasRC = !HMIsEnabled(PDMDevHlpGetVM(pDevIns));
1248	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/MmioReadR0", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R0.");
1249	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/MmioWriteR0", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R0.");
1250	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/SetIrqR0", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R0.");
1251	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR0, STAMTYPE_COUNTER, "/Devices/IOAPIC/R0/SetEoiR0", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R0.");
1252
1253	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1254	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1255	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1256	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1257
1258	if (fHasRC)
1259	{
1260	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/MmioReadRC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RC.");
1261	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/MmioWriteRC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RC.");
1262	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/SetIrqRC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RC.");
1263	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRC, STAMTYPE_COUNTER, "/Devices/IOAPIC/RC/SetEoiRC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RC.");
1264	}
1265
1266	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1267	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1268	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1269
1270	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1271	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1272	#endif
1273
1274	/*
1275	* Init. the device state.
1276	*/
1277	LogRel(("IOAPIC: Using implementation 2.0!\n"));
1278	ioapicR3Reset(pDevIns);
1279
1280	return VINF_SUCCESS;
1281	}
1282
1283
1284	/**
1285	* IO APIC device registration structure.
1286	*/
1287	const PDMDEVREG g_DeviceIOAPIC =
1288	{
1289	/* u32Version */
1290	PDM_DEVREG_VERSION,
1291	/* szName */
1292	"ioapic",
1293	/* szRCMod */
1294	"VBoxDDRC.rc",
1295	/* szR0Mod */
1296	"VBoxDDR0.r0",
1297	/* pszDescription */
1298	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1299	/* fFlags */
1300	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36
1301	\| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1302	/* fClass */
1303	PDM_DEVREG_CLASS_PIC,
1304	/* cMaxInstances */
1305	1,
1306	/* cbInstance */
1307	sizeof(IOAPIC),
1308	/* pfnConstruct */
1309	ioapicR3Construct,
1310	/* pfnDestruct */
1311	ioapicR3Destruct,
1312	/* pfnRelocate */
1313	ioapicR3Relocate,
1314	/* pfnMemSetup */
1315	NULL,
1316	/* pfnPowerOn */
1317	NULL,
1318	/* pfnReset */
1319	ioapicR3Reset,
1320	/* pfnSuspend */
1321	NULL,
1322	/* pfnResume */
1323	NULL,
1324	/* pfnAttach */
1325	NULL,
1326	/* pfnDetach */
1327	NULL,
1328	/* pfnQueryInterface. */
1329	NULL,
1330	/* pfnInitComplete */
1331	NULL,
1332	/* pfnPowerOff */
1333	NULL,
1334	/* pfnSoftReset */
1335	NULL,
1336	/* u32VersionEnd */
1337	PDM_DEVREG_VERSION
1338	};
1339
1340	#endif /* IN_RING3 */
1341
1342	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1343

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source: vbox/trunk/src/VBox/Devices/PC/DevIOAPIC_New.cpp@ 61815

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