DevIOAPIC_New.cpp@ 61847

Last change on this file since 61847 was 61847, checked in by vboxsync, 9 years ago
IOAPIC, VMM/APIC: Use dedicated rc for when the APIC doesn't accept an IRQ (very rare but can happen). Also added more stats, assertions to verify interrupt delivery a bit better.
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1	/* $Id: DevIOAPIC_New.cpp 61847 2016-06-23 12:03:01Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/** The current IO APIC saved state version. */
36	#define IOAPIC_SAVED_STATE_VERSION 2
37	/** The saved state version used by VirtualBox 5.0 and
38	* earlier. */
39	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
40
41	/** Implementation specified by the "Intel I/O Controller Hub 9
42	* (ICH9) Family" */
43	#define IOAPIC_HARDWARE_VERSION_ICH9 1
44	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
45	Controller" */
46	#define IOAPIC_HARDWARE_VERSION_82093AA 2
47	/** The IO APIC implementation to use. */
48	#define IOAPIC_HARDWARE_VERSION IOAPIC_HARDWARE_VERSION_ICH9
49
50	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
51	/** The version. */
52	# define IOAPIC_VERSION 0x11
53	/** The ID mask. */
54	# define IOAPIC_ID_MASK 0x0f
55	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
56	/** The version. */
57	# define IOAPIC_VERSION 0x20
58	/** The ID mask. */
59	# define IOAPIC_ID_MASK 0xff
60	#else
61	# error "Implement me"
62	#endif
63
64	/** The default MMIO base physical address. */
65	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
66	/** The size of the MMIO range. */
67	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
68	/** The mask for getting direct registers from physical address. */
69	#define IOAPIC_MMIO_REG_MASK 0xff
70
71	/** The number of interrupt input pins. */
72	#define IOAPIC_NUM_INTR_PINS 24
73	/** Maximum redirection entires. */
74	#define IOAPIC_MAX_REDIR_ENTRIES (IOAPIC_NUM_INTR_PINS - 1)
75
76	/** Version register - Gets the version. */
77	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
78	/** Version register - Gets the maximum redirection entry. */
79	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
80	/** Version register - Gets whether Pin Assertion Register (PRQ) is
81	* supported. */
82	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
83
84	/** Index register - Valid write mask. */
85	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
86
87	/** Arbitration register - Gets the ID. */
88	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
89
90	/** ID register - Gets the ID. */
91	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & IOAPIC_ID_MASK)
92
93	/** Redirection table entry - Vector. */
94	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
95	/** Redirection table entry - Delivery mode. */
96	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
97	/** Redirection table entry - Destination mode. */
98	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
99	/** Redirection table entry - Delivery status. */
100	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
101	/** Redirection table entry - Interrupt input pin polarity. */
102	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
103	/** Redirection table entry - Remote IRR. */
104	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
105	/** Redirection table entry - Trigger Mode. */
106	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
107	/** Redirection table entry - the mask bit number. */
108	#define IOAPIC_RTE_MASK_BIT 16
109	/** Redirection table entry - the mask. */
110	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
111	/** Redirection table entry - Extended Destination ID. */
112	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
113	/** Redirection table entry - Destination. */
114	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
115
116	/** Redirection table entry - Gets the destination. */
117	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
118	/** Redirection table entry - Gets the mask flag. */
119	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
120	/** Redirection table entry - Checks whether it's masked. */
121	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
122	/** Redirection table entry - Gets the trigger mode. */
123	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
124	/** Redirection table entry - Gets the remote IRR flag. */
125	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
126	/** Redirection table entry - Gets the interrupt pin polarity. */
127	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
128	/** Redirection table entry - Gets the delivery status. */
129	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
130	/** Redirection table entry - Gets the destination mode. */
131	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
132	/** Redirection table entry - Gets the delivery mode. */
133	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
134	/** Redirection table entry - Gets the vector. */
135	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
136	/** Redirection table entry - Valid write mask. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
139	\| IOAPIC_RTE_VECTOR)
140
141	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
142	/** Redirection table entry - Valid read mask. */
143	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
144	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
145	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
146	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
147	/** Redirection table entry - Valid read mask. */
148	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
149	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
150	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
151	\| IOAPIC_RTE_VECTOR)
152	#endif
153	/** Redirection table entry - Trigger mode edge. */
154	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
155	/** Redirection table entry - Trigger mode level. */
156	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
157	/** Redirection table entry - Destination mode physical. */
158	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
159	/** Redirection table entry - Destination mode logical. */
160	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
161
162
163	/** Index of indirect registers in the I/O APIC register table. */
164	#define IOAPIC_INDIRECT_INDEX_ID 0x0
165	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
166	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
167	# define IOAPIC_INDIRECT_INDEX_ARB 0x2
168	#endif
169	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10
170	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_END 0x3F
171
172	/** Offset of direct registers in the I/O APIC MMIO space. */
173	#define IOAPIC_DIRECT_OFF_INDEX 0x00
174	#define IOAPIC_DIRECT_OFF_DATA 0x10
175	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
176	# define IOAPIC_DIRECT_OFF_EOI 0x40
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The per-VM I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The device instance - R3 Ptr. */
189	PPDMDEVINSR3 pDevInsR3;
190	/** The IOAPIC helpers - R3 Ptr. */
191	PCPDMIOAPICHLPR3 pIoApicHlpR3;
192
193	/** The device instance - R0 Ptr. */
194	PPDMDEVINSR0 pDevInsR0;
195	/** The IOAPIC helpers - R0 Ptr. */
196	PCPDMIOAPICHLPR0 pIoApicHlpR0;
197
198	/** The device instance - RC Ptr. */
199	PPDMDEVINSRC pDevInsRC;
200	/** The IOAPIC helpers - RC Ptr. */
201	PCPDMIOAPICHLPRC pIoApicHlpRC;
202
203	/** The ID register. */
204	uint8_t volatile u8Id;
205	/** The index register. */
206	uint8_t volatile u8Index;
207	/** Number of CPUs. */
208	uint8_t cCpus;
209	/* Alignment padding. */
210	uint8_t u8Padding0[5];
211
212	/** The redirection table registers. */
213	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
214	/** The IRQ tags and source IDs for each pin (tracing purposes). */
215	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
216
217	/** Alignment padding. */
218	uint32_t u32Padding2;
219	/** The internal IRR reflecting state of the interrupt lines. */
220	uint32_t uIrr;
221
222	/** The critsect for updating to the RTEs. */
223	PDMCRITSECT CritSect;
224
225	#ifdef VBOX_WITH_STATISTICS
226	/** Number of MMIO reads in RZ. */
227	STAMCOUNTER StatMmioReadRZ;
228	/** Number of MMIO reads in R3. */
229	STAMCOUNTER StatMmioReadR3;
230
231	/** Number of MMIO writes in RZ. */
232	STAMCOUNTER StatMmioWriteRZ;
233	/** Number of MMIO writes in R3. */
234	STAMCOUNTER StatMmioWriteR3;
235
236	/** Number of SetIrq calls in RZ. */
237	STAMCOUNTER StatSetIrqRZ;
238	/** Number of SetIrq calls in R3. */
239	STAMCOUNTER StatSetIrqR3;
240
241	/** Number of SetEoi calls in RZ. */
242	STAMCOUNTER StatSetEoiRZ;
243	/** Number of SetEoi calls in R3. */
244	STAMCOUNTER StatSetEoiR3;
245
246	/** Number of redundant edge-triggered interrupts. */
247	STAMCOUNTER StatRedundantEdgeIntr;
248	/** Number of redundant level-triggered interrupts. */
249	STAMCOUNTER StatRedundantLevelIntr;
250	/** Number of suppressed level-triggered interrupts (by remote IRR). */
251	STAMCOUNTER StatSuppressedLevelIntr;
252	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
253	STAMCOUNTER StatEoiContention;
254	/** Number of returns to ring-3 due to Set RTE lock contention. */
255	STAMCOUNTER StatSetRteContention;
256	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
257	STAMCOUNTER StatLevelIrqSent;
258	/** Number of EOIs received for level-triggered interrupts from the local
259	* APIC(s). */
260	STAMCOUNTER StatEoiReceived;
261	#endif
262	} IOAPIC;
263	/** Pointer to IOAPIC data. */
264	typedef IOAPIC *PIOAPIC;
265	/** Pointer to a const IOAPIC data. */
266	typedef IOAPIC const *PCIOAPIC;
267	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
268
269	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
270
271	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
272	/**
273	* Gets the arbitration register.
274	*
275	* @returns The arbitration.
276	*/
277	DECLINLINE(uint32_t) ioapicGetArb(void)
278	{
279	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
280	return 0;
281	}
282	#endif
283
284
285	/**
286	* Gets the version register.
287	*
288	* @returns The version.
289	*/
290	DECLINLINE(uint32_t) ioapicGetVersion(void)
291	{
292	uint32_t uValue = RT_MAKE_U32(IOAPIC_VERSION, IOAPIC_MAX_REDIR_ENTRIES);
293	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
294	return uValue;
295	}
296
297
298	/**
299	* Sets the ID register.
300	*
301	* @param pThis Pointer to the IOAPIC instance.
302	* @param uValue The value to set.
303	*/
304	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
305	{
306	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
307	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & IOAPIC_ID_MASK);
308	}
309
310
311	/**
312	* Gets the ID register.
313	*
314	* @returns The ID.
315	* @param pThis Pointer to the IOAPIC instance.
316	*/
317	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
318	{
319	uint32_t uValue = (uint32_t)(pThis->u8Id & IOAPIC_ID_MASK) << 24;
320	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
321	return uValue;
322	}
323
324
325	/**
326	* Sets the index register.
327	*
328	* @param pThis Pointer to the IOAPIC instance.
329	* @param uValue The value to set.
330	*/
331	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
332	{
333	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
334	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
335	}
336
337
338	/**
339	* Gets the index register.
340	*
341	* @returns The index value.
342	*/
343	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
344	{
345	uint32_t const uValue = pThis->u8Index;
346	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
347	return uValue;
348	}
349
350
351	/**
352	* Signals the next pending interrupt for the specified Redirection Table Entry
353	* (RTE).
354	*
355	* @param pThis The IOAPIC instance.
356	* @param idxRte The index of the RTE.
357	*
358	* @remarks It is the responsibility of the caller to verify that an interrupt is
359	* pending for the pin corresponding to the RTE before calling this
360	* function.
361	*/
362	static void ioapicSignalIntrForRte(PIOAPIC pThis, uint8_t idxRte)
363	{
364	Assert(PDMCritSectIsOwner(&pThis->CritSect));
365
366	/* Ensure the RTE isn't masked. */
367	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
368	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
369	{
370	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
371	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
372	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
373	{
374	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
375	if (u8RemoteIrr)
376	{
377	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
378	return;
379	}
380	}
381
382	uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
383	uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
384	uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
385	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
386	uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
387	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
388
389	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)",
390	u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
391	u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
392
393	/*
394	* Deliver to the local APIC via the system/3-wire-APIC bus.
395	*/
396	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns),
397	u8Dest,
398	u8DestMode,
399	u8DeliveryMode,
400	u8Vector,
401	u8Polarity,
402	u8TriggerMode,
403	u32TagSrc);
404	/* Can't reschedule to R3. */
405	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
406	#ifdef DEBUG_ramshankar
407	if (rc == VERR_APIC_INTR_DISCARDED)
408	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
409	#endif
410
411	/*
412	* For level-triggered interrupts, we set the remote IRR bit to indicate
413	* the local APIC has accepted the interrupt.
414	*
415	* For edge-triggered interrupts, we should not clear the IRR bit as it
416	* should remain intact to reflect the state of the interrupt line.
417	* The device will explicitly transition to inactive state via the
418	* ioapicSetIrq() callback.
419	*/
420	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
421	&& rc == VINF_SUCCESS)
422	{
423	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
424	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
425	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
426	}
427	}
428	}
429
430
431	/**
432	* Gets the redirection table entry.
433	*
434	* @returns The redirection table entry.
435	* @param pThis Pointer to the IOAPIC instance.
436	* @param uIndex The index value.
437	*/
438	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
439	{
440	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
441	uint32_t uValue;
442	if (!(uIndex & 1))
443	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(IOAPIC_RTE_VALID_READ_MASK);
444	else
445	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(IOAPIC_RTE_VALID_READ_MASK);
446
447	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
448	return uValue;
449	}
450
451
452	/**
453	* Sets the redirection table entry.
454	*
455	* @param pThis Pointer to the IOAPIC instance.
456	* @param uIndex The index value.
457	* @param uValue The value to set.
458	*/
459	static int ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)
460	{
461	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
462	AssertMsg(idxRte < RT_ELEMENTS(pThis->au64RedirTable), ("Invalid index %u, expected <= %u\n", idxRte,
463	RT_ELEMENTS(pThis->au64RedirTable)));
464
465	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_MMIO_WRITE);
466	if (rc == VINF_SUCCESS)
467	{
468	/*
469	* Write the low or high 32-bit value into the specified 64-bit RTE register.
470	* Update only the valid, writable bits.
471	*/
472	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
473	if (!(uIndex & 1))
474	{
475	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(IOAPIC_RTE_VALID_WRITE_MASK);
476	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(IOAPIC_RTE_VALID_WRITE_MASK)) \| u32RtePreserveLo;
477	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
478	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
479	}
480	else
481	{
482	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK);
483	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
484	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) \| u32RtePreserveHi) << 32);
485	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
486	}
487
488	/*
489	* Signal the next pending interrupt for this RTE.
490	*/
491	uint32_t const uPinMask = UINT32_C(1) << idxRte;
492	if (pThis->uIrr & uPinMask)
493	ioapicSignalIntrForRte(pThis, idxRte);
494
495	PDMCritSectLeave(&pThis->CritSect);
496	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
497	}
498	else
499	STAM_COUNTER_INC(&pThis->StatSetRteContention);
500
501	return rc;
502	}
503
504
505	/**
506	* Gets the data register.
507	*
508	* @returns The data value.
509	* @param pThis Pointer to the IOAPIC instance.
510	*/
511	static uint32_t ioapicGetData(PCIOAPIC pThis)
512	{
513	uint8_t const uIndex = pThis->u8Index;
514	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
515	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
516	return ioapicGetRedirTableEntry(pThis, uIndex);
517
518	uint32_t uValue;
519	switch (uIndex)
520	{
521	case IOAPIC_INDIRECT_INDEX_ID:
522	uValue = ioapicGetId(pThis);
523	break;
524
525	case IOAPIC_INDIRECT_INDEX_VERSION:
526	uValue = ioapicGetVersion();
527	break;
528
529	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
530	case IOAPIC_INDIRECT_INDEX_ARB:
531	uValue = ioapicGetArb();
532	break;
533	#endif
534
535	default:
536	uValue = UINT32_C(0xffffffff);
537	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
538	break;
539	}
540	return uValue;
541	}
542
543
544	/**
545	* Sets the data register.
546	*
547	* @param pThis Pointer to the IOAPIC instance.
548	* @param uValue The value to set.
549	*/
550	static int ioapicSetData(PIOAPIC pThis, uint32_t uValue)
551	{
552	uint8_t const uIndex = pThis->u8Index;
553	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
554
555	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
556	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
557	return ioapicSetRedirTableEntry(pThis, uIndex, uValue);
558
559	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
560	ioapicSetId(pThis, uValue);
561	else
562	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
563
564	return VINF_SUCCESS;
565	}
566
567
568	/**
569	* @interface_method_impl{PDMIOAPICREG,pfnSetEoiR3}
570	*/
571	PDMBOTHCBDECL(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
572	{
573	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
574	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
575	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
576
577	bool fRemoteIrrCleared = false;
578	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_MMIO_WRITE);
579	if (rc == VINF_SUCCESS)
580	{
581	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
582	{
583	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
584	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
585	{
586	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
587	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
588	fRemoteIrrCleared = true;
589	STAM_COUNTER_INC(&pThis->StatEoiReceived);
590	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
591
592	/*
593	* Signal the next pending interrupt for this RTE.
594	*/
595	uint32_t const uPinMask = UINT32_C(1) << idxRte;
596	if (pThis->uIrr & uPinMask)
597	ioapicSignalIntrForRte(pThis, idxRte);
598	}
599	}
600
601	PDMCritSectLeave(&pThis->CritSect);
602	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
603	}
604	else
605	STAM_COUNTER_INC(&pThis->StatEoiContention);
606
607	return rc;
608	}
609
610
611	/**
612	* @interface_method_impl{PDMIOAPICREG,pfnSetIrqR3}
613	*/
614	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
615	{
616	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
617	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
618
619	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
620
621	if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))
622	{
623	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_SUCCESS);
624	AssertRC(rc);
625
626	uint8_t const idxRte = iIrq;
627	uint32_t const uPinMask = UINT32_C(1) << idxRte;
628	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
629	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
630
631	bool fActive = RT_BOOL(iLevel & 1);
632	/** @todo Polarity is busted elsewhere, we need to fix that
633	* first. See @bugref{8386#c7}. */
634	#if 0
635	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
636	fActive ^= u8Polarity; */
637	#endif
638	if (!fActive)
639	{
640	pThis->uIrr &= ~uPinMask;
641	PDMCritSectLeave(&pThis->CritSect);
642	return;
643	}
644
645	/*
646	* If the device is flip-flopping the interrupt line, there's no need to
647	* set and unset the IRR.
648	*/
649	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
650	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
651	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
652	{
653	/*
654	* For edge-triggered interrupts, we need to act only on an edge transition.
655	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)"
656	*/
657	if (!uPrevIrr)
658	{
659	if (!fFlipFlop)
660	pThis->uIrr \|= uPinMask;
661
662	if (!pThis->au32TagSrc[idxRte])
663	pThis->au32TagSrc[idxRte] = uTagSrc;
664	else
665	pThis->au32TagSrc[idxRte] = RT_BIT_32(31);
666
667	ioapicSignalIntrForRte(pThis, idxRte);
668	}
669	else
670	{
671	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
672	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
673	}
674	}
675	else
676	{
677	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
678
679	/*
680	* For level-triggered interrupts, redundant interrupts are not a problem
681	* and will eventually be delivered anyway after an EOI, but our PDM devices
682	* should not typically call us with no change to the level.
683	*/
684	if (!uPrevIrr)
685	{ /* likely */ }
686	else
687	{
688	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
689	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
690	}
691
692	if (!fFlipFlop)
693	pThis->uIrr \|= uPinMask;
694
695	if (!pThis->au32TagSrc[idxRte])
696	pThis->au32TagSrc[idxRte] = uTagSrc;
697	else
698	pThis->au32TagSrc[idxRte] = RT_BIT_32(31);
699
700	ioapicSignalIntrForRte(pThis, idxRte);
701	}
702
703	PDMCritSectLeave(&pThis->CritSect);
704	}
705	}
706
707
708	/**
709	* @interface_method_impl{PDMIOAPICREG,pfnSendMsiR3}
710	*/
711	PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
712	{
713	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
714	LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
715
716	/*
717	* Parse the message from the physical address.
718	* See Intel spec. 10.11.1 "Message Address Register Format".
719	*/
720	uint8_t const u8DestAddr = (GCPhys & VBOX_MSI_ADDR_DEST_ID_MASK) >> VBOX_MSI_ADDR_DEST_ID_SHIFT;
721	uint8_t const u8DestMode = (GCPhys >> VBOX_MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
722	/** @todo Check if we need to implement Redirection Hint Indicator. */
723	/* uint8_t const uRedirectHint = (GCPhys >> VBOX_MSI_ADDR_REDIRECTION_SHIFT) & 0x1; */
724
725	/*
726	* Parse the message data.
727	* See Intel spec. 10.11.2 "Message Data Register Format".
728	*/
729	uint8_t const u8Vector = (uValue & VBOX_MSI_DATA_VECTOR_MASK) >> VBOX_MSI_DATA_VECTOR_SHIFT;
730	uint8_t const u8TriggerMode = (uValue >> VBOX_MSI_DATA_TRIGGER_SHIFT) & 0x1;
731	uint8_t const u8DeliveryMode = (uValue >> VBOX_MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
732
733	/*
734	* Deliver to the local APIC via the system/3-wire-APIC bus.
735	*/
736	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,
737	u8DestAddr,
738	u8DestMode,
739	u8DeliveryMode,
740	u8Vector,
741	0 /* u8Polarity - N/A */,
742	u8TriggerMode,
743	uTagSrc);
744	/* Can't reschedule to R3. */
745	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
746	}
747
748
749	/**
750	* @callback_method_impl{FNIOMMMIOREAD}
751	*/
752	PDMBOTHCBDECL(int) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
753	{
754	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
755	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
756
757	int rc = VINF_SUCCESS;
758	uint32_t puValue = (uint32_t )pv;
759	uint32_t offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
760	switch (offReg)
761	{
762	case IOAPIC_DIRECT_OFF_INDEX:
763	*puValue = ioapicGetIndex(pThis);
764	break;
765
766	case IOAPIC_DIRECT_OFF_DATA:
767	*puValue = ioapicGetData(pThis);
768	break;
769
770	default:
771	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
772	rc = VINF_IOM_MMIO_UNUSED_FF;
773	break;
774	}
775
776	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
777	return rc;
778	}
779
780
781	/**
782	* @callback_method_impl{FNIOMMMIOWRITE}
783	*/
784	PDMBOTHCBDECL(int) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
785	{
786	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
787
788	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
789
790	Assert(!(GCPhysAddr & 3));
791	Assert(cb == 4);
792
793	uint32_t const uValue = (uint32_t const )pv;
794	uint32_t const offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
795
796	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p GCPhysAddr=%#RGp cb=%u uValue=%#RX32\n", pThis, GCPhysAddr, cb, uValue));
797	int rc = VINF_SUCCESS;
798	switch (offReg)
799	{
800	case IOAPIC_DIRECT_OFF_INDEX:
801	ioapicSetIndex(pThis, uValue);
802	break;
803
804	case IOAPIC_DIRECT_OFF_DATA:
805	rc = ioapicSetData(pThis, uValue);
806	break;
807
808	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
809	case IOAPIC_DIRECT_OFF_EOI:
810	rc = ioapicSetEoi(pDevIns, uValue);
811	break;
812	#endif
813
814	default:
815	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
816	break;
817	}
818
819	return rc;
820	}
821
822
823	#ifdef IN_RING3
824	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
825	static DECLCALLBACK(int) ioapicDbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
826	{
827	pValue->u32 = ioapicGetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
828	return VINF_SUCCESS;
829	}
830
831	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
832	static DECLCALLBACK(int) ioapicDbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
833	{
834	ioapicSetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
835	return VINF_SUCCESS;
836	}
837
838	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
839	static DECLCALLBACK(int) ioapicDbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
840	{
841	pValue->u32 = ioapicGetData((PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
842	return VINF_SUCCESS;
843	}
844
845	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
846	static DECLCALLBACK(int) ioapicDbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
847	{
848	return ioapicSetData(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);
849	}
850
851	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
852	static DECLCALLBACK(int) ioapicDbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
853	{
854	pValue->u32 = ioapicGetVersion();
855	return VINF_SUCCESS;
856	}
857
858	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
859	static DECLCALLBACK(int) ioapicDbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
860	{
861	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
862	pValue->u32 = ioapicGetArb(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
863	#else
864	pValue->u32 = UINT32_C(0xffffffff);
865	#endif
866	return VINF_SUCCESS;
867	}
868
869	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
870	static DECLCALLBACK(int) ioapicDbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
871	{
872	PCIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
873	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
874	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
875	return VINF_SUCCESS;
876	}
877
878	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
879	static DECLCALLBACK(int) ioapicDbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
880	{
881	PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
882	/* No locks, no checks, just do it. */
883	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
884	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
885	return VINF_SUCCESS;
886	}
887
888	/** IOREDTBLn sub fields. */
889	static DBGFREGSUBFIELD const g_aRteSubs[] =
890	{
891	{ "vector", 0, 8, 0, 0, NULL, NULL },
892	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
893	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
894	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
895	{ "polarity", 13, 1, 0, 0, NULL, NULL },
896	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
897	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
898	{ "mask", 16, 1, 0, 0, NULL, NULL },
899	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
900	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
901	#endif
902	{ "dest", 56, 8, 0, 0, NULL, NULL },
903	DBGFREGSUBFIELD_TERMINATOR()
904	};
905
906	/** Register descriptors for DBGF. */
907	static DBGFREGDESC const g_aRegDesc[] =
908	{
909	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicDbgReg_GetIndex, ioapicDbgReg_SetIndex, NULL, NULL },
910	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicDbgReg_GetData, ioapicDbgReg_SetData, NULL, NULL },
911	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetVersion, NULL, NULL, NULL },
912	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
913	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetArb, NULL, NULL, NULL },
914	#endif
915	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
916	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
917	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
918	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
919	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
920	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
921	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
922	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
923	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
924	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
925	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
926	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
927	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
928	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
929	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
930	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
931	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
932	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
933	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
934	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
935	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
936	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
937	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
938	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
939	DBGFREGDESC_TERMINATOR()
940	};
941
942
943	/**
944	* @callback_method_impl{FNDBGFHANDLERDEV}
945	*/
946	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
947	{
948	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
949	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
950
951	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
952
953	uint32_t const uId = ioapicGetId(pThis);
954	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
955	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
956
957	uint32_t const uVer = ioapicGetVersion();
958	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
959	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
960	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
961	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
962
963	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
964	uint32_t const uArb = ioapicGetArb();
965	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
966	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
967	#endif
968
969	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
970
971	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
972	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
973
974	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
975	{
976	static const char * const s_apszDeliveryModes[] =
977	{
978	"Fixed ",
979	"LowPri",
980	"SMI ",
981	"Rsvd ",
982	"NMI ",
983	"INIT ",
984	"Rsvd ",
985	"ExtINT"
986	};
987
988	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
989	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
990	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
991	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
992	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
993	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
994	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
995	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
996	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
997	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
998	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
999	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1000
1001	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1002	idxRte,
1003	pszDestMode,
1004	uDest,
1005	uMask,
1006	(pThis->uIrr >> idxRte) & 1,
1007	pszTriggerMode,
1008	uRemoteIrr,
1009	pszPolarity,
1010	pszDeliveryStatus,
1011	pszDeliveryMode,
1012	uVector,
1013	u64Rte);
1014	}
1015	}
1016
1017
1018	/**
1019	* @copydoc FNSSMDEVSAVEEXEC
1020	*/
1021	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1022	{
1023	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
1024	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1025
1026	SSMR3PutU32(pSSM, pThis->uIrr);
1027	SSMR3PutU8(pSSM, pThis->u8Id);
1028	SSMR3PutU8(pSSM, pThis->u8Index);
1029	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1030	SSMR3PutU64(pSSM, pThis->au64RedirTable[idxRte]);
1031
1032	return VINF_SUCCESS;
1033	}
1034
1035
1036	/**
1037	* @copydoc FNSSMDEVLOADEXEC
1038	*/
1039	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1040	{
1041	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1042	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1043
1044	Assert(uPass == SSM_PASS_FINAL);
1045	NOREF(uPass);
1046
1047	/* Weed out invalid versions. */
1048	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1049	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1050	{
1051	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1052	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1053	}
1054
1055	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1056	SSMR3GetU32(pSSM, (uint32_t *)&pThis->uIrr);
1057
1058	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Id);
1059	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Index);
1060	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1061	SSMR3GetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1062
1063	return VINF_SUCCESS;
1064	}
1065
1066
1067	/**
1068	* @interface_method_impl{PDMDEVREG,pfnReset}
1069	*/
1070	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1071	{
1072	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1073	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1074
1075	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1076	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1077
1078	pThis->uIrr = 0;
1079	pThis->u8Index = 0;
1080	pThis->u8Id = 0;
1081
1082	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1083	{
1084	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1085	pThis->au32TagSrc[idxRte] = 0;
1086	}
1087
1088	PDMCritSectLeave(&pThis->CritSect);
1089	}
1090
1091
1092	/**
1093	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1094	*/
1095	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1096	{
1097	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1098	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", pThis, offDelta));
1099
1100	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1101	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1102	}
1103
1104
1105	/**
1106	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1107	*/
1108	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1109	{
1110	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1111	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1112	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1113
1114	/*
1115	* Destroy the RTE critical section.
1116	*/
1117	if (PDMCritSectIsInitialized(&pThis->CritSect))
1118	PDMR3CritSectDelete(&pThis->CritSect);
1119
1120	return VINF_SUCCESS;
1121	}
1122
1123
1124	/**
1125	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1126	*/
1127	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1128	{
1129	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1130	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1131	Assert(iInstance == 0);
1132
1133	/*
1134	* Initialize the state data.
1135	*/
1136	pThis->pDevInsR3 = pDevIns;
1137	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1138	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1139
1140	/*
1141	* Validate and read the configuration.
1142	*/
1143	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|RZEnabled", "");
1144
1145	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1146	upsets some guest which we haven't yet tested. */
1147	uint32_t cCpus;
1148	int rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1149	if (RT_FAILURE(rc))
1150	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1151	pThis->cCpus = (uint8_t)cCpus;
1152
1153	bool fRZEnabled;
1154	rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
1155	if (RT_FAILURE(rc))
1156	return PDMDEV_SET_ERROR(pDevIns, rc,
1157	N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
1158
1159	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool\n", cCpus, fRZEnabled));
1160
1161	/*
1162	* We will use our own critical section for the IOAPIC device.
1163	*/
1164	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1165	AssertRCReturn(rc, rc);
1166
1167	/*
1168	* Setup the critical section to protect concurrent writes to the RTEs.
1169	*/
1170	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1171	if (RT_FAILURE(rc))
1172	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("IOAPIC: Failed to create critical section. rc=%Rrc"), rc);
1173
1174	/*
1175	* Register the IOAPIC.
1176	*/
1177	PDMIOAPICREG IoApicReg;
1178	RT_ZERO(IoApicReg);
1179	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1180	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
1181	IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
1182	IoApicReg.pfnSetEoiR3 = ioapicSetEoi;
1183	if (fRZEnabled)
1184	{
1185	IoApicReg.pszSetIrqRC = "ioapicSetIrq";
1186	IoApicReg.pszSetIrqR0 = "ioapicSetIrq";
1187
1188	IoApicReg.pszSendMsiRC = "ioapicSendMsi";
1189	IoApicReg.pszSendMsiR0 = "ioapicSendMsi";
1190
1191	IoApicReg.pszSetEoiRC = "ioapicSetEoi";
1192	IoApicReg.pszSetEoiR0 = "ioapicSetEoi";
1193	}
1194	rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
1195	if (RT_FAILURE(rc))
1196	{
1197	AssertMsgFailed(("IOAPIC: PDMDevHlpIOAPICRegister failed! rc=%Rrc\n", rc));
1198	return rc;
1199	}
1200
1201	/*
1202	* Register MMIO callbacks.
1203	*/
1204	rc = PDMDevHlpMMIORegister(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, pThis,
1205	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead,
1206	"I/O APIC");
1207	if (RT_SUCCESS(rc))
1208	{
1209	if (fRZEnabled)
1210	{
1211	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1212	rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
1213	"ioapicMmioWrite", "ioapicMmioRead");
1214	AssertRCReturn(rc, rc);
1215
1216	pThis->pIoApicHlpR0 = pThis->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1217	rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
1218	"ioapicMmioWrite", "ioapicMmioRead");
1219	AssertRCReturn(rc, rc);
1220	}
1221	}
1222	else
1223	{
1224	LogRel(("IOAPIC: PDMDevHlpMMIORegister failed! rc=%Rrc\n", rc));
1225	return rc;
1226	}
1227
1228	/*
1229	* Register saved-state callbacks.
1230	*/
1231	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1232	if (RT_FAILURE(rc))
1233	{
1234	LogRel(("IOAPIC: PDMDevHlpSSMRegister failed! rc=%Rrc\n", rc));
1235	return rc;
1236	}
1237
1238	/*
1239	* Register debugger info callback.
1240	*/
1241	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1242	AssertRCReturn(rc, rc);
1243
1244	/*
1245	* Register debugger register access.
1246	*/
1247	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); AssertRC(rc);
1248	AssertRCReturn(rc, rc);
1249
1250	#ifdef VBOX_WITH_STATISTICS
1251	/*
1252	* Statistics.
1253	*/
1254	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1255	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1256	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1257	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1258
1259	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1260	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1261	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1262	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1263
1264	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1265	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1266	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1267
1268	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1269	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/Contention/SetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1270
1271	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1272	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1273	#endif
1274
1275	/*
1276	* Init. the device state.
1277	*/
1278	LogRel(("IOAPIC: Using implementation 2.0!\n"));
1279	ioapicR3Reset(pDevIns);
1280
1281	return VINF_SUCCESS;
1282	}
1283
1284
1285	/**
1286	* IO APIC device registration structure.
1287	*/
1288	const PDMDEVREG g_DeviceIOAPIC =
1289	{
1290	/* u32Version */
1291	PDM_DEVREG_VERSION,
1292	/* szName */
1293	"ioapic",
1294	/* szRCMod */
1295	"VBoxDDRC.rc",
1296	/* szR0Mod */
1297	"VBoxDDR0.r0",
1298	/* pszDescription */
1299	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1300	/* fFlags */
1301	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36
1302	\| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1303	/* fClass */
1304	PDM_DEVREG_CLASS_PIC,
1305	/* cMaxInstances */
1306	1,
1307	/* cbInstance */
1308	sizeof(IOAPIC),
1309	/* pfnConstruct */
1310	ioapicR3Construct,
1311	/* pfnDestruct */
1312	ioapicR3Destruct,
1313	/* pfnRelocate */
1314	ioapicR3Relocate,
1315	/* pfnMemSetup */
1316	NULL,
1317	/* pfnPowerOn */
1318	NULL,
1319	/* pfnReset */
1320	ioapicR3Reset,
1321	/* pfnSuspend */
1322	NULL,
1323	/* pfnResume */
1324	NULL,
1325	/* pfnAttach */
1326	NULL,
1327	/* pfnDetach */
1328	NULL,
1329	/* pfnQueryInterface. */
1330	NULL,
1331	/* pfnInitComplete */
1332	NULL,
1333	/* pfnPowerOff */
1334	NULL,
1335	/* pfnSoftReset */
1336	NULL,
1337	/* u32VersionEnd */
1338	PDM_DEVREG_VERSION
1339	};
1340
1341	#endif /* IN_RING3 */
1342
1343	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1344

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source: vbox/trunk/src/VBox/Devices/PC/DevIOAPIC_New.cpp@ 61847

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