DevIoApic.cpp@ 90264

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1	/* $Id: DevIoApic.cpp 89738 2021-06-16 10:20:53Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - Number of bits to shift to get the Mask. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - The Mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** @name DMAR variant interpretation of RTE fields.
126	* @{ */
127	/** Redirection table entry - Number of bits to shift to get Interrupt
128	* Index[14:0]. */
129	#define IOAPIC_RTE_INTR_INDEX_LO_BIT 49
130	/** Redirection table entry - Interrupt Index[14:0]. */
131	#define IOAPIC_RTE_INTR_INDEX_LO UINT64_C(0xfffe000000000000)
132	/** Redirection table entry - Number of bits to shift to get interrupt format. */
133	#define IOAPIC_RTE_INTR_FORMAT_BIT 48
134	/** Redirection table entry - Interrupt format. */
135	#define IOAPIC_RTE_INTR_FORMAT RT_BIT_64(IOAPIC_RTE_INTR_FORMAT_BIT)
136	/** Redirection table entry - Number of bits to shift to get Interrupt Index[15]. */
137	#define IOAPIC_RTE_INTR_INDEX_HI_BIT 11
138	/** Redirection table entry - Interrupt Index[15]. */
139	#define IOAPIC_RTE_INTR_INDEX_HI RT_BIT_64(11)
140
141	/** Redirection table entry - Gets the Interrupt Index[14:0]. */
142	#define IOAPIC_RTE_GET_INTR_INDEX_LO(a_Reg) ((a_Reg) >> IOAPIC_RTE_INTR_INDEX_LO_BIT)
143	/** Redirection table entry - Gets the Interrupt format. */
144	#define IOAPIC_RTE_GET_INTR_FORMAT(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_FORMAT_BIT) & 0x1)
145	/** Redirection table entry - Gets the Interrupt Index[15]. */
146	#define IOAPIC_RTE_GET_INTR_INDEX_HI(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_INDEX_HI_BIT) & 0x1)
147	/** @} */
148
149	/** Redirection table entry - Valid write mask for 82093AA. */
150	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
151	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
152	\| IOAPIC_RTE_VECTOR)
153	/** Redirection table entry - Valid read mask for 82093AA. */
154	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
155	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
156	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
157
158	/** Redirection table entry - Valid write mask for ICH9. */
159	/** @note The remote IRR bit has been reverted to read-only as it turns out the
160	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
161	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
162	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
163	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
164	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
165	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
166	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
167	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
168	\| IOAPIC_RTE_VECTOR)
169
170	/** Redirection table entry - Valid write mask for DMAR variant. */
171	#define IOAPIC_RTE_VALID_WRITE_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
172	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_INTR_INDEX_HI \
173	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
174	/** Redirection table entry - Valid read mask for DMAR variant. */
175	#define IOAPIC_RTE_VALID_READ_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO \| IOAPIC_RTE_INTR_FORMAT \| IOAPIC_RTE_MASK \
176	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
177	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_INTR_INDEX_HI \| IOAPIC_RTE_DELIVERY_MODE \
178	\| IOAPIC_RTE_VECTOR)
179
180	/** Redirection table entry - Trigger mode edge. */
181	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
182	/** Redirection table entry - Trigger mode level. */
183	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
184	/** Redirection table entry - Destination mode physical. */
185	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
186	/** Redirection table entry - Destination mode logical. */
187	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
188
189
190	/** Index of indirect registers in the I/O APIC register table. */
191	#define IOAPIC_INDIRECT_INDEX_ID 0x0
192	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
193	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
194	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
195	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
196	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
197
198	/** Offset of direct registers in the I/O APIC MMIO space. */
199	#define IOAPIC_DIRECT_OFF_INDEX 0x00
200	#define IOAPIC_DIRECT_OFF_DATA 0x10
201	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
202
203	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
204	#define IOAPIC_WITH_PDM_CRITSECT
205	#ifdef IOAPIC_WITH_PDM_CRITSECT
206	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
207	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
208	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnLockIsOwner((a_pDevIns))
209	#else
210	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
211	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
212	# define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectIsOwner((a_pDevIns), &(a_pThis)->CritSect)
213	#endif
214
215
216	/*********************************************************************************************************************************
217	* Structures and Typedefs *
218	*********************************************************************************************************************************/
219	/**
220	* I/O APIC chipset (and variants) we support.
221	*/
222	typedef enum IOAPICTYPE
223	{
224	IOAPICTYPE_ICH9 = 1,
225	IOAPICTYPE_DMAR,
226	IOAPICTYPE_82093AA,
227	IOAPICTYPE_82379AB,
228	IOAPICTYPE_32BIT_HACK = 0x7fffffff
229	} IOAPICTYPE;
230	AssertCompileSize(IOAPICTYPE, 4);
231
232	/**
233	* The shared I/O APIC device state.
234	*/
235	typedef struct IOAPIC
236	{
237	/** The ID register. */
238	uint8_t volatile u8Id;
239	/** The index register. */
240	uint8_t volatile u8Index;
241	/** Number of CPUs. */
242	uint8_t cCpus;
243	/** I/O APIC version. */
244	uint8_t u8ApicVer;
245	/** I/O APIC ID mask. */
246	uint8_t u8IdMask;
247	/** Maximum Redirection Table Entry (RTE) Entry. */
248	uint8_t u8MaxRte;
249	/** Last valid RTE indirect register index. */
250	uint8_t u8LastRteRegIdx;
251	/* Alignment padding. */
252	uint8_t u8Padding0[1];
253	/** Redirection table entry - Valid write mask. */
254	uint64_t u64RteWriteMask;
255	/** Redirection table entry - Valid read mask. */
256	uint64_t u64RteReadMask;
257
258	/** The redirection table registers. */
259	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
260	/** The IRQ tags and source IDs for each pin (tracing purposes). */
261	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
262
263	/** The internal IRR reflecting state of the interrupt lines. */
264	uint32_t uIrr;
265	/** The I/O APIC chipset type. */
266	IOAPICTYPE enmType;
267	/** The I/O APIC PCI address. */
268	PCIBDF uPciAddress;
269	/** Padding. */
270	uint32_t uPadding0;
271
272	#ifndef IOAPIC_WITH_PDM_CRITSECT
273	/** The critsect for updating to the RTEs. */
274	PDMCRITSECT CritSect;
275	#endif
276
277	/** The MMIO region. */
278	IOMMMIOHANDLE hMmio;
279
280	#ifdef VBOX_WITH_STATISTICS
281	/** Number of MMIO reads in RZ. */
282	STAMCOUNTER StatMmioReadRZ;
283	/** Number of MMIO reads in R3. */
284	STAMCOUNTER StatMmioReadR3;
285
286	/** Number of MMIO writes in RZ. */
287	STAMCOUNTER StatMmioWriteRZ;
288	/** Number of MMIO writes in R3. */
289	STAMCOUNTER StatMmioWriteR3;
290
291	/** Number of SetIrq calls in RZ. */
292	STAMCOUNTER StatSetIrqRZ;
293	/** Number of SetIrq calls in R3. */
294	STAMCOUNTER StatSetIrqR3;
295
296	/** Number of SetEoi calls in RZ. */
297	STAMCOUNTER StatSetEoiRZ;
298	/** Number of SetEoi calls in R3. */
299	STAMCOUNTER StatSetEoiR3;
300
301	/** Number of redundant edge-triggered interrupts. */
302	STAMCOUNTER StatRedundantEdgeIntr;
303	/** Number of redundant level-triggered interrupts. */
304	STAMCOUNTER StatRedundantLevelIntr;
305	/** Number of suppressed level-triggered interrupts (by remote IRR). */
306	STAMCOUNTER StatSuppressedLevelIntr;
307	/** Number of IOMMU remapped interrupts (signaled by RTE). */
308	STAMCOUNTER StatIommuRemappedIntr;
309	/** Number of IOMMU discarded interrupts (signaled by RTE). */
310	STAMCOUNTER StatIommuDiscardedIntr;
311	/** Number of IOMMU remapped MSIs. */
312	STAMCOUNTER StatIommuRemappedMsi;
313	/** Number of IOMMU denied or failed MSIs. */
314	STAMCOUNTER StatIommuDiscardedMsi;
315	/** Number of returns to ring-3 due to Set RTE lock contention. */
316	STAMCOUNTER StatSetRteContention;
317	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
318	STAMCOUNTER StatLevelIrqSent;
319	/** Number of EOIs received for level-triggered interrupts from the local
320	* APIC(s). */
321	STAMCOUNTER StatEoiReceived;
322	/** The time an interrupt level spent in the pending state. */
323	STAMPROFILEADV aStatLevelAct[IOAPIC_NUM_INTR_PINS];
324	#endif
325	/** Per-vector stats. */
326	STAMCOUNTER aStatVectors[256];
327	} IOAPIC;
328	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
329	/** Pointer to shared IOAPIC data. */
330	typedef IOAPIC *PIOAPIC;
331	/** Pointer to const shared IOAPIC data. */
332	typedef IOAPIC const *PCIOAPIC;
333
334
335	/**
336	* The I/O APIC device state for ring-3.
337	*/
338	typedef struct IOAPICR3
339	{
340	/** The IOAPIC helpers. */
341	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
342	} IOAPICR3;
343	/** Pointer to the I/O APIC device state for ring-3. */
344	typedef IOAPICR3 *PIOAPICR3;
345
346
347	/**
348	* The I/O APIC device state for ring-0.
349	*/
350	typedef struct IOAPICR0
351	{
352	/** The IOAPIC helpers. */
353	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
354	} IOAPICR0;
355	/** Pointer to the I/O APIC device state for ring-0. */
356	typedef IOAPICR0 *PIOAPICR0;
357
358
359	/**
360	* The I/O APIC device state for raw-mode.
361	*/
362	typedef struct IOAPICRC
363	{
364	/** The IOAPIC helpers. */
365	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
366	} IOAPICRC;
367	/** Pointer to the I/O APIC device state for raw-mode. */
368	typedef IOAPICRC *PIOAPICRC;
369
370
371	/** The I/O APIC device state for the current context. */
372	typedef CTX_SUFF(IOAPIC) IOAPICCC;
373	/** Pointer to the I/O APIC device state for the current context. */
374	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
375
376
377	/**
378	* xAPIC interrupt.
379	*/
380	typedef struct XAPICINTR
381	{
382	/** The interrupt vector. */
383	uint8_t u8Vector;
384	/** The destination (mask or ID). */
385	uint8_t u8Dest;
386	/** The destination mode. */
387	uint8_t u8DestMode;
388	/** Delivery mode. */
389	uint8_t u8DeliveryMode;
390	/** Trigger mode. */
391	uint8_t u8TriggerMode;
392	/** Redirection hint. */
393	uint8_t u8RedirHint;
394	/** Polarity. */
395	uint8_t u8Polarity;
396	/** Padding. */
397	uint8_t abPadding0;
398	} XAPICINTR;
399	/** Pointer to an I/O xAPIC interrupt struct. */
400	typedef XAPICINTR *PXAPICINTR;
401	/** Pointer to a const xAPIC interrupt struct. */
402	typedef XAPICINTR const *PCXAPICINTR;
403
404
405	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
406
407	/**
408	* Gets the arbitration register.
409	*
410	* @returns The arbitration.
411	*/
412	DECLINLINE(uint32_t) ioapicGetArb(void)
413	{
414	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
415	return 0;
416	}
417
418
419	/**
420	* Gets the version register.
421	*
422	* @returns The version.
423	*/
424	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
425	{
426	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
427	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
428	return uValue;
429	}
430
431
432	/**
433	* Sets the ID register.
434	*
435	* @param pThis The shared I/O APIC device state.
436	* @param uValue The value to set.
437	*/
438	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
439	{
440	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
441	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
442	}
443
444
445	/**
446	* Gets the ID register.
447	*
448	* @returns The ID.
449	* @param pThis The shared I/O APIC device state.
450	*/
451	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
452	{
453	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
454	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
455	return uValue;
456	}
457
458
459	/**
460	* Sets the index register.
461	*
462	* @param pThis The shared I/O APIC device state.
463	* @param uValue The value to set.
464	*/
465	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
466	{
467	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
468	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
469	}
470
471
472	/**
473	* Gets the index register.
474	*
475	* @returns The index value.
476	*/
477	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
478	{
479	uint32_t const uValue = pThis->u8Index;
480	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
481	return uValue;
482	}
483
484
485	/**
486	* Converts an MSI message to an APIC interrupt.
487	*
488	* @param pMsi The MSI message to convert.
489	* @param pIntr Where to store the APIC interrupt.
490	*/
491	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
492	{
493	/*
494	* Parse the message from the physical address and data.
495	* Do -not- zero out other fields in the APIC interrupt.
496	*
497	* See Intel spec. 10.11.1 "Message Address Register Format".
498	* See Intel spec. 10.11.2 "Message Data Register Format".
499	*/
500	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
501	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
502	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
503
504	pIntr->u8Vector = pMsi->Data.n.u8Vector;
505	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
506	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
507	}
508
509
510	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
511	/**
512	* Convert an RTE into an MSI message.
513	*
514	* @param u64Rte The RTE to convert.
515	* @param enmType The I/O APIC chipset type.
516	* @param pMsi Where to store the MSI message.
517	*/
518	DECLINLINE(void) ioapicGetMsiFromRte(uint64_t u64Rte, IOAPICTYPE enmType, PMSIMSG pMsi)
519	{
520	bool const fRemappable = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
521	if (!fRemappable)
522	{
523	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
524	pMsi->Addr.n.u8DestId = IOAPIC_RTE_GET_DEST(u64Rte);
525	pMsi->Addr.n.u1RedirHint = 0;
526	pMsi->Addr.n.u1DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
527
528	pMsi->Data.n.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
529	pMsi->Data.n.u3DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
530	pMsi->Data.n.u1TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
531	/* pMsi->Data.n.u1Level = ??? */
532	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
533	* possible in theory? Maybe document this more explicitly... */
534	}
535	else
536	{
537	Assert(enmType == IOAPICTYPE_DMAR);
538	NOREF(enmType);
539
540	/*
541	* The spec. mentions that SHV will be 0 when delivery mode is 0 (fixed), but
542	* not what SHV will be if delivery mode is not 0. I ASSUME copying delivery
543	* mode into SHV here is what hardware actually does.
544	*
545	* See Intel VT-d spec. 5.1.5.1 "I/OxAPIC Programming".
546	*/
547	pMsi->Addr.dmar_remap.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
548	pMsi->Addr.dmar_remap.u14IntrIndexLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
549	pMsi->Addr.dmar_remap.fIntrFormat = 1;
550	pMsi->Addr.dmar_remap.fShv = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
551	pMsi->Addr.dmar_remap.u1IntrIndexHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
552
553	pMsi->Data.dmar_remap.u16SubHandle = 0;
554	}
555	}
556	#endif
557
558
559	/**
560	* Signals the next pending interrupt for the specified Redirection Table Entry
561	* (RTE).
562	*
563	* @param pDevIns The device instance.
564	* @param pThis The shared I/O APIC device state.
565	* @param pThisCC The I/O APIC device state for the current context.
566	* @param idxRte The index of the RTE (validated).
567	*
568	* @remarks It is the responsibility of the caller to verify that an interrupt is
569	* pending for the pin corresponding to the RTE before calling this
570	* function.
571	*/
572	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
573	{
574	Assert(IOAPIC_LOCK_IS_OWNER(pDevIns, pThis, pThisCC));
575
576	/*
577	* Ensure the interrupt isn't masked.
578	*/
579	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
580	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
581	{ /* likely */ }
582	else
583	return;
584
585	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
586	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
587	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
588	{
589	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
590	if (u8RemoteIrr)
591	{
592	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
593	return;
594	}
595	}
596
597	XAPICINTR ApicIntr;
598	RT_ZERO(ApicIntr);
599	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
600	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
601	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
602	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
603	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
604	ApicIntr.u8TriggerMode = u8TriggerMode;
605	//ApicIntr.u8RedirHint = 0;
606
607	/** @todo We might be able to release the IOAPIC(PDM) lock here and re-acquire it
608	* before setting the remote IRR bit below. The APIC and IOMMU should not
609	* require the caller to hold the PDM lock. */
610
611	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
612	/*
613	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
614	* For line-based interrupts we must use the southbridge I/O APIC's BDF as
615	* the origin of the interrupt, see @bugref{9654#c74}.
616	*/
617	MSIMSG MsiIn;
618	RT_ZERO(MsiIn);
619	ioapicGetMsiFromRte(u64Rte, pThis->enmType, &MsiIn);
620
621	MSIMSG MsiOut;
622	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, pThis->uPciAddress, &MsiIn, &MsiOut);
623	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
624	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
625	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
626	else if (RT_SUCCESS(rcRemap))
627	{
628	/* Update the APIC interrupt with the remapped data. */
629	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
630
631	/* Ensure polarity hasn't changed (trigger mode might change with Intel IOMMUs). */
632	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte));
633	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
634	}
635	else
636	{
637	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
638	return;
639	}
640	#endif
641
642	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
643	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
644	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
645	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
646	ApicIntr.u8Vector, ApicIntr.u8Vector));
647
648	/*
649	* Deliver to the local APIC via the system/3-wire-APIC bus.
650	*/
651	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
652	ApicIntr.u8Dest,
653	ApicIntr.u8DestMode,
654	ApicIntr.u8DeliveryMode,
655	ApicIntr.u8Vector,
656	ApicIntr.u8Polarity,
657	ApicIntr.u8TriggerMode,
658	u32TagSrc);
659	/* Can't reschedule to R3. */
660	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
661	#ifdef DEBUG_ramshankar
662	if (rc == VERR_APIC_INTR_DISCARDED)
663	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
664	#endif
665
666	/*
667	* For level-triggered interrupts, we set the remote IRR bit to indicate
668	* the local APIC has accepted the interrupt.
669	*
670	* For edge-triggered interrupts, we should not clear the IRR bit as it
671	* should remain intact to reflect the state of the interrupt line.
672	* The device will explicitly transition to inactive state via the
673	* ioapicSetIrq() callback.
674	*/
675	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
676	&& rc == VINF_SUCCESS)
677	{
678	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
679	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
680	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
681	STAM_PROFILE_ADV_START(&pThis->aStatLevelAct[idxRte], a);
682	}
683	}
684
685
686	/**
687	* Gets the redirection table entry.
688	*
689	* @returns The redirection table entry.
690	* @param pThis The shared I/O APIC device state.
691	* @param uIndex The index value.
692	*/
693	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
694	{
695	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
696	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
697	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
698	UINT32_MAX);
699	uint32_t uValue;
700	if (!(uIndex & 1))
701	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
702	else
703	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
704
705	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
706	return uValue;
707	}
708
709
710	/**
711	* Sets the redirection table entry.
712	*
713	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
714	* @param pDevIns The device instance.
715	* @param pThis The shared I/O APIC device state.
716	* @param pThisCC The I/O APIC device state for the current context.
717	* @param uIndex The index value.
718	* @param uValue The value to set.
719	*/
720	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
721	uint32_t uIndex, uint32_t uValue)
722	{
723	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
724	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
725	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
726	VINF_SUCCESS);
727
728	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
729	if (rc == VINF_SUCCESS)
730	{
731	/*
732	* Write the low or high 32-bit value into the specified 64-bit RTE register,
733	* update only the valid, writable bits.
734	*
735	* We need to preserve the read-only bits as it can have dire consequences
736	* otherwise, see @bugref{8386#c24}.
737	*/
738	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
739	if (!(uIndex & 1))
740	{
741	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
742	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
743	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
744	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
745	}
746	else
747	{
748	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
749	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
750	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
751	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
752	}
753
754	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
755
756	/*
757	* Signal the next pending interrupt for this RTE.
758	*/
759	uint32_t const uPinMask = UINT32_C(1) << idxRte;
760	if (pThis->uIrr & uPinMask)
761	{
762	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
763	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
764	}
765
766	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
767	}
768	else
769	STAM_COUNTER_INC(&pThis->StatSetRteContention);
770
771	return rc;
772	}
773
774
775	/**
776	* Gets the data register.
777	*
778	* @returns The data value.
779	* @param pThis The shared I/O APIC device state.
780	*/
781	static uint32_t ioapicGetData(PCIOAPIC pThis)
782	{
783	uint8_t const uIndex = pThis->u8Index;
784	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
785	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
786	&& uIndex <= pThis->u8LastRteRegIdx)
787	return ioapicGetRedirTableEntry(pThis, uIndex);
788
789	uint32_t uValue;
790	switch (uIndex)
791	{
792	case IOAPIC_INDIRECT_INDEX_ID:
793	uValue = ioapicGetId(pThis);
794	break;
795
796	case IOAPIC_INDIRECT_INDEX_VERSION:
797	uValue = ioapicGetVersion(pThis);
798	break;
799
800	case IOAPIC_INDIRECT_INDEX_ARB:
801	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
802	{
803	uValue = ioapicGetArb();
804	break;
805	}
806	RT_FALL_THRU();
807
808	default:
809	uValue = UINT32_C(0xffffffff);
810	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
811	break;
812	}
813	return uValue;
814	}
815
816
817	/**
818	* Sets the data register.
819	*
820	* @returns Strict VBox status code.
821	* @param pDevIns The device instance.
822	* @param pThis The shared I/O APIC device state.
823	* @param pThisCC The I/O APIC device state for the current context.
824	* @param uValue The value to set.
825	*/
826	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
827	{
828	uint8_t const uIndex = pThis->u8Index;
829	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
830	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
831
832	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
833	&& uIndex <= pThis->u8LastRteRegIdx)
834	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
835
836	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
837	ioapicSetId(pThis, uValue);
838	else
839	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
840
841	return VINF_SUCCESS;
842	}
843
844
845	/**
846	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
847	*/
848	static DECLCALLBACK(void) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
849	{
850	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
851	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
852
853	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
854	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
855
856	bool fRemoteIrrCleared = false;
857	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
858	AssertRC(rc);
859
860	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
861	{
862	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
863	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
864	{
865	#ifdef DEBUG_ramshankar
866	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
867	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
868	#endif
869	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
870	fRemoteIrrCleared = true;
871	STAM_PROFILE_ADV_STOP(&pThis->aStatLevelAct[idxRte], a);
872	STAM_COUNTER_INC(&pThis->StatEoiReceived);
873	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
874
875	/*
876	* Signal the next pending interrupt for this RTE.
877	*/
878	uint32_t const uPinMask = UINT32_C(1) << idxRte;
879	if (pThis->uIrr & uPinMask)
880	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
881	}
882	}
883
884	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
885
886	#ifndef VBOX_WITH_IOMMU_AMD
887	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
888	#endif
889	}
890
891
892	/**
893	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
894	*/
895	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
896	{
897	RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
898	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
899	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
900	pThis->uIrr \|= a_PinMask; \
901	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
902	} while (0)
903
904	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
905	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
906	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
907
908	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
909
910	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
911	{
912	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
913	AssertRC(rc);
914
915	uint8_t const idxRte = iIrq;
916	uint32_t const uPinMask = UINT32_C(1) << idxRte;
917	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
918	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
919
920	bool fActive = RT_BOOL(iLevel & 1);
921	/** @todo Polarity is busted elsewhere, we need to fix that
922	* first. See @bugref{8386#c7}. */
923	#if 0
924	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
925	fActive ^= u8Polarity; */
926	#endif
927	if (!fActive)
928	{
929	pThis->uIrr &= ~uPinMask;
930	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
931	return;
932	}
933
934	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
935	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
936	if (!fFlipFlop)
937	{
938	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
939	{
940	/*
941	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
942	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
943	*/
944	if (!uPrevIrr)
945	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
946	else
947	{
948	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
949	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
950	}
951	}
952	else
953	{
954	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
955
956	/*
957	* For level-triggered interrupts, redundant interrupts are not a problem
958	* and will eventually be delivered anyway after an EOI, but our PDM devices
959	* should not typically call us with no change to the level.
960	*/
961	if (!uPrevIrr)
962	{ /* likely */ }
963	else
964	{
965	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
966	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
967	}
968
969	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
970	}
971	}
972	else
973	{
974	/*
975	* The device is flip-flopping the interrupt line, which implies we should de-assert
976	* and assert the interrupt line. The interrupt line is left in the asserted state
977	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
978	* hence just the assert is done.
979	*/
980	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
981	}
982
983	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
984	}
985	#undef IOAPIC_ASSERT_IRQ
986	}
987
988
989	/**
990	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
991	*/
992	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
993	{
994	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
995	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
996	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
997
998	XAPICINTR ApicIntr;
999	RT_ZERO(ApicIntr);
1000
1001	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
1002	/*
1003	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
1004	*
1005	* If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
1006	* MSI is the IOMMU itself and hence isn't subjected to remapping. This
1007	* is the case with Intel IOMMUs.
1008	*
1009	* AMD IOMMUs are full fledged PCI devices, hence the BDF will be a
1010	* valid PCI slot, but interrupts generated by the IOMMU will be handled
1011	* by VERR_IOMMU_CANNOT_CALL_SELF case.
1012	*/
1013	if (PCIBDF_IS_VALID(uBusDevFn))
1014	{
1015	MSIMSG MsiOut;
1016	int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
1017	if ( rcRemap == VERR_IOMMU_NOT_PRESENT
1018	\|\| rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
1019	{ /* likely - assuming majority of VMs don't have IOMMU configured. */ }
1020	else if (RT_SUCCESS(rcRemap))
1021	{
1022	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
1023	pMsi = &MsiOut;
1024	}
1025	else
1026	{
1027	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
1028	return;
1029	}
1030	}
1031	#else
1032	NOREF(uBusDevFn);
1033	#endif
1034
1035	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
1036
1037	/*
1038	* Deliver to the local APIC via the system/3-wire-APIC bus.
1039	*/
1040	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
1041
1042	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
1043	ApicIntr.u8Dest,
1044	ApicIntr.u8DestMode,
1045	ApicIntr.u8DeliveryMode,
1046	ApicIntr.u8Vector,
1047	0 /* u8Polarity - N/A */,
1048	ApicIntr.u8TriggerMode,
1049	uTagSrc);
1050	/* Can't reschedule to R3. */
1051	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
1052	}
1053
1054
1055	/**
1056	* @callback_method_impl{FNIOMMMIONEWREAD}
1057	*/
1058	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1059	{
1060	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1061	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1062	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1063	RT_NOREF_PV(pvUser);
1064
1065	VBOXSTRICTRC rc = VINF_SUCCESS;
1066	uint32_t puValue = (uint32_t )pv;
1067	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
1068	switch (offReg)
1069	{
1070	case IOAPIC_DIRECT_OFF_INDEX:
1071	*puValue = ioapicGetIndex(pThis);
1072	break;
1073
1074	case IOAPIC_DIRECT_OFF_DATA:
1075	*puValue = ioapicGetData(pThis);
1076	break;
1077
1078	default:
1079	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1080	rc = VINF_IOM_MMIO_UNUSED_FF;
1081	break;
1082	}
1083
1084	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
1085	return rc;
1086	}
1087
1088
1089	/**
1090	* @callback_method_impl{FNIOMMMIONEWWRITE}
1091	*/
1092	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1093	{
1094	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1095	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1096	RT_NOREF_PV(pvUser);
1097
1098	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1099
1100	Assert(!(off & 3));
1101	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1102
1103	VBOXSTRICTRC rc = VINF_SUCCESS;
1104	uint32_t const uValue = (uint32_t const )pv;
1105	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1106
1107	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1108	switch (offReg)
1109	{
1110	case IOAPIC_DIRECT_OFF_INDEX:
1111	ioapicSetIndex(pThis, uValue);
1112	break;
1113
1114	case IOAPIC_DIRECT_OFF_DATA:
1115	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1116	break;
1117
1118	case IOAPIC_DIRECT_OFF_EOI:
1119	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1120	ioapicSetEoi(pDevIns, uValue);
1121	else
1122	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1123	break;
1124
1125	default:
1126	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1127	break;
1128	}
1129
1130	return rc;
1131	}
1132
1133
1134	#ifdef IN_RING3
1135
1136	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1137	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1138	{
1139	RT_NOREF(pDesc);
1140	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1141	return VINF_SUCCESS;
1142	}
1143
1144
1145	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1146	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1147	{
1148	RT_NOREF(pDesc, pfMask);
1149	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1150	return VINF_SUCCESS;
1151	}
1152
1153
1154	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1155	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1156	{
1157	RT_NOREF(pDesc);
1158	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1159	return VINF_SUCCESS;
1160	}
1161
1162
1163	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1164	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1165	{
1166	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1167	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1168	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1169	RT_NOREF(pDesc, pfMask);
1170	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1171	}
1172
1173
1174	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1175	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1176	{
1177	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1178	RT_NOREF(pDesc);
1179	pValue->u32 = ioapicGetVersion(pThis);
1180	return VINF_SUCCESS;
1181	}
1182
1183
1184	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1185	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1186	{
1187	RT_NOREF(pvUser, pDesc);
1188	pValue->u32 = ioapicGetArb();
1189	return VINF_SUCCESS;
1190	}
1191
1192
1193	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1194	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1195	{
1196	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1197	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1198	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1199	return VINF_SUCCESS;
1200	}
1201
1202
1203	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1204	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1205	{
1206	RT_NOREF(pfMask);
1207	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1208	/* No locks, no checks, just do it. */
1209	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1210	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1211	return VINF_SUCCESS;
1212	}
1213
1214
1215	/** IOREDTBLn sub fields. */
1216	static DBGFREGSUBFIELD const g_aRteSubs[] =
1217	{
1218	{ "vector", 0, 8, 0, 0, NULL, NULL },
1219	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1220	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1221	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1222	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1223	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1224	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1225	{ "mask", 16, 1, 0, 0, NULL, NULL },
1226	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1227	{ "dest", 56, 8, 0, 0, NULL, NULL },
1228	DBGFREGSUBFIELD_TERMINATOR()
1229	};
1230
1231
1232	/** Register descriptors for DBGF. */
1233	static DBGFREGDESC const g_aRegDesc[] =
1234	{
1235	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1236	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1237	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1238	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1239	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1240	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1241	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1242	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1243	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1244	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1245	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1246	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1247	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1248	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1249	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1250	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1251	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1252	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1253	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1254	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1255	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1256	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1257	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1258	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1259	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1260	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1261	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1262	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1263	DBGFREGDESC_TERMINATOR()
1264	};
1265
1266
1267	/**
1268	* @callback_method_impl{FNDBGFHANDLERDEV}
1269	*/
1270	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1271	{
1272	RT_NOREF(pszArgs);
1273	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1274	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1275
1276	bool const fLegacy = RTStrCmp(pszArgs, "legacy") == 0;
1277
1278	static const char * const s_apszDeliveryModes[] =
1279	{
1280	" fixed",
1281	"lowpri",
1282	" smi",
1283	" rsvd",
1284	" nmi",
1285	" init",
1286	" rsvd",
1287	"extint"
1288	};
1289	static const char * const s_apszDestMode[] = { "phys", "log " };
1290	static const char * const s_apszTrigMode[] = { " edge", "level" };
1291	static const char * const s_apszPolarity[] = { "acthi", "actlo" };
1292	static const char * const s_apszDeliveryStatus[] = { "idle", "pend" };
1293
1294	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1295
1296	uint32_t const uId = ioapicGetId(pThis);
1297	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1298	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1299
1300	uint32_t const uVer = ioapicGetVersion(pThis);
1301	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1302	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1303	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1304	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1305
1306	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1307	{
1308	uint32_t const uArb = ioapicGetArb();
1309	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1310	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1311	}
1312
1313	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1314
1315	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1316	if ( pThis->enmType != IOAPICTYPE_DMAR
1317	\|\| fLegacy)
1318	{
1319	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1320	pHlp->pfnPrintf(pHlp, " ---------------------------------------------------------------------------------------------\n");
1321
1322	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1323	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1324	{
1325	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1326	const char *pszDestMode = s_apszDestMode[IOAPIC_RTE_GET_DEST_MODE(u64Rte)];
1327	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1328	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1329	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1330	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1331	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1332	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1333	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1334	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1335	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1336	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1337
1338	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1339	idxRte,
1340	pszDestMode,
1341	uDest,
1342	uMask,
1343	(pThis->uIrr >> idxRte) & 1,
1344	pszTriggerMode,
1345	uRemoteIrr,
1346	pszPolarity,
1347	pszDeliveryStatus,
1348	pszDeliveryMode,
1349	uVector,
1350	u64Rte);
1351	}
1352	}
1353	else
1354	{
1355	pHlp->pfnPrintf(pHlp, " idx intr_idx fmt mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
1356	pHlp->pfnPrintf(pHlp, " ----------------------------------------------------------------------------------------\n");
1357
1358	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1359	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1360	{
1361	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1362	const uint16_t idxIntrLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
1363	const uint8_t fIntrFormat = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
1364	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1365	const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
1366	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1367	const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
1368	const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
1369	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1370	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1371	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1372	const uint16_t idxIntrHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
1373	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1374	const uint16_t idxIntr = idxIntrLo \| (idxIntrHi << 15);
1375	pHlp->pfnPrintf(pHlp, " %02d %4u %u %u %u %s %u %s %s %s %3u (%016llx)\n",
1376	idxRte,
1377	idxIntr,
1378	fIntrFormat,
1379	uMask,
1380	(pThis->uIrr >> idxRte) & 1,
1381	pszTriggerMode,
1382	uRemoteIrr,
1383	pszPolarity,
1384	pszDeliveryStatus,
1385	pszDeliveryMode,
1386	uVector,
1387	u64Rte);
1388	}
1389	}
1390	}
1391
1392
1393	/**
1394	* @copydoc FNSSMDEVSAVEEXEC
1395	*/
1396	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1397	{
1398	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1399	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1400	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1401
1402	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1403	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1404	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1405	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1406	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1407
1408	return VINF_SUCCESS;
1409	}
1410
1411
1412	/**
1413	* @copydoc FNSSMDEVLOADEXEC
1414	*/
1415	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1416	{
1417	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1418	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1419	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1420
1421	Assert(uPass == SSM_PASS_FINAL);
1422	NOREF(uPass);
1423
1424	/* Weed out invalid versions. */
1425	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1426	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1427	{
1428	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1429	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1430	}
1431
1432	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1433	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1434
1435	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1436	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1437	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1438	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1439
1440	return VINF_SUCCESS;
1441	}
1442
1443
1444	/**
1445	* @interface_method_impl{PDMDEVREG,pfnReset}
1446	*/
1447	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1448	{
1449	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1450	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1451	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1452
1453	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1454	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1455
1456	pThis->uIrr = 0;
1457	pThis->u8Index = 0;
1458	pThis->u8Id = 0;
1459
1460	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1461	{
1462	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1463	pThis->au32TagSrc[idxRte] = 0;
1464	}
1465
1466	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1467	}
1468
1469
1470	/**
1471	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1472	*/
1473	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1474	{
1475	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1476	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1477
1478	pThisRC->pIoApicHlp += offDelta;
1479	}
1480
1481
1482	/**
1483	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1484	*/
1485	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1486	{
1487	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1488	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1489	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1490
1491	# ifndef IOAPIC_WITH_PDM_CRITSECT
1492	/*
1493	* Destroy the RTE critical section.
1494	*/
1495	if (PDMCritSectIsInitialized(&pThis->CritSect))
1496	PDMR3CritSectDelete(&pThis->CritSect);
1497	# else
1498	RT_NOREF_PV(pThis);
1499	# endif
1500
1501	return VINF_SUCCESS;
1502	}
1503
1504
1505	/**
1506	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1507	*/
1508	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1509	{
1510	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1511	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1512	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1513	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1514	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1515	Assert(iInstance == 0); RT_NOREF(iInstance);
1516
1517	/*
1518	* Validate and read the configuration.
1519	*/
1520	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType\|PCIAddress", "");
1521
1522	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
1523	upsets some guest which we haven't yet been tested. */
1524	uint32_t cCpus;
1525	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1526	if (RT_FAILURE(rc))
1527	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1528	pThis->cCpus = (uint8_t)cCpus;
1529
1530	char szChipType[16];
1531	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1532	if (RT_FAILURE(rc))
1533	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1534
1535	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
1536	if (RT_FAILURE(rc))
1537	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
1538
1539	if (!strcmp(szChipType, "ICH9"))
1540	{
1541	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1542	pThis->enmType = IOAPICTYPE_ICH9;
1543	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1544	pThis->u8IdMask = 0xff;
1545	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1546	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1547	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1548	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1549	}
1550	else if (!strcmp(szChipType, "DMAR"))
1551	{
1552	/* Intel DMAR compatible I/O APIC integrated into ICH southbridges. */
1553	/* Identical to ICH9, but interprets RTEs and MSI address and data fields differently. */
1554	pThis->enmType = IOAPICTYPE_DMAR;
1555	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1556	pThis->u8IdMask = 0xff;
1557	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1558	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1559	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_DMAR;
1560	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_DMAR;
1561	}
1562	else if (!strcmp(szChipType, "82093AA"))
1563	{
1564	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1565	pThis->enmType = IOAPICTYPE_82093AA;
1566	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1567	pThis->u8IdMask = 0x0f;
1568	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1569	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1570	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1571	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1572	}
1573	else if (!strcmp(szChipType, "82379AB"))
1574	{
1575	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1576	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1577	pThis->enmType = IOAPICTYPE_82379AB;
1578	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1579	pThis->u8IdMask = 0x0f;
1580	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1581	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1582	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1583	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1584	}
1585	else
1586	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1587	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1588	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1589
1590	/*
1591	* We will use our own critical section for the IOAPIC device.
1592	*/
1593	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1594	AssertRCReturn(rc, rc);
1595
1596	# ifndef IOAPIC_WITH_PDM_CRITSECT
1597	/*
1598	* Setup the critical section to protect concurrent writes to the RTEs.
1599	*/
1600	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1601	AssertRCReturn(rc, rc);
1602	# endif
1603
1604	/*
1605	* Register the IOAPIC.
1606	*/
1607	PDMIOAPICREG IoApicReg;
1608	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1609	IoApicReg.pfnSetIrq = ioapicSetIrq;
1610	IoApicReg.pfnSendMsi = ioapicSendMsi;
1611	IoApicReg.pfnSetEoi = ioapicSetEoi;
1612	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1613	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1614	AssertRCReturn(rc, rc);
1615	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1616	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1617	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1618	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1619	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1620
1621	/*
1622	* Register MMIO region.
1623	*/
1624	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1625	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1626	AssertRCReturn(rc, rc);
1627
1628	/*
1629	* Register the saved state.
1630	*/
1631	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1632	AssertRCReturn(rc, rc);
1633
1634	/*
1635	* Register debugger info item.
1636	*/
1637	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1638	AssertRCReturn(rc, rc);
1639
1640	/*
1641	* Register debugger register access.
1642	*/
1643	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1644	AssertRCReturn(rc, rc);
1645
1646	# ifdef VBOX_WITH_STATISTICS
1647	/*
1648	* Statistics.
1649	*/
1650	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1651	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1652	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1653	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1654
1655	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1656	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1657	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1658	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1659
1660	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1661	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1662	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1663
1664	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1665	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1666	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1667	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1668
1669	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1670
1671	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1672	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1673
1674	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatLevelAct); ++i)
1675	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatLevelAct[i], STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Time spent in the level active state", "IntPending/%02x", i);
1676	# endif
1677	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1678	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1679	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1680
1681	/*
1682	* Init. the device state.
1683	*/
1684	LogRel(("IOAPIC: Version=%d.%d ChipType=%s\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0f, szChipType));
1685	ioapicR3Reset(pDevIns);
1686
1687	return VINF_SUCCESS;
1688	}
1689
1690	#else /* !IN_RING3 */
1691
1692	/**
1693	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1694	*/
1695	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1696	{
1697	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1698	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1699	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1700
1701	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1702	AssertRCReturn(rc, rc);
1703
1704	PDMIOAPICREG IoApicReg;
1705	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1706	IoApicReg.pfnSetIrq = ioapicSetIrq;
1707	IoApicReg.pfnSendMsi = ioapicSendMsi;
1708	IoApicReg.pfnSetEoi = ioapicSetEoi;
1709	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1710	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1711	AssertRCReturn(rc, rc);
1712	AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
1713	AssertPtr(pThisCC->pIoApicHlp->pfnLock);
1714	AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
1715	AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
1716	AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
1717
1718	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1719	AssertRCReturn(rc, rc);
1720
1721	return VINF_SUCCESS;
1722	}
1723
1724	#endif /* !IN_RING3 */
1725
1726	/**
1727	* IO APIC device registration structure.
1728	*/
1729	const PDMDEVREG g_DeviceIOAPIC =
1730	{
1731	/* .u32Version = */ PDM_DEVREG_VERSION,
1732	/* .uReserved0 = */ 0,
1733	/* .szName = */ "ioapic",
1734	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1735	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1736	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1737	/* .cMaxInstances = */ 1,
1738	/* .uSharedVersion = */ 42,
1739	/* .cbInstanceShared = */ sizeof(IOAPIC),
1740	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1741	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1742	/* .cMaxPciDevices = */ 0,
1743	/* .cMaxMsixVectors = */ 0,
1744	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1745	#if defined(IN_RING3)
1746	/* .pszRCMod = */ "VBoxDDRC.rc",
1747	/* .pszR0Mod = */ "VBoxDDR0.r0",
1748	/* .pfnConstruct = */ ioapicR3Construct,
1749	/* .pfnDestruct = */ ioapicR3Destruct,
1750	/* .pfnRelocate = */ ioapicR3Relocate,
1751	/* .pfnMemSetup = */ NULL,
1752	/* .pfnPowerOn = */ NULL,
1753	/* .pfnReset = */ ioapicR3Reset,
1754	/* .pfnSuspend = */ NULL,
1755	/* .pfnResume = */ NULL,
1756	/* .pfnAttach = */ NULL,
1757	/* .pfnDetach = */ NULL,
1758	/* .pfnQueryInterface = */ NULL,
1759	/* .pfnInitComplete = */ NULL,
1760	/* .pfnPowerOff = */ NULL,
1761	/* .pfnSoftReset = */ NULL,
1762	/* .pfnReserved0 = */ NULL,
1763	/* .pfnReserved1 = */ NULL,
1764	/* .pfnReserved2 = */ NULL,
1765	/* .pfnReserved3 = */ NULL,
1766	/* .pfnReserved4 = */ NULL,
1767	/* .pfnReserved5 = */ NULL,
1768	/* .pfnReserved6 = */ NULL,
1769	/* .pfnReserved7 = */ NULL,
1770	#elif defined(IN_RING0)
1771	/* .pfnEarlyConstruct = */ NULL,
1772	/* .pfnConstruct = */ ioapicRZConstruct,
1773	/* .pfnDestruct = */ NULL,
1774	/* .pfnFinalDestruct = */ NULL,
1775	/* .pfnRequest = */ NULL,
1776	/* .pfnReserved0 = */ NULL,
1777	/* .pfnReserved1 = */ NULL,
1778	/* .pfnReserved2 = */ NULL,
1779	/* .pfnReserved3 = */ NULL,
1780	/* .pfnReserved4 = */ NULL,
1781	/* .pfnReserved5 = */ NULL,
1782	/* .pfnReserved6 = */ NULL,
1783	/* .pfnReserved7 = */ NULL,
1784	#elif defined(IN_RC)
1785	/* .pfnConstruct = */ ioapicRZConstruct,
1786	/* .pfnReserved0 = */ NULL,
1787	/* .pfnReserved1 = */ NULL,
1788	/* .pfnReserved2 = */ NULL,
1789	/* .pfnReserved3 = */ NULL,
1790	/* .pfnReserved4 = */ NULL,
1791	/* .pfnReserved5 = */ NULL,
1792	/* .pfnReserved6 = */ NULL,
1793	/* .pfnReserved7 = */ NULL,
1794	#else
1795	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1796	#endif
1797	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1798	};
1799
1800
1801	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1802

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 90264

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