DevIoApic.cpp@ 86861

Last change on this file since 86861 was 86810, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 DevIoApic: Add stat for counting interrupts and MSIs discarded due to the IOMMU.
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1	/* $Id: DevIoApic.cpp 86810 2020-11-05 06:55:26Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - the mask bit number. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - the mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** Redirection table entry - Valid write mask for 82093AA. */
126	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
127	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
128	\| IOAPIC_RTE_VECTOR)
129	/** Redirection table entry - Valid read mask for 82093AA. */
130	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
131	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
132	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
133
134	/** Redirection table entry - Valid write mask for ICH9. */
135	/** @note The remote IRR bit has been reverted to read-only as it turns out the
136	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
139	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
140	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
141	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
142	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
143	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
144	\| IOAPIC_RTE_VECTOR)
145
146	/** Redirection table entry - Trigger mode edge. */
147	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
148	/** Redirection table entry - Trigger mode level. */
149	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
150	/** Redirection table entry - Destination mode physical. */
151	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
152	/** Redirection table entry - Destination mode logical. */
153	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
154
155
156	/** Index of indirect registers in the I/O APIC register table. */
157	#define IOAPIC_INDIRECT_INDEX_ID 0x0
158	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
159	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
160	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
161	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
162	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
163
164	/** Offset of direct registers in the I/O APIC MMIO space. */
165	#define IOAPIC_DIRECT_OFF_INDEX 0x00
166	#define IOAPIC_DIRECT_OFF_DATA 0x10
167	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
168
169	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
170	#define IOAPIC_WITH_PDM_CRITSECT
171	#ifdef IOAPIC_WITH_PDM_CRITSECT
172	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
173	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
174	#else
175	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
176	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The shared I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The ID register. */
189	uint8_t volatile u8Id;
190	/** The index register. */
191	uint8_t volatile u8Index;
192	/** Number of CPUs. */
193	uint8_t cCpus;
194	/** I/O APIC version. */
195	uint8_t u8ApicVer;
196	/** I/O APIC ID mask. */
197	uint8_t u8IdMask;
198	/** Maximum Redirection Table Entry (RTE) Entry. */
199	uint8_t u8MaxRte;
200	/** Last valid RTE indirect register index. */
201	uint8_t u8LastRteRegIdx;
202	/* Alignment padding. */
203	uint8_t u8Padding0[1];
204	/** Redirection table entry - Valid write mask. */
205	uint64_t u64RteWriteMask;
206	/** Redirection table entry - Valid read mask. */
207	uint64_t u64RteReadMask;
208
209	/** The redirection table registers. */
210	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
211	/** The IRQ tags and source IDs for each pin (tracing purposes). */
212	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
213
214	/** The internal IRR reflecting state of the interrupt lines. */
215	uint32_t uIrr;
216	/** Alignment padding. */
217	uint32_t u32Padding2;
218
219	#ifndef IOAPIC_WITH_PDM_CRITSECT
220	/** The critsect for updating to the RTEs. */
221	PDMCRITSECT CritSect;
222	#endif
223
224	/** The MMIO region. */
225	IOMMMIOHANDLE hMmio;
226
227	#ifdef VBOX_WITH_STATISTICS
228	/** Number of MMIO reads in RZ. */
229	STAMCOUNTER StatMmioReadRZ;
230	/** Number of MMIO reads in R3. */
231	STAMCOUNTER StatMmioReadR3;
232
233	/** Number of MMIO writes in RZ. */
234	STAMCOUNTER StatMmioWriteRZ;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237
238	/** Number of SetIrq calls in RZ. */
239	STAMCOUNTER StatSetIrqRZ;
240	/** Number of SetIrq calls in R3. */
241	STAMCOUNTER StatSetIrqR3;
242
243	/** Number of SetEoi calls in RZ. */
244	STAMCOUNTER StatSetEoiRZ;
245	/** Number of SetEoi calls in R3. */
246	STAMCOUNTER StatSetEoiR3;
247
248	/** Number of redundant edge-triggered interrupts. */
249	STAMCOUNTER StatRedundantEdgeIntr;
250	/** Number of redundant level-triggered interrupts. */
251	STAMCOUNTER StatRedundantLevelIntr;
252	/** Number of suppressed level-triggered interrupts (by remote IRR). */
253	STAMCOUNTER StatSuppressedLevelIntr;
254	/** Number of IOMMU discarded interrupts (signaled by RTE). */
255	STAMCOUNTER StatIommuDiscardedIntr;
256	/** Number of IOMMU denied or failed MSIs. */
257	STAMCOUNTER StatIommuDiscardedMsi;
258	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
259	STAMCOUNTER StatEoiContention;
260	/** Number of returns to ring-3 due to Set RTE lock contention. */
261	STAMCOUNTER StatSetRteContention;
262	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
263	STAMCOUNTER StatLevelIrqSent;
264	/** Number of EOIs received for level-triggered interrupts from the local
265	* APIC(s). */
266	STAMCOUNTER StatEoiReceived;
267	#endif
268	/** Per-vector stats. */
269	STAMCOUNTER aStatVectors[256];
270	} IOAPIC;
271	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
272	/** Pointer to shared IOAPIC data. */
273	typedef IOAPIC *PIOAPIC;
274	/** Pointer to const shared IOAPIC data. */
275	typedef IOAPIC const *PCIOAPIC;
276
277
278	/**
279	* The I/O APIC device state for ring-3.
280	*/
281	typedef struct IOAPICR3
282	{
283	/** The IOAPIC helpers. */
284	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
285	} IOAPICR3;
286	/** Pointer to the I/O APIC device state for ring-3. */
287	typedef IOAPICR3 *PIOAPICR3;
288
289
290	/**
291	* The I/O APIC device state for ring-0.
292	*/
293	typedef struct IOAPICR0
294	{
295	/** The IOAPIC helpers. */
296	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
297	} IOAPICR0;
298	/** Pointer to the I/O APIC device state for ring-0. */
299	typedef IOAPICR0 *PIOAPICR0;
300
301
302	/**
303	* The I/O APIC device state for raw-mode.
304	*/
305	typedef struct IOAPICRC
306	{
307	/** The IOAPIC helpers. */
308	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
309	} IOAPICRC;
310	/** Pointer to the I/O APIC device state for raw-mode. */
311	typedef IOAPICRC *PIOAPICRC;
312
313
314	/** The I/O APIC device state for the current context. */
315	typedef CTX_SUFF(IOAPIC) IOAPICCC;
316	/** Pointer to the I/O APIC device state for the current context. */
317	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
318
319
320	/**
321	* xAPIC interrupt.
322	*/
323	typedef struct XAPICINTR
324	{
325	/** The interrupt vector. */
326	uint8_t u8Vector;
327	/** The destination (mask or ID). */
328	uint8_t u8Dest;
329	/** The destination mode. */
330	uint8_t u8DestMode;
331	/** Delivery mode. */
332	uint8_t u8DeliveryMode;
333	/** Trigger mode. */
334	uint8_t u8TriggerMode;
335	/** Redirection hint. */
336	uint8_t u8RedirHint;
337	/** Polarity. */
338	uint8_t u8Polarity;
339	/** Padding. */
340	uint8_t abPadding0;
341	} XAPICINTR;
342	/** Pointer to an I/O xAPIC interrupt struct. */
343	typedef XAPICINTR *PXAPICINTR;
344	/** Pointer to a const xAPIC interrupt struct. */
345	typedef XAPICINTR const *PCXAPICINTR;
346
347
348	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
349
350	/**
351	* Gets the arbitration register.
352	*
353	* @returns The arbitration.
354	*/
355	DECLINLINE(uint32_t) ioapicGetArb(void)
356	{
357	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
358	return 0;
359	}
360
361
362	/**
363	* Gets the version register.
364	*
365	* @returns The version.
366	*/
367	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
368	{
369	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
370	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
371	return uValue;
372	}
373
374
375	/**
376	* Sets the ID register.
377	*
378	* @param pThis The shared I/O APIC device state.
379	* @param uValue The value to set.
380	*/
381	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
382	{
383	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
384	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
385	}
386
387
388	/**
389	* Gets the ID register.
390	*
391	* @returns The ID.
392	* @param pThis The shared I/O APIC device state.
393	*/
394	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
395	{
396	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
397	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
398	return uValue;
399	}
400
401
402	/**
403	* Sets the index register.
404	*
405	* @param pThis The shared I/O APIC device state.
406	* @param uValue The value to set.
407	*/
408	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
409	{
410	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
411	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
412	}
413
414
415	/**
416	* Gets the index register.
417	*
418	* @returns The index value.
419	*/
420	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
421	{
422	uint32_t const uValue = pThis->u8Index;
423	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
424	return uValue;
425	}
426
427
428	/**
429	* Converts an MSI message to an APIC interrupt.
430	*
431	* @param pMsi The MSI message to convert.
432	* @param pIntr Where to store the APIC interrupt.
433	*/
434	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
435	{
436	/*
437	* Parse the message from the physical address and data
438	* See Intel spec. 10.11.1 "Message Address Register Format".
439	* See Intel spec. 10.11.2 "Message Data Register Format".
440	*/
441	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
442	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
443	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
444
445	pIntr->u8Vector = pMsi->Data.n.u8Vector;
446	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
447	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
448	}
449
450
451	#ifdef VBOX_WITH_IOMMU_AMD
452	/**
453	* Convert an APIC interrupt to an MSI message.
454	*
455	* @param pIntr The APIC interrupt to convert.
456	* @param pMsi Where to store the MSI message.
457	*/
458	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
459	{
460	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
461	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
462	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
463	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
464
465	pMsi->Data.n.u8Vector = pIntr->u8Vector;
466	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
467	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
468
469	/* pMsi->Data.n.u1Level = ??? */
470	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
471	* possible in theory? Maybe document this more explicitly... */
472	}
473	#endif
474
475
476	/**
477	* Signals the next pending interrupt for the specified Redirection Table Entry
478	* (RTE).
479	*
480	* @param pDevIns The device instance.
481	* @param pThis The shared I/O APIC device state.
482	* @param pThisCC The I/O APIC device state for the current context.
483	* @param uBusDevFn The bus:device:function of the device initiating the IRQ.
484	* @param idxRte The index of the RTE (validated).
485	*
486	* @remarks It is the responsibility of the caller to verify that an interrupt is
487	* pending for the pin corresponding to the RTE before calling this
488	* function.
489	*/
490	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte)
491	{
492	#ifndef IOAPIC_WITH_PDM_CRITSECT
493	Assert(PDMCritSectIsOwner(&pThis->CritSect));
494	#endif
495
496	/*
497	* Ensure the interrupt isn't masked.
498	*/
499	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
500	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
501	{
502	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
503	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
504	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
505	{
506	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
507	if (u8RemoteIrr)
508	{
509	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
510	return;
511	}
512	}
513
514	XAPICINTR ApicIntr;
515	RT_ZERO(ApicIntr);
516	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
517	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
518	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
519	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
520	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
521	ApicIntr.u8TriggerMode = u8TriggerMode;
522	ApicIntr.u8RedirHint = 0;
523
524	#ifdef VBOX_WITH_IOMMU_AMD
525	/*
526	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
527	*/
528	MSIMSG MsiOut;
529	MSIMSG MsiIn;
530	RT_ZERO(MsiOut);
531	RT_ZERO(MsiIn);
532	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
533	if (!PCIBDF_IS_VALID(uBusDevFn))
534	uBusDevFn = VBOX_PCI_BDF_SB_IOAPIC;
535	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, &MsiIn, &MsiOut);
536	LogFlow(("IOAPIC: IOMMU Remap. rc=%Rrc VectorIn=%#x VectorOut=%#x\n", rcRemap, MsiIn.Data.n.u8Vector, MsiOut.Data.n.u8Vector));
537	if (RT_SUCCESS(rcRemap))
538	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
539	else
540	{
541	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
542	Log(("IOAPIC: Interrupt (%#x) discarded (rc=%Rrc)\n", ApicIntr.u8Vector, rcRemap));
543	return;
544	}
545	#else
546	NOREF(uBusDevFn);
547	#endif
548
549	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
550	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
551	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
552	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
553	ApicIntr.u8Vector, ApicIntr.u8Vector));
554
555	/*
556	* Deliver to the local APIC via the system/3-wire-APIC bus.
557	*/
558	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
559	ApicIntr.u8Dest,
560	ApicIntr.u8DestMode,
561	ApicIntr.u8DeliveryMode,
562	ApicIntr.u8Vector,
563	ApicIntr.u8Polarity,
564	ApicIntr.u8TriggerMode,
565	u32TagSrc);
566	/* Can't reschedule to R3. */
567	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
568	#ifdef DEBUG_ramshankar
569	if (rc == VERR_APIC_INTR_DISCARDED)
570	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
571	#endif
572
573	/*
574	* For level-triggered interrupts, we set the remote IRR bit to indicate
575	* the local APIC has accepted the interrupt.
576	*
577	* For edge-triggered interrupts, we should not clear the IRR bit as it
578	* should remain intact to reflect the state of the interrupt line.
579	* The device will explicitly transition to inactive state via the
580	* ioapicSetIrq() callback.
581	*/
582	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
583	&& rc == VINF_SUCCESS)
584	{
585	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
586	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
587	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
588	}
589	}
590	}
591
592
593	/**
594	* Gets the redirection table entry.
595	*
596	* @returns The redirection table entry.
597	* @param pThis The shared I/O APIC device state.
598	* @param uIndex The index value.
599	*/
600	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
601	{
602	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
603	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
604	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
605	UINT32_MAX);
606	uint32_t uValue;
607	if (!(uIndex & 1))
608	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
609	else
610	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
611
612	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
613	return uValue;
614	}
615
616
617	/**
618	* Sets the redirection table entry.
619	*
620	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
621	* @param pDevIns The device instance.
622	* @param pThis The shared I/O APIC device state.
623	* @param pThisCC The I/O APIC device state for the current context.
624	* @param uIndex The index value.
625	* @param uValue The value to set.
626	*/
627	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
628	uint32_t uIndex, uint32_t uValue)
629	{
630	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
631	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
632	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
633	VINF_SUCCESS);
634
635	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
636	if (rc == VINF_SUCCESS)
637	{
638	/*
639	* Write the low or high 32-bit value into the specified 64-bit RTE register,
640	* update only the valid, writable bits.
641	*
642	* We need to preserve the read-only bits as it can have dire consequences
643	* otherwise, see @bugref{8386#c24}.
644	*/
645	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
646	if (!(uIndex & 1))
647	{
648	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
649	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
650	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
651	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
652	}
653	else
654	{
655	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
656	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
657	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
658	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
659	}
660
661	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
662
663	/*
664	* Signal the next pending interrupt for this RTE.
665	*/
666	uint32_t const uPinMask = UINT32_C(1) << idxRte;
667	if (pThis->uIrr & uPinMask)
668	{
669	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
670	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
671	}
672
673	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
674	}
675	else
676	STAM_COUNTER_INC(&pThis->StatSetRteContention);
677
678	return rc;
679	}
680
681
682	/**
683	* Gets the data register.
684	*
685	* @returns The data value.
686	* @param pThis The shared I/O APIC device state.
687	*/
688	static uint32_t ioapicGetData(PCIOAPIC pThis)
689	{
690	uint8_t const uIndex = pThis->u8Index;
691	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
692	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
693	&& uIndex <= pThis->u8LastRteRegIdx)
694	return ioapicGetRedirTableEntry(pThis, uIndex);
695
696	uint32_t uValue;
697	switch (uIndex)
698	{
699	case IOAPIC_INDIRECT_INDEX_ID:
700	uValue = ioapicGetId(pThis);
701	break;
702
703	case IOAPIC_INDIRECT_INDEX_VERSION:
704	uValue = ioapicGetVersion(pThis);
705	break;
706
707	case IOAPIC_INDIRECT_INDEX_ARB:
708	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
709	{
710	uValue = ioapicGetArb();
711	break;
712	}
713	RT_FALL_THRU();
714
715	default:
716	uValue = UINT32_C(0xffffffff);
717	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
718	break;
719	}
720	return uValue;
721	}
722
723
724	/**
725	* Sets the data register.
726	*
727	* @returns Strict VBox status code.
728	* @param pDevIns The device instance.
729	* @param pThis The shared I/O APIC device state.
730	* @param pThisCC The I/O APIC device state for the current context.
731	* @param uValue The value to set.
732	*/
733	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
734	{
735	uint8_t const uIndex = pThis->u8Index;
736	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
737	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
738
739	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
740	&& uIndex <= pThis->u8LastRteRegIdx)
741	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
742
743	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
744	ioapicSetId(pThis, uValue);
745	else
746	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
747
748	return VINF_SUCCESS;
749	}
750
751
752	/**
753	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
754	*/
755	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
756	{
757	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
758	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
759	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
760	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
761
762	bool fRemoteIrrCleared = false;
763	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
764	if (rc == VINF_SUCCESS)
765	{
766	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
767	{
768	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
769	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
770	{
771	#ifdef DEBUG_ramshankar
772	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
773	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
774	#endif
775	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
776	fRemoteIrrCleared = true;
777	STAM_COUNTER_INC(&pThis->StatEoiReceived);
778	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
779
780	/*
781	* Signal the next pending interrupt for this RTE.
782	*/
783	uint32_t const uPinMask = UINT32_C(1) << idxRte;
784	if (pThis->uIrr & uPinMask)
785	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
786	}
787	}
788
789	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
790	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
791	}
792	else
793	STAM_COUNTER_INC(&pThis->StatEoiContention);
794
795	return rc;
796	}
797
798
799	/**
800	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
801	*/
802	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
803	{
804	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
805	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
806	pThis->uIrr \|= a_PinMask; \
807	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \
808	} while (0)
809
810	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
811	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
812	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
813
814	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
815
816	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
817	{
818	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
819	AssertRC(rc);
820
821	uint8_t const idxRte = iIrq;
822	uint32_t const uPinMask = UINT32_C(1) << idxRte;
823	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
824	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
825
826	bool fActive = RT_BOOL(iLevel & 1);
827	/** @todo Polarity is busted elsewhere, we need to fix that
828	* first. See @bugref{8386#c7}. */
829	#if 0
830	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
831	fActive ^= u8Polarity; */
832	#endif
833	if (!fActive)
834	{
835	pThis->uIrr &= ~uPinMask;
836	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
837	return;
838	}
839
840	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
841	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
842	if (!fFlipFlop)
843	{
844	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
845	{
846	/*
847	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
848	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
849	*/
850	if (!uPrevIrr)
851	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
852	else
853	{
854	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
855	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
856	}
857	}
858	else
859	{
860	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
861
862	/*
863	* For level-triggered interrupts, redundant interrupts are not a problem
864	* and will eventually be delivered anyway after an EOI, but our PDM devices
865	* should not typically call us with no change to the level.
866	*/
867	if (!uPrevIrr)
868	{ /* likely */ }
869	else
870	{
871	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
872	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
873	}
874
875	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
876	}
877	}
878	else
879	{
880	/*
881	* The device is flip-flopping the interrupt line, which implies we should de-assert
882	* and assert the interrupt line. The interrupt line is left in the asserted state
883	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
884	* hence just the assert is done.
885	*/
886	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
887	}
888
889	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
890	}
891	#undef IOAPIC_ASSERT_IRQ
892	}
893
894
895	/**
896	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
897	*/
898	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
899	{
900	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
901	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
902	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
903
904	XAPICINTR ApicIntr;
905	RT_ZERO(ApicIntr);
906
907	#ifdef VBOX_WITH_IOMMU_AMD
908	/*
909	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
910	*/
911	MSIMSG MsiOut;
912	RT_ZERO(MsiOut);
913	Assert(PCIBDF_IS_VALID(uBusDevFn));
914	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
915	if (RT_SUCCESS(rcRemap))
916	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
917	else
918	{
919	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
920	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
921	Log3(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping denied. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
922	else
923	Log(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping failed. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
924	return;
925	}
926	#else
927	NOREF(uBusDevFn);
928	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
929	#endif
930
931	/*
932	* Deliver to the local APIC via the system/3-wire-APIC bus.
933	*/
934	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
935
936	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
937	ApicIntr.u8Dest,
938	ApicIntr.u8DestMode,
939	ApicIntr.u8DeliveryMode,
940	ApicIntr.u8Vector,
941	0 /* u8Polarity - N/A */,
942	ApicIntr.u8TriggerMode,
943	uTagSrc);
944	/* Can't reschedule to R3. */
945	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
946	}
947
948
949	/**
950	* @callback_method_impl{FNIOMMMIONEWREAD}
951	*/
952	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
953	{
954	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
955	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
956	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
957	RT_NOREF_PV(pvUser);
958
959	VBOXSTRICTRC rc = VINF_SUCCESS;
960	uint32_t puValue = (uint32_t )pv;
961	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
962	switch (offReg)
963	{
964	case IOAPIC_DIRECT_OFF_INDEX:
965	*puValue = ioapicGetIndex(pThis);
966	break;
967
968	case IOAPIC_DIRECT_OFF_DATA:
969	*puValue = ioapicGetData(pThis);
970	break;
971
972	default:
973	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
974	rc = VINF_IOM_MMIO_UNUSED_FF;
975	break;
976	}
977
978	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
979	return rc;
980	}
981
982
983	/**
984	* @callback_method_impl{FNIOMMMIONEWWRITE}
985	*/
986	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
987	{
988	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
989	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
990	RT_NOREF_PV(pvUser);
991
992	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
993
994	Assert(!(off & 3));
995	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
996
997	VBOXSTRICTRC rc = VINF_SUCCESS;
998	uint32_t const uValue = (uint32_t const )pv;
999	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1000
1001	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1002	switch (offReg)
1003	{
1004	case IOAPIC_DIRECT_OFF_INDEX:
1005	ioapicSetIndex(pThis, uValue);
1006	break;
1007
1008	case IOAPIC_DIRECT_OFF_DATA:
1009	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1010	break;
1011
1012	case IOAPIC_DIRECT_OFF_EOI:
1013	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1014	rc = ioapicSetEoi(pDevIns, uValue);
1015	else
1016	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1017	break;
1018
1019	default:
1020	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1021	break;
1022	}
1023
1024	return rc;
1025	}
1026
1027
1028	#ifdef IN_RING3
1029
1030	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1031	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1032	{
1033	RT_NOREF(pDesc);
1034	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1035	return VINF_SUCCESS;
1036	}
1037
1038
1039	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1040	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1041	{
1042	RT_NOREF(pDesc, pfMask);
1043	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1044	return VINF_SUCCESS;
1045	}
1046
1047
1048	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1049	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1050	{
1051	RT_NOREF(pDesc);
1052	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1053	return VINF_SUCCESS;
1054	}
1055
1056
1057	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1058	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1059	{
1060	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1061	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1062	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1063	RT_NOREF(pDesc, pfMask);
1064	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1065	}
1066
1067
1068	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1069	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1070	{
1071	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1072	RT_NOREF(pDesc);
1073	pValue->u32 = ioapicGetVersion(pThis);
1074	return VINF_SUCCESS;
1075	}
1076
1077
1078	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1079	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1080	{
1081	RT_NOREF(pvUser, pDesc);
1082	pValue->u32 = ioapicGetArb();
1083	return VINF_SUCCESS;
1084	}
1085
1086
1087	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1088	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1089	{
1090	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1091	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1092	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1093	return VINF_SUCCESS;
1094	}
1095
1096
1097	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1098	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1099	{
1100	RT_NOREF(pfMask);
1101	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1102	/* No locks, no checks, just do it. */
1103	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1104	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1105	return VINF_SUCCESS;
1106	}
1107
1108
1109	/** IOREDTBLn sub fields. */
1110	static DBGFREGSUBFIELD const g_aRteSubs[] =
1111	{
1112	{ "vector", 0, 8, 0, 0, NULL, NULL },
1113	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1114	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1115	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1116	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1117	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1118	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1119	{ "mask", 16, 1, 0, 0, NULL, NULL },
1120	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1121	{ "dest", 56, 8, 0, 0, NULL, NULL },
1122	DBGFREGSUBFIELD_TERMINATOR()
1123	};
1124
1125
1126	/** Register descriptors for DBGF. */
1127	static DBGFREGDESC const g_aRegDesc[] =
1128	{
1129	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1130	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1131	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1132	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1133	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1134	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1135	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1136	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1137	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1138	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1139	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1140	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1141	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1142	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1143	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1144	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1145	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1146	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1147	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1148	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1149	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1150	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1151	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1152	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1153	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1154	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1155	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1156	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1157	DBGFREGDESC_TERMINATOR()
1158	};
1159
1160
1161	/**
1162	* @callback_method_impl{FNDBGFHANDLERDEV}
1163	*/
1164	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1165	{
1166	RT_NOREF(pszArgs);
1167	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1168	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1169
1170	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1171
1172	uint32_t const uId = ioapicGetId(pThis);
1173	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1174	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1175
1176	uint32_t const uVer = ioapicGetVersion(pThis);
1177	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1178	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1179	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1180	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1181
1182	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1183	{
1184	uint32_t const uArb = ioapicGetArb();
1185	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1186	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1187	}
1188
1189	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1190
1191	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1192	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1193
1194	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1195	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1196	{
1197	static const char * const s_apszDeliveryModes[] =
1198	{
1199	"Fixed ",
1200	"LowPri",
1201	"SMI ",
1202	"Rsvd ",
1203	"NMI ",
1204	"INIT ",
1205	"Rsvd ",
1206	"ExtINT"
1207	};
1208
1209	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1210	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1211	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1212	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1213	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1214	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1215	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1216	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1217	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1218	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1219	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1220	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1221
1222	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1223	idxRte,
1224	pszDestMode,
1225	uDest,
1226	uMask,
1227	(pThis->uIrr >> idxRte) & 1,
1228	pszTriggerMode,
1229	uRemoteIrr,
1230	pszPolarity,
1231	pszDeliveryStatus,
1232	pszDeliveryMode,
1233	uVector,
1234	u64Rte);
1235	}
1236	}
1237
1238
1239	/**
1240	* @copydoc FNSSMDEVSAVEEXEC
1241	*/
1242	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1243	{
1244	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1245	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1246	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1247
1248	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1249	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1250	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1251	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1252	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1253
1254	return VINF_SUCCESS;
1255	}
1256
1257
1258	/**
1259	* @copydoc FNSSMDEVLOADEXEC
1260	*/
1261	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1262	{
1263	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1264	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1265	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1266
1267	Assert(uPass == SSM_PASS_FINAL);
1268	NOREF(uPass);
1269
1270	/* Weed out invalid versions. */
1271	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1272	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1273	{
1274	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1275	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1276	}
1277
1278	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1279	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1280
1281	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1282	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1283	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1284	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1285
1286	return VINF_SUCCESS;
1287	}
1288
1289
1290	/**
1291	* @interface_method_impl{PDMDEVREG,pfnReset}
1292	*/
1293	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1294	{
1295	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1296	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1297	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1298
1299	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1300	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1301
1302	pThis->uIrr = 0;
1303	pThis->u8Index = 0;
1304	pThis->u8Id = 0;
1305
1306	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1307	{
1308	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1309	pThis->au32TagSrc[idxRte] = 0;
1310	}
1311
1312	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1313	}
1314
1315
1316	/**
1317	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1318	*/
1319	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1320	{
1321	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1322	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1323
1324	pThisRC->pIoApicHlp += offDelta;
1325	}
1326
1327
1328	/**
1329	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1330	*/
1331	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1332	{
1333	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1334	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1335	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1336
1337	# ifndef IOAPIC_WITH_PDM_CRITSECT
1338	/*
1339	* Destroy the RTE critical section.
1340	*/
1341	if (PDMCritSectIsInitialized(&pThis->CritSect))
1342	PDMR3CritSectDelete(&pThis->CritSect);
1343	# else
1344	RT_NOREF_PV(pThis);
1345	# endif
1346
1347	return VINF_SUCCESS;
1348	}
1349
1350
1351	/**
1352	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1353	*/
1354	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1355	{
1356	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1357	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1358	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1359	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1360	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1361	Assert(iInstance == 0); RT_NOREF(iInstance);
1362
1363	/*
1364	* Validate and read the configuration.
1365	*/
1366	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1367
1368	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1369	upsets some guest which we haven't yet tested. */
1370	uint32_t cCpus;
1371	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1372	if (RT_FAILURE(rc))
1373	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1374	pThis->cCpus = (uint8_t)cCpus;
1375
1376	char szChipType[16];
1377	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1378	if (RT_FAILURE(rc))
1379	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1380
1381	if (!strcmp(szChipType, "ICH9"))
1382	{
1383	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1384	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1385	pThis->u8IdMask = 0xff;
1386	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1387	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1388	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1389	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1390	}
1391	else if (!strcmp(szChipType, "82093AA"))
1392	{
1393	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1394	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1395	pThis->u8IdMask = 0x0f;
1396	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1397	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1398	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1399	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1400	}
1401	else if (!strcmp(szChipType, "82379AB"))
1402	{
1403	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1404	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1405	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1406	pThis->u8IdMask = 0x0f;
1407	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1408	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1409	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1410	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1411	}
1412	else
1413	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1414	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1415	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1416
1417	/*
1418	* We will use our own critical section for the IOAPIC device.
1419	*/
1420	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1421	AssertRCReturn(rc, rc);
1422
1423	# ifndef IOAPIC_WITH_PDM_CRITSECT
1424	/*
1425	* Setup the critical section to protect concurrent writes to the RTEs.
1426	*/
1427	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1428	AssertRCReturn(rc, rc);
1429	# endif
1430
1431	/*
1432	* Register the IOAPIC.
1433	*/
1434	PDMIOAPICREG IoApicReg;
1435	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1436	IoApicReg.pfnSetIrq = ioapicSetIrq;
1437	IoApicReg.pfnSendMsi = ioapicSendMsi;
1438	IoApicReg.pfnSetEoi = ioapicSetEoi;
1439	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1440	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1441	AssertRCReturn(rc, rc);
1442
1443	/*
1444	* Register MMIO region.
1445	*/
1446	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1447	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1448	AssertRCReturn(rc, rc);
1449
1450	/*
1451	* Register the saved state.
1452	*/
1453	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1454	AssertRCReturn(rc, rc);
1455
1456	/*
1457	* Register debugger info item.
1458	*/
1459	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1460	AssertRCReturn(rc, rc);
1461
1462	/*
1463	* Register debugger register access.
1464	*/
1465	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1466	AssertRCReturn(rc, rc);
1467
1468	# ifdef VBOX_WITH_STATISTICS
1469	/*
1470	* Statistics.
1471	*/
1472	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1473	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1474	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1475	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1476
1477	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1478	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1479	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1480	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1481
1482	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1483	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1484	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1485	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "IommuDiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded due to IOMMU.");
1486	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "IommuDiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded due to IOMMU.");
1487
1488	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1489	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1490
1491	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1492	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1493	# endif
1494	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1495	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1496	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1497
1498	/*
1499	* Init. the device state.
1500	*/
1501	LogRel(("IOAPIC: Using implementation 2.0! I/O APIC version is %d.%d\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0F));
1502	ioapicR3Reset(pDevIns);
1503
1504	return VINF_SUCCESS;
1505	}
1506
1507	#else /* !IN_RING3 */
1508
1509	/**
1510	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1511	*/
1512	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1513	{
1514	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1515	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1516	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1517
1518	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1519	AssertRCReturn(rc, rc);
1520
1521	PDMIOAPICREG IoApicReg;
1522	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1523	IoApicReg.pfnSetIrq = ioapicSetIrq;
1524	IoApicReg.pfnSendMsi = ioapicSendMsi;
1525	IoApicReg.pfnSetEoi = ioapicSetEoi;
1526	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1527	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1528	AssertRCReturn(rc, rc);
1529
1530	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1531	AssertRCReturn(rc, rc);
1532
1533	return VINF_SUCCESS;
1534	}
1535
1536	#endif /* !IN_RING3 */
1537
1538	/**
1539	* IO APIC device registration structure.
1540	*/
1541	const PDMDEVREG g_DeviceIOAPIC =
1542	{
1543	/* .u32Version = */ PDM_DEVREG_VERSION,
1544	/* .uReserved0 = */ 0,
1545	/* .szName = */ "ioapic",
1546	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1547	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1548	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1549	/* .cMaxInstances = */ 1,
1550	/* .uSharedVersion = */ 42,
1551	/* .cbInstanceShared = */ sizeof(IOAPIC),
1552	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1553	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1554	/* .cMaxPciDevices = */ 0,
1555	/* .cMaxMsixVectors = */ 0,
1556	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1557	#if defined(IN_RING3)
1558	/* .pszRCMod = */ "VBoxDDRC.rc",
1559	/* .pszR0Mod = */ "VBoxDDR0.r0",
1560	/* .pfnConstruct = */ ioapicR3Construct,
1561	/* .pfnDestruct = */ ioapicR3Destruct,
1562	/* .pfnRelocate = */ ioapicR3Relocate,
1563	/* .pfnMemSetup = */ NULL,
1564	/* .pfnPowerOn = */ NULL,
1565	/* .pfnReset = */ ioapicR3Reset,
1566	/* .pfnSuspend = */ NULL,
1567	/* .pfnResume = */ NULL,
1568	/* .pfnAttach = */ NULL,
1569	/* .pfnDetach = */ NULL,
1570	/* .pfnQueryInterface = */ NULL,
1571	/* .pfnInitComplete = */ NULL,
1572	/* .pfnPowerOff = */ NULL,
1573	/* .pfnSoftReset = */ NULL,
1574	/* .pfnReserved0 = */ NULL,
1575	/* .pfnReserved1 = */ NULL,
1576	/* .pfnReserved2 = */ NULL,
1577	/* .pfnReserved3 = */ NULL,
1578	/* .pfnReserved4 = */ NULL,
1579	/* .pfnReserved5 = */ NULL,
1580	/* .pfnReserved6 = */ NULL,
1581	/* .pfnReserved7 = */ NULL,
1582	#elif defined(IN_RING0)
1583	/* .pfnEarlyConstruct = */ NULL,
1584	/* .pfnConstruct = */ ioapicRZConstruct,
1585	/* .pfnDestruct = */ NULL,
1586	/* .pfnFinalDestruct = */ NULL,
1587	/* .pfnRequest = */ NULL,
1588	/* .pfnReserved0 = */ NULL,
1589	/* .pfnReserved1 = */ NULL,
1590	/* .pfnReserved2 = */ NULL,
1591	/* .pfnReserved3 = */ NULL,
1592	/* .pfnReserved4 = */ NULL,
1593	/* .pfnReserved5 = */ NULL,
1594	/* .pfnReserved6 = */ NULL,
1595	/* .pfnReserved7 = */ NULL,
1596	#elif defined(IN_RC)
1597	/* .pfnConstruct = */ ioapicRZConstruct,
1598	/* .pfnReserved0 = */ NULL,
1599	/* .pfnReserved1 = */ NULL,
1600	/* .pfnReserved2 = */ NULL,
1601	/* .pfnReserved3 = */ NULL,
1602	/* .pfnReserved4 = */ NULL,
1603	/* .pfnReserved5 = */ NULL,
1604	/* .pfnReserved6 = */ NULL,
1605	/* .pfnReserved7 = */ NULL,
1606	#else
1607	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1608	#endif
1609	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1610	};
1611
1612
1613	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1614

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 86861

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