VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 76553

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1/* $Id: DevIoApic.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23#include <VBox/log.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/msi.h>
26#include <VBox/vmm/pdmdev.h>
27
28#include "VBoxDD.h"
29#include <iprt/x86.h>
30
31
32/*********************************************************************************************************************************
33* Defined Constants And Macros *
34*********************************************************************************************************************************/
35/** The current IO APIC saved state version. */
36#define IOAPIC_SAVED_STATE_VERSION 2
37/** The saved state version used by VirtualBox 5.0 and
38 * earlier. */
39#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
40
41/** Implementation specified by the "Intel I/O Controller Hub 9
42 * (ICH9) Family" */
43#define IOAPIC_VERSION_ICH9 0x20
44/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
45Controller" */
46#define IOAPIC_VERSION_82093AA 0x11
47
48/** The default MMIO base physical address. */
49#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
50/** The size of the MMIO range. */
51#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
52/** The mask for getting direct registers from physical address. */
53#define IOAPIC_MMIO_REG_MASK 0xff
54
55/** The number of interrupt input pins. */
56#define IOAPIC_NUM_INTR_PINS 24
57/** Maximum redirection entires. */
58#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
59/** Reduced RTEs used by SIO.A (82379AB). */
60#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
61
62/** Version register - Gets the version. */
63#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
64/** Version register - Gets the maximum redirection entry. */
65#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
66/** Version register - Gets whether Pin Assertion Register (PRQ) is
67 * supported. */
68#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
69
70/** Index register - Valid write mask. */
71#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
72
73/** Arbitration register - Gets the ID. */
74#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
75
76/** ID register - Gets the ID. */
77#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
78
79/** Redirection table entry - Vector. */
80#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
81/** Redirection table entry - Delivery mode. */
82#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
83/** Redirection table entry - Destination mode. */
84#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
85/** Redirection table entry - Delivery status. */
86#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
87/** Redirection table entry - Interrupt input pin polarity. */
88#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
89/** Redirection table entry - Remote IRR. */
90#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
91/** Redirection table entry - Trigger Mode. */
92#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
93/** Redirection table entry - the mask bit number. */
94#define IOAPIC_RTE_MASK_BIT 16
95/** Redirection table entry - the mask. */
96#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
97/** Redirection table entry - Extended Destination ID. */
98#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
99/** Redirection table entry - Destination. */
100#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
101
102/** Redirection table entry - Gets the destination. */
103#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
104/** Redirection table entry - Gets the mask flag. */
105#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
106/** Redirection table entry - Checks whether it's masked. */
107#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
108/** Redirection table entry - Gets the trigger mode. */
109#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
110/** Redirection table entry - Gets the remote IRR flag. */
111#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
112/** Redirection table entry - Gets the interrupt pin polarity. */
113#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
114/** Redirection table entry - Gets the delivery status. */
115#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
116/** Redirection table entry - Gets the destination mode. */
117#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
118/** Redirection table entry - Gets the delivery mode. */
119#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
120/** Redirection table entry - Gets the vector. */
121#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
122
123/** Redirection table entry - Valid write mask for 82093AA. */
124#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
125 | IOAPIC_RTE_POLARITY | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE \
126 | IOAPIC_RTE_VECTOR)
127/** Redirection table entry - Valid read mask for 82093AA. */
128#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
129 | IOAPIC_RTE_REMOTE_IRR | IOAPIC_RTE_POLARITY | IOAPIC_RTE_DELIVERY_STATUS \
130 | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE | IOAPIC_RTE_VECTOR)
131
132/** Redirection table entry - Valid write mask for ICH9. */
133/** @note The remote IRR bit has been reverted to read-only as it turns out the
134 * ICH9 spec. is wrong, see @bugref{8386#c46}. */
135#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
136 /*| IOAPIC_RTE_REMOTE_IRR */| IOAPIC_RTE_POLARITY | IOAPIC_RTE_DEST_MODE \
137 | IOAPIC_RTE_DELIVERY_MODE | IOAPIC_RTE_VECTOR)
138/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
139#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST | IOAPIC_RTE_EXT_DEST_ID | IOAPIC_RTE_MASK \
140 | IOAPIC_RTE_TRIGGER_MODE | IOAPIC_RTE_REMOTE_IRR | IOAPIC_RTE_POLARITY \
141 | IOAPIC_RTE_DELIVERY_STATUS | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE \
142 | IOAPIC_RTE_VECTOR)
143
144/** Redirection table entry - Trigger mode edge. */
145#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
146/** Redirection table entry - Trigger mode level. */
147#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
148/** Redirection table entry - Destination mode physical. */
149#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
150/** Redirection table entry - Destination mode logical. */
151#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
152
153
154/** Index of indirect registers in the I/O APIC register table. */
155#define IOAPIC_INDIRECT_INDEX_ID 0x0
156#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
157#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
158#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
159#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
160#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
161
162/** Offset of direct registers in the I/O APIC MMIO space. */
163#define IOAPIC_DIRECT_OFF_INDEX 0x00
164#define IOAPIC_DIRECT_OFF_DATA 0x10
165#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
166
167/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
168#define IOAPIC_WITH_PDM_CRITSECT
169#ifdef IOAPIC_WITH_PDM_CRITSECT
170# define IOAPIC_LOCK(pThis, rcBusy) (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), (rcBusy))
171# define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
172#else
173# define IOAPIC_LOCK(pThis, rcBusy) PDMCritSectEnter(&(pThis)->CritSect, (rcBusy))
174# define IOAPIC_UNLOCK(pThis) PDMCritSectLeave(&(pThis)->CritSect)
175#endif
176
177
178/*********************************************************************************************************************************
179* Structures and Typedefs *
180*********************************************************************************************************************************/
181/**
182 * The per-VM I/O APIC device state.
183 */
184typedef struct IOAPIC
185{
186 /** The device instance - R3 Ptr. */
187 PPDMDEVINSR3 pDevInsR3;
188 /** The IOAPIC helpers - R3 Ptr. */
189 PCPDMIOAPICHLPR3 pIoApicHlpR3;
190
191 /** The device instance - R0 Ptr. */
192 PPDMDEVINSR0 pDevInsR0;
193 /** The IOAPIC helpers - R0 Ptr. */
194 PCPDMIOAPICHLPR0 pIoApicHlpR0;
195
196 /** The device instance - RC Ptr. */
197 PPDMDEVINSRC pDevInsRC;
198 /** The IOAPIC helpers - RC Ptr. */
199 PCPDMIOAPICHLPRC pIoApicHlpRC;
200
201 /** The ID register. */
202 uint8_t volatile u8Id;
203 /** The index register. */
204 uint8_t volatile u8Index;
205 /** Number of CPUs. */
206 uint8_t cCpus;
207 /** I/O APIC version. */
208 uint8_t u8ApicVer;
209 /** I/O APIC ID mask. */
210 uint8_t u8IdMask;
211 /** Maximum Redirection Table Entry (RTE) Entry. */
212 uint8_t u8MaxRte;
213 /** Last valid RTE indirect register index. */
214 uint8_t u8LastRteRegIdx;
215 /* Alignment padding. */
216 uint8_t u8Padding0[1];
217 /** Redirection table entry - Valid write mask. */
218 uint64_t u64RteWriteMask;
219 /** Redirection table entry - Valid read mask. */
220 uint64_t u64RteReadMask;
221
222 /** The redirection table registers. */
223 uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
224 /** The IRQ tags and source IDs for each pin (tracing purposes). */
225 uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
226
227 /** Alignment padding. */
228 uint32_t u32Padding2;
229 /** The internal IRR reflecting state of the interrupt lines. */
230 uint32_t uIrr;
231
232#ifndef IOAPIC_WITH_PDM_CRITSECT
233 /** The critsect for updating to the RTEs. */
234 PDMCRITSECT CritSect;
235#endif
236
237#ifdef VBOX_WITH_STATISTICS
238 /** Number of MMIO reads in RZ. */
239 STAMCOUNTER StatMmioReadRZ;
240 /** Number of MMIO reads in R3. */
241 STAMCOUNTER StatMmioReadR3;
242
243 /** Number of MMIO writes in RZ. */
244 STAMCOUNTER StatMmioWriteRZ;
245 /** Number of MMIO writes in R3. */
246 STAMCOUNTER StatMmioWriteR3;
247
248 /** Number of SetIrq calls in RZ. */
249 STAMCOUNTER StatSetIrqRZ;
250 /** Number of SetIrq calls in R3. */
251 STAMCOUNTER StatSetIrqR3;
252
253 /** Number of SetEoi calls in RZ. */
254 STAMCOUNTER StatSetEoiRZ;
255 /** Number of SetEoi calls in R3. */
256 STAMCOUNTER StatSetEoiR3;
257
258 /** Number of redundant edge-triggered interrupts. */
259 STAMCOUNTER StatRedundantEdgeIntr;
260 /** Number of redundant level-triggered interrupts. */
261 STAMCOUNTER StatRedundantLevelIntr;
262 /** Number of suppressed level-triggered interrupts (by remote IRR). */
263 STAMCOUNTER StatSuppressedLevelIntr;
264 /** Number of returns to ring-3 due to EOI broadcast lock contention. */
265 STAMCOUNTER StatEoiContention;
266 /** Number of returns to ring-3 due to Set RTE lock contention. */
267 STAMCOUNTER StatSetRteContention;
268 /** Number of level-triggered interrupts dispatched to the local APIC(s). */
269 STAMCOUNTER StatLevelIrqSent;
270 /** Number of EOIs received for level-triggered interrupts from the local
271 * APIC(s). */
272 STAMCOUNTER StatEoiReceived;
273#endif
274} IOAPIC;
275/** Pointer to IOAPIC data. */
276typedef IOAPIC *PIOAPIC;
277/** Pointer to a const IOAPIC data. */
278typedef IOAPIC const *PCIOAPIC;
279AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
280
281#ifndef VBOX_DEVICE_STRUCT_TESTCASE
282
283/**
284 * Gets the arbitration register.
285 *
286 * @returns The arbitration.
287 */
288DECLINLINE(uint32_t) ioapicGetArb(void)
289{
290 Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
291 return 0;
292}
293
294
295/**
296 * Gets the version register.
297 *
298 * @returns The version.
299 */
300DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
301{
302 uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
303 Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
304 return uValue;
305}
306
307
308/**
309 * Sets the ID register.
310 *
311 * @param pThis Pointer to the IOAPIC instance.
312 * @param uValue The value to set.
313 */
314DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
315{
316 Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
317 ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
318}
319
320
321/**
322 * Gets the ID register.
323 *
324 * @returns The ID.
325 * @param pThis Pointer to the IOAPIC instance.
326 */
327DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
328{
329 uint32_t uValue = (uint32_t)pThis->u8Id << 24;
330 Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
331 return uValue;
332}
333
334
335/**
336 * Sets the index register.
337 *
338 * @param pThis Pointer to the IOAPIC instance.
339 * @param uValue The value to set.
340 */
341DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
342{
343 LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
344 ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
345}
346
347
348/**
349 * Gets the index register.
350 *
351 * @returns The index value.
352 */
353DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
354{
355 uint32_t const uValue = pThis->u8Index;
356 LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
357 return uValue;
358}
359
360
361/**
362 * Signals the next pending interrupt for the specified Redirection Table Entry
363 * (RTE).
364 *
365 * @param pThis The IOAPIC instance.
366 * @param idxRte The index of the RTE.
367 *
368 * @remarks It is the responsibility of the caller to verify that an interrupt is
369 * pending for the pin corresponding to the RTE before calling this
370 * function.
371 */
372static void ioapicSignalIntrForRte(PIOAPIC pThis, uint8_t idxRte)
373{
374#ifndef IOAPIC_WITH_PDM_CRITSECT
375 Assert(PDMCritSectIsOwner(&pThis->CritSect));
376#endif
377
378 /* Ensure the RTE isn't masked. */
379 uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
380 if (!IOAPIC_RTE_IS_MASKED(u64Rte))
381 {
382 /* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
383 uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
384 if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
385 {
386 uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
387 if (u8RemoteIrr)
388 {
389 STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
390 return;
391 }
392 }
393
394 uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
395 uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
396 uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
397 uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
398 uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
399 uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
400
401 Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
402 u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
403 u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
404
405 /*
406 * Deliver to the local APIC via the system/3-wire-APIC bus.
407 */
408 int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns),
409 u8Dest,
410 u8DestMode,
411 u8DeliveryMode,
412 u8Vector,
413 u8Polarity,
414 u8TriggerMode,
415 u32TagSrc);
416 /* Can't reschedule to R3. */
417 Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED);
418#ifdef DEBUG_ramshankar
419 if (rc == VERR_APIC_INTR_DISCARDED)
420 AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
421#endif
422
423 /*
424 * For level-triggered interrupts, we set the remote IRR bit to indicate
425 * the local APIC has accepted the interrupt.
426 *
427 * For edge-triggered interrupts, we should not clear the IRR bit as it
428 * should remain intact to reflect the state of the interrupt line.
429 * The device will explicitly transition to inactive state via the
430 * ioapicSetIrq() callback.
431 */
432 if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
433 && rc == VINF_SUCCESS)
434 {
435 Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
436 pThis->au64RedirTable[idxRte] |= IOAPIC_RTE_REMOTE_IRR;
437 STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
438 }
439 }
440}
441
442
443/**
444 * Gets the redirection table entry.
445 *
446 * @returns The redirection table entry.
447 * @param pThis Pointer to the IOAPIC instance.
448 * @param uIndex The index value.
449 */
450DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
451{
452 uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
453 uint32_t uValue;
454 if (!(uIndex & 1))
455 uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
456 else
457 uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
458
459 LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
460 return uValue;
461}
462
463
464/**
465 * Sets the redirection table entry.
466 *
467 * @param pThis Pointer to the IOAPIC instance.
468 * @param uIndex The index value.
469 * @param uValue The value to set.
470 */
471static int ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)
472{
473 uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
474 AssertMsg(idxRte < RT_ELEMENTS(pThis->au64RedirTable), ("Invalid index %u, expected <= %u\n", idxRte,
475 RT_ELEMENTS(pThis->au64RedirTable)));
476
477 int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
478 if (rc == VINF_SUCCESS)
479 {
480 /*
481 * Write the low or high 32-bit value into the specified 64-bit RTE register,
482 * update only the valid, writable bits.
483 *
484 * We need to preserve the read-only bits as it can have dire consequences
485 * otherwise, see @bugref{8386#c24}.
486 */
487 uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
488 if (!(uIndex & 1))
489 {
490 uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
491 uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) | u32RtePreserveLo;
492 uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
493 pThis->au64RedirTable[idxRte] = u64RteHi | u32RteNewLo;
494 }
495 else
496 {
497 uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
498 uint32_t const u32RteLo = RT_LO_U32(u64Rte);
499 uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) | u32RtePreserveHi) << 32);
500 pThis->au64RedirTable[idxRte] = u64RteNewHi | u32RteLo;
501 }
502
503 /*
504 * Signal the next pending interrupt for this RTE.
505 */
506 uint32_t const uPinMask = UINT32_C(1) << idxRte;
507 if (pThis->uIrr & uPinMask)
508 ioapicSignalIntrForRte(pThis, idxRte);
509
510 IOAPIC_UNLOCK(pThis);
511 LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
512 }
513 else
514 STAM_COUNTER_INC(&pThis->StatSetRteContention);
515
516 return rc;
517}
518
519
520/**
521 * Gets the data register.
522 *
523 * @returns The data value.
524 * @param pThis Pointer to the IOAPIC instance.
525 */
526static uint32_t ioapicGetData(PCIOAPIC pThis)
527{
528 uint8_t const uIndex = pThis->u8Index;
529 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
530 if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
531 && uIndex <= pThis->u8LastRteRegIdx)
532 return ioapicGetRedirTableEntry(pThis, uIndex);
533
534 uint32_t uValue;
535 switch (uIndex)
536 {
537 case IOAPIC_INDIRECT_INDEX_ID:
538 uValue = ioapicGetId(pThis);
539 break;
540
541 case IOAPIC_INDIRECT_INDEX_VERSION:
542 uValue = ioapicGetVersion(pThis);
543 break;
544
545 case IOAPIC_INDIRECT_INDEX_ARB:
546 if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
547 {
548 uValue = ioapicGetArb();
549 break;
550 }
551 RT_FALL_THRU();
552
553 default:
554 uValue = UINT32_C(0xffffffff);
555 Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
556 break;
557 }
558 return uValue;
559}
560
561
562/**
563 * Sets the data register.
564 *
565 * @param pThis Pointer to the IOAPIC instance.
566 * @param uValue The value to set.
567 */
568static int ioapicSetData(PIOAPIC pThis, uint32_t uValue)
569{
570 uint8_t const uIndex = pThis->u8Index;
571 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
572 LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
573
574 if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
575 && uIndex <= pThis->u8LastRteRegIdx)
576 return ioapicSetRedirTableEntry(pThis, uIndex, uValue);
577
578 if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
579 ioapicSetId(pThis, uValue);
580 else
581 Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
582
583 return VINF_SUCCESS;
584}
585
586
587/**
588 * @interface_method_impl{PDMIOAPICREG,pfnSetEoiR3}
589 */
590PDMBOTHCBDECL(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
591{
592 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
593 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
594 LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
595
596 bool fRemoteIrrCleared = false;
597 int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
598 if (rc == VINF_SUCCESS)
599 {
600 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
601 {
602 uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
603 if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
604 {
605#ifdef DEBUG_ramshankar
606 /* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
607 Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
608#endif
609 pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
610 fRemoteIrrCleared = true;
611 STAM_COUNTER_INC(&pThis->StatEoiReceived);
612 Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
613
614 /*
615 * Signal the next pending interrupt for this RTE.
616 */
617 uint32_t const uPinMask = UINT32_C(1) << idxRte;
618 if (pThis->uIrr & uPinMask)
619 ioapicSignalIntrForRte(pThis, idxRte);
620 }
621 }
622
623 IOAPIC_UNLOCK(pThis);
624 AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
625 }
626 else
627 STAM_COUNTER_INC(&pThis->StatEoiContention);
628
629 return rc;
630}
631
632
633/**
634 * @interface_method_impl{PDMIOAPICREG,pfnSetIrqR3}
635 */
636PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
637{
638#define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) do { \
639 pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
640 pThis->uIrr |= a_PinMask; \
641 ioapicSignalIntrForRte(pThis, (a_idxRte)); \
642 } while (0)
643
644 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
645 LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
646
647 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
648
649 if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))
650 {
651 int rc = IOAPIC_LOCK(pThis, VINF_SUCCESS);
652 AssertRC(rc);
653
654 uint8_t const idxRte = iIrq;
655 uint32_t const uPinMask = UINT32_C(1) << idxRte;
656 uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
657 uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
658
659 bool fActive = RT_BOOL(iLevel & 1);
660 /** @todo Polarity is busted elsewhere, we need to fix that
661 * first. See @bugref{8386#c7}. */
662#if 0
663 uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
664 fActive ^= u8Polarity; */
665#endif
666 if (!fActive)
667 {
668 pThis->uIrr &= ~uPinMask;
669 IOAPIC_UNLOCK(pThis);
670 return;
671 }
672
673 bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
674 uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
675 if (!fFlipFlop)
676 {
677 if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
678 {
679 /*
680 * For edge-triggered interrupts, we need to act only on a low to high edge transition.
681 * See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
682 */
683 if (!uPrevIrr)
684 IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
685 else
686 {
687 STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
688 Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
689 }
690 }
691 else
692 {
693 Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
694
695 /*
696 * For level-triggered interrupts, redundant interrupts are not a problem
697 * and will eventually be delivered anyway after an EOI, but our PDM devices
698 * should not typically call us with no change to the level.
699 */
700 if (!uPrevIrr)
701 { /* likely */ }
702 else
703 {
704 STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
705 Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
706 }
707
708 IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
709 }
710 }
711 else
712 {
713 /*
714 * The device is flip-flopping the interrupt line, which implies we should de-assert
715 * and assert the interrupt line. The interrupt line is left in the asserted state
716 * after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
717 * hence just the assert is done.
718 */
719 IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
720 }
721
722 IOAPIC_UNLOCK(pThis);
723 }
724#undef IOAPIC_ASSERT_IRQ
725}
726
727
728/**
729 * @interface_method_impl{PDMIOAPICREG,pfnSendMsiR3}
730 */
731PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
732{
733 PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
734 LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
735
736 /*
737 * Parse the message from the physical address.
738 * See Intel spec. 10.11.1 "Message Address Register Format".
739 */
740 uint8_t const u8DestAddr = (GCPhys & VBOX_MSI_ADDR_DEST_ID_MASK) >> VBOX_MSI_ADDR_DEST_ID_SHIFT;
741 uint8_t const u8DestMode = (GCPhys >> VBOX_MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
742 /** @todo Check if we need to implement Redirection Hint Indicator. */
743 /* uint8_t const uRedirectHint = (GCPhys >> VBOX_MSI_ADDR_REDIRECTION_SHIFT) & 0x1; */
744
745 /*
746 * Parse the message data.
747 * See Intel spec. 10.11.2 "Message Data Register Format".
748 */
749 uint8_t const u8Vector = (uValue & VBOX_MSI_DATA_VECTOR_MASK) >> VBOX_MSI_DATA_VECTOR_SHIFT;
750 uint8_t const u8TriggerMode = (uValue >> VBOX_MSI_DATA_TRIGGER_SHIFT) & 0x1;
751 uint8_t const u8DeliveryMode = (uValue >> VBOX_MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
752
753 /*
754 * Deliver to the local APIC via the system/3-wire-APIC bus.
755 */
756 int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,
757 u8DestAddr,
758 u8DestMode,
759 u8DeliveryMode,
760 u8Vector,
761 0 /* u8Polarity - N/A */,
762 u8TriggerMode,
763 uTagSrc);
764 /* Can't reschedule to R3. */
765 Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
766}
767
768
769/**
770 * @callback_method_impl{FNIOMMMIOREAD}
771 */
772PDMBOTHCBDECL(int) ioapicMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
773{
774 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
775 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
776 Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
777 RT_NOREF_PV(pvUser);
778
779 int rc = VINF_SUCCESS;
780 uint32_t *puValue = (uint32_t *)pv;
781 uint32_t offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
782 switch (offReg)
783 {
784 case IOAPIC_DIRECT_OFF_INDEX:
785 *puValue = ioapicGetIndex(pThis);
786 break;
787
788 case IOAPIC_DIRECT_OFF_DATA:
789 *puValue = ioapicGetData(pThis);
790 break;
791
792 default:
793 Log2(("IOAPIC: ioapicMmioRead: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
794 rc = VINF_IOM_MMIO_UNUSED_FF;
795 break;
796 }
797
798 LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
799 return rc;
800}
801
802
803/**
804 * @callback_method_impl{FNIOMMMIOWRITE}
805 */
806PDMBOTHCBDECL(int) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
807{
808 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
809 RT_NOREF_PV(pvUser);
810
811 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
812
813 Assert(!(GCPhysAddr & 3));
814 Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
815
816 uint32_t const uValue = *(uint32_t const *)pv;
817 uint32_t const offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
818
819 LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p GCPhysAddr=%#RGp cb=%u uValue=%#RX32\n", pThis, GCPhysAddr, cb, uValue));
820 int rc = VINF_SUCCESS;
821 switch (offReg)
822 {
823 case IOAPIC_DIRECT_OFF_INDEX:
824 ioapicSetIndex(pThis, uValue);
825 break;
826
827 case IOAPIC_DIRECT_OFF_DATA:
828 rc = ioapicSetData(pThis, uValue);
829 break;
830
831 case IOAPIC_DIRECT_OFF_EOI:
832 if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
833 rc = ioapicSetEoi(pDevIns, uValue);
834 else
835 Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
836 break;
837
838 default:
839 Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
840 break;
841 }
842
843 return rc;
844}
845
846
847#ifdef IN_RING3
848
849/** @interface_method_impl{DBGFREGDESC,pfnGet} */
850static DECLCALLBACK(int) ioapicDbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
851{
852 RT_NOREF(pDesc);
853 pValue->u32 = ioapicGetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
854 return VINF_SUCCESS;
855}
856
857
858/** @interface_method_impl{DBGFREGDESC,pfnSet} */
859static DECLCALLBACK(int) ioapicDbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
860{
861 RT_NOREF(pDesc, pfMask);
862 ioapicSetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
863 return VINF_SUCCESS;
864}
865
866
867/** @interface_method_impl{DBGFREGDESC,pfnGet} */
868static DECLCALLBACK(int) ioapicDbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
869{
870 RT_NOREF(pDesc);
871 pValue->u32 = ioapicGetData((PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
872 return VINF_SUCCESS;
873}
874
875
876/** @interface_method_impl{DBGFREGDESC,pfnSet} */
877static DECLCALLBACK(int) ioapicDbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
878{
879 RT_NOREF(pDesc, pfMask);
880 return ioapicSetData(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);
881}
882
883
884/** @interface_method_impl{DBGFREGDESC,pfnGet} */
885static DECLCALLBACK(int) ioapicDbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
886{
887 PCIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
888 RT_NOREF(pDesc);
889 pValue->u32 = ioapicGetVersion(pThis);
890 return VINF_SUCCESS;
891}
892
893
894/** @interface_method_impl{DBGFREGDESC,pfnGet} */
895static DECLCALLBACK(int) ioapicDbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
896{
897 RT_NOREF(pvUser, pDesc);
898 pValue->u32 = ioapicGetArb();
899 return VINF_SUCCESS;
900}
901
902
903/** @interface_method_impl{DBGFREGDESC,pfnGet} */
904static DECLCALLBACK(int) ioapicDbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
905{
906 PCIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
907 Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
908 pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
909 return VINF_SUCCESS;
910}
911
912
913/** @interface_method_impl{DBGFREGDESC,pfnSet} */
914static DECLCALLBACK(int) ioapicDbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
915{
916 RT_NOREF(pfMask);
917 PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
918 /* No locks, no checks, just do it. */
919 Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
920 pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
921 return VINF_SUCCESS;
922}
923
924
925/** IOREDTBLn sub fields. */
926static DBGFREGSUBFIELD const g_aRteSubs[] =
927{
928 { "vector", 0, 8, 0, 0, NULL, NULL },
929 { "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
930 { "dest_mode", 11, 1, 0, 0, NULL, NULL },
931 { "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
932 { "polarity", 13, 1, 0, 0, NULL, NULL },
933 { "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
934 { "trigger_mode", 15, 1, 0, 0, NULL, NULL },
935 { "mask", 16, 1, 0, 0, NULL, NULL },
936 { "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
937 { "dest", 56, 8, 0, 0, NULL, NULL },
938 DBGFREGSUBFIELD_TERMINATOR()
939};
940
941
942/** Register descriptors for DBGF. */
943static DBGFREGDESC const g_aRegDesc[] =
944{
945 { "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicDbgReg_GetIndex, ioapicDbgReg_SetIndex, NULL, NULL },
946 { "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicDbgReg_GetData, ioapicDbgReg_SetData, NULL, NULL },
947 { "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetVersion, NULL, NULL, NULL },
948 { "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetArb, NULL, NULL, NULL },
949 { "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
950 { "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
951 { "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
952 { "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
953 { "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
954 { "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
955 { "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
956 { "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
957 { "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
958 { "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
959 { "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
960 { "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
961 { "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
962 { "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
963 { "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
964 { "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
965 { "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
966 { "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
967 { "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
968 { "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
969 { "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
970 { "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
971 { "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
972 { "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
973 DBGFREGDESC_TERMINATOR()
974};
975
976
977/**
978 * @callback_method_impl{FNDBGFHANDLERDEV}
979 */
980static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
981{
982 RT_NOREF(pszArgs);
983 PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
984 LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
985
986 pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
987
988 uint32_t const uId = ioapicGetId(pThis);
989 pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
990 pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
991
992 uint32_t const uVer = ioapicGetVersion(pThis);
993 pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
994 pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
995 pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
996 pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
997
998 if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
999 {
1000 uint32_t const uArb = ioapicGetArb();
1001 pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1002 pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1003 }
1004
1005 pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1006
1007 pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1008 pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1009
1010 for (uint8_t idxRte = 0; idxRte <= pThis->u8MaxRte; idxRte++)
1011 {
1012 static const char * const s_apszDeliveryModes[] =
1013 {
1014 "Fixed ",
1015 "LowPri",
1016 "SMI ",
1017 "Rsvd ",
1018 "NMI ",
1019 "INIT ",
1020 "Rsvd ",
1021 "ExtINT"
1022 };
1023
1024 const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1025 const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1026 const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1027 const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1028 const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1029 const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1030 const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1031 const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1032 const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1033 Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1034 const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1035 const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1036
1037 pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1038 idxRte,
1039 pszDestMode,
1040 uDest,
1041 uMask,
1042 (pThis->uIrr >> idxRte) & 1,
1043 pszTriggerMode,
1044 uRemoteIrr,
1045 pszPolarity,
1046 pszDeliveryStatus,
1047 pszDeliveryMode,
1048 uVector,
1049 u64Rte);
1050 }
1051}
1052
1053
1054/**
1055 * @copydoc FNSSMDEVSAVEEXEC
1056 */
1057static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1058{
1059 PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
1060 LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1061
1062 SSMR3PutU32(pSSM, pThis->uIrr);
1063 SSMR3PutU8(pSSM, pThis->u8Id);
1064 SSMR3PutU8(pSSM, pThis->u8Index);
1065 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1066 SSMR3PutU64(pSSM, pThis->au64RedirTable[idxRte]);
1067
1068 return VINF_SUCCESS;
1069}
1070
1071
1072/**
1073 * @copydoc FNSSMDEVLOADEXEC
1074 */
1075static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1076{
1077 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1078 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1079
1080 Assert(uPass == SSM_PASS_FINAL);
1081 NOREF(uPass);
1082
1083 /* Weed out invalid versions. */
1084 if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1085 && uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1086 {
1087 LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1088 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1089 }
1090
1091 if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1092 SSMR3GetU32(pSSM, (uint32_t *)&pThis->uIrr);
1093
1094 SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Id);
1095 SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Index);
1096 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1097 SSMR3GetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1098
1099 return VINF_SUCCESS;
1100}
1101
1102
1103/**
1104 * @interface_method_impl{PDMDEVREG,pfnReset}
1105 */
1106static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1107{
1108 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1109 LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1110
1111 /* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1112 IOAPIC_LOCK(pThis, VERR_IGNORED);
1113
1114 pThis->uIrr = 0;
1115 pThis->u8Index = 0;
1116 pThis->u8Id = 0;
1117
1118 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1119 {
1120 pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1121 pThis->au32TagSrc[idxRte] = 0;
1122 }
1123
1124 IOAPIC_UNLOCK(pThis);
1125}
1126
1127
1128/**
1129 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1130 */
1131static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1132{
1133 RT_NOREF(offDelta);
1134 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1135 LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", pThis, offDelta));
1136
1137 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1138 pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1139}
1140
1141
1142/**
1143 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1144 */
1145static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1146{
1147 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1148 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1149 LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1150
1151# ifndef IOAPIC_WITH_PDM_CRITSECT
1152 /*
1153 * Destroy the RTE critical section.
1154 */
1155 if (PDMCritSectIsInitialized(&pThis->CritSect))
1156 PDMR3CritSectDelete(&pThis->CritSect);
1157# else
1158 RT_NOREF_PV(pThis);
1159# endif
1160
1161 return VINF_SUCCESS;
1162}
1163
1164
1165/**
1166 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1167 */
1168static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1169{
1170 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1171 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1172 LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1173 Assert(iInstance == 0); RT_NOREF(iInstance);
1174
1175 /*
1176 * Initialize the state data.
1177 */
1178 pThis->pDevInsR3 = pDevIns;
1179 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1180 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1181
1182 /*
1183 * Validate and read the configuration.
1184 */
1185 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs|RZEnabled|ChipType", "");
1186
1187 /* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1188 upsets some guest which we haven't yet tested. */
1189 uint32_t cCpus;
1190 int rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1191 if (RT_FAILURE(rc))
1192 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1193 pThis->cCpus = (uint8_t)cCpus;
1194
1195 bool fRZEnabled;
1196 rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
1197 if (RT_FAILURE(rc))
1198 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
1199
1200 char szChipType[16];
1201 rc = CFGMR3QueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1202 if (RT_FAILURE(rc))
1203 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1204
1205 if (!strcmp(szChipType, "ICH9"))
1206 {
1207 /* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1208 pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1209 pThis->u8IdMask = 0xff;
1210 pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1211 pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1212 pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1213 pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1214 }
1215 else if (!strcmp(szChipType, "82093AA"))
1216 {
1217 /* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1218 pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1219 pThis->u8IdMask = 0x0f;
1220 pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1221 pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1222 pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1223 pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1224 }
1225 else if (!strcmp(szChipType, "82379AB"))
1226 {
1227 /* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1228 /* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1229 pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1230 pThis->u8IdMask = 0x0f;
1231 pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1232 pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1233 pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1234 pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1235 }
1236 else
1237 {
1238 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1239 N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"),
1240 szChipType);
1241 }
1242 Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, fRZEnabled, szChipType));
1243
1244 /*
1245 * We will use our own critical section for the IOAPIC device.
1246 */
1247 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1248 AssertRCReturn(rc, rc);
1249
1250# ifndef IOAPIC_WITH_PDM_CRITSECT
1251 /*
1252 * Setup the critical section to protect concurrent writes to the RTEs.
1253 */
1254 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1255 if (RT_FAILURE(rc))
1256 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("IOAPIC: Failed to create critical section. rc=%Rrc"), rc);
1257# endif
1258
1259 /*
1260 * Register the IOAPIC.
1261 */
1262 PDMIOAPICREG IoApicReg;
1263 RT_ZERO(IoApicReg);
1264 IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1265 IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
1266 IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
1267 IoApicReg.pfnSetEoiR3 = ioapicSetEoi;
1268 if (fRZEnabled)
1269 {
1270 IoApicReg.pszSetIrqRC = "ioapicSetIrq";
1271 IoApicReg.pszSetIrqR0 = "ioapicSetIrq";
1272
1273 IoApicReg.pszSendMsiRC = "ioapicSendMsi";
1274 IoApicReg.pszSendMsiR0 = "ioapicSendMsi";
1275
1276 IoApicReg.pszSetEoiRC = "ioapicSetEoi";
1277 IoApicReg.pszSetEoiR0 = "ioapicSetEoi";
1278 }
1279 rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
1280 if (RT_FAILURE(rc))
1281 {
1282 AssertMsgFailed(("IOAPIC: PDMDevHlpIOAPICRegister failed! rc=%Rrc\n", rc));
1283 return rc;
1284 }
1285
1286 /*
1287 * Register MMIO callbacks.
1288 */
1289 rc = PDMDevHlpMMIORegister(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, pThis,
1290 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead,
1291 "I/O APIC");
1292 if (RT_SUCCESS(rc))
1293 {
1294 if (fRZEnabled)
1295 {
1296 pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1297 rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
1298 "ioapicMmioWrite", "ioapicMmioRead");
1299 AssertRCReturn(rc, rc);
1300
1301 pThis->pIoApicHlpR0 = pThis->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1302 rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
1303 "ioapicMmioWrite", "ioapicMmioRead");
1304 AssertRCReturn(rc, rc);
1305 }
1306 }
1307 else
1308 {
1309 LogRel(("IOAPIC: PDMDevHlpMMIORegister failed! rc=%Rrc\n", rc));
1310 return rc;
1311 }
1312
1313 /*
1314 * Register saved-state callbacks.
1315 */
1316 rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1317 if (RT_FAILURE(rc))
1318 {
1319 LogRel(("IOAPIC: PDMDevHlpSSMRegister failed! rc=%Rrc\n", rc));
1320 return rc;
1321 }
1322
1323 /*
1324 * Register debugger info callback.
1325 */
1326 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1327 AssertRCReturn(rc, rc);
1328
1329 /*
1330 * Register debugger register access.
1331 */
1332 rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); AssertRC(rc);
1333 AssertRCReturn(rc, rc);
1334
1335# ifdef VBOX_WITH_STATISTICS
1336 /*
1337 * Statistics.
1338 */
1339 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1340 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1341 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1342 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1343
1344 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1345 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1346 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1347 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1348
1349 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1350 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1351 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1352
1353 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1354 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1355
1356 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1357 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1358# endif
1359
1360 /*
1361 * Init. the device state.
1362 */
1363 LogRel(("IOAPIC: Using implementation 2.0! Chipset type %s\n", szChipType));
1364 ioapicR3Reset(pDevIns);
1365
1366 return VINF_SUCCESS;
1367}
1368
1369
1370/**
1371 * IO APIC device registration structure.
1372 */
1373const PDMDEVREG g_DeviceIOAPIC =
1374{
1375 /* u32Version */
1376 PDM_DEVREG_VERSION,
1377 /* szName */
1378 "ioapic",
1379 /* szRCMod */
1380 "VBoxDDRC.rc",
1381 /* szR0Mod */
1382 "VBoxDDR0.r0",
1383 /* pszDescription */
1384 "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1385 /* fFlags */
1386 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1387 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1388 /* fClass */
1389 PDM_DEVREG_CLASS_PIC,
1390 /* cMaxInstances */
1391 1,
1392 /* cbInstance */
1393 sizeof(IOAPIC),
1394 /* pfnConstruct */
1395 ioapicR3Construct,
1396 /* pfnDestruct */
1397 ioapicR3Destruct,
1398 /* pfnRelocate */
1399 ioapicR3Relocate,
1400 /* pfnMemSetup */
1401 NULL,
1402 /* pfnPowerOn */
1403 NULL,
1404 /* pfnReset */
1405 ioapicR3Reset,
1406 /* pfnSuspend */
1407 NULL,
1408 /* pfnResume */
1409 NULL,
1410 /* pfnAttach */
1411 NULL,
1412 /* pfnDetach */
1413 NULL,
1414 /* pfnQueryInterface. */
1415 NULL,
1416 /* pfnInitComplete */
1417 NULL,
1418 /* pfnPowerOff */
1419 NULL,
1420 /* pfnSoftReset */
1421 NULL,
1422 /* u32VersionEnd */
1423 PDM_DEVREG_VERSION
1424};
1425
1426#endif /* IN_RING3 */
1427
1428#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1429
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