DevIoApic.cpp@ 84663

Last change on this file since 84663 was 84663, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 DevIoApic: Conversion between xAPIC interrupts and MSIs for upcoming IOMMU changes.
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1	/* $Id: DevIoApic.cpp 84663 2020-06-03 13:24:01Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/** The current IO APIC saved state version. */
36	#define IOAPIC_SAVED_STATE_VERSION 2
37	/** The saved state version used by VirtualBox 5.0 and
38	* earlier. */
39	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
40
41	/** Implementation specified by the "Intel I/O Controller Hub 9
42	* (ICH9) Family" */
43	#define IOAPIC_VERSION_ICH9 0x20
44	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
45	Controller" */
46	#define IOAPIC_VERSION_82093AA 0x11
47
48	/** The default MMIO base physical address. */
49	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
50	/** The size of the MMIO range. */
51	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
52	/** The mask for getting direct registers from physical address. */
53	#define IOAPIC_MMIO_REG_MASK 0xff
54
55	/** The number of interrupt input pins. */
56	#define IOAPIC_NUM_INTR_PINS 24
57	/** Maximum redirection entires. */
58	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
59	/** Reduced RTEs used by SIO.A (82379AB). */
60	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
61
62	/** Version register - Gets the version. */
63	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
64	/** Version register - Gets the maximum redirection entry. */
65	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
66	/** Version register - Gets whether Pin Assertion Register (PRQ) is
67	* supported. */
68	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
69
70	/** Index register - Valid write mask. */
71	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
72
73	/** Arbitration register - Gets the ID. */
74	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
75
76	/** ID register - Gets the ID. */
77	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
78
79	/** Redirection table entry - Vector. */
80	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
81	/** Redirection table entry - Delivery mode. */
82	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
83	/** Redirection table entry - Destination mode. */
84	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
85	/** Redirection table entry - Delivery status. */
86	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
87	/** Redirection table entry - Interrupt input pin polarity. */
88	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
89	/** Redirection table entry - Remote IRR. */
90	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
91	/** Redirection table entry - Trigger Mode. */
92	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
93	/** Redirection table entry - the mask bit number. */
94	#define IOAPIC_RTE_MASK_BIT 16
95	/** Redirection table entry - the mask. */
96	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
97	/** Redirection table entry - Extended Destination ID. */
98	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
99	/** Redirection table entry - Destination. */
100	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
101
102	/** Redirection table entry - Gets the destination. */
103	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
104	/** Redirection table entry - Gets the mask flag. */
105	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
106	/** Redirection table entry - Checks whether it's masked. */
107	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
108	/** Redirection table entry - Gets the trigger mode. */
109	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
110	/** Redirection table entry - Gets the remote IRR flag. */
111	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
112	/** Redirection table entry - Gets the interrupt pin polarity. */
113	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
114	/** Redirection table entry - Gets the delivery status. */
115	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
116	/** Redirection table entry - Gets the destination mode. */
117	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
118	/** Redirection table entry - Gets the delivery mode. */
119	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
120	/** Redirection table entry - Gets the vector. */
121	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
122
123	/** Redirection table entry - Valid write mask for 82093AA. */
124	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
125	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
126	\| IOAPIC_RTE_VECTOR)
127	/** Redirection table entry - Valid read mask for 82093AA. */
128	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
129	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
130	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
131
132	/** Redirection table entry - Valid write mask for ICH9. */
133	/** @note The remote IRR bit has been reverted to read-only as it turns out the
134	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
135	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
136	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
137	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
138	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
139	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
140	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
141	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
142	\| IOAPIC_RTE_VECTOR)
143
144	/** Redirection table entry - Trigger mode edge. */
145	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
146	/** Redirection table entry - Trigger mode level. */
147	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
148	/** Redirection table entry - Destination mode physical. */
149	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
150	/** Redirection table entry - Destination mode logical. */
151	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
152
153
154	/** Index of indirect registers in the I/O APIC register table. */
155	#define IOAPIC_INDIRECT_INDEX_ID 0x0
156	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
157	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
158	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
159	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
160	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
161
162	/** Offset of direct registers in the I/O APIC MMIO space. */
163	#define IOAPIC_DIRECT_OFF_INDEX 0x00
164	#define IOAPIC_DIRECT_OFF_DATA 0x10
165	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
166
167	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
168	#define IOAPIC_WITH_PDM_CRITSECT
169	#ifdef IOAPIC_WITH_PDM_CRITSECT
170	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
171	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
172	#else
173	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
174	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
175	#endif
176
177
178	/*********************************************************************************************************************************
179	* Structures and Typedefs *
180	*********************************************************************************************************************************/
181	/**
182	* The shared I/O APIC device state.
183	*/
184	typedef struct IOAPIC
185	{
186	/** The ID register. */
187	uint8_t volatile u8Id;
188	/** The index register. */
189	uint8_t volatile u8Index;
190	/** Number of CPUs. */
191	uint8_t cCpus;
192	/** I/O APIC version. */
193	uint8_t u8ApicVer;
194	/** I/O APIC ID mask. */
195	uint8_t u8IdMask;
196	/** Maximum Redirection Table Entry (RTE) Entry. */
197	uint8_t u8MaxRte;
198	/** Last valid RTE indirect register index. */
199	uint8_t u8LastRteRegIdx;
200	/* Alignment padding. */
201	uint8_t u8Padding0[1];
202	/** Redirection table entry - Valid write mask. */
203	uint64_t u64RteWriteMask;
204	/** Redirection table entry - Valid read mask. */
205	uint64_t u64RteReadMask;
206
207	/** The redirection table registers. */
208	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
209	/** The IRQ tags and source IDs for each pin (tracing purposes). */
210	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
211
212	/** The internal IRR reflecting state of the interrupt lines. */
213	uint32_t uIrr;
214	/** Alignment padding. */
215	uint32_t u32Padding2;
216
217	#ifndef IOAPIC_WITH_PDM_CRITSECT
218	/** The critsect for updating to the RTEs. */
219	PDMCRITSECT CritSect;
220	#endif
221
222	/** The MMIO region. */
223	IOMMMIOHANDLE hMmio;
224
225	#ifdef VBOX_WITH_STATISTICS
226	/** Number of MMIO reads in RZ. */
227	STAMCOUNTER StatMmioReadRZ;
228	/** Number of MMIO reads in R3. */
229	STAMCOUNTER StatMmioReadR3;
230
231	/** Number of MMIO writes in RZ. */
232	STAMCOUNTER StatMmioWriteRZ;
233	/** Number of MMIO writes in R3. */
234	STAMCOUNTER StatMmioWriteR3;
235
236	/** Number of SetIrq calls in RZ. */
237	STAMCOUNTER StatSetIrqRZ;
238	/** Number of SetIrq calls in R3. */
239	STAMCOUNTER StatSetIrqR3;
240
241	/** Number of SetEoi calls in RZ. */
242	STAMCOUNTER StatSetEoiRZ;
243	/** Number of SetEoi calls in R3. */
244	STAMCOUNTER StatSetEoiR3;
245
246	/** Number of redundant edge-triggered interrupts. */
247	STAMCOUNTER StatRedundantEdgeIntr;
248	/** Number of redundant level-triggered interrupts. */
249	STAMCOUNTER StatRedundantLevelIntr;
250	/** Number of suppressed level-triggered interrupts (by remote IRR). */
251	STAMCOUNTER StatSuppressedLevelIntr;
252	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
253	STAMCOUNTER StatEoiContention;
254	/** Number of returns to ring-3 due to Set RTE lock contention. */
255	STAMCOUNTER StatSetRteContention;
256	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
257	STAMCOUNTER StatLevelIrqSent;
258	/** Number of EOIs received for level-triggered interrupts from the local
259	* APIC(s). */
260	STAMCOUNTER StatEoiReceived;
261	#endif
262	} IOAPIC;
263	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
264	/** Pointer to shared IOAPIC data. */
265	typedef IOAPIC *PIOAPIC;
266	/** Pointer to const shared IOAPIC data. */
267	typedef IOAPIC const *PCIOAPIC;
268
269
270	/**
271	* The I/O APIC device state for ring-3.
272	*/
273	typedef struct IOAPICR3
274	{
275	/** The IOAPIC helpers. */
276	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
277	} IOAPICR3;
278	/** Pointer to the I/O APIC device state for ring-3. */
279	typedef IOAPICR3 *PIOAPICR3;
280
281
282	/**
283	* The I/O APIC device state for ring-0.
284	*/
285	typedef struct IOAPICR0
286	{
287	/** The IOAPIC helpers. */
288	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
289	} IOAPICR0;
290	/** Pointer to the I/O APIC device state for ring-0. */
291	typedef IOAPICR0 *PIOAPICR0;
292
293
294	/**
295	* The I/O APIC device state for raw-mode.
296	*/
297	typedef struct IOAPICRC
298	{
299	/** The IOAPIC helpers. */
300	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
301	} IOAPICRC;
302	/** Pointer to the I/O APIC device state for raw-mode. */
303	typedef IOAPICRC *PIOAPICRC;
304
305
306	/** The I/O APIC device state for the current context. */
307	typedef CTX_SUFF(IOAPIC) IOAPICCC;
308	/** Pointer to the I/O APIC device state for the current context. */
309	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
310
311
312	/**
313	* xAPIC interrupt.
314	*/
315	typedef struct XAPICINTR
316	{
317	/** The interrupt vector. */
318	uint8_t u8Vector;
319	/** The destination (mask or ID). */
320	uint8_t u8Dest;
321	/** The destination mode. */
322	uint8_t u8DestMode;
323	/** Delivery mode. */
324	uint8_t u8DeliveryMode;
325	/** Trigger mode. */
326	uint8_t u8TriggerMode;
327	/** Redirection hint. */
328	uint8_t u8RedirHint;
329	/** Polarity. */
330	uint8_t u8Polarity;
331	/** Padding. */
332	uint8_t abPadding0;
333	} XAPICINTR;
334	/** Pointer to an I/O xAPIC interrupt struct. */
335	typedef XAPICINTR *PXAPICINTR;
336	/** Pointer to a const xAPIC interrupt struct. */
337	typedef XAPICINTR const *PCXAPICINTR;
338
339
340	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
341
342	/**
343	* Gets the arbitration register.
344	*
345	* @returns The arbitration.
346	*/
347	DECLINLINE(uint32_t) ioapicGetArb(void)
348	{
349	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
350	return 0;
351	}
352
353
354	/**
355	* Gets the version register.
356	*
357	* @returns The version.
358	*/
359	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
360	{
361	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
362	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
363	return uValue;
364	}
365
366
367	/**
368	* Sets the ID register.
369	*
370	* @param pThis The shared I/O APIC device state.
371	* @param uValue The value to set.
372	*/
373	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
374	{
375	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
376	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
377	}
378
379
380	/**
381	* Gets the ID register.
382	*
383	* @returns The ID.
384	* @param pThis The shared I/O APIC device state.
385	*/
386	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
387	{
388	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
389	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
390	return uValue;
391	}
392
393
394	/**
395	* Sets the index register.
396	*
397	* @param pThis The shared I/O APIC device state.
398	* @param uValue The value to set.
399	*/
400	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
401	{
402	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
403	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
404	}
405
406
407	/**
408	* Gets the index register.
409	*
410	* @returns The index value.
411	*/
412	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
413	{
414	uint32_t const uValue = pThis->u8Index;
415	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
416	return uValue;
417	}
418
419
420	/**
421	* Converts an MSI message to an APIC interrupt.
422	*
423	* @param pMsi The MSI message to convert.
424	* @param pIntr Where to store the APIC interrupt.
425	*/
426	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
427	{
428	/*
429	* Parse the message from the physical address and data
430	* See Intel spec. 10.11.1 "Message Address Register Format".
431	* See Intel spec. 10.11.2 "Message Data Register Format".
432	*/
433	memset(pIntr, 0, sizeof(*pIntr));
434	pIntr->u8Dest = pMsi->MsiAddr.n.u8DestId;
435	pIntr->u8DestMode = pMsi->MsiAddr.n.u1DestMode;
436	pIntr->u8RedirHint = pMsi->MsiAddr.n.u1RedirHint;
437
438	pIntr->u8Vector = pMsi->MsiData.n.u8Vector;
439	pIntr->u8TriggerMode = pMsi->MsiData.n.u1TriggerMode;
440	pIntr->u8DeliveryMode = pMsi->MsiData.n.u3DeliveryMode;
441	}
442
443	#if 0
444	/**
445	* Convert an APIC interrupt to an MSI message.
446	*
447	* @param pIntr The APIC interrupt to convert.
448	* @param pMsi Where to store the MSI message.
449	*/
450	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
451	{
452	memset(pMsi, 0, sizeof(*pMsi));
453	pMsi->MsiAddr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
454	pMsi->MsiAddr.n.u8DestId = pIntr->u8Dest;
455	pMsi->MsiAddr.n.u1RedirHint = pIntr->u8RedirHint;
456	pMsi->MsiAddr.n.u1DestMode = pIntr->u8DestMode;
457
458	pMsi->MsiData.n.u8Vector = pIntr->u8Vector;
459	pMsi->MsiData.n.u3DeliveryMode = pIntr->u8DeliveryMode;
460	pMsi->MsiData.n.u1TriggerMode = pIntr->u8TriggerMode;
461
462	/* pMsi->MsiData.n.u1Level = ??? */
463	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
464	* possible in theory? Maybe document this more explicitly... */
465	}
466	#endif
467
468	/**
469	* Signals the next pending interrupt for the specified Redirection Table Entry
470	* (RTE).
471	*
472	* @param pDevIns The device instance.
473	* @param pThis The shared I/O APIC device state.
474	* @param pThisCC The I/O APIC device state for the current context.
475	* @param idxRte The index of the RTE (validated).
476	*
477	* @remarks It is the responsibility of the caller to verify that an interrupt is
478	* pending for the pin corresponding to the RTE before calling this
479	* function.
480	*/
481	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
482	{
483	#ifndef IOAPIC_WITH_PDM_CRITSECT
484	Assert(PDMCritSectIsOwner(&pThis->CritSect));
485	#endif
486
487	/* Ensure the RTE isn't masked. */
488	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
489	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
490	{
491	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
492	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
493	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
494	{
495	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
496	if (u8RemoteIrr)
497	{
498	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
499	return;
500	}
501	}
502
503	uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
504	uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
505	uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
506	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
507	uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
508	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
509
510	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
511	u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
512	u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
513
514	/*
515	* Deliver to the local APIC via the system/3-wire-APIC bus.
516	*/
517	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
518	u8Dest,
519	u8DestMode,
520	u8DeliveryMode,
521	u8Vector,
522	u8Polarity,
523	u8TriggerMode,
524	u32TagSrc);
525	/* Can't reschedule to R3. */
526	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
527	#ifdef DEBUG_ramshankar
528	if (rc == VERR_APIC_INTR_DISCARDED)
529	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
530	#endif
531
532	/*
533	* For level-triggered interrupts, we set the remote IRR bit to indicate
534	* the local APIC has accepted the interrupt.
535	*
536	* For edge-triggered interrupts, we should not clear the IRR bit as it
537	* should remain intact to reflect the state of the interrupt line.
538	* The device will explicitly transition to inactive state via the
539	* ioapicSetIrq() callback.
540	*/
541	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
542	&& rc == VINF_SUCCESS)
543	{
544	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
545	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
546	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
547	}
548	}
549	}
550
551
552	/**
553	* Gets the redirection table entry.
554	*
555	* @returns The redirection table entry.
556	* @param pThis The shared I/O APIC device state.
557	* @param uIndex The index value.
558	*/
559	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
560	{
561	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
562	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
563	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
564	UINT32_MAX);
565	uint32_t uValue;
566	if (!(uIndex & 1))
567	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
568	else
569	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
570
571	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
572	return uValue;
573	}
574
575
576	/**
577	* Sets the redirection table entry.
578	*
579	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
580	* @param pDevIns The device instance.
581	* @param pThis The shared I/O APIC device state.
582	* @param pThisCC The I/O APIC device state for the current context.
583	* @param uIndex The index value.
584	* @param uValue The value to set.
585	*/
586	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
587	uint32_t uIndex, uint32_t uValue)
588	{
589	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
590	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
591	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
592	VINF_SUCCESS);
593
594	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
595	if (rc == VINF_SUCCESS)
596	{
597	/*
598	* Write the low or high 32-bit value into the specified 64-bit RTE register,
599	* update only the valid, writable bits.
600	*
601	* We need to preserve the read-only bits as it can have dire consequences
602	* otherwise, see @bugref{8386#c24}.
603	*/
604	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
605	if (!(uIndex & 1))
606	{
607	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
608	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
609	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
610	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
611	}
612	else
613	{
614	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
615	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
616	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
617	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
618	}
619
620	/*
621	* Signal the next pending interrupt for this RTE.
622	*/
623	uint32_t const uPinMask = UINT32_C(1) << idxRte;
624	if (pThis->uIrr & uPinMask)
625	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
626
627	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
628	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
629	}
630	else
631	STAM_COUNTER_INC(&pThis->StatSetRteContention);
632
633	return rc;
634	}
635
636
637	/**
638	* Gets the data register.
639	*
640	* @returns The data value.
641	* @param pThis The shared I/O APIC device state.
642	*/
643	static uint32_t ioapicGetData(PCIOAPIC pThis)
644	{
645	uint8_t const uIndex = pThis->u8Index;
646	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
647	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
648	&& uIndex <= pThis->u8LastRteRegIdx)
649	return ioapicGetRedirTableEntry(pThis, uIndex);
650
651	uint32_t uValue;
652	switch (uIndex)
653	{
654	case IOAPIC_INDIRECT_INDEX_ID:
655	uValue = ioapicGetId(pThis);
656	break;
657
658	case IOAPIC_INDIRECT_INDEX_VERSION:
659	uValue = ioapicGetVersion(pThis);
660	break;
661
662	case IOAPIC_INDIRECT_INDEX_ARB:
663	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
664	{
665	uValue = ioapicGetArb();
666	break;
667	}
668	RT_FALL_THRU();
669
670	default:
671	uValue = UINT32_C(0xffffffff);
672	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
673	break;
674	}
675	return uValue;
676	}
677
678
679	/**
680	* Sets the data register.
681	*
682	* @returns Strict VBox status code.
683	* @param pDevIns The device instance.
684	* @param pThis The shared I/O APIC device state.
685	* @param pThisCC The I/O APIC device state for the current context.
686	* @param uValue The value to set.
687	*/
688	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
689	{
690	uint8_t const uIndex = pThis->u8Index;
691	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
692	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
693
694	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
695	&& uIndex <= pThis->u8LastRteRegIdx)
696	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
697
698	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
699	ioapicSetId(pThis, uValue);
700	else
701	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
702
703	return VINF_SUCCESS;
704	}
705
706
707	/**
708	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
709	*/
710	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
711	{
712	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
713	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
714	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
715	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
716
717	bool fRemoteIrrCleared = false;
718	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
719	if (rc == VINF_SUCCESS)
720	{
721	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
722	{
723	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
724	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
725	{
726	#ifdef DEBUG_ramshankar
727	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
728	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
729	#endif
730	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
731	fRemoteIrrCleared = true;
732	STAM_COUNTER_INC(&pThis->StatEoiReceived);
733	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
734
735	/*
736	* Signal the next pending interrupt for this RTE.
737	*/
738	uint32_t const uPinMask = UINT32_C(1) << idxRte;
739	if (pThis->uIrr & uPinMask)
740	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
741	}
742	}
743
744	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
745	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
746	}
747	else
748	STAM_COUNTER_INC(&pThis->StatEoiContention);
749
750	return rc;
751	}
752
753
754	/**
755	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
756	*/
757	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
758	{
759	#define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) do { \
760	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
761	pThis->uIrr \|= a_PinMask; \
762	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
763	} while (0)
764
765	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
766	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
767	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
768
769	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
770
771	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
772	{
773	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
774	AssertRC(rc);
775
776	uint8_t const idxRte = iIrq;
777	uint32_t const uPinMask = UINT32_C(1) << idxRte;
778	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
779	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
780
781	bool fActive = RT_BOOL(iLevel & 1);
782	/** @todo Polarity is busted elsewhere, we need to fix that
783	* first. See @bugref{8386#c7}. */
784	#if 0
785	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
786	fActive ^= u8Polarity; */
787	#endif
788	if (!fActive)
789	{
790	pThis->uIrr &= ~uPinMask;
791	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
792	return;
793	}
794
795	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
796	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
797	if (!fFlipFlop)
798	{
799	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
800	{
801	/*
802	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
803	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
804	*/
805	if (!uPrevIrr)
806	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
807	else
808	{
809	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
810	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
811	}
812	}
813	else
814	{
815	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
816
817	/*
818	* For level-triggered interrupts, redundant interrupts are not a problem
819	* and will eventually be delivered anyway after an EOI, but our PDM devices
820	* should not typically call us with no change to the level.
821	*/
822	if (!uPrevIrr)
823	{ /* likely */ }
824	else
825	{
826	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
827	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
828	}
829
830	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
831	}
832	}
833	else
834	{
835	/*
836	* The device is flip-flopping the interrupt line, which implies we should de-assert
837	* and assert the interrupt line. The interrupt line is left in the asserted state
838	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
839	* hence just the assert is done.
840	*/
841	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
842	}
843
844	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
845	}
846	#undef IOAPIC_ASSERT_IRQ
847	}
848
849
850	/**
851	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
852	*/
853	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
854	{
855	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
856	LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
857
858	MSIMSG MsiMsg;
859	MsiMsg.MsiAddr.u64 = GCPhys;
860	MsiMsg.MsiData.u32 = uValue;
861
862	XAPICINTR ApicIntr;
863	ioapicGetApicIntrFromMsi(&MsiMsg, &ApicIntr);
864
865	/*
866	* Deliver to the local APIC via the system/3-wire-APIC bus.
867	*/
868	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
869	ApicIntr.u8Dest,
870	ApicIntr.u8DestMode,
871	ApicIntr.u8DeliveryMode,
872	ApicIntr.u8Vector,
873	0 /* u8Polarity - N/A */,
874	ApicIntr.u8TriggerMode,
875	uTagSrc);
876	/* Can't reschedule to R3. */
877	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
878	}
879
880
881	/**
882	* @callback_method_impl{FNIOMMMIONEWREAD}
883	*/
884	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
885	{
886	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
887	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
888	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
889	RT_NOREF_PV(pvUser);
890
891	VBOXSTRICTRC rc = VINF_SUCCESS;
892	uint32_t puValue = (uint32_t )pv;
893	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
894	switch (offReg)
895	{
896	case IOAPIC_DIRECT_OFF_INDEX:
897	*puValue = ioapicGetIndex(pThis);
898	break;
899
900	case IOAPIC_DIRECT_OFF_DATA:
901	*puValue = ioapicGetData(pThis);
902	break;
903
904	default:
905	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
906	rc = VINF_IOM_MMIO_UNUSED_FF;
907	break;
908	}
909
910	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
911	return rc;
912	}
913
914
915	/**
916	* @callback_method_impl{FNIOMMMIONEWWRITE}
917	*/
918	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
919	{
920	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
921	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
922	RT_NOREF_PV(pvUser);
923
924	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
925
926	Assert(!(off & 3));
927	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
928
929	VBOXSTRICTRC rc = VINF_SUCCESS;
930	uint32_t const uValue = (uint32_t const )pv;
931	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
932
933	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
934	switch (offReg)
935	{
936	case IOAPIC_DIRECT_OFF_INDEX:
937	ioapicSetIndex(pThis, uValue);
938	break;
939
940	case IOAPIC_DIRECT_OFF_DATA:
941	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
942	break;
943
944	case IOAPIC_DIRECT_OFF_EOI:
945	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
946	rc = ioapicSetEoi(pDevIns, uValue);
947	else
948	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
949	break;
950
951	default:
952	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
953	break;
954	}
955
956	return rc;
957	}
958
959
960	#ifdef IN_RING3
961
962	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
963	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
964	{
965	RT_NOREF(pDesc);
966	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
967	return VINF_SUCCESS;
968	}
969
970
971	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
972	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
973	{
974	RT_NOREF(pDesc, pfMask);
975	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
976	return VINF_SUCCESS;
977	}
978
979
980	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
981	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
982	{
983	RT_NOREF(pDesc);
984	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
985	return VINF_SUCCESS;
986	}
987
988
989	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
990	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
991	{
992	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
993	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
994	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
995	RT_NOREF(pDesc, pfMask);
996	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
997	}
998
999
1000	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1001	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1002	{
1003	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1004	RT_NOREF(pDesc);
1005	pValue->u32 = ioapicGetVersion(pThis);
1006	return VINF_SUCCESS;
1007	}
1008
1009
1010	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1011	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1012	{
1013	RT_NOREF(pvUser, pDesc);
1014	pValue->u32 = ioapicGetArb();
1015	return VINF_SUCCESS;
1016	}
1017
1018
1019	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1020	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1021	{
1022	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1023	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1024	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1025	return VINF_SUCCESS;
1026	}
1027
1028
1029	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1030	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1031	{
1032	RT_NOREF(pfMask);
1033	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1034	/* No locks, no checks, just do it. */
1035	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1036	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1037	return VINF_SUCCESS;
1038	}
1039
1040
1041	/** IOREDTBLn sub fields. */
1042	static DBGFREGSUBFIELD const g_aRteSubs[] =
1043	{
1044	{ "vector", 0, 8, 0, 0, NULL, NULL },
1045	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1046	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1047	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1048	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1049	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1050	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1051	{ "mask", 16, 1, 0, 0, NULL, NULL },
1052	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1053	{ "dest", 56, 8, 0, 0, NULL, NULL },
1054	DBGFREGSUBFIELD_TERMINATOR()
1055	};
1056
1057
1058	/** Register descriptors for DBGF. */
1059	static DBGFREGDESC const g_aRegDesc[] =
1060	{
1061	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1062	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1063	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1064	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1065	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1066	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1067	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1068	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1069	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1070	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1071	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1072	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1073	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1074	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1075	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1076	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1077	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1078	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1079	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1080	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1081	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1082	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1083	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1084	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1085	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1086	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1087	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1088	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1089	DBGFREGDESC_TERMINATOR()
1090	};
1091
1092
1093	/**
1094	* @callback_method_impl{FNDBGFHANDLERDEV}
1095	*/
1096	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1097	{
1098	RT_NOREF(pszArgs);
1099	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1100	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1101
1102	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1103
1104	uint32_t const uId = ioapicGetId(pThis);
1105	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1106	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1107
1108	uint32_t const uVer = ioapicGetVersion(pThis);
1109	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1110	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1111	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1112	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1113
1114	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1115	{
1116	uint32_t const uArb = ioapicGetArb();
1117	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1118	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1119	}
1120
1121	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1122
1123	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1124	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1125
1126	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1127	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1128	{
1129	static const char * const s_apszDeliveryModes[] =
1130	{
1131	"Fixed ",
1132	"LowPri",
1133	"SMI ",
1134	"Rsvd ",
1135	"NMI ",
1136	"INIT ",
1137	"Rsvd ",
1138	"ExtINT"
1139	};
1140
1141	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1142	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1143	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1144	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1145	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1146	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1147	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1148	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1149	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1150	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1151	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1152	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1153
1154	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1155	idxRte,
1156	pszDestMode,
1157	uDest,
1158	uMask,
1159	(pThis->uIrr >> idxRte) & 1,
1160	pszTriggerMode,
1161	uRemoteIrr,
1162	pszPolarity,
1163	pszDeliveryStatus,
1164	pszDeliveryMode,
1165	uVector,
1166	u64Rte);
1167	}
1168	}
1169
1170
1171	/**
1172	* @copydoc FNSSMDEVSAVEEXEC
1173	*/
1174	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1175	{
1176	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1177	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1178	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1179
1180	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1181	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1182	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1183	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1184	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1185
1186	return VINF_SUCCESS;
1187	}
1188
1189
1190	/**
1191	* @copydoc FNSSMDEVLOADEXEC
1192	*/
1193	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1194	{
1195	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1196	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1197	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1198
1199	Assert(uPass == SSM_PASS_FINAL);
1200	NOREF(uPass);
1201
1202	/* Weed out invalid versions. */
1203	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1204	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1205	{
1206	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1207	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1208	}
1209
1210	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1211	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1212
1213	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1214	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1215	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1216	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1217
1218	return VINF_SUCCESS;
1219	}
1220
1221
1222	/**
1223	* @interface_method_impl{PDMDEVREG,pfnReset}
1224	*/
1225	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1226	{
1227	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1228	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1229	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1230
1231	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1232	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1233
1234	pThis->uIrr = 0;
1235	pThis->u8Index = 0;
1236	pThis->u8Id = 0;
1237
1238	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1239	{
1240	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1241	pThis->au32TagSrc[idxRte] = 0;
1242	}
1243
1244	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1245	}
1246
1247
1248	/**
1249	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1250	*/
1251	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1252	{
1253	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1254	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1255
1256	pThisRC->pIoApicHlp += offDelta;
1257	}
1258
1259
1260	/**
1261	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1262	*/
1263	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1264	{
1265	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1266	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1267	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1268
1269	# ifndef IOAPIC_WITH_PDM_CRITSECT
1270	/*
1271	* Destroy the RTE critical section.
1272	*/
1273	if (PDMCritSectIsInitialized(&pThis->CritSect))
1274	PDMR3CritSectDelete(&pThis->CritSect);
1275	# else
1276	RT_NOREF_PV(pThis);
1277	# endif
1278
1279	return VINF_SUCCESS;
1280	}
1281
1282
1283	/**
1284	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1285	*/
1286	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1287	{
1288	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1289	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1290	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1291	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1292	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1293	Assert(iInstance == 0); RT_NOREF(iInstance);
1294
1295	/*
1296	* Validate and read the configuration.
1297	*/
1298	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1299
1300	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1301	upsets some guest which we haven't yet tested. */
1302	uint32_t cCpus;
1303	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1304	if (RT_FAILURE(rc))
1305	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1306	pThis->cCpus = (uint8_t)cCpus;
1307
1308	char szChipType[16];
1309	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1310	if (RT_FAILURE(rc))
1311	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1312
1313	if (!strcmp(szChipType, "ICH9"))
1314	{
1315	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1316	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1317	pThis->u8IdMask = 0xff;
1318	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1319	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1320	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1321	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1322	}
1323	else if (!strcmp(szChipType, "82093AA"))
1324	{
1325	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1326	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1327	pThis->u8IdMask = 0x0f;
1328	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1329	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1330	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1331	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1332	}
1333	else if (!strcmp(szChipType, "82379AB"))
1334	{
1335	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1336	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1337	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1338	pThis->u8IdMask = 0x0f;
1339	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1340	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1341	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1342	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1343	}
1344	else
1345	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1346	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1347	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1348
1349	/*
1350	* We will use our own critical section for the IOAPIC device.
1351	*/
1352	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1353	AssertRCReturn(rc, rc);
1354
1355	# ifndef IOAPIC_WITH_PDM_CRITSECT
1356	/*
1357	* Setup the critical section to protect concurrent writes to the RTEs.
1358	*/
1359	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1360	AssertRCReturn(rc, rc);
1361	# endif
1362
1363	/*
1364	* Register the IOAPIC.
1365	*/
1366	PDMIOAPICREG IoApicReg;
1367	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1368	IoApicReg.pfnSetIrq = ioapicSetIrq;
1369	IoApicReg.pfnSendMsi = ioapicSendMsi;
1370	IoApicReg.pfnSetEoi = ioapicSetEoi;
1371	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1372	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1373	AssertRCReturn(rc, rc);
1374
1375	/*
1376	* Register MMIO region.
1377	*/
1378	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1379	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1380	AssertRCReturn(rc, rc);
1381
1382	/*
1383	* Register the saved state.
1384	*/
1385	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1386	AssertRCReturn(rc, rc);
1387
1388	/*
1389	* Register debugger info item.
1390	*/
1391	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1392	AssertRCReturn(rc, rc);
1393
1394	/*
1395	* Register debugger register access.
1396	*/
1397	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1398	AssertRCReturn(rc, rc);
1399
1400	# ifdef VBOX_WITH_STATISTICS
1401	/*
1402	* Statistics.
1403	*/
1404	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1405	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1406	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1407	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1408
1409	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1410	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1411	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1412	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1413
1414	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1415	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1416	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1417
1418	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1419	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1420
1421	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1422	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1423	# endif
1424
1425	/*
1426	* Init. the device state.
1427	*/
1428	LogRel(("IOAPIC: Using implementation 2.0! Chipset type %s\n", szChipType));
1429	ioapicR3Reset(pDevIns);
1430
1431	return VINF_SUCCESS;
1432	}
1433
1434	#else /* !IN_RING3 */
1435
1436	/**
1437	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1438	*/
1439	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1440	{
1441	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1442	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1443	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1444
1445	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1446	AssertRCReturn(rc, rc);
1447
1448	PDMIOAPICREG IoApicReg;
1449	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1450	IoApicReg.pfnSetIrq = ioapicSetIrq;
1451	IoApicReg.pfnSendMsi = ioapicSendMsi;
1452	IoApicReg.pfnSetEoi = ioapicSetEoi;
1453	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1454	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1455	AssertRCReturn(rc, rc);
1456
1457	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1458	AssertRCReturn(rc, rc);
1459
1460	return VINF_SUCCESS;
1461	}
1462
1463	#endif /* !IN_RING3 */
1464
1465	/**
1466	* IO APIC device registration structure.
1467	*/
1468	const PDMDEVREG g_DeviceIOAPIC =
1469	{
1470	/* .u32Version = */ PDM_DEVREG_VERSION,
1471	/* .uReserved0 = */ 0,
1472	/* .szName = */ "ioapic",
1473	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1474	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1475	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1476	/* .cMaxInstances = */ 1,
1477	/* .uSharedVersion = */ 42,
1478	/* .cbInstanceShared = */ sizeof(IOAPIC),
1479	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1480	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1481	/* .cMaxPciDevices = */ 0,
1482	/* .cMaxMsixVectors = */ 0,
1483	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1484	#if defined(IN_RING3)
1485	/* .pszRCMod = */ "VBoxDDRC.rc",
1486	/* .pszR0Mod = */ "VBoxDDR0.r0",
1487	/* .pfnConstruct = */ ioapicR3Construct,
1488	/* .pfnDestruct = */ ioapicR3Destruct,
1489	/* .pfnRelocate = */ ioapicR3Relocate,
1490	/* .pfnMemSetup = */ NULL,
1491	/* .pfnPowerOn = */ NULL,
1492	/* .pfnReset = */ ioapicR3Reset,
1493	/* .pfnSuspend = */ NULL,
1494	/* .pfnResume = */ NULL,
1495	/* .pfnAttach = */ NULL,
1496	/* .pfnDetach = */ NULL,
1497	/* .pfnQueryInterface = */ NULL,
1498	/* .pfnInitComplete = */ NULL,
1499	/* .pfnPowerOff = */ NULL,
1500	/* .pfnSoftReset = */ NULL,
1501	/* .pfnReserved0 = */ NULL,
1502	/* .pfnReserved1 = */ NULL,
1503	/* .pfnReserved2 = */ NULL,
1504	/* .pfnReserved3 = */ NULL,
1505	/* .pfnReserved4 = */ NULL,
1506	/* .pfnReserved5 = */ NULL,
1507	/* .pfnReserved6 = */ NULL,
1508	/* .pfnReserved7 = */ NULL,
1509	#elif defined(IN_RING0)
1510	/* .pfnEarlyConstruct = */ NULL,
1511	/* .pfnConstruct = */ ioapicRZConstruct,
1512	/* .pfnDestruct = */ NULL,
1513	/* .pfnFinalDestruct = */ NULL,
1514	/* .pfnRequest = */ NULL,
1515	/* .pfnReserved0 = */ NULL,
1516	/* .pfnReserved1 = */ NULL,
1517	/* .pfnReserved2 = */ NULL,
1518	/* .pfnReserved3 = */ NULL,
1519	/* .pfnReserved4 = */ NULL,
1520	/* .pfnReserved5 = */ NULL,
1521	/* .pfnReserved6 = */ NULL,
1522	/* .pfnReserved7 = */ NULL,
1523	#elif defined(IN_RC)
1524	/* .pfnConstruct = */ ioapicRZConstruct,
1525	/* .pfnReserved0 = */ NULL,
1526	/* .pfnReserved1 = */ NULL,
1527	/* .pfnReserved2 = */ NULL,
1528	/* .pfnReserved3 = */ NULL,
1529	/* .pfnReserved4 = */ NULL,
1530	/* .pfnReserved5 = */ NULL,
1531	/* .pfnReserved6 = */ NULL,
1532	/* .pfnReserved7 = */ NULL,
1533	#else
1534	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1535	#endif
1536	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1537	};
1538
1539
1540	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1541

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 84663

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