DevIoApic.cpp@ 84665

Last change on this file since 84665 was 84665, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 DevIoApic: Attempted burn fix.
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1	/* $Id: DevIoApic.cpp 84665 2020-06-03 13:30:23Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30	#include <iprt/string.h>
31
32
33	/*********************************************************************************************************************************
34	* Defined Constants And Macros *
35	*********************************************************************************************************************************/
36	/** The current IO APIC saved state version. */
37	#define IOAPIC_SAVED_STATE_VERSION 2
38	/** The saved state version used by VirtualBox 5.0 and
39	* earlier. */
40	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
41
42	/** Implementation specified by the "Intel I/O Controller Hub 9
43	* (ICH9) Family" */
44	#define IOAPIC_VERSION_ICH9 0x20
45	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
46	Controller" */
47	#define IOAPIC_VERSION_82093AA 0x11
48
49	/** The default MMIO base physical address. */
50	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
51	/** The size of the MMIO range. */
52	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
53	/** The mask for getting direct registers from physical address. */
54	#define IOAPIC_MMIO_REG_MASK 0xff
55
56	/** The number of interrupt input pins. */
57	#define IOAPIC_NUM_INTR_PINS 24
58	/** Maximum redirection entires. */
59	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
60	/** Reduced RTEs used by SIO.A (82379AB). */
61	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
62
63	/** Version register - Gets the version. */
64	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
65	/** Version register - Gets the maximum redirection entry. */
66	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
67	/** Version register - Gets whether Pin Assertion Register (PRQ) is
68	* supported. */
69	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
70
71	/** Index register - Valid write mask. */
72	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
73
74	/** Arbitration register - Gets the ID. */
75	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
76
77	/** ID register - Gets the ID. */
78	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
79
80	/** Redirection table entry - Vector. */
81	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
82	/** Redirection table entry - Delivery mode. */
83	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
84	/** Redirection table entry - Destination mode. */
85	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
86	/** Redirection table entry - Delivery status. */
87	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
88	/** Redirection table entry - Interrupt input pin polarity. */
89	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
90	/** Redirection table entry - Remote IRR. */
91	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
92	/** Redirection table entry - Trigger Mode. */
93	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
94	/** Redirection table entry - the mask bit number. */
95	#define IOAPIC_RTE_MASK_BIT 16
96	/** Redirection table entry - the mask. */
97	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
98	/** Redirection table entry - Extended Destination ID. */
99	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
100	/** Redirection table entry - Destination. */
101	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
102
103	/** Redirection table entry - Gets the destination. */
104	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
105	/** Redirection table entry - Gets the mask flag. */
106	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
107	/** Redirection table entry - Checks whether it's masked. */
108	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
109	/** Redirection table entry - Gets the trigger mode. */
110	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
111	/** Redirection table entry - Gets the remote IRR flag. */
112	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
113	/** Redirection table entry - Gets the interrupt pin polarity. */
114	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
115	/** Redirection table entry - Gets the delivery status. */
116	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
117	/** Redirection table entry - Gets the destination mode. */
118	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
119	/** Redirection table entry - Gets the delivery mode. */
120	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
121	/** Redirection table entry - Gets the vector. */
122	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
123
124	/** Redirection table entry - Valid write mask for 82093AA. */
125	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
126	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
127	\| IOAPIC_RTE_VECTOR)
128	/** Redirection table entry - Valid read mask for 82093AA. */
129	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
130	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
131	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
132
133	/** Redirection table entry - Valid write mask for ICH9. */
134	/** @note The remote IRR bit has been reverted to read-only as it turns out the
135	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
136	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
137	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
138	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
139	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
140	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
141	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
142	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
143	\| IOAPIC_RTE_VECTOR)
144
145	/** Redirection table entry - Trigger mode edge. */
146	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
147	/** Redirection table entry - Trigger mode level. */
148	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
149	/** Redirection table entry - Destination mode physical. */
150	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
151	/** Redirection table entry - Destination mode logical. */
152	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
153
154
155	/** Index of indirect registers in the I/O APIC register table. */
156	#define IOAPIC_INDIRECT_INDEX_ID 0x0
157	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
158	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
159	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
160	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
161	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
162
163	/** Offset of direct registers in the I/O APIC MMIO space. */
164	#define IOAPIC_DIRECT_OFF_INDEX 0x00
165	#define IOAPIC_DIRECT_OFF_DATA 0x10
166	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
167
168	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
169	#define IOAPIC_WITH_PDM_CRITSECT
170	#ifdef IOAPIC_WITH_PDM_CRITSECT
171	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
172	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
173	#else
174	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
175	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
176	#endif
177
178
179	/*********************************************************************************************************************************
180	* Structures and Typedefs *
181	*********************************************************************************************************************************/
182	/**
183	* The shared I/O APIC device state.
184	*/
185	typedef struct IOAPIC
186	{
187	/** The ID register. */
188	uint8_t volatile u8Id;
189	/** The index register. */
190	uint8_t volatile u8Index;
191	/** Number of CPUs. */
192	uint8_t cCpus;
193	/** I/O APIC version. */
194	uint8_t u8ApicVer;
195	/** I/O APIC ID mask. */
196	uint8_t u8IdMask;
197	/** Maximum Redirection Table Entry (RTE) Entry. */
198	uint8_t u8MaxRte;
199	/** Last valid RTE indirect register index. */
200	uint8_t u8LastRteRegIdx;
201	/* Alignment padding. */
202	uint8_t u8Padding0[1];
203	/** Redirection table entry - Valid write mask. */
204	uint64_t u64RteWriteMask;
205	/** Redirection table entry - Valid read mask. */
206	uint64_t u64RteReadMask;
207
208	/** The redirection table registers. */
209	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
210	/** The IRQ tags and source IDs for each pin (tracing purposes). */
211	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
212
213	/** The internal IRR reflecting state of the interrupt lines. */
214	uint32_t uIrr;
215	/** Alignment padding. */
216	uint32_t u32Padding2;
217
218	#ifndef IOAPIC_WITH_PDM_CRITSECT
219	/** The critsect for updating to the RTEs. */
220	PDMCRITSECT CritSect;
221	#endif
222
223	/** The MMIO region. */
224	IOMMMIOHANDLE hMmio;
225
226	#ifdef VBOX_WITH_STATISTICS
227	/** Number of MMIO reads in RZ. */
228	STAMCOUNTER StatMmioReadRZ;
229	/** Number of MMIO reads in R3. */
230	STAMCOUNTER StatMmioReadR3;
231
232	/** Number of MMIO writes in RZ. */
233	STAMCOUNTER StatMmioWriteRZ;
234	/** Number of MMIO writes in R3. */
235	STAMCOUNTER StatMmioWriteR3;
236
237	/** Number of SetIrq calls in RZ. */
238	STAMCOUNTER StatSetIrqRZ;
239	/** Number of SetIrq calls in R3. */
240	STAMCOUNTER StatSetIrqR3;
241
242	/** Number of SetEoi calls in RZ. */
243	STAMCOUNTER StatSetEoiRZ;
244	/** Number of SetEoi calls in R3. */
245	STAMCOUNTER StatSetEoiR3;
246
247	/** Number of redundant edge-triggered interrupts. */
248	STAMCOUNTER StatRedundantEdgeIntr;
249	/** Number of redundant level-triggered interrupts. */
250	STAMCOUNTER StatRedundantLevelIntr;
251	/** Number of suppressed level-triggered interrupts (by remote IRR). */
252	STAMCOUNTER StatSuppressedLevelIntr;
253	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
254	STAMCOUNTER StatEoiContention;
255	/** Number of returns to ring-3 due to Set RTE lock contention. */
256	STAMCOUNTER StatSetRteContention;
257	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
258	STAMCOUNTER StatLevelIrqSent;
259	/** Number of EOIs received for level-triggered interrupts from the local
260	* APIC(s). */
261	STAMCOUNTER StatEoiReceived;
262	#endif
263	} IOAPIC;
264	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
265	/** Pointer to shared IOAPIC data. */
266	typedef IOAPIC *PIOAPIC;
267	/** Pointer to const shared IOAPIC data. */
268	typedef IOAPIC const *PCIOAPIC;
269
270
271	/**
272	* The I/O APIC device state for ring-3.
273	*/
274	typedef struct IOAPICR3
275	{
276	/** The IOAPIC helpers. */
277	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
278	} IOAPICR3;
279	/** Pointer to the I/O APIC device state for ring-3. */
280	typedef IOAPICR3 *PIOAPICR3;
281
282
283	/**
284	* The I/O APIC device state for ring-0.
285	*/
286	typedef struct IOAPICR0
287	{
288	/** The IOAPIC helpers. */
289	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
290	} IOAPICR0;
291	/** Pointer to the I/O APIC device state for ring-0. */
292	typedef IOAPICR0 *PIOAPICR0;
293
294
295	/**
296	* The I/O APIC device state for raw-mode.
297	*/
298	typedef struct IOAPICRC
299	{
300	/** The IOAPIC helpers. */
301	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
302	} IOAPICRC;
303	/** Pointer to the I/O APIC device state for raw-mode. */
304	typedef IOAPICRC *PIOAPICRC;
305
306
307	/** The I/O APIC device state for the current context. */
308	typedef CTX_SUFF(IOAPIC) IOAPICCC;
309	/** Pointer to the I/O APIC device state for the current context. */
310	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
311
312
313	/**
314	* xAPIC interrupt.
315	*/
316	typedef struct XAPICINTR
317	{
318	/** The interrupt vector. */
319	uint8_t u8Vector;
320	/** The destination (mask or ID). */
321	uint8_t u8Dest;
322	/** The destination mode. */
323	uint8_t u8DestMode;
324	/** Delivery mode. */
325	uint8_t u8DeliveryMode;
326	/** Trigger mode. */
327	uint8_t u8TriggerMode;
328	/** Redirection hint. */
329	uint8_t u8RedirHint;
330	/** Polarity. */
331	uint8_t u8Polarity;
332	/** Padding. */
333	uint8_t abPadding0;
334	} XAPICINTR;
335	/** Pointer to an I/O xAPIC interrupt struct. */
336	typedef XAPICINTR *PXAPICINTR;
337	/** Pointer to a const xAPIC interrupt struct. */
338	typedef XAPICINTR const *PCXAPICINTR;
339
340
341	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
342
343	/**
344	* Gets the arbitration register.
345	*
346	* @returns The arbitration.
347	*/
348	DECLINLINE(uint32_t) ioapicGetArb(void)
349	{
350	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
351	return 0;
352	}
353
354
355	/**
356	* Gets the version register.
357	*
358	* @returns The version.
359	*/
360	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
361	{
362	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
363	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
364	return uValue;
365	}
366
367
368	/**
369	* Sets the ID register.
370	*
371	* @param pThis The shared I/O APIC device state.
372	* @param uValue The value to set.
373	*/
374	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
375	{
376	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
377	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
378	}
379
380
381	/**
382	* Gets the ID register.
383	*
384	* @returns The ID.
385	* @param pThis The shared I/O APIC device state.
386	*/
387	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
388	{
389	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
390	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
391	return uValue;
392	}
393
394
395	/**
396	* Sets the index register.
397	*
398	* @param pThis The shared I/O APIC device state.
399	* @param uValue The value to set.
400	*/
401	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
402	{
403	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
404	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
405	}
406
407
408	/**
409	* Gets the index register.
410	*
411	* @returns The index value.
412	*/
413	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
414	{
415	uint32_t const uValue = pThis->u8Index;
416	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
417	return uValue;
418	}
419
420
421	/**
422	* Converts an MSI message to an APIC interrupt.
423	*
424	* @param pMsi The MSI message to convert.
425	* @param pIntr Where to store the APIC interrupt.
426	*/
427	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
428	{
429	/*
430	* Parse the message from the physical address and data
431	* See Intel spec. 10.11.1 "Message Address Register Format".
432	* See Intel spec. 10.11.2 "Message Data Register Format".
433	*/
434	memset(pIntr, 0, sizeof(*pIntr));
435	pIntr->u8Dest = pMsi->MsiAddr.n.u8DestId;
436	pIntr->u8DestMode = pMsi->MsiAddr.n.u1DestMode;
437	pIntr->u8RedirHint = pMsi->MsiAddr.n.u1RedirHint;
438
439	pIntr->u8Vector = pMsi->MsiData.n.u8Vector;
440	pIntr->u8TriggerMode = pMsi->MsiData.n.u1TriggerMode;
441	pIntr->u8DeliveryMode = pMsi->MsiData.n.u3DeliveryMode;
442	}
443
444	#if 0
445	/**
446	* Convert an APIC interrupt to an MSI message.
447	*
448	* @param pIntr The APIC interrupt to convert.
449	* @param pMsi Where to store the MSI message.
450	*/
451	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
452	{
453	memset(pMsi, 0, sizeof(*pMsi));
454	pMsi->MsiAddr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
455	pMsi->MsiAddr.n.u8DestId = pIntr->u8Dest;
456	pMsi->MsiAddr.n.u1RedirHint = pIntr->u8RedirHint;
457	pMsi->MsiAddr.n.u1DestMode = pIntr->u8DestMode;
458
459	pMsi->MsiData.n.u8Vector = pIntr->u8Vector;
460	pMsi->MsiData.n.u3DeliveryMode = pIntr->u8DeliveryMode;
461	pMsi->MsiData.n.u1TriggerMode = pIntr->u8TriggerMode;
462
463	/* pMsi->MsiData.n.u1Level = ??? */
464	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
465	* possible in theory? Maybe document this more explicitly... */
466	}
467	#endif
468
469	/**
470	* Signals the next pending interrupt for the specified Redirection Table Entry
471	* (RTE).
472	*
473	* @param pDevIns The device instance.
474	* @param pThis The shared I/O APIC device state.
475	* @param pThisCC The I/O APIC device state for the current context.
476	* @param idxRte The index of the RTE (validated).
477	*
478	* @remarks It is the responsibility of the caller to verify that an interrupt is
479	* pending for the pin corresponding to the RTE before calling this
480	* function.
481	*/
482	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
483	{
484	#ifndef IOAPIC_WITH_PDM_CRITSECT
485	Assert(PDMCritSectIsOwner(&pThis->CritSect));
486	#endif
487
488	/* Ensure the RTE isn't masked. */
489	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
490	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
491	{
492	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
493	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
494	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
495	{
496	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
497	if (u8RemoteIrr)
498	{
499	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
500	return;
501	}
502	}
503
504	uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
505	uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
506	uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
507	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
508	uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
509	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
510
511	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
512	u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
513	u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
514
515	/*
516	* Deliver to the local APIC via the system/3-wire-APIC bus.
517	*/
518	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
519	u8Dest,
520	u8DestMode,
521	u8DeliveryMode,
522	u8Vector,
523	u8Polarity,
524	u8TriggerMode,
525	u32TagSrc);
526	/* Can't reschedule to R3. */
527	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
528	#ifdef DEBUG_ramshankar
529	if (rc == VERR_APIC_INTR_DISCARDED)
530	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
531	#endif
532
533	/*
534	* For level-triggered interrupts, we set the remote IRR bit to indicate
535	* the local APIC has accepted the interrupt.
536	*
537	* For edge-triggered interrupts, we should not clear the IRR bit as it
538	* should remain intact to reflect the state of the interrupt line.
539	* The device will explicitly transition to inactive state via the
540	* ioapicSetIrq() callback.
541	*/
542	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
543	&& rc == VINF_SUCCESS)
544	{
545	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
546	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
547	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
548	}
549	}
550	}
551
552
553	/**
554	* Gets the redirection table entry.
555	*
556	* @returns The redirection table entry.
557	* @param pThis The shared I/O APIC device state.
558	* @param uIndex The index value.
559	*/
560	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
561	{
562	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
563	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
564	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
565	UINT32_MAX);
566	uint32_t uValue;
567	if (!(uIndex & 1))
568	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
569	else
570	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
571
572	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
573	return uValue;
574	}
575
576
577	/**
578	* Sets the redirection table entry.
579	*
580	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
581	* @param pDevIns The device instance.
582	* @param pThis The shared I/O APIC device state.
583	* @param pThisCC The I/O APIC device state for the current context.
584	* @param uIndex The index value.
585	* @param uValue The value to set.
586	*/
587	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
588	uint32_t uIndex, uint32_t uValue)
589	{
590	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
591	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
592	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
593	VINF_SUCCESS);
594
595	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
596	if (rc == VINF_SUCCESS)
597	{
598	/*
599	* Write the low or high 32-bit value into the specified 64-bit RTE register,
600	* update only the valid, writable bits.
601	*
602	* We need to preserve the read-only bits as it can have dire consequences
603	* otherwise, see @bugref{8386#c24}.
604	*/
605	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
606	if (!(uIndex & 1))
607	{
608	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
609	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
610	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
611	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
612	}
613	else
614	{
615	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
616	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
617	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
618	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
619	}
620
621	/*
622	* Signal the next pending interrupt for this RTE.
623	*/
624	uint32_t const uPinMask = UINT32_C(1) << idxRte;
625	if (pThis->uIrr & uPinMask)
626	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
627
628	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
629	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
630	}
631	else
632	STAM_COUNTER_INC(&pThis->StatSetRteContention);
633
634	return rc;
635	}
636
637
638	/**
639	* Gets the data register.
640	*
641	* @returns The data value.
642	* @param pThis The shared I/O APIC device state.
643	*/
644	static uint32_t ioapicGetData(PCIOAPIC pThis)
645	{
646	uint8_t const uIndex = pThis->u8Index;
647	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
648	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
649	&& uIndex <= pThis->u8LastRteRegIdx)
650	return ioapicGetRedirTableEntry(pThis, uIndex);
651
652	uint32_t uValue;
653	switch (uIndex)
654	{
655	case IOAPIC_INDIRECT_INDEX_ID:
656	uValue = ioapicGetId(pThis);
657	break;
658
659	case IOAPIC_INDIRECT_INDEX_VERSION:
660	uValue = ioapicGetVersion(pThis);
661	break;
662
663	case IOAPIC_INDIRECT_INDEX_ARB:
664	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
665	{
666	uValue = ioapicGetArb();
667	break;
668	}
669	RT_FALL_THRU();
670
671	default:
672	uValue = UINT32_C(0xffffffff);
673	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
674	break;
675	}
676	return uValue;
677	}
678
679
680	/**
681	* Sets the data register.
682	*
683	* @returns Strict VBox status code.
684	* @param pDevIns The device instance.
685	* @param pThis The shared I/O APIC device state.
686	* @param pThisCC The I/O APIC device state for the current context.
687	* @param uValue The value to set.
688	*/
689	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
690	{
691	uint8_t const uIndex = pThis->u8Index;
692	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
693	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
694
695	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
696	&& uIndex <= pThis->u8LastRteRegIdx)
697	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
698
699	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
700	ioapicSetId(pThis, uValue);
701	else
702	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
703
704	return VINF_SUCCESS;
705	}
706
707
708	/**
709	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
710	*/
711	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
712	{
713	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
714	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
715	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
716	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
717
718	bool fRemoteIrrCleared = false;
719	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
720	if (rc == VINF_SUCCESS)
721	{
722	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
723	{
724	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
725	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
726	{
727	#ifdef DEBUG_ramshankar
728	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
729	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
730	#endif
731	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
732	fRemoteIrrCleared = true;
733	STAM_COUNTER_INC(&pThis->StatEoiReceived);
734	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
735
736	/*
737	* Signal the next pending interrupt for this RTE.
738	*/
739	uint32_t const uPinMask = UINT32_C(1) << idxRte;
740	if (pThis->uIrr & uPinMask)
741	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
742	}
743	}
744
745	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
746	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
747	}
748	else
749	STAM_COUNTER_INC(&pThis->StatEoiContention);
750
751	return rc;
752	}
753
754
755	/**
756	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
757	*/
758	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
759	{
760	#define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) do { \
761	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
762	pThis->uIrr \|= a_PinMask; \
763	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
764	} while (0)
765
766	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
767	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
768	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
769
770	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
771
772	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
773	{
774	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
775	AssertRC(rc);
776
777	uint8_t const idxRte = iIrq;
778	uint32_t const uPinMask = UINT32_C(1) << idxRte;
779	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
780	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
781
782	bool fActive = RT_BOOL(iLevel & 1);
783	/** @todo Polarity is busted elsewhere, we need to fix that
784	* first. See @bugref{8386#c7}. */
785	#if 0
786	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
787	fActive ^= u8Polarity; */
788	#endif
789	if (!fActive)
790	{
791	pThis->uIrr &= ~uPinMask;
792	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
793	return;
794	}
795
796	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
797	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
798	if (!fFlipFlop)
799	{
800	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
801	{
802	/*
803	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
804	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
805	*/
806	if (!uPrevIrr)
807	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
808	else
809	{
810	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
811	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
812	}
813	}
814	else
815	{
816	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
817
818	/*
819	* For level-triggered interrupts, redundant interrupts are not a problem
820	* and will eventually be delivered anyway after an EOI, but our PDM devices
821	* should not typically call us with no change to the level.
822	*/
823	if (!uPrevIrr)
824	{ /* likely */ }
825	else
826	{
827	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
828	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
829	}
830
831	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
832	}
833	}
834	else
835	{
836	/*
837	* The device is flip-flopping the interrupt line, which implies we should de-assert
838	* and assert the interrupt line. The interrupt line is left in the asserted state
839	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
840	* hence just the assert is done.
841	*/
842	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
843	}
844
845	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
846	}
847	#undef IOAPIC_ASSERT_IRQ
848	}
849
850
851	/**
852	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
853	*/
854	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
855	{
856	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
857	LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
858
859	MSIMSG MsiMsg;
860	MsiMsg.MsiAddr.u64 = GCPhys;
861	MsiMsg.MsiData.u32 = uValue;
862
863	XAPICINTR ApicIntr;
864	ioapicGetApicIntrFromMsi(&MsiMsg, &ApicIntr);
865
866	/*
867	* Deliver to the local APIC via the system/3-wire-APIC bus.
868	*/
869	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
870	ApicIntr.u8Dest,
871	ApicIntr.u8DestMode,
872	ApicIntr.u8DeliveryMode,
873	ApicIntr.u8Vector,
874	0 /* u8Polarity - N/A */,
875	ApicIntr.u8TriggerMode,
876	uTagSrc);
877	/* Can't reschedule to R3. */
878	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
879	}
880
881
882	/**
883	* @callback_method_impl{FNIOMMMIONEWREAD}
884	*/
885	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
886	{
887	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
888	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
889	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
890	RT_NOREF_PV(pvUser);
891
892	VBOXSTRICTRC rc = VINF_SUCCESS;
893	uint32_t puValue = (uint32_t )pv;
894	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
895	switch (offReg)
896	{
897	case IOAPIC_DIRECT_OFF_INDEX:
898	*puValue = ioapicGetIndex(pThis);
899	break;
900
901	case IOAPIC_DIRECT_OFF_DATA:
902	*puValue = ioapicGetData(pThis);
903	break;
904
905	default:
906	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
907	rc = VINF_IOM_MMIO_UNUSED_FF;
908	break;
909	}
910
911	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
912	return rc;
913	}
914
915
916	/**
917	* @callback_method_impl{FNIOMMMIONEWWRITE}
918	*/
919	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
920	{
921	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
922	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
923	RT_NOREF_PV(pvUser);
924
925	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
926
927	Assert(!(off & 3));
928	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
929
930	VBOXSTRICTRC rc = VINF_SUCCESS;
931	uint32_t const uValue = (uint32_t const )pv;
932	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
933
934	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
935	switch (offReg)
936	{
937	case IOAPIC_DIRECT_OFF_INDEX:
938	ioapicSetIndex(pThis, uValue);
939	break;
940
941	case IOAPIC_DIRECT_OFF_DATA:
942	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
943	break;
944
945	case IOAPIC_DIRECT_OFF_EOI:
946	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
947	rc = ioapicSetEoi(pDevIns, uValue);
948	else
949	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
950	break;
951
952	default:
953	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
954	break;
955	}
956
957	return rc;
958	}
959
960
961	#ifdef IN_RING3
962
963	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
964	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
965	{
966	RT_NOREF(pDesc);
967	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
968	return VINF_SUCCESS;
969	}
970
971
972	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
973	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
974	{
975	RT_NOREF(pDesc, pfMask);
976	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
977	return VINF_SUCCESS;
978	}
979
980
981	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
982	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
983	{
984	RT_NOREF(pDesc);
985	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
986	return VINF_SUCCESS;
987	}
988
989
990	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
991	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
992	{
993	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
994	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
995	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
996	RT_NOREF(pDesc, pfMask);
997	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
998	}
999
1000
1001	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1002	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1003	{
1004	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1005	RT_NOREF(pDesc);
1006	pValue->u32 = ioapicGetVersion(pThis);
1007	return VINF_SUCCESS;
1008	}
1009
1010
1011	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1012	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1013	{
1014	RT_NOREF(pvUser, pDesc);
1015	pValue->u32 = ioapicGetArb();
1016	return VINF_SUCCESS;
1017	}
1018
1019
1020	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1021	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1022	{
1023	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1024	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1025	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1026	return VINF_SUCCESS;
1027	}
1028
1029
1030	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1031	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1032	{
1033	RT_NOREF(pfMask);
1034	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1035	/* No locks, no checks, just do it. */
1036	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1037	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1038	return VINF_SUCCESS;
1039	}
1040
1041
1042	/** IOREDTBLn sub fields. */
1043	static DBGFREGSUBFIELD const g_aRteSubs[] =
1044	{
1045	{ "vector", 0, 8, 0, 0, NULL, NULL },
1046	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1047	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1048	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1049	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1050	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1051	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1052	{ "mask", 16, 1, 0, 0, NULL, NULL },
1053	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1054	{ "dest", 56, 8, 0, 0, NULL, NULL },
1055	DBGFREGSUBFIELD_TERMINATOR()
1056	};
1057
1058
1059	/** Register descriptors for DBGF. */
1060	static DBGFREGDESC const g_aRegDesc[] =
1061	{
1062	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1063	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1064	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1065	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1066	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1067	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1068	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1069	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1070	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1071	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1072	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1073	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1074	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1075	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1076	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1077	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1078	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1079	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1080	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1081	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1082	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1083	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1084	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1085	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1086	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1087	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1088	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1089	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1090	DBGFREGDESC_TERMINATOR()
1091	};
1092
1093
1094	/**
1095	* @callback_method_impl{FNDBGFHANDLERDEV}
1096	*/
1097	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1098	{
1099	RT_NOREF(pszArgs);
1100	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1101	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1102
1103	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1104
1105	uint32_t const uId = ioapicGetId(pThis);
1106	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1107	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1108
1109	uint32_t const uVer = ioapicGetVersion(pThis);
1110	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1111	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1112	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1113	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1114
1115	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1116	{
1117	uint32_t const uArb = ioapicGetArb();
1118	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1119	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1120	}
1121
1122	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1123
1124	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1125	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1126
1127	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1128	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1129	{
1130	static const char * const s_apszDeliveryModes[] =
1131	{
1132	"Fixed ",
1133	"LowPri",
1134	"SMI ",
1135	"Rsvd ",
1136	"NMI ",
1137	"INIT ",
1138	"Rsvd ",
1139	"ExtINT"
1140	};
1141
1142	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1143	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1144	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1145	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1146	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1147	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1148	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1149	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1150	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1151	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1152	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1153	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1154
1155	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1156	idxRte,
1157	pszDestMode,
1158	uDest,
1159	uMask,
1160	(pThis->uIrr >> idxRte) & 1,
1161	pszTriggerMode,
1162	uRemoteIrr,
1163	pszPolarity,
1164	pszDeliveryStatus,
1165	pszDeliveryMode,
1166	uVector,
1167	u64Rte);
1168	}
1169	}
1170
1171
1172	/**
1173	* @copydoc FNSSMDEVSAVEEXEC
1174	*/
1175	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1176	{
1177	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1178	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1179	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1180
1181	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1182	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1183	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1184	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1185	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1186
1187	return VINF_SUCCESS;
1188	}
1189
1190
1191	/**
1192	* @copydoc FNSSMDEVLOADEXEC
1193	*/
1194	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1195	{
1196	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1197	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1198	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1199
1200	Assert(uPass == SSM_PASS_FINAL);
1201	NOREF(uPass);
1202
1203	/* Weed out invalid versions. */
1204	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1205	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1206	{
1207	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1208	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1209	}
1210
1211	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1212	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1213
1214	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1215	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1216	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1217	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1218
1219	return VINF_SUCCESS;
1220	}
1221
1222
1223	/**
1224	* @interface_method_impl{PDMDEVREG,pfnReset}
1225	*/
1226	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1227	{
1228	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1229	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1230	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1231
1232	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1233	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1234
1235	pThis->uIrr = 0;
1236	pThis->u8Index = 0;
1237	pThis->u8Id = 0;
1238
1239	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1240	{
1241	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1242	pThis->au32TagSrc[idxRte] = 0;
1243	}
1244
1245	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1246	}
1247
1248
1249	/**
1250	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1251	*/
1252	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1253	{
1254	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1255	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1256
1257	pThisRC->pIoApicHlp += offDelta;
1258	}
1259
1260
1261	/**
1262	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1263	*/
1264	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1265	{
1266	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1267	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1268	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1269
1270	# ifndef IOAPIC_WITH_PDM_CRITSECT
1271	/*
1272	* Destroy the RTE critical section.
1273	*/
1274	if (PDMCritSectIsInitialized(&pThis->CritSect))
1275	PDMR3CritSectDelete(&pThis->CritSect);
1276	# else
1277	RT_NOREF_PV(pThis);
1278	# endif
1279
1280	return VINF_SUCCESS;
1281	}
1282
1283
1284	/**
1285	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1286	*/
1287	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1288	{
1289	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1290	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1291	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1292	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1293	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1294	Assert(iInstance == 0); RT_NOREF(iInstance);
1295
1296	/*
1297	* Validate and read the configuration.
1298	*/
1299	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1300
1301	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1302	upsets some guest which we haven't yet tested. */
1303	uint32_t cCpus;
1304	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1305	if (RT_FAILURE(rc))
1306	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1307	pThis->cCpus = (uint8_t)cCpus;
1308
1309	char szChipType[16];
1310	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1311	if (RT_FAILURE(rc))
1312	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1313
1314	if (!strcmp(szChipType, "ICH9"))
1315	{
1316	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1317	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1318	pThis->u8IdMask = 0xff;
1319	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1320	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1321	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1322	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1323	}
1324	else if (!strcmp(szChipType, "82093AA"))
1325	{
1326	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1327	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1328	pThis->u8IdMask = 0x0f;
1329	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1330	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1331	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1332	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1333	}
1334	else if (!strcmp(szChipType, "82379AB"))
1335	{
1336	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1337	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1338	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1339	pThis->u8IdMask = 0x0f;
1340	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1341	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1342	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1343	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1344	}
1345	else
1346	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1347	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1348	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1349
1350	/*
1351	* We will use our own critical section for the IOAPIC device.
1352	*/
1353	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1354	AssertRCReturn(rc, rc);
1355
1356	# ifndef IOAPIC_WITH_PDM_CRITSECT
1357	/*
1358	* Setup the critical section to protect concurrent writes to the RTEs.
1359	*/
1360	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1361	AssertRCReturn(rc, rc);
1362	# endif
1363
1364	/*
1365	* Register the IOAPIC.
1366	*/
1367	PDMIOAPICREG IoApicReg;
1368	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1369	IoApicReg.pfnSetIrq = ioapicSetIrq;
1370	IoApicReg.pfnSendMsi = ioapicSendMsi;
1371	IoApicReg.pfnSetEoi = ioapicSetEoi;
1372	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1373	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1374	AssertRCReturn(rc, rc);
1375
1376	/*
1377	* Register MMIO region.
1378	*/
1379	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1380	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1381	AssertRCReturn(rc, rc);
1382
1383	/*
1384	* Register the saved state.
1385	*/
1386	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1387	AssertRCReturn(rc, rc);
1388
1389	/*
1390	* Register debugger info item.
1391	*/
1392	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1393	AssertRCReturn(rc, rc);
1394
1395	/*
1396	* Register debugger register access.
1397	*/
1398	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1399	AssertRCReturn(rc, rc);
1400
1401	# ifdef VBOX_WITH_STATISTICS
1402	/*
1403	* Statistics.
1404	*/
1405	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1406	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1407	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1408	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1409
1410	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1411	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1412	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1413	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1414
1415	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1416	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1417	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1418
1419	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1420	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1421
1422	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1423	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1424	# endif
1425
1426	/*
1427	* Init. the device state.
1428	*/
1429	LogRel(("IOAPIC: Using implementation 2.0! Chipset type %s\n", szChipType));
1430	ioapicR3Reset(pDevIns);
1431
1432	return VINF_SUCCESS;
1433	}
1434
1435	#else /* !IN_RING3 */
1436
1437	/**
1438	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1439	*/
1440	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1441	{
1442	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1443	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1444	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1445
1446	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1447	AssertRCReturn(rc, rc);
1448
1449	PDMIOAPICREG IoApicReg;
1450	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1451	IoApicReg.pfnSetIrq = ioapicSetIrq;
1452	IoApicReg.pfnSendMsi = ioapicSendMsi;
1453	IoApicReg.pfnSetEoi = ioapicSetEoi;
1454	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1455	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1456	AssertRCReturn(rc, rc);
1457
1458	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1459	AssertRCReturn(rc, rc);
1460
1461	return VINF_SUCCESS;
1462	}
1463
1464	#endif /* !IN_RING3 */
1465
1466	/**
1467	* IO APIC device registration structure.
1468	*/
1469	const PDMDEVREG g_DeviceIOAPIC =
1470	{
1471	/* .u32Version = */ PDM_DEVREG_VERSION,
1472	/* .uReserved0 = */ 0,
1473	/* .szName = */ "ioapic",
1474	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1475	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1476	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1477	/* .cMaxInstances = */ 1,
1478	/* .uSharedVersion = */ 42,
1479	/* .cbInstanceShared = */ sizeof(IOAPIC),
1480	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1481	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1482	/* .cMaxPciDevices = */ 0,
1483	/* .cMaxMsixVectors = */ 0,
1484	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1485	#if defined(IN_RING3)
1486	/* .pszRCMod = */ "VBoxDDRC.rc",
1487	/* .pszR0Mod = */ "VBoxDDR0.r0",
1488	/* .pfnConstruct = */ ioapicR3Construct,
1489	/* .pfnDestruct = */ ioapicR3Destruct,
1490	/* .pfnRelocate = */ ioapicR3Relocate,
1491	/* .pfnMemSetup = */ NULL,
1492	/* .pfnPowerOn = */ NULL,
1493	/* .pfnReset = */ ioapicR3Reset,
1494	/* .pfnSuspend = */ NULL,
1495	/* .pfnResume = */ NULL,
1496	/* .pfnAttach = */ NULL,
1497	/* .pfnDetach = */ NULL,
1498	/* .pfnQueryInterface = */ NULL,
1499	/* .pfnInitComplete = */ NULL,
1500	/* .pfnPowerOff = */ NULL,
1501	/* .pfnSoftReset = */ NULL,
1502	/* .pfnReserved0 = */ NULL,
1503	/* .pfnReserved1 = */ NULL,
1504	/* .pfnReserved2 = */ NULL,
1505	/* .pfnReserved3 = */ NULL,
1506	/* .pfnReserved4 = */ NULL,
1507	/* .pfnReserved5 = */ NULL,
1508	/* .pfnReserved6 = */ NULL,
1509	/* .pfnReserved7 = */ NULL,
1510	#elif defined(IN_RING0)
1511	/* .pfnEarlyConstruct = */ NULL,
1512	/* .pfnConstruct = */ ioapicRZConstruct,
1513	/* .pfnDestruct = */ NULL,
1514	/* .pfnFinalDestruct = */ NULL,
1515	/* .pfnRequest = */ NULL,
1516	/* .pfnReserved0 = */ NULL,
1517	/* .pfnReserved1 = */ NULL,
1518	/* .pfnReserved2 = */ NULL,
1519	/* .pfnReserved3 = */ NULL,
1520	/* .pfnReserved4 = */ NULL,
1521	/* .pfnReserved5 = */ NULL,
1522	/* .pfnReserved6 = */ NULL,
1523	/* .pfnReserved7 = */ NULL,
1524	#elif defined(IN_RC)
1525	/* .pfnConstruct = */ ioapicRZConstruct,
1526	/* .pfnReserved0 = */ NULL,
1527	/* .pfnReserved1 = */ NULL,
1528	/* .pfnReserved2 = */ NULL,
1529	/* .pfnReserved3 = */ NULL,
1530	/* .pfnReserved4 = */ NULL,
1531	/* .pfnReserved5 = */ NULL,
1532	/* .pfnReserved6 = */ NULL,
1533	/* .pfnReserved7 = */ NULL,
1534	#else
1535	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1536	#endif
1537	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1538	};
1539
1540
1541	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1542

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 84665

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