DevIoApic.cpp@ 84859

Last change on this file since 84859 was 84859, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 DevIoApic: Remap MSIs via the IOMMU before calling into the APIC.
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1	/* $Id: DevIoApic.cpp 84859 2020-06-17 09:12:19Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30	#include <iprt/string.h>
31
32
33	/*********************************************************************************************************************************
34	* Defined Constants And Macros *
35	*********************************************************************************************************************************/
36	/** The current IO APIC saved state version. */
37	#define IOAPIC_SAVED_STATE_VERSION 2
38	/** The saved state version used by VirtualBox 5.0 and
39	* earlier. */
40	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
41
42	/** Implementation specified by the "Intel I/O Controller Hub 9
43	* (ICH9) Family" */
44	#define IOAPIC_VERSION_ICH9 0x20
45	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
46	Controller" */
47	#define IOAPIC_VERSION_82093AA 0x11
48
49	/** The default MMIO base physical address. */
50	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
51	/** The size of the MMIO range. */
52	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
53	/** The mask for getting direct registers from physical address. */
54	#define IOAPIC_MMIO_REG_MASK 0xff
55
56	/** The number of interrupt input pins. */
57	#define IOAPIC_NUM_INTR_PINS 24
58	/** Maximum redirection entires. */
59	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
60	/** Reduced RTEs used by SIO.A (82379AB). */
61	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
62
63	/** Version register - Gets the version. */
64	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
65	/** Version register - Gets the maximum redirection entry. */
66	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
67	/** Version register - Gets whether Pin Assertion Register (PRQ) is
68	* supported. */
69	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
70
71	/** Index register - Valid write mask. */
72	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
73
74	/** Arbitration register - Gets the ID. */
75	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
76
77	/** ID register - Gets the ID. */
78	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
79
80	/** Redirection table entry - Vector. */
81	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
82	/** Redirection table entry - Delivery mode. */
83	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
84	/** Redirection table entry - Destination mode. */
85	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
86	/** Redirection table entry - Delivery status. */
87	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
88	/** Redirection table entry - Interrupt input pin polarity. */
89	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
90	/** Redirection table entry - Remote IRR. */
91	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
92	/** Redirection table entry - Trigger Mode. */
93	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
94	/** Redirection table entry - the mask bit number. */
95	#define IOAPIC_RTE_MASK_BIT 16
96	/** Redirection table entry - the mask. */
97	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
98	/** Redirection table entry - Extended Destination ID. */
99	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
100	/** Redirection table entry - Destination. */
101	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
102
103	/** Redirection table entry - Gets the destination. */
104	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
105	/** Redirection table entry - Gets the mask flag. */
106	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
107	/** Redirection table entry - Checks whether it's masked. */
108	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
109	/** Redirection table entry - Gets the trigger mode. */
110	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
111	/** Redirection table entry - Gets the remote IRR flag. */
112	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
113	/** Redirection table entry - Gets the interrupt pin polarity. */
114	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
115	/** Redirection table entry - Gets the delivery status. */
116	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
117	/** Redirection table entry - Gets the destination mode. */
118	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
119	/** Redirection table entry - Gets the delivery mode. */
120	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
121	/** Redirection table entry - Gets the vector. */
122	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
123
124	/** Redirection table entry - Valid write mask for 82093AA. */
125	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
126	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
127	\| IOAPIC_RTE_VECTOR)
128	/** Redirection table entry - Valid read mask for 82093AA. */
129	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
130	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
131	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
132
133	/** Redirection table entry - Valid write mask for ICH9. */
134	/** @note The remote IRR bit has been reverted to read-only as it turns out the
135	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
136	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
137	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
138	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
139	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
140	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
141	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
142	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
143	\| IOAPIC_RTE_VECTOR)
144
145	/** Redirection table entry - Trigger mode edge. */
146	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
147	/** Redirection table entry - Trigger mode level. */
148	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
149	/** Redirection table entry - Destination mode physical. */
150	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
151	/** Redirection table entry - Destination mode logical. */
152	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
153
154
155	/** Index of indirect registers in the I/O APIC register table. */
156	#define IOAPIC_INDIRECT_INDEX_ID 0x0
157	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
158	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
159	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
160	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
161	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
162
163	/** Offset of direct registers in the I/O APIC MMIO space. */
164	#define IOAPIC_DIRECT_OFF_INDEX 0x00
165	#define IOAPIC_DIRECT_OFF_DATA 0x10
166	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
167
168	/** The I/O APIC's Bus:Device:Function. */
169	#define IOAPIC_BUS_DEV_FN NIL_PCIBDF
170
171	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
172	#define IOAPIC_WITH_PDM_CRITSECT
173	#ifdef IOAPIC_WITH_PDM_CRITSECT
174	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
175	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
176	#else
177	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
178	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
179	#endif
180
181
182	/*********************************************************************************************************************************
183	* Structures and Typedefs *
184	*********************************************************************************************************************************/
185	/**
186	* The shared I/O APIC device state.
187	*/
188	typedef struct IOAPIC
189	{
190	/** The ID register. */
191	uint8_t volatile u8Id;
192	/** The index register. */
193	uint8_t volatile u8Index;
194	/** Number of CPUs. */
195	uint8_t cCpus;
196	/** I/O APIC version. */
197	uint8_t u8ApicVer;
198	/** I/O APIC ID mask. */
199	uint8_t u8IdMask;
200	/** Maximum Redirection Table Entry (RTE) Entry. */
201	uint8_t u8MaxRte;
202	/** Last valid RTE indirect register index. */
203	uint8_t u8LastRteRegIdx;
204	/* Alignment padding. */
205	uint8_t u8Padding0[1];
206	/** Redirection table entry - Valid write mask. */
207	uint64_t u64RteWriteMask;
208	/** Redirection table entry - Valid read mask. */
209	uint64_t u64RteReadMask;
210
211	/** The redirection table registers. */
212	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
213	/** The IRQ tags and source IDs for each pin (tracing purposes). */
214	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
215
216	/** The internal IRR reflecting state of the interrupt lines. */
217	uint32_t uIrr;
218	/** Alignment padding. */
219	uint32_t u32Padding2;
220
221	#ifndef IOAPIC_WITH_PDM_CRITSECT
222	/** The critsect for updating to the RTEs. */
223	PDMCRITSECT CritSect;
224	#endif
225
226	/** The MMIO region. */
227	IOMMMIOHANDLE hMmio;
228
229	#ifdef VBOX_WITH_STATISTICS
230	/** Number of MMIO reads in RZ. */
231	STAMCOUNTER StatMmioReadRZ;
232	/** Number of MMIO reads in R3. */
233	STAMCOUNTER StatMmioReadR3;
234
235	/** Number of MMIO writes in RZ. */
236	STAMCOUNTER StatMmioWriteRZ;
237	/** Number of MMIO writes in R3. */
238	STAMCOUNTER StatMmioWriteR3;
239
240	/** Number of SetIrq calls in RZ. */
241	STAMCOUNTER StatSetIrqRZ;
242	/** Number of SetIrq calls in R3. */
243	STAMCOUNTER StatSetIrqR3;
244
245	/** Number of SetEoi calls in RZ. */
246	STAMCOUNTER StatSetEoiRZ;
247	/** Number of SetEoi calls in R3. */
248	STAMCOUNTER StatSetEoiR3;
249
250	/** Number of redundant edge-triggered interrupts. */
251	STAMCOUNTER StatRedundantEdgeIntr;
252	/** Number of redundant level-triggered interrupts. */
253	STAMCOUNTER StatRedundantLevelIntr;
254	/** Number of suppressed level-triggered interrupts (by remote IRR). */
255	STAMCOUNTER StatSuppressedLevelIntr;
256	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
257	STAMCOUNTER StatEoiContention;
258	/** Number of returns to ring-3 due to Set RTE lock contention. */
259	STAMCOUNTER StatSetRteContention;
260	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
261	STAMCOUNTER StatLevelIrqSent;
262	/** Number of EOIs received for level-triggered interrupts from the local
263	* APIC(s). */
264	STAMCOUNTER StatEoiReceived;
265	#endif
266	} IOAPIC;
267	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
268	/** Pointer to shared IOAPIC data. */
269	typedef IOAPIC *PIOAPIC;
270	/** Pointer to const shared IOAPIC data. */
271	typedef IOAPIC const *PCIOAPIC;
272
273
274	/**
275	* The I/O APIC device state for ring-3.
276	*/
277	typedef struct IOAPICR3
278	{
279	/** The IOAPIC helpers. */
280	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
281	} IOAPICR3;
282	/** Pointer to the I/O APIC device state for ring-3. */
283	typedef IOAPICR3 *PIOAPICR3;
284
285
286	/**
287	* The I/O APIC device state for ring-0.
288	*/
289	typedef struct IOAPICR0
290	{
291	/** The IOAPIC helpers. */
292	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
293	} IOAPICR0;
294	/** Pointer to the I/O APIC device state for ring-0. */
295	typedef IOAPICR0 *PIOAPICR0;
296
297
298	/**
299	* The I/O APIC device state for raw-mode.
300	*/
301	typedef struct IOAPICRC
302	{
303	/** The IOAPIC helpers. */
304	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
305	} IOAPICRC;
306	/** Pointer to the I/O APIC device state for raw-mode. */
307	typedef IOAPICRC *PIOAPICRC;
308
309
310	/** The I/O APIC device state for the current context. */
311	typedef CTX_SUFF(IOAPIC) IOAPICCC;
312	/** Pointer to the I/O APIC device state for the current context. */
313	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
314
315
316	/**
317	* xAPIC interrupt.
318	*/
319	typedef struct XAPICINTR
320	{
321	/** The interrupt vector. */
322	uint8_t u8Vector;
323	/** The destination (mask or ID). */
324	uint8_t u8Dest;
325	/** The destination mode. */
326	uint8_t u8DestMode;
327	/** Delivery mode. */
328	uint8_t u8DeliveryMode;
329	/** Trigger mode. */
330	uint8_t u8TriggerMode;
331	/** Redirection hint. */
332	uint8_t u8RedirHint;
333	/** Polarity. */
334	uint8_t u8Polarity;
335	/** Padding. */
336	uint8_t abPadding0;
337	} XAPICINTR;
338	/** Pointer to an I/O xAPIC interrupt struct. */
339	typedef XAPICINTR *PXAPICINTR;
340	/** Pointer to a const xAPIC interrupt struct. */
341	typedef XAPICINTR const *PCXAPICINTR;
342
343
344	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
345
346	/**
347	* Gets the arbitration register.
348	*
349	* @returns The arbitration.
350	*/
351	DECLINLINE(uint32_t) ioapicGetArb(void)
352	{
353	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
354	return 0;
355	}
356
357
358	/**
359	* Gets the version register.
360	*
361	* @returns The version.
362	*/
363	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
364	{
365	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
366	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
367	return uValue;
368	}
369
370
371	/**
372	* Sets the ID register.
373	*
374	* @param pThis The shared I/O APIC device state.
375	* @param uValue The value to set.
376	*/
377	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
378	{
379	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
380	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
381	}
382
383
384	/**
385	* Gets the ID register.
386	*
387	* @returns The ID.
388	* @param pThis The shared I/O APIC device state.
389	*/
390	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
391	{
392	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
393	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
394	return uValue;
395	}
396
397
398	/**
399	* Sets the index register.
400	*
401	* @param pThis The shared I/O APIC device state.
402	* @param uValue The value to set.
403	*/
404	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
405	{
406	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
407	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
408	}
409
410
411	/**
412	* Gets the index register.
413	*
414	* @returns The index value.
415	*/
416	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
417	{
418	uint32_t const uValue = pThis->u8Index;
419	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
420	return uValue;
421	}
422
423
424	/**
425	* Converts an MSI message to an APIC interrupt.
426	*
427	* @param pMsi The MSI message to convert.
428	* @param pIntr Where to store the APIC interrupt.
429	*/
430	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
431	{
432	/*
433	* Parse the message from the physical address and data
434	* See Intel spec. 10.11.1 "Message Address Register Format".
435	* See Intel spec. 10.11.2 "Message Data Register Format".
436	*/
437	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
438	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
439	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
440
441	pIntr->u8Vector = pMsi->Data.n.u8Vector;
442	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
443	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
444	}
445
446	#if 0
447	/**
448	* Convert an APIC interrupt to an MSI message.
449	*
450	* @param pIntr The APIC interrupt to convert.
451	* @param pMsi Where to store the MSI message.
452	*/
453	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
454	{
455	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
456	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
457	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
458	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
459
460	pMsi->Data.n.u8Vector = pIntr->u8Vector;
461	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
462	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
463
464	/* pMsi->Data.n.u1Level = ??? */
465	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
466	* possible in theory? Maybe document this more explicitly... */
467	}
468	#endif
469
470	/**
471	* Signals the next pending interrupt for the specified Redirection Table Entry
472	* (RTE).
473	*
474	* @param pDevIns The device instance.
475	* @param pThis The shared I/O APIC device state.
476	* @param pThisCC The I/O APIC device state for the current context.
477	* @param uBusDevFn The bus:device:function of the device initiating the IRQ.
478	* @param idxRte The index of the RTE (validated).
479	*
480	* @remarks It is the responsibility of the caller to verify that an interrupt is
481	* pending for the pin corresponding to the RTE before calling this
482	* function.
483	*/
484	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte)
485	{
486	#ifndef IOAPIC_WITH_PDM_CRITSECT
487	Assert(PDMCritSectIsOwner(&pThis->CritSect));
488	#endif
489
490	/* Ensure the RTE isn't masked. */
491	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
492	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
493	{
494	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
495	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
496	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
497	{
498	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
499	if (u8RemoteIrr)
500	{
501	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
502	return;
503	}
504	}
505
506	/** @todo IOMMU: Call into the IOMMU on how to remap this interrupt. uBusDevFn
507	* will be needed then. */
508	NOREF(uBusDevFn);
509
510	uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
511	uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
512	uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
513	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
514	uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
515	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
516
517	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
518	u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
519	u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
520
521	/*
522	* Deliver to the local APIC via the system/3-wire-APIC bus.
523	*/
524	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
525	u8Dest,
526	u8DestMode,
527	u8DeliveryMode,
528	u8Vector,
529	u8Polarity,
530	u8TriggerMode,
531	u32TagSrc);
532	/* Can't reschedule to R3. */
533	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
534	#ifdef DEBUG_ramshankar
535	if (rc == VERR_APIC_INTR_DISCARDED)
536	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
537	#endif
538
539	/*
540	* For level-triggered interrupts, we set the remote IRR bit to indicate
541	* the local APIC has accepted the interrupt.
542	*
543	* For edge-triggered interrupts, we should not clear the IRR bit as it
544	* should remain intact to reflect the state of the interrupt line.
545	* The device will explicitly transition to inactive state via the
546	* ioapicSetIrq() callback.
547	*/
548	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
549	&& rc == VINF_SUCCESS)
550	{
551	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
552	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
553	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
554	}
555	}
556	}
557
558
559	/**
560	* Gets the redirection table entry.
561	*
562	* @returns The redirection table entry.
563	* @param pThis The shared I/O APIC device state.
564	* @param uIndex The index value.
565	*/
566	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
567	{
568	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
569	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
570	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
571	UINT32_MAX);
572	uint32_t uValue;
573	if (!(uIndex & 1))
574	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
575	else
576	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
577
578	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
579	return uValue;
580	}
581
582
583	/**
584	* Sets the redirection table entry.
585	*
586	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
587	* @param pDevIns The device instance.
588	* @param pThis The shared I/O APIC device state.
589	* @param pThisCC The I/O APIC device state for the current context.
590	* @param uIndex The index value.
591	* @param uValue The value to set.
592	*/
593	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
594	uint32_t uIndex, uint32_t uValue)
595	{
596	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
597	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
598	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
599	VINF_SUCCESS);
600
601	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
602	if (rc == VINF_SUCCESS)
603	{
604	/*
605	* Write the low or high 32-bit value into the specified 64-bit RTE register,
606	* update only the valid, writable bits.
607	*
608	* We need to preserve the read-only bits as it can have dire consequences
609	* otherwise, see @bugref{8386#c24}.
610	*/
611	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
612	if (!(uIndex & 1))
613	{
614	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
615	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
616	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
617	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
618	}
619	else
620	{
621	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
622	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
623	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
624	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
625	}
626
627	/*
628	* Signal the next pending interrupt for this RTE.
629	*/
630	uint32_t const uPinMask = UINT32_C(1) << idxRte;
631	if (pThis->uIrr & uPinMask)
632	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte);
633
634	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
635	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
636	}
637	else
638	STAM_COUNTER_INC(&pThis->StatSetRteContention);
639
640	return rc;
641	}
642
643
644	/**
645	* Gets the data register.
646	*
647	* @returns The data value.
648	* @param pThis The shared I/O APIC device state.
649	*/
650	static uint32_t ioapicGetData(PCIOAPIC pThis)
651	{
652	uint8_t const uIndex = pThis->u8Index;
653	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
654	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
655	&& uIndex <= pThis->u8LastRteRegIdx)
656	return ioapicGetRedirTableEntry(pThis, uIndex);
657
658	uint32_t uValue;
659	switch (uIndex)
660	{
661	case IOAPIC_INDIRECT_INDEX_ID:
662	uValue = ioapicGetId(pThis);
663	break;
664
665	case IOAPIC_INDIRECT_INDEX_VERSION:
666	uValue = ioapicGetVersion(pThis);
667	break;
668
669	case IOAPIC_INDIRECT_INDEX_ARB:
670	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
671	{
672	uValue = ioapicGetArb();
673	break;
674	}
675	RT_FALL_THRU();
676
677	default:
678	uValue = UINT32_C(0xffffffff);
679	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
680	break;
681	}
682	return uValue;
683	}
684
685
686	/**
687	* Sets the data register.
688	*
689	* @returns Strict VBox status code.
690	* @param pDevIns The device instance.
691	* @param pThis The shared I/O APIC device state.
692	* @param pThisCC The I/O APIC device state for the current context.
693	* @param uValue The value to set.
694	*/
695	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
696	{
697	uint8_t const uIndex = pThis->u8Index;
698	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
699	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
700
701	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
702	&& uIndex <= pThis->u8LastRteRegIdx)
703	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
704
705	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
706	ioapicSetId(pThis, uValue);
707	else
708	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
709
710	return VINF_SUCCESS;
711	}
712
713
714	/**
715	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
716	*/
717	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
718	{
719	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
720	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
721	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
722	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
723
724	bool fRemoteIrrCleared = false;
725	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
726	if (rc == VINF_SUCCESS)
727	{
728	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
729	{
730	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
731	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
732	{
733	#ifdef DEBUG_ramshankar
734	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
735	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
736	#endif
737	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
738	fRemoteIrrCleared = true;
739	STAM_COUNTER_INC(&pThis->StatEoiReceived);
740	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
741
742	/*
743	* Signal the next pending interrupt for this RTE.
744	*/
745	uint32_t const uPinMask = UINT32_C(1) << idxRte;
746	if (pThis->uIrr & uPinMask)
747	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte);
748	}
749	}
750
751	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
752	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
753	}
754	else
755	STAM_COUNTER_INC(&pThis->StatEoiContention);
756
757	return rc;
758	}
759
760
761	/**
762	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
763	*/
764	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
765	{
766	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
767	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
768	pThis->uIrr \|= a_PinMask; \
769	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \
770	} while (0)
771
772	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
773	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
774	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
775
776	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
777
778	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
779	{
780	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
781	AssertRC(rc);
782
783	uint8_t const idxRte = iIrq;
784	uint32_t const uPinMask = UINT32_C(1) << idxRte;
785	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
786	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
787
788	bool fActive = RT_BOOL(iLevel & 1);
789	/** @todo Polarity is busted elsewhere, we need to fix that
790	* first. See @bugref{8386#c7}. */
791	#if 0
792	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
793	fActive ^= u8Polarity; */
794	#endif
795	if (!fActive)
796	{
797	pThis->uIrr &= ~uPinMask;
798	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
799	return;
800	}
801
802	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
803	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
804	if (!fFlipFlop)
805	{
806	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
807	{
808	/*
809	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
810	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
811	*/
812	if (!uPrevIrr)
813	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
814	else
815	{
816	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
817	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
818	}
819	}
820	else
821	{
822	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
823
824	/*
825	* For level-triggered interrupts, redundant interrupts are not a problem
826	* and will eventually be delivered anyway after an EOI, but our PDM devices
827	* should not typically call us with no change to the level.
828	*/
829	if (!uPrevIrr)
830	{ /* likely */ }
831	else
832	{
833	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
834	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
835	}
836
837	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
838	}
839	}
840	else
841	{
842	/*
843	* The device is flip-flopping the interrupt line, which implies we should de-assert
844	* and assert the interrupt line. The interrupt line is left in the asserted state
845	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
846	* hence just the assert is done.
847	*/
848	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
849	}
850
851	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
852	}
853	#undef IOAPIC_ASSERT_IRQ
854	}
855
856
857	/**
858	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
859	*/
860	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
861	{
862	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
863	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
864
865	XAPICINTR ApicIntr;
866	RT_ZERO(ApicIntr);
867
868	#ifdef VBOX_WITH_IOMMU_AMD
869	/*
870	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
871	*/
872	MSIMSG MsiOut;
873	Assert(PCIBDF_IS_VALID(uBusDevFn));
874	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
875	if (RT_SUCCESS(rcRemap))
876	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
877	else
878	{
879	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
880	Log3(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping denied. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
881	else
882	Log(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping failed. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
883	return;
884	}
885	#else
886	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
887	#endif
888
889	/*
890	* Deliver to the local APIC via the system/3-wire-APIC bus.
891	*/
892	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
893	ApicIntr.u8Dest,
894	ApicIntr.u8DestMode,
895	ApicIntr.u8DeliveryMode,
896	ApicIntr.u8Vector,
897	0 /* u8Polarity - N/A */,
898	ApicIntr.u8TriggerMode,
899	uTagSrc);
900	/* Can't reschedule to R3. */
901	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
902	}
903
904
905	/**
906	* @callback_method_impl{FNIOMMMIONEWREAD}
907	*/
908	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
909	{
910	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
911	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
912	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
913	RT_NOREF_PV(pvUser);
914
915	VBOXSTRICTRC rc = VINF_SUCCESS;
916	uint32_t puValue = (uint32_t )pv;
917	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
918	switch (offReg)
919	{
920	case IOAPIC_DIRECT_OFF_INDEX:
921	*puValue = ioapicGetIndex(pThis);
922	break;
923
924	case IOAPIC_DIRECT_OFF_DATA:
925	*puValue = ioapicGetData(pThis);
926	break;
927
928	default:
929	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
930	rc = VINF_IOM_MMIO_UNUSED_FF;
931	break;
932	}
933
934	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
935	return rc;
936	}
937
938
939	/**
940	* @callback_method_impl{FNIOMMMIONEWWRITE}
941	*/
942	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
943	{
944	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
945	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
946	RT_NOREF_PV(pvUser);
947
948	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
949
950	Assert(!(off & 3));
951	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
952
953	VBOXSTRICTRC rc = VINF_SUCCESS;
954	uint32_t const uValue = (uint32_t const )pv;
955	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
956
957	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
958	switch (offReg)
959	{
960	case IOAPIC_DIRECT_OFF_INDEX:
961	ioapicSetIndex(pThis, uValue);
962	break;
963
964	case IOAPIC_DIRECT_OFF_DATA:
965	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
966	break;
967
968	case IOAPIC_DIRECT_OFF_EOI:
969	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
970	rc = ioapicSetEoi(pDevIns, uValue);
971	else
972	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
973	break;
974
975	default:
976	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
977	break;
978	}
979
980	return rc;
981	}
982
983
984	#ifdef IN_RING3
985
986	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
987	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
988	{
989	RT_NOREF(pDesc);
990	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
991	return VINF_SUCCESS;
992	}
993
994
995	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
996	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
997	{
998	RT_NOREF(pDesc, pfMask);
999	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1000	return VINF_SUCCESS;
1001	}
1002
1003
1004	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1005	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1006	{
1007	RT_NOREF(pDesc);
1008	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1014	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1015	{
1016	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1017	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1018	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1019	RT_NOREF(pDesc, pfMask);
1020	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1021	}
1022
1023
1024	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1025	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1026	{
1027	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1028	RT_NOREF(pDesc);
1029	pValue->u32 = ioapicGetVersion(pThis);
1030	return VINF_SUCCESS;
1031	}
1032
1033
1034	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1035	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1036	{
1037	RT_NOREF(pvUser, pDesc);
1038	pValue->u32 = ioapicGetArb();
1039	return VINF_SUCCESS;
1040	}
1041
1042
1043	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1044	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1045	{
1046	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1047	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1048	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1049	return VINF_SUCCESS;
1050	}
1051
1052
1053	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1054	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1055	{
1056	RT_NOREF(pfMask);
1057	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1058	/* No locks, no checks, just do it. */
1059	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1060	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1061	return VINF_SUCCESS;
1062	}
1063
1064
1065	/** IOREDTBLn sub fields. */
1066	static DBGFREGSUBFIELD const g_aRteSubs[] =
1067	{
1068	{ "vector", 0, 8, 0, 0, NULL, NULL },
1069	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1070	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1071	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1072	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1073	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1074	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1075	{ "mask", 16, 1, 0, 0, NULL, NULL },
1076	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1077	{ "dest", 56, 8, 0, 0, NULL, NULL },
1078	DBGFREGSUBFIELD_TERMINATOR()
1079	};
1080
1081
1082	/** Register descriptors for DBGF. */
1083	static DBGFREGDESC const g_aRegDesc[] =
1084	{
1085	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1086	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1087	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1088	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1089	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1090	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1091	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1092	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1093	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1094	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1095	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1096	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1097	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1098	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1099	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1100	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1101	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1102	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1103	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1104	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1105	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1106	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1107	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1108	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1109	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1110	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1111	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1112	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1113	DBGFREGDESC_TERMINATOR()
1114	};
1115
1116
1117	/**
1118	* @callback_method_impl{FNDBGFHANDLERDEV}
1119	*/
1120	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1121	{
1122	RT_NOREF(pszArgs);
1123	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1124	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1125
1126	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1127
1128	uint32_t const uId = ioapicGetId(pThis);
1129	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1130	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1131
1132	uint32_t const uVer = ioapicGetVersion(pThis);
1133	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1134	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1135	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1136	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1137
1138	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1139	{
1140	uint32_t const uArb = ioapicGetArb();
1141	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1142	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1143	}
1144
1145	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1146
1147	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1148	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1149
1150	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1151	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1152	{
1153	static const char * const s_apszDeliveryModes[] =
1154	{
1155	"Fixed ",
1156	"LowPri",
1157	"SMI ",
1158	"Rsvd ",
1159	"NMI ",
1160	"INIT ",
1161	"Rsvd ",
1162	"ExtINT"
1163	};
1164
1165	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1166	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1167	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1168	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1169	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1170	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1171	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1172	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1173	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1174	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1175	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1176	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1177
1178	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1179	idxRte,
1180	pszDestMode,
1181	uDest,
1182	uMask,
1183	(pThis->uIrr >> idxRte) & 1,
1184	pszTriggerMode,
1185	uRemoteIrr,
1186	pszPolarity,
1187	pszDeliveryStatus,
1188	pszDeliveryMode,
1189	uVector,
1190	u64Rte);
1191	}
1192	}
1193
1194
1195	/**
1196	* @copydoc FNSSMDEVSAVEEXEC
1197	*/
1198	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1199	{
1200	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1201	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1202	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1203
1204	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1205	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1206	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1207	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1208	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1209
1210	return VINF_SUCCESS;
1211	}
1212
1213
1214	/**
1215	* @copydoc FNSSMDEVLOADEXEC
1216	*/
1217	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1218	{
1219	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1220	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1221	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1222
1223	Assert(uPass == SSM_PASS_FINAL);
1224	NOREF(uPass);
1225
1226	/* Weed out invalid versions. */
1227	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1228	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1229	{
1230	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1231	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1232	}
1233
1234	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1235	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1236
1237	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1238	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1239	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1240	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1241
1242	return VINF_SUCCESS;
1243	}
1244
1245
1246	/**
1247	* @interface_method_impl{PDMDEVREG,pfnReset}
1248	*/
1249	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1250	{
1251	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1252	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1253	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1254
1255	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1256	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1257
1258	pThis->uIrr = 0;
1259	pThis->u8Index = 0;
1260	pThis->u8Id = 0;
1261
1262	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1263	{
1264	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1265	pThis->au32TagSrc[idxRte] = 0;
1266	}
1267
1268	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1269	}
1270
1271
1272	/**
1273	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1274	*/
1275	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1276	{
1277	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1278	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1279
1280	pThisRC->pIoApicHlp += offDelta;
1281	}
1282
1283
1284	/**
1285	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1286	*/
1287	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1288	{
1289	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1290	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1291	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1292
1293	# ifndef IOAPIC_WITH_PDM_CRITSECT
1294	/*
1295	* Destroy the RTE critical section.
1296	*/
1297	if (PDMCritSectIsInitialized(&pThis->CritSect))
1298	PDMR3CritSectDelete(&pThis->CritSect);
1299	# else
1300	RT_NOREF_PV(pThis);
1301	# endif
1302
1303	return VINF_SUCCESS;
1304	}
1305
1306
1307	/**
1308	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1309	*/
1310	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1311	{
1312	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1313	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1314	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1315	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1316	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1317	Assert(iInstance == 0); RT_NOREF(iInstance);
1318
1319	/*
1320	* Validate and read the configuration.
1321	*/
1322	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1323
1324	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1325	upsets some guest which we haven't yet tested. */
1326	uint32_t cCpus;
1327	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1328	if (RT_FAILURE(rc))
1329	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1330	pThis->cCpus = (uint8_t)cCpus;
1331
1332	char szChipType[16];
1333	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1334	if (RT_FAILURE(rc))
1335	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1336
1337	if (!strcmp(szChipType, "ICH9"))
1338	{
1339	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1340	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1341	pThis->u8IdMask = 0xff;
1342	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1343	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1344	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1345	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1346	}
1347	else if (!strcmp(szChipType, "82093AA"))
1348	{
1349	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1350	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1351	pThis->u8IdMask = 0x0f;
1352	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1353	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1354	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1355	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1356	}
1357	else if (!strcmp(szChipType, "82379AB"))
1358	{
1359	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1360	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1361	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1362	pThis->u8IdMask = 0x0f;
1363	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1364	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1365	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1366	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1367	}
1368	else
1369	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1370	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1371	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1372
1373	/*
1374	* We will use our own critical section for the IOAPIC device.
1375	*/
1376	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1377	AssertRCReturn(rc, rc);
1378
1379	# ifndef IOAPIC_WITH_PDM_CRITSECT
1380	/*
1381	* Setup the critical section to protect concurrent writes to the RTEs.
1382	*/
1383	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1384	AssertRCReturn(rc, rc);
1385	# endif
1386
1387	/*
1388	* Register the IOAPIC.
1389	*/
1390	PDMIOAPICREG IoApicReg;
1391	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1392	IoApicReg.pfnSetIrq = ioapicSetIrq;
1393	IoApicReg.pfnSendMsi = ioapicSendMsi;
1394	IoApicReg.pfnSetEoi = ioapicSetEoi;
1395	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1396	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1397	AssertRCReturn(rc, rc);
1398
1399	/*
1400	* Register MMIO region.
1401	*/
1402	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1403	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1404	AssertRCReturn(rc, rc);
1405
1406	/*
1407	* Register the saved state.
1408	*/
1409	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1410	AssertRCReturn(rc, rc);
1411
1412	/*
1413	* Register debugger info item.
1414	*/
1415	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1416	AssertRCReturn(rc, rc);
1417
1418	/*
1419	* Register debugger register access.
1420	*/
1421	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1422	AssertRCReturn(rc, rc);
1423
1424	# ifdef VBOX_WITH_STATISTICS
1425	/*
1426	* Statistics.
1427	*/
1428	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1429	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1430	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1431	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1432
1433	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1434	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1435	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1436	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1437
1438	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1439	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1440	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1441
1442	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1443	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1444
1445	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1446	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1447	# endif
1448
1449	/*
1450	* Init. the device state.
1451	*/
1452	LogRel(("IOAPIC: Using implementation 2.0! Chipset type %s\n", szChipType));
1453	ioapicR3Reset(pDevIns);
1454
1455	return VINF_SUCCESS;
1456	}
1457
1458	#else /* !IN_RING3 */
1459
1460	/**
1461	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1462	*/
1463	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1464	{
1465	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1466	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1467	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1468
1469	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1470	AssertRCReturn(rc, rc);
1471
1472	PDMIOAPICREG IoApicReg;
1473	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1474	IoApicReg.pfnSetIrq = ioapicSetIrq;
1475	IoApicReg.pfnSendMsi = ioapicSendMsi;
1476	IoApicReg.pfnSetEoi = ioapicSetEoi;
1477	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1478	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1479	AssertRCReturn(rc, rc);
1480
1481	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1482	AssertRCReturn(rc, rc);
1483
1484	return VINF_SUCCESS;
1485	}
1486
1487	#endif /* !IN_RING3 */
1488
1489	/**
1490	* IO APIC device registration structure.
1491	*/
1492	const PDMDEVREG g_DeviceIOAPIC =
1493	{
1494	/* .u32Version = */ PDM_DEVREG_VERSION,
1495	/* .uReserved0 = */ 0,
1496	/* .szName = */ "ioapic",
1497	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1498	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1499	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1500	/* .cMaxInstances = */ 1,
1501	/* .uSharedVersion = */ 42,
1502	/* .cbInstanceShared = */ sizeof(IOAPIC),
1503	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1504	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1505	/* .cMaxPciDevices = */ 0,
1506	/* .cMaxMsixVectors = */ 0,
1507	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1508	#if defined(IN_RING3)
1509	/* .pszRCMod = */ "VBoxDDRC.rc",
1510	/* .pszR0Mod = */ "VBoxDDR0.r0",
1511	/* .pfnConstruct = */ ioapicR3Construct,
1512	/* .pfnDestruct = */ ioapicR3Destruct,
1513	/* .pfnRelocate = */ ioapicR3Relocate,
1514	/* .pfnMemSetup = */ NULL,
1515	/* .pfnPowerOn = */ NULL,
1516	/* .pfnReset = */ ioapicR3Reset,
1517	/* .pfnSuspend = */ NULL,
1518	/* .pfnResume = */ NULL,
1519	/* .pfnAttach = */ NULL,
1520	/* .pfnDetach = */ NULL,
1521	/* .pfnQueryInterface = */ NULL,
1522	/* .pfnInitComplete = */ NULL,
1523	/* .pfnPowerOff = */ NULL,
1524	/* .pfnSoftReset = */ NULL,
1525	/* .pfnReserved0 = */ NULL,
1526	/* .pfnReserved1 = */ NULL,
1527	/* .pfnReserved2 = */ NULL,
1528	/* .pfnReserved3 = */ NULL,
1529	/* .pfnReserved4 = */ NULL,
1530	/* .pfnReserved5 = */ NULL,
1531	/* .pfnReserved6 = */ NULL,
1532	/* .pfnReserved7 = */ NULL,
1533	#elif defined(IN_RING0)
1534	/* .pfnEarlyConstruct = */ NULL,
1535	/* .pfnConstruct = */ ioapicRZConstruct,
1536	/* .pfnDestruct = */ NULL,
1537	/* .pfnFinalDestruct = */ NULL,
1538	/* .pfnRequest = */ NULL,
1539	/* .pfnReserved0 = */ NULL,
1540	/* .pfnReserved1 = */ NULL,
1541	/* .pfnReserved2 = */ NULL,
1542	/* .pfnReserved3 = */ NULL,
1543	/* .pfnReserved4 = */ NULL,
1544	/* .pfnReserved5 = */ NULL,
1545	/* .pfnReserved6 = */ NULL,
1546	/* .pfnReserved7 = */ NULL,
1547	#elif defined(IN_RC)
1548	/* .pfnConstruct = */ ioapicRZConstruct,
1549	/* .pfnReserved0 = */ NULL,
1550	/* .pfnReserved1 = */ NULL,
1551	/* .pfnReserved2 = */ NULL,
1552	/* .pfnReserved3 = */ NULL,
1553	/* .pfnReserved4 = */ NULL,
1554	/* .pfnReserved5 = */ NULL,
1555	/* .pfnReserved6 = */ NULL,
1556	/* .pfnReserved7 = */ NULL,
1557	#else
1558	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1559	#endif
1560	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1561	};
1562
1563
1564	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1565

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 84859

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