VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 84867

Last change on this file since 84867 was 84867, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 DevIoApic: Remap interrupts via the IOMMU.
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1/* $Id: DevIoApic.cpp 84867 2020-06-18 08:17:47Z vboxsync $ */
2/** @file
3 * IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23#include <VBox/log.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/msi.h>
26#include <VBox/vmm/pdmdev.h>
27
28#include "VBoxDD.h"
29#include <iprt/x86.h>
30#include <iprt/string.h>
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36/** The current IO APIC saved state version. */
37#define IOAPIC_SAVED_STATE_VERSION 2
38/** The saved state version used by VirtualBox 5.0 and
39 * earlier. */
40#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
41
42/** Implementation specified by the "Intel I/O Controller Hub 9
43 * (ICH9) Family" */
44#define IOAPIC_VERSION_ICH9 0x20
45/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
46Controller" */
47#define IOAPIC_VERSION_82093AA 0x11
48
49/** The default MMIO base physical address. */
50#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
51/** The size of the MMIO range. */
52#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
53/** The mask for getting direct registers from physical address. */
54#define IOAPIC_MMIO_REG_MASK 0xff
55
56/** The number of interrupt input pins. */
57#define IOAPIC_NUM_INTR_PINS 24
58/** Maximum redirection entires. */
59#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
60/** Reduced RTEs used by SIO.A (82379AB). */
61#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
62
63/** Version register - Gets the version. */
64#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
65/** Version register - Gets the maximum redirection entry. */
66#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
67/** Version register - Gets whether Pin Assertion Register (PRQ) is
68 * supported. */
69#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
70
71/** Index register - Valid write mask. */
72#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
73
74/** Arbitration register - Gets the ID. */
75#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
76
77/** ID register - Gets the ID. */
78#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
79
80/** Redirection table entry - Vector. */
81#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
82/** Redirection table entry - Delivery mode. */
83#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
84/** Redirection table entry - Destination mode. */
85#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
86/** Redirection table entry - Delivery status. */
87#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
88/** Redirection table entry - Interrupt input pin polarity. */
89#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
90/** Redirection table entry - Remote IRR. */
91#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
92/** Redirection table entry - Trigger Mode. */
93#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
94/** Redirection table entry - the mask bit number. */
95#define IOAPIC_RTE_MASK_BIT 16
96/** Redirection table entry - the mask. */
97#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
98/** Redirection table entry - Extended Destination ID. */
99#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
100/** Redirection table entry - Destination. */
101#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
102
103/** Redirection table entry - Gets the destination. */
104#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
105/** Redirection table entry - Gets the mask flag. */
106#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
107/** Redirection table entry - Checks whether it's masked. */
108#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
109/** Redirection table entry - Gets the trigger mode. */
110#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
111/** Redirection table entry - Gets the remote IRR flag. */
112#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
113/** Redirection table entry - Gets the interrupt pin polarity. */
114#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
115/** Redirection table entry - Gets the delivery status. */
116#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
117/** Redirection table entry - Gets the destination mode. */
118#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
119/** Redirection table entry - Gets the delivery mode. */
120#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
121/** Redirection table entry - Gets the vector. */
122#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
123
124/** Redirection table entry - Valid write mask for 82093AA. */
125#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
126 | IOAPIC_RTE_POLARITY | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE \
127 | IOAPIC_RTE_VECTOR)
128/** Redirection table entry - Valid read mask for 82093AA. */
129#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
130 | IOAPIC_RTE_REMOTE_IRR | IOAPIC_RTE_POLARITY | IOAPIC_RTE_DELIVERY_STATUS \
131 | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE | IOAPIC_RTE_VECTOR)
132
133/** Redirection table entry - Valid write mask for ICH9. */
134/** @note The remote IRR bit has been reverted to read-only as it turns out the
135 * ICH9 spec. is wrong, see @bugref{8386#c46}. */
136#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
137 /*| IOAPIC_RTE_REMOTE_IRR */| IOAPIC_RTE_POLARITY | IOAPIC_RTE_DEST_MODE \
138 | IOAPIC_RTE_DELIVERY_MODE | IOAPIC_RTE_VECTOR)
139/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
140#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST | IOAPIC_RTE_EXT_DEST_ID | IOAPIC_RTE_MASK \
141 | IOAPIC_RTE_TRIGGER_MODE | IOAPIC_RTE_REMOTE_IRR | IOAPIC_RTE_POLARITY \
142 | IOAPIC_RTE_DELIVERY_STATUS | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE \
143 | IOAPIC_RTE_VECTOR)
144
145/** Redirection table entry - Trigger mode edge. */
146#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
147/** Redirection table entry - Trigger mode level. */
148#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
149/** Redirection table entry - Destination mode physical. */
150#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
151/** Redirection table entry - Destination mode logical. */
152#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
153
154
155/** Index of indirect registers in the I/O APIC register table. */
156#define IOAPIC_INDIRECT_INDEX_ID 0x0
157#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
158#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
159#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
160#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
161#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
162
163/** Offset of direct registers in the I/O APIC MMIO space. */
164#define IOAPIC_DIRECT_OFF_INDEX 0x00
165#define IOAPIC_DIRECT_OFF_DATA 0x10
166#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
167
168/** The I/O APIC's Bus:Device:Function. */
169#define IOAPIC_BUS_DEV_FN NIL_PCIBDF
170
171/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
172#define IOAPIC_WITH_PDM_CRITSECT
173#ifdef IOAPIC_WITH_PDM_CRITSECT
174# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
175# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
176#else
177# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
178# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
179#endif
180
181
182/*********************************************************************************************************************************
183* Structures and Typedefs *
184*********************************************************************************************************************************/
185/**
186 * The shared I/O APIC device state.
187 */
188typedef struct IOAPIC
189{
190 /** The ID register. */
191 uint8_t volatile u8Id;
192 /** The index register. */
193 uint8_t volatile u8Index;
194 /** Number of CPUs. */
195 uint8_t cCpus;
196 /** I/O APIC version. */
197 uint8_t u8ApicVer;
198 /** I/O APIC ID mask. */
199 uint8_t u8IdMask;
200 /** Maximum Redirection Table Entry (RTE) Entry. */
201 uint8_t u8MaxRte;
202 /** Last valid RTE indirect register index. */
203 uint8_t u8LastRteRegIdx;
204 /* Alignment padding. */
205 uint8_t u8Padding0[1];
206 /** Redirection table entry - Valid write mask. */
207 uint64_t u64RteWriteMask;
208 /** Redirection table entry - Valid read mask. */
209 uint64_t u64RteReadMask;
210
211 /** The redirection table registers. */
212 uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
213 /** The IRQ tags and source IDs for each pin (tracing purposes). */
214 uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
215
216 /** The internal IRR reflecting state of the interrupt lines. */
217 uint32_t uIrr;
218 /** Alignment padding. */
219 uint32_t u32Padding2;
220
221#ifndef IOAPIC_WITH_PDM_CRITSECT
222 /** The critsect for updating to the RTEs. */
223 PDMCRITSECT CritSect;
224#endif
225
226 /** The MMIO region. */
227 IOMMMIOHANDLE hMmio;
228
229#ifdef VBOX_WITH_STATISTICS
230 /** Number of MMIO reads in RZ. */
231 STAMCOUNTER StatMmioReadRZ;
232 /** Number of MMIO reads in R3. */
233 STAMCOUNTER StatMmioReadR3;
234
235 /** Number of MMIO writes in RZ. */
236 STAMCOUNTER StatMmioWriteRZ;
237 /** Number of MMIO writes in R3. */
238 STAMCOUNTER StatMmioWriteR3;
239
240 /** Number of SetIrq calls in RZ. */
241 STAMCOUNTER StatSetIrqRZ;
242 /** Number of SetIrq calls in R3. */
243 STAMCOUNTER StatSetIrqR3;
244
245 /** Number of SetEoi calls in RZ. */
246 STAMCOUNTER StatSetEoiRZ;
247 /** Number of SetEoi calls in R3. */
248 STAMCOUNTER StatSetEoiR3;
249
250 /** Number of redundant edge-triggered interrupts. */
251 STAMCOUNTER StatRedundantEdgeIntr;
252 /** Number of redundant level-triggered interrupts. */
253 STAMCOUNTER StatRedundantLevelIntr;
254 /** Number of suppressed level-triggered interrupts (by remote IRR). */
255 STAMCOUNTER StatSuppressedLevelIntr;
256 /** Number of returns to ring-3 due to EOI broadcast lock contention. */
257 STAMCOUNTER StatEoiContention;
258 /** Number of returns to ring-3 due to Set RTE lock contention. */
259 STAMCOUNTER StatSetRteContention;
260 /** Number of level-triggered interrupts dispatched to the local APIC(s). */
261 STAMCOUNTER StatLevelIrqSent;
262 /** Number of EOIs received for level-triggered interrupts from the local
263 * APIC(s). */
264 STAMCOUNTER StatEoiReceived;
265#endif
266} IOAPIC;
267AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
268/** Pointer to shared IOAPIC data. */
269typedef IOAPIC *PIOAPIC;
270/** Pointer to const shared IOAPIC data. */
271typedef IOAPIC const *PCIOAPIC;
272
273
274/**
275 * The I/O APIC device state for ring-3.
276 */
277typedef struct IOAPICR3
278{
279 /** The IOAPIC helpers. */
280 R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
281} IOAPICR3;
282/** Pointer to the I/O APIC device state for ring-3. */
283typedef IOAPICR3 *PIOAPICR3;
284
285
286/**
287 * The I/O APIC device state for ring-0.
288 */
289typedef struct IOAPICR0
290{
291 /** The IOAPIC helpers. */
292 R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
293} IOAPICR0;
294/** Pointer to the I/O APIC device state for ring-0. */
295typedef IOAPICR0 *PIOAPICR0;
296
297
298/**
299 * The I/O APIC device state for raw-mode.
300 */
301typedef struct IOAPICRC
302{
303 /** The IOAPIC helpers. */
304 RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
305} IOAPICRC;
306/** Pointer to the I/O APIC device state for raw-mode. */
307typedef IOAPICRC *PIOAPICRC;
308
309
310/** The I/O APIC device state for the current context. */
311typedef CTX_SUFF(IOAPIC) IOAPICCC;
312/** Pointer to the I/O APIC device state for the current context. */
313typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
314
315
316/**
317 * xAPIC interrupt.
318 */
319typedef struct XAPICINTR
320{
321 /** The interrupt vector. */
322 uint8_t u8Vector;
323 /** The destination (mask or ID). */
324 uint8_t u8Dest;
325 /** The destination mode. */
326 uint8_t u8DestMode;
327 /** Delivery mode. */
328 uint8_t u8DeliveryMode;
329 /** Trigger mode. */
330 uint8_t u8TriggerMode;
331 /** Redirection hint. */
332 uint8_t u8RedirHint;
333 /** Polarity. */
334 uint8_t u8Polarity;
335 /** Padding. */
336 uint8_t abPadding0;
337} XAPICINTR;
338/** Pointer to an I/O xAPIC interrupt struct. */
339typedef XAPICINTR *PXAPICINTR;
340/** Pointer to a const xAPIC interrupt struct. */
341typedef XAPICINTR const *PCXAPICINTR;
342
343
344#ifndef VBOX_DEVICE_STRUCT_TESTCASE
345
346/**
347 * Gets the arbitration register.
348 *
349 * @returns The arbitration.
350 */
351DECLINLINE(uint32_t) ioapicGetArb(void)
352{
353 Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
354 return 0;
355}
356
357
358/**
359 * Gets the version register.
360 *
361 * @returns The version.
362 */
363DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
364{
365 uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
366 Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
367 return uValue;
368}
369
370
371/**
372 * Sets the ID register.
373 *
374 * @param pThis The shared I/O APIC device state.
375 * @param uValue The value to set.
376 */
377DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
378{
379 Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
380 ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
381}
382
383
384/**
385 * Gets the ID register.
386 *
387 * @returns The ID.
388 * @param pThis The shared I/O APIC device state.
389 */
390DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
391{
392 uint32_t uValue = (uint32_t)pThis->u8Id << 24;
393 Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
394 return uValue;
395}
396
397
398/**
399 * Sets the index register.
400 *
401 * @param pThis The shared I/O APIC device state.
402 * @param uValue The value to set.
403 */
404DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
405{
406 LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
407 ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
408}
409
410
411/**
412 * Gets the index register.
413 *
414 * @returns The index value.
415 */
416DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
417{
418 uint32_t const uValue = pThis->u8Index;
419 LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
420 return uValue;
421}
422
423
424/**
425 * Converts an MSI message to an APIC interrupt.
426 *
427 * @param pMsi The MSI message to convert.
428 * @param pIntr Where to store the APIC interrupt.
429 */
430DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
431{
432 /*
433 * Parse the message from the physical address and data
434 * See Intel spec. 10.11.1 "Message Address Register Format".
435 * See Intel spec. 10.11.2 "Message Data Register Format".
436 */
437 pIntr->u8Dest = pMsi->Addr.n.u8DestId;
438 pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
439 pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
440
441 pIntr->u8Vector = pMsi->Data.n.u8Vector;
442 pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
443 pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
444}
445
446
447/**
448 * Convert an APIC interrupt to an MSI message.
449 *
450 * @param pIntr The APIC interrupt to convert.
451 * @param pMsi Where to store the MSI message.
452 */
453DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
454{
455 pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
456 pMsi->Addr.n.u8DestId = pIntr->u8Dest;
457 pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
458 pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
459
460 pMsi->Data.n.u8Vector = pIntr->u8Vector;
461 pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
462 pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
463
464 /* pMsi->Data.n.u1Level = ??? */
465 /** @todo r=ramshankar: Level triggered MSIs don't make much sense though
466 * possible in theory? Maybe document this more explicitly... */
467}
468
469
470/**
471 * Signals the next pending interrupt for the specified Redirection Table Entry
472 * (RTE).
473 *
474 * @param pDevIns The device instance.
475 * @param pThis The shared I/O APIC device state.
476 * @param pThisCC The I/O APIC device state for the current context.
477 * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
478 * @param idxRte The index of the RTE (validated).
479 *
480 * @remarks It is the responsibility of the caller to verify that an interrupt is
481 * pending for the pin corresponding to the RTE before calling this
482 * function.
483 */
484static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte)
485{
486#ifndef IOAPIC_WITH_PDM_CRITSECT
487 Assert(PDMCritSectIsOwner(&pThis->CritSect));
488#endif
489
490 /*
491 * Ensure the interrupt isn't masked.
492 */
493 uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
494 if (!IOAPIC_RTE_IS_MASKED(u64Rte))
495 {
496 /* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
497 uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
498 if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
499 {
500 uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
501 if (u8RemoteIrr)
502 {
503 STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
504 return;
505 }
506 }
507
508 XAPICINTR ApicIntr;
509 ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
510 ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
511 ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
512 ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
513 ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
514 ApicIntr.u8TriggerMode = u8TriggerMode;
515 ApicIntr.u8RedirHint = 0;
516
517#ifdef VBOX_WITH_IOMMU_AMD
518 /*
519 * The interrupt may need to be remapped (or discarded) if an IOMMU is present.
520 */
521 MSIMSG MsiOut;
522 MSIMSG MsiIn;
523 ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
524 Assert(PCIBDF_IS_VALID(uBusDevFn));
525 int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, &MsiIn, &MsiOut);
526 if (RT_SUCCESS(rcRemap))
527 ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
528 else
529 {
530 if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
531 Log3(("IOAPIC: Interrupt (u8Vector=%#x) remapping denied. rc=%Rrc", ApicIntr.u8Vector, rcRemap));
532 else
533 Log(("IOAPIC: Interrupt (u8Vector=%#x) remapping failed. rc=%Rrc", ApicIntr.u8Vector, rcRemap));
534 return;
535 }
536#else
537 NOREF(uBusDevFn);
538#endif
539
540 uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
541 Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
542 ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
543 ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
544 ApicIntr.u8Vector, ApicIntr.u8Vector));
545
546 /*
547 * Deliver to the local APIC via the system/3-wire-APIC bus.
548 */
549 int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
550 ApicIntr.u8Dest,
551 ApicIntr.u8DestMode,
552 ApicIntr.u8DeliveryMode,
553 ApicIntr.u8Vector,
554 ApicIntr.u8Polarity,
555 ApicIntr.u8TriggerMode,
556 u32TagSrc);
557 /* Can't reschedule to R3. */
558 Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED);
559#ifdef DEBUG_ramshankar
560 if (rc == VERR_APIC_INTR_DISCARDED)
561 AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
562#endif
563
564 /*
565 * For level-triggered interrupts, we set the remote IRR bit to indicate
566 * the local APIC has accepted the interrupt.
567 *
568 * For edge-triggered interrupts, we should not clear the IRR bit as it
569 * should remain intact to reflect the state of the interrupt line.
570 * The device will explicitly transition to inactive state via the
571 * ioapicSetIrq() callback.
572 */
573 if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
574 && rc == VINF_SUCCESS)
575 {
576 Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
577 pThis->au64RedirTable[idxRte] |= IOAPIC_RTE_REMOTE_IRR;
578 STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
579 }
580 }
581}
582
583
584/**
585 * Gets the redirection table entry.
586 *
587 * @returns The redirection table entry.
588 * @param pThis The shared I/O APIC device state.
589 * @param uIndex The index value.
590 */
591DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
592{
593 uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
594 AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
595 ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
596 UINT32_MAX);
597 uint32_t uValue;
598 if (!(uIndex & 1))
599 uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
600 else
601 uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
602
603 LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
604 return uValue;
605}
606
607
608/**
609 * Sets the redirection table entry.
610 *
611 * @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
612 * @param pDevIns The device instance.
613 * @param pThis The shared I/O APIC device state.
614 * @param pThisCC The I/O APIC device state for the current context.
615 * @param uIndex The index value.
616 * @param uValue The value to set.
617 */
618static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
619 uint32_t uIndex, uint32_t uValue)
620{
621 uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
622 AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
623 ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
624 VINF_SUCCESS);
625
626 VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
627 if (rc == VINF_SUCCESS)
628 {
629 /*
630 * Write the low or high 32-bit value into the specified 64-bit RTE register,
631 * update only the valid, writable bits.
632 *
633 * We need to preserve the read-only bits as it can have dire consequences
634 * otherwise, see @bugref{8386#c24}.
635 */
636 uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
637 if (!(uIndex & 1))
638 {
639 uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
640 uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) | u32RtePreserveLo;
641 uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
642 pThis->au64RedirTable[idxRte] = u64RteHi | u32RteNewLo;
643 }
644 else
645 {
646 uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
647 uint32_t const u32RteLo = RT_LO_U32(u64Rte);
648 uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) | u32RtePreserveHi) << 32);
649 pThis->au64RedirTable[idxRte] = u64RteNewHi | u32RteLo;
650 }
651
652 /*
653 * Signal the next pending interrupt for this RTE.
654 */
655 uint32_t const uPinMask = UINT32_C(1) << idxRte;
656 if (pThis->uIrr & uPinMask)
657 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte);
658
659 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
660 LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
661 }
662 else
663 STAM_COUNTER_INC(&pThis->StatSetRteContention);
664
665 return rc;
666}
667
668
669/**
670 * Gets the data register.
671 *
672 * @returns The data value.
673 * @param pThis The shared I/O APIC device state.
674 */
675static uint32_t ioapicGetData(PCIOAPIC pThis)
676{
677 uint8_t const uIndex = pThis->u8Index;
678 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
679 if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
680 && uIndex <= pThis->u8LastRteRegIdx)
681 return ioapicGetRedirTableEntry(pThis, uIndex);
682
683 uint32_t uValue;
684 switch (uIndex)
685 {
686 case IOAPIC_INDIRECT_INDEX_ID:
687 uValue = ioapicGetId(pThis);
688 break;
689
690 case IOAPIC_INDIRECT_INDEX_VERSION:
691 uValue = ioapicGetVersion(pThis);
692 break;
693
694 case IOAPIC_INDIRECT_INDEX_ARB:
695 if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
696 {
697 uValue = ioapicGetArb();
698 break;
699 }
700 RT_FALL_THRU();
701
702 default:
703 uValue = UINT32_C(0xffffffff);
704 Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
705 break;
706 }
707 return uValue;
708}
709
710
711/**
712 * Sets the data register.
713 *
714 * @returns Strict VBox status code.
715 * @param pDevIns The device instance.
716 * @param pThis The shared I/O APIC device state.
717 * @param pThisCC The I/O APIC device state for the current context.
718 * @param uValue The value to set.
719 */
720static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
721{
722 uint8_t const uIndex = pThis->u8Index;
723 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
724 LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
725
726 if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
727 && uIndex <= pThis->u8LastRteRegIdx)
728 return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
729
730 if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
731 ioapicSetId(pThis, uValue);
732 else
733 Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
734
735 return VINF_SUCCESS;
736}
737
738
739/**
740 * @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
741 */
742static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
743{
744 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
745 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
746 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
747 LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
748
749 bool fRemoteIrrCleared = false;
750 VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
751 if (rc == VINF_SUCCESS)
752 {
753 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
754 {
755 uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
756 if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
757 {
758#ifdef DEBUG_ramshankar
759 /* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
760 Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
761#endif
762 pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
763 fRemoteIrrCleared = true;
764 STAM_COUNTER_INC(&pThis->StatEoiReceived);
765 Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
766
767 /*
768 * Signal the next pending interrupt for this RTE.
769 */
770 uint32_t const uPinMask = UINT32_C(1) << idxRte;
771 if (pThis->uIrr & uPinMask)
772 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte);
773 }
774 }
775
776 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
777 AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
778 }
779 else
780 STAM_COUNTER_INC(&pThis->StatEoiContention);
781
782 return rc;
783}
784
785
786/**
787 * @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
788 */
789static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
790{
791#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
792 pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
793 pThis->uIrr |= a_PinMask; \
794 ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \
795 } while (0)
796
797 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
798 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
799 LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
800
801 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
802
803 if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
804 {
805 int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
806 AssertRC(rc);
807
808 uint8_t const idxRte = iIrq;
809 uint32_t const uPinMask = UINT32_C(1) << idxRte;
810 uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
811 uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
812
813 bool fActive = RT_BOOL(iLevel & 1);
814 /** @todo Polarity is busted elsewhere, we need to fix that
815 * first. See @bugref{8386#c7}. */
816#if 0
817 uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
818 fActive ^= u8Polarity; */
819#endif
820 if (!fActive)
821 {
822 pThis->uIrr &= ~uPinMask;
823 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
824 return;
825 }
826
827 bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
828 uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
829 if (!fFlipFlop)
830 {
831 if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
832 {
833 /*
834 * For edge-triggered interrupts, we need to act only on a low to high edge transition.
835 * See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
836 */
837 if (!uPrevIrr)
838 IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
839 else
840 {
841 STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
842 Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
843 }
844 }
845 else
846 {
847 Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
848
849 /*
850 * For level-triggered interrupts, redundant interrupts are not a problem
851 * and will eventually be delivered anyway after an EOI, but our PDM devices
852 * should not typically call us with no change to the level.
853 */
854 if (!uPrevIrr)
855 { /* likely */ }
856 else
857 {
858 STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
859 Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
860 }
861
862 IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
863 }
864 }
865 else
866 {
867 /*
868 * The device is flip-flopping the interrupt line, which implies we should de-assert
869 * and assert the interrupt line. The interrupt line is left in the asserted state
870 * after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
871 * hence just the assert is done.
872 */
873 IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
874 }
875
876 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
877 }
878#undef IOAPIC_ASSERT_IRQ
879}
880
881
882/**
883 * @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
884 */
885static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
886{
887 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
888 LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
889
890 XAPICINTR ApicIntr;
891 RT_ZERO(ApicIntr);
892
893#ifdef VBOX_WITH_IOMMU_AMD
894 /*
895 * The MSI may need to be remapped (or discarded) if an IOMMU is present.
896 */
897 MSIMSG MsiOut;
898 Assert(PCIBDF_IS_VALID(uBusDevFn));
899 int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
900 if (RT_SUCCESS(rcRemap))
901 ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
902 else
903 {
904 if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
905 Log3(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping denied. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
906 else
907 Log(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping failed. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
908 return;
909 }
910#else
911 NOREF(uBusDevFn);
912 ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
913#endif
914
915 /*
916 * Deliver to the local APIC via the system/3-wire-APIC bus.
917 */
918 int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
919 ApicIntr.u8Dest,
920 ApicIntr.u8DestMode,
921 ApicIntr.u8DeliveryMode,
922 ApicIntr.u8Vector,
923 0 /* u8Polarity - N/A */,
924 ApicIntr.u8TriggerMode,
925 uTagSrc);
926 /* Can't reschedule to R3. */
927 Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
928}
929
930
931/**
932 * @callback_method_impl{FNIOMMMIONEWREAD}
933 */
934static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
935{
936 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
937 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
938 Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
939 RT_NOREF_PV(pvUser);
940
941 VBOXSTRICTRC rc = VINF_SUCCESS;
942 uint32_t *puValue = (uint32_t *)pv;
943 uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
944 switch (offReg)
945 {
946 case IOAPIC_DIRECT_OFF_INDEX:
947 *puValue = ioapicGetIndex(pThis);
948 break;
949
950 case IOAPIC_DIRECT_OFF_DATA:
951 *puValue = ioapicGetData(pThis);
952 break;
953
954 default:
955 Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
956 rc = VINF_IOM_MMIO_UNUSED_FF;
957 break;
958 }
959
960 LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
961 return rc;
962}
963
964
965/**
966 * @callback_method_impl{FNIOMMMIONEWWRITE}
967 */
968static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
969{
970 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
971 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
972 RT_NOREF_PV(pvUser);
973
974 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
975
976 Assert(!(off & 3));
977 Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
978
979 VBOXSTRICTRC rc = VINF_SUCCESS;
980 uint32_t const uValue = *(uint32_t const *)pv;
981 uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
982
983 LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
984 switch (offReg)
985 {
986 case IOAPIC_DIRECT_OFF_INDEX:
987 ioapicSetIndex(pThis, uValue);
988 break;
989
990 case IOAPIC_DIRECT_OFF_DATA:
991 rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
992 break;
993
994 case IOAPIC_DIRECT_OFF_EOI:
995 if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
996 rc = ioapicSetEoi(pDevIns, uValue);
997 else
998 Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
999 break;
1000
1001 default:
1002 Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1003 break;
1004 }
1005
1006 return rc;
1007}
1008
1009
1010#ifdef IN_RING3
1011
1012/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1013static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1014{
1015 RT_NOREF(pDesc);
1016 pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1017 return VINF_SUCCESS;
1018}
1019
1020
1021/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1022static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1023{
1024 RT_NOREF(pDesc, pfMask);
1025 ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1026 return VINF_SUCCESS;
1027}
1028
1029
1030/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1031static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1032{
1033 RT_NOREF(pDesc);
1034 pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1035 return VINF_SUCCESS;
1036}
1037
1038
1039/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1040static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1041{
1042 PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1043 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1044 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1045 RT_NOREF(pDesc, pfMask);
1046 return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1047}
1048
1049
1050/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1051static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1052{
1053 PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1054 RT_NOREF(pDesc);
1055 pValue->u32 = ioapicGetVersion(pThis);
1056 return VINF_SUCCESS;
1057}
1058
1059
1060/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1061static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1062{
1063 RT_NOREF(pvUser, pDesc);
1064 pValue->u32 = ioapicGetArb();
1065 return VINF_SUCCESS;
1066}
1067
1068
1069/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1070static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1071{
1072 PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1073 Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1074 pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1075 return VINF_SUCCESS;
1076}
1077
1078
1079/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1080static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1081{
1082 RT_NOREF(pfMask);
1083 PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1084 /* No locks, no checks, just do it. */
1085 Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1086 pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1087 return VINF_SUCCESS;
1088}
1089
1090
1091/** IOREDTBLn sub fields. */
1092static DBGFREGSUBFIELD const g_aRteSubs[] =
1093{
1094 { "vector", 0, 8, 0, 0, NULL, NULL },
1095 { "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1096 { "dest_mode", 11, 1, 0, 0, NULL, NULL },
1097 { "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1098 { "polarity", 13, 1, 0, 0, NULL, NULL },
1099 { "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1100 { "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1101 { "mask", 16, 1, 0, 0, NULL, NULL },
1102 { "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1103 { "dest", 56, 8, 0, 0, NULL, NULL },
1104 DBGFREGSUBFIELD_TERMINATOR()
1105};
1106
1107
1108/** Register descriptors for DBGF. */
1109static DBGFREGDESC const g_aRegDesc[] =
1110{
1111 { "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1112 { "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1113 { "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1114 { "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1115 { "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1116 { "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1117 { "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1118 { "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1119 { "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1120 { "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1121 { "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1122 { "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1123 { "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1124 { "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1125 { "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1126 { "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1127 { "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1128 { "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1129 { "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1130 { "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1131 { "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1132 { "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1133 { "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1134 { "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1135 { "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1136 { "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1137 { "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1138 { "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1139 DBGFREGDESC_TERMINATOR()
1140};
1141
1142
1143/**
1144 * @callback_method_impl{FNDBGFHANDLERDEV}
1145 */
1146static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1147{
1148 RT_NOREF(pszArgs);
1149 PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1150 LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1151
1152 pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1153
1154 uint32_t const uId = ioapicGetId(pThis);
1155 pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1156 pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1157
1158 uint32_t const uVer = ioapicGetVersion(pThis);
1159 pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1160 pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1161 pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1162 pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1163
1164 if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1165 {
1166 uint32_t const uArb = ioapicGetArb();
1167 pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1168 pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1169 }
1170
1171 pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1172
1173 pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1174 pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1175
1176 uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1177 for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1178 {
1179 static const char * const s_apszDeliveryModes[] =
1180 {
1181 "Fixed ",
1182 "LowPri",
1183 "SMI ",
1184 "Rsvd ",
1185 "NMI ",
1186 "INIT ",
1187 "Rsvd ",
1188 "ExtINT"
1189 };
1190
1191 const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1192 const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1193 const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1194 const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1195 const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1196 const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1197 const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1198 const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1199 const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1200 Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1201 const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1202 const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1203
1204 pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1205 idxRte,
1206 pszDestMode,
1207 uDest,
1208 uMask,
1209 (pThis->uIrr >> idxRte) & 1,
1210 pszTriggerMode,
1211 uRemoteIrr,
1212 pszPolarity,
1213 pszDeliveryStatus,
1214 pszDeliveryMode,
1215 uVector,
1216 u64Rte);
1217 }
1218}
1219
1220
1221/**
1222 * @copydoc FNSSMDEVSAVEEXEC
1223 */
1224static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1225{
1226 PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1227 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1228 LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1229
1230 pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1231 pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1232 pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1233 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1234 pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1235
1236 return VINF_SUCCESS;
1237}
1238
1239
1240/**
1241 * @copydoc FNSSMDEVLOADEXEC
1242 */
1243static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1244{
1245 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1246 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1247 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1248
1249 Assert(uPass == SSM_PASS_FINAL);
1250 NOREF(uPass);
1251
1252 /* Weed out invalid versions. */
1253 if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1254 && uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1255 {
1256 LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1257 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1258 }
1259
1260 if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1261 pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1262
1263 pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1264 pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1265 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1266 pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1267
1268 return VINF_SUCCESS;
1269}
1270
1271
1272/**
1273 * @interface_method_impl{PDMDEVREG,pfnReset}
1274 */
1275static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1276{
1277 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1278 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1279 LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1280
1281 /* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1282 IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1283
1284 pThis->uIrr = 0;
1285 pThis->u8Index = 0;
1286 pThis->u8Id = 0;
1287
1288 for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1289 {
1290 pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1291 pThis->au32TagSrc[idxRte] = 0;
1292 }
1293
1294 IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1295}
1296
1297
1298/**
1299 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1300 */
1301static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1302{
1303 PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1304 LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1305
1306 pThisRC->pIoApicHlp += offDelta;
1307}
1308
1309
1310/**
1311 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1312 */
1313static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1314{
1315 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1316 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1317 LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1318
1319# ifndef IOAPIC_WITH_PDM_CRITSECT
1320 /*
1321 * Destroy the RTE critical section.
1322 */
1323 if (PDMCritSectIsInitialized(&pThis->CritSect))
1324 PDMR3CritSectDelete(&pThis->CritSect);
1325# else
1326 RT_NOREF_PV(pThis);
1327# endif
1328
1329 return VINF_SUCCESS;
1330}
1331
1332
1333/**
1334 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1335 */
1336static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1337{
1338 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1339 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1340 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1341 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1342 LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1343 Assert(iInstance == 0); RT_NOREF(iInstance);
1344
1345 /*
1346 * Validate and read the configuration.
1347 */
1348 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs|ChipType", "");
1349
1350 /* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1351 upsets some guest which we haven't yet tested. */
1352 uint32_t cCpus;
1353 int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1354 if (RT_FAILURE(rc))
1355 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1356 pThis->cCpus = (uint8_t)cCpus;
1357
1358 char szChipType[16];
1359 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1360 if (RT_FAILURE(rc))
1361 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1362
1363 if (!strcmp(szChipType, "ICH9"))
1364 {
1365 /* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1366 pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1367 pThis->u8IdMask = 0xff;
1368 pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1369 pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1370 pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1371 pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1372 }
1373 else if (!strcmp(szChipType, "82093AA"))
1374 {
1375 /* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1376 pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1377 pThis->u8IdMask = 0x0f;
1378 pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1379 pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1380 pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1381 pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1382 }
1383 else if (!strcmp(szChipType, "82379AB"))
1384 {
1385 /* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1386 /* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1387 pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1388 pThis->u8IdMask = 0x0f;
1389 pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1390 pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1391 pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1392 pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1393 }
1394 else
1395 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1396 N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1397 Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled | pDevIns->fRCEnabled, szChipType));
1398
1399 /*
1400 * We will use our own critical section for the IOAPIC device.
1401 */
1402 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1403 AssertRCReturn(rc, rc);
1404
1405# ifndef IOAPIC_WITH_PDM_CRITSECT
1406 /*
1407 * Setup the critical section to protect concurrent writes to the RTEs.
1408 */
1409 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1410 AssertRCReturn(rc, rc);
1411# endif
1412
1413 /*
1414 * Register the IOAPIC.
1415 */
1416 PDMIOAPICREG IoApicReg;
1417 IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1418 IoApicReg.pfnSetIrq = ioapicSetIrq;
1419 IoApicReg.pfnSendMsi = ioapicSendMsi;
1420 IoApicReg.pfnSetEoi = ioapicSetEoi;
1421 IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1422 rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1423 AssertRCReturn(rc, rc);
1424
1425 /*
1426 * Register MMIO region.
1427 */
1428 rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1429 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1430 AssertRCReturn(rc, rc);
1431
1432 /*
1433 * Register the saved state.
1434 */
1435 rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1436 AssertRCReturn(rc, rc);
1437
1438 /*
1439 * Register debugger info item.
1440 */
1441 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1442 AssertRCReturn(rc, rc);
1443
1444 /*
1445 * Register debugger register access.
1446 */
1447 rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1448 AssertRCReturn(rc, rc);
1449
1450# ifdef VBOX_WITH_STATISTICS
1451 /*
1452 * Statistics.
1453 */
1454 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1455 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1456 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1457 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1458
1459 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1460 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1461 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1462 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1463
1464 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1465 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1466 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1467
1468 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1469 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1470
1471 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1472 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1473# endif
1474
1475 /*
1476 * Init. the device state.
1477 */
1478 LogRel(("IOAPIC: Using implementation 2.0! Chipset type %s\n", szChipType));
1479 ioapicR3Reset(pDevIns);
1480
1481 return VINF_SUCCESS;
1482}
1483
1484#else /* !IN_RING3 */
1485
1486/**
1487 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1488 */
1489static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1490{
1491 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1492 PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1493 PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1494
1495 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1496 AssertRCReturn(rc, rc);
1497
1498 PDMIOAPICREG IoApicReg;
1499 IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1500 IoApicReg.pfnSetIrq = ioapicSetIrq;
1501 IoApicReg.pfnSendMsi = ioapicSendMsi;
1502 IoApicReg.pfnSetEoi = ioapicSetEoi;
1503 IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1504 rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1505 AssertRCReturn(rc, rc);
1506
1507 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /*pvUser*/);
1508 AssertRCReturn(rc, rc);
1509
1510 return VINF_SUCCESS;
1511}
1512
1513#endif /* !IN_RING3 */
1514
1515/**
1516 * IO APIC device registration structure.
1517 */
1518const PDMDEVREG g_DeviceIOAPIC =
1519{
1520 /* .u32Version = */ PDM_DEVREG_VERSION,
1521 /* .uReserved0 = */ 0,
1522 /* .szName = */ "ioapic",
1523 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE
1524 | PDM_DEVREG_FLAGS_REQUIRE_R0 | PDM_DEVREG_FLAGS_REQUIRE_RC,
1525 /* .fClass = */ PDM_DEVREG_CLASS_PIC,
1526 /* .cMaxInstances = */ 1,
1527 /* .uSharedVersion = */ 42,
1528 /* .cbInstanceShared = */ sizeof(IOAPIC),
1529 /* .cbInstanceCC = */ sizeof(IOAPICCC),
1530 /* .cbInstanceRC = */ sizeof(IOAPICRC),
1531 /* .cMaxPciDevices = */ 0,
1532 /* .cMaxMsixVectors = */ 0,
1533 /* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1534#if defined(IN_RING3)
1535 /* .pszRCMod = */ "VBoxDDRC.rc",
1536 /* .pszR0Mod = */ "VBoxDDR0.r0",
1537 /* .pfnConstruct = */ ioapicR3Construct,
1538 /* .pfnDestruct = */ ioapicR3Destruct,
1539 /* .pfnRelocate = */ ioapicR3Relocate,
1540 /* .pfnMemSetup = */ NULL,
1541 /* .pfnPowerOn = */ NULL,
1542 /* .pfnReset = */ ioapicR3Reset,
1543 /* .pfnSuspend = */ NULL,
1544 /* .pfnResume = */ NULL,
1545 /* .pfnAttach = */ NULL,
1546 /* .pfnDetach = */ NULL,
1547 /* .pfnQueryInterface = */ NULL,
1548 /* .pfnInitComplete = */ NULL,
1549 /* .pfnPowerOff = */ NULL,
1550 /* .pfnSoftReset = */ NULL,
1551 /* .pfnReserved0 = */ NULL,
1552 /* .pfnReserved1 = */ NULL,
1553 /* .pfnReserved2 = */ NULL,
1554 /* .pfnReserved3 = */ NULL,
1555 /* .pfnReserved4 = */ NULL,
1556 /* .pfnReserved5 = */ NULL,
1557 /* .pfnReserved6 = */ NULL,
1558 /* .pfnReserved7 = */ NULL,
1559#elif defined(IN_RING0)
1560 /* .pfnEarlyConstruct = */ NULL,
1561 /* .pfnConstruct = */ ioapicRZConstruct,
1562 /* .pfnDestruct = */ NULL,
1563 /* .pfnFinalDestruct = */ NULL,
1564 /* .pfnRequest = */ NULL,
1565 /* .pfnReserved0 = */ NULL,
1566 /* .pfnReserved1 = */ NULL,
1567 /* .pfnReserved2 = */ NULL,
1568 /* .pfnReserved3 = */ NULL,
1569 /* .pfnReserved4 = */ NULL,
1570 /* .pfnReserved5 = */ NULL,
1571 /* .pfnReserved6 = */ NULL,
1572 /* .pfnReserved7 = */ NULL,
1573#elif defined(IN_RC)
1574 /* .pfnConstruct = */ ioapicRZConstruct,
1575 /* .pfnReserved0 = */ NULL,
1576 /* .pfnReserved1 = */ NULL,
1577 /* .pfnReserved2 = */ NULL,
1578 /* .pfnReserved3 = */ NULL,
1579 /* .pfnReserved4 = */ NULL,
1580 /* .pfnReserved5 = */ NULL,
1581 /* .pfnReserved6 = */ NULL,
1582 /* .pfnReserved7 = */ NULL,
1583#else
1584# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1585#endif
1586 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
1587};
1588
1589
1590#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1591
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