DevIoApic.cpp@ 84909

Last change on this file since 84909 was 84868, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 DevIoAcpi: Darwin build fix.
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1	/* $Id: DevIoApic.cpp 84868 2020-06-18 09:11:33Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30	#include <iprt/string.h>
31
32
33	/*********************************************************************************************************************************
34	* Defined Constants And Macros *
35	*********************************************************************************************************************************/
36	/** The current IO APIC saved state version. */
37	#define IOAPIC_SAVED_STATE_VERSION 2
38	/** The saved state version used by VirtualBox 5.0 and
39	* earlier. */
40	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
41
42	/** Implementation specified by the "Intel I/O Controller Hub 9
43	* (ICH9) Family" */
44	#define IOAPIC_VERSION_ICH9 0x20
45	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
46	Controller" */
47	#define IOAPIC_VERSION_82093AA 0x11
48
49	/** The default MMIO base physical address. */
50	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
51	/** The size of the MMIO range. */
52	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
53	/** The mask for getting direct registers from physical address. */
54	#define IOAPIC_MMIO_REG_MASK 0xff
55
56	/** The number of interrupt input pins. */
57	#define IOAPIC_NUM_INTR_PINS 24
58	/** Maximum redirection entires. */
59	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
60	/** Reduced RTEs used by SIO.A (82379AB). */
61	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
62
63	/** Version register - Gets the version. */
64	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
65	/** Version register - Gets the maximum redirection entry. */
66	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
67	/** Version register - Gets whether Pin Assertion Register (PRQ) is
68	* supported. */
69	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
70
71	/** Index register - Valid write mask. */
72	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
73
74	/** Arbitration register - Gets the ID. */
75	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
76
77	/** ID register - Gets the ID. */
78	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
79
80	/** Redirection table entry - Vector. */
81	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
82	/** Redirection table entry - Delivery mode. */
83	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
84	/** Redirection table entry - Destination mode. */
85	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
86	/** Redirection table entry - Delivery status. */
87	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
88	/** Redirection table entry - Interrupt input pin polarity. */
89	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
90	/** Redirection table entry - Remote IRR. */
91	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
92	/** Redirection table entry - Trigger Mode. */
93	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
94	/** Redirection table entry - the mask bit number. */
95	#define IOAPIC_RTE_MASK_BIT 16
96	/** Redirection table entry - the mask. */
97	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
98	/** Redirection table entry - Extended Destination ID. */
99	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
100	/** Redirection table entry - Destination. */
101	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
102
103	/** Redirection table entry - Gets the destination. */
104	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
105	/** Redirection table entry - Gets the mask flag. */
106	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
107	/** Redirection table entry - Checks whether it's masked. */
108	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
109	/** Redirection table entry - Gets the trigger mode. */
110	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
111	/** Redirection table entry - Gets the remote IRR flag. */
112	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
113	/** Redirection table entry - Gets the interrupt pin polarity. */
114	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
115	/** Redirection table entry - Gets the delivery status. */
116	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
117	/** Redirection table entry - Gets the destination mode. */
118	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
119	/** Redirection table entry - Gets the delivery mode. */
120	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
121	/** Redirection table entry - Gets the vector. */
122	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
123
124	/** Redirection table entry - Valid write mask for 82093AA. */
125	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
126	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
127	\| IOAPIC_RTE_VECTOR)
128	/** Redirection table entry - Valid read mask for 82093AA. */
129	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
130	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
131	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
132
133	/** Redirection table entry - Valid write mask for ICH9. */
134	/** @note The remote IRR bit has been reverted to read-only as it turns out the
135	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
136	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
137	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
138	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
139	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
140	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
141	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
142	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
143	\| IOAPIC_RTE_VECTOR)
144
145	/** Redirection table entry - Trigger mode edge. */
146	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
147	/** Redirection table entry - Trigger mode level. */
148	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
149	/** Redirection table entry - Destination mode physical. */
150	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
151	/** Redirection table entry - Destination mode logical. */
152	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
153
154
155	/** Index of indirect registers in the I/O APIC register table. */
156	#define IOAPIC_INDIRECT_INDEX_ID 0x0
157	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
158	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
159	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
160	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
161	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
162
163	/** Offset of direct registers in the I/O APIC MMIO space. */
164	#define IOAPIC_DIRECT_OFF_INDEX 0x00
165	#define IOAPIC_DIRECT_OFF_DATA 0x10
166	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
167
168	/** The I/O APIC's Bus:Device:Function. */
169	#define IOAPIC_BUS_DEV_FN NIL_PCIBDF
170
171	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
172	#define IOAPIC_WITH_PDM_CRITSECT
173	#ifdef IOAPIC_WITH_PDM_CRITSECT
174	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
175	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
176	#else
177	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
178	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
179	#endif
180
181
182	/*********************************************************************************************************************************
183	* Structures and Typedefs *
184	*********************************************************************************************************************************/
185	/**
186	* The shared I/O APIC device state.
187	*/
188	typedef struct IOAPIC
189	{
190	/** The ID register. */
191	uint8_t volatile u8Id;
192	/** The index register. */
193	uint8_t volatile u8Index;
194	/** Number of CPUs. */
195	uint8_t cCpus;
196	/** I/O APIC version. */
197	uint8_t u8ApicVer;
198	/** I/O APIC ID mask. */
199	uint8_t u8IdMask;
200	/** Maximum Redirection Table Entry (RTE) Entry. */
201	uint8_t u8MaxRte;
202	/** Last valid RTE indirect register index. */
203	uint8_t u8LastRteRegIdx;
204	/* Alignment padding. */
205	uint8_t u8Padding0[1];
206	/** Redirection table entry - Valid write mask. */
207	uint64_t u64RteWriteMask;
208	/** Redirection table entry - Valid read mask. */
209	uint64_t u64RteReadMask;
210
211	/** The redirection table registers. */
212	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
213	/** The IRQ tags and source IDs for each pin (tracing purposes). */
214	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
215
216	/** The internal IRR reflecting state of the interrupt lines. */
217	uint32_t uIrr;
218	/** Alignment padding. */
219	uint32_t u32Padding2;
220
221	#ifndef IOAPIC_WITH_PDM_CRITSECT
222	/** The critsect for updating to the RTEs. */
223	PDMCRITSECT CritSect;
224	#endif
225
226	/** The MMIO region. */
227	IOMMMIOHANDLE hMmio;
228
229	#ifdef VBOX_WITH_STATISTICS
230	/** Number of MMIO reads in RZ. */
231	STAMCOUNTER StatMmioReadRZ;
232	/** Number of MMIO reads in R3. */
233	STAMCOUNTER StatMmioReadR3;
234
235	/** Number of MMIO writes in RZ. */
236	STAMCOUNTER StatMmioWriteRZ;
237	/** Number of MMIO writes in R3. */
238	STAMCOUNTER StatMmioWriteR3;
239
240	/** Number of SetIrq calls in RZ. */
241	STAMCOUNTER StatSetIrqRZ;
242	/** Number of SetIrq calls in R3. */
243	STAMCOUNTER StatSetIrqR3;
244
245	/** Number of SetEoi calls in RZ. */
246	STAMCOUNTER StatSetEoiRZ;
247	/** Number of SetEoi calls in R3. */
248	STAMCOUNTER StatSetEoiR3;
249
250	/** Number of redundant edge-triggered interrupts. */
251	STAMCOUNTER StatRedundantEdgeIntr;
252	/** Number of redundant level-triggered interrupts. */
253	STAMCOUNTER StatRedundantLevelIntr;
254	/** Number of suppressed level-triggered interrupts (by remote IRR). */
255	STAMCOUNTER StatSuppressedLevelIntr;
256	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
257	STAMCOUNTER StatEoiContention;
258	/** Number of returns to ring-3 due to Set RTE lock contention. */
259	STAMCOUNTER StatSetRteContention;
260	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
261	STAMCOUNTER StatLevelIrqSent;
262	/** Number of EOIs received for level-triggered interrupts from the local
263	* APIC(s). */
264	STAMCOUNTER StatEoiReceived;
265	#endif
266	} IOAPIC;
267	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
268	/** Pointer to shared IOAPIC data. */
269	typedef IOAPIC *PIOAPIC;
270	/** Pointer to const shared IOAPIC data. */
271	typedef IOAPIC const *PCIOAPIC;
272
273
274	/**
275	* The I/O APIC device state for ring-3.
276	*/
277	typedef struct IOAPICR3
278	{
279	/** The IOAPIC helpers. */
280	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
281	} IOAPICR3;
282	/** Pointer to the I/O APIC device state for ring-3. */
283	typedef IOAPICR3 *PIOAPICR3;
284
285
286	/**
287	* The I/O APIC device state for ring-0.
288	*/
289	typedef struct IOAPICR0
290	{
291	/** The IOAPIC helpers. */
292	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
293	} IOAPICR0;
294	/** Pointer to the I/O APIC device state for ring-0. */
295	typedef IOAPICR0 *PIOAPICR0;
296
297
298	/**
299	* The I/O APIC device state for raw-mode.
300	*/
301	typedef struct IOAPICRC
302	{
303	/** The IOAPIC helpers. */
304	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
305	} IOAPICRC;
306	/** Pointer to the I/O APIC device state for raw-mode. */
307	typedef IOAPICRC *PIOAPICRC;
308
309
310	/** The I/O APIC device state for the current context. */
311	typedef CTX_SUFF(IOAPIC) IOAPICCC;
312	/** Pointer to the I/O APIC device state for the current context. */
313	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
314
315
316	/**
317	* xAPIC interrupt.
318	*/
319	typedef struct XAPICINTR
320	{
321	/** The interrupt vector. */
322	uint8_t u8Vector;
323	/** The destination (mask or ID). */
324	uint8_t u8Dest;
325	/** The destination mode. */
326	uint8_t u8DestMode;
327	/** Delivery mode. */
328	uint8_t u8DeliveryMode;
329	/** Trigger mode. */
330	uint8_t u8TriggerMode;
331	/** Redirection hint. */
332	uint8_t u8RedirHint;
333	/** Polarity. */
334	uint8_t u8Polarity;
335	/** Padding. */
336	uint8_t abPadding0;
337	} XAPICINTR;
338	/** Pointer to an I/O xAPIC interrupt struct. */
339	typedef XAPICINTR *PXAPICINTR;
340	/** Pointer to a const xAPIC interrupt struct. */
341	typedef XAPICINTR const *PCXAPICINTR;
342
343
344	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
345
346	/**
347	* Gets the arbitration register.
348	*
349	* @returns The arbitration.
350	*/
351	DECLINLINE(uint32_t) ioapicGetArb(void)
352	{
353	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
354	return 0;
355	}
356
357
358	/**
359	* Gets the version register.
360	*
361	* @returns The version.
362	*/
363	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
364	{
365	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
366	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
367	return uValue;
368	}
369
370
371	/**
372	* Sets the ID register.
373	*
374	* @param pThis The shared I/O APIC device state.
375	* @param uValue The value to set.
376	*/
377	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
378	{
379	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
380	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
381	}
382
383
384	/**
385	* Gets the ID register.
386	*
387	* @returns The ID.
388	* @param pThis The shared I/O APIC device state.
389	*/
390	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
391	{
392	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
393	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
394	return uValue;
395	}
396
397
398	/**
399	* Sets the index register.
400	*
401	* @param pThis The shared I/O APIC device state.
402	* @param uValue The value to set.
403	*/
404	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
405	{
406	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
407	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
408	}
409
410
411	/**
412	* Gets the index register.
413	*
414	* @returns The index value.
415	*/
416	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
417	{
418	uint32_t const uValue = pThis->u8Index;
419	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
420	return uValue;
421	}
422
423
424	/**
425	* Converts an MSI message to an APIC interrupt.
426	*
427	* @param pMsi The MSI message to convert.
428	* @param pIntr Where to store the APIC interrupt.
429	*/
430	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
431	{
432	/*
433	* Parse the message from the physical address and data
434	* See Intel spec. 10.11.1 "Message Address Register Format".
435	* See Intel spec. 10.11.2 "Message Data Register Format".
436	*/
437	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
438	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
439	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
440
441	pIntr->u8Vector = pMsi->Data.n.u8Vector;
442	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
443	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
444	}
445
446
447	#ifdef VBOX_WITH_IOMMU_AMD
448	/**
449	* Convert an APIC interrupt to an MSI message.
450	*
451	* @param pIntr The APIC interrupt to convert.
452	* @param pMsi Where to store the MSI message.
453	*/
454	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
455	{
456	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
457	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
458	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
459	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
460
461	pMsi->Data.n.u8Vector = pIntr->u8Vector;
462	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
463	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
464
465	/* pMsi->Data.n.u1Level = ??? */
466	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
467	* possible in theory? Maybe document this more explicitly... */
468	}
469	#endif
470
471
472	/**
473	* Signals the next pending interrupt for the specified Redirection Table Entry
474	* (RTE).
475	*
476	* @param pDevIns The device instance.
477	* @param pThis The shared I/O APIC device state.
478	* @param pThisCC The I/O APIC device state for the current context.
479	* @param uBusDevFn The bus:device:function of the device initiating the IRQ.
480	* @param idxRte The index of the RTE (validated).
481	*
482	* @remarks It is the responsibility of the caller to verify that an interrupt is
483	* pending for the pin corresponding to the RTE before calling this
484	* function.
485	*/
486	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte)
487	{
488	#ifndef IOAPIC_WITH_PDM_CRITSECT
489	Assert(PDMCritSectIsOwner(&pThis->CritSect));
490	#endif
491
492	/*
493	* Ensure the interrupt isn't masked.
494	*/
495	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
496	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
497	{
498	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
499	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
500	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
501	{
502	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
503	if (u8RemoteIrr)
504	{
505	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
506	return;
507	}
508	}
509
510	XAPICINTR ApicIntr;
511	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
512	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
513	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
514	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
515	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
516	ApicIntr.u8TriggerMode = u8TriggerMode;
517	ApicIntr.u8RedirHint = 0;
518
519	#ifdef VBOX_WITH_IOMMU_AMD
520	/*
521	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
522	*/
523	MSIMSG MsiOut;
524	MSIMSG MsiIn;
525	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
526	Assert(PCIBDF_IS_VALID(uBusDevFn));
527	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, &MsiIn, &MsiOut);
528	if (RT_SUCCESS(rcRemap))
529	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
530	else
531	{
532	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
533	Log3(("IOAPIC: Interrupt (u8Vector=%#x) remapping denied. rc=%Rrc", ApicIntr.u8Vector, rcRemap));
534	else
535	Log(("IOAPIC: Interrupt (u8Vector=%#x) remapping failed. rc=%Rrc", ApicIntr.u8Vector, rcRemap));
536	return;
537	}
538	#else
539	NOREF(uBusDevFn);
540	#endif
541
542	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
543	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
544	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
545	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
546	ApicIntr.u8Vector, ApicIntr.u8Vector));
547
548	/*
549	* Deliver to the local APIC via the system/3-wire-APIC bus.
550	*/
551	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
552	ApicIntr.u8Dest,
553	ApicIntr.u8DestMode,
554	ApicIntr.u8DeliveryMode,
555	ApicIntr.u8Vector,
556	ApicIntr.u8Polarity,
557	ApicIntr.u8TriggerMode,
558	u32TagSrc);
559	/* Can't reschedule to R3. */
560	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
561	#ifdef DEBUG_ramshankar
562	if (rc == VERR_APIC_INTR_DISCARDED)
563	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
564	#endif
565
566	/*
567	* For level-triggered interrupts, we set the remote IRR bit to indicate
568	* the local APIC has accepted the interrupt.
569	*
570	* For edge-triggered interrupts, we should not clear the IRR bit as it
571	* should remain intact to reflect the state of the interrupt line.
572	* The device will explicitly transition to inactive state via the
573	* ioapicSetIrq() callback.
574	*/
575	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
576	&& rc == VINF_SUCCESS)
577	{
578	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
579	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
580	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
581	}
582	}
583	}
584
585
586	/**
587	* Gets the redirection table entry.
588	*
589	* @returns The redirection table entry.
590	* @param pThis The shared I/O APIC device state.
591	* @param uIndex The index value.
592	*/
593	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
594	{
595	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
596	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
597	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
598	UINT32_MAX);
599	uint32_t uValue;
600	if (!(uIndex & 1))
601	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
602	else
603	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
604
605	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
606	return uValue;
607	}
608
609
610	/**
611	* Sets the redirection table entry.
612	*
613	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
614	* @param pDevIns The device instance.
615	* @param pThis The shared I/O APIC device state.
616	* @param pThisCC The I/O APIC device state for the current context.
617	* @param uIndex The index value.
618	* @param uValue The value to set.
619	*/
620	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
621	uint32_t uIndex, uint32_t uValue)
622	{
623	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
624	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
625	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
626	VINF_SUCCESS);
627
628	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
629	if (rc == VINF_SUCCESS)
630	{
631	/*
632	* Write the low or high 32-bit value into the specified 64-bit RTE register,
633	* update only the valid, writable bits.
634	*
635	* We need to preserve the read-only bits as it can have dire consequences
636	* otherwise, see @bugref{8386#c24}.
637	*/
638	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
639	if (!(uIndex & 1))
640	{
641	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
642	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
643	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
644	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
645	}
646	else
647	{
648	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
649	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
650	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
651	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
652	}
653
654	/*
655	* Signal the next pending interrupt for this RTE.
656	*/
657	uint32_t const uPinMask = UINT32_C(1) << idxRte;
658	if (pThis->uIrr & uPinMask)
659	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte);
660
661	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
662	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
663	}
664	else
665	STAM_COUNTER_INC(&pThis->StatSetRteContention);
666
667	return rc;
668	}
669
670
671	/**
672	* Gets the data register.
673	*
674	* @returns The data value.
675	* @param pThis The shared I/O APIC device state.
676	*/
677	static uint32_t ioapicGetData(PCIOAPIC pThis)
678	{
679	uint8_t const uIndex = pThis->u8Index;
680	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
681	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
682	&& uIndex <= pThis->u8LastRteRegIdx)
683	return ioapicGetRedirTableEntry(pThis, uIndex);
684
685	uint32_t uValue;
686	switch (uIndex)
687	{
688	case IOAPIC_INDIRECT_INDEX_ID:
689	uValue = ioapicGetId(pThis);
690	break;
691
692	case IOAPIC_INDIRECT_INDEX_VERSION:
693	uValue = ioapicGetVersion(pThis);
694	break;
695
696	case IOAPIC_INDIRECT_INDEX_ARB:
697	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
698	{
699	uValue = ioapicGetArb();
700	break;
701	}
702	RT_FALL_THRU();
703
704	default:
705	uValue = UINT32_C(0xffffffff);
706	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
707	break;
708	}
709	return uValue;
710	}
711
712
713	/**
714	* Sets the data register.
715	*
716	* @returns Strict VBox status code.
717	* @param pDevIns The device instance.
718	* @param pThis The shared I/O APIC device state.
719	* @param pThisCC The I/O APIC device state for the current context.
720	* @param uValue The value to set.
721	*/
722	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
723	{
724	uint8_t const uIndex = pThis->u8Index;
725	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
726	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
727
728	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
729	&& uIndex <= pThis->u8LastRteRegIdx)
730	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
731
732	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
733	ioapicSetId(pThis, uValue);
734	else
735	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
736
737	return VINF_SUCCESS;
738	}
739
740
741	/**
742	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
743	*/
744	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
745	{
746	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
747	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
748	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
749	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
750
751	bool fRemoteIrrCleared = false;
752	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
753	if (rc == VINF_SUCCESS)
754	{
755	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
756	{
757	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
758	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
759	{
760	#ifdef DEBUG_ramshankar
761	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
762	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
763	#endif
764	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
765	fRemoteIrrCleared = true;
766	STAM_COUNTER_INC(&pThis->StatEoiReceived);
767	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
768
769	/*
770	* Signal the next pending interrupt for this RTE.
771	*/
772	uint32_t const uPinMask = UINT32_C(1) << idxRte;
773	if (pThis->uIrr & uPinMask)
774	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, IOAPIC_BUS_DEV_FN, idxRte);
775	}
776	}
777
778	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
779	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
780	}
781	else
782	STAM_COUNTER_INC(&pThis->StatEoiContention);
783
784	return rc;
785	}
786
787
788	/**
789	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
790	*/
791	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
792	{
793	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
794	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
795	pThis->uIrr \|= a_PinMask; \
796	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \
797	} while (0)
798
799	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
800	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
801	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
802
803	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
804
805	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
806	{
807	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
808	AssertRC(rc);
809
810	uint8_t const idxRte = iIrq;
811	uint32_t const uPinMask = UINT32_C(1) << idxRte;
812	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
813	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
814
815	bool fActive = RT_BOOL(iLevel & 1);
816	/** @todo Polarity is busted elsewhere, we need to fix that
817	* first. See @bugref{8386#c7}. */
818	#if 0
819	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
820	fActive ^= u8Polarity; */
821	#endif
822	if (!fActive)
823	{
824	pThis->uIrr &= ~uPinMask;
825	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
826	return;
827	}
828
829	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
830	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
831	if (!fFlipFlop)
832	{
833	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
834	{
835	/*
836	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
837	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
838	*/
839	if (!uPrevIrr)
840	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
841	else
842	{
843	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
844	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
845	}
846	}
847	else
848	{
849	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
850
851	/*
852	* For level-triggered interrupts, redundant interrupts are not a problem
853	* and will eventually be delivered anyway after an EOI, but our PDM devices
854	* should not typically call us with no change to the level.
855	*/
856	if (!uPrevIrr)
857	{ /* likely */ }
858	else
859	{
860	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
861	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
862	}
863
864	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
865	}
866	}
867	else
868	{
869	/*
870	* The device is flip-flopping the interrupt line, which implies we should de-assert
871	* and assert the interrupt line. The interrupt line is left in the asserted state
872	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
873	* hence just the assert is done.
874	*/
875	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
876	}
877
878	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
879	}
880	#undef IOAPIC_ASSERT_IRQ
881	}
882
883
884	/**
885	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
886	*/
887	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
888	{
889	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
890	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
891
892	XAPICINTR ApicIntr;
893	RT_ZERO(ApicIntr);
894
895	#ifdef VBOX_WITH_IOMMU_AMD
896	/*
897	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
898	*/
899	MSIMSG MsiOut;
900	Assert(PCIBDF_IS_VALID(uBusDevFn));
901	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
902	if (RT_SUCCESS(rcRemap))
903	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
904	else
905	{
906	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
907	Log3(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping denied. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
908	else
909	Log(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping failed. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
910	return;
911	}
912	#else
913	NOREF(uBusDevFn);
914	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
915	#endif
916
917	/*
918	* Deliver to the local APIC via the system/3-wire-APIC bus.
919	*/
920	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
921	ApicIntr.u8Dest,
922	ApicIntr.u8DestMode,
923	ApicIntr.u8DeliveryMode,
924	ApicIntr.u8Vector,
925	0 /* u8Polarity - N/A */,
926	ApicIntr.u8TriggerMode,
927	uTagSrc);
928	/* Can't reschedule to R3. */
929	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
930	}
931
932
933	/**
934	* @callback_method_impl{FNIOMMMIONEWREAD}
935	*/
936	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
937	{
938	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
939	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
940	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
941	RT_NOREF_PV(pvUser);
942
943	VBOXSTRICTRC rc = VINF_SUCCESS;
944	uint32_t puValue = (uint32_t )pv;
945	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
946	switch (offReg)
947	{
948	case IOAPIC_DIRECT_OFF_INDEX:
949	*puValue = ioapicGetIndex(pThis);
950	break;
951
952	case IOAPIC_DIRECT_OFF_DATA:
953	*puValue = ioapicGetData(pThis);
954	break;
955
956	default:
957	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
958	rc = VINF_IOM_MMIO_UNUSED_FF;
959	break;
960	}
961
962	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
963	return rc;
964	}
965
966
967	/**
968	* @callback_method_impl{FNIOMMMIONEWWRITE}
969	*/
970	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
971	{
972	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
973	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
974	RT_NOREF_PV(pvUser);
975
976	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
977
978	Assert(!(off & 3));
979	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
980
981	VBOXSTRICTRC rc = VINF_SUCCESS;
982	uint32_t const uValue = (uint32_t const )pv;
983	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
984
985	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
986	switch (offReg)
987	{
988	case IOAPIC_DIRECT_OFF_INDEX:
989	ioapicSetIndex(pThis, uValue);
990	break;
991
992	case IOAPIC_DIRECT_OFF_DATA:
993	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
994	break;
995
996	case IOAPIC_DIRECT_OFF_EOI:
997	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
998	rc = ioapicSetEoi(pDevIns, uValue);
999	else
1000	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1001	break;
1002
1003	default:
1004	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1005	break;
1006	}
1007
1008	return rc;
1009	}
1010
1011
1012	#ifdef IN_RING3
1013
1014	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1015	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1016	{
1017	RT_NOREF(pDesc);
1018	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1019	return VINF_SUCCESS;
1020	}
1021
1022
1023	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1024	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1025	{
1026	RT_NOREF(pDesc, pfMask);
1027	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1028	return VINF_SUCCESS;
1029	}
1030
1031
1032	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1033	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1034	{
1035	RT_NOREF(pDesc);
1036	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1037	return VINF_SUCCESS;
1038	}
1039
1040
1041	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1042	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1043	{
1044	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1045	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1046	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1047	RT_NOREF(pDesc, pfMask);
1048	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1049	}
1050
1051
1052	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1053	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1054	{
1055	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1056	RT_NOREF(pDesc);
1057	pValue->u32 = ioapicGetVersion(pThis);
1058	return VINF_SUCCESS;
1059	}
1060
1061
1062	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1063	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1064	{
1065	RT_NOREF(pvUser, pDesc);
1066	pValue->u32 = ioapicGetArb();
1067	return VINF_SUCCESS;
1068	}
1069
1070
1071	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1072	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1073	{
1074	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1075	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1076	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1077	return VINF_SUCCESS;
1078	}
1079
1080
1081	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1082	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1083	{
1084	RT_NOREF(pfMask);
1085	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1086	/* No locks, no checks, just do it. */
1087	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1088	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1089	return VINF_SUCCESS;
1090	}
1091
1092
1093	/** IOREDTBLn sub fields. */
1094	static DBGFREGSUBFIELD const g_aRteSubs[] =
1095	{
1096	{ "vector", 0, 8, 0, 0, NULL, NULL },
1097	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1098	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1099	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1100	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1101	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1102	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1103	{ "mask", 16, 1, 0, 0, NULL, NULL },
1104	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1105	{ "dest", 56, 8, 0, 0, NULL, NULL },
1106	DBGFREGSUBFIELD_TERMINATOR()
1107	};
1108
1109
1110	/** Register descriptors for DBGF. */
1111	static DBGFREGDESC const g_aRegDesc[] =
1112	{
1113	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1114	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1115	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1116	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1117	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1118	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1119	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1120	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1121	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1122	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1123	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1124	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1125	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1126	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1127	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1128	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1129	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1130	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1131	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1132	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1133	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1134	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1135	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1136	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1137	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1138	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1139	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1140	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1141	DBGFREGDESC_TERMINATOR()
1142	};
1143
1144
1145	/**
1146	* @callback_method_impl{FNDBGFHANDLERDEV}
1147	*/
1148	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1149	{
1150	RT_NOREF(pszArgs);
1151	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1152	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1153
1154	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1155
1156	uint32_t const uId = ioapicGetId(pThis);
1157	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1158	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1159
1160	uint32_t const uVer = ioapicGetVersion(pThis);
1161	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1162	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1163	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1164	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1165
1166	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1167	{
1168	uint32_t const uArb = ioapicGetArb();
1169	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1170	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1171	}
1172
1173	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1174
1175	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1176	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1177
1178	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1179	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1180	{
1181	static const char * const s_apszDeliveryModes[] =
1182	{
1183	"Fixed ",
1184	"LowPri",
1185	"SMI ",
1186	"Rsvd ",
1187	"NMI ",
1188	"INIT ",
1189	"Rsvd ",
1190	"ExtINT"
1191	};
1192
1193	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1194	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1195	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1196	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1197	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1198	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1199	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1200	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1201	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1202	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1203	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1204	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1205
1206	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1207	idxRte,
1208	pszDestMode,
1209	uDest,
1210	uMask,
1211	(pThis->uIrr >> idxRte) & 1,
1212	pszTriggerMode,
1213	uRemoteIrr,
1214	pszPolarity,
1215	pszDeliveryStatus,
1216	pszDeliveryMode,
1217	uVector,
1218	u64Rte);
1219	}
1220	}
1221
1222
1223	/**
1224	* @copydoc FNSSMDEVSAVEEXEC
1225	*/
1226	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1227	{
1228	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1229	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1230	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1231
1232	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1233	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1234	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1235	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1236	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1237
1238	return VINF_SUCCESS;
1239	}
1240
1241
1242	/**
1243	* @copydoc FNSSMDEVLOADEXEC
1244	*/
1245	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1246	{
1247	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1248	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1249	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1250
1251	Assert(uPass == SSM_PASS_FINAL);
1252	NOREF(uPass);
1253
1254	/* Weed out invalid versions. */
1255	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1256	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1257	{
1258	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1259	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1260	}
1261
1262	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1263	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1264
1265	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1266	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1267	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1268	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1269
1270	return VINF_SUCCESS;
1271	}
1272
1273
1274	/**
1275	* @interface_method_impl{PDMDEVREG,pfnReset}
1276	*/
1277	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1278	{
1279	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1280	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1281	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1282
1283	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1284	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1285
1286	pThis->uIrr = 0;
1287	pThis->u8Index = 0;
1288	pThis->u8Id = 0;
1289
1290	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1291	{
1292	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1293	pThis->au32TagSrc[idxRte] = 0;
1294	}
1295
1296	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1297	}
1298
1299
1300	/**
1301	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1302	*/
1303	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1304	{
1305	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1306	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1307
1308	pThisRC->pIoApicHlp += offDelta;
1309	}
1310
1311
1312	/**
1313	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1314	*/
1315	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1316	{
1317	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1318	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1319	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1320
1321	# ifndef IOAPIC_WITH_PDM_CRITSECT
1322	/*
1323	* Destroy the RTE critical section.
1324	*/
1325	if (PDMCritSectIsInitialized(&pThis->CritSect))
1326	PDMR3CritSectDelete(&pThis->CritSect);
1327	# else
1328	RT_NOREF_PV(pThis);
1329	# endif
1330
1331	return VINF_SUCCESS;
1332	}
1333
1334
1335	/**
1336	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1337	*/
1338	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1339	{
1340	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1341	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1342	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1343	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1344	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1345	Assert(iInstance == 0); RT_NOREF(iInstance);
1346
1347	/*
1348	* Validate and read the configuration.
1349	*/
1350	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1351
1352	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1353	upsets some guest which we haven't yet tested. */
1354	uint32_t cCpus;
1355	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1356	if (RT_FAILURE(rc))
1357	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1358	pThis->cCpus = (uint8_t)cCpus;
1359
1360	char szChipType[16];
1361	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1362	if (RT_FAILURE(rc))
1363	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1364
1365	if (!strcmp(szChipType, "ICH9"))
1366	{
1367	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1368	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1369	pThis->u8IdMask = 0xff;
1370	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1371	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1372	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1373	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1374	}
1375	else if (!strcmp(szChipType, "82093AA"))
1376	{
1377	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1378	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1379	pThis->u8IdMask = 0x0f;
1380	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1381	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1382	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1383	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1384	}
1385	else if (!strcmp(szChipType, "82379AB"))
1386	{
1387	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1388	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1389	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1390	pThis->u8IdMask = 0x0f;
1391	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1392	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1393	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1394	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1395	}
1396	else
1397	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1398	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1399	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1400
1401	/*
1402	* We will use our own critical section for the IOAPIC device.
1403	*/
1404	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1405	AssertRCReturn(rc, rc);
1406
1407	# ifndef IOAPIC_WITH_PDM_CRITSECT
1408	/*
1409	* Setup the critical section to protect concurrent writes to the RTEs.
1410	*/
1411	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1412	AssertRCReturn(rc, rc);
1413	# endif
1414
1415	/*
1416	* Register the IOAPIC.
1417	*/
1418	PDMIOAPICREG IoApicReg;
1419	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1420	IoApicReg.pfnSetIrq = ioapicSetIrq;
1421	IoApicReg.pfnSendMsi = ioapicSendMsi;
1422	IoApicReg.pfnSetEoi = ioapicSetEoi;
1423	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1424	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1425	AssertRCReturn(rc, rc);
1426
1427	/*
1428	* Register MMIO region.
1429	*/
1430	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1431	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1432	AssertRCReturn(rc, rc);
1433
1434	/*
1435	* Register the saved state.
1436	*/
1437	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1438	AssertRCReturn(rc, rc);
1439
1440	/*
1441	* Register debugger info item.
1442	*/
1443	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1444	AssertRCReturn(rc, rc);
1445
1446	/*
1447	* Register debugger register access.
1448	*/
1449	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1450	AssertRCReturn(rc, rc);
1451
1452	# ifdef VBOX_WITH_STATISTICS
1453	/*
1454	* Statistics.
1455	*/
1456	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1457	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1458	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1459	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1460
1461	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1462	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1463	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1464	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1465
1466	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1467	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1468	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1469
1470	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1471	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1472
1473	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1474	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1475	# endif
1476
1477	/*
1478	* Init. the device state.
1479	*/
1480	LogRel(("IOAPIC: Using implementation 2.0! Chipset type %s\n", szChipType));
1481	ioapicR3Reset(pDevIns);
1482
1483	return VINF_SUCCESS;
1484	}
1485
1486	#else /* !IN_RING3 */
1487
1488	/**
1489	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1490	*/
1491	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1492	{
1493	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1494	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1495	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1496
1497	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1498	AssertRCReturn(rc, rc);
1499
1500	PDMIOAPICREG IoApicReg;
1501	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1502	IoApicReg.pfnSetIrq = ioapicSetIrq;
1503	IoApicReg.pfnSendMsi = ioapicSendMsi;
1504	IoApicReg.pfnSetEoi = ioapicSetEoi;
1505	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1506	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1507	AssertRCReturn(rc, rc);
1508
1509	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1510	AssertRCReturn(rc, rc);
1511
1512	return VINF_SUCCESS;
1513	}
1514
1515	#endif /* !IN_RING3 */
1516
1517	/**
1518	* IO APIC device registration structure.
1519	*/
1520	const PDMDEVREG g_DeviceIOAPIC =
1521	{
1522	/* .u32Version = */ PDM_DEVREG_VERSION,
1523	/* .uReserved0 = */ 0,
1524	/* .szName = */ "ioapic",
1525	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1526	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1527	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1528	/* .cMaxInstances = */ 1,
1529	/* .uSharedVersion = */ 42,
1530	/* .cbInstanceShared = */ sizeof(IOAPIC),
1531	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1532	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1533	/* .cMaxPciDevices = */ 0,
1534	/* .cMaxMsixVectors = */ 0,
1535	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1536	#if defined(IN_RING3)
1537	/* .pszRCMod = */ "VBoxDDRC.rc",
1538	/* .pszR0Mod = */ "VBoxDDR0.r0",
1539	/* .pfnConstruct = */ ioapicR3Construct,
1540	/* .pfnDestruct = */ ioapicR3Destruct,
1541	/* .pfnRelocate = */ ioapicR3Relocate,
1542	/* .pfnMemSetup = */ NULL,
1543	/* .pfnPowerOn = */ NULL,
1544	/* .pfnReset = */ ioapicR3Reset,
1545	/* .pfnSuspend = */ NULL,
1546	/* .pfnResume = */ NULL,
1547	/* .pfnAttach = */ NULL,
1548	/* .pfnDetach = */ NULL,
1549	/* .pfnQueryInterface = */ NULL,
1550	/* .pfnInitComplete = */ NULL,
1551	/* .pfnPowerOff = */ NULL,
1552	/* .pfnSoftReset = */ NULL,
1553	/* .pfnReserved0 = */ NULL,
1554	/* .pfnReserved1 = */ NULL,
1555	/* .pfnReserved2 = */ NULL,
1556	/* .pfnReserved3 = */ NULL,
1557	/* .pfnReserved4 = */ NULL,
1558	/* .pfnReserved5 = */ NULL,
1559	/* .pfnReserved6 = */ NULL,
1560	/* .pfnReserved7 = */ NULL,
1561	#elif defined(IN_RING0)
1562	/* .pfnEarlyConstruct = */ NULL,
1563	/* .pfnConstruct = */ ioapicRZConstruct,
1564	/* .pfnDestruct = */ NULL,
1565	/* .pfnFinalDestruct = */ NULL,
1566	/* .pfnRequest = */ NULL,
1567	/* .pfnReserved0 = */ NULL,
1568	/* .pfnReserved1 = */ NULL,
1569	/* .pfnReserved2 = */ NULL,
1570	/* .pfnReserved3 = */ NULL,
1571	/* .pfnReserved4 = */ NULL,
1572	/* .pfnReserved5 = */ NULL,
1573	/* .pfnReserved6 = */ NULL,
1574	/* .pfnReserved7 = */ NULL,
1575	#elif defined(IN_RC)
1576	/* .pfnConstruct = */ ioapicRZConstruct,
1577	/* .pfnReserved0 = */ NULL,
1578	/* .pfnReserved1 = */ NULL,
1579	/* .pfnReserved2 = */ NULL,
1580	/* .pfnReserved3 = */ NULL,
1581	/* .pfnReserved4 = */ NULL,
1582	/* .pfnReserved5 = */ NULL,
1583	/* .pfnReserved6 = */ NULL,
1584	/* .pfnReserved7 = */ NULL,
1585	#else
1586	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1587	#endif
1588	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1589	};
1590
1591
1592	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1593

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 84909

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