DevIoApic.cpp@ 85966

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1	/* $Id: DevIoApic.cpp 85966 2020-08-31 23:47:52Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - the mask bit number. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - the mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** Redirection table entry - Valid write mask for 82093AA. */
126	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
127	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
128	\| IOAPIC_RTE_VECTOR)
129	/** Redirection table entry - Valid read mask for 82093AA. */
130	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
131	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
132	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
133
134	/** Redirection table entry - Valid write mask for ICH9. */
135	/** @note The remote IRR bit has been reverted to read-only as it turns out the
136	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
139	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
140	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
141	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
142	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
143	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
144	\| IOAPIC_RTE_VECTOR)
145
146	/** Redirection table entry - Trigger mode edge. */
147	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
148	/** Redirection table entry - Trigger mode level. */
149	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
150	/** Redirection table entry - Destination mode physical. */
151	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
152	/** Redirection table entry - Destination mode logical. */
153	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
154
155
156	/** Index of indirect registers in the I/O APIC register table. */
157	#define IOAPIC_INDIRECT_INDEX_ID 0x0
158	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
159	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
160	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
161	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
162	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
163
164	/** Offset of direct registers in the I/O APIC MMIO space. */
165	#define IOAPIC_DIRECT_OFF_INDEX 0x00
166	#define IOAPIC_DIRECT_OFF_DATA 0x10
167	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
168
169	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
170	#define IOAPIC_WITH_PDM_CRITSECT
171	#ifdef IOAPIC_WITH_PDM_CRITSECT
172	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
173	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
174	#else
175	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
176	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The shared I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The ID register. */
189	uint8_t volatile u8Id;
190	/** The index register. */
191	uint8_t volatile u8Index;
192	/** Number of CPUs. */
193	uint8_t cCpus;
194	/** I/O APIC version. */
195	uint8_t u8ApicVer;
196	/** I/O APIC ID mask. */
197	uint8_t u8IdMask;
198	/** Maximum Redirection Table Entry (RTE) Entry. */
199	uint8_t u8MaxRte;
200	/** Last valid RTE indirect register index. */
201	uint8_t u8LastRteRegIdx;
202	/* Alignment padding. */
203	uint8_t u8Padding0[1];
204	/** Redirection table entry - Valid write mask. */
205	uint64_t u64RteWriteMask;
206	/** Redirection table entry - Valid read mask. */
207	uint64_t u64RteReadMask;
208
209	/** The redirection table registers. */
210	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
211	/** The IRQ tags and source IDs for each pin (tracing purposes). */
212	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
213
214	/** The internal IRR reflecting state of the interrupt lines. */
215	uint32_t uIrr;
216	/** Alignment padding. */
217	uint32_t u32Padding2;
218
219	#ifndef IOAPIC_WITH_PDM_CRITSECT
220	/** The critsect for updating to the RTEs. */
221	PDMCRITSECT CritSect;
222	#endif
223
224	/** The MMIO region. */
225	IOMMMIOHANDLE hMmio;
226
227	#ifdef VBOX_WITH_STATISTICS
228	/** Number of MMIO reads in RZ. */
229	STAMCOUNTER StatMmioReadRZ;
230	/** Number of MMIO reads in R3. */
231	STAMCOUNTER StatMmioReadR3;
232
233	/** Number of MMIO writes in RZ. */
234	STAMCOUNTER StatMmioWriteRZ;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237
238	/** Number of SetIrq calls in RZ. */
239	STAMCOUNTER StatSetIrqRZ;
240	/** Number of SetIrq calls in R3. */
241	STAMCOUNTER StatSetIrqR3;
242
243	/** Number of SetEoi calls in RZ. */
244	STAMCOUNTER StatSetEoiRZ;
245	/** Number of SetEoi calls in R3. */
246	STAMCOUNTER StatSetEoiR3;
247
248	/** Number of redundant edge-triggered interrupts. */
249	STAMCOUNTER StatRedundantEdgeIntr;
250	/** Number of redundant level-triggered interrupts. */
251	STAMCOUNTER StatRedundantLevelIntr;
252	/** Number of suppressed level-triggered interrupts (by remote IRR). */
253	STAMCOUNTER StatSuppressedLevelIntr;
254	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
255	STAMCOUNTER StatEoiContention;
256	/** Number of returns to ring-3 due to Set RTE lock contention. */
257	STAMCOUNTER StatSetRteContention;
258	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
259	STAMCOUNTER StatLevelIrqSent;
260	/** Number of EOIs received for level-triggered interrupts from the local
261	* APIC(s). */
262	STAMCOUNTER StatEoiReceived;
263	#endif
264	/** Per-vector stats. */
265	STAMCOUNTER aStatVectors[256];
266	} IOAPIC;
267	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
268	/** Pointer to shared IOAPIC data. */
269	typedef IOAPIC *PIOAPIC;
270	/** Pointer to const shared IOAPIC data. */
271	typedef IOAPIC const *PCIOAPIC;
272
273
274	/**
275	* The I/O APIC device state for ring-3.
276	*/
277	typedef struct IOAPICR3
278	{
279	/** The IOAPIC helpers. */
280	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
281	} IOAPICR3;
282	/** Pointer to the I/O APIC device state for ring-3. */
283	typedef IOAPICR3 *PIOAPICR3;
284
285
286	/**
287	* The I/O APIC device state for ring-0.
288	*/
289	typedef struct IOAPICR0
290	{
291	/** The IOAPIC helpers. */
292	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
293	} IOAPICR0;
294	/** Pointer to the I/O APIC device state for ring-0. */
295	typedef IOAPICR0 *PIOAPICR0;
296
297
298	/**
299	* The I/O APIC device state for raw-mode.
300	*/
301	typedef struct IOAPICRC
302	{
303	/** The IOAPIC helpers. */
304	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
305	} IOAPICRC;
306	/** Pointer to the I/O APIC device state for raw-mode. */
307	typedef IOAPICRC *PIOAPICRC;
308
309
310	/** The I/O APIC device state for the current context. */
311	typedef CTX_SUFF(IOAPIC) IOAPICCC;
312	/** Pointer to the I/O APIC device state for the current context. */
313	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
314
315
316	/**
317	* xAPIC interrupt.
318	*/
319	typedef struct XAPICINTR
320	{
321	/** The interrupt vector. */
322	uint8_t u8Vector;
323	/** The destination (mask or ID). */
324	uint8_t u8Dest;
325	/** The destination mode. */
326	uint8_t u8DestMode;
327	/** Delivery mode. */
328	uint8_t u8DeliveryMode;
329	/** Trigger mode. */
330	uint8_t u8TriggerMode;
331	/** Redirection hint. */
332	uint8_t u8RedirHint;
333	/** Polarity. */
334	uint8_t u8Polarity;
335	/** Padding. */
336	uint8_t abPadding0;
337	} XAPICINTR;
338	/** Pointer to an I/O xAPIC interrupt struct. */
339	typedef XAPICINTR *PXAPICINTR;
340	/** Pointer to a const xAPIC interrupt struct. */
341	typedef XAPICINTR const *PCXAPICINTR;
342
343
344	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
345
346	/**
347	* Gets the arbitration register.
348	*
349	* @returns The arbitration.
350	*/
351	DECLINLINE(uint32_t) ioapicGetArb(void)
352	{
353	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
354	return 0;
355	}
356
357
358	/**
359	* Gets the version register.
360	*
361	* @returns The version.
362	*/
363	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
364	{
365	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
366	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
367	return uValue;
368	}
369
370
371	/**
372	* Sets the ID register.
373	*
374	* @param pThis The shared I/O APIC device state.
375	* @param uValue The value to set.
376	*/
377	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
378	{
379	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
380	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
381	}
382
383
384	/**
385	* Gets the ID register.
386	*
387	* @returns The ID.
388	* @param pThis The shared I/O APIC device state.
389	*/
390	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
391	{
392	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
393	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
394	return uValue;
395	}
396
397
398	/**
399	* Sets the index register.
400	*
401	* @param pThis The shared I/O APIC device state.
402	* @param uValue The value to set.
403	*/
404	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
405	{
406	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
407	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
408	}
409
410
411	/**
412	* Gets the index register.
413	*
414	* @returns The index value.
415	*/
416	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
417	{
418	uint32_t const uValue = pThis->u8Index;
419	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
420	return uValue;
421	}
422
423
424	/**
425	* Converts an MSI message to an APIC interrupt.
426	*
427	* @param pMsi The MSI message to convert.
428	* @param pIntr Where to store the APIC interrupt.
429	*/
430	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
431	{
432	/*
433	* Parse the message from the physical address and data
434	* See Intel spec. 10.11.1 "Message Address Register Format".
435	* See Intel spec. 10.11.2 "Message Data Register Format".
436	*/
437	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
438	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
439	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
440
441	pIntr->u8Vector = pMsi->Data.n.u8Vector;
442	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
443	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
444	}
445
446
447	#ifdef VBOX_WITH_IOMMU_AMD
448	/**
449	* Convert an APIC interrupt to an MSI message.
450	*
451	* @param pIntr The APIC interrupt to convert.
452	* @param pMsi Where to store the MSI message.
453	*/
454	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
455	{
456	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
457	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
458	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
459	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
460
461	pMsi->Data.n.u8Vector = pIntr->u8Vector;
462	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
463	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
464
465	/* pMsi->Data.n.u1Level = ??? */
466	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
467	* possible in theory? Maybe document this more explicitly... */
468	}
469	#endif
470
471
472	/**
473	* Signals the next pending interrupt for the specified Redirection Table Entry
474	* (RTE).
475	*
476	* @param pDevIns The device instance.
477	* @param pThis The shared I/O APIC device state.
478	* @param pThisCC The I/O APIC device state for the current context.
479	* @param uBusDevFn The bus:device:function of the device initiating the IRQ.
480	* @param idxRte The index of the RTE (validated).
481	*
482	* @remarks It is the responsibility of the caller to verify that an interrupt is
483	* pending for the pin corresponding to the RTE before calling this
484	* function.
485	*/
486	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte)
487	{
488	#ifndef IOAPIC_WITH_PDM_CRITSECT
489	Assert(PDMCritSectIsOwner(&pThis->CritSect));
490	#endif
491
492	/*
493	* Ensure the interrupt isn't masked.
494	*/
495	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
496	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
497	{
498	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
499	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
500	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
501	{
502	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
503	if (u8RemoteIrr)
504	{
505	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
506	return;
507	}
508	}
509
510	XAPICINTR ApicIntr;
511	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
512	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
513	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
514	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
515	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
516	ApicIntr.u8TriggerMode = u8TriggerMode;
517	ApicIntr.u8RedirHint = 0;
518
519	#ifdef VBOX_WITH_IOMMU_AMD
520	/*
521	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
522	*/
523	MSIMSG MsiOut;
524	MSIMSG MsiIn;
525	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
526	if (!PCIBDF_IS_VALID(uBusDevFn))
527	uBusDevFn = VBOX_PCI_BDF_SB_IOAPIC;
528	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, &MsiIn, &MsiOut);
529	if (RT_SUCCESS(rcRemap))
530	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
531	else
532	{
533	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
534	Log3(("IOAPIC: Interrupt (u8Vector=%#x) remapping denied. rc=%Rrc", ApicIntr.u8Vector, rcRemap));
535	else
536	Log(("IOAPIC: Interrupt (u8Vector=%#x) remapping failed. rc=%Rrc", ApicIntr.u8Vector, rcRemap));
537	return;
538	}
539	#else
540	NOREF(uBusDevFn);
541	#endif
542
543	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
544	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
545	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
546	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
547	ApicIntr.u8Vector, ApicIntr.u8Vector));
548
549	/*
550	* Deliver to the local APIC via the system/3-wire-APIC bus.
551	*/
552	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
553	ApicIntr.u8Dest,
554	ApicIntr.u8DestMode,
555	ApicIntr.u8DeliveryMode,
556	ApicIntr.u8Vector,
557	ApicIntr.u8Polarity,
558	ApicIntr.u8TriggerMode,
559	u32TagSrc);
560	/* Can't reschedule to R3. */
561	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
562	#ifdef DEBUG_ramshankar
563	if (rc == VERR_APIC_INTR_DISCARDED)
564	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
565	#endif
566
567	/*
568	* For level-triggered interrupts, we set the remote IRR bit to indicate
569	* the local APIC has accepted the interrupt.
570	*
571	* For edge-triggered interrupts, we should not clear the IRR bit as it
572	* should remain intact to reflect the state of the interrupt line.
573	* The device will explicitly transition to inactive state via the
574	* ioapicSetIrq() callback.
575	*/
576	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
577	&& rc == VINF_SUCCESS)
578	{
579	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
580	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
581	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
582	}
583	}
584	}
585
586
587	/**
588	* Gets the redirection table entry.
589	*
590	* @returns The redirection table entry.
591	* @param pThis The shared I/O APIC device state.
592	* @param uIndex The index value.
593	*/
594	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
595	{
596	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
597	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
598	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
599	UINT32_MAX);
600	uint32_t uValue;
601	if (!(uIndex & 1))
602	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
603	else
604	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
605
606	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
607	return uValue;
608	}
609
610
611	/**
612	* Sets the redirection table entry.
613	*
614	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
615	* @param pDevIns The device instance.
616	* @param pThis The shared I/O APIC device state.
617	* @param pThisCC The I/O APIC device state for the current context.
618	* @param uIndex The index value.
619	* @param uValue The value to set.
620	*/
621	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
622	uint32_t uIndex, uint32_t uValue)
623	{
624	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
625	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
626	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
627	VINF_SUCCESS);
628
629	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
630	if (rc == VINF_SUCCESS)
631	{
632	/*
633	* Write the low or high 32-bit value into the specified 64-bit RTE register,
634	* update only the valid, writable bits.
635	*
636	* We need to preserve the read-only bits as it can have dire consequences
637	* otherwise, see @bugref{8386#c24}.
638	*/
639	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
640	if (!(uIndex & 1))
641	{
642	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
643	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
644	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
645	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
646	}
647	else
648	{
649	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
650	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
651	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
652	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
653	}
654
655	/*
656	* Signal the next pending interrupt for this RTE.
657	*/
658	uint32_t const uPinMask = UINT32_C(1) << idxRte;
659	if (pThis->uIrr & uPinMask)
660	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
661
662	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
663	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
664	}
665	else
666	STAM_COUNTER_INC(&pThis->StatSetRteContention);
667
668	return rc;
669	}
670
671
672	/**
673	* Gets the data register.
674	*
675	* @returns The data value.
676	* @param pThis The shared I/O APIC device state.
677	*/
678	static uint32_t ioapicGetData(PCIOAPIC pThis)
679	{
680	uint8_t const uIndex = pThis->u8Index;
681	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
682	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
683	&& uIndex <= pThis->u8LastRteRegIdx)
684	return ioapicGetRedirTableEntry(pThis, uIndex);
685
686	uint32_t uValue;
687	switch (uIndex)
688	{
689	case IOAPIC_INDIRECT_INDEX_ID:
690	uValue = ioapicGetId(pThis);
691	break;
692
693	case IOAPIC_INDIRECT_INDEX_VERSION:
694	uValue = ioapicGetVersion(pThis);
695	break;
696
697	case IOAPIC_INDIRECT_INDEX_ARB:
698	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
699	{
700	uValue = ioapicGetArb();
701	break;
702	}
703	RT_FALL_THRU();
704
705	default:
706	uValue = UINT32_C(0xffffffff);
707	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
708	break;
709	}
710	return uValue;
711	}
712
713
714	/**
715	* Sets the data register.
716	*
717	* @returns Strict VBox status code.
718	* @param pDevIns The device instance.
719	* @param pThis The shared I/O APIC device state.
720	* @param pThisCC The I/O APIC device state for the current context.
721	* @param uValue The value to set.
722	*/
723	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
724	{
725	uint8_t const uIndex = pThis->u8Index;
726	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
727	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
728
729	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
730	&& uIndex <= pThis->u8LastRteRegIdx)
731	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
732
733	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
734	ioapicSetId(pThis, uValue);
735	else
736	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
737
738	return VINF_SUCCESS;
739	}
740
741
742	/**
743	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
744	*/
745	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
746	{
747	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
748	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
749	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
750	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
751
752	bool fRemoteIrrCleared = false;
753	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
754	if (rc == VINF_SUCCESS)
755	{
756	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
757	{
758	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
759	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
760	{
761	#ifdef DEBUG_ramshankar
762	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
763	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
764	#endif
765	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
766	fRemoteIrrCleared = true;
767	STAM_COUNTER_INC(&pThis->StatEoiReceived);
768	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
769
770	/*
771	* Signal the next pending interrupt for this RTE.
772	*/
773	uint32_t const uPinMask = UINT32_C(1) << idxRte;
774	if (pThis->uIrr & uPinMask)
775	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
776	}
777	}
778
779	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
780	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
781	}
782	else
783	STAM_COUNTER_INC(&pThis->StatEoiContention);
784
785	return rc;
786	}
787
788
789	/**
790	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
791	*/
792	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
793	{
794	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
795	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
796	pThis->uIrr \|= a_PinMask; \
797	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \
798	} while (0)
799
800	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
801	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
802	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
803
804	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
805
806	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
807	{
808	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
809	AssertRC(rc);
810
811	uint8_t const idxRte = iIrq;
812	uint32_t const uPinMask = UINT32_C(1) << idxRte;
813	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
814	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
815
816	bool fActive = RT_BOOL(iLevel & 1);
817	/** @todo Polarity is busted elsewhere, we need to fix that
818	* first. See @bugref{8386#c7}. */
819	#if 0
820	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
821	fActive ^= u8Polarity; */
822	#endif
823	if (!fActive)
824	{
825	pThis->uIrr &= ~uPinMask;
826	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
827	return;
828	}
829
830	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
831	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
832	if (!fFlipFlop)
833	{
834	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
835	{
836	/*
837	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
838	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
839	*/
840	if (!uPrevIrr)
841	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
842	else
843	{
844	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
845	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
846	}
847	}
848	else
849	{
850	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
851
852	/*
853	* For level-triggered interrupts, redundant interrupts are not a problem
854	* and will eventually be delivered anyway after an EOI, but our PDM devices
855	* should not typically call us with no change to the level.
856	*/
857	if (!uPrevIrr)
858	{ /* likely */ }
859	else
860	{
861	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
862	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
863	}
864
865	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
866	}
867	}
868	else
869	{
870	/*
871	* The device is flip-flopping the interrupt line, which implies we should de-assert
872	* and assert the interrupt line. The interrupt line is left in the asserted state
873	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
874	* hence just the assert is done.
875	*/
876	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
877	}
878
879	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
880	}
881	#undef IOAPIC_ASSERT_IRQ
882	}
883
884
885	/**
886	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
887	*/
888	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
889	{
890	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
891	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
892
893	XAPICINTR ApicIntr;
894	RT_ZERO(ApicIntr);
895
896	#ifdef VBOX_WITH_IOMMU_AMD
897	/*
898	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
899	*/
900	MSIMSG MsiOut;
901	Assert(PCIBDF_IS_VALID(uBusDevFn));
902	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
903	if (RT_SUCCESS(rcRemap))
904	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
905	else
906	{
907	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
908	Log3(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping denied. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
909	else
910	Log(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping failed. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
911	return;
912	}
913	#else
914	NOREF(uBusDevFn);
915	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
916	#endif
917
918	/*
919	* Deliver to the local APIC via the system/3-wire-APIC bus.
920	*/
921	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
922	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
923
924	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
925	ApicIntr.u8Dest,
926	ApicIntr.u8DestMode,
927	ApicIntr.u8DeliveryMode,
928	ApicIntr.u8Vector,
929	0 /* u8Polarity - N/A */,
930	ApicIntr.u8TriggerMode,
931	uTagSrc);
932	/* Can't reschedule to R3. */
933	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
934	}
935
936
937	/**
938	* @callback_method_impl{FNIOMMMIONEWREAD}
939	*/
940	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
941	{
942	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
943	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
944	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
945	RT_NOREF_PV(pvUser);
946
947	VBOXSTRICTRC rc = VINF_SUCCESS;
948	uint32_t puValue = (uint32_t )pv;
949	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
950	switch (offReg)
951	{
952	case IOAPIC_DIRECT_OFF_INDEX:
953	*puValue = ioapicGetIndex(pThis);
954	break;
955
956	case IOAPIC_DIRECT_OFF_DATA:
957	*puValue = ioapicGetData(pThis);
958	break;
959
960	default:
961	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
962	rc = VINF_IOM_MMIO_UNUSED_FF;
963	break;
964	}
965
966	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
967	return rc;
968	}
969
970
971	/**
972	* @callback_method_impl{FNIOMMMIONEWWRITE}
973	*/
974	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
975	{
976	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
977	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
978	RT_NOREF_PV(pvUser);
979
980	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
981
982	Assert(!(off & 3));
983	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
984
985	VBOXSTRICTRC rc = VINF_SUCCESS;
986	uint32_t const uValue = (uint32_t const )pv;
987	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
988
989	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
990	switch (offReg)
991	{
992	case IOAPIC_DIRECT_OFF_INDEX:
993	ioapicSetIndex(pThis, uValue);
994	break;
995
996	case IOAPIC_DIRECT_OFF_DATA:
997	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
998	break;
999
1000	case IOAPIC_DIRECT_OFF_EOI:
1001	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1002	rc = ioapicSetEoi(pDevIns, uValue);
1003	else
1004	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1005	break;
1006
1007	default:
1008	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1009	break;
1010	}
1011
1012	return rc;
1013	}
1014
1015
1016	#ifdef IN_RING3
1017
1018	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1019	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1020	{
1021	RT_NOREF(pDesc);
1022	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1023	return VINF_SUCCESS;
1024	}
1025
1026
1027	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1028	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1029	{
1030	RT_NOREF(pDesc, pfMask);
1031	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1032	return VINF_SUCCESS;
1033	}
1034
1035
1036	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1037	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1038	{
1039	RT_NOREF(pDesc);
1040	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1041	return VINF_SUCCESS;
1042	}
1043
1044
1045	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1046	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1047	{
1048	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1049	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1050	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1051	RT_NOREF(pDesc, pfMask);
1052	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1053	}
1054
1055
1056	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1057	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1058	{
1059	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1060	RT_NOREF(pDesc);
1061	pValue->u32 = ioapicGetVersion(pThis);
1062	return VINF_SUCCESS;
1063	}
1064
1065
1066	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1067	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1068	{
1069	RT_NOREF(pvUser, pDesc);
1070	pValue->u32 = ioapicGetArb();
1071	return VINF_SUCCESS;
1072	}
1073
1074
1075	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1076	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1077	{
1078	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1079	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1080	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1081	return VINF_SUCCESS;
1082	}
1083
1084
1085	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1086	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1087	{
1088	RT_NOREF(pfMask);
1089	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1090	/* No locks, no checks, just do it. */
1091	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1092	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1093	return VINF_SUCCESS;
1094	}
1095
1096
1097	/** IOREDTBLn sub fields. */
1098	static DBGFREGSUBFIELD const g_aRteSubs[] =
1099	{
1100	{ "vector", 0, 8, 0, 0, NULL, NULL },
1101	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1102	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1103	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1104	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1105	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1106	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1107	{ "mask", 16, 1, 0, 0, NULL, NULL },
1108	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1109	{ "dest", 56, 8, 0, 0, NULL, NULL },
1110	DBGFREGSUBFIELD_TERMINATOR()
1111	};
1112
1113
1114	/** Register descriptors for DBGF. */
1115	static DBGFREGDESC const g_aRegDesc[] =
1116	{
1117	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1118	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1119	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1120	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1121	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1122	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1123	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1124	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1125	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1126	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1127	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1128	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1129	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1130	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1131	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1132	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1133	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1134	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1135	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1136	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1137	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1138	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1139	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1140	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1141	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1142	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1143	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1144	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1145	DBGFREGDESC_TERMINATOR()
1146	};
1147
1148
1149	/**
1150	* @callback_method_impl{FNDBGFHANDLERDEV}
1151	*/
1152	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1153	{
1154	RT_NOREF(pszArgs);
1155	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1156	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1157
1158	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1159
1160	uint32_t const uId = ioapicGetId(pThis);
1161	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1162	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1163
1164	uint32_t const uVer = ioapicGetVersion(pThis);
1165	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1166	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1167	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1168	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1169
1170	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1171	{
1172	uint32_t const uArb = ioapicGetArb();
1173	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1174	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1175	}
1176
1177	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1178
1179	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1180	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1181
1182	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1183	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1184	{
1185	static const char * const s_apszDeliveryModes[] =
1186	{
1187	"Fixed ",
1188	"LowPri",
1189	"SMI ",
1190	"Rsvd ",
1191	"NMI ",
1192	"INIT ",
1193	"Rsvd ",
1194	"ExtINT"
1195	};
1196
1197	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1198	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1199	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1200	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1201	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1202	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1203	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1204	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1205	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1206	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1207	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1208	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1209
1210	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1211	idxRte,
1212	pszDestMode,
1213	uDest,
1214	uMask,
1215	(pThis->uIrr >> idxRte) & 1,
1216	pszTriggerMode,
1217	uRemoteIrr,
1218	pszPolarity,
1219	pszDeliveryStatus,
1220	pszDeliveryMode,
1221	uVector,
1222	u64Rte);
1223	}
1224	}
1225
1226
1227	/**
1228	* @copydoc FNSSMDEVSAVEEXEC
1229	*/
1230	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1231	{
1232	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1233	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1234	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1235
1236	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1237	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1238	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1239	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1240	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1241
1242	return VINF_SUCCESS;
1243	}
1244
1245
1246	/**
1247	* @copydoc FNSSMDEVLOADEXEC
1248	*/
1249	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1250	{
1251	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1252	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1253	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1254
1255	Assert(uPass == SSM_PASS_FINAL);
1256	NOREF(uPass);
1257
1258	/* Weed out invalid versions. */
1259	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1260	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1261	{
1262	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1263	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1264	}
1265
1266	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1267	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1268
1269	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1270	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1271	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1272	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1273
1274	return VINF_SUCCESS;
1275	}
1276
1277
1278	/**
1279	* @interface_method_impl{PDMDEVREG,pfnReset}
1280	*/
1281	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1282	{
1283	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1284	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1285	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1286
1287	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1288	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1289
1290	pThis->uIrr = 0;
1291	pThis->u8Index = 0;
1292	pThis->u8Id = 0;
1293
1294	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1295	{
1296	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1297	pThis->au32TagSrc[idxRte] = 0;
1298	}
1299
1300	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1301	}
1302
1303
1304	/**
1305	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1306	*/
1307	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1308	{
1309	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1310	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1311
1312	pThisRC->pIoApicHlp += offDelta;
1313	}
1314
1315
1316	/**
1317	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1318	*/
1319	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1320	{
1321	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1322	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1323	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1324
1325	# ifndef IOAPIC_WITH_PDM_CRITSECT
1326	/*
1327	* Destroy the RTE critical section.
1328	*/
1329	if (PDMCritSectIsInitialized(&pThis->CritSect))
1330	PDMR3CritSectDelete(&pThis->CritSect);
1331	# else
1332	RT_NOREF_PV(pThis);
1333	# endif
1334
1335	return VINF_SUCCESS;
1336	}
1337
1338
1339	/**
1340	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1341	*/
1342	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1343	{
1344	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1345	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1346	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1347	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1348	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1349	Assert(iInstance == 0); RT_NOREF(iInstance);
1350
1351	/*
1352	* Validate and read the configuration.
1353	*/
1354	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1355
1356	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1357	upsets some guest which we haven't yet tested. */
1358	uint32_t cCpus;
1359	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1360	if (RT_FAILURE(rc))
1361	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1362	pThis->cCpus = (uint8_t)cCpus;
1363
1364	char szChipType[16];
1365	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1366	if (RT_FAILURE(rc))
1367	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1368
1369	if (!strcmp(szChipType, "ICH9"))
1370	{
1371	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1372	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1373	pThis->u8IdMask = 0xff;
1374	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1375	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1376	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1377	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1378	}
1379	else if (!strcmp(szChipType, "82093AA"))
1380	{
1381	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1382	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1383	pThis->u8IdMask = 0x0f;
1384	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1385	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1386	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1387	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1388	}
1389	else if (!strcmp(szChipType, "82379AB"))
1390	{
1391	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1392	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1393	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1394	pThis->u8IdMask = 0x0f;
1395	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1396	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1397	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1398	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1399	}
1400	else
1401	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1402	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1403	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1404
1405	/*
1406	* We will use our own critical section for the IOAPIC device.
1407	*/
1408	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1409	AssertRCReturn(rc, rc);
1410
1411	# ifndef IOAPIC_WITH_PDM_CRITSECT
1412	/*
1413	* Setup the critical section to protect concurrent writes to the RTEs.
1414	*/
1415	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1416	AssertRCReturn(rc, rc);
1417	# endif
1418
1419	/*
1420	* Register the IOAPIC.
1421	*/
1422	PDMIOAPICREG IoApicReg;
1423	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1424	IoApicReg.pfnSetIrq = ioapicSetIrq;
1425	IoApicReg.pfnSendMsi = ioapicSendMsi;
1426	IoApicReg.pfnSetEoi = ioapicSetEoi;
1427	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1428	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1429	AssertRCReturn(rc, rc);
1430
1431	/*
1432	* Register MMIO region.
1433	*/
1434	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1435	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1436	AssertRCReturn(rc, rc);
1437
1438	/*
1439	* Register the saved state.
1440	*/
1441	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1442	AssertRCReturn(rc, rc);
1443
1444	/*
1445	* Register debugger info item.
1446	*/
1447	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1448	AssertRCReturn(rc, rc);
1449
1450	/*
1451	* Register debugger register access.
1452	*/
1453	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1454	AssertRCReturn(rc, rc);
1455
1456	# ifdef VBOX_WITH_STATISTICS
1457	/*
1458	* Statistics.
1459	*/
1460	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1461	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1462	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1463	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1464
1465	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1466	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1467	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1468	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1469
1470	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1471	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1472	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1473
1474	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1475	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1476
1477	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1478	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1479	# endif
1480	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1481	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1482	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1483
1484	/*
1485	* Init. the device state.
1486	*/
1487	LogRel(("IOAPIC: Using implementation 2.0! I/O APIC version is %d.%d\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0F));
1488	ioapicR3Reset(pDevIns);
1489
1490	return VINF_SUCCESS;
1491	}
1492
1493	#else /* !IN_RING3 */
1494
1495	/**
1496	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1497	*/
1498	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1499	{
1500	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1501	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1502	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1503
1504	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1505	AssertRCReturn(rc, rc);
1506
1507	PDMIOAPICREG IoApicReg;
1508	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1509	IoApicReg.pfnSetIrq = ioapicSetIrq;
1510	IoApicReg.pfnSendMsi = ioapicSendMsi;
1511	IoApicReg.pfnSetEoi = ioapicSetEoi;
1512	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1513	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1514	AssertRCReturn(rc, rc);
1515
1516	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1517	AssertRCReturn(rc, rc);
1518
1519	return VINF_SUCCESS;
1520	}
1521
1522	#endif /* !IN_RING3 */
1523
1524	/**
1525	* IO APIC device registration structure.
1526	*/
1527	const PDMDEVREG g_DeviceIOAPIC =
1528	{
1529	/* .u32Version = */ PDM_DEVREG_VERSION,
1530	/* .uReserved0 = */ 0,
1531	/* .szName = */ "ioapic",
1532	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1533	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1534	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1535	/* .cMaxInstances = */ 1,
1536	/* .uSharedVersion = */ 42,
1537	/* .cbInstanceShared = */ sizeof(IOAPIC),
1538	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1539	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1540	/* .cMaxPciDevices = */ 0,
1541	/* .cMaxMsixVectors = */ 0,
1542	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1543	#if defined(IN_RING3)
1544	/* .pszRCMod = */ "VBoxDDRC.rc",
1545	/* .pszR0Mod = */ "VBoxDDR0.r0",
1546	/* .pfnConstruct = */ ioapicR3Construct,
1547	/* .pfnDestruct = */ ioapicR3Destruct,
1548	/* .pfnRelocate = */ ioapicR3Relocate,
1549	/* .pfnMemSetup = */ NULL,
1550	/* .pfnPowerOn = */ NULL,
1551	/* .pfnReset = */ ioapicR3Reset,
1552	/* .pfnSuspend = */ NULL,
1553	/* .pfnResume = */ NULL,
1554	/* .pfnAttach = */ NULL,
1555	/* .pfnDetach = */ NULL,
1556	/* .pfnQueryInterface = */ NULL,
1557	/* .pfnInitComplete = */ NULL,
1558	/* .pfnPowerOff = */ NULL,
1559	/* .pfnSoftReset = */ NULL,
1560	/* .pfnReserved0 = */ NULL,
1561	/* .pfnReserved1 = */ NULL,
1562	/* .pfnReserved2 = */ NULL,
1563	/* .pfnReserved3 = */ NULL,
1564	/* .pfnReserved4 = */ NULL,
1565	/* .pfnReserved5 = */ NULL,
1566	/* .pfnReserved6 = */ NULL,
1567	/* .pfnReserved7 = */ NULL,
1568	#elif defined(IN_RING0)
1569	/* .pfnEarlyConstruct = */ NULL,
1570	/* .pfnConstruct = */ ioapicRZConstruct,
1571	/* .pfnDestruct = */ NULL,
1572	/* .pfnFinalDestruct = */ NULL,
1573	/* .pfnRequest = */ NULL,
1574	/* .pfnReserved0 = */ NULL,
1575	/* .pfnReserved1 = */ NULL,
1576	/* .pfnReserved2 = */ NULL,
1577	/* .pfnReserved3 = */ NULL,
1578	/* .pfnReserved4 = */ NULL,
1579	/* .pfnReserved5 = */ NULL,
1580	/* .pfnReserved6 = */ NULL,
1581	/* .pfnReserved7 = */ NULL,
1582	#elif defined(IN_RC)
1583	/* .pfnConstruct = */ ioapicRZConstruct,
1584	/* .pfnReserved0 = */ NULL,
1585	/* .pfnReserved1 = */ NULL,
1586	/* .pfnReserved2 = */ NULL,
1587	/* .pfnReserved3 = */ NULL,
1588	/* .pfnReserved4 = */ NULL,
1589	/* .pfnReserved5 = */ NULL,
1590	/* .pfnReserved6 = */ NULL,
1591	/* .pfnReserved7 = */ NULL,
1592	#else
1593	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1594	#endif
1595	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1596	};
1597
1598
1599	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1600

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 85966

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