DevIoApic.cpp@ 86865

Last change on this file since 86865 was 86865, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 DevIoApic: Assertion to ensure polarity hasn't changed when converting between MSI and XAPIC interrupts.
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1	/* $Id: DevIoApic.cpp 86865 2020-11-12 06:57:40Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - the mask bit number. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - the mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** Redirection table entry - Valid write mask for 82093AA. */
126	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
127	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
128	\| IOAPIC_RTE_VECTOR)
129	/** Redirection table entry - Valid read mask for 82093AA. */
130	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
131	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
132	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
133
134	/** Redirection table entry - Valid write mask for ICH9. */
135	/** @note The remote IRR bit has been reverted to read-only as it turns out the
136	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
139	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
140	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
141	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
142	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
143	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
144	\| IOAPIC_RTE_VECTOR)
145
146	/** Redirection table entry - Trigger mode edge. */
147	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
148	/** Redirection table entry - Trigger mode level. */
149	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
150	/** Redirection table entry - Destination mode physical. */
151	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
152	/** Redirection table entry - Destination mode logical. */
153	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
154
155
156	/** Index of indirect registers in the I/O APIC register table. */
157	#define IOAPIC_INDIRECT_INDEX_ID 0x0
158	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
159	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
160	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
161	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
162	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
163
164	/** Offset of direct registers in the I/O APIC MMIO space. */
165	#define IOAPIC_DIRECT_OFF_INDEX 0x00
166	#define IOAPIC_DIRECT_OFF_DATA 0x10
167	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
168
169	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
170	#define IOAPIC_WITH_PDM_CRITSECT
171	#ifdef IOAPIC_WITH_PDM_CRITSECT
172	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
173	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
174	#else
175	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
176	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The shared I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The ID register. */
189	uint8_t volatile u8Id;
190	/** The index register. */
191	uint8_t volatile u8Index;
192	/** Number of CPUs. */
193	uint8_t cCpus;
194	/** I/O APIC version. */
195	uint8_t u8ApicVer;
196	/** I/O APIC ID mask. */
197	uint8_t u8IdMask;
198	/** Maximum Redirection Table Entry (RTE) Entry. */
199	uint8_t u8MaxRte;
200	/** Last valid RTE indirect register index. */
201	uint8_t u8LastRteRegIdx;
202	/* Alignment padding. */
203	uint8_t u8Padding0[1];
204	/** Redirection table entry - Valid write mask. */
205	uint64_t u64RteWriteMask;
206	/** Redirection table entry - Valid read mask. */
207	uint64_t u64RteReadMask;
208
209	/** The redirection table registers. */
210	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
211	/** The IRQ tags and source IDs for each pin (tracing purposes). */
212	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
213
214	/** The internal IRR reflecting state of the interrupt lines. */
215	uint32_t uIrr;
216	/** Alignment padding. */
217	uint32_t u32Padding2;
218
219	#ifndef IOAPIC_WITH_PDM_CRITSECT
220	/** The critsect for updating to the RTEs. */
221	PDMCRITSECT CritSect;
222	#endif
223
224	/** The MMIO region. */
225	IOMMMIOHANDLE hMmio;
226
227	#ifdef VBOX_WITH_STATISTICS
228	/** Number of MMIO reads in RZ. */
229	STAMCOUNTER StatMmioReadRZ;
230	/** Number of MMIO reads in R3. */
231	STAMCOUNTER StatMmioReadR3;
232
233	/** Number of MMIO writes in RZ. */
234	STAMCOUNTER StatMmioWriteRZ;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237
238	/** Number of SetIrq calls in RZ. */
239	STAMCOUNTER StatSetIrqRZ;
240	/** Number of SetIrq calls in R3. */
241	STAMCOUNTER StatSetIrqR3;
242
243	/** Number of SetEoi calls in RZ. */
244	STAMCOUNTER StatSetEoiRZ;
245	/** Number of SetEoi calls in R3. */
246	STAMCOUNTER StatSetEoiR3;
247
248	/** Number of redundant edge-triggered interrupts. */
249	STAMCOUNTER StatRedundantEdgeIntr;
250	/** Number of redundant level-triggered interrupts. */
251	STAMCOUNTER StatRedundantLevelIntr;
252	/** Number of suppressed level-triggered interrupts (by remote IRR). */
253	STAMCOUNTER StatSuppressedLevelIntr;
254	/** Number of IOMMU discarded interrupts (signaled by RTE). */
255	STAMCOUNTER StatIommuDiscardedIntr;
256	/** Number of IOMMU denied or failed MSIs. */
257	STAMCOUNTER StatIommuDiscardedMsi;
258	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
259	STAMCOUNTER StatEoiContention;
260	/** Number of returns to ring-3 due to Set RTE lock contention. */
261	STAMCOUNTER StatSetRteContention;
262	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
263	STAMCOUNTER StatLevelIrqSent;
264	/** Number of EOIs received for level-triggered interrupts from the local
265	* APIC(s). */
266	STAMCOUNTER StatEoiReceived;
267	#endif
268	/** Per-vector stats. */
269	STAMCOUNTER aStatVectors[256];
270	} IOAPIC;
271	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
272	/** Pointer to shared IOAPIC data. */
273	typedef IOAPIC *PIOAPIC;
274	/** Pointer to const shared IOAPIC data. */
275	typedef IOAPIC const *PCIOAPIC;
276
277
278	/**
279	* The I/O APIC device state for ring-3.
280	*/
281	typedef struct IOAPICR3
282	{
283	/** The IOAPIC helpers. */
284	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
285	} IOAPICR3;
286	/** Pointer to the I/O APIC device state for ring-3. */
287	typedef IOAPICR3 *PIOAPICR3;
288
289
290	/**
291	* The I/O APIC device state for ring-0.
292	*/
293	typedef struct IOAPICR0
294	{
295	/** The IOAPIC helpers. */
296	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
297	} IOAPICR0;
298	/** Pointer to the I/O APIC device state for ring-0. */
299	typedef IOAPICR0 *PIOAPICR0;
300
301
302	/**
303	* The I/O APIC device state for raw-mode.
304	*/
305	typedef struct IOAPICRC
306	{
307	/** The IOAPIC helpers. */
308	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
309	} IOAPICRC;
310	/** Pointer to the I/O APIC device state for raw-mode. */
311	typedef IOAPICRC *PIOAPICRC;
312
313
314	/** The I/O APIC device state for the current context. */
315	typedef CTX_SUFF(IOAPIC) IOAPICCC;
316	/** Pointer to the I/O APIC device state for the current context. */
317	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
318
319
320	/**
321	* xAPIC interrupt.
322	*/
323	typedef struct XAPICINTR
324	{
325	/** The interrupt vector. */
326	uint8_t u8Vector;
327	/** The destination (mask or ID). */
328	uint8_t u8Dest;
329	/** The destination mode. */
330	uint8_t u8DestMode;
331	/** Delivery mode. */
332	uint8_t u8DeliveryMode;
333	/** Trigger mode. */
334	uint8_t u8TriggerMode;
335	/** Redirection hint. */
336	uint8_t u8RedirHint;
337	/** Polarity. */
338	uint8_t u8Polarity;
339	/** Padding. */
340	uint8_t abPadding0;
341	} XAPICINTR;
342	/** Pointer to an I/O xAPIC interrupt struct. */
343	typedef XAPICINTR *PXAPICINTR;
344	/** Pointer to a const xAPIC interrupt struct. */
345	typedef XAPICINTR const *PCXAPICINTR;
346
347
348	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
349
350	/**
351	* Gets the arbitration register.
352	*
353	* @returns The arbitration.
354	*/
355	DECLINLINE(uint32_t) ioapicGetArb(void)
356	{
357	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
358	return 0;
359	}
360
361
362	/**
363	* Gets the version register.
364	*
365	* @returns The version.
366	*/
367	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
368	{
369	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
370	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
371	return uValue;
372	}
373
374
375	/**
376	* Sets the ID register.
377	*
378	* @param pThis The shared I/O APIC device state.
379	* @param uValue The value to set.
380	*/
381	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
382	{
383	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
384	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
385	}
386
387
388	/**
389	* Gets the ID register.
390	*
391	* @returns The ID.
392	* @param pThis The shared I/O APIC device state.
393	*/
394	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
395	{
396	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
397	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
398	return uValue;
399	}
400
401
402	/**
403	* Sets the index register.
404	*
405	* @param pThis The shared I/O APIC device state.
406	* @param uValue The value to set.
407	*/
408	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
409	{
410	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
411	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
412	}
413
414
415	/**
416	* Gets the index register.
417	*
418	* @returns The index value.
419	*/
420	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
421	{
422	uint32_t const uValue = pThis->u8Index;
423	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
424	return uValue;
425	}
426
427
428	/**
429	* Converts an MSI message to an APIC interrupt.
430	*
431	* @param pMsi The MSI message to convert.
432	* @param pIntr Where to store the APIC interrupt.
433	*/
434	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
435	{
436	/*
437	* Parse the message from the physical address and data
438	* See Intel spec. 10.11.1 "Message Address Register Format".
439	* See Intel spec. 10.11.2 "Message Data Register Format".
440	*/
441	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
442	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
443	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
444
445	pIntr->u8Vector = pMsi->Data.n.u8Vector;
446	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
447	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
448	}
449
450
451	#ifdef VBOX_WITH_IOMMU_AMD
452	/**
453	* Convert an APIC interrupt to an MSI message.
454	*
455	* @param pIntr The APIC interrupt to convert.
456	* @param pMsi Where to store the MSI message.
457	*/
458	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
459	{
460	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
461	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
462	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
463	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
464
465	pMsi->Data.n.u8Vector = pIntr->u8Vector;
466	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
467	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
468
469	/* pMsi->Data.n.u1Level = ??? */
470	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
471	* possible in theory? Maybe document this more explicitly... */
472	}
473	#endif
474
475
476	/**
477	* Signals the next pending interrupt for the specified Redirection Table Entry
478	* (RTE).
479	*
480	* @param pDevIns The device instance.
481	* @param pThis The shared I/O APIC device state.
482	* @param pThisCC The I/O APIC device state for the current context.
483	* @param uBusDevFn The bus:device:function of the device initiating the IRQ.
484	* @param idxRte The index of the RTE (validated).
485	*
486	* @remarks It is the responsibility of the caller to verify that an interrupt is
487	* pending for the pin corresponding to the RTE before calling this
488	* function.
489	*/
490	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte)
491	{
492	#ifndef IOAPIC_WITH_PDM_CRITSECT
493	Assert(PDMCritSectIsOwner(&pThis->CritSect));
494	#endif
495
496	/*
497	* Ensure the interrupt isn't masked.
498	*/
499	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
500	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
501	{
502	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
503	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
504	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
505	{
506	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
507	if (u8RemoteIrr)
508	{
509	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
510	return;
511	}
512	}
513
514	XAPICINTR ApicIntr;
515	RT_ZERO(ApicIntr);
516	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
517	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
518	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
519	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
520	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
521	ApicIntr.u8TriggerMode = u8TriggerMode;
522	ApicIntr.u8RedirHint = 0;
523
524	#ifdef VBOX_WITH_IOMMU_AMD
525	/*
526	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
527	*/
528	MSIMSG MsiOut;
529	MSIMSG MsiIn;
530	RT_ZERO(MsiOut);
531	RT_ZERO(MsiIn);
532	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
533	if (!PCIBDF_IS_VALID(uBusDevFn))
534	uBusDevFn = VBOX_PCI_BDF_SB_IOAPIC;
535	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, &MsiIn, &MsiOut);
536	LogFlow(("IOAPIC: IOMMU Remap. rc=%Rrc VectorIn=%#x VectorOut=%#x\n", rcRemap, MsiIn.Data.n.u8Vector, MsiOut.Data.n.u8Vector));
537	if (RT_SUCCESS(rcRemap))
538	{
539	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
540	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte)); /* Ensure polarity hasn't changed. */
541	}
542	else
543	{
544	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
545	Log(("IOAPIC: Interrupt (%#x) discarded (rc=%Rrc)\n", ApicIntr.u8Vector, rcRemap));
546	return;
547	}
548	#else
549	NOREF(uBusDevFn);
550	#endif
551
552	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
553	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
554	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
555	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
556	ApicIntr.u8Vector, ApicIntr.u8Vector));
557
558	/*
559	* Deliver to the local APIC via the system/3-wire-APIC bus.
560	*/
561	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
562	ApicIntr.u8Dest,
563	ApicIntr.u8DestMode,
564	ApicIntr.u8DeliveryMode,
565	ApicIntr.u8Vector,
566	ApicIntr.u8Polarity,
567	ApicIntr.u8TriggerMode,
568	u32TagSrc);
569	/* Can't reschedule to R3. */
570	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
571	#ifdef DEBUG_ramshankar
572	if (rc == VERR_APIC_INTR_DISCARDED)
573	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
574	#endif
575
576	/*
577	* For level-triggered interrupts, we set the remote IRR bit to indicate
578	* the local APIC has accepted the interrupt.
579	*
580	* For edge-triggered interrupts, we should not clear the IRR bit as it
581	* should remain intact to reflect the state of the interrupt line.
582	* The device will explicitly transition to inactive state via the
583	* ioapicSetIrq() callback.
584	*/
585	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
586	&& rc == VINF_SUCCESS)
587	{
588	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
589	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
590	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
591	}
592	}
593	}
594
595
596	/**
597	* Gets the redirection table entry.
598	*
599	* @returns The redirection table entry.
600	* @param pThis The shared I/O APIC device state.
601	* @param uIndex The index value.
602	*/
603	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
604	{
605	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
606	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
607	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
608	UINT32_MAX);
609	uint32_t uValue;
610	if (!(uIndex & 1))
611	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
612	else
613	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
614
615	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
616	return uValue;
617	}
618
619
620	/**
621	* Sets the redirection table entry.
622	*
623	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
624	* @param pDevIns The device instance.
625	* @param pThis The shared I/O APIC device state.
626	* @param pThisCC The I/O APIC device state for the current context.
627	* @param uIndex The index value.
628	* @param uValue The value to set.
629	*/
630	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
631	uint32_t uIndex, uint32_t uValue)
632	{
633	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
634	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
635	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
636	VINF_SUCCESS);
637
638	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
639	if (rc == VINF_SUCCESS)
640	{
641	/*
642	* Write the low or high 32-bit value into the specified 64-bit RTE register,
643	* update only the valid, writable bits.
644	*
645	* We need to preserve the read-only bits as it can have dire consequences
646	* otherwise, see @bugref{8386#c24}.
647	*/
648	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
649	if (!(uIndex & 1))
650	{
651	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
652	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
653	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
654	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
655	}
656	else
657	{
658	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
659	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
660	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
661	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
662	}
663
664	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
665
666	/*
667	* Signal the next pending interrupt for this RTE.
668	*/
669	uint32_t const uPinMask = UINT32_C(1) << idxRte;
670	if (pThis->uIrr & uPinMask)
671	{
672	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
673	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
674	}
675
676	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
677	}
678	else
679	STAM_COUNTER_INC(&pThis->StatSetRteContention);
680
681	return rc;
682	}
683
684
685	/**
686	* Gets the data register.
687	*
688	* @returns The data value.
689	* @param pThis The shared I/O APIC device state.
690	*/
691	static uint32_t ioapicGetData(PCIOAPIC pThis)
692	{
693	uint8_t const uIndex = pThis->u8Index;
694	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
695	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
696	&& uIndex <= pThis->u8LastRteRegIdx)
697	return ioapicGetRedirTableEntry(pThis, uIndex);
698
699	uint32_t uValue;
700	switch (uIndex)
701	{
702	case IOAPIC_INDIRECT_INDEX_ID:
703	uValue = ioapicGetId(pThis);
704	break;
705
706	case IOAPIC_INDIRECT_INDEX_VERSION:
707	uValue = ioapicGetVersion(pThis);
708	break;
709
710	case IOAPIC_INDIRECT_INDEX_ARB:
711	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
712	{
713	uValue = ioapicGetArb();
714	break;
715	}
716	RT_FALL_THRU();
717
718	default:
719	uValue = UINT32_C(0xffffffff);
720	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
721	break;
722	}
723	return uValue;
724	}
725
726
727	/**
728	* Sets the data register.
729	*
730	* @returns Strict VBox status code.
731	* @param pDevIns The device instance.
732	* @param pThis The shared I/O APIC device state.
733	* @param pThisCC The I/O APIC device state for the current context.
734	* @param uValue The value to set.
735	*/
736	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
737	{
738	uint8_t const uIndex = pThis->u8Index;
739	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
740	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
741
742	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
743	&& uIndex <= pThis->u8LastRteRegIdx)
744	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
745
746	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
747	ioapicSetId(pThis, uValue);
748	else
749	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
750
751	return VINF_SUCCESS;
752	}
753
754
755	/**
756	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
757	*/
758	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
759	{
760	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
761	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
762	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
763	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
764
765	bool fRemoteIrrCleared = false;
766	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
767	if (rc == VINF_SUCCESS)
768	{
769	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
770	{
771	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
772	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
773	{
774	#ifdef DEBUG_ramshankar
775	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
776	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
777	#endif
778	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
779	fRemoteIrrCleared = true;
780	STAM_COUNTER_INC(&pThis->StatEoiReceived);
781	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
782
783	/*
784	* Signal the next pending interrupt for this RTE.
785	*/
786	uint32_t const uPinMask = UINT32_C(1) << idxRte;
787	if (pThis->uIrr & uPinMask)
788	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
789	}
790	}
791
792	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
793	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
794	}
795	else
796	STAM_COUNTER_INC(&pThis->StatEoiContention);
797
798	return rc;
799	}
800
801
802	/**
803	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
804	*/
805	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
806	{
807	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
808	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
809	pThis->uIrr \|= a_PinMask; \
810	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \
811	} while (0)
812
813	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
814	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
815	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
816
817	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
818
819	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
820	{
821	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
822	AssertRC(rc);
823
824	uint8_t const idxRte = iIrq;
825	uint32_t const uPinMask = UINT32_C(1) << idxRte;
826	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
827	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
828
829	bool fActive = RT_BOOL(iLevel & 1);
830	/** @todo Polarity is busted elsewhere, we need to fix that
831	* first. See @bugref{8386#c7}. */
832	#if 0
833	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
834	fActive ^= u8Polarity; */
835	#endif
836	if (!fActive)
837	{
838	pThis->uIrr &= ~uPinMask;
839	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
840	return;
841	}
842
843	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
844	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
845	if (!fFlipFlop)
846	{
847	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
848	{
849	/*
850	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
851	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
852	*/
853	if (!uPrevIrr)
854	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
855	else
856	{
857	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
858	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
859	}
860	}
861	else
862	{
863	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
864
865	/*
866	* For level-triggered interrupts, redundant interrupts are not a problem
867	* and will eventually be delivered anyway after an EOI, but our PDM devices
868	* should not typically call us with no change to the level.
869	*/
870	if (!uPrevIrr)
871	{ /* likely */ }
872	else
873	{
874	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
875	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
876	}
877
878	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
879	}
880	}
881	else
882	{
883	/*
884	* The device is flip-flopping the interrupt line, which implies we should de-assert
885	* and assert the interrupt line. The interrupt line is left in the asserted state
886	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
887	* hence just the assert is done.
888	*/
889	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
890	}
891
892	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
893	}
894	#undef IOAPIC_ASSERT_IRQ
895	}
896
897
898	/**
899	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
900	*/
901	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
902	{
903	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
904	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
905	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
906
907	XAPICINTR ApicIntr;
908	RT_ZERO(ApicIntr);
909
910	#ifdef VBOX_WITH_IOMMU_AMD
911	/*
912	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
913	*/
914	MSIMSG MsiOut;
915	RT_ZERO(MsiOut);
916	Assert(PCIBDF_IS_VALID(uBusDevFn));
917	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
918	if (RT_SUCCESS(rcRemap))
919	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
920	else
921	{
922	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
923	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
924	Log3(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping denied. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
925	else
926	Log(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping failed. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
927	return;
928	}
929	#else
930	NOREF(uBusDevFn);
931	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
932	#endif
933
934	/*
935	* Deliver to the local APIC via the system/3-wire-APIC bus.
936	*/
937	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
938
939	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
940	ApicIntr.u8Dest,
941	ApicIntr.u8DestMode,
942	ApicIntr.u8DeliveryMode,
943	ApicIntr.u8Vector,
944	0 /* u8Polarity - N/A */,
945	ApicIntr.u8TriggerMode,
946	uTagSrc);
947	/* Can't reschedule to R3. */
948	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
949	}
950
951
952	/**
953	* @callback_method_impl{FNIOMMMIONEWREAD}
954	*/
955	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
956	{
957	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
958	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
959	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
960	RT_NOREF_PV(pvUser);
961
962	VBOXSTRICTRC rc = VINF_SUCCESS;
963	uint32_t puValue = (uint32_t )pv;
964	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
965	switch (offReg)
966	{
967	case IOAPIC_DIRECT_OFF_INDEX:
968	*puValue = ioapicGetIndex(pThis);
969	break;
970
971	case IOAPIC_DIRECT_OFF_DATA:
972	*puValue = ioapicGetData(pThis);
973	break;
974
975	default:
976	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
977	rc = VINF_IOM_MMIO_UNUSED_FF;
978	break;
979	}
980
981	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
982	return rc;
983	}
984
985
986	/**
987	* @callback_method_impl{FNIOMMMIONEWWRITE}
988	*/
989	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
990	{
991	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
992	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
993	RT_NOREF_PV(pvUser);
994
995	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
996
997	Assert(!(off & 3));
998	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
999
1000	VBOXSTRICTRC rc = VINF_SUCCESS;
1001	uint32_t const uValue = (uint32_t const )pv;
1002	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1003
1004	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1005	switch (offReg)
1006	{
1007	case IOAPIC_DIRECT_OFF_INDEX:
1008	ioapicSetIndex(pThis, uValue);
1009	break;
1010
1011	case IOAPIC_DIRECT_OFF_DATA:
1012	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1013	break;
1014
1015	case IOAPIC_DIRECT_OFF_EOI:
1016	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1017	rc = ioapicSetEoi(pDevIns, uValue);
1018	else
1019	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1020	break;
1021
1022	default:
1023	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1024	break;
1025	}
1026
1027	return rc;
1028	}
1029
1030
1031	#ifdef IN_RING3
1032
1033	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1034	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1035	{
1036	RT_NOREF(pDesc);
1037	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1038	return VINF_SUCCESS;
1039	}
1040
1041
1042	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1043	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1044	{
1045	RT_NOREF(pDesc, pfMask);
1046	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1047	return VINF_SUCCESS;
1048	}
1049
1050
1051	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1052	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1053	{
1054	RT_NOREF(pDesc);
1055	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1056	return VINF_SUCCESS;
1057	}
1058
1059
1060	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1061	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1062	{
1063	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1064	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1065	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1066	RT_NOREF(pDesc, pfMask);
1067	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1068	}
1069
1070
1071	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1072	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1073	{
1074	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1075	RT_NOREF(pDesc);
1076	pValue->u32 = ioapicGetVersion(pThis);
1077	return VINF_SUCCESS;
1078	}
1079
1080
1081	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1082	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1083	{
1084	RT_NOREF(pvUser, pDesc);
1085	pValue->u32 = ioapicGetArb();
1086	return VINF_SUCCESS;
1087	}
1088
1089
1090	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1091	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1092	{
1093	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1094	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1095	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1096	return VINF_SUCCESS;
1097	}
1098
1099
1100	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1101	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1102	{
1103	RT_NOREF(pfMask);
1104	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1105	/* No locks, no checks, just do it. */
1106	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1107	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1108	return VINF_SUCCESS;
1109	}
1110
1111
1112	/** IOREDTBLn sub fields. */
1113	static DBGFREGSUBFIELD const g_aRteSubs[] =
1114	{
1115	{ "vector", 0, 8, 0, 0, NULL, NULL },
1116	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1117	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1118	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1119	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1120	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1121	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1122	{ "mask", 16, 1, 0, 0, NULL, NULL },
1123	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1124	{ "dest", 56, 8, 0, 0, NULL, NULL },
1125	DBGFREGSUBFIELD_TERMINATOR()
1126	};
1127
1128
1129	/** Register descriptors for DBGF. */
1130	static DBGFREGDESC const g_aRegDesc[] =
1131	{
1132	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1133	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1134	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1135	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1136	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1137	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1138	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1139	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1140	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1141	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1142	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1143	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1144	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1145	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1146	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1147	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1148	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1149	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1150	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1151	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1152	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1153	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1154	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1155	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1156	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1157	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1158	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1159	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1160	DBGFREGDESC_TERMINATOR()
1161	};
1162
1163
1164	/**
1165	* @callback_method_impl{FNDBGFHANDLERDEV}
1166	*/
1167	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1168	{
1169	RT_NOREF(pszArgs);
1170	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1171	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1172
1173	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1174
1175	uint32_t const uId = ioapicGetId(pThis);
1176	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1177	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1178
1179	uint32_t const uVer = ioapicGetVersion(pThis);
1180	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1181	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1182	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1183	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1184
1185	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1186	{
1187	uint32_t const uArb = ioapicGetArb();
1188	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1189	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1190	}
1191
1192	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1193
1194	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1195	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1196
1197	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1198	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1199	{
1200	static const char * const s_apszDeliveryModes[] =
1201	{
1202	"Fixed ",
1203	"LowPri",
1204	"SMI ",
1205	"Rsvd ",
1206	"NMI ",
1207	"INIT ",
1208	"Rsvd ",
1209	"ExtINT"
1210	};
1211
1212	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1213	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1214	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1215	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1216	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1217	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1218	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1219	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1220	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1221	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1222	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1223	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1224
1225	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1226	idxRte,
1227	pszDestMode,
1228	uDest,
1229	uMask,
1230	(pThis->uIrr >> idxRte) & 1,
1231	pszTriggerMode,
1232	uRemoteIrr,
1233	pszPolarity,
1234	pszDeliveryStatus,
1235	pszDeliveryMode,
1236	uVector,
1237	u64Rte);
1238	}
1239	}
1240
1241
1242	/**
1243	* @copydoc FNSSMDEVSAVEEXEC
1244	*/
1245	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1246	{
1247	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1248	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1249	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1250
1251	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1252	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1253	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1254	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1255	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1256
1257	return VINF_SUCCESS;
1258	}
1259
1260
1261	/**
1262	* @copydoc FNSSMDEVLOADEXEC
1263	*/
1264	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1265	{
1266	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1267	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1268	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1269
1270	Assert(uPass == SSM_PASS_FINAL);
1271	NOREF(uPass);
1272
1273	/* Weed out invalid versions. */
1274	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1275	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1276	{
1277	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1278	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1279	}
1280
1281	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1282	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1283
1284	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1285	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1286	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1287	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1288
1289	return VINF_SUCCESS;
1290	}
1291
1292
1293	/**
1294	* @interface_method_impl{PDMDEVREG,pfnReset}
1295	*/
1296	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1297	{
1298	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1299	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1300	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1301
1302	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1303	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1304
1305	pThis->uIrr = 0;
1306	pThis->u8Index = 0;
1307	pThis->u8Id = 0;
1308
1309	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1310	{
1311	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1312	pThis->au32TagSrc[idxRte] = 0;
1313	}
1314
1315	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1316	}
1317
1318
1319	/**
1320	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1321	*/
1322	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1323	{
1324	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1325	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1326
1327	pThisRC->pIoApicHlp += offDelta;
1328	}
1329
1330
1331	/**
1332	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1333	*/
1334	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1335	{
1336	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1337	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1338	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1339
1340	# ifndef IOAPIC_WITH_PDM_CRITSECT
1341	/*
1342	* Destroy the RTE critical section.
1343	*/
1344	if (PDMCritSectIsInitialized(&pThis->CritSect))
1345	PDMR3CritSectDelete(&pThis->CritSect);
1346	# else
1347	RT_NOREF_PV(pThis);
1348	# endif
1349
1350	return VINF_SUCCESS;
1351	}
1352
1353
1354	/**
1355	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1356	*/
1357	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1358	{
1359	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1360	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1361	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1362	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1363	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1364	Assert(iInstance == 0); RT_NOREF(iInstance);
1365
1366	/*
1367	* Validate and read the configuration.
1368	*/
1369	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1370
1371	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1372	upsets some guest which we haven't yet tested. */
1373	uint32_t cCpus;
1374	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1375	if (RT_FAILURE(rc))
1376	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1377	pThis->cCpus = (uint8_t)cCpus;
1378
1379	char szChipType[16];
1380	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1381	if (RT_FAILURE(rc))
1382	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1383
1384	if (!strcmp(szChipType, "ICH9"))
1385	{
1386	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1387	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1388	pThis->u8IdMask = 0xff;
1389	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1390	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1391	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1392	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1393	}
1394	else if (!strcmp(szChipType, "82093AA"))
1395	{
1396	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1397	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1398	pThis->u8IdMask = 0x0f;
1399	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1400	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1401	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1402	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1403	}
1404	else if (!strcmp(szChipType, "82379AB"))
1405	{
1406	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1407	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1408	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1409	pThis->u8IdMask = 0x0f;
1410	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1411	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1412	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1413	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1414	}
1415	else
1416	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1417	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1418	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1419
1420	/*
1421	* We will use our own critical section for the IOAPIC device.
1422	*/
1423	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1424	AssertRCReturn(rc, rc);
1425
1426	# ifndef IOAPIC_WITH_PDM_CRITSECT
1427	/*
1428	* Setup the critical section to protect concurrent writes to the RTEs.
1429	*/
1430	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1431	AssertRCReturn(rc, rc);
1432	# endif
1433
1434	/*
1435	* Register the IOAPIC.
1436	*/
1437	PDMIOAPICREG IoApicReg;
1438	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1439	IoApicReg.pfnSetIrq = ioapicSetIrq;
1440	IoApicReg.pfnSendMsi = ioapicSendMsi;
1441	IoApicReg.pfnSetEoi = ioapicSetEoi;
1442	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1443	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1444	AssertRCReturn(rc, rc);
1445
1446	/*
1447	* Register MMIO region.
1448	*/
1449	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1450	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1451	AssertRCReturn(rc, rc);
1452
1453	/*
1454	* Register the saved state.
1455	*/
1456	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1457	AssertRCReturn(rc, rc);
1458
1459	/*
1460	* Register debugger info item.
1461	*/
1462	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1463	AssertRCReturn(rc, rc);
1464
1465	/*
1466	* Register debugger register access.
1467	*/
1468	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1469	AssertRCReturn(rc, rc);
1470
1471	# ifdef VBOX_WITH_STATISTICS
1472	/*
1473	* Statistics.
1474	*/
1475	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1476	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1477	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1478	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1479
1480	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1481	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1482	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1483	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1484
1485	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1486	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1487	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1488	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "IommuDiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded due to IOMMU.");
1489	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "IommuDiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded due to IOMMU.");
1490
1491	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1492	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1493
1494	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1495	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1496	# endif
1497	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1498	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1499	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1500
1501	/*
1502	* Init. the device state.
1503	*/
1504	LogRel(("IOAPIC: Using implementation 2.0! I/O APIC version is %d.%d\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0F));
1505	ioapicR3Reset(pDevIns);
1506
1507	return VINF_SUCCESS;
1508	}
1509
1510	#else /* !IN_RING3 */
1511
1512	/**
1513	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1514	*/
1515	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1516	{
1517	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1518	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1519	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1520
1521	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1522	AssertRCReturn(rc, rc);
1523
1524	PDMIOAPICREG IoApicReg;
1525	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1526	IoApicReg.pfnSetIrq = ioapicSetIrq;
1527	IoApicReg.pfnSendMsi = ioapicSendMsi;
1528	IoApicReg.pfnSetEoi = ioapicSetEoi;
1529	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1530	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1531	AssertRCReturn(rc, rc);
1532
1533	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1534	AssertRCReturn(rc, rc);
1535
1536	return VINF_SUCCESS;
1537	}
1538
1539	#endif /* !IN_RING3 */
1540
1541	/**
1542	* IO APIC device registration structure.
1543	*/
1544	const PDMDEVREG g_DeviceIOAPIC =
1545	{
1546	/* .u32Version = */ PDM_DEVREG_VERSION,
1547	/* .uReserved0 = */ 0,
1548	/* .szName = */ "ioapic",
1549	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1550	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1551	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1552	/* .cMaxInstances = */ 1,
1553	/* .uSharedVersion = */ 42,
1554	/* .cbInstanceShared = */ sizeof(IOAPIC),
1555	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1556	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1557	/* .cMaxPciDevices = */ 0,
1558	/* .cMaxMsixVectors = */ 0,
1559	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1560	#if defined(IN_RING3)
1561	/* .pszRCMod = */ "VBoxDDRC.rc",
1562	/* .pszR0Mod = */ "VBoxDDR0.r0",
1563	/* .pfnConstruct = */ ioapicR3Construct,
1564	/* .pfnDestruct = */ ioapicR3Destruct,
1565	/* .pfnRelocate = */ ioapicR3Relocate,
1566	/* .pfnMemSetup = */ NULL,
1567	/* .pfnPowerOn = */ NULL,
1568	/* .pfnReset = */ ioapicR3Reset,
1569	/* .pfnSuspend = */ NULL,
1570	/* .pfnResume = */ NULL,
1571	/* .pfnAttach = */ NULL,
1572	/* .pfnDetach = */ NULL,
1573	/* .pfnQueryInterface = */ NULL,
1574	/* .pfnInitComplete = */ NULL,
1575	/* .pfnPowerOff = */ NULL,
1576	/* .pfnSoftReset = */ NULL,
1577	/* .pfnReserved0 = */ NULL,
1578	/* .pfnReserved1 = */ NULL,
1579	/* .pfnReserved2 = */ NULL,
1580	/* .pfnReserved3 = */ NULL,
1581	/* .pfnReserved4 = */ NULL,
1582	/* .pfnReserved5 = */ NULL,
1583	/* .pfnReserved6 = */ NULL,
1584	/* .pfnReserved7 = */ NULL,
1585	#elif defined(IN_RING0)
1586	/* .pfnEarlyConstruct = */ NULL,
1587	/* .pfnConstruct = */ ioapicRZConstruct,
1588	/* .pfnDestruct = */ NULL,
1589	/* .pfnFinalDestruct = */ NULL,
1590	/* .pfnRequest = */ NULL,
1591	/* .pfnReserved0 = */ NULL,
1592	/* .pfnReserved1 = */ NULL,
1593	/* .pfnReserved2 = */ NULL,
1594	/* .pfnReserved3 = */ NULL,
1595	/* .pfnReserved4 = */ NULL,
1596	/* .pfnReserved5 = */ NULL,
1597	/* .pfnReserved6 = */ NULL,
1598	/* .pfnReserved7 = */ NULL,
1599	#elif defined(IN_RC)
1600	/* .pfnConstruct = */ ioapicRZConstruct,
1601	/* .pfnReserved0 = */ NULL,
1602	/* .pfnReserved1 = */ NULL,
1603	/* .pfnReserved2 = */ NULL,
1604	/* .pfnReserved3 = */ NULL,
1605	/* .pfnReserved4 = */ NULL,
1606	/* .pfnReserved5 = */ NULL,
1607	/* .pfnReserved6 = */ NULL,
1608	/* .pfnReserved7 = */ NULL,
1609	#else
1610	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1611	#endif
1612	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1613	};
1614
1615
1616	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1617

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 86865

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