DevIoApic.cpp@ 86901

Last change on this file since 86901 was 86901, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 Devices/PC/DevIoApic: Add stats for remapped interrupts and MSIs. Fix registering of 'aStatsVectors'.
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1	/* $Id: DevIoApic.cpp 86901 2020-11-17 12:28:45Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/pci.h>
27	#include <VBox/vmm/pdmdev.h>
28
29	#include "VBoxDD.h"
30	#include <iprt/x86.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** The current IO APIC saved state version. */
38	#define IOAPIC_SAVED_STATE_VERSION 2
39	/** The saved state version used by VirtualBox 5.0 and
40	* earlier. */
41	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
42
43	/** Implementation specified by the "Intel I/O Controller Hub 9
44	* (ICH9) Family" */
45	#define IOAPIC_VERSION_ICH9 0x20
46	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
47	Controller" */
48	#define IOAPIC_VERSION_82093AA 0x11
49
50	/** The default MMIO base physical address. */
51	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
52	/** The size of the MMIO range. */
53	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
54	/** The mask for getting direct registers from physical address. */
55	#define IOAPIC_MMIO_REG_MASK 0xff
56
57	/** The number of interrupt input pins. */
58	#define IOAPIC_NUM_INTR_PINS 24
59	/** Maximum redirection entires. */
60	#define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
61	/** Reduced RTEs used by SIO.A (82379AB). */
62	#define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
63
64	/** Version register - Gets the version. */
65	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
66	/** Version register - Gets the maximum redirection entry. */
67	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
68	/** Version register - Gets whether Pin Assertion Register (PRQ) is
69	* supported. */
70	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
71
72	/** Index register - Valid write mask. */
73	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
74
75	/** Arbitration register - Gets the ID. */
76	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
77
78	/** ID register - Gets the ID. */
79	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
80
81	/** Redirection table entry - Vector. */
82	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
83	/** Redirection table entry - Delivery mode. */
84	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
85	/** Redirection table entry - Destination mode. */
86	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
87	/** Redirection table entry - Delivery status. */
88	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
89	/** Redirection table entry - Interrupt input pin polarity. */
90	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
91	/** Redirection table entry - Remote IRR. */
92	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
93	/** Redirection table entry - Trigger Mode. */
94	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
95	/** Redirection table entry - the mask bit number. */
96	#define IOAPIC_RTE_MASK_BIT 16
97	/** Redirection table entry - the mask. */
98	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
99	/** Redirection table entry - Extended Destination ID. */
100	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
101	/** Redirection table entry - Destination. */
102	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
103
104	/** Redirection table entry - Gets the destination. */
105	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
106	/** Redirection table entry - Gets the mask flag. */
107	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
108	/** Redirection table entry - Checks whether it's masked. */
109	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
110	/** Redirection table entry - Gets the trigger mode. */
111	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
112	/** Redirection table entry - Gets the remote IRR flag. */
113	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
114	/** Redirection table entry - Gets the interrupt pin polarity. */
115	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
116	/** Redirection table entry - Gets the delivery status. */
117	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
118	/** Redirection table entry - Gets the destination mode. */
119	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
120	/** Redirection table entry - Gets the delivery mode. */
121	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
122	/** Redirection table entry - Gets the vector. */
123	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
124
125	/** Redirection table entry - Valid write mask for 82093AA. */
126	#define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
127	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
128	\| IOAPIC_RTE_VECTOR)
129	/** Redirection table entry - Valid read mask for 82093AA. */
130	#define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
131	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
132	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
133
134	/** Redirection table entry - Valid write mask for ICH9. */
135	/** @note The remote IRR bit has been reverted to read-only as it turns out the
136	* ICH9 spec. is wrong, see @bugref{8386#c46}. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
139	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
140	/** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
141	#define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
142	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
143	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
144	\| IOAPIC_RTE_VECTOR)
145
146	/** Redirection table entry - Trigger mode edge. */
147	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
148	/** Redirection table entry - Trigger mode level. */
149	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
150	/** Redirection table entry - Destination mode physical. */
151	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
152	/** Redirection table entry - Destination mode logical. */
153	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
154
155
156	/** Index of indirect registers in the I/O APIC register table. */
157	#define IOAPIC_INDIRECT_INDEX_ID 0x0
158	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
159	#define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
160	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
161	#define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
162	#define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
163
164	/** Offset of direct registers in the I/O APIC MMIO space. */
165	#define IOAPIC_DIRECT_OFF_INDEX 0x00
166	#define IOAPIC_DIRECT_OFF_DATA 0x10
167	#define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
168
169	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
170	#define IOAPIC_WITH_PDM_CRITSECT
171	#ifdef IOAPIC_WITH_PDM_CRITSECT
172	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
173	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
174	#else
175	# define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
176	# define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Structures and Typedefs *
182	*********************************************************************************************************************************/
183	/**
184	* The shared I/O APIC device state.
185	*/
186	typedef struct IOAPIC
187	{
188	/** The ID register. */
189	uint8_t volatile u8Id;
190	/** The index register. */
191	uint8_t volatile u8Index;
192	/** Number of CPUs. */
193	uint8_t cCpus;
194	/** I/O APIC version. */
195	uint8_t u8ApicVer;
196	/** I/O APIC ID mask. */
197	uint8_t u8IdMask;
198	/** Maximum Redirection Table Entry (RTE) Entry. */
199	uint8_t u8MaxRte;
200	/** Last valid RTE indirect register index. */
201	uint8_t u8LastRteRegIdx;
202	/* Alignment padding. */
203	uint8_t u8Padding0[1];
204	/** Redirection table entry - Valid write mask. */
205	uint64_t u64RteWriteMask;
206	/** Redirection table entry - Valid read mask. */
207	uint64_t u64RteReadMask;
208
209	/** The redirection table registers. */
210	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
211	/** The IRQ tags and source IDs for each pin (tracing purposes). */
212	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
213
214	/** The internal IRR reflecting state of the interrupt lines. */
215	uint32_t uIrr;
216	/** Alignment padding. */
217	uint32_t u32Padding2;
218
219	#ifndef IOAPIC_WITH_PDM_CRITSECT
220	/** The critsect for updating to the RTEs. */
221	PDMCRITSECT CritSect;
222	#endif
223
224	/** The MMIO region. */
225	IOMMMIOHANDLE hMmio;
226
227	#ifdef VBOX_WITH_STATISTICS
228	/** Number of MMIO reads in RZ. */
229	STAMCOUNTER StatMmioReadRZ;
230	/** Number of MMIO reads in R3. */
231	STAMCOUNTER StatMmioReadR3;
232
233	/** Number of MMIO writes in RZ. */
234	STAMCOUNTER StatMmioWriteRZ;
235	/** Number of MMIO writes in R3. */
236	STAMCOUNTER StatMmioWriteR3;
237
238	/** Number of SetIrq calls in RZ. */
239	STAMCOUNTER StatSetIrqRZ;
240	/** Number of SetIrq calls in R3. */
241	STAMCOUNTER StatSetIrqR3;
242
243	/** Number of SetEoi calls in RZ. */
244	STAMCOUNTER StatSetEoiRZ;
245	/** Number of SetEoi calls in R3. */
246	STAMCOUNTER StatSetEoiR3;
247
248	/** Number of redundant edge-triggered interrupts. */
249	STAMCOUNTER StatRedundantEdgeIntr;
250	/** Number of redundant level-triggered interrupts. */
251	STAMCOUNTER StatRedundantLevelIntr;
252	/** Number of suppressed level-triggered interrupts (by remote IRR). */
253	STAMCOUNTER StatSuppressedLevelIntr;
254	/** Number of IOMMU remapped interrupts (signaled by RTE). */
255	STAMCOUNTER StatIommuRemappedIntr;
256	/** Number of IOMMU discarded interrupts (signaled by RTE). */
257	STAMCOUNTER StatIommuDiscardedIntr;
258	/** Number of IOMMU remapped MSIs. */
259	STAMCOUNTER StatIommuRemappedMsi;
260	/** Number of IOMMU denied or failed MSIs. */
261	STAMCOUNTER StatIommuDiscardedMsi;
262	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
263	STAMCOUNTER StatEoiContention;
264	/** Number of returns to ring-3 due to Set RTE lock contention. */
265	STAMCOUNTER StatSetRteContention;
266	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
267	STAMCOUNTER StatLevelIrqSent;
268	/** Number of EOIs received for level-triggered interrupts from the local
269	* APIC(s). */
270	STAMCOUNTER StatEoiReceived;
271	#endif
272	/** Per-vector stats. */
273	STAMCOUNTER aStatVectors[256];
274	} IOAPIC;
275	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
276	/** Pointer to shared IOAPIC data. */
277	typedef IOAPIC *PIOAPIC;
278	/** Pointer to const shared IOAPIC data. */
279	typedef IOAPIC const *PCIOAPIC;
280
281
282	/**
283	* The I/O APIC device state for ring-3.
284	*/
285	typedef struct IOAPICR3
286	{
287	/** The IOAPIC helpers. */
288	R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
289	} IOAPICR3;
290	/** Pointer to the I/O APIC device state for ring-3. */
291	typedef IOAPICR3 *PIOAPICR3;
292
293
294	/**
295	* The I/O APIC device state for ring-0.
296	*/
297	typedef struct IOAPICR0
298	{
299	/** The IOAPIC helpers. */
300	R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
301	} IOAPICR0;
302	/** Pointer to the I/O APIC device state for ring-0. */
303	typedef IOAPICR0 *PIOAPICR0;
304
305
306	/**
307	* The I/O APIC device state for raw-mode.
308	*/
309	typedef struct IOAPICRC
310	{
311	/** The IOAPIC helpers. */
312	RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
313	} IOAPICRC;
314	/** Pointer to the I/O APIC device state for raw-mode. */
315	typedef IOAPICRC *PIOAPICRC;
316
317
318	/** The I/O APIC device state for the current context. */
319	typedef CTX_SUFF(IOAPIC) IOAPICCC;
320	/** Pointer to the I/O APIC device state for the current context. */
321	typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
322
323
324	/**
325	* xAPIC interrupt.
326	*/
327	typedef struct XAPICINTR
328	{
329	/** The interrupt vector. */
330	uint8_t u8Vector;
331	/** The destination (mask or ID). */
332	uint8_t u8Dest;
333	/** The destination mode. */
334	uint8_t u8DestMode;
335	/** Delivery mode. */
336	uint8_t u8DeliveryMode;
337	/** Trigger mode. */
338	uint8_t u8TriggerMode;
339	/** Redirection hint. */
340	uint8_t u8RedirHint;
341	/** Polarity. */
342	uint8_t u8Polarity;
343	/** Padding. */
344	uint8_t abPadding0;
345	} XAPICINTR;
346	/** Pointer to an I/O xAPIC interrupt struct. */
347	typedef XAPICINTR *PXAPICINTR;
348	/** Pointer to a const xAPIC interrupt struct. */
349	typedef XAPICINTR const *PCXAPICINTR;
350
351
352	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
353
354	/**
355	* Gets the arbitration register.
356	*
357	* @returns The arbitration.
358	*/
359	DECLINLINE(uint32_t) ioapicGetArb(void)
360	{
361	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
362	return 0;
363	}
364
365
366	/**
367	* Gets the version register.
368	*
369	* @returns The version.
370	*/
371	DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
372	{
373	uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
374	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
375	return uValue;
376	}
377
378
379	/**
380	* Sets the ID register.
381	*
382	* @param pThis The shared I/O APIC device state.
383	* @param uValue The value to set.
384	*/
385	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
386	{
387	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
388	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
389	}
390
391
392	/**
393	* Gets the ID register.
394	*
395	* @returns The ID.
396	* @param pThis The shared I/O APIC device state.
397	*/
398	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
399	{
400	uint32_t uValue = (uint32_t)pThis->u8Id << 24;
401	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
402	return uValue;
403	}
404
405
406	/**
407	* Sets the index register.
408	*
409	* @param pThis The shared I/O APIC device state.
410	* @param uValue The value to set.
411	*/
412	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
413	{
414	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
415	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
416	}
417
418
419	/**
420	* Gets the index register.
421	*
422	* @returns The index value.
423	*/
424	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
425	{
426	uint32_t const uValue = pThis->u8Index;
427	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
428	return uValue;
429	}
430
431
432	/**
433	* Converts an MSI message to an APIC interrupt.
434	*
435	* @param pMsi The MSI message to convert.
436	* @param pIntr Where to store the APIC interrupt.
437	*/
438	DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
439	{
440	/*
441	* Parse the message from the physical address and data
442	* See Intel spec. 10.11.1 "Message Address Register Format".
443	* See Intel spec. 10.11.2 "Message Data Register Format".
444	*/
445	pIntr->u8Dest = pMsi->Addr.n.u8DestId;
446	pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
447	pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
448
449	pIntr->u8Vector = pMsi->Data.n.u8Vector;
450	pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
451	pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
452	}
453
454
455	#ifdef VBOX_WITH_IOMMU_AMD
456	/**
457	* Convert an APIC interrupt to an MSI message.
458	*
459	* @param pIntr The APIC interrupt to convert.
460	* @param pMsi Where to store the MSI message.
461	*/
462	DECLINLINE(void) ioapicGetMsiFromApicIntr(PCXAPICINTR pIntr, PMSIMSG pMsi)
463	{
464	pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
465	pMsi->Addr.n.u8DestId = pIntr->u8Dest;
466	pMsi->Addr.n.u1RedirHint = pIntr->u8RedirHint;
467	pMsi->Addr.n.u1DestMode = pIntr->u8DestMode;
468
469	pMsi->Data.n.u8Vector = pIntr->u8Vector;
470	pMsi->Data.n.u3DeliveryMode = pIntr->u8DeliveryMode;
471	pMsi->Data.n.u1TriggerMode = pIntr->u8TriggerMode;
472
473	/* pMsi->Data.n.u1Level = ??? */
474	/** @todo r=ramshankar: Level triggered MSIs don't make much sense though
475	* possible in theory? Maybe document this more explicitly... */
476	}
477	#endif
478
479
480	/**
481	* Signals the next pending interrupt for the specified Redirection Table Entry
482	* (RTE).
483	*
484	* @param pDevIns The device instance.
485	* @param pThis The shared I/O APIC device state.
486	* @param pThisCC The I/O APIC device state for the current context.
487	* @param uBusDevFn The bus:device:function of the device initiating the IRQ.
488	* @param idxRte The index of the RTE (validated).
489	*
490	* @remarks It is the responsibility of the caller to verify that an interrupt is
491	* pending for the pin corresponding to the RTE before calling this
492	* function.
493	*/
494	static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, PCIBDF uBusDevFn, uint8_t idxRte)
495	{
496	#ifndef IOAPIC_WITH_PDM_CRITSECT
497	Assert(PDMCritSectIsOwner(&pThis->CritSect));
498	#endif
499
500	/*
501	* Ensure the interrupt isn't masked.
502	*/
503	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
504	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
505	{
506	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
507	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
508	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
509	{
510	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
511	if (u8RemoteIrr)
512	{
513	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
514	return;
515	}
516	}
517
518	XAPICINTR ApicIntr;
519	RT_ZERO(ApicIntr);
520	ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
521	ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
522	ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
523	ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
524	ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
525	ApicIntr.u8TriggerMode = u8TriggerMode;
526	ApicIntr.u8RedirHint = 0;
527
528	#ifdef VBOX_WITH_IOMMU_AMD
529	/*
530	* The interrupt may need to be remapped (or discarded) if an IOMMU is present.
531	*/
532	MSIMSG MsiOut;
533	MSIMSG MsiIn;
534	RT_ZERO(MsiOut);
535	RT_ZERO(MsiIn);
536	ioapicGetMsiFromApicIntr(&ApicIntr, &MsiIn);
537	if (!PCIBDF_IS_VALID(uBusDevFn))
538	uBusDevFn = VBOX_PCI_BDF_SB_IOAPIC;
539	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, &MsiIn, &MsiOut);
540	LogFlow(("IOAPIC: IOMMU Remap. rc=%Rrc VectorIn=%#x VectorOut=%#x\n", rcRemap, MsiIn.Data.n.u8Vector, MsiOut.Data.n.u8Vector));
541	if (RT_SUCCESS(rcRemap))
542	{
543	STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
544	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
545	Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte)); /* Ensure polarity hasn't changed. */
546	Assert(ApicIntr.u8TriggerMode == u8TriggerMode); /* Ensure trigger mode hasn't changed. */
547	}
548	else
549	{
550	STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
551	Log(("IOAPIC: Interrupt (%#x) discarded (rc=%Rrc)\n", ApicIntr.u8Vector, rcRemap));
552	return;
553	}
554	#else
555	NOREF(uBusDevFn);
556	#endif
557
558	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
559	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
560	ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
561	ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
562	ApicIntr.u8Vector, ApicIntr.u8Vector));
563
564	/*
565	* Deliver to the local APIC via the system/3-wire-APIC bus.
566	*/
567	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
568	ApicIntr.u8Dest,
569	ApicIntr.u8DestMode,
570	ApicIntr.u8DeliveryMode,
571	ApicIntr.u8Vector,
572	ApicIntr.u8Polarity,
573	ApicIntr.u8TriggerMode,
574	u32TagSrc);
575	/* Can't reschedule to R3. */
576	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
577	#ifdef DEBUG_ramshankar
578	if (rc == VERR_APIC_INTR_DISCARDED)
579	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
580	#endif
581
582	/*
583	* For level-triggered interrupts, we set the remote IRR bit to indicate
584	* the local APIC has accepted the interrupt.
585	*
586	* For edge-triggered interrupts, we should not clear the IRR bit as it
587	* should remain intact to reflect the state of the interrupt line.
588	* The device will explicitly transition to inactive state via the
589	* ioapicSetIrq() callback.
590	*/
591	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
592	&& rc == VINF_SUCCESS)
593	{
594	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
595	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
596	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
597	}
598	}
599	}
600
601
602	/**
603	* Gets the redirection table entry.
604	*
605	* @returns The redirection table entry.
606	* @param pThis The shared I/O APIC device state.
607	* @param uIndex The index value.
608	*/
609	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
610	{
611	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
612	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
613	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
614	UINT32_MAX);
615	uint32_t uValue;
616	if (!(uIndex & 1))
617	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
618	else
619	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
620
621	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
622	return uValue;
623	}
624
625
626	/**
627	* Sets the redirection table entry.
628	*
629	* @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
630	* @param pDevIns The device instance.
631	* @param pThis The shared I/O APIC device state.
632	* @param pThisCC The I/O APIC device state for the current context.
633	* @param uIndex The index value.
634	* @param uValue The value to set.
635	*/
636	static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
637	uint32_t uIndex, uint32_t uValue)
638	{
639	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
640	AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
641	("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
642	VINF_SUCCESS);
643
644	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
645	if (rc == VINF_SUCCESS)
646	{
647	/*
648	* Write the low or high 32-bit value into the specified 64-bit RTE register,
649	* update only the valid, writable bits.
650	*
651	* We need to preserve the read-only bits as it can have dire consequences
652	* otherwise, see @bugref{8386#c24}.
653	*/
654	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
655	if (!(uIndex & 1))
656	{
657	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
658	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) \| u32RtePreserveLo;
659	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
660	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
661	}
662	else
663	{
664	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
665	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
666	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) \| u32RtePreserveHi) << 32);
667	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
668	}
669
670	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
671
672	/*
673	* Signal the next pending interrupt for this RTE.
674	*/
675	uint32_t const uPinMask = UINT32_C(1) << idxRte;
676	if (pThis->uIrr & uPinMask)
677	{
678	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
679	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
680	}
681
682	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
683	}
684	else
685	STAM_COUNTER_INC(&pThis->StatSetRteContention);
686
687	return rc;
688	}
689
690
691	/**
692	* Gets the data register.
693	*
694	* @returns The data value.
695	* @param pThis The shared I/O APIC device state.
696	*/
697	static uint32_t ioapicGetData(PCIOAPIC pThis)
698	{
699	uint8_t const uIndex = pThis->u8Index;
700	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
701	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
702	&& uIndex <= pThis->u8LastRteRegIdx)
703	return ioapicGetRedirTableEntry(pThis, uIndex);
704
705	uint32_t uValue;
706	switch (uIndex)
707	{
708	case IOAPIC_INDIRECT_INDEX_ID:
709	uValue = ioapicGetId(pThis);
710	break;
711
712	case IOAPIC_INDIRECT_INDEX_VERSION:
713	uValue = ioapicGetVersion(pThis);
714	break;
715
716	case IOAPIC_INDIRECT_INDEX_ARB:
717	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
718	{
719	uValue = ioapicGetArb();
720	break;
721	}
722	RT_FALL_THRU();
723
724	default:
725	uValue = UINT32_C(0xffffffff);
726	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
727	break;
728	}
729	return uValue;
730	}
731
732
733	/**
734	* Sets the data register.
735	*
736	* @returns Strict VBox status code.
737	* @param pDevIns The device instance.
738	* @param pThis The shared I/O APIC device state.
739	* @param pThisCC The I/O APIC device state for the current context.
740	* @param uValue The value to set.
741	*/
742	static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
743	{
744	uint8_t const uIndex = pThis->u8Index;
745	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
746	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
747
748	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
749	&& uIndex <= pThis->u8LastRteRegIdx)
750	return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
751
752	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
753	ioapicSetId(pThis, uValue);
754	else
755	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
756
757	return VINF_SUCCESS;
758	}
759
760
761	/**
762	* @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
763	*/
764	static DECLCALLBACK(VBOXSTRICTRC) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
765	{
766	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
767	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
768	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
769	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
770
771	bool fRemoteIrrCleared = false;
772	VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
773	if (rc == VINF_SUCCESS)
774	{
775	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
776	{
777	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
778	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
779	{
780	#ifdef DEBUG_ramshankar
781	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
782	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
783	#endif
784	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
785	fRemoteIrrCleared = true;
786	STAM_COUNTER_INC(&pThis->StatEoiReceived);
787	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
788
789	/*
790	* Signal the next pending interrupt for this RTE.
791	*/
792	uint32_t const uPinMask = UINT32_C(1) << idxRte;
793	if (pThis->uIrr & uPinMask)
794	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, VBOX_PCI_BDF_SB_IOAPIC, idxRte);
795	}
796	}
797
798	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
799	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
800	}
801	else
802	STAM_COUNTER_INC(&pThis->StatEoiContention);
803
804	return rc;
805	}
806
807
808	/**
809	* @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
810	*/
811	static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
812	{
813	#define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask) do { \
814	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
815	pThis->uIrr \|= a_PinMask; \
816	ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_uBusDevFn), (a_idxRte)); \
817	} while (0)
818
819	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
820	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
821	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
822
823	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
824
825	if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
826	{
827	int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
828	AssertRC(rc);
829
830	uint8_t const idxRte = iIrq;
831	uint32_t const uPinMask = UINT32_C(1) << idxRte;
832	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
833	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
834
835	bool fActive = RT_BOOL(iLevel & 1);
836	/** @todo Polarity is busted elsewhere, we need to fix that
837	* first. See @bugref{8386#c7}. */
838	#if 0
839	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
840	fActive ^= u8Polarity; */
841	#endif
842	if (!fActive)
843	{
844	pThis->uIrr &= ~uPinMask;
845	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
846	return;
847	}
848
849	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
850	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
851	if (!fFlipFlop)
852	{
853	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
854	{
855	/*
856	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
857	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
858	*/
859	if (!uPrevIrr)
860	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
861	else
862	{
863	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
864	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
865	}
866	}
867	else
868	{
869	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
870
871	/*
872	* For level-triggered interrupts, redundant interrupts are not a problem
873	* and will eventually be delivered anyway after an EOI, but our PDM devices
874	* should not typically call us with no change to the level.
875	*/
876	if (!uPrevIrr)
877	{ /* likely */ }
878	else
879	{
880	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
881	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
882	}
883
884	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
885	}
886	}
887	else
888	{
889	/*
890	* The device is flip-flopping the interrupt line, which implies we should de-assert
891	* and assert the interrupt line. The interrupt line is left in the asserted state
892	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
893	* hence just the assert is done.
894	*/
895	IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask);
896	}
897
898	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
899	}
900	#undef IOAPIC_ASSERT_IRQ
901	}
902
903
904	/**
905	* @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
906	*/
907	static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
908	{
909	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
910	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
911	LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32\n", uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32));
912
913	XAPICINTR ApicIntr;
914	RT_ZERO(ApicIntr);
915
916	#ifdef VBOX_WITH_IOMMU_AMD
917	/*
918	* The MSI may need to be remapped (or discarded) if an IOMMU is present.
919	*/
920	MSIMSG MsiOut;
921	RT_ZERO(MsiOut);
922	Assert(PCIBDF_IS_VALID(uBusDevFn));
923	int rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
924	if (RT_SUCCESS(rcRemap))
925	{
926	STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
927	ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
928	}
929	else
930	{
931	STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
932	if (rcRemap == VERR_IOMMU_INTR_REMAP_DENIED)
933	Log3(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping denied. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
934	else
935	Log(("IOAPIC: MSI (Addr=%#RX64 Data=%#RX32) remapping failed. rc=%Rrc", pMsi->Addr.u64, pMsi->Data.u32, rcRemap));
936	return;
937	}
938	#else
939	NOREF(uBusDevFn);
940	ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
941	#endif
942
943	/*
944	* Deliver to the local APIC via the system/3-wire-APIC bus.
945	*/
946	STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
947
948	int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
949	ApicIntr.u8Dest,
950	ApicIntr.u8DestMode,
951	ApicIntr.u8DeliveryMode,
952	ApicIntr.u8Vector,
953	0 /* u8Polarity - N/A */,
954	ApicIntr.u8TriggerMode,
955	uTagSrc);
956	/* Can't reschedule to R3. */
957	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
958	}
959
960
961	/**
962	* @callback_method_impl{FNIOMMMIONEWREAD}
963	*/
964	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
965	{
966	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
967	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
968	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
969	RT_NOREF_PV(pvUser);
970
971	VBOXSTRICTRC rc = VINF_SUCCESS;
972	uint32_t puValue = (uint32_t )pv;
973	uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
974	switch (offReg)
975	{
976	case IOAPIC_DIRECT_OFF_INDEX:
977	*puValue = ioapicGetIndex(pThis);
978	break;
979
980	case IOAPIC_DIRECT_OFF_DATA:
981	*puValue = ioapicGetData(pThis);
982	break;
983
984	default:
985	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
986	rc = VINF_IOM_MMIO_UNUSED_FF;
987	break;
988	}
989
990	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
991	return rc;
992	}
993
994
995	/**
996	* @callback_method_impl{FNIOMMMIONEWWRITE}
997	*/
998	static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
999	{
1000	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1001	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1002	RT_NOREF_PV(pvUser);
1003
1004	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1005
1006	Assert(!(off & 3));
1007	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
1008
1009	VBOXSTRICTRC rc = VINF_SUCCESS;
1010	uint32_t const uValue = (uint32_t const )pv;
1011	uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
1012
1013	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
1014	switch (offReg)
1015	{
1016	case IOAPIC_DIRECT_OFF_INDEX:
1017	ioapicSetIndex(pThis, uValue);
1018	break;
1019
1020	case IOAPIC_DIRECT_OFF_DATA:
1021	rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
1022	break;
1023
1024	case IOAPIC_DIRECT_OFF_EOI:
1025	if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
1026	rc = ioapicSetEoi(pDevIns, uValue);
1027	else
1028	Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
1029	break;
1030
1031	default:
1032	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
1033	break;
1034	}
1035
1036	return rc;
1037	}
1038
1039
1040	#ifdef IN_RING3
1041
1042	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1043	static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1044	{
1045	RT_NOREF(pDesc);
1046	pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
1047	return VINF_SUCCESS;
1048	}
1049
1050
1051	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1052	static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1053	{
1054	RT_NOREF(pDesc, pfMask);
1055	ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
1056	return VINF_SUCCESS;
1057	}
1058
1059
1060	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1061	static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1062	{
1063	RT_NOREF(pDesc);
1064	pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
1065	return VINF_SUCCESS;
1066	}
1067
1068
1069	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1070	static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1071	{
1072	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1073	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1074	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1075	RT_NOREF(pDesc, pfMask);
1076	return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
1077	}
1078
1079
1080	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1081	static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1082	{
1083	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1084	RT_NOREF(pDesc);
1085	pValue->u32 = ioapicGetVersion(pThis);
1086	return VINF_SUCCESS;
1087	}
1088
1089
1090	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1091	static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1092	{
1093	RT_NOREF(pvUser, pDesc);
1094	pValue->u32 = ioapicGetArb();
1095	return VINF_SUCCESS;
1096	}
1097
1098
1099	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
1100	static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
1101	{
1102	PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
1103	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1104	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
1105	return VINF_SUCCESS;
1106	}
1107
1108
1109	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
1110	static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
1111	{
1112	RT_NOREF(pfMask);
1113	PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
1114	/* No locks, no checks, just do it. */
1115	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
1116	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
1117	return VINF_SUCCESS;
1118	}
1119
1120
1121	/** IOREDTBLn sub fields. */
1122	static DBGFREGSUBFIELD const g_aRteSubs[] =
1123	{
1124	{ "vector", 0, 8, 0, 0, NULL, NULL },
1125	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
1126	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
1127	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1128	{ "polarity", 13, 1, 0, 0, NULL, NULL },
1129	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1130	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
1131	{ "mask", 16, 1, 0, 0, NULL, NULL },
1132	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
1133	{ "dest", 56, 8, 0, 0, NULL, NULL },
1134	DBGFREGSUBFIELD_TERMINATOR()
1135	};
1136
1137
1138	/** Register descriptors for DBGF. */
1139	static DBGFREGDESC const g_aRegDesc[] =
1140	{
1141	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
1142	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
1143	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
1144	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
1145	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1146	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1147	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1148	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1149	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1150	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1151	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1152	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1153	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1154	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1155	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1156	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1157	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1158	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1159	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1160	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1161	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1162	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1163	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1164	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1165	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1166	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1167	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1168	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
1169	DBGFREGDESC_TERMINATOR()
1170	};
1171
1172
1173	/**
1174	* @callback_method_impl{FNDBGFHANDLERDEV}
1175	*/
1176	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1177	{
1178	RT_NOREF(pszArgs);
1179	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1180	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
1181
1182	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
1183
1184	uint32_t const uId = ioapicGetId(pThis);
1185	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
1186	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
1187
1188	uint32_t const uVer = ioapicGetVersion(pThis);
1189	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1190	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1191	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1192	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1193
1194	if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
1195	{
1196	uint32_t const uArb = ioapicGetArb();
1197	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1198	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1199	}
1200
1201	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1202
1203	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1204	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1205
1206	uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
1207	for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
1208	{
1209	static const char * const s_apszDeliveryModes[] =
1210	{
1211	"Fixed ",
1212	"LowPri",
1213	"SMI ",
1214	"Rsvd ",
1215	"NMI ",
1216	"INIT ",
1217	"Rsvd ",
1218	"ExtINT"
1219	};
1220
1221	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1222	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1223	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1224	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1225	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1226	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1227	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1228	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1229	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1230	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1231	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1232	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1233
1234	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1235	idxRte,
1236	pszDestMode,
1237	uDest,
1238	uMask,
1239	(pThis->uIrr >> idxRte) & 1,
1240	pszTriggerMode,
1241	uRemoteIrr,
1242	pszPolarity,
1243	pszDeliveryStatus,
1244	pszDeliveryMode,
1245	uVector,
1246	u64Rte);
1247	}
1248	}
1249
1250
1251	/**
1252	* @copydoc FNSSMDEVSAVEEXEC
1253	*/
1254	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1255	{
1256	PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
1257	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1258	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1259
1260	pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
1261	pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
1262	pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
1263	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1264	pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
1265
1266	return VINF_SUCCESS;
1267	}
1268
1269
1270	/**
1271	* @copydoc FNSSMDEVLOADEXEC
1272	*/
1273	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1274	{
1275	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1276	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1277	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1278
1279	Assert(uPass == SSM_PASS_FINAL);
1280	NOREF(uPass);
1281
1282	/* Weed out invalid versions. */
1283	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1284	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1285	{
1286	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1287	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1288	}
1289
1290	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1291	pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
1292
1293	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
1294	pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
1295	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1296	pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1297
1298	return VINF_SUCCESS;
1299	}
1300
1301
1302	/**
1303	* @interface_method_impl{PDMDEVREG,pfnReset}
1304	*/
1305	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1306	{
1307	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1308	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1309	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1310
1311	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1312	IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
1313
1314	pThis->uIrr = 0;
1315	pThis->u8Index = 0;
1316	pThis->u8Id = 0;
1317
1318	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1319	{
1320	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1321	pThis->au32TagSrc[idxRte] = 0;
1322	}
1323
1324	IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
1325	}
1326
1327
1328	/**
1329	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1330	*/
1331	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1332	{
1333	PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
1334	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
1335
1336	pThisRC->pIoApicHlp += offDelta;
1337	}
1338
1339
1340	/**
1341	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1342	*/
1343	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1344	{
1345	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1346	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1347	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1348
1349	# ifndef IOAPIC_WITH_PDM_CRITSECT
1350	/*
1351	* Destroy the RTE critical section.
1352	*/
1353	if (PDMCritSectIsInitialized(&pThis->CritSect))
1354	PDMR3CritSectDelete(&pThis->CritSect);
1355	# else
1356	RT_NOREF_PV(pThis);
1357	# endif
1358
1359	return VINF_SUCCESS;
1360	}
1361
1362
1363	/**
1364	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1365	*/
1366	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1367	{
1368	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1369	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1370	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1371	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1372	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1373	Assert(iInstance == 0); RT_NOREF(iInstance);
1374
1375	/*
1376	* Validate and read the configuration.
1377	*/
1378	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|ChipType", "");
1379
1380	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1381	upsets some guest which we haven't yet tested. */
1382	uint32_t cCpus;
1383	int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1384	if (RT_FAILURE(rc))
1385	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1386	pThis->cCpus = (uint8_t)cCpus;
1387
1388	char szChipType[16];
1389	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
1390	if (RT_FAILURE(rc))
1391	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
1392
1393	if (!strcmp(szChipType, "ICH9"))
1394	{
1395	/* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
1396	pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
1397	pThis->u8IdMask = 0xff;
1398	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1399	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1400	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
1401	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
1402	}
1403	else if (!strcmp(szChipType, "82093AA"))
1404	{
1405	/* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
1406	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1407	pThis->u8IdMask = 0x0f;
1408	pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
1409	pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
1410	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1411	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1412	}
1413	else if (!strcmp(szChipType, "82379AB"))
1414	{
1415	/* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
1416	/* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
1417	pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
1418	pThis->u8IdMask = 0x0f;
1419	pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
1420	pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
1421	pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
1422	pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
1423	}
1424	else
1425	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
1426	N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
1427	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled \| pDevIns->fRCEnabled, szChipType));
1428
1429	/*
1430	* We will use our own critical section for the IOAPIC device.
1431	*/
1432	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1433	AssertRCReturn(rc, rc);
1434
1435	# ifndef IOAPIC_WITH_PDM_CRITSECT
1436	/*
1437	* Setup the critical section to protect concurrent writes to the RTEs.
1438	*/
1439	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1440	AssertRCReturn(rc, rc);
1441	# endif
1442
1443	/*
1444	* Register the IOAPIC.
1445	*/
1446	PDMIOAPICREG IoApicReg;
1447	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1448	IoApicReg.pfnSetIrq = ioapicSetIrq;
1449	IoApicReg.pfnSendMsi = ioapicSendMsi;
1450	IoApicReg.pfnSetEoi = ioapicSetEoi;
1451	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1452	rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1453	AssertRCReturn(rc, rc);
1454
1455	/*
1456	* Register MMIO region.
1457	*/
1458	rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
1459	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
1460	AssertRCReturn(rc, rc);
1461
1462	/*
1463	* Register the saved state.
1464	*/
1465	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1466	AssertRCReturn(rc, rc);
1467
1468	/*
1469	* Register debugger info item.
1470	*/
1471	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1472	AssertRCReturn(rc, rc);
1473
1474	/*
1475	* Register debugger register access.
1476	*/
1477	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
1478	AssertRCReturn(rc, rc);
1479
1480	# ifdef VBOX_WITH_STATISTICS
1481	/*
1482	* Statistics.
1483	*/
1484	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1485	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1486	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1487	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1488
1489	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1490	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1491	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1492	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1493
1494	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1495	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1496	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1497
1498	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
1499	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
1500	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
1501	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
1502
1503	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1504	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1505
1506	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1507	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1508	# endif
1509	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
1510	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1511	"Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
1512
1513	/*
1514	* Init. the device state.
1515	*/
1516	LogRel(("IOAPIC: Using implementation 2.0! I/O APIC version is %d.%d\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0F));
1517	ioapicR3Reset(pDevIns);
1518
1519	return VINF_SUCCESS;
1520	}
1521
1522	#else /* !IN_RING3 */
1523
1524	/**
1525	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1526	*/
1527	static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
1528	{
1529	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1530	PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
1531	PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
1532
1533	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1534	AssertRCReturn(rc, rc);
1535
1536	PDMIOAPICREG IoApicReg;
1537	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1538	IoApicReg.pfnSetIrq = ioapicSetIrq;
1539	IoApicReg.pfnSendMsi = ioapicSendMsi;
1540	IoApicReg.pfnSetEoi = ioapicSetEoi;
1541	IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
1542	rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
1543	AssertRCReturn(rc, rc);
1544
1545	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /pvUser/);
1546	AssertRCReturn(rc, rc);
1547
1548	return VINF_SUCCESS;
1549	}
1550
1551	#endif /* !IN_RING3 */
1552
1553	/**
1554	* IO APIC device registration structure.
1555	*/
1556	const PDMDEVREG g_DeviceIOAPIC =
1557	{
1558	/* .u32Version = */ PDM_DEVREG_VERSION,
1559	/* .uReserved0 = */ 0,
1560	/* .szName = */ "ioapic",
1561	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1562	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1563	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1564	/* .cMaxInstances = */ 1,
1565	/* .uSharedVersion = */ 42,
1566	/* .cbInstanceShared = */ sizeof(IOAPIC),
1567	/* .cbInstanceCC = */ sizeof(IOAPICCC),
1568	/* .cbInstanceRC = */ sizeof(IOAPICRC),
1569	/* .cMaxPciDevices = */ 0,
1570	/* .cMaxMsixVectors = */ 0,
1571	/* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1572	#if defined(IN_RING3)
1573	/* .pszRCMod = */ "VBoxDDRC.rc",
1574	/* .pszR0Mod = */ "VBoxDDR0.r0",
1575	/* .pfnConstruct = */ ioapicR3Construct,
1576	/* .pfnDestruct = */ ioapicR3Destruct,
1577	/* .pfnRelocate = */ ioapicR3Relocate,
1578	/* .pfnMemSetup = */ NULL,
1579	/* .pfnPowerOn = */ NULL,
1580	/* .pfnReset = */ ioapicR3Reset,
1581	/* .pfnSuspend = */ NULL,
1582	/* .pfnResume = */ NULL,
1583	/* .pfnAttach = */ NULL,
1584	/* .pfnDetach = */ NULL,
1585	/* .pfnQueryInterface = */ NULL,
1586	/* .pfnInitComplete = */ NULL,
1587	/* .pfnPowerOff = */ NULL,
1588	/* .pfnSoftReset = */ NULL,
1589	/* .pfnReserved0 = */ NULL,
1590	/* .pfnReserved1 = */ NULL,
1591	/* .pfnReserved2 = */ NULL,
1592	/* .pfnReserved3 = */ NULL,
1593	/* .pfnReserved4 = */ NULL,
1594	/* .pfnReserved5 = */ NULL,
1595	/* .pfnReserved6 = */ NULL,
1596	/* .pfnReserved7 = */ NULL,
1597	#elif defined(IN_RING0)
1598	/* .pfnEarlyConstruct = */ NULL,
1599	/* .pfnConstruct = */ ioapicRZConstruct,
1600	/* .pfnDestruct = */ NULL,
1601	/* .pfnFinalDestruct = */ NULL,
1602	/* .pfnRequest = */ NULL,
1603	/* .pfnReserved0 = */ NULL,
1604	/* .pfnReserved1 = */ NULL,
1605	/* .pfnReserved2 = */ NULL,
1606	/* .pfnReserved3 = */ NULL,
1607	/* .pfnReserved4 = */ NULL,
1608	/* .pfnReserved5 = */ NULL,
1609	/* .pfnReserved6 = */ NULL,
1610	/* .pfnReserved7 = */ NULL,
1611	#elif defined(IN_RC)
1612	/* .pfnConstruct = */ ioapicRZConstruct,
1613	/* .pfnReserved0 = */ NULL,
1614	/* .pfnReserved1 = */ NULL,
1615	/* .pfnReserved2 = */ NULL,
1616	/* .pfnReserved3 = */ NULL,
1617	/* .pfnReserved4 = */ NULL,
1618	/* .pfnReserved5 = */ NULL,
1619	/* .pfnReserved6 = */ NULL,
1620	/* .pfnReserved7 = */ NULL,
1621	#else
1622	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1623	#endif
1624	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1625	};
1626
1627
1628	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1629

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 86901

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